/***************************************************************************** * @file: K1921VK028.h * @author NIIET * @version: V2.14 * @date: 26.02.2019 * @brief: K1921VK028 header file ***************************************************************************** *

* * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, NIIET NOT BE HELD LIABLE FOR ANY DIRECT, * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2019 NIIET

***************************************************************************** * FILE K1921VK028.h */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __K1921VK028_H #define __K1921VK028_H #define __I volatile const /*!< defines 'read only' permissions */ #define __O volatile /*!< defines 'write only' permissions */ #define __IO volatile /*!< defines 'read / write' permissions */ /* Start of section using anonymous unions */ #if defined (__CC_ARM) #pragma push #pragma anon_unions #elif defined (__ICCARM__) #pragma language=extended #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wc11-extensions" #pragma clang diagnostic ignored "-Wreserved-id-macro" #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning 586 #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #elif defined (__CMCPPARM__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /* Configuration of the Cortex-M4F Processor and Core Peripherals */ #define __CM4_REV 0x0001 /*!< Cortex-M4F Core Revision r0p1 */ #define __MPU_PRESENT 1 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1 /*!< FPU present or not */ #include "stdint.h" #ifdef __cplusplus extern "C" { #endif /******************************************************************************/ /* Interrupt Number Definition */ /******************************************************************************/ typedef enum IRQn { /*-- Cortex-M4F Processor Exceptions Numbers ---------------------------------*/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 System Tick Timer Interrupt */ /*-- Device specific Interrupt Numbers ---------------------------------------*/ WDT_IRQn = 0, /*!< Watchdog timer interrupt */ RCU_IRQn = 1, /*!< Reset and clock unit interrupt */ RTC_IRQn = 2, /*!< RTC interrupt */ MFLASH_IRQn = 3, /*!< MFLASH interrupt */ BFLASH_IRQn = 4, /*!< BFLASH interrupt */ GPIOA_IRQn = 5, /*!< GPIO A interrupt */ GPIOB_IRQn = 6, /*!< GPIO B interrupt */ GPIOC_IRQn = 7, /*!< GPIO C interrupt */ GPIOD_IRQn = 8, /*!< GPIO D interrupt */ GPIOE_IRQn = 9, /*!< GPIO E interrupt */ GPIOF_IRQn = 10, /*!< GPIO F interrupt */ GPIOG_IRQn = 11, /*!< GPIO G interrupt */ GPIOH_IRQn = 12, /*!< GPIO H interrupt */ GPIOJ_IRQn = 13, /*!< GPIO J interrupt */ GPIOK_IRQn = 14, /*!< GPIO K interrupt */ GPIOL_IRQn = 15, /*!< GPIO L interrupt */ GPIOM_IRQn = 16, /*!< GPIO M interrupt */ DMA_CH0_IRQn = 17, /*!< DMA channel 0 interrupt */ DMA_CH1_IRQn = 18, /*!< DMA channel 1 interrupt */ DMA_CH2_IRQn = 19, /*!< DMA channel 2 interrupt */ DMA_CH3_IRQn = 20, /*!< DMA channel 3 interrupt */ DMA_CH4_IRQn = 21, /*!< DMA channel 4 interrupt */ DMA_CH5_IRQn = 22, /*!< DMA channel 5 interrupt */ DMA_CH6_IRQn = 23, /*!< DMA channel 6 interrupt */ DMA_CH7_IRQn = 24, /*!< DMA channel 7 interrupt */ DMA_CH8_IRQn = 25, /*!< DMA channel 8 interrupt */ DMA_CH9_IRQn = 26, /*!< DMA channel 9 interrupt */ DMA_CH10_IRQn = 27, /*!< DMA channel 10 interrupt */ DMA_CH11_IRQn = 28, /*!< DMA channel 11 interrupt */ DMA_CH12_IRQn = 29, /*!< DMA channel 12 interrupt */ DMA_CH13_IRQn = 30, /*!< DMA channel 13 interrupt */ DMA_CH14_IRQn = 31, /*!< DMA channel 14 interrupt */ DMA_CH15_IRQn = 32, /*!< DMA channel 15 interrupt */ DMA_CH16_IRQn = 33, /*!< DMA channel 16 interrupt */ DMA_CH17_IRQn = 34, /*!< DMA channel 17 interrupt */ DMA_CH18_IRQn = 35, /*!< DMA channel 18 interrupt */ DMA_CH19_IRQn = 36, /*!< DMA channel 19 interrupt */ DMA_CH20_IRQn = 37, /*!< DMA channel 20 interrupt */ DMA_CH21_IRQn = 38, /*!< DMA channel 21 interrupt */ DMA_CH22_IRQn = 39, /*!< DMA channel 22 interrupt */ DMA_CH23_IRQn = 40, /*!< DMA channel 23 interrupt */ DMA_CH24_IRQn = 41, /*!< DMA channel 24 interrupt */ DMA_CH25_IRQn = 42, /*!< DMA channel 25 interrupt */ DMA_CH26_IRQn = 43, /*!< DMA channel 26 interrupt */ DMA_CH27_IRQn = 44, /*!< DMA channel 27 interrupt */ DMA_CH28_IRQn = 45, /*!< DMA channel 28 interrupt */ DMA_CH29_IRQn = 46, /*!< DMA channel 29 interrupt */ DMA_CH30_IRQn = 47, /*!< DMA channel 30 interrupt */ DMA_CH31_IRQn = 48, /*!< DMA channel 31 interrupt */ TMR0_IRQn = 49, /*!< Timer 0 interrupt */ TMR1_IRQn = 50, /*!< Timer 1 interrupt */ TMR2_IRQn = 51, /*!< Timer 2 interrupt */ TMR3_IRQn = 52, /*!< Timer 3 interrupt */ ETMR0_IRQn = 53, /*!< Enhanced Timer 0 interrupt */ ETMR1_IRQn = 54, /*!< Enhanced Timer 1 interrupt */ ETMR2_IRQn = 55, /*!< Enhanced Timer 2 interrupt */ ETMR3_IRQn = 56, /*!< Enhanced Timer 3 interrupt */ UART0_TD_IRQn = 57, /*!< UART0 Transmit Done interrupt */ UART0_MS_IRQn = 58, /*!< UART0 Modem interrupt */ UART0_RX_IRQn = 59, /*!< UART0 Recieve interrupt */ UART0_TX_IRQn = 60, /*!< UART0 Transmit interrupt */ UART0_RT_IRQn = 61, /*!< UART0 Recieve interrupt */ UART0_E_IRQn = 62, /*!< UART0 Error interrupt */ UART0_IRQn = 63, /*!< UART0 interrupt */ UART1_TD_IRQn = 64, /*!< UART1 Transmit Done interrupt */ UART1_MS_IRQn = 65, /*!< UART1 Modem interrupt */ UART1_RX_IRQn = 66, /*!< UART1 Recieve interrupt */ UART1_TX_IRQn = 67, /*!< UART1 Transmit interrupt */ UART1_RT_IRQn = 68, /*!< UART1 Recieve interrupt */ UART1_E_IRQn = 69, /*!< UART1 Error interrupt */ UART1_IRQn = 70, /*!< UART1 interrupt */ UART2_TD_IRQn = 71, /*!< UART2 Transmit Done interrupt */ UART2_MS_IRQn = 72, /*!< UART2 Modem interrupt */ UART2_RX_IRQn = 73, /*!< UART2 Recieve interrupt */ UART2_TX_IRQn = 74, /*!< UART2 Transmit interrupt */ UART2_RT_IRQn = 75, /*!< UART2 Recieve interrupt */ UART2_E_IRQn = 76, /*!< UART2 Error interrupt */ UART2_IRQn = 77, /*!< UART2 interrupt */ UART3_TD_IRQn = 78, /*!< UART3 Transmit Done interrupt */ UART3_MS_IRQn = 79, /*!< UART3 Modem interrupt */ UART3_RX_IRQn = 80, /*!< UART3 Recieve interrupt */ UART3_TX_IRQn = 81, /*!< UART3 Transmit interrupt */ UART3_RT_IRQn = 82, /*!< UART3 Recieve interrupt */ UART3_E_IRQn = 83, /*!< UART3 Error interrupt */ UART3_IRQn = 84, /*!< UART3 interrupt */ TUART0_RX_IRQn = 85, /*!< Tiny UART0 Receive interrupt */ TUART0_TX_IRQn = 86, /*!< Tiny UART0 Transmit interrupt */ TUART0_RO_IRQn = 87, /*!< Tiny UART0 Receive Overrun interrupt*/ TUART0_TO_IRQn = 88, /*!< Tiny UART0 Transmit Overrun interrupt*/ TUART0_IRQn = 89, /*!< Tiny UART0 interrupt */ TUART1_RX_IRQn = 90, /*!< Tiny UART1 Receive interrupt */ TUART1_TX_IRQn = 91, /*!< Tiny UART1 Transmit interrupt */ TUART1_RO_IRQn = 92, /*!< Tiny UART1 Receive Overrun interrupt*/ TUART1_TO_IRQn = 93, /*!< Tiny UART1 Transmit Overrun interrupt*/ TUART1_IRQn = 94, /*!< Tiny UART1 interrupt */ SPI0_IRQn = 95, /*!< SPI0 interrupt */ SPI0_RX_IRQn = 96, /*!< SPI0 Receive interrupt */ SPI0_TX_IRQn = 97, /*!< SPI0 Transmit interrupt */ SPI0_RO_IRQn = 98, /*!< SPI0 Receive Overrun interrupt */ SPI0_RT_IRQn = 99, /*!< SPI0 Receive Timeout interrupt */ SPI1_IRQn = 100, /*!< SPI1 interrupt */ SPI1_RX_IRQn = 101, /*!< SPI1 Receive interrupt */ SPI1_TX_IRQn = 102, /*!< SPI1 Transmit interrupt */ SPI1_RO_IRQn = 103, /*!< SPI1 Receive Overrun interrupt */ SPI1_RT_IRQn = 104, /*!< SPI1 Receive Timeout interrupt */ SPI2_IRQn = 105, /*!< SPI2 interrupt */ SPI2_RX_IRQn = 106, /*!< SPI2 Receive interrupt */ SPI2_TX_IRQn = 107, /*!< SPI2 Transmit interrupt */ SPI2_RO_IRQn = 108, /*!< SPI2 Receive Overrun interrupt */ SPI2_RT_IRQn = 109, /*!< SPI2 Receive Timeout interrupt */ SPI3_IRQn = 110, /*!< SPI3 interrupt */ SPI3_RX_IRQn = 111, /*!< SPI3 Receive interrupt */ SPI3_TX_IRQn = 112, /*!< SPI3 Transmit interrupt */ SPI3_RO_IRQn = 113, /*!< SPI3 Receive Overrun interrupt */ SPI3_RT_IRQn = 114, /*!< SPI3 Receive Timeout interrupt */ I2C0_IRQn = 115, /*!< I2C0 interrupt */ I2C1_IRQn = 116, /*!< I2C1 interrupt */ SPWR0_IRQn = 117, /*!< SpaceWire0 interrupt */ SPWR1_IRQn = 118, /*!< SpaceWire1 interrupt */ MILSTD0_IRQn = 119, /*!< MIL-STD 1553 0 interrupt */ MILSTD1_IRQn = 120, /*!< MIL-STD 1553 1 interrupt */ ECAP0_IRQn = 121, /*!< Capture Unit 0 interrupt */ ECAP1_IRQn = 122, /*!< Capture Unit 1 interrupt */ ECAP2_IRQn = 123, /*!< Capture Unit 2 interrupt */ ECAP3_IRQn = 124, /*!< Capture Unit 3 interrupt */ ECAP4_IRQn = 125, /*!< Capture Unit 4 interrupt */ ECAP5_IRQn = 126, /*!< Capture Unit 5 interrupt */ PWM0_IRQn = 127, /*!< PWM0 interrupt */ PWM0_HD_IRQn = 128, /*!< PWM0 HD interrupt */ PWM0_TZ_IRQn = 129, /*!< PWM0 TZ interrupt */ PWM1_IRQn = 130, /*!< PWM1 interrupt */ PWM1_HD_IRQn = 131, /*!< PWM1 HD interrupt */ PWM1_TZ_IRQn = 132, /*!< PWM1 TZ interrupt */ PWM2_IRQn = 133, /*!< PWM2 interrupt */ PWM2_HD_IRQn = 134, /*!< PWM2 HD interrupt */ PWM2_TZ_IRQn = 135, /*!< PWM2 TZ interrupt */ PWM3_IRQn = 136, /*!< PWM3 interrupt */ PWM3_HD_IRQn = 137, /*!< PWM3 HD interrupt */ PWM3_TZ_IRQn = 138, /*!< PWM3 TZ interrupt */ PWM4_IRQn = 139, /*!< PWM4 interrupt */ PWM4_HD_IRQn = 140, /*!< PWM4 HD interrupt */ PWM4_TZ_IRQn = 141, /*!< PWM4 TZ interrupt */ PWM5_IRQn = 142, /*!< PWM5 interrupt */ PWM5_HD_IRQn = 143, /*!< PWM5 HD interrupt */ PWM5_TZ_IRQn = 144, /*!< PWM5 TZ interrupt */ PWM6_IRQn = 145, /*!< PWM6 interrupt */ PWM6_HD_IRQn = 146, /*!< PWM6 HD interrupt */ PWM6_TZ_IRQn = 147, /*!< PWM6 TZ interrupt */ PWM7_IRQn = 148, /*!< PWM7 interrupt */ PWM7_HD_IRQn = 149, /*!< PWM7 HD interrupt */ PWM7_TZ_IRQn = 150, /*!< PWM7 TZ interrupt */ PWM8_IRQn = 151, /*!< PWM8 interrupt */ PWM8_HD_IRQn = 152, /*!< PWM8 HD interrupt */ PWM8_TZ_IRQn = 153, /*!< PWM8 TZ interrupt */ PWM9_IRQn = 154, /*!< PWM9 interrupt */ PWM9_HD_IRQn = 155, /*!< PWM9 HD interrupt */ PWM9_TZ_IRQn = 156, /*!< PWM9 TZ interrupt */ QEP0_IRQn = 157, /*!< QEP0 interrupt */ QEP1_IRQn = 158, /*!< QEP1 interrupt */ QEP2_IRQn = 159, /*!< QEP2 interrupt */ QEP3_IRQn = 160, /*!< QEP3 interrupt */ ADC_SEQ0_IRQn = 161, /*!< ADC Sequencer 0 interrupt */ ADC_SEQ1_IRQn = 162, /*!< ADC Sequencer 1 interrupt */ ADC_SEQ2_IRQn = 163, /*!< ADC Sequencer 2 interrupt */ ADC_SEQ3_IRQn = 164, /*!< ADC Sequencer 3 interrupt */ ADC_SEQ4_IRQn = 165, /*!< ADC Sequencer 4 interrupt */ ADC_SEQ5_IRQn = 166, /*!< ADC Sequencer 5 interrupt */ ADC_SEQ6_IRQn = 167, /*!< ADC Sequencer 6 interrupt */ ADC_SEQ7_IRQn = 168, /*!< ADC Sequencer 7 interrupt */ ADC_DC_IRQn = 169, /*!< ADC Digital Comparator interrupt */ ETH_IRQn = 170, /*!< Ethernet interrupt */ CAN0_IRQn = 171, /*!< CAN0 interrupt */ CAN1_IRQn = 172, /*!< CAN1 interrupt */ CAN2_IRQn = 173, /*!< CAN2 interrupt */ CAN3_IRQn = 174, /*!< CAN3 interrupt */ CAN4_IRQn = 175, /*!< CAN4 interrupt */ CAN5_IRQn = 176, /*!< CAN5 interrupt */ CAN6_IRQn = 177, /*!< CAN6 interrupt */ CAN7_IRQn = 178, /*!< CAN7 interrupt */ CAN8_IRQn = 179, /*!< CAN8 interrupt */ CAN9_IRQn = 180, /*!< CAN9 interrupt */ CAN10_IRQn = 181, /*!< CAN10 interrupt */ CAN11_IRQn = 182, /*!< CAN11 interrupt */ CAN12_IRQn = 183, /*!< CAN12 interrupt */ CAN13_IRQn = 184, /*!< CAN13 interrupt */ CAN14_IRQn = 185, /*!< CAN14 interrupt */ CAN15_IRQn = 186, /*!< CAN15 interrupt */ FPU_IRQn = 187, /*!< FPU exception interrupt */ TMU_IRQn = 188, /*!< TMU interrupt */ LAU_IRQn = 189, /*!< LAU interrupt */ SDFM_IRQn = 190, /*!< SDFM interrupt */ OWI0_IRQn = 191, /*!< OWI0 interrupt */ OWI1_IRQn = 192, /*!< OWI1 interrupt */ } IRQn_Type; #include /* Cortex-M4 processor and core peripherals */ #include /* System initialization */ /******************************************************************************/ /* System Specific Defenitions */ /******************************************************************************/ /*-- System memory ----------------------------------------------------------*/ #define MEM_MFLASH_BASE 0x10000000UL #define MEM_MFLASH_BUS_WIDTH_WORDS 16UL #define MEM_MFLASH_PAGE_SIZE 16384UL #define MEM_MFLASH_PAGE_SIZE_LOG2 14UL #define MEM_MFLASH_PAGE_TOTAL 128UL #define MEM_MFLASH_SIZE (MEM_MFLASH_PAGE_TOTAL*MEM_MFLASH_PAGE_SIZE) #define MEM_MFLASH_NVR_PAGE_SIZE (MEM_MFLASH_PAGE_SIZE) #define MEM_MFLASH_NVR_PAGE_SIZE_LOG2 (MEM_MFLASH_PAGE_SIZE_LOG2) #define MEM_MFLASH_NVR_PAGE_TOTAL 4UL #define MEM_MFLASH_NVR_SIZE (MEM_MFLASH_NVR_PAGE_TOTAL*MEM_MFLASH_NVR_PAGE_SIZE) #define MEM_BFLASH_BASE 0x11000000UL #define MEM_BFLASH_BUS_WIDTH_WORDS 4UL #define MEM_BFLASH_PAGE_SIZE 4096UL #define MEM_BFLASH_PAGE_SIZE_LOG2 12UL #define MEM_BFLASH_PAGE_TOTAL 128UL #define MEM_BFLASH_SIZE (MEM_BFLASH_PAGE_TOTAL*MEM_BFLASH_PAGE_SIZE) #define MEM_BFLASH_NVR_PAGE_SIZE (MEM_BFLASH_PAGE_SIZE) #define MEM_BFLASH_NVR_PAGE_SIZE_LOG2 (MEM_BFLASH_PAGE_SIZE_LOG2) #define MEM_BFLASH_NVR_PAGE_TOTAL 4UL #define MEM_BFLASH_NVR_SIZE (MEM_BFLASH_NVR_PAGE_TOTAL*MEM_BFLASH_NVR_PAGE_SIZE) #define MEM_RAM0_BASE 0x13000000UL #define MEM_RAM0_SIZE 0x10000UL #define MEM_RAM1_BASE 0x20000000UL #define MEM_RAM1_SIZE 0x80000UL #define MEM_RAM2_BASE 0x20080000UL #define MEM_RAM2_SIZE 0x20000UL #define MEM_EXT0_BASE 0x80000000UL #define MEM_EXT1_BASE 0x81000000UL #define MEM_EXT2_BASE 0x82000000UL #define MEM_EXT3_BASE 0x83000000UL #define MEM_EXT4_BASE 0x84000000UL #define MEM_EXT5_BASE 0x85000000UL #define MEM_EXT6_BASE 0x86000000UL #define MEM_EXT7_BASE 0x87000000UL #define MEM_EXT_SIZE 0x1000000UL /*-- CFGWORD: System configure word -----------------------------------------*/ #define CFGWORD0_BASE 0x00000FF0UL typedef struct { uint32_t RDC : 4; /*!< External memory read cycle length (default 0xF - 16 cycles) */ uint32_t WRC : 4; /*!< External memory write cycle length (default 0xF - 16 cycles) */ uint32_t MASK : 24; /*!< External memory address mask (default 0xFFFFF - all bits masked) */ } CFGWORD0_bits; /* Bit field positions: */ #define CFGWORD0_RDC_Pos 0 /*!< External memory read cycle length (default 0xF - 16 cycles) */ #define CFGWORD0_WRC_Pos 4 /*!< External memory write cycle length (default 0xF - 16 cycles) */ #define CFGWORD0_MASK_Pos 8 /*!< External memory address mask (default 0xFFFFF - all bits masked) */ /* Bit field masks: */ #define CFGWORD0_RDC_Msk 0x0000000FUL /*!< External memory read cycle length (default 0xF - 16 cycles) */ #define CFGWORD0_WRC_Msk 0x000000F0UL /*!< External memory write cycle length (default 0xF - 16 cycles) */ #define CFGWORD0_MASK_Msk 0xFFFFFF00UL /*!< External memory address mask (default 0xFFFFF - all bits masked) */ #define CFGWORD1_BASE 0x00000FF4UL typedef struct { uint32_t TAC : 4; /*!< External memory turnaround cycle length (default 0xF - 16 cycles) */ uint32_t MODE : 1; /*!< External memory bit mode (default 1 - 16 bit; 0 - 8 bit) */ uint32_t AF : 1; /*!< External memory GPIO alternative function (default 1 - AF1; 0 - AF0) */ uint32_t MFLASHWE : 1; /*!< Main MFLASH region write enable (default 1 - enabled) */ uint32_t MNVRWE : 1; /*!< NVR MFLASH region write enable (default 1 - enabled) */ uint32_t BFLASHWE : 1; /*!< Main BFLASH region write enable (default 1 - enabled) */ uint32_t BNVRWE : 1; /*!< NVR BFLASH region write enable (default 1 - enabled) */ uint32_t JTAGEN : 1; /*!< Enable JTAG pins (default 1 - enabled) */ uint32_t DEBUGEN : 1; /*!< Enable core debug (default 1 - enabled) */ } CFGWORD1_bits; /* Bit field positions: */ #define CFGWORD1_TAC_Pos 0 /*!< External memory turnaround cycle length (default 0xF - 16 cycles) */ #define CFGWORD1_MODE_Pos 4 /*!< External memory bit mode (default 1 - 16 bit; 0 - 8 bit) */ #define CFGWORD1_AF_Pos 5 /*!< External memory GPIO alternative function (default 1 - AF1; 0 - AF0) */ #define CFGWORD1_MFLASHWE_Pos 6 /*!< Main flash region write enable (default 1 - enabled) */ #define CFGWORD1_MNVRWE_Pos 7 /*!< NVR flash region write enable (default 1 - enabled) */ #define CFGWORD1_BFLASHWE_Pos 8 /*!< Main flash region write enable (default 1 - enabled) */ #define CFGWORD1_BNVRWE_Pos 9 /*!< NVR flash region write enable (default 1 - enabled) */ #define CFGWORD1_JTAGEN_Pos 10 /*!< Enable JTAG pins (default 1 - enabled) */ #define CFGWORD1_DEBUGEN_Pos 11 /*!< Enable core debug (default 1 - enabled) */ /* Bit field masks: */ #define CFGWORD1_TAC_Msk 0x0000000FUL /*!< External memory turnaround cycle length (default 0xF - 16 cycles) */ #define CFGWORD1_MODE_Msk 0x00000010UL /*!< External memory bit mode (default 1 - 16 bit; 0 - 8 bit) */ #define CFGWORD1_AF_Msk 0x00000020UL /*!< External memory GPIO alternative function (default 1 - AF1; 0 - AF0) */ #define CFGWORD1_MFLASHWE_Msk 0x00000040UL /*!< Main flash region write enable (default 1 - enabled) */ #define CFGWORD1_MNVRWE_Msk 0x00000080UL /*!< NVR flash region write enable (default 1 - enabled) */ #define CFGWORD1_BFLASHWE_Msk 0x00000100UL /*!< Main flash region write enable (default 1 - enabled) */ #define CFGWORD1_BNVRWE_Msk 0x00000200UL /*!< NVR flash region write enable (default 1 - enabled) */ #define CFGWORD1_JTAGEN_Msk 0x00000400UL /*!< Enable JTAG pins (default 1 - enabled) */ #define CFGWORD1_DEBUGEN_Msk 0x00000800UL /*!< Enable core debug (default 1 - enabled) */ /*-- CHANNEL_CFG: DMA channel configure word --------------------------------*/ typedef struct { uint32_t CYCLE_CTRL : 3; /*!< The operating mode of the DMA cycle */ uint32_t NEXT_USEBURST : 1; /*!< Controls if the DMA->USEBURSTSET bit is set to a 1 */ uint32_t N_MINUS_1 : 10; /*!< The total number of DMA transfers that the DMA cycle contains */ uint32_t R_POWER : 4; /*!< Control how many DMA transfers can occur before the controller rearbitrates (2^R_POWER, 1024 max) */ uint32_t SRC_PROT_PRIV : 1; /*!< Bus protection when the controller reads the source data: privileged access */ uint32_t SRC_PROT_BUFF : 1; /*!< Bus protection when the controller reads the source data: bufferable access */ uint32_t SRC_PROT_CACHE : 1; /*!< Bus protection when the controller reads the source data: cacheable access */ uint32_t DST_PROT_PRIV : 1; /*!< Bus protection when the controller writes the destination data: privileged access */ uint32_t DST_PROT_BUFF : 1; /*!< Bus protection when the controller writes the destination data: bufferable access */ uint32_t DST_PROT_CACHE : 1; /*!< Bus protection when the controller writes the destination data: cacheable access */ uint32_t SRC_SIZE : 2; /*!< Size of the source data */ uint32_t SRC_INC : 2; /*!< Source address increment */ uint32_t DST_SIZE : 2; /*!< Destination data size */ uint32_t DST_INC : 2; /*!< Destination address increment */ } _CHANNEL_CFG_bits; /* Bit field positions: */ #define DMA_CHANNEL_CFG_CYCLE_CTRL_Pos 0 /*!< The operating mode of the DMA cycle */ #define DMA_CHANNEL_CFG_NEXT_USEBURST_Pos 3 /*!< Controls if the DMA->USEBURSTSET bit is set to a 1 */ #define DMA_CHANNEL_CFG_N_MINUS_1_Pos 4 /*!< The total number of DMA transfers that the DMA cycle contains */ #define DMA_CHANNEL_CFG_R_POWER_Pos 14 /*!< Control how many DMA transfers can occur before the controller rearbitrates */ #define DMA_CHANNEL_CFG_SRC_PROT_PRIV_Pos 18 /*!< Bus protection when the controller reads the source data: privileged access */ #define DMA_CHANNEL_CFG_SRC_PROT_BUFF_Pos 19 /*!< Bus protection when the controller reads the source data: bufferable access */ #define DMA_CHANNEL_CFG_SRC_PROT_CACHE_Pos 20 /*!< Bus protection when the controller reads the source data: cacheable access */ #define DMA_CHANNEL_CFG_DST_PROT_PRIV_Pos 21 /*!< Bus protection when the controller writes the destination data: privileged access */ #define DMA_CHANNEL_CFG_DST_PROT_BUFF_Pos 22 /*!< Bus protection when the controller writes the destination data: bufferable access */ #define DMA_CHANNEL_CFG_DST_PROT_CACHE_Pos 23 /*!< Bus protection when the controller writes the destination data: cacheable access */ #define DMA_CHANNEL_CFG_SRC_SIZE_Pos 24 /*!< Size of the source data */ #define DMA_CHANNEL_CFG_SRC_INC_Pos 26 /*!< Source address increment */ #define DMA_CHANNEL_CFG_DST_SIZE_Pos 28 /*!< Destination data size */ #define DMA_CHANNEL_CFG_DST_INC_Pos 30 /*!< Destination address increment */ /* Bit field masks: */ #define DMA_CHANNEL_CFG_CYCLE_CTRL_Msk 0x00000007UL /*!< The operating mode of the DMA cycle */ #define DMA_CHANNEL_CFG_NEXT_USEBURST_Msk 0x00000008UL /*!< Controls if the DMA->USEBURSTSET bit is set to a 1 */ #define DMA_CHANNEL_CFG_N_MINUS_1_Msk 0x00003FF0UL /*!< The total number of DMA transfers that the DMA cycle contains */ #define DMA_CHANNEL_CFG_R_POWER_Msk 0x0003C000UL /*!< Control how many DMA transfers can occur before the controller rearbitrates */ #define DMA_CHANNEL_CFG_SRC_PROT_PRIV_Msk 0x00040000UL /*!< Bus protection when the controller reads the source data: privileged access */ #define DMA_CHANNEL_CFG_SRC_PROT_BUFF_Msk 0x00080000UL /*!< Bus protection when the controller reads the source data: bufferable access */ #define DMA_CHANNEL_CFG_SRC_PROT_CACHE_Msk 0x00100000UL /*!< Bus protection when the controller reads the source data: cacheable access */ #define DMA_CHANNEL_CFG_DST_PROT_PRIV_Msk 0x00200000UL /*!< Bus protection when the controller writes the destination data: privileged access */ #define DMA_CHANNEL_CFG_DST_PROT_BUFF_Msk 0x00400000UL /*!< Bus protection when the controller writes the destination data: bufferable access */ #define DMA_CHANNEL_CFG_DST_PROT_CACHE_Msk 0x00800000UL /*!< Bus protection when the controller writes the destination data: cacheable access */ #define DMA_CHANNEL_CFG_SRC_SIZE_Msk 0x03000000UL /*!< Size of the source data */ #define DMA_CHANNEL_CFG_SRC_INC_Msk 0x0C000000UL /*!< Source address increment */ #define DMA_CHANNEL_CFG_DST_SIZE_Msk 0x30000000UL /*!< Destination data size */ #define DMA_CHANNEL_CFG_DST_INC_Msk 0xC0000000UL /*!< Destination address increment */ /* Bit field enums: */ typedef enum { DMA_CHANNEL_CFG_CYCLE_CTRL_Stop = 0x0UL, /*!< Stop */ DMA_CHANNEL_CFG_CYCLE_CTRL_Basic = 0x1UL, /*!< Basic */ DMA_CHANNEL_CFG_CYCLE_CTRL_AutoReq = 0x2UL, /*!< Auto-request */ DMA_CHANNEL_CFG_CYCLE_CTRL_PingPong = 0x3UL, /*!< Ping-pong */ DMA_CHANNEL_CFG_CYCLE_CTRL_MemScatGathPrim = 0x4UL, /*!< Memory scatter-gather for primary structure */ DMA_CHANNEL_CFG_CYCLE_CTRL_MemScatGathAlt = 0x5UL, /*!< Memory scatter-gather for alternative structure */ DMA_CHANNEL_CFG_CYCLE_CTRL_PeriphScatGathPrim = 0x6UL, /*!< Peripheral scatter-gather for primary structure */ DMA_CHANNEL_CFG_CYCLE_CTRL_PeriphScatGathAlt = 0x7UL, /*!< Peripheral scatter-gather for alternative structure */ } DMA_CHANNEL_CFG_CYCLE_CTRL_Enum; typedef enum { DMA_CHANNEL_CFG_SRC_SIZE_Byte = 0x0UL, /*!< 8 bit */ DMA_CHANNEL_CFG_SRC_SIZE_Halfword = 0x1UL, /*!< 16 bit */ DMA_CHANNEL_CFG_SRC_SIZE_Word = 0x2UL, /*!< 32 bit */ } DMA_CHANNEL_CFG_SRC_SIZE_Enum; typedef enum { DMA_CHANNEL_CFG_SRC_INC_Byte = 0x0UL, /*!< 8 bit */ DMA_CHANNEL_CFG_SRC_INC_Halfword = 0x1UL, /*!< 16 bit */ DMA_CHANNEL_CFG_SRC_INC_Word = 0x2UL, /*!< 32 bit */ DMA_CHANNEL_CFG_SRC_INC_None = 0x3UL, /*!< No increment */ } DMA_CHANNEL_CFG_SRC_INC_Enum; typedef enum { DMA_CHANNEL_CFG_DST_SIZE_Byte = 0x0UL, /*!< 8 bit */ DMA_CHANNEL_CFG_DST_SIZE_Halfword = 0x1UL, /*!< 16 bit */ DMA_CHANNEL_CFG_DST_SIZE_Word = 0x2UL, /*!< 32 bit */ } DMA_CHANNEL_CFG_DST_SIZE_Enum; typedef enum { DMA_CHANNEL_CFG_DST_INC_Byte = 0x0UL, /*!< 8 bit */ DMA_CHANNEL_CFG_DST_INC_Halfword = 0x1UL, /*!< 16 bit */ DMA_CHANNEL_CFG_DST_INC_Word = 0x2UL, /*!< 32 bit */ DMA_CHANNEL_CFG_DST_INC_None = 0x3UL, /*!< No increment */ } DMA_CHANNEL_CFG_DST_INC_Enum; /*-- DMA channel structure --------------------------------------------------*/ typedef struct { __IO uint32_t SRC_DATA_END_PTR; /*!< Source data end pointer */ __IO uint32_t DST_DATA_END_PTR; /*!< Destination data end pointer */ union { __IO uint32_t CHANNEL_CFG; /*!< Channel configure word */ __IO _CHANNEL_CFG_bits CHANNEL_CFG_bit; /*!< channel configure word: bit access */ }; __IO uint32_t RESERVED; } DMA_Channel_TypeDef; /*-- DMA control structure --------------------------------------------------*/ typedef struct { DMA_Channel_TypeDef CH[32]; /*!< Control structure channels */ } DMA_CtrlStruct_TypeDef; #define DMA_CH_UART0TX 0 /*!< UART0 TX DMA channel */ #define DMA_CH_UART1TX 1 /*!< UART1 TX DMA channel */ #define DMA_CH_UART2TX 2 /*!< UART2 TX DMA channel */ #define DMA_CH_UART3TX 3 /*!< UART3 TX DMA channel */ #define DMA_CH_UART0RX 4 /*!< UART0 RX DMA channel */ #define DMA_CH_UART1RX 5 /*!< UART1 RX DMA channel */ #define DMA_CH_UART2RX 6 /*!< UART2 RX DMA channel */ #define DMA_CH_UART3RX 7 /*!< UART3 RX DMA channel */ #define DMA_CH_SPI0TX 8 /*!< SPI0 TX DMA channel */ #define DMA_CH_SPI1TX 9 /*!< SPI1 TX DMA channel */ #define DMA_CH_SPI2TX 10 /*!< SPI2 TX DMA channel */ #define DMA_CH_SPI3TX 11 /*!< SPI3 TX DMA channel */ #define DMA_CH_SPI0RX 12 /*!< SPI0 RX DMA channel */ #define DMA_CH_SPI1RX 13 /*!< SPI1 RX DMA channel */ #define DMA_CH_SPI2RX 14 /*!< SPI2 RX DMA channel */ #define DMA_CH_SPI3RX 15 /*!< SPI3 RX DMA channel */ #define DMA_CH_ADCSEQ0 16 /*!< ADC sequencer 0 DMA channel */ #define DMA_CH_ADCSEQ1 17 /*!< ADC sequencer 1 DMA channel */ #define DMA_CH_ADCSEQ2 18 /*!< ADC sequencer 2 DMA channel */ #define DMA_CH_ADCSEQ3 19 /*!< ADC sequencer 3 DMA channel */ #define DMA_CH_ADCSEQ4 20 /*!< ADC sequencer 4 DMA channel */ #define DMA_CH_ADCSEQ5 21 /*!< ADC sequencer 5 DMA channel */ #define DMA_CH_ADCSEQ6 22 /*!< ADC sequencer 6 DMA channel */ #define DMA_CH_ADCSEQ7 23 /*!< ADC sequencer 7 DMA channel */ #define DMA_CH_GPIOA 24 /*!< GPIOA DMA channel */ #define DMA_CH_GPIOB 25 /*!< GPIOB DMA channel */ #define DMA_CH_GPIOC 26 /*!< GPIOC DMA channel */ #define DMA_CH_GPIOD 27 /*!< GPIOD DMA channel */ #define DMA_CH_GPIOE 28 /*!< GPIOE DMA channel */ #define DMA_CH_GPIOF 29 /*!< GPIOF DMA channel */ #define DMA_CH_GPIOG 30 /*!< GPIOG DMA channel */ #define DMA_CH_GPIOH 31 /*!< GPIOH DMA channel */ #define DMA_CH_GPIOJ 27 /*!< GPIOJ DMA channel */ #define DMA_CH_GPIOK 27 /*!< GPIOK DMA channel */ #define DMA_CH_GPIOL 31 /*!< GPIOL DMA channel */ #define DMA_CH_GPIOM 31 /*!< GPIOM DMA channel */ #define DMA_CH_TMR0 24 /*!< TMR0 DMA channel */ #define DMA_CH_TMR1 25 /*!< TMR1 DMA channel */ #define DMA_CH_TMR2 26 /*!< TMR2 DMA channel */ #define DMA_CH_TMR3 27 /*!< TMR3 DMA channel */ #define DMA_CH_ETMR0 28 /*!< EMR0 DMA channel */ #define DMA_CH_ETMR1 29 /*!< EMR1 DMA channel */ #define DMA_CH_ETMR2 30 /*!< EMR2 DMA channel */ #define DMA_CH_ETMR3 31 /*!< EMR3 DMA channel */ #define DMA_CH_PWM0A 24 /*!< PWM0A DMA channel */ #define DMA_CH_PWM1A 24 /*!< PWM1A DMA channel */ #define DMA_CH_PWM2A 25 /*!< PWM2A DMA channel */ #define DMA_CH_PWM3A 25 /*!< PWM3A DMA channel */ #define DMA_CH_PWM4A 26 /*!< PWM4A DMA channel */ #define DMA_CH_PWM5A 26 /*!< PWM5A DMA channel */ #define DMA_CH_PWM6A 27 /*!< PWM6A DMA channel */ #define DMA_CH_PWM7A 27 /*!< PWM7A DMA channel */ #define DMA_CH_PWM8A 24 /*!< PWM8A DMA channel */ #define DMA_CH_PWM9A 24 /*!< PWM9A DMA channel */ #define DMA_CH_PWM0B 28 /*!< PWM0B DMA channel */ #define DMA_CH_PWM1B 28 /*!< PWM1B DMA channel */ #define DMA_CH_PWM2B 29 /*!< PWM2B DMA channel */ #define DMA_CH_PWM3B 29 /*!< PWM3B DMA channel */ #define DMA_CH_PWM4B 30 /*!< PWM4B DMA channel */ #define DMA_CH_PWM5B 30 /*!< PWM5B DMA channel */ #define DMA_CH_PWM6B 31 /*!< PWM6B DMA channel */ #define DMA_CH_PWM7B 31 /*!< PWM7B DMA channel */ #define DMA_CH_PWM8B 28 /*!< PWM8B DMA channel */ #define DMA_CH_PWM9B 28 /*!< PWM9B DMA channel */ #define DMA_CH_SDFM0 25 /*!< SDFM0 DMA channel */ #define DMA_CH_SDFM1 26 /*!< SDFM1 DMA channel */ #define DMA_CH_SDFM2 29 /*!< SDFM2 DMA channel */ #define DMA_CH_SDFM3 30 /*!< SDFM3 DMA channel */ #define DMA_CH_QEP0 25 /*!< QEP0 DMA channel */ #define DMA_CH_QEP1 26 /*!< QEP1 DMA channel */ #define DMA_CH_QEP2 29 /*!< QEP2 DMA channel */ #define DMA_CH_QEP3 30 /*!< QEP3 DMA channel */ /*-- DMA control data summary -----------------------------------------------*/ /*!< WARNING: struct should be 1024 byte aligned! Allowed addresses 0xXXXXX000, 0xXXXXX400, 0xXXXXX800, etc */ typedef struct { DMA_CtrlStruct_TypeDef PRM_DATA; /*!< Primary control structure */ DMA_CtrlStruct_TypeDef ALT_DATA; /*!< Alternative control structure */ } DMA_CtrlData_TypeDef; /*-- SpaceWire RX descriptor CTRL structure --------------------------------*/ typedef struct { uint32_t PKTLEN : 25; /*!< Packet length */ uint32_t EN : 1; /*!< Enable */ uint32_t WR : 1; /*!< Wrap */ uint32_t IE : 1; /*!< Interrupt enable */ uint32_t EP : 1; /*!< EEP termination */ uint32_t : 2; /*!< RESERVED */ uint32_t TR : 1; /*!< Packet truncated */ } _SPWR_RXD_CTRL_bits; /* Bit field positions: */ #define SPWR_RXD_CTRL_PKTLEN_Pos 0 /*!< Packet length */ #define SPWR_RXD_CTRL_EN_Pos 25 /*!< Enable */ #define SPWR_RXD_CTRL_WR_Pos 26 /*!< Wrap */ #define SPWR_RXD_CTRL_IE_Pos 27 /*!< Interrupt enable */ #define SPWR_RXD_CTRL_EP_Pos 28 /*!< EEP termination */ #define SPWR_RXD_CTRL_TR_Pos 31 /*!< Packet truncated */ /* Bit field masks: */ #define SPWR_RXD_CTRL_PKTLEN_Msk 0x01FFFFFFUL /*!< Packet length */ #define SPWR_RXD_CTRL_EN_Msk 0x02000000UL /*!< Enable */ #define SPWR_RXD_CTRL_WR_Msk 0x04000000UL /*!< Wrap */ #define SPWR_RXD_CTRL_IE_Msk 0x08000000UL /*!< Interrupt enable */ #define SPWR_RXD_CTRL_EP_Msk 0x10000000UL /*!< EEP termination */ #define SPWR_RXD_CTRL_TR_Msk 0x80000000UL /*!< Packet truncated */ /*-- SpaceWire RX descriptor structure --------------------------------------------------*/ /*!< WARNING: struct should be 16 byte aligned!*/ typedef struct { union { __IO uint32_t WORDS[2]; /*!< RX descriptor words array */ struct { union { __IO uint32_t CTRL; /*!< RX descriptor word 0 */ __IO _SPWR_RXD_CTRL_bits CTRL_bit; /*!< RX descriptor word 0: bit access */ }; __IO uint32_t PKTADDR; /*!< RX descriptor word 1: packet address */ }; } ; } SPWR_RXD_TypeDef; /*-- SpaceWire TX descriptor CTRL structure --------------------------------*/ /*!< WARNING: struct should be 16 byte aligned!*/ typedef struct { uint32_t HEADERLEN : 8; /*!< Header length */ uint32_t : 4; /*!< RESERVED */ uint32_t EN : 1; /*!< Enable */ uint32_t WR : 1; /*!< Wrap */ uint32_t IE : 1; /*!< Interrupt enable */ uint32_t LE : 1; /*!< Link error */ } _SPWR_TXD_CTRL_bits; /* Bit field positions: */ #define SPWR_TXD_CTRL_HEADERLEN_Pos 0 /*!< Header length */ #define SPWR_TXD_CTRL_EN_Pos 12 /*!< Enable */ #define SPWR_TXD_CTRL_WR_Pos 13 /*!< Wrap */ #define SPWR_TXD_CTRL_IE_Pos 14 /*!< Interrupt enable */ #define SPWR_TXD_CTRL_LE_Pos 15 /*!< Link error */ /* Bit field masks: */ #define SPWR_TXD_CTRL_HEADERLEN_Msk 0x000000FFUL /*!< Header length */ #define SPWR_TXD_CTRL_EN_Msk 0x00001000UL /*!< Enable */ #define SPWR_TXD_CTRL_WR_Msk 0x00002000UL /*!< Wrap */ #define SPWR_TXD_CTRL_IE_Msk 0x00004000UL /*!< Interrupt enable */ #define SPWR_TXD_CTRL_LE_Msk 0x00008000UL /*!< Link error */ typedef struct { union { __IO uint32_t WORDS[4]; /*!< TX descriptor words array */ struct { union { __IO uint32_t CTRL; /*!< TX descriptor word 0 */ __IO _SPWR_TXD_CTRL_bits CTRL_bit; /*!< TX descriptor word 0: bit access */ }; __IO uint32_t HEADERADDR; /*!< TX descriptor word 1: header address */ __IO uint32_t DATALEN; /*!< TX descriptor word 2: data length */ __IO uint32_t DATAADDR; /*!< TX descriptor word 3: data address */ }; } ; } SPWR_TXD_TypeDef; /*-- Milstd Transfer descriptor Word 0 configure word --------------------------------*/ typedef struct { uint32_t STIME :16; /*!< Slot time (STIME) - Allocated time in 4 microsecond units, remaining time after transfer will insert delay */ uint32_t RESERVED :2; /*!< Reserved */ uint32_t GAP :1; /*!< Extended intermessage gap (GAP) - If set, adds an additional amount of gap time, corresponding to the RTTO field, after the transfer */ uint32_t STBUS :1; /*!< Store bus (STBUS) - If the transfer succeeds and this bit is set, store the bus on which the transfer succeeded (0 for bus A, 1 for bus B) into the per-RT bus swap register. If the transfer fails and this bit is set, store the opposite bus instead. (only if the per-RT bus mask is supported in the core) */ uint32_t NRET :3; /*!< Number of retries (NRET) - Number of automatic retries per bus The total number of tries (including the first attempt) is NRET+1 for RETMD=00, 2 x (NRET+1) for RETMD=01/10 */ uint32_t RETMD :2; /*!< Retry mode (RETMD). */ uint32_t SUSN :1; /*!< Suspend normally (SUSN) - Always suspends after transfer */ uint32_t SUSE :1; /*!< Suspend on Error (SUSE) - Suspends the schedule (or stops the async transfer list) on error */ uint32_t IRQN :1; /*!< IRQ normally (IRQN) - Always interrupts after transfer */ uint32_t IRQE :1; /*!< IRQ after transfer on Error (IRQE) */ uint32_t EXCL :1; /*!< Exclusive time slot (EXCL) - Do not schedule asynchronous messages */ uint32_t WTRIG :1; /*!< Wait for external trigger (WTRIG) */ uint32_t ZERO :1; /*!< Must be 0 to identify as descriptor */ } _MILSTD_BC_TDESC_WORD0_bits; /* Bit field positions: */ #define MILSTD_BC_TDESC_WORD0_STIME_Pos 0 /*!< Slot time (STIME) - Allocated time in 4 microsecond units, remaining time after transfer will insert delay */ #define MILSTD_BC_TDESC_WORD0_GAP_Pos 18 /*!< Extended intermessage gap (GAP) - If set, adds an additional amount of gap time, corresponding to the RTTO field, after the transfer */ #define MILSTD_BC_TDESC_WORD0_STBUS_Pos 19 /*!< Store bus (STBUS) - If the transfer succeeds and this bit is set, store the bus on which the transfer succeeded */ #define MILSTD_BC_TDESC_WORD0_NRET_Pos 20 /*!< Number of retries (NRET) - Number of automatic retries per bus */ #define MILSTD_BC_TDESC_WORD0_RETMD_Pos 23 /*!< Retry mode (RETMD) */ #define MILSTD_BC_TDESC_WORD0_SUSN_Pos 25 /*!< Suspend normally (SUSN) - Always suspends after transfer */ #define MILSTD_BC_TDESC_WORD0_SUSE_Pos 26 /*!< Suspend on Error (SUSE) - Suspends the schedule (or stops the async transfer list) on error */ #define MILSTD_BC_TDESC_WORD0_IRQN_Pos 27 /*!< IRQ normally (IRQN) - Always interrupts after transfer */ #define MILSTD_BC_TDESC_WORD0_IRQE_Pos 28 /*!< IRQ after transfer on Error (IRQE) */ #define MILSTD_BC_TDESC_WORD0_EXCL_Pos 29 /*!< Exclusive time slot (EXCL) - Do not schedule asynchronous messages */ #define MILSTD_BC_TDESC_WORD0_WTRIG_Pos 30 /*!< Wait for external trigger (WTRIG) */ /* Bit field masks: */ #define MILSTD_BC_TDESC_WORD0_STIME_Msk 0x0000FFFFUL /*!< Slot time (STIME) - Allocated time in 4 microsecond units, remaining time after transfer will insert delay */ #define MILSTD_BC_TDESC_WORD0_GAP_Msk 0x00040000UL /*!< Extended intermessage gap (GAP) - If set, adds an additional amount of gap time, corresponding to the RTTO field, after the transfer */ #define MILSTD_BC_TDESC_WORD0_STBUS_Msk 0x00080000UL /*!< Store bus (STBUS) - If the transfer succeeds and this bit is set, store the bus on which the transfer succeeded */ #define MILSTD_BC_TDESC_WORD0_NRET_Msk 0x00700000UL /*!< Number of retries (NRET) - Number of automatic retries per bus */ #define MILSTD_BC_TDESC_WORD0_RETMD_Msk 0x01800000UL /*!< Retry mode (RETMD) */ #define MILSTD_BC_TDESC_WORD0_SUSN_Msk 0x02000000UL /*!< Suspend normally (SUSN) - Always suspends after transfer */ #define MILSTD_BC_TDESC_WORD0_SUSE_Msk 0x04000000UL /*!< Suspend on Error (SUSE) - Suspends the schedule (or stops the async transfer list) on error */ #define MILSTD_BC_TDESC_WORD0_IRQN_Msk 0x08000000UL /*!< IRQ normally (IRQN) - Always interrupts after transfer */ #define MILSTD_BC_TDESC_WORD0_IRQE_Msk 0x10000000UL /*!< IRQ after transfer on Error (IRQE) */ #define MILSTD_BC_TDESC_WORD0_EXCL_Msk 0x20000000UL /*!< Exclusive time slot (EXCL) - Do not schedule asynchronous messages */ #define MILSTD_BC_TDESC_WORD0_WTRIG_Msk 0x40000000UL /*!< Wait for external trigger (WTRIG) */ #define MILSTD_BC_TDESC_WORD0_ZERO_Msk 0x80000000UL /*!< Wait for external trigger (WTRIG) */ /* Bit field enums: */ typedef enum { MILSTD_BC_TDESC_WORD0_RETMD_SameBus = 0x0UL, /*!< Retry on same bus only */ MILSTD_BC_TDESC_WORD0_RETMD_BothBus = 0x1UL, /*!< Retry alternating on both buses */ MILSTD_BC_TDESC_WORD0_RETMD_FirstSameBus = 0x2UL, /*!< Retry first on same bus, then on alternating bus */ } MILSTD_BC_TDESC_WORD0_RETMD_Enum; /*-- Milstd Transfer descriptor Word 1 configure word --------------------------------*/ typedef struct { uint32_t WCMC :5; /*!< Word count/Mode code (WCMC) */ uint32_t RTSA1 :5; /*!< RT Subaddress (RTSA1) */ uint32_t TR :1; /*!< Transmit/receive (TR) */ uint32_t RTAD1 :5; /*!< RT Address (RTAD1) */ uint32_t RTSA2 :5; /*!< Second RT Subaddress for RT-to-RT transfer (RTSA2) */ uint32_t RTAD2 :5; /*!< Second RT Address for RT-to-RT transfer (RTAD2) */ uint32_t RTTO :4; /*!< RT Timeout (RTTO) - Extra RT status word timeout above nominal in units of 4 us Note: This extra time is also used as extra intermessage gap time if the GAP bit is set. */ uint32_t BUS :1; /*!< Bus selection (BUS) - Bus to use for transfer, 0 - Bus A, 1 - Bus B */ uint32_t DUM :1; /*!< Dummy transfer (DUM) - If set to �1� no bus traffic is generated and transfer �succeeds� immediately For dummy transfers, the EXCL,IRQN,SUSN,STBUS,GAP,STIME settings are still in effect, other bits and the data buffer pointer are ignored. */ } _MILSTD_BC_TDESC_WORD1_bits; /* Bit field positions: */ #define MILSTD_BC_TDESC_WORD1_WCMC_Pos 0 /*!< Word count/Mode code (WCMC) */ #define MILSTD_BC_TDESC_WORD1_RTSA1_Pos 5 /*!< RT Subaddress (RTSA1) */ #define MILSTD_BC_TDESC_WORD1_TR_Pos 10 /*!< Transmit/receive (TR) */ #define MILSTD_BC_TDESC_WORD1_RTAD1_Pos 11 /*!< RT Address (RTAD1) */ #define MILSTD_BC_TDESC_WORD1_RTSA2_Pos 16 /*!< Second RT Subaddress for RT-to-RT transfer (RTSA2) */ #define MILSTD_BC_TDESC_WORD1_RTAD2_Pos 21 /*!< Second RT Address for RT-to-RT transfer (RTAD2) */ #define MILSTD_BC_TDESC_WORD1_RTTO_Pos 26 /*!< RT Timeout (RTTO) - Extra RT status word timeout above nominal in units of 4 us */ #define MILSTD_BC_TDESC_WORD1_BUS_Pos 30 /*!< Bus selection (BUS) - Bus to use for transfer, 0 - Bus A, 1 - Bus B */ #define MILSTD_BC_TDESC_WORD1_DUM_Pos 31 /*!< Dummy transfer (DUM) */ /* Bit field masks: */ #define MILSTD_BC_TDESC_WORD1_WCMC_Msk 0x0000001FUL /*!< Word count/Mode code (WCMC) */ #define MILSTD_BC_TDESC_WORD1_RTSA1_Msk 0x000003E0UL /*!< RT Subaddress (RTSA1) */ #define MILSTD_BC_TDESC_WORD1_TR_Msk 0x00000400UL /*!< Transmit/receive (TR) */ #define MILSTD_BC_TDESC_WORD1_RTAD1_Msk 0x0000F800UL /*!< RT Address (RTAD1) */ #define MILSTD_BC_TDESC_WORD1_RTSA2_Msk 0x001F0000UL /*!< Second RT Subaddress for RT-to-RT transfer (RTSA2) */ #define MILSTD_BC_TDESC_WORD1_RTAD2_Msk 0x03E00000UL /*!< Second RT Address for RT-to-RT transfer (RTAD2) */ #define MILSTD_BC_TDESC_WORD1_RTTO_Msk 0x3C000000UL /*!< RT Timeout (RTTO) - Extra RT status word timeout above nominal in units of 4 us */ #define MILSTD_BC_TDESC_WORD1_BUS_Msk 0x40000000UL /*!< Bus selection (BUS) - Bus to use for transfer, 0 - Bus A, 1 - Bus B */ #define MILSTD_BC_TDESC_WORD1_DUM_Msk 0x80000000UL /*!< Dummy transfer (DUM) */ /* Bit field enums: */ typedef enum { MILSTD_BC_TDESC_WORD1_RTTO_14us = 0x0UL, /*!< RT Timeout 14us */ MILSTD_BC_TDESC_WORD1_RTTO_18us = 0x1UL, /*!< RT Timeout 18us */ MILSTD_BC_TDESC_WORD1_RTTO_22us = 0x2UL, /*!< RT Timeout 22us */ MILSTD_BC_TDESC_WORD1_RTTO_26us = 0x3UL, /*!< RT Timeout 26us */ MILSTD_BC_TDESC_WORD1_RTTO_30us = 0x4UL, /*!< RT Timeout 30us */ MILSTD_BC_TDESC_WORD1_RTTO_34us = 0x5UL, /*!< RT Timeout 34us */ MILSTD_BC_TDESC_WORD1_RTTO_38us = 0x6UL, /*!< RT Timeout 38us */ MILSTD_BC_TDESC_WORD1_RTTO_42us = 0x7UL, /*!< RT Timeout 42us */ MILSTD_BC_TDESC_WORD1_RTTO_46us = 0x8UL, /*!< RT Timeout 46us */ MILSTD_BC_TDESC_WORD1_RTTO_50us = 0x9UL, /*!< RT Timeout 50us */ MILSTD_BC_TDESC_WORD1_RTTO_54us = 0xAUL, /*!< RT Timeout 54us */ MILSTD_BC_TDESC_WORD1_RTTO_58us = 0xBUL, /*!< RT Timeout 58us */ MILSTD_BC_TDESC_WORD1_RTTO_62us = 0xCUL, /*!< RT Timeout 62us */ MILSTD_BC_TDESC_WORD1_RTTO_66us = 0xDUL, /*!< RT Timeout 66us */ MILSTD_BC_TDESC_WORD1_RTTO_70us = 0xEUL, /*!< RT Timeout 70us */ MILSTD_BC_TDESC_WORD1_RTTO_74us = 0xFUL, /*!< RT Timeout 74us */ } MILSTD_BC_TDESC_WORD1_RTTO_Enum; typedef enum { MILSTD_BC_TDESC_WORD1_BUS_A = 0x0UL, /*!< Bus to use for transfer - Bus A */ MILSTD_BC_TDESC_WORD1_BUS_B = 0x1UL, /*!< Bus to use for transfer - Bus B */ } MILSTD_BC_TDESC_WORD1_BUS_Enum; /*-- Milstd Transfer descriptor Result Word configure word --------------------------------*/ typedef struct { uint32_t TFRST :3; /*!< Transfer status (TFRST) - Outcome of last try */ uint32_t RES :1; /*!< Reserved - Mask away on read for forward compatibility */ uint32_t RETCNT :4; /*!< Retry count (RETCNT) - Number of retries performed */ uint32_t RTST :8; /*!< RT Status Bits (RTST) - Status bits from RT (transmitting RT in RT-to-RT transfer)*/ uint32_t RT2ST :8; /*!< RT 2 Status Bits (RT2ST) - Status bits from receiving RT in RT-to-RT transfer, otherwise 0 Same bit pattern as for RTST below */ uint32_t RESERVED :7; /*!< Reserved - Mask away on read for forward compatibility */ uint32_t ZERO :1; /*!< Always written as 0 */ } _MILSTD_BC_TDESC_RESULT_bits; /* Bit field positions: */ #define MILSTD_BC_TDESC_RESULT_TFRST_Pos 0 /*!< Transfer status (TFRST) - Outcome of last try */ #define MILSTD_BC_TDESC_RESULT_RETCNT_Pos 4 /*!< Retry count (RETCNT) - Number of retries performed */ #define MILSTD_BC_TDESC_RESULT_RTST_Pos 8 /*!< RT Status Bits (RTST) - Status bits from RT (transmitting RT in RT-to-RT transfer) */ #define MILSTD_BC_TDESC_RESULT_RT2ST_Pos 16 /*!< RT 2 Status Bits (RT2ST) - Status bits from receiving RT in RT-to-RT transfer */ #define MILSTD_BC_TDESC_RESULT_ZERO_Pos 31 /*!< Retry count (RETCNT) - Number of retries performed */ /* Bit field masks: */ #define MILSTD_BC_TDESC_RESULT_TFRST_Msk 0x00000007UL /*!< Transfer status (TFRST) - Outcome of last try */ #define MILSTD_BC_TDESC_RESULT_RETCNT_Msk 0x000000F0UL /*!< Retry count (RETCNT) - Number of retries performed */ #define MILSTD_BC_TDESC_RESULT_RTST_Msk 0x0000FF00UL /*!< RT Status Bits (RTST) - Status bits from RT (transmitting RT in RT-to-RT transfer) */ #define MILSTD_BC_TDESC_RESULT_RT2ST_Msk 0x00FF0000UL /*!< RT 2 Status Bits (RT2ST) - Status bits from receiving RT in RT-to-RT transfer */ #define MILSTD_BC_TDESC_RESULT_ZERO_Msk 0x80000000UL /*!< Retry count (RETCNT) - Number of retries performed */ /* Bit field enums: */ typedef enum { MILSTD_BC_TDESC_RESULT_TFRST_Success = 0x0UL, /*!< Success (or dummy bit was set) */ MILSTD_BC_TDESC_RESULT_TFRST_Trans_RT_NotRespond = 0x1UL, /*!< RT did not respond (transmitting RT in RT-to-RT transfer) */ MILSTD_BC_TDESC_RESULT_TFRST_Receiv_RT_NotRespond = 0x2UL, /*!< Receiving RT of RT-to-RT transfer did not respond */ MILSTD_BC_TDESC_RESULT_TFRST_StatusWordError = 0x3UL, /*!< A responding RT:s status word had message error, busy, instrumentation or reserved bit set (*) */ MILSTD_BC_TDESC_RESULT_TFRST_ProtocolError = 0x4UL, /*!< Protocol error (improperly timed data words, decoder error, wrong number of data words) */ MILSTD_BC_TDESC_RESULT_TFRST_TD_Invalid = 0x5UL, /*!< The transfer descriptor was invalid */ MILSTD_BC_TDESC_RESULT_TFRST_Error = 0x6UL, /*!< Data buffer DMA timeout or error response */ MILSTD_BC_TDESC_RESULT_TFRST_Aborted = 0x7UL, /*!< Transfer aborted due to loop back check failure */ } MILSTD_BC_TDESC_RESULT_TFRST_Enum; typedef enum { MILSTD_BC_TDESC_RESULT_RTST_TerminalFlag = 0x8UL, /*!< Terminal flag */ MILSTD_BC_TDESC_RESULT_RTST_DynamicBusCtrl = 0x9UL, /*!< Dynamic bus control acceptance */ MILSTD_BC_TDESC_RESULT_RTST_SubSystem = 0xAUL, /*!< Subsystem flag */ MILSTD_BC_TDESC_RESULT_RTST_Busy = 0xBUL, /*!< Busy bit */ MILSTD_BC_TDESC_RESULT_RTST_BroadcastCmd = 0xCUL, /*!< Broadcast command received */ MILSTD_BC_TDESC_RESULT_RTST_SrvReq = 0xDUL, /*!< Service request */ MILSTD_BC_TDESC_RESULT_RTST_InstrBit = 0xEUL, /*!< Instrumentation bit or reserved bit set */ MILSTD_BC_TDESC_RESULT_RTST_MsgError = 0xFUL, /*!< Message error */ } MILSTD_BC_TDESC_RESULT_RTST_Enum; /*-- Milstd BC Transfer descriptor structure --------------------------------------------------*/ typedef struct { union { __IO uint32_t WORD0; /*!< Milstd Transfer descriptor Word 0 configure word */ __IO _MILSTD_BC_TDESC_WORD0_bits WORD0_bit; /*!< Milstd Transfer descriptor Word 0 configure word: bit access */ }; union { __IO uint32_t WORD1; /*!< Milstd Transfer descriptor Word 1 configure word */ __IO _MILSTD_BC_TDESC_WORD1_bits WORD1_bit; /*!< Milstd Transfer descriptor Word 1 configure word: bit access */ }; __IO uint32_t DATA_BUF_PTR; /*!< Milstd Transfer descriptor Data buffer pointer, 16-bit aligned.*/ union { __IO uint32_t RESULT; /*!< Milstd Transfer descriptor Result Word configure word */ __IO _MILSTD_BC_TDESC_RESULT_bits RESULT_bit; /*!< Milstd Transfer descriptor Result Word configure word: bit access */ }; } MILSTD_BC_TDESC_TypeDef; /*-- Milstd branch condition Word Structure definition ----------------------------------*/ typedef struct { uint32_t STCC :8; /*!< Status Condition Code (STCC) - Mask with bits corresponding to status value of last transfer */ uint32_t RTCC :8; /*!< RT Condition Code (RTCC) - Mask with bits corresponding to RTST in result word of last transfer */ uint32_t RT2CC :8; /*!< RT 2 Condition Code (RT2CC) - Mask with bits corresponding to RT2ST in result word of last transfer */ uint32_t MODE :1; /*!< Logic mode (MODE) */ uint32_t ACT :1; /*!< Action (ACT) - What to do if condition is met, 0 - Suspend schedule, 1 - Jump */ uint32_t IRQC :1; /*!< Interrupt if condition met (IRQC) */ uint32_t RESERVED :4; /*!< Reserved - Set to 0 */ uint32_t ONE :1; /*!< Must be 1 to identify as branch */ } _MILSTD_BC_BR_CONDWORD_bits; /* Bit field positions: */ #define MILSTD_BC_BR_CONDWORD_STCC_Pos 0 /*!< Status Condition Code (STCC) - Mask with bits corresponding to status value of last transfer */ #define MILSTD_BC_BR_CONDWORD_RTCC_Pos 8 /*!< RT Condition Code (RTCC) - Mask with bits corresponding to RTST in result word of last transfer */ #define MILSTD_BC_BR_CONDWORD_RT2CC_Pos 16 /*!< RT 2 Condition Code (RT2CC) - Mask with bits corresponding to RT2ST in result word of last transfer */ #define MILSTD_BC_BR_CONDWORD_MODE_Pos 24 /*!< Logic mode (MODE) */ #define MILSTD_BC_BR_CONDWORD_ACT_Pos 25 /*!< Action (ACT) - What to do if condition is met, 0 - Suspend schedule, 1 - Jump */ #define MILSTD_BC_BR_CONDWORD_IRQC_Pos 26 /*!< Interrupt if condition met (IRQC) */ #define MILSTD_BC_BR_CONDWORD_ONE_Pos 31 /*!< Must be 1 to identify as branch */ /* Bit field masks: */ #define MILSTD_BC_BR_CONDWORD_STCC_Msk 0x00000007UL /*!< Status Condition Code (STCC) - Mask with bits corresponding to status value of last transfer */ #define MILSTD_BC_BR_CONDWORD_RTCC_Msk 0x000000F0UL /*!< RT Condition Code (RTCC) - Mask with bits corresponding to RTST in result word of last transfer */ #define MILSTD_BC_BR_CONDWORD_RT2CC_Msk 0x0000FF00UL /*!< RT 2 Condition Code (RT2CC) - Mask with bits corresponding to RT2ST in result word of last transfer */ #define MILSTD_BC_BR_CONDWORD_MODE_Msk 0x00FF0000UL /*!< Logic mode (MODE) */ #define MILSTD_BC_BR_CONDWORD_ACT_Msk 0x80000000UL /*!< Action (ACT) - What to do if condition is met, 0 - Suspend schedule, 1 - Jump */ #define MILSTD_BC_BR_CONDWORD_IRQC_Msk 0x00FF0000UL /*!< Interrupt if condition met (IRQC) */ #define MILSTD_BC_BR_CONDWORD_ONE_Msk 0x80000000UL /*!< Must be 1 to identify as branch */ /* Bit field enums: */ typedef enum { MILSTD_BC_BR_CONDWORD_MODE_Or = 0x0UL, /*!< Or mode (any bit set in RT2CC, RTCC is set in RT2ST,RTST, or result is in STCC mask) */ MILSTD_BC_BR_CONDWORD_MODE_And = 0x1UL, /*!< And mode (all bits set in RT2CC,RTCC are set in RT2ST,RTST and result is in STCC mask) */ } MILSTD_BC_BR_CONDWORD_MODE_Enum; /*-- Milstd BC Branch structure ----------------------------------*/ typedef struct { union { __IO uint32_t CONDWORD; /*!< Condition word */ __IO _MILSTD_BC_BR_CONDWORD_bits CONDWORD_bit; /*!< Condition word: bit access */ }; __IO uint32_t BRADDR; /*!< Branch address, 128-bit aligned */ __IO uint32_t RESERVED0; /*!< Reserved */ __IO uint32_t RESERVED1; /*!< Reserved */ } MILSTD_RTD_TypeDef; /*-- Milstd RT Subaddress table control word Structure definition ----------------------------------*/ typedef struct { uint32_t TXSZ :5; /*!< Maximum legal transmit size (TXSZ) from this subaddress - in 16-bit words, 0 means 32 */ uint32_t TXIRQ :1; /*!< Interrupt on transmit transfers (TXIRQ) - Each transmit transfer will cause an interrupt (only if TXEN,TXLOG=1) */ uint32_t TXLOG :1; /*!< Log transmit transfers (TXLOG) - Log all transmit transfers in event log ring (only if also TXEN=1) */ uint32_t TXEN :1; /*!< Transmit enable (TXEN) - Allow transmit transfers from this subaddress */ uint32_t RXSZ :5; /*!< Maximum legal receive size (RXSZ) from this subaddress - in 16-bit words, 0 means 32 */ uint32_t RXIRQ :1; /*!< Interrupt on receive transfers (RXIRQ) - Each receive transfer will cause an interrupt (only if RXEN,RXLOG=1) */ uint32_t RXLOG :1; /*!< Log receive transfers (RXLOG) - Log all receive transfers in event log ring (only if also RXEN=1) */ uint32_t RXEN :1; /*!< Receive enable (RXEN) - Allow receive transfers to this subaddress */ uint32_t BCRXE :1; /*!< Broadcast receive enable (BCRXEN) - Allow broadcast receive transfers to this subaddress */ uint32_t IGNDV :1; /*!< Ignore data valid bit (IGNDV) - If this is �1� then receive transfers will proceed (and overwrite the buffer) if the receive descriptor has the data valid bit set, instead of not responding to the request. This can be used for descriptor rings where you don�t care if the oldest data is overwritten. */ uint32_t WRAP :1; /*!< Auto-wraparound enable (WRAP) - Enables a test mode for this subaddress, where transmit transfers send back the last received data. This is done by copying the finished transfer�s descriptor pointer to the transmit descriptor pointer address after each successful transfer. Note: If WRAP=1, you should not set TXSZ > RXSZ as this might cause reading beyond buffer end */ uint32_t ZERO :13; /*!< Reserved - set to 0 for forward compatibility */ } _MILSTD_RT_SAT_CTRL_TypeDef; /* Bit field positions: */ #define MILSTD_RT_SAT_CTRL_TXSZ_Pos 0 /*!< Maximum legal transmit size (TXSZ) from this subaddress - in 16-bit words, 0 means 32 */ #define MILSTD_RT_SAT_CTRL_TXIRQ_Pos 5 /*!< Interrupt on transmit transfers (TXIRQ) - Each transmit transfer will cause an interrupt (only if TXEN,TXLOG=1) */ #define MILSTD_RT_SAT_CTRL_TXLOG_Pos 6 /*!< Log transmit transfers (TXLOG) - Log all transmit transfers in event log ring (only if also TXEN=1) */ #define MILSTD_RT_SAT_CTRL_TXEN_Pos 7 /*!< Transmit enable (TXEN) - Allow transmit transfers from this subaddress */ #define MILSTD_RT_SAT_CTRL_RXSZ_Pos 8 /*!< Maximum legal receive size (RXSZ) from this subaddress - in 16-bit words, 0 means 32 */ #define MILSTD_RT_SAT_CTRL_RXIRQ_Pos 13 /*!< Interrupt on receive transfers (RXIRQ) - Each receive transfer will cause an interrupt (only if RXEN,RXLOG=1) */ #define MILSTD_RT_SAT_CTRL_RXLOG_Pos 14 /*!< Log receive transfers (RXLOG) - Log all receive transfers in event log ring (only if also RXEN=1) */ #define MILSTD_RT_SAT_CTRL_RXEN_Pos 15 /*!< Receive enable (RXEN) - Allow receive transfers to this subaddress */ #define MILSTD_RT_SAT_CTRL_BCRXE_Pos 16 /*!< Broadcast receive enable (BCRXEN) - Allow broadcast receive transfers to this subaddress */ #define MILSTD_RT_SAT_CTRL_IGNDV_Pos 17 /*!< Ignore data valid bit (IGNDV) */ #define MILSTD_RT_SAT_CTRL_WRAP_Pos 18 /*!< Auto-wraparound enable (WRAP) */ #define MILSTD_RT_SAT_CTRL_ZERO_Pos 19 /*!< Reserved - set to 0 for forward compatibility */ /* Bit field masks: */ #define MILSTD_RT_SAT_CTRL_TXSZ_Msk 0x0000001FUL /*!< Maximum legal transmit size (TXSZ) from this subaddress - in 16-bit words, 0 means 32 */ #define MILSTD_RT_SAT_CTRL_TXIRQ_Msk 0x00000020UL /*!< Interrupt on transmit transfers (TXIRQ) - Each transmit transfer will cause an interrupt (only if TXEN,TXLOG=1) */ #define MILSTD_RT_SAT_CTRL_TXLOG_Msk 0x00000040UL /*!< Log transmit transfers (TXLOG) - Log all transmit transfers in event log ring (only if also TXEN=1) */ #define MILSTD_RT_SAT_CTRL_TXEN_Msk 0x00000080UL /*!< Transmit enable (TXEN) - Allow transmit transfers from this subaddress */ #define MILSTD_RT_SAT_CTRL_RXSZ_Msk 0x00001F00UL /*!< Maximum legal receive size (RXSZ) from this subaddress - in 16-bit words, 0 means 32 */ #define MILSTD_RT_SAT_CTRL_RXIRQ_Msk 0x00002000UL /*!< Interrupt on receive transfers (RXIRQ) - Each receive transfer will cause an interrupt (only if RXEN,RXLOG=1) */ #define MILSTD_RT_SAT_CTRL_RXLOG_Msk 0x00004000UL /*!< Log receive transfers (RXLOG) - Log all receive transfers in event log ring (only if also RXEN=1) */ #define MILSTD_RT_SAT_CTRL_RXEN_Msk 0x00008000UL /*!< Receive enable (RXEN) - Allow receive transfers to this subaddress */ #define MILSTD_RT_SAT_CTRL_BCRXE_Msk 0x00010000UL /*!< Broadcast receive enable (BCRXEN) - Allow broadcast receive transfers to this subaddress */ #define MILSTD_RT_SAT_CTRL_IGNDV_Msk 0x00020000UL /*!< Ignore data valid bit (IGNDV) */ #define MILSTD_RT_SAT_CTRL_WRAP_Msk 0x00040000UL /*!< Auto-wraparound enable (WRAP) */ #define MILSTD_RT_SAT_CTRL_ZERO_Msk 0xFFF80000UL /*`!< Reserved - set to 0 for forward compatibility */ /*-- Milstd RT SubAddress Table Structure definition ----------------------------------*/ typedef struct { union { __IO uint32_t CTRL; /*!< RT Subaddress table control word */ __IO _MILSTD_RT_SAT_CTRL_TypeDef CTRL_bit; /*!< RT Subaddress table control word: bit access */ }; __IO uint32_t TDSCR; /*!< Transmit descriptor pointer, 16-byte aligned (0x3 to indicate invalid pointer) */ __IO uint32_t RDSCR; /*!< Receive descriptor pointer, 16-byte aligned (0x3 to indicate invalid pointer) */ __IO uint32_t RESERVED; /*!< Reserved */ } MILSTD_RT_SAT_TypeDef; typedef struct { MILSTD_RT_SAT_TypeDef SAT[32]; /*!< RT Subaddress table array */ } MILSTD_RT_SAT_Arr_TypeDef; /*-- Milstd RT Event Log entry format Structure definition ----------------------------------*/ typedef struct { uint32_t TRES :3; /*!< Transfer result (TRES) */ uint32_t SZ :5; /*!< Transfer size (SZ) - Count in 16-bit words (0-32) */ uint32_t BC :1; /*!< Broadcast (BC) - Set to 1 if request was to the broadcast address */ uint32_t TIMEL :14; /*!< Low 14 bits of time tag counter */ uint32_t SAMC :5; /*!< Subaddress / Mode code (SAMC) - If TYPE=00/01 this is the transfer subaddress, If TYPE=10, this is the mode code */ uint32_t TYPE :2; /*!< Transfer type (TYPE) */ uint32_t IRQSR :1; /*!< IRQ Source (IRQSRC) - Set to �1� if this transfer caused an interrup */ } MILSTD_RT_LOG_TypeDef; /* Bit field positions: */ #define MILSTD_RT_LOG_TRES_Pos 0 /*!< Transfer result (TRES) */ #define MILSTD_RT_LOG_SZ_Pos 3 /*!< Transfer size (SZ) - Count in 16-bit words (0-32) */ #define MILSTD_RT_LOG_BC_Pos 9 /*!< Broadcast (BC) - Set to 1 if request was to the broadcast address */ #define MILSTD_RT_LOG_TIMEL_Pos 10 /*!< Low 14 bits of time tag counter */ #define MILSTD_RT_LOG_SAMC_Pos 24 /*!< Subaddress / Mode code (SAMC) */ #define MILSTD_RT_LOG_TYPE_Pos 29 /*!< Transfer type (TYPE) */ #define MILSTD_RT_LOG_IRQSR_Pos 31 /*!< IRQ Source (IRQSRC) - Set to �1� if this transfer caused an interrup */ /* Bit field masks: */ #define MILSTD_RT_LOG_TRES_Msk 0x00000003UL /*!< Transfer result (TRES) */ #define MILSTD_RT_LOG_SZ_Msk 0x000001FCUL /*!< Transfer size (SZ) - Count in 16-bit words (0-32) */ #define MILSTD_RT_LOG_BC_Msk 0x00000200UL /*!< Broadcast (BC) - Set to 1 if request was to the broadcast address */ #define MILSTD_RT_LOG_TIMEL_Msk 0x00FFFC00UL /*!< Low 14 bits of time tag counter */ #define MILSTD_RT_LOG_SAMC_Msk 0x1F000000UL /*!< Subaddress / Mode code (SAMC) */ #define MILSTD_RT_LOG_TYPE_Msk 0x60000000UL /*!< Transfer type (TYPE) */ #define MILSTD_RT_LOG_IRQSR_Msk 0x80000000UL /*!< IRQ Source (IRQSRC) - Set to �1� if this transfer caused an interrup */ /* Bit field enums: */ typedef enum { MILSTD_RT_LOG_TRES_Success = 0x0UL, /*!< Success */ MILSTD_RT_LOG_TRES_Superseded = 0x1UL, /*!< Superseded (canceled because a new command was given on the other bus) */ MILSTD_RT_LOG_TRES_DMAErr = 0x2UL, /*!< DMA error or memory timeout occurred */ MILSTD_RT_LOG_TRES_ProtocolErr = 0x3UL, /*!< Protocol error (improperly timed data words or decoder error) */ MILSTD_RT_LOG_TRES_MsgErr = 0x4UL, /*!< The busy bit or message error bit was set in the transmitted status word and no data was sent */ MILSTD_RT_LOG_TRES_Aborted = 0x5UL, /*!< Transfer aborted due to loop back checker error */ } MILSTD_RT_LOG_TRES_Enum; typedef enum { MILSTD_RT_LOG_TYPE_TxData = 0x0UL, /*!< Transmit data */ MILSTD_RT_LOG_TYPE_RxData = 0x1UL, /*!< Receive data */ MILSTD_RT_LOG_TYPE_ModeCode = 0x2UL, /*!< Mode code */ } MILSTD_RT_LOG_TYPE_Enum; /*-- Milstd RT Descriptor control/status word Structure definition ----------------------------------*/ typedef struct { uint32_t TRES :3; /*!< Transfer result (TRES) 000 = Success 001 = Superseded (canceled because a new command was given on the other bus) 010 = DMA error or memory timeout occurred 011 = Protocol error (improperly timed data words or decoder error) 100 = The busy bit or message error bit was set in the transmitted status word and no data was sent 101 = Transfer aborted due to loop back checker error */ uint32_t SZ :5; /*!< Transfer size (SZ) - Count in 16-bit words (0-32) */ uint32_t BC :1; /*!< Broadcast (BC) - Set by the core if the transfer was a broadcast transfer */ uint32_t TIME :16; /*!< Transmission time tag (TTIME) - Set by the core to the value of the RT timer when the transfer finished. */ uint32_t RESERVED :4; /*!< Reserved - Write 0 and mask out on read for forward compatibility */ uint32_t IRQEN :1; /*!< IRQ Enable override (IRQEN) - Log and IRQ after transfer regardless of SA control word settings Can be used for getting an interrupt when nearing the end of a descriptor list. */ uint32_t DV :1; /*!< Data valid (DV) - Should be set to 0 by software before and set to 1 by hardware after transfer. If DV=1 in the current receive descriptor before the receive transfer begins then a descriptor table error will be triggered. You can override this by setting the IGNDV bit in the subaddress table. */ } _MILSTD_RT_DESC_CTRLSTAT_TypeDef; /* Bit field positions: */ #define MILSTD_RT_DESC_CTRLSTAT_TRES_Pos 0 /*!< Transfer result (TRES) */ #define MILSTD_RT_DESC_CTRLSTAT_SZ_Pos 3 /*!< Transfer size (SZ) - Count in 16-bit words (0-32) */ #define MILSTD_RT_DESC_CTRLSTAT_BC_Pos 9 /*!< Broadcast (BC) - Set by the core if the transfer was a broadcast transfer */ #define MILSTD_RT_DESC_CTRLSTAT_TIME_Pos 10 /*!< Transmission time tag (TTIME) - Set by the core to the value of the RT timer when the transfer finished. */ #define MILSTD_RT_DESC_CTRLSTAT_IRQEN_Pos 30 /*!< IRQ Enable override (IRQEN) */ #define MILSTD_RT_DESC_CTRLSTAT_DV_Pos 31 /*!< Data valid (DV) */ /* Bit field masks: */ #define MILSTD_RT_DESC_CTRLSTAT_TRES_Msk 0x00000003UL /*!< Transfer result (TRES) */ #define MILSTD_RT_DESC_CTRLSTAT_SZ_Msk 0x000001FCUL /*!< Transfer size (SZ) - Count in 16-bit words (0-32) */ #define MILSTD_RT_DESC_CTRLSTAT_BC_Msk 0x00000200UL /*!< Broadcast (BC) - Set by the core if the transfer was a broadcast transfer */ #define MILSTD_RT_DESC_CTRLSTAT_TIME_Msk 0x03FFFC00UL /*!< Transmission time tag (TTIME) - Set by the core to the value of the RT timer when the transfer finished. */ #define MILSTD_RT_DESC_CTRLSTAT_IRQEN_Msk 0x40000000UL /*!< IRQ Enable override (IRQEN) */ #define MILSTD_RT_DESC_CTRLSTAT_DV_Msk 0x80000000UL /*!< Data valid (DV) */ /* Bit field enums: */ typedef enum { MILSTD_RT_DESC_CTRLSTAT_TRES_Success = 0x0UL, /*!< Success */ MILSTD_RT_DESC_CTRLSTAT_TRES_Superseded = 0x1UL, /*!< Superseded (canceled because a new command was given on the other bus) */ MILSTD_RT_DESC_CTRLSTAT_TRES_DMAErr = 0x2UL, /*!< DMA error or memory timeout occurred */ MILSTD_RT_DESC_CTRLSTAT_TRES_ProtocolErr = 0x3UL, /*!< Protocol error (improperly timed data words or decoder error) */ MILSTD_RT_DESC_CTRLSTAT_TRES_MsgErr = 0x4UL, /*!< The busy bit or message error bit was set in the transmitted status word and no data was sent */ MILSTD_RT_DESC_CTRLSTAT_TRES_Aborted = 0x5UL, /*!< Transfer aborted due to loop back checker error */ } MILSTD_RT_DESC_CTRLSTAT_TRES_Enum; /*-- Milstd RT Descriptor format Structure definition ----------------------------------*/ typedef struct { union { __IO uint32_t CTRLSTAT; /*!< Control and status word */ __IO _MILSTD_RT_DESC_CTRLSTAT_TypeDef CTRLSTAT_bit; /*!< Control and status word: bit access */ }; __IO uint32_t DBUFF_PTR; /*!< Data buffer pointer, 16-bit aligned */ __IO uint32_t NEXT_DESCR_PTR; /*!< Pointer to next descriptor, 16-byte aligned or 0x0000003 to indicate end of list */ } MILSTD_RT_DESC_TypeDef; /*-- Milstd BM Log entry word 0 Structure definition ----------------------------------*/ typedef struct { uint32_t TIME :24; /*!< Time tag (TIME) */ uint32_t RESERVED :7; /*!< Reserved - Mask out on read for forward compatibility */ uint32_t ONE :1; /*!< Always written as 1 */ } _BM_LOG_WORD0_TypeDef; /* Bit field positions: */ #define MILSTD_BM_LOG_WORD0_TIME_Pos 0 /*!< Time tag (TIME) */ #define MILSTD_BM_LOG_WORD0_ONE_Pos 31 /*!< Always written as 1 */ /* Bit field masks: */ #define MILSTD_BM_LOG_WORD0_TIME_Msk 0x00FFFFFUL /*!< Time tag (TIME) */ #define MILSTD_BM_LOG_WORD0_ONE_Msk 0x8000000UL /*!< Always written as 1 */ /*-- Milstd BM Log entry word 1 Structure definition ----------------------------------*/ typedef struct { uint32_t WD :16; /*!< Word data (WD) */ uint32_t WTP :1; /*!< Word type (WTP) */ uint32_t WST :2; /*!< Word status (WST) - 00=word OK, 01=Manchester error, 10=Parity error */ uint32_t BUS :1; /*!< Receive data bus (BUS) - 0:A, 1:B */ uint32_t RESERVED :11; /*!< Reserved - Mask out on read for forward compatibility */ uint32_t ZERO :1; /*!< Always written as 0 */ } _BM_LOG_WORD1_TypeDef; /* Bit field positions: */ #define MILSTD_BM_LOG_WORD1_WD_Pos 0 /*!< Word data (WD)*/ #define MILSTD_BM_LOG_WORD1_WTP_Pos 16 /*!< Word type (WTP) */ #define MILSTD_BM_LOG_WORD1_WST_Pos 17 /*!< Word status (WST) */ #define MILSTD_BM_LOG_WORD1_BUS_Pos 19 /*!< Receive data bus (BUS) */ #define MILSTD_BM_LOG_WORD1_ZERO_Pos 31 /*!< Always written as 0 */ /* Bit field masks: */ #define MILSTD_BM_LOG_WORD1_WD_Msk 0x0000FFFFUL /*!< Word data (WD)*/ #define MILSTD_BM_LOG_WORD1_WTP_Msk 0x00010000UL /*!< Word type (WTP) */ #define MILSTD_BM_LOG_WORD1_WST_Msk 0x00060000UL /*!< Word status (WST) */ #define MILSTD_BM_LOG_WORD1_BUS_Msk 0x00080000UL /*!< Receive data bus (BUS) */ #define MILSTD_BM_LOG_WORD1_ZERO_Msk 0x80000000UL /*!< Always written as 0 */ /* Bit field enums: */ typedef enum { MILSTD_BM_LOG_WORD1_WTP_Data = 0x0UL, /*!< Data */ MILSTD_BM_LOG_WORD1_WTP_CmdStatus = 0x1UL /*!< Command/status */ } MILSTD_BM_LOG_WORD1_WTP_Enum; typedef enum { MILSTD_BM_LOG_WORD1_WST_OK = 0x0UL, /*!< Word OK */ MILSTD_BM_LOG_WORD1_WST_ManchErr = 0x1UL, /*!< Manchester error */ MILSTD_BM_LOG_WORD1_WST_ParityErr = 0x2UL /*!< Parity error */ } MILSTD_BM_LOG_WORD1_WST_Enum; typedef enum { MILSTD_BM_LOG_WORD1_BUS_A = 0x0UL, /*!< Bus to use for transfer - Bus A */ MILSTD_BM_LOG_WORD1_BUS_B = 0x1UL, /*!< Bus to use for transfer - Bus B */ } MILSTD_BM_LOG_WORD1_BUS_Enum; typedef struct { union { __IO uint32_t WORD0; /*!< BM Log entry word 0 */ __IO _BM_LOG_WORD0_TypeDef WORD0_bit; /*!< BM Log entry word 0: bit access */ }; union { __IO uint32_t WORD1; /*!< BM Log entry word 1 */ __IO _BM_LOG_WORD1_TypeDef WORD1_bit; /*!< BM Log entry word 1: bit access */ }; } MILSTD_BM_LOG_TypeDef; /******************************************************************************/ /* RCU registers */ /******************************************************************************/ /*-- PLLCFG: PLL Configuration Register ----------------------------------------------------------------------*/ typedef struct { uint32_t FBDIV :12; /*!< PLL FBDIV Coefficient */ uint32_t DIV1 :3; /*!< Output DIV1 coefficient */ uint32_t :1; /*!< RESERVED */ uint32_t DIV2 :3; /*!< Output DIV2 coefficient */ uint32_t :1; /*!< RESERVED */ uint32_t REFDIV :6; /*!< PLL reference clock divider */ uint32_t PD :1; /*!< PLL PowerDown enable bit */ uint32_t LOCK :1; /*!< Lock status of stable PLL output clock */ uint32_t OUTDIS :1; /*!< Disable PLL output clock */ uint32_t BP :1; /*!< Bypass PLL reference clock */ uint32_t REFSRC :2; /*!< Reference clock source */ } _RCU_PLLCFG_bits; /* Bit field positions: */ #define RCU_PLLCFG_FBDIV_Pos 0 /*!< PLL FBDIV Coefficient */ #define RCU_PLLCFG_DIV1_Pos 12 /*!< Output DIV1 coefficient */ #define RCU_PLLCFG_DIV2_Pos 16 /*!< Output DIV2 coefficient */ #define RCU_PLLCFG_REFDIV_Pos 20 /*!< PLL reference clock divider */ #define RCU_PLLCFG_PD_Pos 26 /*!< PLL PowerDown enable bit */ #define RCU_PLLCFG_LOCK_Pos 27 /*!< Lock status of stable PLL output clock */ #define RCU_PLLCFG_OUTDIS_Pos 28 /*!< Disable PLL output clock */ #define RCU_PLLCFG_BP_Pos 29 /*!< Bypass PLL reference clock */ #define RCU_PLLCFG_REFSRC_Pos 30 /*!< Reference clock source */ /* Bit field masks: */ #define RCU_PLLCFG_FBDIV_Msk 0x00000FFFUL /*!< PLL FBDIV Coefficient */ #define RCU_PLLCFG_DIV1_Msk 0x00007000UL /*!< Output DIV1 coefficient */ #define RCU_PLLCFG_DIV2_Msk 0x00070000UL /*!< Output DIV2 coefficient */ #define RCU_PLLCFG_REFDIV_Msk 0x03F00000UL /*!< PLL reference clock divider */ #define RCU_PLLCFG_PD_Msk 0x04000000UL /*!< PLL PowerDown enable bit */ #define RCU_PLLCFG_LOCK_Msk 0x08000000UL /*!< Lock status of stable PLL output clock */ #define RCU_PLLCFG_OUTDIS_Msk 0x10000000UL /*!< Disable PLL output clock */ #define RCU_PLLCFG_BP_Msk 0x20000000UL /*!< Bypass PLL reference clock */ #define RCU_PLLCFG_REFSRC_Msk 0xC0000000UL /*!< Reference clock source */ /* Bit field enums: */ typedef enum { RCU_PLLCFG_REFSRC_OSECLK = 0x0UL, /*!< external oscillator */ RCU_PLLCFG_REFSRC_OSICLK = 0x1UL, /*!< internal oscillator */ RCU_PLLCFG_REFSRC_PLLEXTCLK = 0x2UL, /*!< external PLL clock source */ } RCU_PLLCFG_REFSRC_Enum; /*-- PLLDIV: PLL Divider Register ----------------------------------------------------------------------------*/ typedef struct { uint32_t DIVEN :1; /*!< PLL Divider enable bit */ uint32_t :7; /*!< RESERVED */ uint32_t DIV :6; /*!< PLL divider coefficent */ } _RCU_PLLDIV_bits; /* Bit field positions: */ #define RCU_PLLDIV_DIVEN_Pos 0 /*!< PLL Divider enable bit */ #define RCU_PLLDIV_DIV_Pos 8 /*!< PLL divider coefficent */ /* Bit field masks: */ #define RCU_PLLDIV_DIVEN_Msk 0x00000001UL /*!< PLL Divider enable bit */ #define RCU_PLLDIV_DIV_Msk 0x00003F00UL /*!< PLL divider coefficent */ /*-- SYSCLKCFG: System Clock Configuration Register ----------------------------------------------------------*/ typedef struct { uint32_t SYSSEL :2; /*!< System clock source selection */ uint32_t :14; /*!< RESERVED */ uint32_t SECEN :1; /*!< Enable clock security system */ } _RCU_SYSCLKCFG_bits; /* Bit field positions: */ #define RCU_SYSCLKCFG_SYSSEL_Pos 0 /*!< System clock source selection */ #define RCU_SYSCLKCFG_SECEN_Pos 16 /*!< Enable clock security system */ /* Bit field masks: */ #define RCU_SYSCLKCFG_SYSSEL_Msk 0x00000003UL /*!< System clock source selection */ #define RCU_SYSCLKCFG_SECEN_Msk 0x00010000UL /*!< Enable clock security system */ /* Bit field enums: */ typedef enum { RCU_SYSCLKCFG_SYSSEL_REFCLK = 0x0UL, /*!< reference clock */ RCU_SYSCLKCFG_SYSSEL_SRCCLK = 0x1UL, /*!< additional clock source */ RCU_SYSCLKCFG_SYSSEL_PLLCLK = 0x2UL, /*!< PLL output clock */ RCU_SYSCLKCFG_SYSSEL_PLLDIVCLK = 0x3UL, /*!< PLL divided clock */ } RCU_SYSCLKCFG_SYSSEL_Enum; /*-- SYSCLKSTAT: System Clock Status Register ----------------------------------------------------------------*/ typedef struct { uint32_t SYSSTAT :2; /*!< Current system clock source */ uint32_t :2; /*!< RESERVED */ uint32_t BUSY :1; /*!< Clock manager is busy, for example, when change clock source */ uint32_t :3; /*!< RESERVED */ uint32_t SYSFAIL :1; /*!< Error in current clock was detected */ uint32_t :8; /*!< RESERVED */ uint32_t SRCCLKERR :1; /*!< Additional clock source fail */ uint32_t PLLCLKERR :1; /*!< PLL clock fail */ uint32_t PLLDIVCLKERR :1; /*!< PLL divided clock fail */ uint32_t :5; /*!< RESERVED */ uint32_t SRCCLKOK :1; /*!< Additional clock source good */ uint32_t PLLCLKOK :1; /*!< PLL clock good */ uint32_t PLLDIVCLKOK :1; /*!< PLL divided clock good */ } _RCU_SYSCLKSTAT_bits; /* Bit field positions: */ #define RCU_SYSCLKSTAT_SYSSTAT_Pos 0 /*!< Current system clock source */ #define RCU_SYSCLKSTAT_BUSY_Pos 4 /*!< Clock manager is busy, for example, when change clock source */ #define RCU_SYSCLKSTAT_SYSFAIL_Pos 8 /*!< Error in current clock was detected */ #define RCU_SYSCLKSTAT_SRCCLKERR_Pos 17 /*!< Additional clock source fail */ #define RCU_SYSCLKSTAT_PLLCLKERR_Pos 18 /*!< PLL clock fail */ #define RCU_SYSCLKSTAT_PLLDIVCLKERR_Pos 19 /*!< PLL divided clock fail */ #define RCU_SYSCLKSTAT_SRCCLKOK_Pos 25 /*!< Additional clock source good */ #define RCU_SYSCLKSTAT_PLLCLKOK_Pos 26 /*!< PLL clock good */ #define RCU_SYSCLKSTAT_PLLDIVCLKOK_Pos 27 /*!< PLL divided clock good */ /* Bit field masks: */ #define RCU_SYSCLKSTAT_SYSSTAT_Msk 0x00000003UL /*!< Current system clock source */ #define RCU_SYSCLKSTAT_BUSY_Msk 0x00000010UL /*!< Clock manager is busy, for example, when change clock source */ #define RCU_SYSCLKSTAT_SYSFAIL_Msk 0x00000100UL /*!< Error in current clock was detected */ #define RCU_SYSCLKSTAT_SRCCLKERR_Msk 0x00020000UL /*!< Additional clock source fail */ #define RCU_SYSCLKSTAT_PLLCLKERR_Msk 0x00040000UL /*!< PLL clock fail */ #define RCU_SYSCLKSTAT_PLLDIVCLKERR_Msk 0x00080000UL /*!< PLL divided clock fail */ #define RCU_SYSCLKSTAT_SRCCLKOK_Msk 0x02000000UL /*!< Additional clock source good */ #define RCU_SYSCLKSTAT_PLLCLKOK_Msk 0x04000000UL /*!< PLL clock good */ #define RCU_SYSCLKSTAT_PLLDIVCLKOK_Msk 0x08000000UL /*!< PLL divided clock good */ /* Bit field enums: */ typedef enum { RCU_SYSCLKSTAT_SYSSTAT_REFCLK = 0x0UL, /*!< reference clock */ RCU_SYSCLKSTAT_SYSSTAT_SRCCLK = 0x1UL, /*!< additional clock source */ RCU_SYSCLKSTAT_SYSSTAT_PLLCLK = 0x2UL, /*!< PLL output clock */ RCU_SYSCLKSTAT_SYSSTAT_PLLDIVCLK = 0x3UL, /*!< PLL divided clock */ } RCU_SYSCLKSTAT_SYSSTAT_Enum; /*-- SECPRD: Security Sysytem Clock Period Register 0 --------------------------------------------------------*/ typedef struct { uint32_t :8; /*!< RESERVED */ uint32_t SRCCLK :8; /*!< Additional clock source max counter value for fail detection */ uint32_t PLLCLK :8; /*!< Clock source 2 max counter value for clock fail detection */ uint32_t PLLDIVCLK :8; /*!< Clock source 3 max counter value for clock fail detection */ } _RCU_SECPRD_bits; /* Bit field positions: */ #define RCU_SECPRD_SRCCLK_Pos 8 /*!< Additional clock source max counter value for fail detection */ #define RCU_SECPRD_PLLCLK_Pos 16 /*!< Clock source 2 max counter value for clock fail detection */ #define RCU_SECPRD_PLLDIVCLK_Pos 24 /*!< Clock source 3 max counter value for clock fail detection */ /* Bit field masks: */ #define RCU_SECPRD_SRCCLK_Msk 0x0000FF00UL /*!< Additional clock source max counter value for fail detection */ #define RCU_SECPRD_PLLCLK_Msk 0x00FF0000UL /*!< Clock source 2 max counter value for clock fail detection */ #define RCU_SECPRD_PLLDIVCLK_Msk 0xFF000000UL /*!< Clock source 3 max counter value for clock fail detection */ /*-- SYSRSTCFG: System Reset Configuration Register ----------------------------------------------------------*/ typedef struct { uint32_t LOCKUPEN :1; /*!< Enable reset when processor in LOCKUP state */ } _RCU_SYSRSTCFG_bits; /* Bit field positions: */ #define RCU_SYSRSTCFG_LOCKUPEN_Pos 0 /*!< Enable reset when processor in LOCKUP state */ /* Bit field masks: */ #define RCU_SYSRSTCFG_LOCKUPEN_Msk 0x00000001UL /*!< Enable reset when processor in LOCKUP state */ /*-- SYSRSTSTAT: Reset Status Register -----------------------------------------------------------------------*/ typedef struct { uint32_t POR :1; /*!< PowerOn Reset status */ uint32_t WDOG :1; /*!< WatchDog Reset status */ uint32_t SYSRST :1; /*!< System Reset Status */ uint32_t LOCKUP :1; /*!< Lockup Reset Status */ } _RCU_SYSRSTSTAT_bits; /* Bit field positions: */ #define RCU_SYSRSTSTAT_POR_Pos 0 /*!< PowerOn Reset status */ #define RCU_SYSRSTSTAT_WDOG_Pos 1 /*!< WatchDog Reset status */ #define RCU_SYSRSTSTAT_SYSRST_Pos 2 /*!< System Reset Status */ #define RCU_SYSRSTSTAT_LOCKUP_Pos 3 /*!< Lockup Reset Status */ /* Bit field masks: */ #define RCU_SYSRSTSTAT_POR_Msk 0x00000001UL /*!< PowerOn Reset status */ #define RCU_SYSRSTSTAT_WDOG_Msk 0x00000002UL /*!< WatchDog Reset status */ #define RCU_SYSRSTSTAT_SYSRST_Msk 0x00000004UL /*!< System Reset Status */ #define RCU_SYSRSTSTAT_LOCKUP_Msk 0x00000008UL /*!< Lockup Reset Status */ /*-- INTEN: Interrupt Enable Register ------------------------------------------------------------------------*/ typedef struct { uint32_t :1; /*!< RESERVED */ uint32_t SRCCLKERR :1; /*!< Enable SRCCLK fail interrupt */ uint32_t PLLCLKERR :1; /*!< Enable PLLCLK fail interrupt */ uint32_t PLLDIVCLKERR :1; /*!< Enable PLLDIVCLK fail interrupt */ uint32_t :5; /*!< RESERVED */ uint32_t SRCCLKOK :1; /*!< Enable SRCCLK good interrupt */ uint32_t PLLCLKOK :1; /*!< Enable PLLCLK good interrupt */ uint32_t PLLDIVCLKOK :1; /*!< Enable PLLDIVCLK good interrupt */ uint32_t :4; /*!< RESERVED */ uint32_t PLLLOCK :1; /*!< Enable int from pll lock signal */ } _RCU_INTEN_bits; /* Bit field positions: */ #define RCU_INTEN_SRCCLKERR_Pos 1 /*!< Enable SRCCLK fail interrupt */ #define RCU_INTEN_PLLCLKERR_Pos 2 /*!< Enable PLLCLK fail interrupt */ #define RCU_INTEN_PLLDIVCLKERR_Pos 3 /*!< Enable PLLDIVCLK fail interrupt */ #define RCU_INTEN_SRCCLKOK_Pos 9 /*!< Enable SRCCLK good interrupt */ #define RCU_INTEN_PLLCLKOK_Pos 10 /*!< Enable PLLCLK good interrupt */ #define RCU_INTEN_PLLDIVCLKOK_Pos 11 /*!< Enable PLLDIVCLK good interrupt */ #define RCU_INTEN_PLLLOCK_Pos 16 /*!< Enable int from pll lock signal */ /* Bit field masks: */ #define RCU_INTEN_SRCCLKERR_Msk 0x00000002UL /*!< Enable SRCCLK fail interrupt */ #define RCU_INTEN_PLLCLKERR_Msk 0x00000004UL /*!< Enable PLLCLK fail interrupt */ #define RCU_INTEN_PLLDIVCLKERR_Msk 0x00000008UL /*!< Enable PLLDIVCLK fail interrupt */ #define RCU_INTEN_SRCCLKOK_Msk 0x00000200UL /*!< Enable SRCCLK good interrupt */ #define RCU_INTEN_PLLCLKOK_Msk 0x00000400UL /*!< Enable PLLCLK good interrupt */ #define RCU_INTEN_PLLDIVCLKOK_Msk 0x00000800UL /*!< Enable PLLDIVCLK good interrupt */ #define RCU_INTEN_PLLLOCK_Msk 0x00010000UL /*!< Enable int from pll lock signal */ /*-- INTSTAT: Interrupt Status Register ----------------------------------------------------------------------*/ typedef struct { uint32_t :1; /*!< RESERVED */ uint32_t SRCCLKERR :1; /*!< Status SRCCLK fail */ uint32_t PLLCLKERR :1; /*!< Status PLLCLK fail */ uint32_t PLLDIVCLKERR :1; /*!< Status PLLDIVCLK fail */ uint32_t :5; /*!< RESERVED */ uint32_t SRCCLKOK :1; /*!< Status SRCCLK good */ uint32_t PLLCLKOK :1; /*!< Status PLLCLK good */ uint32_t PLLDIVCLKOK :1; /*!< Status PLLDIVCLK good */ uint32_t :4; /*!< RESERVED */ uint32_t PLLLOCK :1; /*!< Status pll lock signal */ uint32_t :3; /*!< RESERVED */ uint32_t SYSFAIL :1; /*!< SYSCLK fail status */ } _RCU_INTSTAT_bits; /* Bit field positions: */ #define RCU_INTSTAT_SRCCLKERR_Pos 1 /*!< Status SRCCLK fail */ #define RCU_INTSTAT_PLLCLKERR_Pos 2 /*!< Status PLLCLK fail */ #define RCU_INTSTAT_PLLDIVCLKERR_Pos 3 /*!< Status PLLDIVCLK fail */ #define RCU_INTSTAT_SRCCLKOK_Pos 9 /*!< Status SRCCLK good */ #define RCU_INTSTAT_PLLCLKOK_Pos 10 /*!< Status PLLCLK good */ #define RCU_INTSTAT_PLLDIVCLKOK_Pos 11 /*!< Status PLLDIVCLK good */ #define RCU_INTSTAT_PLLLOCK_Pos 16 /*!< Status pll lock signal */ #define RCU_INTSTAT_SYSFAIL_Pos 20 /*!< SYSCLK fail status */ /* Bit field masks: */ #define RCU_INTSTAT_SRCCLKERR_Msk 0x00000002UL /*!< Status SRCCLK fail */ #define RCU_INTSTAT_PLLCLKERR_Msk 0x00000004UL /*!< Status PLLCLK fail */ #define RCU_INTSTAT_PLLDIVCLKERR_Msk 0x00000008UL /*!< Status PLLDIVCLK fail */ #define RCU_INTSTAT_SRCCLKOK_Msk 0x00000200UL /*!< Status SRCCLK good */ #define RCU_INTSTAT_PLLCLKOK_Msk 0x00000400UL /*!< Status PLLCLK good */ #define RCU_INTSTAT_PLLDIVCLKOK_Msk 0x00000800UL /*!< Status PLLDIVCLK good */ #define RCU_INTSTAT_PLLLOCK_Msk 0x00010000UL /*!< Status pll lock signal */ #define RCU_INTSTAT_SYSFAIL_Msk 0x00100000UL /*!< SYSCLK fail status */ /*-- TRACECFG: Trace Clock Configuration Register ------------------------------------------------------------*/ typedef struct { uint32_t CLKEN :1; /*!< Clock enable */ uint32_t :7; /*!< RESERVED */ uint32_t CLKSEL :2; /*!< Clock source select */ uint32_t :6; /*!< RESERVED */ uint32_t DIVEN :1; /*!< Enable divider */ uint32_t :7; /*!< RESERVED */ uint32_t DIVN :6; /*!< Divider coefficient */ } _RCU_TRACECFG_bits; /* Bit field positions: */ #define RCU_TRACECFG_CLKEN_Pos 0 /*!< Clock enable */ #define RCU_TRACECFG_CLKSEL_Pos 8 /*!< Clock source select */ #define RCU_TRACECFG_DIVEN_Pos 16 /*!< Enable divider */ #define RCU_TRACECFG_DIVN_Pos 24 /*!< Divider coefficient */ /* Bit field masks: */ #define RCU_TRACECFG_CLKEN_Msk 0x00000001UL /*!< Clock enable */ #define RCU_TRACECFG_CLKSEL_Msk 0x00000300UL /*!< Clock source select */ #define RCU_TRACECFG_DIVEN_Msk 0x00010000UL /*!< Enable divider */ #define RCU_TRACECFG_DIVN_Msk 0x3F000000UL /*!< Divider coefficient */ /* Bit field enums: */ typedef enum { RCU_TRACECFG_CLKSEL_REFCLK = 0x0UL, /*!< reference clock */ RCU_TRACECFG_CLKSEL_SRCCLK = 0x1UL, /*!< additional clock source */ RCU_TRACECFG_CLKSEL_SYSCLK = 0x2UL, /*!< System clock */ RCU_TRACECFG_CLKSEL_TRACEEXTCLK = 0x3UL, /*!< Trace external clock */ } RCU_TRACECFG_CLKSEL_Enum; /*-- CLKOUTCFG: Clockout Configuration Register --------------------------------------------------------------*/ typedef struct { uint32_t CLKEN :1; /*!< Clock enable */ uint32_t :7; /*!< RESERVED */ uint32_t CLKSEL :2; /*!< Clock source select */ uint32_t :6; /*!< RESERVED */ uint32_t DIVEN :1; /*!< Enable divider */ uint32_t :7; /*!< RESERVED */ uint32_t DIVN :3; /*!< Divider coefficient */ } _RCU_CLKOUTCFG_bits; /* Bit field positions: */ #define RCU_CLKOUTCFG_CLKEN_Pos 0 /*!< Clock enable */ #define RCU_CLKOUTCFG_CLKSEL_Pos 8 /*!< Clock source select */ #define RCU_CLKOUTCFG_DIVEN_Pos 16 /*!< Enable divider */ #define RCU_CLKOUTCFG_DIVN_Pos 24 /*!< Divider coefficient */ /* Bit field masks: */ #define RCU_CLKOUTCFG_CLKEN_Msk 0x00000001UL /*!< Clock enable */ #define RCU_CLKOUTCFG_CLKSEL_Msk 0x00000300UL /*!< Clock source select */ #define RCU_CLKOUTCFG_DIVEN_Msk 0x00010000UL /*!< Enable divider */ #define RCU_CLKOUTCFG_DIVN_Msk 0x07000000UL /*!< Divider coefficient */ /* Bit field enums: */ typedef enum { RCU_CLKOUTCFG_CLKSEL_REFCLK = 0x0UL, /*!< reference clock */ RCU_CLKOUTCFG_CLKSEL_SRCCLK = 0x1UL, /*!< additional clock source */ RCU_CLKOUTCFG_CLKSEL_SYSCLK = 0x2UL, /*!< System clock */ RCU_CLKOUTCFG_CLKSEL_PLLCLK = 0x3UL, /*!< PLL output clock */ } RCU_CLKOUTCFG_CLKSEL_Enum; /*-- WDTCFG: WatchDog Configuration Register -----------------------------------------------------------------*/ typedef struct { uint32_t CLKEN :1; /*!< Clock enable */ uint32_t :3; /*!< RESERVED */ uint32_t RSTDIS :1; /*!< Reset disable */ uint32_t :3; /*!< RESERVED */ uint32_t CLKSEL :2; /*!< Clock source select */ uint32_t :6; /*!< RESERVED */ uint32_t DIVEN :1; /*!< Enable divider */ uint32_t :7; /*!< RESERVED */ uint32_t DIVN :6; /*!< Divider coefficient */ } _RCU_WDTCFG_bits; /* Bit field positions: */ #define RCU_WDTCFG_CLKEN_Pos 0 /*!< Clock enable */ #define RCU_WDTCFG_RSTDIS_Pos 4 /*!< Reset disable */ #define RCU_WDTCFG_CLKSEL_Pos 8 /*!< Clock source select */ #define RCU_WDTCFG_DIVEN_Pos 16 /*!< Enable divider */ #define RCU_WDTCFG_DIVN_Pos 24 /*!< Divider coefficient */ /* Bit field masks: */ #define RCU_WDTCFG_CLKEN_Msk 0x00000001UL /*!< Clock enable */ #define RCU_WDTCFG_RSTDIS_Msk 0x00000010UL /*!< Reset disable */ #define RCU_WDTCFG_CLKSEL_Msk 0x00000300UL /*!< Clock source select */ #define RCU_WDTCFG_DIVEN_Msk 0x00010000UL /*!< Enable divider */ #define RCU_WDTCFG_DIVN_Msk 0x3F000000UL /*!< Divider coefficient */ /* Bit field enums: */ typedef enum { RCU_WDTCFG_CLKSEL_REFCLK = 0x0UL, /*!< reference clock */ RCU_WDTCFG_CLKSEL_SRCCLK = 0x1UL, /*!< additional clock source */ RCU_WDTCFG_CLKSEL_SYSCLK = 0x2UL, /*!< System clock */ RCU_WDTCFG_CLKSEL_PLLCLK = 0x3UL, /*!< PLL output clock */ } RCU_WDTCFG_CLKSEL_Enum; /*-- MILSTDCFG: MILSTDCFG: MILSTD Codec Clock and Reset Configuration Register --------------------------------*/ typedef struct { uint32_t CLKEN :1; /*!< Clock enable */ uint32_t :3; /*!< RESERVED */ uint32_t RSTDIS :1; /*!< Reset disable */ uint32_t :3; /*!< RESERVED */ uint32_t CLKSEL :2; /*!< Clock source select */ uint32_t :6; /*!< RESERVED */ uint32_t DIVEN :1; /*!< Enable divider */ uint32_t :7; /*!< RESERVED */ uint32_t DIVN :6; /*!< Divider coefficient */ } _RCU_MILSTDCFG_MILSTDCFG_bits; /* Bit field positions: */ #define RCU_MILSTDCFG_MILSTDCFG_CLKEN_Pos 0 /*!< Clock enable */ #define RCU_MILSTDCFG_MILSTDCFG_RSTDIS_Pos 4 /*!< Reset disable */ #define RCU_MILSTDCFG_MILSTDCFG_CLKSEL_Pos 8 /*!< Clock source select */ #define RCU_MILSTDCFG_MILSTDCFG_DIVEN_Pos 16 /*!< Enable divider */ #define RCU_MILSTDCFG_MILSTDCFG_DIVN_Pos 24 /*!< Divider coefficient */ /* Bit field masks: */ #define RCU_MILSTDCFG_MILSTDCFG_CLKEN_Msk 0x00000001UL /*!< Clock enable */ #define RCU_MILSTDCFG_MILSTDCFG_RSTDIS_Msk 0x00000010UL /*!< Reset disable */ #define RCU_MILSTDCFG_MILSTDCFG_CLKSEL_Msk 0x00000300UL /*!< Clock source select */ #define RCU_MILSTDCFG_MILSTDCFG_DIVEN_Msk 0x00010000UL /*!< Enable divider */ #define RCU_MILSTDCFG_MILSTDCFG_DIVN_Msk 0x3F000000UL /*!< Divider coefficient */ /* Bit field enums: */ typedef enum { RCU_MILSTDCFG_MILSTDCFG_CLKSEL_OSECLK = 0x0UL, /*!< external oscillator */ RCU_MILSTDCFG_MILSTDCFG_CLKSEL_PLLCLK = 0x1UL, /*!< PLL output clock */ RCU_MILSTDCFG_MILSTDCFG_CLKSEL_PLLDIVCLK = 0x2UL, /*!< PLL divided clock */ RCU_MILSTDCFG_MILSTDCFG_CLKSEL_PLLEXTCLK = 0x3UL, /*!< external PLL clock source */ } RCU_MILSTDCFG_MILSTDCFG_CLKSEL_Enum; /*-- SPWRCFG: SPWRCFG: SPWR TX Clock Configuration Register ---------------------------------------------------*/ typedef struct { uint32_t CLKEN :1; /*!< Clock enable */ uint32_t :15; /*!< RESERVED */ uint32_t DIVEN :1; /*!< Enable divider */ uint32_t :7; /*!< RESERVED */ uint32_t DIVN :6; /*!< Divider coefficient */ } _RCU_SPWRCFG_SPWRCFG_bits; /* Bit field positions: */ #define RCU_SPWRCFG_SPWRCFG_CLKEN_Pos 0 /*!< Clock enable */ #define RCU_SPWRCFG_SPWRCFG_DIVEN_Pos 16 /*!< Enable divider */ #define RCU_SPWRCFG_SPWRCFG_DIVN_Pos 24 /*!< Divider coefficient */ /* Bit field masks: */ #define RCU_SPWRCFG_SPWRCFG_CLKEN_Msk 0x00000001UL /*!< Clock enable */ #define RCU_SPWRCFG_SPWRCFG_DIVEN_Msk 0x00010000UL /*!< Enable divider */ #define RCU_SPWRCFG_SPWRCFG_DIVN_Msk 0x3F000000UL /*!< Divider coefficient */ /*-- UARTCFG: UARTCFG: UART Clock and Reset Configuration Register --------------------------------------------*/ typedef struct { uint32_t CLKEN :1; /*!< Clock enable */ uint32_t :3; /*!< RESERVED */ uint32_t RSTDIS :1; /*!< Reset disable */ uint32_t :3; /*!< RESERVED */ uint32_t CLKSEL :2; /*!< Clock source select */ uint32_t :6; /*!< RESERVED */ uint32_t DIVEN :1; /*!< Enable divider */ uint32_t :7; /*!< RESERVED */ uint32_t DIVN :6; /*!< Divider coefficient */ } _RCU_UARTCFG_UARTCFG_bits; /* Bit field positions: */ #define RCU_UARTCFG_UARTCFG_CLKEN_Pos 0 /*!< Clock enable */ #define RCU_UARTCFG_UARTCFG_RSTDIS_Pos 4 /*!< Reset disable */ #define RCU_UARTCFG_UARTCFG_CLKSEL_Pos 8 /*!< Clock source select */ #define RCU_UARTCFG_UARTCFG_DIVEN_Pos 16 /*!< Enable divider */ #define RCU_UARTCFG_UARTCFG_DIVN_Pos 24 /*!< Divider coefficient */ /* Bit field masks: */ #define RCU_UARTCFG_UARTCFG_CLKEN_Msk 0x00000001UL /*!< Clock enable */ #define RCU_UARTCFG_UARTCFG_RSTDIS_Msk 0x00000010UL /*!< Reset disable */ #define RCU_UARTCFG_UARTCFG_CLKSEL_Msk 0x00000300UL /*!< Clock source select */ #define RCU_UARTCFG_UARTCFG_DIVEN_Msk 0x00010000UL /*!< Enable divider */ #define RCU_UARTCFG_UARTCFG_DIVN_Msk 0x3F000000UL /*!< Divider coefficient */ /* Bit field enums: */ typedef enum { RCU_UARTCFG_UARTCFG_CLKSEL_OSECLK = 0x0UL, /*!< external oscillator */ RCU_UARTCFG_UARTCFG_CLKSEL_PLLCLK = 0x1UL, /*!< PLL output clock */ RCU_UARTCFG_UARTCFG_CLKSEL_PLLDIVCLK = 0x2UL, /*!< PLL divided clock */ RCU_UARTCFG_UARTCFG_CLKSEL_PLLEXTCLK = 0x3UL, /*!< external PLL clock source */ } RCU_UARTCFG_UARTCFG_CLKSEL_Enum; /*-- SPICFG: SPICFG: SPI Clock and Reset Configuration Register -----------------------------------------------*/ typedef struct { uint32_t CLKEN :1; /*!< Clock enable */ uint32_t :3; /*!< RESERVED */ uint32_t RSTDIS :1; /*!< Reset disable */ uint32_t :3; /*!< RESERVED */ uint32_t CLKSEL :2; /*!< Clock source select */ uint32_t :6; /*!< RESERVED */ uint32_t DIVEN :1; /*!< Enable divider */ uint32_t :7; /*!< RESERVED */ uint32_t DIVN :6; /*!< Divider coefficient */ } _RCU_SPICFG_SPICFG_bits; /* Bit field positions: */ #define RCU_SPICFG_SPICFG_CLKEN_Pos 0 /*!< Clock enable */ #define RCU_SPICFG_SPICFG_RSTDIS_Pos 4 /*!< Reset disable */ #define RCU_SPICFG_SPICFG_CLKSEL_Pos 8 /*!< Clock source select */ #define RCU_SPICFG_SPICFG_DIVEN_Pos 16 /*!< Enable divider */ #define RCU_SPICFG_SPICFG_DIVN_Pos 24 /*!< Divider coefficient */ /* Bit field masks: */ #define RCU_SPICFG_SPICFG_CLKEN_Msk 0x00000001UL /*!< Clock enable */ #define RCU_SPICFG_SPICFG_RSTDIS_Msk 0x00000010UL /*!< Reset disable */ #define RCU_SPICFG_SPICFG_CLKSEL_Msk 0x00000300UL /*!< Clock source select */ #define RCU_SPICFG_SPICFG_DIVEN_Msk 0x00010000UL /*!< Enable divider */ #define RCU_SPICFG_SPICFG_DIVN_Msk 0x3F000000UL /*!< Divider coefficient */ /* Bit field enums: */ typedef enum { RCU_SPICFG_SPICFG_CLKSEL_OSECLK = 0x0UL, /*!< external oscillator */ RCU_SPICFG_SPICFG_CLKSEL_PLLCLK = 0x1UL, /*!< PLL output clock */ RCU_SPICFG_SPICFG_CLKSEL_PLLDIVCLK = 0x2UL, /*!< PLL divided clock */ RCU_SPICFG_SPICFG_CLKSEL_PLLEXTCLK = 0x3UL, /*!< external PLL clock source */ } RCU_SPICFG_SPICFG_CLKSEL_Enum; /*-- ADCCFG: ADC Clock and Reset Configuration Register ------------------------------------------------------*/ typedef struct { uint32_t CLKEN :1; /*!< Clock enable */ uint32_t :3; /*!< RESERVED */ uint32_t RSTDIS :1; /*!< Reset disable */ uint32_t :3; /*!< RESERVED */ uint32_t CLKSEL :2; /*!< Clock source select */ uint32_t :6; /*!< RESERVED */ uint32_t DIVEN :1; /*!< Enable divider */ uint32_t :7; /*!< RESERVED */ uint32_t DIVN :6; /*!< Divider coefficient */ } _RCU_ADCCFG_bits; /* Bit field positions: */ #define RCU_ADCCFG_CLKEN_Pos 0 /*!< Clock enable */ #define RCU_ADCCFG_RSTDIS_Pos 4 /*!< Reset disable */ #define RCU_ADCCFG_CLKSEL_Pos 8 /*!< Clock source select */ #define RCU_ADCCFG_DIVEN_Pos 16 /*!< Enable divider */ #define RCU_ADCCFG_DIVN_Pos 24 /*!< Divider coefficient */ /* Bit field masks: */ #define RCU_ADCCFG_CLKEN_Msk 0x00000001UL /*!< Clock enable */ #define RCU_ADCCFG_RSTDIS_Msk 0x00000010UL /*!< Reset disable */ #define RCU_ADCCFG_CLKSEL_Msk 0x00000300UL /*!< Clock source select */ #define RCU_ADCCFG_DIVEN_Msk 0x00010000UL /*!< Enable divider */ #define RCU_ADCCFG_DIVN_Msk 0x3F000000UL /*!< Divider coefficient */ /* Bit field enums: */ typedef enum { RCU_ADCCFG_CLKSEL_OSECLK = 0x0UL, /*!< external oscillator */ RCU_ADCCFG_CLKSEL_PLLCLK = 0x1UL, /*!< PLL output clock */ RCU_ADCCFG_CLKSEL_PLLDIVCLK = 0x2UL, /*!< PLL divided clock */ RCU_ADCCFG_CLKSEL_PLLEXTCLK = 0x3UL, /*!< external PLL clock source */ } RCU_ADCCFG_CLKSEL_Enum; /*-- APBCFG: APB Clock Configuraton Register -----------------------------------------------------------------*/ typedef struct { uint32_t DIV :2; /*!< Divider coefficent */ } _RCU_APBCFG_bits; /* Bit field positions: */ #define RCU_APBCFG_DIV_Pos 0 /*!< Divider coefficent */ /* Bit field masks: */ #define RCU_APBCFG_DIV_Msk 0x00000003UL /*!< Divider coefficent */ /* Bit field enums: */ typedef enum { RCU_APBCFG_DIV_None = 0x0UL, /*!< no divide */ RCU_APBCFG_DIV_DIV2 = 0x1UL, /*!< divide by 2 */ RCU_APBCFG_DIV_DIV4 = 0x2UL, /*!< divide by 4 */ RCU_APBCFG_DIV_DIV8 = 0x3UL, /*!< divide by 8 */ } RCU_APBCFG_DIV_Enum; /*-- PCLKCFG0: APB Clock Configuration Register 0 ------------------------------------------------------------*/ typedef struct { uint32_t :9; /*!< RESERVED */ uint32_t TUART0EN :1; /*!< TUART0 clock enable */ uint32_t TUART1EN :1; /*!< TUART1 clock enable */ uint32_t I2C0EN :1; /*!< I2C0 clock enable */ uint32_t I2C1EN :1; /*!< I2C1 clock enable */ uint32_t :4; /*!< RESERVED */ uint32_t TMR0EN :1; /*!< TMR0 clock enable */ uint32_t TMR1EN :1; /*!< TMR1 clock enable */ uint32_t TMR2EN :1; /*!< TMR2 clock enable */ uint32_t TMR3EN :1; /*!< TMR3 clock enable */ uint32_t ETMR0EN :1; /*!< ETMR0 clock enable */ uint32_t ETMR1EN :1; /*!< ETMR1 clock enable */ uint32_t ETMR2EN :1; /*!< ETMR2 clock enable */ uint32_t ETMR3EN :1; /*!< ETMR3 clock enable */ uint32_t RTCEN :1; /*!< RTC clock enable */ uint32_t ECAP0EN :1; /*!< CAP0 clock enable */ uint32_t ECAP1EN :1; /*!< CAP1 clock enable */ uint32_t ECAP2EN :1; /*!< CAP2 clock enable */ uint32_t ECAP3EN :1; /*!< CAP3 clock enable */ uint32_t ECAP4EN :1; /*!< CAP4 clock enable */ uint32_t ECAP5EN :1; /*!< CAP5 clock enable */ } _RCU_PCLKCFG0_bits; /* Bit field positions: */ #define RCU_PCLKCFG0_TUART0EN_Pos 9 /*!< TUART0 clock enable */ #define RCU_PCLKCFG0_TUART1EN_Pos 10 /*!< TUART1 clock enable */ #define RCU_PCLKCFG0_I2C0EN_Pos 11 /*!< I2C0 clock enable */ #define RCU_PCLKCFG0_I2C1EN_Pos 12 /*!< I2C1 clock enable */ #define RCU_PCLKCFG0_TMR0EN_Pos 17 /*!< TMR0 clock enable */ #define RCU_PCLKCFG0_TMR1EN_Pos 18 /*!< TMR1 clock enable */ #define RCU_PCLKCFG0_TMR2EN_Pos 19 /*!< TMR2 clock enable */ #define RCU_PCLKCFG0_TMR3EN_Pos 20 /*!< TMR3 clock enable */ #define RCU_PCLKCFG0_ETMR0EN_Pos 21 /*!< ETMR0 clock enable */ #define RCU_PCLKCFG0_ETMR1EN_Pos 22 /*!< ETMR1 clock enable */ #define RCU_PCLKCFG0_ETMR2EN_Pos 23 /*!< ETMR2 clock enable */ #define RCU_PCLKCFG0_ETMR3EN_Pos 24 /*!< ETMR3 clock enable */ #define RCU_PCLKCFG0_RTCEN_Pos 25 /*!< RTC clock enable */ #define RCU_PCLKCFG0_ECAP0EN_Pos 26 /*!< CAP0 clock enable */ #define RCU_PCLKCFG0_ECAP1EN_Pos 27 /*!< CAP1 clock enable */ #define RCU_PCLKCFG0_ECAP2EN_Pos 28 /*!< CAP2 clock enable */ #define RCU_PCLKCFG0_ECAP3EN_Pos 29 /*!< CAP3 clock enable */ #define RCU_PCLKCFG0_ECAP4EN_Pos 30 /*!< CAP4 clock enable */ #define RCU_PCLKCFG0_ECAP5EN_Pos 31 /*!< CAP5 clock enable */ /* Bit field masks: */ #define RCU_PCLKCFG0_TUART0EN_Msk 0x00000200UL /*!< TUART0 clock enable */ #define RCU_PCLKCFG0_TUART1EN_Msk 0x00000400UL /*!< TUART1 clock enable */ #define RCU_PCLKCFG0_I2C0EN_Msk 0x00000800UL /*!< I2C0 clock enable */ #define RCU_PCLKCFG0_I2C1EN_Msk 0x00001000UL /*!< I2C1 clock enable */ #define RCU_PCLKCFG0_TMR0EN_Msk 0x00020000UL /*!< TMR0 clock enable */ #define RCU_PCLKCFG0_TMR1EN_Msk 0x00040000UL /*!< TMR1 clock enable */ #define RCU_PCLKCFG0_TMR2EN_Msk 0x00080000UL /*!< TMR2 clock enable */ #define RCU_PCLKCFG0_TMR3EN_Msk 0x00100000UL /*!< TMR3 clock enable */ #define RCU_PCLKCFG0_ETMR0EN_Msk 0x00200000UL /*!< ETMR0 clock enable */ #define RCU_PCLKCFG0_ETMR1EN_Msk 0x00400000UL /*!< ETMR1 clock enable */ #define RCU_PCLKCFG0_ETMR2EN_Msk 0x00800000UL /*!< ETMR2 clock enable */ #define RCU_PCLKCFG0_ETMR3EN_Msk 0x01000000UL /*!< ETMR3 clock enable */ #define RCU_PCLKCFG0_RTCEN_Msk 0x02000000UL /*!< RTC clock enable */ #define RCU_PCLKCFG0_ECAP0EN_Msk 0x04000000UL /*!< CAP0 clock enable */ #define RCU_PCLKCFG0_ECAP1EN_Msk 0x08000000UL /*!< CAP1 clock enable */ #define RCU_PCLKCFG0_ECAP2EN_Msk 0x10000000UL /*!< CAP2 clock enable */ #define RCU_PCLKCFG0_ECAP3EN_Msk 0x20000000UL /*!< CAP3 clock enable */ #define RCU_PCLKCFG0_ECAP4EN_Msk 0x40000000UL /*!< CAP4 clock enable */ #define RCU_PCLKCFG0_ECAP5EN_Msk 0x80000000UL /*!< CAP5 clock enable */ /*-- PCLKCFG1: APB Clock Configuration Register 1 ------------------------------------------------------------*/ typedef struct { uint32_t PWM0EN :1; /*!< PWM0 clock enable */ uint32_t PWM1EN :1; /*!< PWM1 clock enable */ uint32_t PWM2EN :1; /*!< PWM2 clock enable */ uint32_t PWM3EN :1; /*!< PWM3 clock enable */ uint32_t PWM4EN :1; /*!< PWM4 clock enable */ uint32_t PWM5EN :1; /*!< PWM5 clock enable */ uint32_t PWM6EN :1; /*!< PWM6 clock enable */ uint32_t PWM7EN :1; /*!< PWM7 clock enable */ uint32_t PWM8EN :1; /*!< PWM8 clock enable */ uint32_t PWM9EN :1; /*!< PWM9 clock enable */ uint32_t QEP0EN :1; /*!< QEP0 clock enable */ uint32_t QEP1EN :1; /*!< QEP1 clock enable */ uint32_t QEP2EN :1; /*!< QEP2 clock enable */ uint32_t QEP3EN :1; /*!< QEP3 clock enable */ uint32_t LAUEN :1; /*!< LAU clock enable */ uint32_t OWI0EN :1; /*!< OWI0 clock enable */ uint32_t OWI1EN :1; /*!< OWI1 clock enable */ } _RCU_PCLKCFG1_bits; /* Bit field positions: */ #define RCU_PCLKCFG1_PWM0EN_Pos 0 /*!< PWM0 clock enable */ #define RCU_PCLKCFG1_PWM1EN_Pos 1 /*!< PWM1 clock enable */ #define RCU_PCLKCFG1_PWM2EN_Pos 2 /*!< PWM2 clock enable */ #define RCU_PCLKCFG1_PWM3EN_Pos 3 /*!< PWM3 clock enable */ #define RCU_PCLKCFG1_PWM4EN_Pos 4 /*!< PWM4 clock enable */ #define RCU_PCLKCFG1_PWM5EN_Pos 5 /*!< PWM5 clock enable */ #define RCU_PCLKCFG1_PWM6EN_Pos 6 /*!< PWM6 clock enable */ #define RCU_PCLKCFG1_PWM7EN_Pos 7 /*!< PWM7 clock enable */ #define RCU_PCLKCFG1_PWM8EN_Pos 8 /*!< PWM8 clock enable */ #define RCU_PCLKCFG1_PWM9EN_Pos 9 /*!< PWM9 clock enable */ #define RCU_PCLKCFG1_QEP0EN_Pos 10 /*!< QEP0 clock enable */ #define RCU_PCLKCFG1_QEP1EN_Pos 11 /*!< QEP1 clock enable */ #define RCU_PCLKCFG1_QEP2EN_Pos 12 /*!< QEP2 clock enable */ #define RCU_PCLKCFG1_QEP3EN_Pos 13 /*!< QEP3 clock enable */ #define RCU_PCLKCFG1_LAUEN_Pos 14 /*!< LAU clock enable */ #define RCU_PCLKCFG1_OWI0EN_Pos 15 /*!< OWI0 clock enable */ #define RCU_PCLKCFG1_OWI1EN_Pos 16 /*!< OWI1 clock enable */ /* Bit field masks: */ #define RCU_PCLKCFG1_PWM0EN_Msk 0x00000001UL /*!< PWM0 clock enable */ #define RCU_PCLKCFG1_PWM1EN_Msk 0x00000002UL /*!< PWM1 clock enable */ #define RCU_PCLKCFG1_PWM2EN_Msk 0x00000004UL /*!< PWM2 clock enable */ #define RCU_PCLKCFG1_PWM3EN_Msk 0x00000008UL /*!< PWM3 clock enable */ #define RCU_PCLKCFG1_PWM4EN_Msk 0x00000010UL /*!< PWM4 clock enable */ #define RCU_PCLKCFG1_PWM5EN_Msk 0x00000020UL /*!< PWM5 clock enable */ #define RCU_PCLKCFG1_PWM6EN_Msk 0x00000040UL /*!< PWM6 clock enable */ #define RCU_PCLKCFG1_PWM7EN_Msk 0x00000080UL /*!< PWM7 clock enable */ #define RCU_PCLKCFG1_PWM8EN_Msk 0x00000100UL /*!< PWM8 clock enable */ #define RCU_PCLKCFG1_PWM9EN_Msk 0x00000200UL /*!< PWM9 clock enable */ #define RCU_PCLKCFG1_QEP0EN_Msk 0x00000400UL /*!< QEP0 clock enable */ #define RCU_PCLKCFG1_QEP1EN_Msk 0x00000800UL /*!< QEP1 clock enable */ #define RCU_PCLKCFG1_QEP2EN_Msk 0x00001000UL /*!< QEP2 clock enable */ #define RCU_PCLKCFG1_QEP3EN_Msk 0x00002000UL /*!< QEP3 clock enable */ #define RCU_PCLKCFG1_LAUEN_Msk 0x00004000UL /*!< LAU clock enable */ #define RCU_PCLKCFG1_OWI0EN_Msk 0x00008000UL /*!< OWI0 clock enable */ #define RCU_PCLKCFG1_OWI1EN_Msk 0x00010000UL /*!< OWI1 clock enable */ /*-- PRSTCFG0: APB Reset Configuration Register 0 ------------------------------------------------------------*/ typedef struct { uint32_t :9; /*!< RESERVED */ uint32_t TUART0EN :1; /*!< TUART0 reset disable */ uint32_t TUART1EN :1; /*!< TUART1 reset disable */ uint32_t I2C0EN :1; /*!< I2C0 reset disable */ uint32_t I2C1EN :1; /*!< I2C1 reset disable */ uint32_t :4; /*!< RESERVED */ uint32_t TMR0EN :1; /*!< TMR0 reset disable */ uint32_t TMR1EN :1; /*!< TMR1 reset disable */ uint32_t TMR2EN :1; /*!< TMR2 reset disable */ uint32_t TMR3EN :1; /*!< TMR3 reset disable */ uint32_t ETMR0EN :1; /*!< ETMR0 reset disable */ uint32_t ETMR1EN :1; /*!< ETMR1 reset disable */ uint32_t ETMR2EN :1; /*!< ETMR2 reset disable */ uint32_t ETMR3EN :1; /*!< ETMR3 reset disable */ uint32_t RTCEN :1; /*!< RTC reset disable */ uint32_t ECAP0EN :1; /*!< CAP0 reset disable */ uint32_t ECAP1EN :1; /*!< CAP1 reset disable */ uint32_t ECAP2EN :1; /*!< CAP2 reset disable */ uint32_t ECAP3EN :1; /*!< CAP3 reset disable */ uint32_t ECAP4EN :1; /*!< CAP4 reset disable */ uint32_t ECAP5EN :1; /*!< CAP5 reset disable */ } _RCU_PRSTCFG0_bits; /* Bit field positions: */ #define RCU_PRSTCFG0_TUART0EN_Pos 9 /*!< TUART0 reset disable */ #define RCU_PRSTCFG0_TUART1EN_Pos 10 /*!< TUART1 reset disable */ #define RCU_PRSTCFG0_I2C0EN_Pos 11 /*!< I2C0 reset disable */ #define RCU_PRSTCFG0_I2C1EN_Pos 12 /*!< I2C1 reset disable */ #define RCU_PRSTCFG0_TMR0EN_Pos 17 /*!< TMR0 reset disable */ #define RCU_PRSTCFG0_TMR1EN_Pos 18 /*!< TMR1 reset disable */ #define RCU_PRSTCFG0_TMR2EN_Pos 19 /*!< TMR2 reset disable */ #define RCU_PRSTCFG0_TMR3EN_Pos 20 /*!< TMR3 reset disable */ #define RCU_PRSTCFG0_ETMR0EN_Pos 21 /*!< ETMR0 reset disable */ #define RCU_PRSTCFG0_ETMR1EN_Pos 22 /*!< ETMR1 reset disable */ #define RCU_PRSTCFG0_ETMR2EN_Pos 23 /*!< ETMR2 reset disable */ #define RCU_PRSTCFG0_ETMR3EN_Pos 24 /*!< ETMR3 reset disable */ #define RCU_PRSTCFG0_RTCEN_Pos 25 /*!< RTC reset disable */ #define RCU_PRSTCFG0_ECAP0EN_Pos 26 /*!< CAP0 reset disable */ #define RCU_PRSTCFG0_ECAP1EN_Pos 27 /*!< CAP1 reset disable */ #define RCU_PRSTCFG0_ECAP2EN_Pos 28 /*!< CAP2 reset disable */ #define RCU_PRSTCFG0_ECAP3EN_Pos 29 /*!< CAP3 reset disable */ #define RCU_PRSTCFG0_ECAP4EN_Pos 30 /*!< CAP4 reset disable */ #define RCU_PRSTCFG0_ECAP5EN_Pos 31 /*!< CAP5 reset disable */ /* Bit field masks: */ #define RCU_PRSTCFG0_TUART0EN_Msk 0x00000200UL /*!< TUART0 reset disable */ #define RCU_PRSTCFG0_TUART1EN_Msk 0x00000400UL /*!< TUART1 reset disable */ #define RCU_PRSTCFG0_I2C0EN_Msk 0x00000800UL /*!< I2C0 reset disable */ #define RCU_PRSTCFG0_I2C1EN_Msk 0x00001000UL /*!< I2C1 reset disable */ #define RCU_PRSTCFG0_TMR0EN_Msk 0x00020000UL /*!< TMR0 reset disable */ #define RCU_PRSTCFG0_TMR1EN_Msk 0x00040000UL /*!< TMR1 reset disable */ #define RCU_PRSTCFG0_TMR2EN_Msk 0x00080000UL /*!< TMR2 reset disable */ #define RCU_PRSTCFG0_TMR3EN_Msk 0x00100000UL /*!< TMR3 reset disable */ #define RCU_PRSTCFG0_ETMR0EN_Msk 0x00200000UL /*!< ETMR0 reset disable */ #define RCU_PRSTCFG0_ETMR1EN_Msk 0x00400000UL /*!< ETMR1 reset disable */ #define RCU_PRSTCFG0_ETMR2EN_Msk 0x00800000UL /*!< ETMR2 reset disable */ #define RCU_PRSTCFG0_ETMR3EN_Msk 0x01000000UL /*!< ETMR3 reset disable */ #define RCU_PRSTCFG0_RTCEN_Msk 0x02000000UL /*!< RTC reset disable */ #define RCU_PRSTCFG0_ECAP0EN_Msk 0x04000000UL /*!< CAP0 reset disable */ #define RCU_PRSTCFG0_ECAP1EN_Msk 0x08000000UL /*!< CAP1 reset disable */ #define RCU_PRSTCFG0_ECAP2EN_Msk 0x10000000UL /*!< CAP2 reset disable */ #define RCU_PRSTCFG0_ECAP3EN_Msk 0x20000000UL /*!< CAP3 reset disable */ #define RCU_PRSTCFG0_ECAP4EN_Msk 0x40000000UL /*!< CAP4 reset disable */ #define RCU_PRSTCFG0_ECAP5EN_Msk 0x80000000UL /*!< CAP5 reset disable */ /*-- PRSTCFG1: APB Reset Configuration Register 1 ------------------------------------------------------------*/ typedef struct { uint32_t PWM0EN :1; /*!< PWM0 reset disable */ uint32_t PWM1EN :1; /*!< PWM1 reset disable */ uint32_t PWM2EN :1; /*!< PWM2 reset disable */ uint32_t PWM3EN :1; /*!< PWM3 reset disable */ uint32_t PWM4EN :1; /*!< PWM4 reset disable */ uint32_t PWM5EN :1; /*!< PWM5 reset disable */ uint32_t PWM6EN :1; /*!< PWM6 reset disable */ uint32_t PWM7EN :1; /*!< PWM7 reset disable */ uint32_t PWM8EN :1; /*!< PWM8 reset disable */ uint32_t PWM9EN :1; /*!< PWM9 reset disable */ uint32_t QEP0EN :1; /*!< QEP0 reset disable */ uint32_t QEP1EN :1; /*!< QEP1 reset disable */ uint32_t QEP2EN :1; /*!< QEP2 reset disable */ uint32_t QEP3EN :1; /*!< QEP3 reset disable */ uint32_t LAUEN :1; /*!< LAU reset disable */ uint32_t OWI0EN :1; /*!< OWI0 reset disable */ uint32_t OWI1EN :1; /*!< OWI1 reset disable */ } _RCU_PRSTCFG1_bits; /* Bit field positions: */ #define RCU_PRSTCFG1_PWM0EN_Pos 0 /*!< PWM0 reset disable */ #define RCU_PRSTCFG1_PWM1EN_Pos 1 /*!< PWM1 reset disable */ #define RCU_PRSTCFG1_PWM2EN_Pos 2 /*!< PWM2 reset disable */ #define RCU_PRSTCFG1_PWM3EN_Pos 3 /*!< PWM3 reset disable */ #define RCU_PRSTCFG1_PWM4EN_Pos 4 /*!< PWM4 reset disable */ #define RCU_PRSTCFG1_PWM5EN_Pos 5 /*!< PWM5 reset disable */ #define RCU_PRSTCFG1_PWM6EN_Pos 6 /*!< PWM6 reset disable */ #define RCU_PRSTCFG1_PWM7EN_Pos 7 /*!< PWM7 reset disable */ #define RCU_PRSTCFG1_PWM8EN_Pos 8 /*!< PWM8 reset disable */ #define RCU_PRSTCFG1_PWM9EN_Pos 9 /*!< PWM9 reset disable */ #define RCU_PRSTCFG1_QEP0EN_Pos 10 /*!< QEP0 reset disable */ #define RCU_PRSTCFG1_QEP1EN_Pos 11 /*!< QEP1 reset disable */ #define RCU_PRSTCFG1_QEP2EN_Pos 12 /*!< QEP2 reset disable */ #define RCU_PRSTCFG1_QEP3EN_Pos 13 /*!< QEP3 reset disable */ #define RCU_PRSTCFG1_LAUEN_Pos 14 /*!< LAU reset disable */ #define RCU_PRSTCFG1_OWI0EN_Pos 15 /*!< OWI0 reset disable */ #define RCU_PRSTCFG1_OWI1EN_Pos 16 /*!< OWI1 reset disable */ /* Bit field masks: */ #define RCU_PRSTCFG1_PWM0EN_Msk 0x00000001UL /*!< PWM0 reset disable */ #define RCU_PRSTCFG1_PWM1EN_Msk 0x00000002UL /*!< PWM1 reset disable */ #define RCU_PRSTCFG1_PWM2EN_Msk 0x00000004UL /*!< PWM2 reset disable */ #define RCU_PRSTCFG1_PWM3EN_Msk 0x00000008UL /*!< PWM3 reset disable */ #define RCU_PRSTCFG1_PWM4EN_Msk 0x00000010UL /*!< PWM4 reset disable */ #define RCU_PRSTCFG1_PWM5EN_Msk 0x00000020UL /*!< PWM5 reset disable */ #define RCU_PRSTCFG1_PWM6EN_Msk 0x00000040UL /*!< PWM6 reset disable */ #define RCU_PRSTCFG1_PWM7EN_Msk 0x00000080UL /*!< PWM7 reset disable */ #define RCU_PRSTCFG1_PWM8EN_Msk 0x00000100UL /*!< PWM8 reset disable */ #define RCU_PRSTCFG1_PWM9EN_Msk 0x00000200UL /*!< PWM9 reset disable */ #define RCU_PRSTCFG1_QEP0EN_Msk 0x00000400UL /*!< QEP0 reset disable */ #define RCU_PRSTCFG1_QEP1EN_Msk 0x00000800UL /*!< QEP1 reset disable */ #define RCU_PRSTCFG1_QEP2EN_Msk 0x00001000UL /*!< QEP2 reset disable */ #define RCU_PRSTCFG1_QEP3EN_Msk 0x00002000UL /*!< QEP3 reset disable */ #define RCU_PRSTCFG1_LAUEN_Msk 0x00004000UL /*!< LAU reset disable */ #define RCU_PRSTCFG1_OWI0EN_Msk 0x00008000UL /*!< OWI0 reset disable */ #define RCU_PRSTCFG1_OWI1EN_Msk 0x00010000UL /*!< OWI1 reset disable */ /*-- HCLKCFG: AHB Clock Configuration Register ---------------------------------------------------------------*/ typedef struct { uint32_t GPIOAEN :1; /*!< Enable clock for GPIOA port */ uint32_t GPIOBEN :1; /*!< Enable clock for GPIOB port */ uint32_t GPIOCEN :1; /*!< Enable clock for GPIOC port */ uint32_t GPIODEN :1; /*!< Enable clock for GPIOD port */ uint32_t GPIOEEN :1; /*!< Enable clock for GPIOE port */ uint32_t GPIOFEN :1; /*!< Enable clock for GPIOF port */ uint32_t GPIOGEN :1; /*!< Enable clock for GPIOG port */ uint32_t GPIOHEN :1; /*!< Enable clock for GPIOH port */ uint32_t GPIOJEN :1; /*!< Enable clock for GPIOJ port */ uint32_t GPIOKEN :1; /*!< Enable clock for GPIOK port */ uint32_t GPIOLEN :1; /*!< Enable clock for GPIOL port */ uint32_t GPIOMEN :1; /*!< Enable clock for GPIOM port */ uint32_t CANEN :1; /*!< Enable clock for CAN interface */ uint32_t ETHEN :1; /*!< Enable clock for ethernet */ uint32_t MILSTD0EN :1; /*!< Enable clock for milstd 0 interface */ uint32_t MILSTD1EN :1; /*!< Enable clock for milstd 1 interface */ uint32_t SPWR0EN :1; /*!< Enable clock for spacewire 0 interface */ uint32_t SPWR1EN :1; /*!< Enable clock for spacewire 1 interface */ uint32_t EXTMEMEN :1; /*!< Enable clock for extmem interface */ uint32_t SDFMEN :1; /*!< Enable clock for SDFM */ } _RCU_HCLKCFG_bits; /* Bit field positions: */ #define RCU_HCLKCFG_GPIOAEN_Pos 0 /*!< Enable clock for GPIOA port */ #define RCU_HCLKCFG_GPIOBEN_Pos 1 /*!< Enable clock for GPIOB port */ #define RCU_HCLKCFG_GPIOCEN_Pos 2 /*!< Enable clock for GPIOC port */ #define RCU_HCLKCFG_GPIODEN_Pos 3 /*!< Enable clock for GPIOD port */ #define RCU_HCLKCFG_GPIOEEN_Pos 4 /*!< Enable clock for GPIOE port */ #define RCU_HCLKCFG_GPIOFEN_Pos 5 /*!< Enable clock for GPIOF port */ #define RCU_HCLKCFG_GPIOGEN_Pos 6 /*!< Enable clock for GPIOG port */ #define RCU_HCLKCFG_GPIOHEN_Pos 7 /*!< Enable clock for GPIOH port */ #define RCU_HCLKCFG_GPIOJEN_Pos 8 /*!< Enable clock for GPIOJ port */ #define RCU_HCLKCFG_GPIOKEN_Pos 9 /*!< Enable clock for GPIOK port */ #define RCU_HCLKCFG_GPIOLEN_Pos 10 /*!< Enable clock for GPIOL port */ #define RCU_HCLKCFG_GPIOMEN_Pos 11 /*!< Enable clock for GPIOM port */ #define RCU_HCLKCFG_CANEN_Pos 12 /*!< Enable clock for CAN interface */ #define RCU_HCLKCFG_ETHEN_Pos 13 /*!< Enable clock for ethernet */ #define RCU_HCLKCFG_MILSTD0EN_Pos 14 /*!< Enable clock for milstd 0 interface */ #define RCU_HCLKCFG_MILSTD1EN_Pos 15 /*!< Enable clock for milstd 1 interface */ #define RCU_HCLKCFG_SPWR0EN_Pos 16 /*!< Enable clock for spacewire 0 interface */ #define RCU_HCLKCFG_SPWR1EN_Pos 17 /*!< Enable clock for spacewire 1 interface */ #define RCU_HCLKCFG_EXTMEMEN_Pos 18 /*!< Enable clock for extmem interface */ #define RCU_HCLKCFG_SDFMEN_Pos 19 /*!< Enable clock for SDFM */ /* Bit field masks: */ #define RCU_HCLKCFG_GPIOAEN_Msk 0x00000001UL /*!< Enable clock for GPIOA port */ #define RCU_HCLKCFG_GPIOBEN_Msk 0x00000002UL /*!< Enable clock for GPIOB port */ #define RCU_HCLKCFG_GPIOCEN_Msk 0x00000004UL /*!< Enable clock for GPIOC port */ #define RCU_HCLKCFG_GPIODEN_Msk 0x00000008UL /*!< Enable clock for GPIOD port */ #define RCU_HCLKCFG_GPIOEEN_Msk 0x00000010UL /*!< Enable clock for GPIOE port */ #define RCU_HCLKCFG_GPIOFEN_Msk 0x00000020UL /*!< Enable clock for GPIOF port */ #define RCU_HCLKCFG_GPIOGEN_Msk 0x00000040UL /*!< Enable clock for GPIOG port */ #define RCU_HCLKCFG_GPIOHEN_Msk 0x00000080UL /*!< Enable clock for GPIOH port */ #define RCU_HCLKCFG_GPIOJEN_Msk 0x00000100UL /*!< Enable clock for GPIOJ port */ #define RCU_HCLKCFG_GPIOKEN_Msk 0x00000200UL /*!< Enable clock for GPIOK port */ #define RCU_HCLKCFG_GPIOLEN_Msk 0x00000400UL /*!< Enable clock for GPIOL port */ #define RCU_HCLKCFG_GPIOMEN_Msk 0x00000800UL /*!< Enable clock for GPIOM port */ #define RCU_HCLKCFG_CANEN_Msk 0x00001000UL /*!< Enable clock for CAN interface */ #define RCU_HCLKCFG_ETHEN_Msk 0x00002000UL /*!< Enable clock for ethernet */ #define RCU_HCLKCFG_MILSTD0EN_Msk 0x00004000UL /*!< Enable clock for milstd 0 interface */ #define RCU_HCLKCFG_MILSTD1EN_Msk 0x00008000UL /*!< Enable clock for milstd 1 interface */ #define RCU_HCLKCFG_SPWR0EN_Msk 0x00010000UL /*!< Enable clock for spacewire 0 interface */ #define RCU_HCLKCFG_SPWR1EN_Msk 0x00020000UL /*!< Enable clock for spacewire 1 interface */ #define RCU_HCLKCFG_EXTMEMEN_Msk 0x00040000UL /*!< Enable clock for extmem interface */ #define RCU_HCLKCFG_SDFMEN_Msk 0x00080000UL /*!< Enable clock for SDFM */ /*-- HRSTCFG: AHB Reset Configuration Register ---------------------------------------------------------------*/ typedef struct { uint32_t GPIOAEN :1; /*!< Disable reset from GPIOA port */ uint32_t GPIOBEN :1; /*!< Disable reset from GPIOB port */ uint32_t GPIOCEN :1; /*!< Disable reset from GPIOC port */ uint32_t GPIODEN :1; /*!< Disable reset from GPIOD port */ uint32_t GPIOEEN :1; /*!< Disable reset from GPIOE port */ uint32_t GPIOFEN :1; /*!< Disable reset from GPIOF port */ uint32_t GPIOGEN :1; /*!< Disable reset from GPIOG port */ uint32_t GPIOHEN :1; /*!< Disable reset from GPIOH port */ uint32_t GPIOJEN :1; /*!< Disable reset from GPIOJ port */ uint32_t GPIOKEN :1; /*!< Disable reset from GPIOK port */ uint32_t GPIOLEN :1; /*!< Disable reset from GPIOL port */ uint32_t GPIOMEN :1; /*!< Disable reset from GPIOM port */ uint32_t CANEN :1; /*!< Disable reset from CAN interface */ uint32_t ETHEN :1; /*!< Disable reset from Ethernet */ uint32_t MILSTD0EN :1; /*!< Disable reset from milstd 0 interface */ uint32_t MILSTD1EN :1; /*!< Disable reset from milstd 1 nterface */ uint32_t SPWR0EN :1; /*!< Disable reset from spacewire 0 interface */ uint32_t SPWR1EN :1; /*!< Disable reset from spacewire 1 interface */ uint32_t EXTMEMEN :1; /*!< Disable reset from extmem interface */ uint32_t SDFMEN :1; /*!< Disable reset from SDFM */ } _RCU_HRSTCFG_bits; /* Bit field positions: */ #define RCU_HRSTCFG_GPIOAEN_Pos 0 /*!< Disable reset from GPIOA port */ #define RCU_HRSTCFG_GPIOBEN_Pos 1 /*!< Disable reset from GPIOB port */ #define RCU_HRSTCFG_GPIOCEN_Pos 2 /*!< Disable reset from GPIOC port */ #define RCU_HRSTCFG_GPIODEN_Pos 3 /*!< Disable reset from GPIOD port */ #define RCU_HRSTCFG_GPIOEEN_Pos 4 /*!< Disable reset from GPIOE port */ #define RCU_HRSTCFG_GPIOFEN_Pos 5 /*!< Disable reset from GPIOF port */ #define RCU_HRSTCFG_GPIOGEN_Pos 6 /*!< Disable reset from GPIOG port */ #define RCU_HRSTCFG_GPIOHEN_Pos 7 /*!< Disable reset from GPIOH port */ #define RCU_HRSTCFG_GPIOJEN_Pos 8 /*!< Disable reset from GPIOJ port */ #define RCU_HRSTCFG_GPIOKEN_Pos 9 /*!< Disable reset from GPIOK port */ #define RCU_HRSTCFG_GPIOLEN_Pos 10 /*!< Disable reset from GPIOL port */ #define RCU_HRSTCFG_GPIOMEN_Pos 11 /*!< Disable reset from GPIOM port */ #define RCU_HRSTCFG_CANEN_Pos 12 /*!< Disable reset from CAN interface */ #define RCU_HRSTCFG_ETHEN_Pos 13 /*!< Disable reset from Ethernet */ #define RCU_HRSTCFG_MILSTD0EN_Pos 14 /*!< Disable reset from milstd 0 interface */ #define RCU_HRSTCFG_MILSTD1EN_Pos 15 /*!< Disable reset from milstd 1 nterface */ #define RCU_HRSTCFG_SPWR0EN_Pos 16 /*!< Disable reset from spacewire 0 interface */ #define RCU_HRSTCFG_SPWR1EN_Pos 17 /*!< Disable reset from spacewire 1 interface */ #define RCU_HRSTCFG_EXTMEMEN_Pos 18 /*!< Disable reset from extmem interface */ #define RCU_HRSTCFG_SDFMEN_Pos 19 /*!< Disable reset from SDFM */ /* Bit field masks: */ #define RCU_HRSTCFG_GPIOAEN_Msk 0x00000001UL /*!< Disable reset from GPIOA port */ #define RCU_HRSTCFG_GPIOBEN_Msk 0x00000002UL /*!< Disable reset from GPIOB port */ #define RCU_HRSTCFG_GPIOCEN_Msk 0x00000004UL /*!< Disable reset from GPIOC port */ #define RCU_HRSTCFG_GPIODEN_Msk 0x00000008UL /*!< Disable reset from GPIOD port */ #define RCU_HRSTCFG_GPIOEEN_Msk 0x00000010UL /*!< Disable reset from GPIOE port */ #define RCU_HRSTCFG_GPIOFEN_Msk 0x00000020UL /*!< Disable reset from GPIOF port */ #define RCU_HRSTCFG_GPIOGEN_Msk 0x00000040UL /*!< Disable reset from GPIOG port */ #define RCU_HRSTCFG_GPIOHEN_Msk 0x00000080UL /*!< Disable reset from GPIOH port */ #define RCU_HRSTCFG_GPIOJEN_Msk 0x00000100UL /*!< Disable reset from GPIOJ port */ #define RCU_HRSTCFG_GPIOKEN_Msk 0x00000200UL /*!< Disable reset from GPIOK port */ #define RCU_HRSTCFG_GPIOLEN_Msk 0x00000400UL /*!< Disable reset from GPIOL port */ #define RCU_HRSTCFG_GPIOMEN_Msk 0x00000800UL /*!< Disable reset from GPIOM port */ #define RCU_HRSTCFG_CANEN_Msk 0x00001000UL /*!< Disable reset from CAN interface */ #define RCU_HRSTCFG_ETHEN_Msk 0x00002000UL /*!< Disable reset from Ethernet */ #define RCU_HRSTCFG_MILSTD0EN_Msk 0x00004000UL /*!< Disable reset from milstd 0 interface */ #define RCU_HRSTCFG_MILSTD1EN_Msk 0x00008000UL /*!< Disable reset from milstd 1 nterface */ #define RCU_HRSTCFG_SPWR0EN_Msk 0x00010000UL /*!< Disable reset from spacewire 0 interface */ #define RCU_HRSTCFG_SPWR1EN_Msk 0x00020000UL /*!< Disable reset from spacewire 1 interface */ #define RCU_HRSTCFG_EXTMEMEN_Msk 0x00040000UL /*!< Disable reset from extmem interface */ #define RCU_HRSTCFG_SDFMEN_Msk 0x00080000UL /*!< Disable reset from SDFM */ //Cluster MILSTDCFG: typedef struct { union { /*!< MILSTD Codec Clock and Reset Configuration Register */ __IO uint32_t MILSTDCFG; /*!< MILSTDCFG : type used for word access */ __IO _RCU_MILSTDCFG_MILSTDCFG_bits MILSTDCFG_bit; /*!< MILSTDCFG_bit: structure used for bit access */ }; } _RCU_MILSTDCFG_TypeDef; //Cluster SPWRCFG: typedef struct { union { /*!< SPWR TX Clock Configuration Register */ __IO uint32_t SPWRCFG; /*!< SPWRCFG : type used for word access */ __IO _RCU_SPWRCFG_SPWRCFG_bits SPWRCFG_bit; /*!< SPWRCFG_bit: structure used for bit access */ }; } _RCU_SPWRCFG_TypeDef; //Cluster UARTCFG: typedef struct { union { /*!< UART Clock and Reset Configuration Register */ __IO uint32_t UARTCFG; /*!< UARTCFG : type used for word access */ __IO _RCU_UARTCFG_UARTCFG_bits UARTCFG_bit; /*!< UARTCFG_bit: structure used for bit access */ }; } _RCU_UARTCFG_TypeDef; //Cluster SPICFG: typedef struct { union { /*!< SPI Clock and Reset Configuration Register */ __IO uint32_t SPICFG; /*!< SPICFG : type used for word access */ __IO _RCU_SPICFG_SPICFG_bits SPICFG_bit; /*!< SPICFG_bit: structure used for bit access */ }; } _RCU_SPICFG_TypeDef; typedef struct { __IO uint32_t Reserved0[2]; union { /*!< PLL Configuration Register */ __IO uint32_t PLLCFG; /*!< PLLCFG : type used for word access */ __IO _RCU_PLLCFG_bits PLLCFG_bit; /*!< PLLCFG_bit: structure used for bit access */ }; union { /*!< PLL Divider Register */ __IO uint32_t PLLDIV; /*!< PLLDIV : type used for word access */ __IO _RCU_PLLDIV_bits PLLDIV_bit; /*!< PLLDIV_bit: structure used for bit access */ }; union { /*!< System Clock Configuration Register */ __IO uint32_t SYSCLKCFG; /*!< SYSCLKCFG : type used for word access */ __IO _RCU_SYSCLKCFG_bits SYSCLKCFG_bit; /*!< SYSCLKCFG_bit: structure used for bit access */ }; union { /*!< System Clock Status Register */ __I uint32_t SYSCLKSTAT; /*!< SYSCLKSTAT : type used for word access */ __I _RCU_SYSCLKSTAT_bits SYSCLKSTAT_bit; /*!< SYSCLKSTAT_bit: structure used for bit access */ }; union { /*!< Security Sysytem Clock Period Register 0 */ __IO uint32_t SECPRD; /*!< SECPRD : type used for word access */ __IO _RCU_SECPRD_bits SECPRD_bit; /*!< SECPRD_bit: structure used for bit access */ }; union { /*!< System Reset Configuration Register */ __IO uint32_t SYSRSTCFG; /*!< SYSRSTCFG : type used for word access */ __IO _RCU_SYSRSTCFG_bits SYSRSTCFG_bit; /*!< SYSRSTCFG_bit: structure used for bit access */ }; union { /*!< Reset Status Register */ __IO uint32_t SYSRSTSTAT; /*!< SYSRSTSTAT : type used for word access */ __IO _RCU_SYSRSTSTAT_bits SYSRSTSTAT_bit; /*!< SYSRSTSTAT_bit: structure used for bit access */ }; union { /*!< Interrupt Enable Register */ __IO uint32_t INTEN; /*!< INTEN : type used for word access */ __IO _RCU_INTEN_bits INTEN_bit; /*!< INTEN_bit: structure used for bit access */ }; union { /*!< Interrupt Status Register */ __IO uint32_t INTSTAT; /*!< INTSTAT : type used for word access */ __IO _RCU_INTSTAT_bits INTSTAT_bit; /*!< INTSTAT_bit: structure used for bit access */ }; union { /*!< Trace Clock Configuration Register */ __IO uint32_t TRACECFG; /*!< TRACECFG : type used for word access */ __IO _RCU_TRACECFG_bits TRACECFG_bit; /*!< TRACECFG_bit: structure used for bit access */ }; union { /*!< Clockout Configuration Register */ __IO uint32_t CLKOUTCFG; /*!< CLKOUTCFG : type used for word access */ __IO _RCU_CLKOUTCFG_bits CLKOUTCFG_bit; /*!< CLKOUTCFG_bit: structure used for bit access */ }; union { /*!< WatchDog Configuration Register */ __IO uint32_t WDTCFG; /*!< WDTCFG : type used for word access */ __IO _RCU_WDTCFG_bits WDTCFG_bit; /*!< WDTCFG_bit: structure used for bit access */ }; __IO uint32_t Reserved1[2]; _RCU_MILSTDCFG_TypeDef MILSTDCFG[2]; __IO uint32_t Reserved2[2]; _RCU_SPWRCFG_TypeDef SPWRCFG[2]; __IO uint32_t Reserved3[2]; _RCU_UARTCFG_TypeDef UARTCFG[4]; __IO uint32_t Reserved4[4]; _RCU_SPICFG_TypeDef SPICFG[4]; __IO uint32_t Reserved5[4]; union { /*!< ADC Clock and Reset Configuration Register */ __IO uint32_t ADCCFG; /*!< ADCCFG : type used for word access */ __IO _RCU_ADCCFG_bits ADCCFG_bit; /*!< ADCCFG_bit: structure used for bit access */ }; __IO uint32_t Reserved6[7]; union { /*!< APB Clock Configuraton Register */ __IO uint32_t APBCFG; /*!< APBCFG : type used for word access */ __IO _RCU_APBCFG_bits APBCFG_bit; /*!< APBCFG_bit: structure used for bit access */ }; __IO uint32_t Reserved7[7]; union { /*!< APB Clock Configuration Register 0 */ __IO uint32_t PCLKCFG0; /*!< PCLKCFG0 : type used for word access */ __IO _RCU_PCLKCFG0_bits PCLKCFG0_bit; /*!< PCLKCFG0_bit: structure used for bit access */ }; union { /*!< APB Clock Configuration Register 1 */ __IO uint32_t PCLKCFG1; /*!< PCLKCFG1 : type used for word access */ __IO _RCU_PCLKCFG1_bits PCLKCFG1_bit; /*!< PCLKCFG1_bit: structure used for bit access */ }; __IO uint32_t Reserved8[2]; union { /*!< APB Reset Configuration Register 0 */ __IO uint32_t PRSTCFG0; /*!< PRSTCFG0 : type used for word access */ __IO _RCU_PRSTCFG0_bits PRSTCFG0_bit; /*!< PRSTCFG0_bit: structure used for bit access */ }; union { /*!< APB Reset Configuration Register 1 */ __IO uint32_t PRSTCFG1; /*!< PRSTCFG1 : type used for word access */ __IO _RCU_PRSTCFG1_bits PRSTCFG1_bit; /*!< PRSTCFG1_bit: structure used for bit access */ }; __IO uint32_t Reserved9[2]; union { /*!< AHB Clock Configuration Register */ __IO uint32_t HCLKCFG; /*!< HCLKCFG : type used for word access */ __IO _RCU_HCLKCFG_bits HCLKCFG_bit; /*!< HCLKCFG_bit: structure used for bit access */ }; union { /*!< AHB Reset Configuration Register */ __IO uint32_t HRSTCFG; /*!< HRSTCFG : type used for word access */ __IO _RCU_HRSTCFG_bits HRSTCFG_bit; /*!< HRSTCFG_bit: structure used for bit access */ }; } RCU_TypeDef; /******************************************************************************/ /* SIU registers */ /******************************************************************************/ /*-- PWMSYNC: PWM syncronization control register ------------------------------------------------------------*/ typedef struct { uint32_t SYNCSEL :2; /*!< PWM sync scheme control */ uint32_t SWSYNC :1; /*!< SYNCI pulse software emulation on PWM0 */ uint32_t :1; /*!< RESERVED */ uint32_t CAPSYNCSEL :1; /*!< CAP sync scheme control */ uint32_t :3; /*!< RESERVED */ uint32_t PRESCRST :10; /*!< PWM prescalers reset control */ } _SIU_PWMSYNC_bits; /* Bit field positions: */ #define SIU_PWMSYNC_SYNCSEL_Pos 0 /*!< PWM sync scheme control */ #define SIU_PWMSYNC_SWSYNC_Pos 2 /*!< SYNCI pulse software emulation on PWM0 */ #define SIU_PWMSYNC_CAPSYNCSEL_Pos 4 /*!< CAP sync scheme control */ #define SIU_PWMSYNC_PRESCRST_Pos 8 /*!< PWM prescalers reset control */ /* Bit field masks: */ #define SIU_PWMSYNC_SYNCSEL_Msk 0x00000003UL /*!< PWM sync scheme control */ #define SIU_PWMSYNC_SWSYNC_Msk 0x00000004UL /*!< SYNCI pulse software emulation on PWM0 */ #define SIU_PWMSYNC_CAPSYNCSEL_Msk 0x00000010UL /*!< CAP sync scheme control */ #define SIU_PWMSYNC_PRESCRST_Msk 0x0003FF00UL /*!< PWM prescalers reset control */ /*-- SERVCTL: Service mode control register ------------------------------------------------------------------*/ typedef struct { uint32_t CHIPCLR :1; /*!< On-chip memories full clear task start */ uint32_t DONE :1; /*!< Status of clear task */ uint32_t :29; /*!< RESERVED */ uint32_t SERVEN :1; /*!< Service mode enable status */ } _SIU_SERVCTL_bits; /* Bit field positions: */ #define SIU_SERVCTL_CHIPCLR_Pos 0 /*!< On-chip memories full clear task start */ #define SIU_SERVCTL_DONE_Pos 1 /*!< Status of clear task */ #define SIU_SERVCTL_SERVEN_Pos 31 /*!< Service mode enable status */ /* Bit field masks: */ #define SIU_SERVCTL_CHIPCLR_Msk 0x00000001UL /*!< On-chip memories full clear task start */ #define SIU_SERVCTL_DONE_Msk 0x00000002UL /*!< Status of clear task */ #define SIU_SERVCTL_SERVEN_Msk 0x80000000UL /*!< Service mode enable status */ /*-- DMAMUX: DMA external requests mux control register ------------------------------------------------------*/ typedef struct { uint32_t SRCSEL24 :3; /*!< Request source select for DMA channel 24 */ uint32_t :1; /*!< RESERVED */ uint32_t SRCSEL25 :3; /*!< Request source select for DMA channel 25 */ uint32_t :1; /*!< RESERVED */ uint32_t SRCSEL26 :3; /*!< Request source select for DMA channel 26 */ uint32_t :1; /*!< RESERVED */ uint32_t SRCSEL27 :3; /*!< Request source select for DMA channel 27 */ uint32_t :1; /*!< RESERVED */ uint32_t SRCSEL28 :3; /*!< Request source select for DMA channel 28 */ uint32_t :1; /*!< RESERVED */ uint32_t SRCSEL29 :3; /*!< Request source select for DMA channel 29 */ uint32_t :1; /*!< RESERVED */ uint32_t SRCSEL30 :3; /*!< Request source select for DMA channel 30 */ uint32_t :1; /*!< RESERVED */ uint32_t SRCSEL31 :3; /*!< Request source select for DMA channel 31 */ } _SIU_DMAMUX_bits; /* Bit field positions: */ #define SIU_DMAMUX_SRCSEL24_Pos 0 /*!< Request source select for DMA channel 24 */ #define SIU_DMAMUX_SRCSEL25_Pos 4 /*!< Request source select for DMA channel 25 */ #define SIU_DMAMUX_SRCSEL26_Pos 8 /*!< Request source select for DMA channel 26 */ #define SIU_DMAMUX_SRCSEL27_Pos 12 /*!< Request source select for DMA channel 27 */ #define SIU_DMAMUX_SRCSEL28_Pos 16 /*!< Request source select for DMA channel 28 */ #define SIU_DMAMUX_SRCSEL29_Pos 20 /*!< Request source select for DMA channel 29 */ #define SIU_DMAMUX_SRCSEL30_Pos 24 /*!< Request source select for DMA channel 30 */ #define SIU_DMAMUX_SRCSEL31_Pos 28 /*!< Request source select for DMA channel 31 */ /* Bit field masks: */ #define SIU_DMAMUX_SRCSEL24_Msk 0x00000007UL /*!< Request source select for DMA channel 24 */ #define SIU_DMAMUX_SRCSEL25_Msk 0x00000070UL /*!< Request source select for DMA channel 25 */ #define SIU_DMAMUX_SRCSEL26_Msk 0x00000700UL /*!< Request source select for DMA channel 26 */ #define SIU_DMAMUX_SRCSEL27_Msk 0x00007000UL /*!< Request source select for DMA channel 27 */ #define SIU_DMAMUX_SRCSEL28_Msk 0x00070000UL /*!< Request source select for DMA channel 28 */ #define SIU_DMAMUX_SRCSEL29_Msk 0x00700000UL /*!< Request source select for DMA channel 29 */ #define SIU_DMAMUX_SRCSEL30_Msk 0x07000000UL /*!< Request source select for DMA channel 30 */ #define SIU_DMAMUX_SRCSEL31_Msk 0x70000000UL /*!< Request source select for DMA channel 31 */ /* Bit field enums: */ typedef enum { SIU_DMAMUX_SRCSEL24_GPIOA = 0x0UL, /*!< request by GPIOA */ SIU_DMAMUX_SRCSEL24_TMR0 = 0x1UL, /*!< request by TMR0 */ SIU_DMAMUX_SRCSEL24_PWM0A = 0x2UL, /*!< request by PWM0A */ SIU_DMAMUX_SRCSEL24_PWM1A = 0x3UL, /*!< request by PWM1A */ SIU_DMAMUX_SRCSEL24_PWM8A = 0x4UL, /*!< request by PWM8A */ SIU_DMAMUX_SRCSEL24_PWM9A = 0x5UL, /*!< request by PWM9A */ } SIU_DMAMUX_SRCSEL24_Enum; typedef enum { SIU_DMAMUX_SRCSEL25_GPIOB = 0x0UL, /*!< request by GPIOB */ SIU_DMAMUX_SRCSEL25_TMR1 = 0x1UL, /*!< request by TMR1 */ SIU_DMAMUX_SRCSEL25_PWM2A = 0x2UL, /*!< request by PWM2A */ SIU_DMAMUX_SRCSEL25_PWM3A = 0x3UL, /*!< request by PWM3A */ SIU_DMAMUX_SRCSEL25_QEP0 = 0x4UL, /*!< request by QEP0 */ SIU_DMAMUX_SRCSEL25_SDFM0 = 0x5UL, /*!< request by SDFM0 */ } SIU_DMAMUX_SRCSEL25_Enum; typedef enum { SIU_DMAMUX_SRCSEL26_GPIOC = 0x0UL, /*!< request by GPIOC */ SIU_DMAMUX_SRCSEL26_TMR2 = 0x1UL, /*!< request by TMR2 */ SIU_DMAMUX_SRCSEL26_PWM4A = 0x2UL, /*!< request by PWM4A */ SIU_DMAMUX_SRCSEL26_PWM5A = 0x3UL, /*!< request by PWM5A */ SIU_DMAMUX_SRCSEL26_QEP1 = 0x4UL, /*!< request by QEP1 */ SIU_DMAMUX_SRCSEL26_SDFM1 = 0x5UL, /*!< request by SDFM1 */ } SIU_DMAMUX_SRCSEL26_Enum; typedef enum { SIU_DMAMUX_SRCSEL27_GPIOD = 0x0UL, /*!< request by GPIOD */ SIU_DMAMUX_SRCSEL27_TMR3 = 0x1UL, /*!< request by TMR3 */ SIU_DMAMUX_SRCSEL27_PWM6A = 0x2UL, /*!< request by PWM6A */ SIU_DMAMUX_SRCSEL27_PWM7A = 0x3UL, /*!< request by PWM7A */ SIU_DMAMUX_SRCSEL27_GPIOJ = 0x4UL, /*!< request by GPIOJ */ SIU_DMAMUX_SRCSEL27_GPIOK = 0x5UL, /*!< request by GPIOK */ } SIU_DMAMUX_SRCSEL27_Enum; typedef enum { SIU_DMAMUX_SRCSEL28_GPIOE = 0x0UL, /*!< request by GPIOE */ SIU_DMAMUX_SRCSEL28_ETMR0 = 0x1UL, /*!< request by ETMR0 */ SIU_DMAMUX_SRCSEL28_PWM0B = 0x2UL, /*!< request by PWM0B */ SIU_DMAMUX_SRCSEL28_PWM1B = 0x3UL, /*!< request by PWM1B */ SIU_DMAMUX_SRCSEL28_PWM8B = 0x4UL, /*!< request by PWM8B */ SIU_DMAMUX_SRCSEL28_PWM9B = 0x5UL, /*!< request by PWM9B */ } SIU_DMAMUX_SRCSEL28_Enum; typedef enum { SIU_DMAMUX_SRCSEL29_GPIOF = 0x0UL, /*!< request by GPIOF */ SIU_DMAMUX_SRCSEL29_ETMR1 = 0x1UL, /*!< request by ETMR1 */ SIU_DMAMUX_SRCSEL29_PWM2B = 0x2UL, /*!< request by PWM2B */ SIU_DMAMUX_SRCSEL29_PWM3B = 0x3UL, /*!< request by PWM3B */ SIU_DMAMUX_SRCSEL29_QEP2 = 0x4UL, /*!< request by QEP2 */ SIU_DMAMUX_SRCSEL29_SDFM2 = 0x5UL, /*!< request by SDFM2 */ } SIU_DMAMUX_SRCSEL29_Enum; typedef enum { SIU_DMAMUX_SRCSEL30_GPIOG = 0x0UL, /*!< request by GPIOG */ SIU_DMAMUX_SRCSEL30_ETMR2 = 0x1UL, /*!< request by ETMR2 */ SIU_DMAMUX_SRCSEL30_PWM4B = 0x2UL, /*!< request by PWM4B */ SIU_DMAMUX_SRCSEL30_PWM5B = 0x3UL, /*!< request by PWM5B */ SIU_DMAMUX_SRCSEL30_QEP3 = 0x4UL, /*!< request by QEP3 */ SIU_DMAMUX_SRCSEL30_SDFM3 = 0x5UL, /*!< request by SDFM3 */ } SIU_DMAMUX_SRCSEL30_Enum; typedef enum { SIU_DMAMUX_SRCSEL31_GPIOH = 0x0UL, /*!< request by GPIOH */ SIU_DMAMUX_SRCSEL31_ETMR3 = 0x1UL, /*!< request by ETMR3 */ SIU_DMAMUX_SRCSEL31_PWM6B = 0x2UL, /*!< request by PWM6B */ SIU_DMAMUX_SRCSEL31_PWM7B = 0x3UL, /*!< request by PWM7B */ SIU_DMAMUX_SRCSEL31_GPIOL = 0x4UL, /*!< request by GPIOL */ SIU_DMAMUX_SRCSEL31_GPIOM = 0x5UL, /*!< request by GPIOM */ } SIU_DMAMUX_SRCSEL31_Enum; /*-- TMRMUX: TMR external clock mux control register ---------------------------------------------------------*/ typedef struct { uint32_t EXTINSEL0 :1; /*!< Select external input source for TMR0 */ uint32_t EXTINSEL1 :1; /*!< Select external input source for TMR1 */ uint32_t EXTINSEL2 :1; /*!< Select external input source for TMR2 */ uint32_t EXTINSEL3 :1; /*!< Select external input source for TMR3 */ } _SIU_TMRMUX_bits; /* Bit field positions: */ #define SIU_TMRMUX_EXTINSEL0_Pos 0 /*!< Select external input source for TMR0 */ #define SIU_TMRMUX_EXTINSEL1_Pos 1 /*!< Select external input source for TMR1 */ #define SIU_TMRMUX_EXTINSEL2_Pos 2 /*!< Select external input source for TMR2 */ #define SIU_TMRMUX_EXTINSEL3_Pos 3 /*!< Select external input source for TMR3 */ /* Bit field masks: */ #define SIU_TMRMUX_EXTINSEL0_Msk 0x00000001UL /*!< Select external input source for TMR0 */ #define SIU_TMRMUX_EXTINSEL1_Msk 0x00000002UL /*!< Select external input source for TMR1 */ #define SIU_TMRMUX_EXTINSEL2_Msk 0x00000004UL /*!< Select external input source for TMR2 */ #define SIU_TMRMUX_EXTINSEL3_Msk 0x00000008UL /*!< Select external input source for TMR3 */ /*-- CAPMUX: CAP input mux control register ------------------------------------------------------------------*/ typedef struct { uint32_t CAPINSEL0 :4; /*!< Select input source for CAP0 */ uint32_t CAPINSEL1 :4; /*!< Select input source for CAP1 */ uint32_t CAPINSEL2 :4; /*!< Select input source for CAP2 */ uint32_t CAPINSEL3 :4; /*!< Select input source for CAP3 */ uint32_t CAPINSEL4 :4; /*!< Select input source for CAP4 */ uint32_t CAPINSEL5 :4; /*!< Select input source for CAP5 */ } _SIU_CAPMUX_bits; /* Bit field positions: */ #define SIU_CAPMUX_CAPINSEL0_Pos 0 /*!< Select input source for CAP0 */ #define SIU_CAPMUX_CAPINSEL1_Pos 4 /*!< Select input source for CAP1 */ #define SIU_CAPMUX_CAPINSEL2_Pos 8 /*!< Select input source for CAP2 */ #define SIU_CAPMUX_CAPINSEL3_Pos 12 /*!< Select input source for CAP3 */ #define SIU_CAPMUX_CAPINSEL4_Pos 16 /*!< Select input source for CAP4 */ #define SIU_CAPMUX_CAPINSEL5_Pos 20 /*!< Select input source for CAP5 */ /* Bit field masks: */ #define SIU_CAPMUX_CAPINSEL0_Msk 0x0000000FUL /*!< Select input source for CAP0 */ #define SIU_CAPMUX_CAPINSEL1_Msk 0x000000F0UL /*!< Select input source for CAP1 */ #define SIU_CAPMUX_CAPINSEL2_Msk 0x00000F00UL /*!< Select input source for CAP2 */ #define SIU_CAPMUX_CAPINSEL3_Msk 0x0000F000UL /*!< Select input source for CAP3 */ #define SIU_CAPMUX_CAPINSEL4_Msk 0x000F0000UL /*!< Select input source for CAP4 */ #define SIU_CAPMUX_CAPINSEL5_Msk 0x00F00000UL /*!< Select input source for CAP5 */ /* Bit field enums: */ typedef enum { SIU_CAPMUX_CAPINSEL0_CAP0 = 0x0UL, /*!< default CAP0 input */ SIU_CAPMUX_CAPINSEL0_SDFMCHZ0 = 0x8UL, /*!< SDFM comparator 0 HZ output */ SIU_CAPMUX_CAPINSEL0_SDFMCHZ1 = 0x9UL, /*!< SDFM comparator 1 HZ output */ SIU_CAPMUX_CAPINSEL0_SDFMCHZ2 = 0xAUL, /*!< SDFM comparator 2 HZ output */ SIU_CAPMUX_CAPINSEL0_SDFMCHZ3 = 0xBUL, /*!< SDFM comparator 3 HZ output */ SIU_CAPMUX_CAPINSEL0_QEPA0 = 0xCUL, /*!< QEP0 A input */ SIU_CAPMUX_CAPINSEL0_QEPA1 = 0xDUL, /*!< QEP1 A input */ SIU_CAPMUX_CAPINSEL0_QEPA2 = 0xEUL, /*!< QEP2 A input */ SIU_CAPMUX_CAPINSEL0_QEPA3 = 0xFUL, /*!< QEP3 A input */ } SIU_CAPMUX_CAPINSEL0_Enum; typedef enum { SIU_CAPMUX_CAPINSEL1_CAP1 = 0x0UL, /*!< default CAP1 input */ SIU_CAPMUX_CAPINSEL1_SDFMCHZ0 = 0x8UL, /*!< SDFM comparator 0 HZ output */ SIU_CAPMUX_CAPINSEL1_SDFMCHZ1 = 0x9UL, /*!< SDFM comparator 1 HZ output */ SIU_CAPMUX_CAPINSEL1_SDFMCHZ2 = 0xAUL, /*!< SDFM comparator 2 HZ output */ SIU_CAPMUX_CAPINSEL1_SDFMCHZ3 = 0xBUL, /*!< SDFM comparator 3 HZ output */ SIU_CAPMUX_CAPINSEL1_QEPB0 = 0xCUL, /*!< QEP0 B input */ SIU_CAPMUX_CAPINSEL1_QEPB1 = 0xDUL, /*!< QEP1 B input */ SIU_CAPMUX_CAPINSEL1_QEPB2 = 0xEUL, /*!< QEP2 B input */ SIU_CAPMUX_CAPINSEL1_QEPB3 = 0xFUL, /*!< QEP3 B input */ } SIU_CAPMUX_CAPINSEL1_Enum; typedef enum { SIU_CAPMUX_CAPINSEL2_CAP2 = 0x0UL, /*!< default CAP2 input */ SIU_CAPMUX_CAPINSEL2_SDFMCHZ0 = 0x8UL, /*!< SDFM comparator 0 HZ output */ SIU_CAPMUX_CAPINSEL2_SDFMCHZ1 = 0x9UL, /*!< SDFM comparator 1 HZ output */ SIU_CAPMUX_CAPINSEL2_SDFMCHZ2 = 0xAUL, /*!< SDFM comparator 2 HZ output */ SIU_CAPMUX_CAPINSEL2_SDFMCHZ3 = 0xBUL, /*!< SDFM comparator 3 HZ output */ SIU_CAPMUX_CAPINSEL2_QEPI0 = 0xCUL, /*!< QEP0 I input */ SIU_CAPMUX_CAPINSEL2_QEPI1 = 0xDUL, /*!< QEP1 I input */ SIU_CAPMUX_CAPINSEL2_QEPI2 = 0xEUL, /*!< QEP2 I input */ SIU_CAPMUX_CAPINSEL2_QEPI3 = 0xFUL, /*!< QEP3 I input */ } SIU_CAPMUX_CAPINSEL2_Enum; typedef enum { SIU_CAPMUX_CAPINSEL3_CAP3 = 0x0UL, /*!< default CAP3 input */ SIU_CAPMUX_CAPINSEL3_SDFMCHZ0 = 0x8UL, /*!< SDFM comparator 0 HZ output */ SIU_CAPMUX_CAPINSEL3_SDFMCHZ1 = 0x9UL, /*!< SDFM comparator 1 HZ output */ SIU_CAPMUX_CAPINSEL3_SDFMCHZ2 = 0xAUL, /*!< SDFM comparator 2 HZ output */ SIU_CAPMUX_CAPINSEL3_SDFMCHZ3 = 0xBUL, /*!< SDFM comparator 3 HZ output */ SIU_CAPMUX_CAPINSEL3_QEPA0 = 0xCUL, /*!< QEP0 A input */ SIU_CAPMUX_CAPINSEL3_QEPA1 = 0xDUL, /*!< QEP1 A input */ SIU_CAPMUX_CAPINSEL3_QEPA2 = 0xEUL, /*!< QEP2 A input */ SIU_CAPMUX_CAPINSEL3_QEPA3 = 0xFUL, /*!< QEP3 A input */ } SIU_CAPMUX_CAPINSEL3_Enum; typedef enum { SIU_CAPMUX_CAPINSEL4_CAP4 = 0x0UL, /*!< default CAP4 input */ SIU_CAPMUX_CAPINSEL4_SDFMCHZ0 = 0x8UL, /*!< SDFM comparator 0 HZ output */ SIU_CAPMUX_CAPINSEL4_SDFMCHZ1 = 0x9UL, /*!< SDFM comparator 1 HZ output */ SIU_CAPMUX_CAPINSEL4_SDFMCHZ2 = 0xAUL, /*!< SDFM comparator 2 HZ output */ SIU_CAPMUX_CAPINSEL4_SDFMCHZ3 = 0xBUL, /*!< SDFM comparator 3 HZ output */ SIU_CAPMUX_CAPINSEL4_QEPB0 = 0xCUL, /*!< QEP0 B input */ SIU_CAPMUX_CAPINSEL4_QEPB1 = 0xDUL, /*!< QEP1 B input */ SIU_CAPMUX_CAPINSEL4_QEPB2 = 0xEUL, /*!< QEP2 B input */ SIU_CAPMUX_CAPINSEL4_QEPB3 = 0xFUL, /*!< QEP3 B input */ } SIU_CAPMUX_CAPINSEL4_Enum; typedef enum { SIU_CAPMUX_CAPINSEL5_CAP5 = 0x0UL, /*!< default CAP5 input */ SIU_CAPMUX_CAPINSEL5_SDFMCHZ0 = 0x8UL, /*!< SDFM comparator 0 HZ output */ SIU_CAPMUX_CAPINSEL5_SDFMCHZ1 = 0x9UL, /*!< SDFM comparator 1 HZ output */ SIU_CAPMUX_CAPINSEL5_SDFMCHZ2 = 0xAUL, /*!< SDFM comparator 2 HZ output */ SIU_CAPMUX_CAPINSEL5_SDFMCHZ3 = 0xBUL, /*!< SDFM comparator 3 HZ output */ SIU_CAPMUX_CAPINSEL5_QEPI0 = 0xCUL, /*!< QEP0 I input */ SIU_CAPMUX_CAPINSEL5_QEPI1 = 0xDUL, /*!< QEP1 I input */ SIU_CAPMUX_CAPINSEL5_QEPI2 = 0xEUL, /*!< QEP2 I input */ SIU_CAPMUX_CAPINSEL5_QEPI3 = 0xFUL, /*!< QEP3 I input */ } SIU_CAPMUX_CAPINSEL5_Enum; /*-- QCQUALCTL: QEP and CAP qualifier control register -------------------------------------------------------*/ typedef struct { uint32_t CAPEN0 :1; /*!< Enable qualifier for CAP0 */ uint32_t CAPEN1 :1; /*!< Enable qualifier for CAP1 */ uint32_t CAPEN2 :1; /*!< Enable qualifier for CAP2 */ uint32_t CAPEN3 :1; /*!< Enable qualifier for CAP3 */ uint32_t CAPEN4 :1; /*!< Enable qualifier for CAP4 */ uint32_t CAPEN5 :1; /*!< Enable qualifier for CAP5 */ uint32_t :2; /*!< RESERVED */ uint32_t CAPMODE0 :1; /*!< Select mode of qualifier for CAP0 */ uint32_t CAPMODE1 :1; /*!< Select mode of qualifier for CAP1 */ uint32_t CAPMODE2 :1; /*!< Select mode of qualifier for CAP2 */ uint32_t CAPMODE3 :1; /*!< Select mode of qualifier for CAP3 */ uint32_t CAPMODE4 :1; /*!< Select mode of qualifier for CAP4 */ uint32_t CAPMODE5 :1; /*!< Select mode of qualifier for CAP5 */ uint32_t :2; /*!< RESERVED */ uint32_t QEPEN0 :1; /*!< Enable qualifier for QEP0 */ uint32_t QEPEN1 :1; /*!< Enable qualifier for QEP1 */ uint32_t QEPEN2 :1; /*!< Enable qualifier for QEP2 */ uint32_t QEPEN3 :1; /*!< Enable qualifier for QEP3 */ uint32_t :4; /*!< RESERVED */ uint32_t QEPMODE0 :1; /*!< Select mode of qualifier for QEP0 */ uint32_t QEPMODE1 :1; /*!< Select mode of qualifier for QEP1 */ uint32_t QEPMODE2 :1; /*!< Select mode of qualifier for QEP2 */ uint32_t QEPMODE3 :1; /*!< Select mode of qualifier for QEP3 */ } _SIU_QCQUALCTL_bits; /* Bit field positions: */ #define SIU_QCQUALCTL_CAPEN0_Pos 0 /*!< Enable qualifier for CAP0 */ #define SIU_QCQUALCTL_CAPEN1_Pos 1 /*!< Enable qualifier for CAP1 */ #define SIU_QCQUALCTL_CAPEN2_Pos 2 /*!< Enable qualifier for CAP2 */ #define SIU_QCQUALCTL_CAPEN3_Pos 3 /*!< Enable qualifier for CAP3 */ #define SIU_QCQUALCTL_CAPEN4_Pos 4 /*!< Enable qualifier for CAP4 */ #define SIU_QCQUALCTL_CAPEN5_Pos 5 /*!< Enable qualifier for CAP5 */ #define SIU_QCQUALCTL_CAPMODE0_Pos 8 /*!< Select mode of qualifier for CAP0 */ #define SIU_QCQUALCTL_CAPMODE1_Pos 9 /*!< Select mode of qualifier for CAP1 */ #define SIU_QCQUALCTL_CAPMODE2_Pos 10 /*!< Select mode of qualifier for CAP2 */ #define SIU_QCQUALCTL_CAPMODE3_Pos 11 /*!< Select mode of qualifier for CAP3 */ #define SIU_QCQUALCTL_CAPMODE4_Pos 12 /*!< Select mode of qualifier for CAP4 */ #define SIU_QCQUALCTL_CAPMODE5_Pos 13 /*!< Select mode of qualifier for CAP5 */ #define SIU_QCQUALCTL_QEPEN0_Pos 16 /*!< Enable qualifier for QEP0 */ #define SIU_QCQUALCTL_QEPEN1_Pos 17 /*!< Enable qualifier for QEP1 */ #define SIU_QCQUALCTL_QEPEN2_Pos 18 /*!< Enable qualifier for QEP2 */ #define SIU_QCQUALCTL_QEPEN3_Pos 19 /*!< Enable qualifier for QEP3 */ #define SIU_QCQUALCTL_QEPMODE0_Pos 24 /*!< Select mode of qualifier for QEP0 */ #define SIU_QCQUALCTL_QEPMODE1_Pos 25 /*!< Select mode of qualifier for QEP1 */ #define SIU_QCQUALCTL_QEPMODE2_Pos 26 /*!< Select mode of qualifier for QEP2 */ #define SIU_QCQUALCTL_QEPMODE3_Pos 27 /*!< Select mode of qualifier for QEP3 */ /* Bit field masks: */ #define SIU_QCQUALCTL_CAPEN0_Msk 0x00000001UL /*!< Enable qualifier for CAP0 */ #define SIU_QCQUALCTL_CAPEN1_Msk 0x00000002UL /*!< Enable qualifier for CAP1 */ #define SIU_QCQUALCTL_CAPEN2_Msk 0x00000004UL /*!< Enable qualifier for CAP2 */ #define SIU_QCQUALCTL_CAPEN3_Msk 0x00000008UL /*!< Enable qualifier for CAP3 */ #define SIU_QCQUALCTL_CAPEN4_Msk 0x00000010UL /*!< Enable qualifier for CAP4 */ #define SIU_QCQUALCTL_CAPEN5_Msk 0x00000020UL /*!< Enable qualifier for CAP5 */ #define SIU_QCQUALCTL_CAPMODE0_Msk 0x00000100UL /*!< Select mode of qualifier for CAP0 */ #define SIU_QCQUALCTL_CAPMODE1_Msk 0x00000200UL /*!< Select mode of qualifier for CAP1 */ #define SIU_QCQUALCTL_CAPMODE2_Msk 0x00000400UL /*!< Select mode of qualifier for CAP2 */ #define SIU_QCQUALCTL_CAPMODE3_Msk 0x00000800UL /*!< Select mode of qualifier for CAP3 */ #define SIU_QCQUALCTL_CAPMODE4_Msk 0x00001000UL /*!< Select mode of qualifier for CAP4 */ #define SIU_QCQUALCTL_CAPMODE5_Msk 0x00002000UL /*!< Select mode of qualifier for CAP5 */ #define SIU_QCQUALCTL_QEPEN0_Msk 0x00010000UL /*!< Enable qualifier for QEP0 */ #define SIU_QCQUALCTL_QEPEN1_Msk 0x00020000UL /*!< Enable qualifier for QEP1 */ #define SIU_QCQUALCTL_QEPEN2_Msk 0x00040000UL /*!< Enable qualifier for QEP2 */ #define SIU_QCQUALCTL_QEPEN3_Msk 0x00080000UL /*!< Enable qualifier for QEP3 */ #define SIU_QCQUALCTL_QEPMODE0_Msk 0x01000000UL /*!< Select mode of qualifier for QEP0 */ #define SIU_QCQUALCTL_QEPMODE1_Msk 0x02000000UL /*!< Select mode of qualifier for QEP1 */ #define SIU_QCQUALCTL_QEPMODE2_Msk 0x04000000UL /*!< Select mode of qualifier for QEP2 */ #define SIU_QCQUALCTL_QEPMODE3_Msk 0x08000000UL /*!< Select mode of qualifier for QEP3 */ /*-- QCQUALSAMPLE: QEP and CAP qualifier sample period set register ------------------------------------------*/ typedef struct { uint32_t CAPVAL :16; /*!< Set sample period of qualifer for all CAPs */ uint32_t QEPVAL :16; /*!< Set sample period of qualifer for all QEPs */ } _SIU_QCQUALSAMPLE_bits; /* Bit field positions: */ #define SIU_QCQUALSAMPLE_CAPVAL_Pos 0 /*!< Set sample period of qualifer for all CAPs */ #define SIU_QCQUALSAMPLE_QEPVAL_Pos 16 /*!< Set sample period of qualifer for all QEPs */ /* Bit field masks: */ #define SIU_QCQUALSAMPLE_CAPVAL_Msk 0x0000FFFFUL /*!< Set sample period of qualifer for all CAPs */ #define SIU_QCQUALSAMPLE_QEPVAL_Msk 0xFFFF0000UL /*!< Set sample period of qualifer for all QEPs */ /*-- RAMWSCTL: RAM waitstates control register ---------------------------------------------------------------*/ typedef struct { uint32_t WSEN0 :1; /*!< RAM0 additional waitstate */ uint32_t WSEN1 :1; /*!< RAM1 additional waitstate */ uint32_t WSEN2 :1; /*!< RAM2 additional waitstate */ } _SIU_RAMWSCTL_bits; /* Bit field positions: */ #define SIU_RAMWSCTL_WSEN0_Pos 0 /*!< RAM0 additional waitstate */ #define SIU_RAMWSCTL_WSEN1_Pos 1 /*!< RAM1 additional waitstate */ #define SIU_RAMWSCTL_WSEN2_Pos 2 /*!< RAM2 additional waitstate */ /* Bit field masks: */ #define SIU_RAMWSCTL_WSEN0_Msk 0x00000001UL /*!< RAM0 additional waitstate */ #define SIU_RAMWSCTL_WSEN1_Msk 0x00000002UL /*!< RAM1 additional waitstate */ #define SIU_RAMWSCTL_WSEN2_Msk 0x00000004UL /*!< RAM2 additional waitstate */ /*-- CHIPID: Chip identifier ---------------------------------------------------------------------------------*/ typedef struct { uint32_t REV :4; /*!< Revision number */ uint32_t ID :28; /*!< Model ID */ } _SIU_CHIPID_bits; /* Bit field positions: */ #define SIU_CHIPID_REV_Pos 0 /*!< Revision number */ #define SIU_CHIPID_ID_Pos 4 /*!< Model ID */ /* Bit field masks: */ #define SIU_CHIPID_REV_Msk 0x0000000FUL /*!< Revision number */ #define SIU_CHIPID_ID_Msk 0xFFFFFFF0UL /*!< Model ID */ typedef struct { __IO uint32_t Reserved0[4]; union { /*!< PWM syncronization control register */ __IO uint32_t PWMSYNC; /*!< PWMSYNC : type used for word access */ __IO _SIU_PWMSYNC_bits PWMSYNC_bit; /*!< PWMSYNC_bit: structure used for bit access */ }; union { /*!< Service mode control register */ __IO uint32_t SERVCTL; /*!< SERVCTL : type used for word access */ __IO _SIU_SERVCTL_bits SERVCTL_bit; /*!< SERVCTL_bit: structure used for bit access */ }; union { /*!< DMA external requests mux control register */ __IO uint32_t DMAMUX; /*!< DMAMUX : type used for word access */ __IO _SIU_DMAMUX_bits DMAMUX_bit; /*!< DMAMUX_bit: structure used for bit access */ }; union { /*!< TMR external clock mux control register */ __IO uint32_t TMRMUX; /*!< TMRMUX : type used for word access */ __IO _SIU_TMRMUX_bits TMRMUX_bit; /*!< TMRMUX_bit: structure used for bit access */ }; union { /*!< CAP input mux control register */ __IO uint32_t CAPMUX; /*!< CAPMUX : type used for word access */ __IO _SIU_CAPMUX_bits CAPMUX_bit; /*!< CAPMUX_bit: structure used for bit access */ }; union { /*!< QEP and CAP qualifier control register */ __IO uint32_t QCQUALCTL; /*!< QCQUALCTL : type used for word access */ __IO _SIU_QCQUALCTL_bits QCQUALCTL_bit; /*!< QCQUALCTL_bit: structure used for bit access */ }; union { /*!< QEP and CAP qualifier sample period set register */ __IO uint32_t QCQUALSAMPLE; /*!< QCQUALSAMPLE : type used for word access */ __IO _SIU_QCQUALSAMPLE_bits QCQUALSAMPLE_bit; /*!< QCQUALSAMPLE_bit: structure used for bit access */ }; union { /*!< RAM waitstates control register */ __IO uint32_t RAMWSCTL; /*!< RAMWSCTL : type used for word access */ __IO _SIU_RAMWSCTL_bits RAMWSCTL_bit; /*!< RAMWSCTL_bit: structure used for bit access */ }; __IO uint32_t Reserved1[1011]; union { /*!< Chip identifier */ __I uint32_t CHIPID; /*!< CHIPID : type used for word access */ __I _SIU_CHIPID_bits CHIPID_bit; /*!< CHIPID_bit: structure used for bit access */ }; } SIU_TypeDef; /******************************************************************************/ /* PMU registers */ /******************************************************************************/ /*-- CFG: PMU Configuration Register -------------------------------------------------------------------------*/ typedef struct { uint32_t EN :1; /*!< Enable PMU */ } _PMU_CFG_bits; /* Bit field positions: */ #define PMU_CFG_EN_Pos 0 /*!< Enable PMU */ /* Bit field masks: */ #define PMU_CFG_EN_Msk 0x00000001UL /*!< Enable PMU */ /*-- PUDEL: PMU Powerup Delay Value --------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :16; /*!< Delay value for powerup peripheral blocks (in REFCLK ticks) */ } _PMU_PUDEL_bits; /* Bit field positions: */ #define PMU_PUDEL_VAL_Pos 0 /*!< Delay value for powerup peripheral blocks (in REFCLK ticks) */ /* Bit field masks: */ #define PMU_PUDEL_VAL_Msk 0x0000FFFFUL /*!< Delay value for powerup peripheral blocks (in REFCLK ticks) */ /*-- PDEN: PMU Enable Powerdown for peripheral ---------------------------------------------------------------*/ typedef struct { uint32_t PLLPD :1; /*!< Enable powerdown for PLL */ uint32_t MFLASHPD :1; /*!< Enable powerdown for MFLASH */ uint32_t BFLASHPD :1; /*!< Enable powerdown for BFLASH */ uint32_t OSEPD :1; /*!< Enable powerdown for external oscillator */ } _PMU_PDEN_bits; /* Bit field positions: */ #define PMU_PDEN_PLLPD_Pos 0 /*!< Enable powerdown for PLL */ #define PMU_PDEN_MFLASHPD_Pos 1 /*!< Enable powerdown for MFLASH */ #define PMU_PDEN_BFLASHPD_Pos 2 /*!< Enable powerdown for BFLASH */ #define PMU_PDEN_OSEPD_Pos 3 /*!< Enable powerdown for external oscillator */ /* Bit field masks: */ #define PMU_PDEN_PLLPD_Msk 0x00000001UL /*!< Enable powerdown for PLL */ #define PMU_PDEN_MFLASHPD_Msk 0x00000002UL /*!< Enable powerdown for MFLASH */ #define PMU_PDEN_BFLASHPD_Msk 0x00000004UL /*!< Enable powerdown for BFLASH */ #define PMU_PDEN_OSEPD_Msk 0x00000008UL /*!< Enable powerdown for external oscillator */ /*-- RXEVEN: PMU RX Event generation enable register ---------------------------------------------------------*/ typedef struct { uint32_t GPIOAEV :1; /*!< Enable RX event from GPIOA pins */ uint32_t GPIOBEV :1; /*!< Enable RX event from GPIOB pins */ uint32_t GPIOCEV :1; /*!< Enable RX event from GPIOC pins */ uint32_t GPIODEV :1; /*!< Enable RX event from GPIOD pins */ uint32_t GPIOEEV :1; /*!< Enable RX event from GPIOE pins */ uint32_t GPIOFEV :1; /*!< Enable RX event from GPIOF pins */ uint32_t GPIOGEV :1; /*!< Enable RX event from GPIOG pins */ uint32_t GPIOHEV :1; /*!< Enable RX event from GPIOH pins */ uint32_t GPIOJEV :1; /*!< Enable RX event from GPIOJ pins */ uint32_t GPIOKEV :1; /*!< Enable RX event from GPIOK pins */ uint32_t GPIOLEV :1; /*!< Enable RX event from GPIOL pins */ uint32_t GPIOMEV :1; /*!< Enable RX event from GPIOM pins */ } _PMU_RXEVEN_bits; /* Bit field positions: */ #define PMU_RXEVEN_GPIOAEV_Pos 0 /*!< Enable RX event from GPIOA pins */ #define PMU_RXEVEN_GPIOBEV_Pos 1 /*!< Enable RX event from GPIOB pins */ #define PMU_RXEVEN_GPIOCEV_Pos 2 /*!< Enable RX event from GPIOC pins */ #define PMU_RXEVEN_GPIODEV_Pos 3 /*!< Enable RX event from GPIOD pins */ #define PMU_RXEVEN_GPIOEEV_Pos 4 /*!< Enable RX event from GPIOE pins */ #define PMU_RXEVEN_GPIOFEV_Pos 5 /*!< Enable RX event from GPIOF pins */ #define PMU_RXEVEN_GPIOGEV_Pos 6 /*!< Enable RX event from GPIOG pins */ #define PMU_RXEVEN_GPIOHEV_Pos 7 /*!< Enable RX event from GPIOH pins */ #define PMU_RXEVEN_GPIOJEV_Pos 8 /*!< Enable RX event from GPIOJ pins */ #define PMU_RXEVEN_GPIOKEV_Pos 9 /*!< Enable RX event from GPIOK pins */ #define PMU_RXEVEN_GPIOLEV_Pos 10 /*!< Enable RX event from GPIOL pins */ #define PMU_RXEVEN_GPIOMEV_Pos 11 /*!< Enable RX event from GPIOM pins */ /* Bit field masks: */ #define PMU_RXEVEN_GPIOAEV_Msk 0x00000001UL /*!< Enable RX event from GPIOA pins */ #define PMU_RXEVEN_GPIOBEV_Msk 0x00000002UL /*!< Enable RX event from GPIOB pins */ #define PMU_RXEVEN_GPIOCEV_Msk 0x00000004UL /*!< Enable RX event from GPIOC pins */ #define PMU_RXEVEN_GPIODEV_Msk 0x00000008UL /*!< Enable RX event from GPIOD pins */ #define PMU_RXEVEN_GPIOEEV_Msk 0x00000010UL /*!< Enable RX event from GPIOE pins */ #define PMU_RXEVEN_GPIOFEV_Msk 0x00000020UL /*!< Enable RX event from GPIOF pins */ #define PMU_RXEVEN_GPIOGEV_Msk 0x00000040UL /*!< Enable RX event from GPIOG pins */ #define PMU_RXEVEN_GPIOHEV_Msk 0x00000080UL /*!< Enable RX event from GPIOH pins */ #define PMU_RXEVEN_GPIOJEV_Msk 0x00000100UL /*!< Enable RX event from GPIOJ pins */ #define PMU_RXEVEN_GPIOKEV_Msk 0x00000200UL /*!< Enable RX event from GPIOK pins */ #define PMU_RXEVEN_GPIOLEV_Msk 0x00000400UL /*!< Enable RX event from GPIOL pins */ #define PMU_RXEVEN_GPIOMEV_Msk 0x00000800UL /*!< Enable RX event from GPIOM pins */ /*-- ADCPC: ADC Power Control --------------------------------------------------------------------------------*/ typedef struct { uint32_t LDOEN0 :1; /*!< Enable LDO of ADC0 */ uint32_t LDOEN1 :1; /*!< Enable LDO of ADC1 */ uint32_t LDOEN2 :1; /*!< Enable LDO of ADC2 */ uint32_t LDOEN3 :1; /*!< Enable LDO of ADC3 */ uint32_t :4; /*!< RESERVED */ uint32_t LDORDY0 :1; /*!< ADC0 LDO ready status */ uint32_t LDORDY1 :1; /*!< ADC1 LDO ready status */ uint32_t LDORDY2 :1; /*!< ADC2 LDO ready status */ uint32_t LDORDY3 :1; /*!< ADC3 LDO ready status */ } _PMU_ADCPC_bits; /* Bit field positions: */ #define PMU_ADCPC_LDOEN0_Pos 0 /*!< Enable LDO of ADC0 */ #define PMU_ADCPC_LDOEN1_Pos 1 /*!< Enable LDO of ADC1 */ #define PMU_ADCPC_LDOEN2_Pos 2 /*!< Enable LDO of ADC2 */ #define PMU_ADCPC_LDOEN3_Pos 3 /*!< Enable LDO of ADC3 */ #define PMU_ADCPC_LDORDY0_Pos 8 /*!< ADC0 LDO ready status */ #define PMU_ADCPC_LDORDY1_Pos 9 /*!< ADC1 LDO ready status */ #define PMU_ADCPC_LDORDY2_Pos 10 /*!< ADC2 LDO ready status */ #define PMU_ADCPC_LDORDY3_Pos 11 /*!< ADC3 LDO ready status */ /* Bit field masks: */ #define PMU_ADCPC_LDOEN0_Msk 0x00000001UL /*!< Enable LDO of ADC0 */ #define PMU_ADCPC_LDOEN1_Msk 0x00000002UL /*!< Enable LDO of ADC1 */ #define PMU_ADCPC_LDOEN2_Msk 0x00000004UL /*!< Enable LDO of ADC2 */ #define PMU_ADCPC_LDOEN3_Msk 0x00000008UL /*!< Enable LDO of ADC3 */ #define PMU_ADCPC_LDORDY0_Msk 0x00000100UL /*!< ADC0 LDO ready status */ #define PMU_ADCPC_LDORDY1_Msk 0x00000200UL /*!< ADC1 LDO ready status */ #define PMU_ADCPC_LDORDY2_Msk 0x00000400UL /*!< ADC2 LDO ready status */ #define PMU_ADCPC_LDORDY3_Msk 0x00000800UL /*!< ADC3 LDO ready status */ typedef struct { union { /*!< PMU Configuration Register */ __IO uint32_t CFG; /*!< CFG : type used for word access */ __IO _PMU_CFG_bits CFG_bit; /*!< CFG_bit: structure used for bit access */ }; union { /*!< PMU Powerup Delay Value */ __IO uint32_t PUDEL; /*!< PUDEL : type used for word access */ __IO _PMU_PUDEL_bits PUDEL_bit; /*!< PUDEL_bit: structure used for bit access */ }; union { /*!< PMU Enable Powerdown for peripheral */ __IO uint32_t PDEN; /*!< PDEN : type used for word access */ __IO _PMU_PDEN_bits PDEN_bit; /*!< PDEN_bit: structure used for bit access */ }; union { /*!< PMU RX Event generation enable register */ __IO uint32_t RXEVEN; /*!< RXEVEN : type used for word access */ __IO _PMU_RXEVEN_bits RXEVEN_bit; /*!< RXEVEN_bit: structure used for bit access */ }; union { /*!< ADC Power Control */ __IO uint32_t ADCPC; /*!< ADCPC : type used for word access */ __IO _PMU_ADCPC_bits ADCPC_bit; /*!< ADCPC_bit: structure used for bit access */ }; } PMU_TypeDef; /******************************************************************************/ /* WDT registers */ /******************************************************************************/ /*-- LOAD: Watchdog Load Register ----------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Begin value counter */ } _WDT_LOAD_bits; /* Bit field positions: */ #define WDT_LOAD_VAL_Pos 0 /*!< Begin value counter */ /* Bit field masks: */ #define WDT_LOAD_VAL_Msk 0xFFFFFFFFUL /*!< Begin value counter */ /*-- VALUE: Watchdog Value Register --------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Current value counter */ } _WDT_VALUE_bits; /* Bit field positions: */ #define WDT_VALUE_VAL_Pos 0 /*!< Current value counter */ /* Bit field masks: */ #define WDT_VALUE_VAL_Msk 0xFFFFFFFFUL /*!< Current value counter */ /*-- CTRL: Watchdog Control Register -------------------------------------------------------------------------*/ typedef struct { uint32_t INTEN :1; /*!< Enable the interrupt event */ uint32_t RESEN :1; /*!< Enable watchdog reset output */ } _WDT_CTRL_bits; /* Bit field positions: */ #define WDT_CTRL_INTEN_Pos 0 /*!< Enable the interrupt event */ #define WDT_CTRL_RESEN_Pos 1 /*!< Enable watchdog reset output */ /* Bit field masks: */ #define WDT_CTRL_INTEN_Msk 0x00000001UL /*!< Enable the interrupt event */ #define WDT_CTRL_RESEN_Msk 0x00000002UL /*!< Enable watchdog reset output */ /*-- INTCLR: Watchdog Clear Interrupt Register ---------------------------------------------------------------*/ typedef struct { uint32_t WDTCLR :32; /*!< Reset interrupt WDT */ } _WDT_INTCLR_bits; /* Bit field positions: */ #define WDT_INTCLR_WDTCLR_Pos 0 /*!< Reset interrupt WDT */ /* Bit field masks: */ #define WDT_INTCLR_WDTCLR_Msk 0xFFFFFFFFUL /*!< Reset interrupt WDT */ /*-- RIS: Watchdog Raw Interrupt Status Register -------------------------------------------------------------*/ typedef struct { uint32_t RAWWDTINT :1; /*!< Raw interrupt status from the counter */ } _WDT_RIS_bits; /* Bit field positions: */ #define WDT_RIS_RAWWDTINT_Pos 0 /*!< Raw interrupt status from the counter */ /* Bit field masks: */ #define WDT_RIS_RAWWDTINT_Msk 0x00000001UL /*!< Raw interrupt status from the counter */ /*-- MIS: Watchdog Interrupt Status Register -----------------------------------------------------------------*/ typedef struct { uint32_t WDTINT :1; /*!< Enabled interrupt status from the counter */ } _WDT_MIS_bits; /* Bit field positions: */ #define WDT_MIS_WDTINT_Pos 0 /*!< Enabled interrupt status from the counter */ /* Bit field masks: */ #define WDT_MIS_WDTINT_Msk 0x00000001UL /*!< Enabled interrupt status from the counter */ /*-- LOCK: Watchdog Lock Register ----------------------------------------------------------------------------*/ typedef struct { uint32_t REGWRDIS :1; /*!< Disable write to all registers Watchdog */ } _WDT_LOCK_bits; /* Bit field positions: */ #define WDT_LOCK_REGWRDIS_Pos 0 /*!< Disable write to all registers Watchdog */ /* Bit field masks: */ #define WDT_LOCK_REGWRDIS_Msk 0x00000001UL /*!< Disable write to all registers Watchdog */ typedef struct { union { /*!< Watchdog Load Register */ __IO uint32_t LOAD; /*!< LOAD : type used for word access */ __IO _WDT_LOAD_bits LOAD_bit; /*!< LOAD_bit: structure used for bit access */ }; union { /*!< Watchdog Value Register */ __I uint32_t VALUE; /*!< VALUE : type used for word access */ __I _WDT_VALUE_bits VALUE_bit; /*!< VALUE_bit: structure used for bit access */ }; union { /*!< Watchdog Control Register */ __IO uint32_t CTRL; /*!< CTRL : type used for word access */ __IO _WDT_CTRL_bits CTRL_bit; /*!< CTRL_bit: structure used for bit access */ }; union { /*!< Watchdog Clear Interrupt Register */ __O uint32_t INTCLR; /*!< INTCLR : type used for word access */ __O _WDT_INTCLR_bits INTCLR_bit; /*!< INTCLR_bit: structure used for bit access */ }; union { /*!< Watchdog Raw Interrupt Status Register */ __I uint32_t RIS; /*!< RIS : type used for word access */ __I _WDT_RIS_bits RIS_bit; /*!< RIS_bit: structure used for bit access */ }; union { /*!< Watchdog Interrupt Status Register */ __I uint32_t MIS; /*!< MIS : type used for word access */ __I _WDT_MIS_bits MIS_bit; /*!< MIS_bit: structure used for bit access */ }; __IO uint32_t Reserved0[762]; union { /*!< Watchdog Lock Register */ __O uint32_t LOCK; /*!< LOCK : type used for word access */ __O _WDT_LOCK_bits LOCK_bit; /*!< LOCK_bit: structure used for bit access */ }; } WDT_TypeDef; /******************************************************************************/ /* TMR registers */ /******************************************************************************/ /*-- CTRL: Control Timer register ----------------------------------------------------------------------------*/ typedef struct { uint32_t ON :1; /*!< Enable Timer */ uint32_t EXTINEN :1; /*!< Enable external input as ENABLE */ uint32_t EXTINCLK :1; /*!< Enable external input as CLK */ uint32_t INTEN :1; /*!< Enable Timer interrupt */ } _TMR_CTRL_bits; /* Bit field positions: */ #define TMR_CTRL_ON_Pos 0 /*!< Enable Timer */ #define TMR_CTRL_EXTINEN_Pos 1 /*!< Enable external input as ENABLE */ #define TMR_CTRL_EXTINCLK_Pos 2 /*!< Enable external input as CLK */ #define TMR_CTRL_INTEN_Pos 3 /*!< Enable Timer interrupt */ /* Bit field masks: */ #define TMR_CTRL_ON_Msk 0x00000001UL /*!< Enable Timer */ #define TMR_CTRL_EXTINEN_Msk 0x00000002UL /*!< Enable external input as ENABLE */ #define TMR_CTRL_EXTINCLK_Msk 0x00000004UL /*!< Enable external input as CLK */ #define TMR_CTRL_INTEN_Msk 0x00000008UL /*!< Enable Timer interrupt */ /*-- VALUE: Current value timer register ---------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Current value timer */ } _TMR_VALUE_bits; /* Bit field positions: */ #define TMR_VALUE_VAL_Pos 0 /*!< Current value timer */ /* Bit field masks: */ #define TMR_VALUE_VAL_Msk 0xFFFFFFFFUL /*!< Current value timer */ /*-- LOAD: Reload value timer register -----------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Reload value. A write to this register sets the current value */ } _TMR_LOAD_bits; /* Bit field positions: */ #define TMR_LOAD_VAL_Pos 0 /*!< Reload value. A write to this register sets the current value */ /* Bit field masks: */ #define TMR_LOAD_VAL_Msk 0xFFFFFFFFUL /*!< Reload value. A write to this register sets the current value */ /*-- INTSTATUS: Interrupt status register --------------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< Timer interrupt flag */ } _TMR_INTSTATUS_bits; /* Bit field positions: */ #define TMR_INTSTATUS_INT_Pos 0 /*!< Timer interrupt flag */ /* Bit field masks: */ #define TMR_INTSTATUS_INT_Msk 0x00000001UL /*!< Timer interrupt flag */ /*-- DMAREQ: DMA request register ----------------------------------------------------------------------------*/ typedef struct { uint32_t EN :1; /*!< */ } _TMR_DMAREQ_bits; /* Bit field positions: */ #define TMR_DMAREQ_EN_Pos 0 /*!< */ /* Bit field masks: */ #define TMR_DMAREQ_EN_Msk 0x00000001UL /*!< */ /*-- ADCSOC: ADC start of conversion register ----------------------------------------------------------------*/ typedef struct { uint32_t EN :1; /*!< */ } _TMR_ADCSOC_bits; /* Bit field positions: */ #define TMR_ADCSOC_EN_Pos 0 /*!< */ /* Bit field masks: */ #define TMR_ADCSOC_EN_Msk 0x00000001UL /*!< */ typedef struct { union { /*!< Control Timer register */ __IO uint32_t CTRL; /*!< CTRL : type used for word access */ __IO _TMR_CTRL_bits CTRL_bit; /*!< CTRL_bit: structure used for bit access */ }; union { /*!< Current value timer register */ __IO uint32_t VALUE; /*!< VALUE : type used for word access */ __IO _TMR_VALUE_bits VALUE_bit; /*!< VALUE_bit: structure used for bit access */ }; union { /*!< Reload value timer register */ __IO uint32_t LOAD; /*!< LOAD : type used for word access */ __IO _TMR_LOAD_bits LOAD_bit; /*!< LOAD_bit: structure used for bit access */ }; union { /*!< Interrupt status register */ __IO uint32_t INTSTATUS; /*!< INTSTATUS : type used for word access */ __IO _TMR_INTSTATUS_bits INTSTATUS_bit; /*!< INTSTATUS_bit: structure used for bit access */ }; union { /*!< DMA request register */ __IO uint32_t DMAREQ; /*!< DMAREQ : type used for word access */ __IO _TMR_DMAREQ_bits DMAREQ_bit; /*!< DMAREQ_bit: structure used for bit access */ }; union { /*!< ADC start of conversion register */ __IO uint32_t ADCSOC; /*!< ADCSOC : type used for word access */ __IO _TMR_ADCSOC_bits ADCSOC_bit; /*!< ADCSOC_bit: structure used for bit access */ }; } TMR_TypeDef; /******************************************************************************/ /* ETMR registers */ /******************************************************************************/ /*-- LOAD: Load register -------------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Load register */ } _ETMR_LOAD_bits; /* Bit field positions: */ #define ETMR_LOAD_VAL_Pos 0 /*!< Load register */ /* Bit field masks: */ #define ETMR_LOAD_VAL_Msk 0xFFFFFFFFUL /*!< Load register */ /*-- VALUE: Current value timer register ---------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Current value timer */ } _ETMR_VALUE_bits; /* Bit field positions: */ #define ETMR_VALUE_VAL_Pos 0 /*!< Current value timer */ /* Bit field masks: */ #define ETMR_VALUE_VAL_Msk 0xFFFFFFFFUL /*!< Current value timer */ /*-- CTRL: Timer control register ----------------------------------------------------------------------------*/ typedef struct { uint32_t ONESH :1; /*!< One-shot count */ uint32_t SIZE32 :1; /*!< Select size if counter: 16 or 32 bit */ uint32_t PRESC :2; /*!< Precaler select */ uint32_t :1; /*!< RESERVED */ uint32_t INTEN :1; /*!< Interrupt enable */ uint32_t PERMODE :1; /*!< Select timer mode: free-run or periodic */ uint32_t ON :1; /*!< Enable timer */ } _ETMR_CTRL_bits; /* Bit field positions: */ #define ETMR_CTRL_ONESH_Pos 0 /*!< One-shot count */ #define ETMR_CTRL_SIZE32_Pos 1 /*!< Select size if counter: 16 or 32 bit */ #define ETMR_CTRL_PRESC_Pos 2 /*!< Precaler select */ #define ETMR_CTRL_INTEN_Pos 5 /*!< Interrupt enable */ #define ETMR_CTRL_PERMODE_Pos 6 /*!< Select timer mode: free-run or periodic */ #define ETMR_CTRL_ON_Pos 7 /*!< Enable timer */ /* Bit field masks: */ #define ETMR_CTRL_ONESH_Msk 0x00000001UL /*!< One-shot count */ #define ETMR_CTRL_SIZE32_Msk 0x00000002UL /*!< Select size if counter: 16 or 32 bit */ #define ETMR_CTRL_PRESC_Msk 0x0000000CUL /*!< Precaler select */ #define ETMR_CTRL_INTEN_Msk 0x00000020UL /*!< Interrupt enable */ #define ETMR_CTRL_PERMODE_Msk 0x00000040UL /*!< Select timer mode: free-run or periodic */ #define ETMR_CTRL_ON_Msk 0x00000080UL /*!< Enable timer */ /*-- INTCLR: Interrupt clear register ------------------------------------------------------------------------*/ typedef struct { uint32_t INTCLR :1; /*!< Clear timer interrupt */ } _ETMR_INTCLR_bits; /* Bit field positions: */ #define ETMR_INTCLR_INTCLR_Pos 0 /*!< Clear timer interrupt */ /* Bit field masks: */ #define ETMR_INTCLR_INTCLR_Msk 0x00000001UL /*!< Clear timer interrupt */ /*-- RIS: Raw interrupt status register ----------------------------------------------------------------------*/ typedef struct { uint32_t RINT :1; /*!< Raw interrupt status flag */ } _ETMR_RIS_bits; /* Bit field positions: */ #define ETMR_RIS_RINT_Pos 0 /*!< Raw interrupt status flag */ /* Bit field masks: */ #define ETMR_RIS_RINT_Msk 0x00000001UL /*!< Raw interrupt status flag */ /*-- MIS: Interrupt status register --------------------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< Timer interrupt flag */ } _ETMR_MIS_bits; /* Bit field positions: */ #define ETMR_MIS_INT_Pos 0 /*!< Timer interrupt flag */ /* Bit field masks: */ #define ETMR_MIS_INT_Msk 0x00000001UL /*!< Timer interrupt flag */ /*-- BGLOAD: Background load register ------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Background load register */ } _ETMR_BGLOAD_bits; /* Bit field positions: */ #define ETMR_BGLOAD_VAL_Pos 0 /*!< Background load register */ /* Bit field masks: */ #define ETMR_BGLOAD_VAL_Msk 0xFFFFFFFFUL /*!< Background load register */ /*-- DMAREQ: DMA request register ----------------------------------------------------------------------------*/ typedef struct { uint32_t EN :1; /*!< */ } _ETMR_DMAREQ_bits; /* Bit field positions: */ #define ETMR_DMAREQ_EN_Pos 0 /*!< */ /* Bit field masks: */ #define ETMR_DMAREQ_EN_Msk 0x00000001UL /*!< */ typedef struct { union { /*!< Load register */ __IO uint32_t LOAD; /*!< LOAD : type used for word access */ __IO _ETMR_LOAD_bits LOAD_bit; /*!< LOAD_bit: structure used for bit access */ }; union { /*!< Current value timer register */ __I uint32_t VALUE; /*!< VALUE : type used for word access */ __I _ETMR_VALUE_bits VALUE_bit; /*!< VALUE_bit: structure used for bit access */ }; union { /*!< Timer control register */ __IO uint32_t CTRL; /*!< CTRL : type used for word access */ __IO _ETMR_CTRL_bits CTRL_bit; /*!< CTRL_bit: structure used for bit access */ }; union { /*!< Interrupt clear register */ __O uint32_t INTCLR; /*!< INTCLR : type used for word access */ __O _ETMR_INTCLR_bits INTCLR_bit; /*!< INTCLR_bit: structure used for bit access */ }; union { /*!< Raw interrupt status register */ __I uint32_t RIS; /*!< RIS : type used for word access */ __I _ETMR_RIS_bits RIS_bit; /*!< RIS_bit: structure used for bit access */ }; union { /*!< Interrupt status register */ __I uint32_t MIS; /*!< MIS : type used for word access */ __I _ETMR_MIS_bits MIS_bit; /*!< MIS_bit: structure used for bit access */ }; union { /*!< Background load register */ __IO uint32_t BGLOAD; /*!< BGLOAD : type used for word access */ __IO _ETMR_BGLOAD_bits BGLOAD_bit; /*!< BGLOAD_bit: structure used for bit access */ }; union { /*!< DMA request register */ __IO uint32_t DMAREQ; /*!< DMAREQ : type used for word access */ __IO _ETMR_DMAREQ_bits DMAREQ_bit; /*!< DMAREQ_bit: structure used for bit access */ }; } ETMR_TypeDef; /******************************************************************************/ /* TMU registers */ /******************************************************************************/ /*-- XIN: X input register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< X input value */ } _TMU_XIN_bits; /* Bit field positions: */ #define TMU_XIN_VAL_Pos 0 /*!< X input value */ /* Bit field masks: */ #define TMU_XIN_VAL_Msk 0xFFFFFFFFUL /*!< X input value */ /*-- YIN: Y input register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Y input value */ } _TMU_YIN_bits; /* Bit field positions: */ #define TMU_YIN_VAL_Pos 0 /*!< Y input value */ /* Bit field masks: */ #define TMU_YIN_VAL_Msk 0xFFFFFFFFUL /*!< Y input value */ /*-- PHIN: Phase input register ------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Phase input value */ } _TMU_PHIN_bits; /* Bit field positions: */ #define TMU_PHIN_VAL_Pos 0 /*!< Phase input value */ /* Bit field masks: */ #define TMU_PHIN_VAL_Msk 0xFFFFFFFFUL /*!< Phase input value */ /*-- CMD: Command register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t START :1; /*!< Start calculations */ uint32_t :3; /*!< RESERVED */ uint32_t FUNC :4; /*!< Select function to compute */ uint32_t ARGT :5; /*!< Input and output argument type: 0-Q28, 1-Q27, . . ., 20-Q8, 31-FP */ uint32_t :3; /*!< RESERVED */ uint32_t WAITRD :1; /*!< Wait calculation complete when any output register read */ uint32_t DONEIRQ :1; /*!< Generate interrupt when calculation done */ uint32_t EXCIRQ :1; /*!< Generate interrupt when any exception happend */ uint32_t DMAREQ :1; /*!< Generate DMA request when calculation done */ } _TMU_CMD_bits; /* Bit field positions: */ #define TMU_CMD_START_Pos 0 /*!< Start calculations */ #define TMU_CMD_FUNC_Pos 4 /*!< Select function to compute */ #define TMU_CMD_ARGT_Pos 8 /*!< Input and output argument type: 0-Q28, 1-Q27, . . ., 20-Q8, 31-FP */ #define TMU_CMD_WAITRD_Pos 16 /*!< Wait calculation complete when any output register read */ #define TMU_CMD_DONEIRQ_Pos 17 /*!< Generate interrupt when calculation done */ #define TMU_CMD_EXCIRQ_Pos 18 /*!< Generate interrupt when any exception happend */ #define TMU_CMD_DMAREQ_Pos 19 /*!< Generate DMA request when calculation done */ /* Bit field masks: */ #define TMU_CMD_START_Msk 0x00000001UL /*!< Start calculations */ #define TMU_CMD_FUNC_Msk 0x000000F0UL /*!< Select function to compute */ #define TMU_CMD_ARGT_Msk 0x00001F00UL /*!< Input and output argument type: 0-Q28, 1-Q27, . . ., 20-Q8, 31-FP */ #define TMU_CMD_WAITRD_Msk 0x00010000UL /*!< Wait calculation complete when any output register read */ #define TMU_CMD_DONEIRQ_Msk 0x00020000UL /*!< Generate interrupt when calculation done */ #define TMU_CMD_EXCIRQ_Msk 0x00040000UL /*!< Generate interrupt when any exception happend */ #define TMU_CMD_DMAREQ_Msk 0x00080000UL /*!< Generate DMA request when calculation done */ /* Bit field enums: */ typedef enum { TMU_CMD_FUNC_SinCos = 0x0UL, /*!< sine and cosine functions */ TMU_CMD_FUNC_Rect2Pol = 0x1UL, /*!< rectangular to polar coordinates */ TMU_CMD_FUNC_Pol2Rect = 0x2UL, /*!< polar to rectangular coordinates */ TMU_CMD_FUNC_Rot = 0x3UL, /*!< Vector rotation */ } TMU_CMD_FUNC_Enum; /*-- XOUT: X output register ---------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< X output value */ } _TMU_XOUT_bits; /* Bit field positions: */ #define TMU_XOUT_VAL_Pos 0 /*!< X output value */ /* Bit field masks: */ #define TMU_XOUT_VAL_Msk 0xFFFFFFFFUL /*!< X output value */ /*-- YOUT: Y output register ---------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Y output value */ } _TMU_YOUT_bits; /* Bit field positions: */ #define TMU_YOUT_VAL_Pos 0 /*!< Y output value */ /* Bit field masks: */ #define TMU_YOUT_VAL_Msk 0xFFFFFFFFUL /*!< Y output value */ /*-- PHOUT: Phase output register ----------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Phase output value */ } _TMU_PHOUT_bits; /* Bit field positions: */ #define TMU_PHOUT_VAL_Pos 0 /*!< Phase output value */ /* Bit field masks: */ #define TMU_PHOUT_VAL_Msk 0xFFFFFFFFUL /*!< Phase output value */ /*-- STAT: Status register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t DONE :1; /*!< Calculation done status */ uint32_t :3; /*!< RESERVED */ uint32_t XNAN :1; /*!< XIN value is NaN exception status */ uint32_t XINF :1; /*!< XIN value is INF exception status */ uint32_t XUNF :1; /*!< XIN value is few than min alowed number exception status */ uint32_t XOVF :1; /*!< XIN value is bigger than max alowed number exception status */ uint32_t YNAN :1; /*!< YIN value is NaN exception status */ uint32_t YINF :1; /*!< YIN value is INF exception status */ uint32_t YUNF :1; /*!< YIN value is few than min alowed number exception status */ uint32_t YOVF :1; /*!< YIN value is bigger than max alowed number exception status */ uint32_t PHNAN :1; /*!< PHIN value is NaN exception status */ uint32_t PHINF :1; /*!< PHIN value is INF exception status */ uint32_t PHUNF :1; /*!< PHIN value is few than min alowed number exception status */ uint32_t PHOVF :1; /*!< PHIN value is bigger than max alowed number exception status */ } _TMU_STAT_bits; /* Bit field positions: */ #define TMU_STAT_DONE_Pos 0 /*!< Calculation done status */ #define TMU_STAT_XNAN_Pos 4 /*!< XIN value is NaN exception status */ #define TMU_STAT_XINF_Pos 5 /*!< XIN value is INF exception status */ #define TMU_STAT_XUNF_Pos 6 /*!< XIN value is few than min alowed number exception status */ #define TMU_STAT_XOVF_Pos 7 /*!< XIN value is bigger than max alowed number exception status */ #define TMU_STAT_YNAN_Pos 8 /*!< YIN value is NaN exception status */ #define TMU_STAT_YINF_Pos 9 /*!< YIN value is INF exception status */ #define TMU_STAT_YUNF_Pos 10 /*!< YIN value is few than min alowed number exception status */ #define TMU_STAT_YOVF_Pos 11 /*!< YIN value is bigger than max alowed number exception status */ #define TMU_STAT_PHNAN_Pos 12 /*!< PHIN value is NaN exception status */ #define TMU_STAT_PHINF_Pos 13 /*!< PHIN value is INF exception status */ #define TMU_STAT_PHUNF_Pos 14 /*!< PHIN value is few than min alowed number exception status */ #define TMU_STAT_PHOVF_Pos 15 /*!< PHIN value is bigger than max alowed number exception status */ /* Bit field masks: */ #define TMU_STAT_DONE_Msk 0x00000001UL /*!< Calculation done status */ #define TMU_STAT_XNAN_Msk 0x00000010UL /*!< XIN value is NaN exception status */ #define TMU_STAT_XINF_Msk 0x00000020UL /*!< XIN value is INF exception status */ #define TMU_STAT_XUNF_Msk 0x00000040UL /*!< XIN value is few than min alowed number exception status */ #define TMU_STAT_XOVF_Msk 0x00000080UL /*!< XIN value is bigger than max alowed number exception status */ #define TMU_STAT_YNAN_Msk 0x00000100UL /*!< YIN value is NaN exception status */ #define TMU_STAT_YINF_Msk 0x00000200UL /*!< YIN value is INF exception status */ #define TMU_STAT_YUNF_Msk 0x00000400UL /*!< YIN value is few than min alowed number exception status */ #define TMU_STAT_YOVF_Msk 0x00000800UL /*!< YIN value is bigger than max alowed number exception status */ #define TMU_STAT_PHNAN_Msk 0x00001000UL /*!< PHIN value is NaN exception status */ #define TMU_STAT_PHINF_Msk 0x00002000UL /*!< PHIN value is INF exception status */ #define TMU_STAT_PHUNF_Msk 0x00004000UL /*!< PHIN value is few than min alowed number exception status */ #define TMU_STAT_PHOVF_Msk 0x00008000UL /*!< PHIN value is bigger than max alowed number exception status */ typedef struct { union { /*!< X input register */ __IO uint32_t XIN; /*!< XIN : type used for word access */ __IO _TMU_XIN_bits XIN_bit; /*!< XIN_bit: structure used for bit access */ }; union { /*!< Y input register */ __IO uint32_t YIN; /*!< YIN : type used for word access */ __IO _TMU_YIN_bits YIN_bit; /*!< YIN_bit: structure used for bit access */ }; union { /*!< Phase input register */ __IO uint32_t PHIN; /*!< PHIN : type used for word access */ __IO _TMU_PHIN_bits PHIN_bit; /*!< PHIN_bit: structure used for bit access */ }; union { /*!< Command register */ __IO uint32_t CMD; /*!< CMD : type used for word access */ __IO _TMU_CMD_bits CMD_bit; /*!< CMD_bit: structure used for bit access */ }; union { /*!< X output register */ __IO uint32_t XOUT; /*!< XOUT : type used for word access */ __IO _TMU_XOUT_bits XOUT_bit; /*!< XOUT_bit: structure used for bit access */ }; union { /*!< Y output register */ __IO uint32_t YOUT; /*!< YOUT : type used for word access */ __IO _TMU_YOUT_bits YOUT_bit; /*!< YOUT_bit: structure used for bit access */ }; union { /*!< Phase output register */ __IO uint32_t PHOUT; /*!< PHOUT : type used for word access */ __IO _TMU_PHOUT_bits PHOUT_bit; /*!< PHOUT_bit: structure used for bit access */ }; union { /*!< Status register */ __IO uint32_t STAT; /*!< STAT : type used for word access */ __IO _TMU_STAT_bits STAT_bit; /*!< STAT_bit: structure used for bit access */ }; } TMU_TypeDef; /******************************************************************************/ /* ADC registers */ /******************************************************************************/ /*-- SEQEN: Enable sequencer register ------------------------------------------------------------------------*/ typedef struct { uint32_t SEQEN0 :1; /*!< Enable sequencer 0 */ uint32_t SEQEN1 :1; /*!< Enable sequencer 1 */ uint32_t SEQEN2 :1; /*!< Enable sequencer 2 */ uint32_t SEQEN3 :1; /*!< Enable sequencer 3 */ uint32_t SEQEN4 :1; /*!< Enable sequencer 4 */ uint32_t SEQEN5 :1; /*!< Enable sequencer 5 */ uint32_t SEQEN6 :1; /*!< Enable sequencer 6 */ uint32_t SEQEN7 :1; /*!< Enable sequencer 7 */ } _ADC_SEQEN_bits; /* Bit field positions: */ #define ADC_SEQEN_SEQEN0_Pos 0 /*!< Enable sequencer 0 */ #define ADC_SEQEN_SEQEN1_Pos 1 /*!< Enable sequencer 1 */ #define ADC_SEQEN_SEQEN2_Pos 2 /*!< Enable sequencer 2 */ #define ADC_SEQEN_SEQEN3_Pos 3 /*!< Enable sequencer 3 */ #define ADC_SEQEN_SEQEN4_Pos 4 /*!< Enable sequencer 4 */ #define ADC_SEQEN_SEQEN5_Pos 5 /*!< Enable sequencer 5 */ #define ADC_SEQEN_SEQEN6_Pos 6 /*!< Enable sequencer 6 */ #define ADC_SEQEN_SEQEN7_Pos 7 /*!< Enable sequencer 7 */ /* Bit field masks: */ #define ADC_SEQEN_SEQEN0_Msk 0x00000001UL /*!< Enable sequencer 0 */ #define ADC_SEQEN_SEQEN1_Msk 0x00000002UL /*!< Enable sequencer 1 */ #define ADC_SEQEN_SEQEN2_Msk 0x00000004UL /*!< Enable sequencer 2 */ #define ADC_SEQEN_SEQEN3_Msk 0x00000008UL /*!< Enable sequencer 3 */ #define ADC_SEQEN_SEQEN4_Msk 0x00000010UL /*!< Enable sequencer 4 */ #define ADC_SEQEN_SEQEN5_Msk 0x00000020UL /*!< Enable sequencer 5 */ #define ADC_SEQEN_SEQEN6_Msk 0x00000040UL /*!< Enable sequencer 6 */ #define ADC_SEQEN_SEQEN7_Msk 0x00000080UL /*!< Enable sequencer 7 */ /*-- SEQSYNC: Sequencer sync register ------------------------------------------------------------------------*/ typedef struct { uint32_t SYNC0 :1; /*!< Enable sequencer 0 software sync */ uint32_t SYNC1 :1; /*!< Enable sequencer 1 software sync */ uint32_t SYNC2 :1; /*!< Enable sequencer 2 software sync */ uint32_t SYNC3 :1; /*!< Enable sequencer 3 software sync */ uint32_t SYNC4 :1; /*!< Enable sequencer 4 software sync */ uint32_t SYNC5 :1; /*!< Enable sequencer 5 software sync */ uint32_t SYNC6 :1; /*!< Enable sequencer 6 software sync */ uint32_t SYNC7 :1; /*!< Enable sequencer 7 software sync */ uint32_t :23; /*!< RESERVED */ uint32_t GSYNC :1; /*!< Sync all sequencers */ } _ADC_SEQSYNC_bits; /* Bit field positions: */ #define ADC_SEQSYNC_SYNC0_Pos 0 /*!< Enable sequencer 0 software sync */ #define ADC_SEQSYNC_SYNC1_Pos 1 /*!< Enable sequencer 1 software sync */ #define ADC_SEQSYNC_SYNC2_Pos 2 /*!< Enable sequencer 2 software sync */ #define ADC_SEQSYNC_SYNC3_Pos 3 /*!< Enable sequencer 3 software sync */ #define ADC_SEQSYNC_SYNC4_Pos 4 /*!< Enable sequencer 4 software sync */ #define ADC_SEQSYNC_SYNC5_Pos 5 /*!< Enable sequencer 5 software sync */ #define ADC_SEQSYNC_SYNC6_Pos 6 /*!< Enable sequencer 6 software sync */ #define ADC_SEQSYNC_SYNC7_Pos 7 /*!< Enable sequencer 7 software sync */ #define ADC_SEQSYNC_GSYNC_Pos 31 /*!< Sync all sequencers */ /* Bit field masks: */ #define ADC_SEQSYNC_SYNC0_Msk 0x00000001UL /*!< Enable sequencer 0 software sync */ #define ADC_SEQSYNC_SYNC1_Msk 0x00000002UL /*!< Enable sequencer 1 software sync */ #define ADC_SEQSYNC_SYNC2_Msk 0x00000004UL /*!< Enable sequencer 2 software sync */ #define ADC_SEQSYNC_SYNC3_Msk 0x00000008UL /*!< Enable sequencer 3 software sync */ #define ADC_SEQSYNC_SYNC4_Msk 0x00000010UL /*!< Enable sequencer 4 software sync */ #define ADC_SEQSYNC_SYNC5_Msk 0x00000020UL /*!< Enable sequencer 5 software sync */ #define ADC_SEQSYNC_SYNC6_Msk 0x00000040UL /*!< Enable sequencer 6 software sync */ #define ADC_SEQSYNC_SYNC7_Msk 0x00000080UL /*!< Enable sequencer 7 software sync */ #define ADC_SEQSYNC_GSYNC_Msk 0x80000000UL /*!< Sync all sequencers */ /*-- FSTAT: FIFO overflow status register --------------------------------------------------------------------*/ typedef struct { uint32_t OV0 :1; /*!< Sequencer 0 FIFO overflow */ uint32_t OV1 :1; /*!< Sequencer 1 FIFO overflow */ uint32_t OV2 :1; /*!< Sequencer 2 FIFO overflow */ uint32_t OV3 :1; /*!< Sequencer 3 FIFO overflow */ uint32_t OV4 :1; /*!< Sequencer 4 FIFO overflow */ uint32_t OV5 :1; /*!< Sequencer 5 FIFO overflow */ uint32_t OV6 :1; /*!< Sequencer 6 FIFO overflow */ uint32_t OV7 :1; /*!< Sequencer 7 FIFO overflow */ uint32_t UN0 :1; /*!< Sequencer 0 FIFO underflow */ uint32_t UN1 :1; /*!< Sequencer 1 FIFO underflow */ uint32_t UN2 :1; /*!< Sequencer 2 FIFO underflow */ uint32_t UN3 :1; /*!< Sequencer 3 FIFO underflow */ uint32_t UN4 :1; /*!< Sequencer 4 FIFO underflow */ uint32_t UN5 :1; /*!< Sequencer 5 FIFO underflow */ uint32_t UN6 :1; /*!< Sequencer 6 FIFO underflow */ uint32_t UN7 :1; /*!< Sequencer 7 FIFO underflow */ uint32_t DOV0 :1; /*!< Sequencer 0 FIFO DMA request overflow */ uint32_t DOV1 :1; /*!< Sequencer 1 FIFO DMA request overflow */ uint32_t DOV2 :1; /*!< Sequencer 2 FIFO DMA request overflow */ uint32_t DOV3 :1; /*!< Sequencer 3 FIFO DMA request overflow */ uint32_t DOV4 :1; /*!< Sequencer 4 FIFO DMA request overflow */ uint32_t DOV5 :1; /*!< Sequencer 5 FIFO DMA request overflow */ uint32_t DOV6 :1; /*!< Sequencer 6 FIFO DMA request overflow */ uint32_t DOV7 :1; /*!< Sequencer 7 FIFO DMA request overflow */ } _ADC_FSTAT_bits; /* Bit field positions: */ #define ADC_FSTAT_OV0_Pos 0 /*!< Sequencer 0 FIFO overflow */ #define ADC_FSTAT_OV1_Pos 1 /*!< Sequencer 1 FIFO overflow */ #define ADC_FSTAT_OV2_Pos 2 /*!< Sequencer 2 FIFO overflow */ #define ADC_FSTAT_OV3_Pos 3 /*!< Sequencer 3 FIFO overflow */ #define ADC_FSTAT_OV4_Pos 4 /*!< Sequencer 4 FIFO overflow */ #define ADC_FSTAT_OV5_Pos 5 /*!< Sequencer 5 FIFO overflow */ #define ADC_FSTAT_OV6_Pos 6 /*!< Sequencer 6 FIFO overflow */ #define ADC_FSTAT_OV7_Pos 7 /*!< Sequencer 7 FIFO overflow */ #define ADC_FSTAT_UN0_Pos 8 /*!< Sequencer 0 FIFO underflow */ #define ADC_FSTAT_UN1_Pos 9 /*!< Sequencer 1 FIFO underflow */ #define ADC_FSTAT_UN2_Pos 10 /*!< Sequencer 2 FIFO underflow */ #define ADC_FSTAT_UN3_Pos 11 /*!< Sequencer 3 FIFO underflow */ #define ADC_FSTAT_UN4_Pos 12 /*!< Sequencer 4 FIFO underflow */ #define ADC_FSTAT_UN5_Pos 13 /*!< Sequencer 5 FIFO underflow */ #define ADC_FSTAT_UN6_Pos 14 /*!< Sequencer 6 FIFO underflow */ #define ADC_FSTAT_UN7_Pos 15 /*!< Sequencer 7 FIFO underflow */ #define ADC_FSTAT_DOV0_Pos 16 /*!< Sequencer 0 FIFO DMA request overflow */ #define ADC_FSTAT_DOV1_Pos 17 /*!< Sequencer 1 FIFO DMA request overflow */ #define ADC_FSTAT_DOV2_Pos 18 /*!< Sequencer 2 FIFO DMA request overflow */ #define ADC_FSTAT_DOV3_Pos 19 /*!< Sequencer 3 FIFO DMA request overflow */ #define ADC_FSTAT_DOV4_Pos 20 /*!< Sequencer 4 FIFO DMA request overflow */ #define ADC_FSTAT_DOV5_Pos 21 /*!< Sequencer 5 FIFO DMA request overflow */ #define ADC_FSTAT_DOV6_Pos 22 /*!< Sequencer 6 FIFO DMA request overflow */ #define ADC_FSTAT_DOV7_Pos 23 /*!< Sequencer 7 FIFO DMA request overflow */ /* Bit field masks: */ #define ADC_FSTAT_OV0_Msk 0x00000001UL /*!< Sequencer 0 FIFO overflow */ #define ADC_FSTAT_OV1_Msk 0x00000002UL /*!< Sequencer 1 FIFO overflow */ #define ADC_FSTAT_OV2_Msk 0x00000004UL /*!< Sequencer 2 FIFO overflow */ #define ADC_FSTAT_OV3_Msk 0x00000008UL /*!< Sequencer 3 FIFO overflow */ #define ADC_FSTAT_OV4_Msk 0x00000010UL /*!< Sequencer 4 FIFO overflow */ #define ADC_FSTAT_OV5_Msk 0x00000020UL /*!< Sequencer 5 FIFO overflow */ #define ADC_FSTAT_OV6_Msk 0x00000040UL /*!< Sequencer 6 FIFO overflow */ #define ADC_FSTAT_OV7_Msk 0x00000080UL /*!< Sequencer 7 FIFO overflow */ #define ADC_FSTAT_UN0_Msk 0x00000100UL /*!< Sequencer 0 FIFO underflow */ #define ADC_FSTAT_UN1_Msk 0x00000200UL /*!< Sequencer 1 FIFO underflow */ #define ADC_FSTAT_UN2_Msk 0x00000400UL /*!< Sequencer 2 FIFO underflow */ #define ADC_FSTAT_UN3_Msk 0x00000800UL /*!< Sequencer 3 FIFO underflow */ #define ADC_FSTAT_UN4_Msk 0x00001000UL /*!< Sequencer 4 FIFO underflow */ #define ADC_FSTAT_UN5_Msk 0x00002000UL /*!< Sequencer 5 FIFO underflow */ #define ADC_FSTAT_UN6_Msk 0x00004000UL /*!< Sequencer 6 FIFO underflow */ #define ADC_FSTAT_UN7_Msk 0x00008000UL /*!< Sequencer 7 FIFO underflow */ #define ADC_FSTAT_DOV0_Msk 0x00010000UL /*!< Sequencer 0 FIFO DMA request overflow */ #define ADC_FSTAT_DOV1_Msk 0x00020000UL /*!< Sequencer 1 FIFO DMA request overflow */ #define ADC_FSTAT_DOV2_Msk 0x00040000UL /*!< Sequencer 2 FIFO DMA request overflow */ #define ADC_FSTAT_DOV3_Msk 0x00080000UL /*!< Sequencer 3 FIFO DMA request overflow */ #define ADC_FSTAT_DOV4_Msk 0x00100000UL /*!< Sequencer 4 FIFO DMA request overflow */ #define ADC_FSTAT_DOV5_Msk 0x00200000UL /*!< Sequencer 5 FIFO DMA request overflow */ #define ADC_FSTAT_DOV6_Msk 0x00400000UL /*!< Sequencer 6 FIFO DMA request overflow */ #define ADC_FSTAT_DOV7_Msk 0x00800000UL /*!< Sequencer 7 FIFO DMA request overflow */ /*-- BSTAT: Busy status register -----------------------------------------------------------------------------*/ typedef struct { uint32_t SEQBUSY0 :1; /*!< Sequencer 0 busy */ uint32_t SEQBUSY1 :1; /*!< Sequencer 1 busy */ uint32_t SEQBUSY2 :1; /*!< Sequencer 2 busy */ uint32_t SEQBUSY3 :1; /*!< Sequencer 3 busy */ uint32_t SEQBUSY4 :1; /*!< Sequencer 4 busy */ uint32_t SEQBUSY5 :1; /*!< Sequencer 5 busy */ uint32_t SEQBUSY6 :1; /*!< Sequencer 6 busy */ uint32_t SEQBUSY7 :1; /*!< Sequencer 7 busy */ uint32_t :8; /*!< RESERVED */ uint32_t ADCBUSY0 :1; /*!< ADC module 0 conversion busy */ uint32_t ADCBUSY1 :1; /*!< ADC module 1 conversion busy */ uint32_t ADCBUSY2 :1; /*!< ADC module 2 conversion busy */ uint32_t ADCBUSY3 :1; /*!< ADC module 3 conversion busy */ } _ADC_BSTAT_bits; /* Bit field positions: */ #define ADC_BSTAT_SEQBUSY0_Pos 0 /*!< Sequencer 0 busy */ #define ADC_BSTAT_SEQBUSY1_Pos 1 /*!< Sequencer 1 busy */ #define ADC_BSTAT_SEQBUSY2_Pos 2 /*!< Sequencer 2 busy */ #define ADC_BSTAT_SEQBUSY3_Pos 3 /*!< Sequencer 3 busy */ #define ADC_BSTAT_SEQBUSY4_Pos 4 /*!< Sequencer 4 busy */ #define ADC_BSTAT_SEQBUSY5_Pos 5 /*!< Sequencer 5 busy */ #define ADC_BSTAT_SEQBUSY6_Pos 6 /*!< Sequencer 6 busy */ #define ADC_BSTAT_SEQBUSY7_Pos 7 /*!< Sequencer 7 busy */ #define ADC_BSTAT_ADCBUSY0_Pos 16 /*!< ADC module 0 conversion busy */ #define ADC_BSTAT_ADCBUSY1_Pos 17 /*!< ADC module 1 conversion busy */ #define ADC_BSTAT_ADCBUSY2_Pos 18 /*!< ADC module 2 conversion busy */ #define ADC_BSTAT_ADCBUSY3_Pos 19 /*!< ADC module 3 conversion busy */ /* Bit field masks: */ #define ADC_BSTAT_SEQBUSY0_Msk 0x00000001UL /*!< Sequencer 0 busy */ #define ADC_BSTAT_SEQBUSY1_Msk 0x00000002UL /*!< Sequencer 1 busy */ #define ADC_BSTAT_SEQBUSY2_Msk 0x00000004UL /*!< Sequencer 2 busy */ #define ADC_BSTAT_SEQBUSY3_Msk 0x00000008UL /*!< Sequencer 3 busy */ #define ADC_BSTAT_SEQBUSY4_Msk 0x00000010UL /*!< Sequencer 4 busy */ #define ADC_BSTAT_SEQBUSY5_Msk 0x00000020UL /*!< Sequencer 5 busy */ #define ADC_BSTAT_SEQBUSY6_Msk 0x00000040UL /*!< Sequencer 6 busy */ #define ADC_BSTAT_SEQBUSY7_Msk 0x00000080UL /*!< Sequencer 7 busy */ #define ADC_BSTAT_ADCBUSY0_Msk 0x00010000UL /*!< ADC module 0 conversion busy */ #define ADC_BSTAT_ADCBUSY1_Msk 0x00020000UL /*!< ADC module 1 conversion busy */ #define ADC_BSTAT_ADCBUSY2_Msk 0x00040000UL /*!< ADC module 2 conversion busy */ #define ADC_BSTAT_ADCBUSY3_Msk 0x00080000UL /*!< ADC module 3 conversion busy */ /*-- DCTRIG: Digital comparator output trigger status register -----------------------------------------------*/ typedef struct { uint32_t TOS0 :1; /*!< DC 0 output trigger status */ uint32_t TOS1 :1; /*!< DC 1 output trigger status */ uint32_t TOS2 :1; /*!< DC 2 output trigger status */ uint32_t TOS3 :1; /*!< DC 3 output trigger status */ uint32_t TOS4 :1; /*!< DC 4 output trigger status */ uint32_t TOS5 :1; /*!< DC 5 output trigger status */ uint32_t TOS6 :1; /*!< DC 6 output trigger status */ uint32_t TOS7 :1; /*!< DC 7 output trigger status */ uint32_t TOS8 :1; /*!< DC 8 output trigger status */ uint32_t TOS9 :1; /*!< DC 9 output trigger status */ uint32_t TOS10 :1; /*!< DC 10 output trigger status */ uint32_t TOS11 :1; /*!< DC 11 output trigger status */ uint32_t TOS12 :1; /*!< DC 12 output trigger status */ uint32_t TOS13 :1; /*!< DC 13 output trigger status */ uint32_t TOS14 :1; /*!< DC 14 output trigger status */ uint32_t TOS15 :1; /*!< DC 15 output trigger status */ uint32_t TOS16 :1; /*!< DC 16 output trigger status */ uint32_t TOS17 :1; /*!< DC 17 output trigger status */ uint32_t TOS18 :1; /*!< DC 18 output trigger status */ uint32_t TOS19 :1; /*!< DC 19 output trigger status */ uint32_t TOS20 :1; /*!< DC 20 output trigger status */ uint32_t TOS21 :1; /*!< DC 21 output trigger status */ uint32_t TOS22 :1; /*!< DC 22 output trigger status */ uint32_t TOS23 :1; /*!< DC 23 output trigger status */ } _ADC_DCTRIG_bits; /* Bit field positions: */ #define ADC_DCTRIG_TOS0_Pos 0 /*!< DC 0 output trigger status */ #define ADC_DCTRIG_TOS1_Pos 1 /*!< DC 1 output trigger status */ #define ADC_DCTRIG_TOS2_Pos 2 /*!< DC 2 output trigger status */ #define ADC_DCTRIG_TOS3_Pos 3 /*!< DC 3 output trigger status */ #define ADC_DCTRIG_TOS4_Pos 4 /*!< DC 4 output trigger status */ #define ADC_DCTRIG_TOS5_Pos 5 /*!< DC 5 output trigger status */ #define ADC_DCTRIG_TOS6_Pos 6 /*!< DC 6 output trigger status */ #define ADC_DCTRIG_TOS7_Pos 7 /*!< DC 7 output trigger status */ #define ADC_DCTRIG_TOS8_Pos 8 /*!< DC 8 output trigger status */ #define ADC_DCTRIG_TOS9_Pos 9 /*!< DC 9 output trigger status */ #define ADC_DCTRIG_TOS10_Pos 10 /*!< DC 10 output trigger status */ #define ADC_DCTRIG_TOS11_Pos 11 /*!< DC 11 output trigger status */ #define ADC_DCTRIG_TOS12_Pos 12 /*!< DC 12 output trigger status */ #define ADC_DCTRIG_TOS13_Pos 13 /*!< DC 13 output trigger status */ #define ADC_DCTRIG_TOS14_Pos 14 /*!< DC 14 output trigger status */ #define ADC_DCTRIG_TOS15_Pos 15 /*!< DC 15 output trigger status */ #define ADC_DCTRIG_TOS16_Pos 16 /*!< DC 16 output trigger status */ #define ADC_DCTRIG_TOS17_Pos 17 /*!< DC 17 output trigger status */ #define ADC_DCTRIG_TOS18_Pos 18 /*!< DC 18 output trigger status */ #define ADC_DCTRIG_TOS19_Pos 19 /*!< DC 19 output trigger status */ #define ADC_DCTRIG_TOS20_Pos 20 /*!< DC 20 output trigger status */ #define ADC_DCTRIG_TOS21_Pos 21 /*!< DC 21 output trigger status */ #define ADC_DCTRIG_TOS22_Pos 22 /*!< DC 22 output trigger status */ #define ADC_DCTRIG_TOS23_Pos 23 /*!< DC 23 output trigger status */ /* Bit field masks: */ #define ADC_DCTRIG_TOS0_Msk 0x00000001UL /*!< DC 0 output trigger status */ #define ADC_DCTRIG_TOS1_Msk 0x00000002UL /*!< DC 1 output trigger status */ #define ADC_DCTRIG_TOS2_Msk 0x00000004UL /*!< DC 2 output trigger status */ #define ADC_DCTRIG_TOS3_Msk 0x00000008UL /*!< DC 3 output trigger status */ #define ADC_DCTRIG_TOS4_Msk 0x00000010UL /*!< DC 4 output trigger status */ #define ADC_DCTRIG_TOS5_Msk 0x00000020UL /*!< DC 5 output trigger status */ #define ADC_DCTRIG_TOS6_Msk 0x00000040UL /*!< DC 6 output trigger status */ #define ADC_DCTRIG_TOS7_Msk 0x00000080UL /*!< DC 7 output trigger status */ #define ADC_DCTRIG_TOS8_Msk 0x00000100UL /*!< DC 8 output trigger status */ #define ADC_DCTRIG_TOS9_Msk 0x00000200UL /*!< DC 9 output trigger status */ #define ADC_DCTRIG_TOS10_Msk 0x00000400UL /*!< DC 10 output trigger status */ #define ADC_DCTRIG_TOS11_Msk 0x00000800UL /*!< DC 11 output trigger status */ #define ADC_DCTRIG_TOS12_Msk 0x00001000UL /*!< DC 12 output trigger status */ #define ADC_DCTRIG_TOS13_Msk 0x00002000UL /*!< DC 13 output trigger status */ #define ADC_DCTRIG_TOS14_Msk 0x00004000UL /*!< DC 14 output trigger status */ #define ADC_DCTRIG_TOS15_Msk 0x00008000UL /*!< DC 15 output trigger status */ #define ADC_DCTRIG_TOS16_Msk 0x00010000UL /*!< DC 16 output trigger status */ #define ADC_DCTRIG_TOS17_Msk 0x00020000UL /*!< DC 17 output trigger status */ #define ADC_DCTRIG_TOS18_Msk 0x00040000UL /*!< DC 18 output trigger status */ #define ADC_DCTRIG_TOS19_Msk 0x00080000UL /*!< DC 19 output trigger status */ #define ADC_DCTRIG_TOS20_Msk 0x00100000UL /*!< DC 20 output trigger status */ #define ADC_DCTRIG_TOS21_Msk 0x00200000UL /*!< DC 21 output trigger status */ #define ADC_DCTRIG_TOS22_Msk 0x00400000UL /*!< DC 22 output trigger status */ #define ADC_DCTRIG_TOS23_Msk 0x00800000UL /*!< DC 23 output trigger status */ /*-- DCEV: Digital comparator compare event status register --------------------------------------------------*/ typedef struct { uint32_t DCEV0 :1; /*!< Digital compare event 0 */ uint32_t DCEV1 :1; /*!< Digital compare event 1 */ uint32_t DCEV2 :1; /*!< Digital compare event 2 */ uint32_t DCEV3 :1; /*!< Digital compare event 3 */ uint32_t DCEV4 :1; /*!< Digital compare event 4 */ uint32_t DCEV5 :1; /*!< Digital compare event 5 */ uint32_t DCEV6 :1; /*!< Digital compare event 6 */ uint32_t DCEV7 :1; /*!< Digital compare event 7 */ uint32_t DCEV8 :1; /*!< Digital compare event 8 */ uint32_t DCEV9 :1; /*!< Digital compare event 9 */ uint32_t DCEV10 :1; /*!< Digital compare event 10 */ uint32_t DCEV11 :1; /*!< Digital compare event 11 */ uint32_t DCEV12 :1; /*!< Digital compare event 12 */ uint32_t DCEV13 :1; /*!< Digital compare event 13 */ uint32_t DCEV14 :1; /*!< Digital compare event 14 */ uint32_t DCEV15 :1; /*!< Digital compare event 15 */ uint32_t DCEV16 :1; /*!< Digital compare event 16 */ uint32_t DCEV17 :1; /*!< Digital compare event 17 */ uint32_t DCEV18 :1; /*!< Digital compare event 18 */ uint32_t DCEV19 :1; /*!< Digital compare event 19 */ uint32_t DCEV20 :1; /*!< Digital compare event 20 */ uint32_t DCEV21 :1; /*!< Digital compare event 21 */ uint32_t DCEV22 :1; /*!< Digital compare event 22 */ uint32_t DCEV23 :1; /*!< Digital compare event 23 */ } _ADC_DCEV_bits; /* Bit field positions: */ #define ADC_DCEV_DCEV0_Pos 0 /*!< Digital compare event 0 */ #define ADC_DCEV_DCEV1_Pos 1 /*!< Digital compare event 1 */ #define ADC_DCEV_DCEV2_Pos 2 /*!< Digital compare event 2 */ #define ADC_DCEV_DCEV3_Pos 3 /*!< Digital compare event 3 */ #define ADC_DCEV_DCEV4_Pos 4 /*!< Digital compare event 4 */ #define ADC_DCEV_DCEV5_Pos 5 /*!< Digital compare event 5 */ #define ADC_DCEV_DCEV6_Pos 6 /*!< Digital compare event 6 */ #define ADC_DCEV_DCEV7_Pos 7 /*!< Digital compare event 7 */ #define ADC_DCEV_DCEV8_Pos 8 /*!< Digital compare event 8 */ #define ADC_DCEV_DCEV9_Pos 9 /*!< Digital compare event 9 */ #define ADC_DCEV_DCEV10_Pos 10 /*!< Digital compare event 10 */ #define ADC_DCEV_DCEV11_Pos 11 /*!< Digital compare event 11 */ #define ADC_DCEV_DCEV12_Pos 12 /*!< Digital compare event 12 */ #define ADC_DCEV_DCEV13_Pos 13 /*!< Digital compare event 13 */ #define ADC_DCEV_DCEV14_Pos 14 /*!< Digital compare event 14 */ #define ADC_DCEV_DCEV15_Pos 15 /*!< Digital compare event 15 */ #define ADC_DCEV_DCEV16_Pos 16 /*!< Digital compare event 16 */ #define ADC_DCEV_DCEV17_Pos 17 /*!< Digital compare event 17 */ #define ADC_DCEV_DCEV18_Pos 18 /*!< Digital compare event 18 */ #define ADC_DCEV_DCEV19_Pos 19 /*!< Digital compare event 19 */ #define ADC_DCEV_DCEV20_Pos 20 /*!< Digital compare event 20 */ #define ADC_DCEV_DCEV21_Pos 21 /*!< Digital compare event 21 */ #define ADC_DCEV_DCEV22_Pos 22 /*!< Digital compare event 22 */ #define ADC_DCEV_DCEV23_Pos 23 /*!< Digital compare event 23 */ /* Bit field masks: */ #define ADC_DCEV_DCEV0_Msk 0x00000001UL /*!< Digital compare event 0 */ #define ADC_DCEV_DCEV1_Msk 0x00000002UL /*!< Digital compare event 1 */ #define ADC_DCEV_DCEV2_Msk 0x00000004UL /*!< Digital compare event 2 */ #define ADC_DCEV_DCEV3_Msk 0x00000008UL /*!< Digital compare event 3 */ #define ADC_DCEV_DCEV4_Msk 0x00000010UL /*!< Digital compare event 4 */ #define ADC_DCEV_DCEV5_Msk 0x00000020UL /*!< Digital compare event 5 */ #define ADC_DCEV_DCEV6_Msk 0x00000040UL /*!< Digital compare event 6 */ #define ADC_DCEV_DCEV7_Msk 0x00000080UL /*!< Digital compare event 7 */ #define ADC_DCEV_DCEV8_Msk 0x00000100UL /*!< Digital compare event 8 */ #define ADC_DCEV_DCEV9_Msk 0x00000200UL /*!< Digital compare event 9 */ #define ADC_DCEV_DCEV10_Msk 0x00000400UL /*!< Digital compare event 10 */ #define ADC_DCEV_DCEV11_Msk 0x00000800UL /*!< Digital compare event 11 */ #define ADC_DCEV_DCEV12_Msk 0x00001000UL /*!< Digital compare event 12 */ #define ADC_DCEV_DCEV13_Msk 0x00002000UL /*!< Digital compare event 13 */ #define ADC_DCEV_DCEV14_Msk 0x00004000UL /*!< Digital compare event 14 */ #define ADC_DCEV_DCEV15_Msk 0x00008000UL /*!< Digital compare event 15 */ #define ADC_DCEV_DCEV16_Msk 0x00010000UL /*!< Digital compare event 16 */ #define ADC_DCEV_DCEV17_Msk 0x00020000UL /*!< Digital compare event 17 */ #define ADC_DCEV_DCEV18_Msk 0x00040000UL /*!< Digital compare event 18 */ #define ADC_DCEV_DCEV19_Msk 0x00080000UL /*!< Digital compare event 19 */ #define ADC_DCEV_DCEV20_Msk 0x00100000UL /*!< Digital compare event 20 */ #define ADC_DCEV_DCEV21_Msk 0x00200000UL /*!< Digital compare event 21 */ #define ADC_DCEV_DCEV22_Msk 0x00400000UL /*!< Digital compare event 22 */ #define ADC_DCEV_DCEV23_Msk 0x00800000UL /*!< Digital compare event 23 */ /*-- CICNT: Interrupt counter clear control ------------------------------------------------------------------*/ typedef struct { uint32_t ICNT0 :1; /*!< Clear interrupt counter on sequencer 0 start */ uint32_t ICNT1 :1; /*!< Clear interrupt counter on sequencer 1 start */ uint32_t ICNT2 :1; /*!< Clear interrupt counter on sequencer 2 start */ uint32_t ICNT3 :1; /*!< Clear interrupt counter on sequencer 3 start */ uint32_t ICNT4 :1; /*!< Clear interrupt counter on sequencer 4 start */ uint32_t ICNT5 :1; /*!< Clear interrupt counter on sequencer 5 start */ uint32_t ICNT6 :1; /*!< Clear interrupt counter on sequencer 6 start */ uint32_t ICNT7 :1; /*!< Clear interrupt counter on sequencer 7 start */ } _ADC_CICNT_bits; /* Bit field positions: */ #define ADC_CICNT_ICNT0_Pos 0 /*!< Clear interrupt counter on sequencer 0 start */ #define ADC_CICNT_ICNT1_Pos 1 /*!< Clear interrupt counter on sequencer 1 start */ #define ADC_CICNT_ICNT2_Pos 2 /*!< Clear interrupt counter on sequencer 2 start */ #define ADC_CICNT_ICNT3_Pos 3 /*!< Clear interrupt counter on sequencer 3 start */ #define ADC_CICNT_ICNT4_Pos 4 /*!< Clear interrupt counter on sequencer 4 start */ #define ADC_CICNT_ICNT5_Pos 5 /*!< Clear interrupt counter on sequencer 5 start */ #define ADC_CICNT_ICNT6_Pos 6 /*!< Clear interrupt counter on sequencer 6 start */ #define ADC_CICNT_ICNT7_Pos 7 /*!< Clear interrupt counter on sequencer 7 start */ /* Bit field masks: */ #define ADC_CICNT_ICNT0_Msk 0x00000001UL /*!< Clear interrupt counter on sequencer 0 start */ #define ADC_CICNT_ICNT1_Msk 0x00000002UL /*!< Clear interrupt counter on sequencer 1 start */ #define ADC_CICNT_ICNT2_Msk 0x00000004UL /*!< Clear interrupt counter on sequencer 2 start */ #define ADC_CICNT_ICNT3_Msk 0x00000008UL /*!< Clear interrupt counter on sequencer 3 start */ #define ADC_CICNT_ICNT4_Msk 0x00000010UL /*!< Clear interrupt counter on sequencer 4 start */ #define ADC_CICNT_ICNT5_Msk 0x00000020UL /*!< Clear interrupt counter on sequencer 5 start */ #define ADC_CICNT_ICNT6_Msk 0x00000040UL /*!< Clear interrupt counter on sequencer 6 start */ #define ADC_CICNT_ICNT7_Msk 0x00000080UL /*!< Clear interrupt counter on sequencer 7 start */ /*-- EMUX: Sequencer start event selection register ----------------------------------------------------------*/ typedef struct { uint32_t EM0 :4; /*!< Select start event for sequencer 0 */ uint32_t EM1 :4; /*!< Select start event for sequencer 1 */ uint32_t EM2 :4; /*!< Select start event for sequencer 2 */ uint32_t EM3 :4; /*!< Select start event for sequencer 3 */ uint32_t EM4 :4; /*!< Select start event for sequencer 4 */ uint32_t EM5 :4; /*!< Select start event for sequencer 5 */ uint32_t EM6 :4; /*!< Select start event for sequencer 6 */ uint32_t EM7 :4; /*!< Select start event for sequencer 7 */ } _ADC_EMUX_bits; /* Bit field positions: */ #define ADC_EMUX_EM0_Pos 0 /*!< Select start event for sequencer 0 */ #define ADC_EMUX_EM1_Pos 4 /*!< Select start event for sequencer 1 */ #define ADC_EMUX_EM2_Pos 8 /*!< Select start event for sequencer 2 */ #define ADC_EMUX_EM3_Pos 12 /*!< Select start event for sequencer 3 */ #define ADC_EMUX_EM4_Pos 16 /*!< Select start event for sequencer 4 */ #define ADC_EMUX_EM5_Pos 20 /*!< Select start event for sequencer 5 */ #define ADC_EMUX_EM6_Pos 24 /*!< Select start event for sequencer 6 */ #define ADC_EMUX_EM7_Pos 28 /*!< Select start event for sequencer 7 */ /* Bit field masks: */ #define ADC_EMUX_EM0_Msk 0x0000000FUL /*!< Select start event for sequencer 0 */ #define ADC_EMUX_EM1_Msk 0x000000F0UL /*!< Select start event for sequencer 1 */ #define ADC_EMUX_EM2_Msk 0x00000F00UL /*!< Select start event for sequencer 2 */ #define ADC_EMUX_EM3_Msk 0x0000F000UL /*!< Select start event for sequencer 3 */ #define ADC_EMUX_EM4_Msk 0x000F0000UL /*!< Select start event for sequencer 4 */ #define ADC_EMUX_EM5_Msk 0x00F00000UL /*!< Select start event for sequencer 5 */ #define ADC_EMUX_EM6_Msk 0x0F000000UL /*!< Select start event for sequencer 6 */ #define ADC_EMUX_EM7_Msk 0xF0000000UL /*!< Select start event for sequencer 7 */ /* Bit field enums: */ typedef enum { ADC_EMUX_EM0_SwReq = 0x0UL, /*!< software request by GSYNC bit */ ADC_EMUX_EM0_GPIOABCD = 0x1UL, /*!< GPIOA or GPIOB or GPIOC or GPIOD interrupt */ ADC_EMUX_EM0_GPIOEFGH = 0x2UL, /*!< GPIOE or GPIOF or GPIOG or GPIOH interrupt */ ADC_EMUX_EM0_GPIOJKLM = 0x3UL, /*!< GPIOJ or GPIOK or GPIOL or GPIOM interrupt */ ADC_EMUX_EM0_TMR0 = 0x5UL, /*!< Timer 0 request */ ADC_EMUX_EM0_TMR1 = 0x6UL, /*!< Timer 1 request */ ADC_EMUX_EM0_TMR2 = 0x7UL, /*!< Timer 2 request */ ADC_EMUX_EM0_TMR3 = 0x8UL, /*!< Timer 3 request */ ADC_EMUX_EM0_PWM012A = 0x9UL, /*!< PWM0,1,2 A channel request */ ADC_EMUX_EM0_PWM012B = 0xAUL, /*!< PWM0,1,2 B channel request */ ADC_EMUX_EM0_PWM345A = 0xBUL, /*!< PWM3,4,5 A channel request */ ADC_EMUX_EM0_PWM345B = 0xCUL, /*!< PWM3,4,5 B channel request */ ADC_EMUX_EM0_PWM6789A = 0xDUL, /*!< PWM6,7,8,9 A channel request */ ADC_EMUX_EM0_PWM6789B = 0xEUL, /*!< PWM6,7,8,9 B channel request */ ADC_EMUX_EM0_Cycle = 0xFUL, /*!< Cycle mode */ } ADC_EMUX_EM0_Enum; typedef enum { ADC_EMUX_EM1_SwReq = 0x0UL, /*!< software request by GSYNC bit */ ADC_EMUX_EM1_GPIOABCD = 0x1UL, /*!< GPIOA or GPIOB or GPIOC or GPIOD interrupt */ ADC_EMUX_EM1_GPIOEFGH = 0x2UL, /*!< GPIOE or GPIOF or GPIOG or GPIOH interrupt */ ADC_EMUX_EM1_GPIOJKLM = 0x3UL, /*!< GPIOJ or GPIOK or GPIOL or GPIOM interrupt */ ADC_EMUX_EM1_TMR0 = 0x5UL, /*!< Timer 0 request */ ADC_EMUX_EM1_TMR1 = 0x6UL, /*!< Timer 1 request */ ADC_EMUX_EM1_TMR2 = 0x7UL, /*!< Timer 2 request */ ADC_EMUX_EM1_TMR3 = 0x8UL, /*!< Timer 3 request */ ADC_EMUX_EM1_PWM012A = 0x9UL, /*!< PWM0,1,2 A channel request */ ADC_EMUX_EM1_PWM012B = 0xAUL, /*!< PWM0,1,2 B channel request */ ADC_EMUX_EM1_PWM345A = 0xBUL, /*!< PWM3,4,5 A channel request */ ADC_EMUX_EM1_PWM345B = 0xCUL, /*!< PWM3,4,5 B channel request */ ADC_EMUX_EM1_PWM6789A = 0xDUL, /*!< PWM6,7,8,9 A channel request */ ADC_EMUX_EM1_PWM6789B = 0xEUL, /*!< PWM6,7,8,9 B channel request */ ADC_EMUX_EM1_Cycle = 0xFUL, /*!< Cycle mode */ } ADC_EMUX_EM1_Enum; typedef enum { ADC_EMUX_EM2_SwReq = 0x0UL, /*!< software request by GSYNC bit */ ADC_EMUX_EM2_GPIOABCD = 0x1UL, /*!< GPIOA or GPIOB or GPIOC or GPIOD interrupt */ ADC_EMUX_EM2_GPIOEFGH = 0x2UL, /*!< GPIOE or GPIOF or GPIOG or GPIOH interrupt */ ADC_EMUX_EM2_GPIOJKLM = 0x3UL, /*!< GPIOJ or GPIOK or GPIOL or GPIOM interrupt */ ADC_EMUX_EM2_TMR0 = 0x5UL, /*!< Timer 0 request */ ADC_EMUX_EM2_TMR1 = 0x6UL, /*!< Timer 1 request */ ADC_EMUX_EM2_TMR2 = 0x7UL, /*!< Timer 2 request */ ADC_EMUX_EM2_TMR3 = 0x8UL, /*!< Timer 3 request */ ADC_EMUX_EM2_PWM012A = 0x9UL, /*!< PWM0,1,2 A channel request */ ADC_EMUX_EM2_PWM012B = 0xAUL, /*!< PWM0,1,2 B channel request */ ADC_EMUX_EM2_PWM345A = 0xBUL, /*!< PWM3,4,5 A channel request */ ADC_EMUX_EM2_PWM345B = 0xCUL, /*!< PWM3,4,5 B channel request */ ADC_EMUX_EM2_PWM6789A = 0xDUL, /*!< PWM6,7,8,9 A channel request */ ADC_EMUX_EM2_PWM6789B = 0xEUL, /*!< PWM6,7,8,9 B channel request */ ADC_EMUX_EM2_Cycle = 0xFUL, /*!< Cycle mode */ } ADC_EMUX_EM2_Enum; typedef enum { ADC_EMUX_EM3_SwReq = 0x0UL, /*!< software request by GSYNC bit */ ADC_EMUX_EM3_GPIOABCD = 0x1UL, /*!< GPIOA or GPIOB or GPIOC or GPIOD interrupt */ ADC_EMUX_EM3_GPIOEFGH = 0x2UL, /*!< GPIOE or GPIOF or GPIOG or GPIOH interrupt */ ADC_EMUX_EM3_GPIOJKLM = 0x3UL, /*!< GPIOJ or GPIOK or GPIOL or GPIOM interrupt */ ADC_EMUX_EM3_TMR0 = 0x5UL, /*!< Timer 0 request */ ADC_EMUX_EM3_TMR1 = 0x6UL, /*!< Timer 1 request */ ADC_EMUX_EM3_TMR2 = 0x7UL, /*!< Timer 2 request */ ADC_EMUX_EM3_TMR3 = 0x8UL, /*!< Timer 3 request */ ADC_EMUX_EM3_PWM012A = 0x9UL, /*!< PWM0,1,2 A channel request */ ADC_EMUX_EM3_PWM012B = 0xAUL, /*!< PWM0,1,2 B channel request */ ADC_EMUX_EM3_PWM345A = 0xBUL, /*!< PWM3,4,5 A channel request */ ADC_EMUX_EM3_PWM345B = 0xCUL, /*!< PWM3,4,5 B channel request */ ADC_EMUX_EM3_PWM6789A = 0xDUL, /*!< PWM6,7,8,9 A channel request */ ADC_EMUX_EM3_PWM6789B = 0xEUL, /*!< PWM6,7,8,9 B channel request */ ADC_EMUX_EM3_Cycle = 0xFUL, /*!< Cycle mode */ } ADC_EMUX_EM3_Enum; typedef enum { ADC_EMUX_EM4_SwReq = 0x0UL, /*!< software request by GSYNC bit */ ADC_EMUX_EM4_GPIOABCD = 0x1UL, /*!< GPIOA or GPIOB or GPIOC or GPIOD interrupt */ ADC_EMUX_EM4_GPIOEFGH = 0x2UL, /*!< GPIOE or GPIOF or GPIOG or GPIOH interrupt */ ADC_EMUX_EM4_GPIOJKLM = 0x3UL, /*!< GPIOJ or GPIOK or GPIOL or GPIOM interrupt */ ADC_EMUX_EM4_TMR0 = 0x5UL, /*!< Timer 0 request */ ADC_EMUX_EM4_TMR1 = 0x6UL, /*!< Timer 1 request */ ADC_EMUX_EM4_TMR2 = 0x7UL, /*!< Timer 2 request */ ADC_EMUX_EM4_TMR3 = 0x8UL, /*!< Timer 3 request */ ADC_EMUX_EM4_PWM012A = 0x9UL, /*!< PWM0,1,2 A channel request */ ADC_EMUX_EM4_PWM012B = 0xAUL, /*!< PWM0,1,2 B channel request */ ADC_EMUX_EM4_PWM345A = 0xBUL, /*!< PWM3,4,5 A channel request */ ADC_EMUX_EM4_PWM345B = 0xCUL, /*!< PWM3,4,5 B channel request */ ADC_EMUX_EM4_PWM6789A = 0xDUL, /*!< PWM6,7,8,9 A channel request */ ADC_EMUX_EM4_PWM6789B = 0xEUL, /*!< PWM6,7,8,9 B channel request */ ADC_EMUX_EM4_Cycle = 0xFUL, /*!< Cycle mode */ } ADC_EMUX_EM4_Enum; typedef enum { ADC_EMUX_EM5_SwReq = 0x0UL, /*!< software request by GSYNC bit */ ADC_EMUX_EM5_GPIOABCD = 0x1UL, /*!< GPIOA or GPIOB or GPIOC or GPIOD interrupt */ ADC_EMUX_EM5_GPIOEFGH = 0x2UL, /*!< GPIOE or GPIOF or GPIOG or GPIOH interrupt */ ADC_EMUX_EM5_GPIOJKLM = 0x3UL, /*!< GPIOJ or GPIOK or GPIOL or GPIOM interrupt */ ADC_EMUX_EM5_TMR0 = 0x5UL, /*!< Timer 0 request */ ADC_EMUX_EM5_TMR1 = 0x6UL, /*!< Timer 1 request */ ADC_EMUX_EM5_TMR2 = 0x7UL, /*!< Timer 2 request */ ADC_EMUX_EM5_TMR3 = 0x8UL, /*!< Timer 3 request */ ADC_EMUX_EM5_PWM012A = 0x9UL, /*!< PWM0,1,2 A channel request */ ADC_EMUX_EM5_PWM012B = 0xAUL, /*!< PWM0,1,2 B channel request */ ADC_EMUX_EM5_PWM345A = 0xBUL, /*!< PWM3,4,5 A channel request */ ADC_EMUX_EM5_PWM345B = 0xCUL, /*!< PWM3,4,5 B channel request */ ADC_EMUX_EM5_PWM6789A = 0xDUL, /*!< PWM6,7,8,9 A channel request */ ADC_EMUX_EM5_PWM6789B = 0xEUL, /*!< PWM6,7,8,9 B channel request */ ADC_EMUX_EM5_Cycle = 0xFUL, /*!< Cycle mode */ } ADC_EMUX_EM5_Enum; typedef enum { ADC_EMUX_EM6_SwReq = 0x0UL, /*!< software request by GSYNC bit */ ADC_EMUX_EM6_GPIOABCD = 0x1UL, /*!< GPIOA or GPIOB or GPIOC or GPIOD interrupt */ ADC_EMUX_EM6_GPIOEFGH = 0x2UL, /*!< GPIOE or GPIOF or GPIOG or GPIOH interrupt */ ADC_EMUX_EM6_GPIOJKLM = 0x3UL, /*!< GPIOJ or GPIOK or GPIOL or GPIOM interrupt */ ADC_EMUX_EM6_TMR0 = 0x5UL, /*!< Timer 0 request */ ADC_EMUX_EM6_TMR1 = 0x6UL, /*!< Timer 1 request */ ADC_EMUX_EM6_TMR2 = 0x7UL, /*!< Timer 2 request */ ADC_EMUX_EM6_TMR3 = 0x8UL, /*!< Timer 3 request */ ADC_EMUX_EM6_PWM012A = 0x9UL, /*!< PWM0,1,2 A channel request */ ADC_EMUX_EM6_PWM012B = 0xAUL, /*!< PWM0,1,2 B channel request */ ADC_EMUX_EM6_PWM345A = 0xBUL, /*!< PWM3,4,5 A channel request */ ADC_EMUX_EM6_PWM345B = 0xCUL, /*!< PWM3,4,5 B channel request */ ADC_EMUX_EM6_PWM6789A = 0xDUL, /*!< PWM6,7,8,9 A channel request */ ADC_EMUX_EM6_PWM6789B = 0xEUL, /*!< PWM6,7,8,9 B channel request */ ADC_EMUX_EM6_Cycle = 0xFUL, /*!< Cycle mode */ } ADC_EMUX_EM6_Enum; typedef enum { ADC_EMUX_EM7_SwReq = 0x0UL, /*!< software request by GSYNC bit */ ADC_EMUX_EM7_GPIOABCD = 0x1UL, /*!< GPIOA or GPIOB or GPIOC or GPIOD interrupt */ ADC_EMUX_EM7_GPIOEFGH = 0x2UL, /*!< GPIOE or GPIOF or GPIOG or GPIOH interrupt */ ADC_EMUX_EM7_GPIOJKLM = 0x3UL, /*!< GPIOJ or GPIOK or GPIOL or GPIOM interrupt */ ADC_EMUX_EM7_TMR0 = 0x5UL, /*!< Timer 0 request */ ADC_EMUX_EM7_TMR1 = 0x6UL, /*!< Timer 1 request */ ADC_EMUX_EM7_TMR2 = 0x7UL, /*!< Timer 2 request */ ADC_EMUX_EM7_TMR3 = 0x8UL, /*!< Timer 3 request */ ADC_EMUX_EM7_PWM012A = 0x9UL, /*!< PWM0,1,2 A channel request */ ADC_EMUX_EM7_PWM012B = 0xAUL, /*!< PWM0,1,2 B channel request */ ADC_EMUX_EM7_PWM345A = 0xBUL, /*!< PWM3,4,5 A channel request */ ADC_EMUX_EM7_PWM345B = 0xCUL, /*!< PWM3,4,5 B channel request */ ADC_EMUX_EM7_PWM6789A = 0xDUL, /*!< PWM6,7,8,9 A channel request */ ADC_EMUX_EM7_PWM6789B = 0xEUL, /*!< PWM6,7,8,9 B channel request */ ADC_EMUX_EM7_Cycle = 0xFUL, /*!< Cycle mode */ } ADC_EMUX_EM7_Enum; /*-- RIS: Raw interrupt status register ----------------------------------------------------------------------*/ typedef struct { uint32_t SEQRIS0 :1; /*!< Sequencer 0 raw interrupt status */ uint32_t SEQRIS1 :1; /*!< Sequencer 1 raw interrupt status */ uint32_t SEQRIS2 :1; /*!< Sequencer 2 raw interrupt status */ uint32_t SEQRIS3 :1; /*!< Sequencer 3 raw interrupt status */ uint32_t SEQRIS4 :1; /*!< Sequencer 4 raw interrupt status */ uint32_t SEQRIS5 :1; /*!< Sequencer 5 raw interrupt status */ uint32_t SEQRIS6 :1; /*!< Sequencer 6 raw interrupt status */ uint32_t SEQRIS7 :1; /*!< Sequencer 7 raw interrupt status */ uint32_t DCRIS0 :1; /*!< Raw interrupt status of Digital Comparator 0 */ uint32_t DCRIS1 :1; /*!< Raw interrupt status of Digital Comparator 1 */ uint32_t DCRIS2 :1; /*!< Raw interrupt status of Digital Comparator 2 */ uint32_t DCRIS3 :1; /*!< Raw interrupt status of Digital Comparator 3 */ uint32_t DCRIS4 :1; /*!< Raw interrupt status of Digital Comparator 4 */ uint32_t DCRIS5 :1; /*!< Raw interrupt status of Digital Comparator 5 */ uint32_t DCRIS6 :1; /*!< Raw interrupt status of Digital Comparator 6 */ uint32_t DCRIS7 :1; /*!< Raw interrupt status of Digital Comparator 7 */ uint32_t DCRIS8 :1; /*!< Raw interrupt status of Digital Comparator 8 */ uint32_t DCRIS9 :1; /*!< Raw interrupt status of Digital Comparator 9 */ uint32_t DCRIS10 :1; /*!< Raw interrupt status of Digital Comparator 10 */ uint32_t DCRIS11 :1; /*!< Raw interrupt status of Digital Comparator 11 */ uint32_t DCRIS12 :1; /*!< Raw interrupt status of Digital Comparator 12 */ uint32_t DCRIS13 :1; /*!< Raw interrupt status of Digital Comparator 13 */ uint32_t DCRIS14 :1; /*!< Raw interrupt status of Digital Comparator 14 */ uint32_t DCRIS15 :1; /*!< Raw interrupt status of Digital Comparator 15 */ uint32_t DCRIS16 :1; /*!< Raw interrupt status of Digital Comparator 16 */ uint32_t DCRIS17 :1; /*!< Raw interrupt status of Digital Comparator 17 */ uint32_t DCRIS18 :1; /*!< Raw interrupt status of Digital Comparator 18 */ uint32_t DCRIS19 :1; /*!< Raw interrupt status of Digital Comparator 19 */ uint32_t DCRIS20 :1; /*!< Raw interrupt status of Digital Comparator 20 */ uint32_t DCRIS21 :1; /*!< Raw interrupt status of Digital Comparator 21 */ uint32_t DCRIS22 :1; /*!< Raw interrupt status of Digital Comparator 22 */ uint32_t DCRIS23 :1; /*!< Raw interrupt status of Digital Comparator 23 */ } _ADC_RIS_bits; /* Bit field positions: */ #define ADC_RIS_SEQRIS0_Pos 0 /*!< Sequencer 0 raw interrupt status */ #define ADC_RIS_SEQRIS1_Pos 1 /*!< Sequencer 1 raw interrupt status */ #define ADC_RIS_SEQRIS2_Pos 2 /*!< Sequencer 2 raw interrupt status */ #define ADC_RIS_SEQRIS3_Pos 3 /*!< Sequencer 3 raw interrupt status */ #define ADC_RIS_SEQRIS4_Pos 4 /*!< Sequencer 4 raw interrupt status */ #define ADC_RIS_SEQRIS5_Pos 5 /*!< Sequencer 5 raw interrupt status */ #define ADC_RIS_SEQRIS6_Pos 6 /*!< Sequencer 6 raw interrupt status */ #define ADC_RIS_SEQRIS7_Pos 7 /*!< Sequencer 7 raw interrupt status */ #define ADC_RIS_DCRIS0_Pos 8 /*!< Raw interrupt status of Digital Comparator 0 */ #define ADC_RIS_DCRIS1_Pos 9 /*!< Raw interrupt status of Digital Comparator 1 */ #define ADC_RIS_DCRIS2_Pos 10 /*!< Raw interrupt status of Digital Comparator 2 */ #define ADC_RIS_DCRIS3_Pos 11 /*!< Raw interrupt status of Digital Comparator 3 */ #define ADC_RIS_DCRIS4_Pos 12 /*!< Raw interrupt status of Digital Comparator 4 */ #define ADC_RIS_DCRIS5_Pos 13 /*!< Raw interrupt status of Digital Comparator 5 */ #define ADC_RIS_DCRIS6_Pos 14 /*!< Raw interrupt status of Digital Comparator 6 */ #define ADC_RIS_DCRIS7_Pos 15 /*!< Raw interrupt status of Digital Comparator 7 */ #define ADC_RIS_DCRIS8_Pos 16 /*!< Raw interrupt status of Digital Comparator 8 */ #define ADC_RIS_DCRIS9_Pos 17 /*!< Raw interrupt status of Digital Comparator 9 */ #define ADC_RIS_DCRIS10_Pos 18 /*!< Raw interrupt status of Digital Comparator 10 */ #define ADC_RIS_DCRIS11_Pos 19 /*!< Raw interrupt status of Digital Comparator 11 */ #define ADC_RIS_DCRIS12_Pos 20 /*!< Raw interrupt status of Digital Comparator 12 */ #define ADC_RIS_DCRIS13_Pos 21 /*!< Raw interrupt status of Digital Comparator 13 */ #define ADC_RIS_DCRIS14_Pos 22 /*!< Raw interrupt status of Digital Comparator 14 */ #define ADC_RIS_DCRIS15_Pos 23 /*!< Raw interrupt status of Digital Comparator 15 */ #define ADC_RIS_DCRIS16_Pos 24 /*!< Raw interrupt status of Digital Comparator 16 */ #define ADC_RIS_DCRIS17_Pos 25 /*!< Raw interrupt status of Digital Comparator 17 */ #define ADC_RIS_DCRIS18_Pos 26 /*!< Raw interrupt status of Digital Comparator 18 */ #define ADC_RIS_DCRIS19_Pos 27 /*!< Raw interrupt status of Digital Comparator 19 */ #define ADC_RIS_DCRIS20_Pos 28 /*!< Raw interrupt status of Digital Comparator 20 */ #define ADC_RIS_DCRIS21_Pos 29 /*!< Raw interrupt status of Digital Comparator 21 */ #define ADC_RIS_DCRIS22_Pos 30 /*!< Raw interrupt status of Digital Comparator 22 */ #define ADC_RIS_DCRIS23_Pos 31 /*!< Raw interrupt status of Digital Comparator 23 */ /* Bit field masks: */ #define ADC_RIS_SEQRIS0_Msk 0x00000001UL /*!< Sequencer 0 raw interrupt status */ #define ADC_RIS_SEQRIS1_Msk 0x00000002UL /*!< Sequencer 1 raw interrupt status */ #define ADC_RIS_SEQRIS2_Msk 0x00000004UL /*!< Sequencer 2 raw interrupt status */ #define ADC_RIS_SEQRIS3_Msk 0x00000008UL /*!< Sequencer 3 raw interrupt status */ #define ADC_RIS_SEQRIS4_Msk 0x00000010UL /*!< Sequencer 4 raw interrupt status */ #define ADC_RIS_SEQRIS5_Msk 0x00000020UL /*!< Sequencer 5 raw interrupt status */ #define ADC_RIS_SEQRIS6_Msk 0x00000040UL /*!< Sequencer 6 raw interrupt status */ #define ADC_RIS_SEQRIS7_Msk 0x00000080UL /*!< Sequencer 7 raw interrupt status */ #define ADC_RIS_DCRIS0_Msk 0x00000100UL /*!< Raw interrupt status of Digital Comparator 0 */ #define ADC_RIS_DCRIS1_Msk 0x00000200UL /*!< Raw interrupt status of Digital Comparator 1 */ #define ADC_RIS_DCRIS2_Msk 0x00000400UL /*!< Raw interrupt status of Digital Comparator 2 */ #define ADC_RIS_DCRIS3_Msk 0x00000800UL /*!< Raw interrupt status of Digital Comparator 3 */ #define ADC_RIS_DCRIS4_Msk 0x00001000UL /*!< Raw interrupt status of Digital Comparator 4 */ #define ADC_RIS_DCRIS5_Msk 0x00002000UL /*!< Raw interrupt status of Digital Comparator 5 */ #define ADC_RIS_DCRIS6_Msk 0x00004000UL /*!< Raw interrupt status of Digital Comparator 6 */ #define ADC_RIS_DCRIS7_Msk 0x00008000UL /*!< Raw interrupt status of Digital Comparator 7 */ #define ADC_RIS_DCRIS8_Msk 0x00010000UL /*!< Raw interrupt status of Digital Comparator 8 */ #define ADC_RIS_DCRIS9_Msk 0x00020000UL /*!< Raw interrupt status of Digital Comparator 9 */ #define ADC_RIS_DCRIS10_Msk 0x00040000UL /*!< Raw interrupt status of Digital Comparator 10 */ #define ADC_RIS_DCRIS11_Msk 0x00080000UL /*!< Raw interrupt status of Digital Comparator 11 */ #define ADC_RIS_DCRIS12_Msk 0x00100000UL /*!< Raw interrupt status of Digital Comparator 12 */ #define ADC_RIS_DCRIS13_Msk 0x00200000UL /*!< Raw interrupt status of Digital Comparator 13 */ #define ADC_RIS_DCRIS14_Msk 0x00400000UL /*!< Raw interrupt status of Digital Comparator 14 */ #define ADC_RIS_DCRIS15_Msk 0x00800000UL /*!< Raw interrupt status of Digital Comparator 15 */ #define ADC_RIS_DCRIS16_Msk 0x01000000UL /*!< Raw interrupt status of Digital Comparator 16 */ #define ADC_RIS_DCRIS17_Msk 0x02000000UL /*!< Raw interrupt status of Digital Comparator 17 */ #define ADC_RIS_DCRIS18_Msk 0x04000000UL /*!< Raw interrupt status of Digital Comparator 18 */ #define ADC_RIS_DCRIS19_Msk 0x08000000UL /*!< Raw interrupt status of Digital Comparator 19 */ #define ADC_RIS_DCRIS20_Msk 0x10000000UL /*!< Raw interrupt status of Digital Comparator 20 */ #define ADC_RIS_DCRIS21_Msk 0x20000000UL /*!< Raw interrupt status of Digital Comparator 21 */ #define ADC_RIS_DCRIS22_Msk 0x40000000UL /*!< Raw interrupt status of Digital Comparator 22 */ #define ADC_RIS_DCRIS23_Msk 0x80000000UL /*!< Raw interrupt status of Digital Comparator 23 */ /*-- IM: Interrupt mask register -----------------------------------------------------------------------------*/ typedef struct { uint32_t SEQIM0 :1; /*!< Sequencer 0 interrupt mask */ uint32_t SEQIM1 :1; /*!< Sequencer 1 interrupt mask */ uint32_t SEQIM2 :1; /*!< Sequencer 2 interrupt mask */ uint32_t SEQIM3 :1; /*!< Sequencer 3 interrupt mask */ uint32_t SEQIM4 :1; /*!< Sequencer 4 interrupt mask */ uint32_t SEQIM5 :1; /*!< Sequencer 5 interrupt mask */ uint32_t SEQIM6 :1; /*!< Sequencer 6 interrupt mask */ uint32_t SEQIM7 :1; /*!< Sequencer 7 interrupt mask */ uint32_t DCIM0 :1; /*!< Interrupt mask of Digital Comparator 0 */ uint32_t DCIM1 :1; /*!< Interrupt mask of Digital Comparator 1 */ uint32_t DCIM2 :1; /*!< Interrupt mask of Digital Comparator 2 */ uint32_t DCIM3 :1; /*!< Interrupt mask of Digital Comparator 3 */ uint32_t DCIM4 :1; /*!< Interrupt mask of Digital Comparator 4 */ uint32_t DCIM5 :1; /*!< Interrupt mask of Digital Comparator 5 */ uint32_t DCIM6 :1; /*!< Interrupt mask of Digital Comparator 6 */ uint32_t DCIM7 :1; /*!< Interrupt mask of Digital Comparator 7 */ uint32_t DCIM8 :1; /*!< Interrupt mask of Digital Comparator 8 */ uint32_t DCIM9 :1; /*!< Interrupt mask of Digital Comparator 9 */ uint32_t DCIM10 :1; /*!< Interrupt mask of Digital Comparator 10 */ uint32_t DCIM11 :1; /*!< Interrupt mask of Digital Comparator 11 */ uint32_t DCIM12 :1; /*!< Interrupt mask of Digital Comparator 12 */ uint32_t DCIM13 :1; /*!< Interrupt mask of Digital Comparator 13 */ uint32_t DCIM14 :1; /*!< Interrupt mask of Digital Comparator 14 */ uint32_t DCIM15 :1; /*!< Interrupt mask of Digital Comparator 15 */ uint32_t DCIM16 :1; /*!< Interrupt mask of Digital Comparator 16 */ uint32_t DCIM17 :1; /*!< Interrupt mask of Digital Comparator 17 */ uint32_t DCIM18 :1; /*!< Interrupt mask of Digital Comparator 18 */ uint32_t DCIM19 :1; /*!< Interrupt mask of Digital Comparator 19 */ uint32_t DCIM20 :1; /*!< Interrupt mask of Digital Comparator 20 */ uint32_t DCIM21 :1; /*!< Interrupt mask of Digital Comparator 21 */ uint32_t DCIM22 :1; /*!< Interrupt mask of Digital Comparator 22 */ uint32_t DCIM23 :1; /*!< Interrupt mask of Digital Comparator 23 */ } _ADC_IM_bits; /* Bit field positions: */ #define ADC_IM_SEQIM0_Pos 0 /*!< Sequencer 0 interrupt mask */ #define ADC_IM_SEQIM1_Pos 1 /*!< Sequencer 1 interrupt mask */ #define ADC_IM_SEQIM2_Pos 2 /*!< Sequencer 2 interrupt mask */ #define ADC_IM_SEQIM3_Pos 3 /*!< Sequencer 3 interrupt mask */ #define ADC_IM_SEQIM4_Pos 4 /*!< Sequencer 4 interrupt mask */ #define ADC_IM_SEQIM5_Pos 5 /*!< Sequencer 5 interrupt mask */ #define ADC_IM_SEQIM6_Pos 6 /*!< Sequencer 6 interrupt mask */ #define ADC_IM_SEQIM7_Pos 7 /*!< Sequencer 7 interrupt mask */ #define ADC_IM_DCIM0_Pos 8 /*!< Interrupt mask of Digital Comparator 0 */ #define ADC_IM_DCIM1_Pos 9 /*!< Interrupt mask of Digital Comparator 1 */ #define ADC_IM_DCIM2_Pos 10 /*!< Interrupt mask of Digital Comparator 2 */ #define ADC_IM_DCIM3_Pos 11 /*!< Interrupt mask of Digital Comparator 3 */ #define ADC_IM_DCIM4_Pos 12 /*!< Interrupt mask of Digital Comparator 4 */ #define ADC_IM_DCIM5_Pos 13 /*!< Interrupt mask of Digital Comparator 5 */ #define ADC_IM_DCIM6_Pos 14 /*!< Interrupt mask of Digital Comparator 6 */ #define ADC_IM_DCIM7_Pos 15 /*!< Interrupt mask of Digital Comparator 7 */ #define ADC_IM_DCIM8_Pos 16 /*!< Interrupt mask of Digital Comparator 8 */ #define ADC_IM_DCIM9_Pos 17 /*!< Interrupt mask of Digital Comparator 9 */ #define ADC_IM_DCIM10_Pos 18 /*!< Interrupt mask of Digital Comparator 10 */ #define ADC_IM_DCIM11_Pos 19 /*!< Interrupt mask of Digital Comparator 11 */ #define ADC_IM_DCIM12_Pos 20 /*!< Interrupt mask of Digital Comparator 12 */ #define ADC_IM_DCIM13_Pos 21 /*!< Interrupt mask of Digital Comparator 13 */ #define ADC_IM_DCIM14_Pos 22 /*!< Interrupt mask of Digital Comparator 14 */ #define ADC_IM_DCIM15_Pos 23 /*!< Interrupt mask of Digital Comparator 15 */ #define ADC_IM_DCIM16_Pos 24 /*!< Interrupt mask of Digital Comparator 16 */ #define ADC_IM_DCIM17_Pos 25 /*!< Interrupt mask of Digital Comparator 17 */ #define ADC_IM_DCIM18_Pos 26 /*!< Interrupt mask of Digital Comparator 18 */ #define ADC_IM_DCIM19_Pos 27 /*!< Interrupt mask of Digital Comparator 19 */ #define ADC_IM_DCIM20_Pos 28 /*!< Interrupt mask of Digital Comparator 20 */ #define ADC_IM_DCIM21_Pos 29 /*!< Interrupt mask of Digital Comparator 21 */ #define ADC_IM_DCIM22_Pos 30 /*!< Interrupt mask of Digital Comparator 22 */ #define ADC_IM_DCIM23_Pos 31 /*!< Interrupt mask of Digital Comparator 23 */ /* Bit field masks: */ #define ADC_IM_SEQIM0_Msk 0x00000001UL /*!< Sequencer 0 interrupt mask */ #define ADC_IM_SEQIM1_Msk 0x00000002UL /*!< Sequencer 1 interrupt mask */ #define ADC_IM_SEQIM2_Msk 0x00000004UL /*!< Sequencer 2 interrupt mask */ #define ADC_IM_SEQIM3_Msk 0x00000008UL /*!< Sequencer 3 interrupt mask */ #define ADC_IM_SEQIM4_Msk 0x00000010UL /*!< Sequencer 4 interrupt mask */ #define ADC_IM_SEQIM5_Msk 0x00000020UL /*!< Sequencer 5 interrupt mask */ #define ADC_IM_SEQIM6_Msk 0x00000040UL /*!< Sequencer 6 interrupt mask */ #define ADC_IM_SEQIM7_Msk 0x00000080UL /*!< Sequencer 7 interrupt mask */ #define ADC_IM_DCIM0_Msk 0x00000100UL /*!< Interrupt mask of Digital Comparator 0 */ #define ADC_IM_DCIM1_Msk 0x00000200UL /*!< Interrupt mask of Digital Comparator 1 */ #define ADC_IM_DCIM2_Msk 0x00000400UL /*!< Interrupt mask of Digital Comparator 2 */ #define ADC_IM_DCIM3_Msk 0x00000800UL /*!< Interrupt mask of Digital Comparator 3 */ #define ADC_IM_DCIM4_Msk 0x00001000UL /*!< Interrupt mask of Digital Comparator 4 */ #define ADC_IM_DCIM5_Msk 0x00002000UL /*!< Interrupt mask of Digital Comparator 5 */ #define ADC_IM_DCIM6_Msk 0x00004000UL /*!< Interrupt mask of Digital Comparator 6 */ #define ADC_IM_DCIM7_Msk 0x00008000UL /*!< Interrupt mask of Digital Comparator 7 */ #define ADC_IM_DCIM8_Msk 0x00010000UL /*!< Interrupt mask of Digital Comparator 8 */ #define ADC_IM_DCIM9_Msk 0x00020000UL /*!< Interrupt mask of Digital Comparator 9 */ #define ADC_IM_DCIM10_Msk 0x00040000UL /*!< Interrupt mask of Digital Comparator 10 */ #define ADC_IM_DCIM11_Msk 0x00080000UL /*!< Interrupt mask of Digital Comparator 11 */ #define ADC_IM_DCIM12_Msk 0x00100000UL /*!< Interrupt mask of Digital Comparator 12 */ #define ADC_IM_DCIM13_Msk 0x00200000UL /*!< Interrupt mask of Digital Comparator 13 */ #define ADC_IM_DCIM14_Msk 0x00400000UL /*!< Interrupt mask of Digital Comparator 14 */ #define ADC_IM_DCIM15_Msk 0x00800000UL /*!< Interrupt mask of Digital Comparator 15 */ #define ADC_IM_DCIM16_Msk 0x01000000UL /*!< Interrupt mask of Digital Comparator 16 */ #define ADC_IM_DCIM17_Msk 0x02000000UL /*!< Interrupt mask of Digital Comparator 17 */ #define ADC_IM_DCIM18_Msk 0x04000000UL /*!< Interrupt mask of Digital Comparator 18 */ #define ADC_IM_DCIM19_Msk 0x08000000UL /*!< Interrupt mask of Digital Comparator 19 */ #define ADC_IM_DCIM20_Msk 0x10000000UL /*!< Interrupt mask of Digital Comparator 20 */ #define ADC_IM_DCIM21_Msk 0x20000000UL /*!< Interrupt mask of Digital Comparator 21 */ #define ADC_IM_DCIM22_Msk 0x40000000UL /*!< Interrupt mask of Digital Comparator 22 */ #define ADC_IM_DCIM23_Msk 0x80000000UL /*!< Interrupt mask of Digital Comparator 23 */ /*-- MIS: Masked interrupt status and clear register ---------------------------------------------------------*/ typedef struct { uint32_t SEQMIS0 :1; /*!< Sequencer 0 masked interrupt status */ uint32_t SEQMIS1 :1; /*!< Sequencer 1 masked interrupt status */ uint32_t SEQMIS2 :1; /*!< Sequencer 2 masked interrupt status */ uint32_t SEQMIS3 :1; /*!< Sequencer 3 masked interrupt status */ uint32_t SEQMIS4 :1; /*!< Sequencer 4 masked interrupt status */ uint32_t SEQMIS5 :1; /*!< Sequencer 5 masked interrupt status */ uint32_t SEQMIS6 :1; /*!< Sequencer 6 masked interrupt status */ uint32_t SEQMIS7 :1; /*!< Sequencer 7 masked interrupt status */ uint32_t DCMIS0 :1; /*!< DC 0 masked interrupt status */ uint32_t DCMIS1 :1; /*!< DC 1 masked interrupt status */ uint32_t DCMIS2 :1; /*!< DC 2 masked interrupt status */ uint32_t DCMIS3 :1; /*!< DC 3 masked interrupt status */ uint32_t DCMIS4 :1; /*!< DC 4 masked interrupt status */ uint32_t DCMIS5 :1; /*!< DC 5 masked interrupt status */ uint32_t DCMIS6 :1; /*!< DC 6 masked interrupt status */ uint32_t DCMIS7 :1; /*!< DC 7 masked interrupt status */ uint32_t DCMIS8 :1; /*!< DC 8 masked interrupt status */ uint32_t DCMIS9 :1; /*!< DC 9 masked interrupt status */ uint32_t DCMIS10 :1; /*!< DC 10 masked interrupt status */ uint32_t DCMIS11 :1; /*!< DC 11 masked interrupt status */ uint32_t DCMIS12 :1; /*!< DC 12 masked interrupt status */ uint32_t DCMIS13 :1; /*!< DC 13 masked interrupt status */ uint32_t DCMIS14 :1; /*!< DC 14 masked interrupt status */ uint32_t DCMIS15 :1; /*!< DC 15 masked interrupt status */ uint32_t DCMIS16 :1; /*!< DC 16 masked interrupt status */ uint32_t DCMIS17 :1; /*!< DC 17 masked interrupt status */ uint32_t DCMIS18 :1; /*!< DC 18 masked interrupt status */ uint32_t DCMIS19 :1; /*!< DC 19 masked interrupt status */ uint32_t DCMIS20 :1; /*!< DC 20 masked interrupt status */ uint32_t DCMIS21 :1; /*!< DC 21 masked interrupt status */ uint32_t DCMIS22 :1; /*!< DC 22 masked interrupt status */ uint32_t DCMIS23 :1; /*!< DC 23 masked interrupt status */ } _ADC_MIS_bits; /* Bit field positions: */ #define ADC_MIS_SEQMIS0_Pos 0 /*!< Sequencer 0 masked interrupt status */ #define ADC_MIS_SEQMIS1_Pos 1 /*!< Sequencer 1 masked interrupt status */ #define ADC_MIS_SEQMIS2_Pos 2 /*!< Sequencer 2 masked interrupt status */ #define ADC_MIS_SEQMIS3_Pos 3 /*!< Sequencer 3 masked interrupt status */ #define ADC_MIS_SEQMIS4_Pos 4 /*!< Sequencer 4 masked interrupt status */ #define ADC_MIS_SEQMIS5_Pos 5 /*!< Sequencer 5 masked interrupt status */ #define ADC_MIS_SEQMIS6_Pos 6 /*!< Sequencer 6 masked interrupt status */ #define ADC_MIS_SEQMIS7_Pos 7 /*!< Sequencer 7 masked interrupt status */ #define ADC_MIS_DCMIS0_Pos 8 /*!< DC 0 masked interrupt status */ #define ADC_MIS_DCMIS1_Pos 9 /*!< DC 1 masked interrupt status */ #define ADC_MIS_DCMIS2_Pos 10 /*!< DC 2 masked interrupt status */ #define ADC_MIS_DCMIS3_Pos 11 /*!< DC 3 masked interrupt status */ #define ADC_MIS_DCMIS4_Pos 12 /*!< DC 4 masked interrupt status */ #define ADC_MIS_DCMIS5_Pos 13 /*!< DC 5 masked interrupt status */ #define ADC_MIS_DCMIS6_Pos 14 /*!< DC 6 masked interrupt status */ #define ADC_MIS_DCMIS7_Pos 15 /*!< DC 7 masked interrupt status */ #define ADC_MIS_DCMIS8_Pos 16 /*!< DC 8 masked interrupt status */ #define ADC_MIS_DCMIS9_Pos 17 /*!< DC 9 masked interrupt status */ #define ADC_MIS_DCMIS10_Pos 18 /*!< DC 10 masked interrupt status */ #define ADC_MIS_DCMIS11_Pos 19 /*!< DC 11 masked interrupt status */ #define ADC_MIS_DCMIS12_Pos 20 /*!< DC 12 masked interrupt status */ #define ADC_MIS_DCMIS13_Pos 21 /*!< DC 13 masked interrupt status */ #define ADC_MIS_DCMIS14_Pos 22 /*!< DC 14 masked interrupt status */ #define ADC_MIS_DCMIS15_Pos 23 /*!< DC 15 masked interrupt status */ #define ADC_MIS_DCMIS16_Pos 24 /*!< DC 16 masked interrupt status */ #define ADC_MIS_DCMIS17_Pos 25 /*!< DC 17 masked interrupt status */ #define ADC_MIS_DCMIS18_Pos 26 /*!< DC 18 masked interrupt status */ #define ADC_MIS_DCMIS19_Pos 27 /*!< DC 19 masked interrupt status */ #define ADC_MIS_DCMIS20_Pos 28 /*!< DC 20 masked interrupt status */ #define ADC_MIS_DCMIS21_Pos 29 /*!< DC 21 masked interrupt status */ #define ADC_MIS_DCMIS22_Pos 30 /*!< DC 22 masked interrupt status */ #define ADC_MIS_DCMIS23_Pos 31 /*!< DC 23 masked interrupt status */ /* Bit field masks: */ #define ADC_MIS_SEQMIS0_Msk 0x00000001UL /*!< Sequencer 0 masked interrupt status */ #define ADC_MIS_SEQMIS1_Msk 0x00000002UL /*!< Sequencer 1 masked interrupt status */ #define ADC_MIS_SEQMIS2_Msk 0x00000004UL /*!< Sequencer 2 masked interrupt status */ #define ADC_MIS_SEQMIS3_Msk 0x00000008UL /*!< Sequencer 3 masked interrupt status */ #define ADC_MIS_SEQMIS4_Msk 0x00000010UL /*!< Sequencer 4 masked interrupt status */ #define ADC_MIS_SEQMIS5_Msk 0x00000020UL /*!< Sequencer 5 masked interrupt status */ #define ADC_MIS_SEQMIS6_Msk 0x00000040UL /*!< Sequencer 6 masked interrupt status */ #define ADC_MIS_SEQMIS7_Msk 0x00000080UL /*!< Sequencer 7 masked interrupt status */ #define ADC_MIS_DCMIS0_Msk 0x00000100UL /*!< DC 0 masked interrupt status */ #define ADC_MIS_DCMIS1_Msk 0x00000200UL /*!< DC 1 masked interrupt status */ #define ADC_MIS_DCMIS2_Msk 0x00000400UL /*!< DC 2 masked interrupt status */ #define ADC_MIS_DCMIS3_Msk 0x00000800UL /*!< DC 3 masked interrupt status */ #define ADC_MIS_DCMIS4_Msk 0x00001000UL /*!< DC 4 masked interrupt status */ #define ADC_MIS_DCMIS5_Msk 0x00002000UL /*!< DC 5 masked interrupt status */ #define ADC_MIS_DCMIS6_Msk 0x00004000UL /*!< DC 6 masked interrupt status */ #define ADC_MIS_DCMIS7_Msk 0x00008000UL /*!< DC 7 masked interrupt status */ #define ADC_MIS_DCMIS8_Msk 0x00010000UL /*!< DC 8 masked interrupt status */ #define ADC_MIS_DCMIS9_Msk 0x00020000UL /*!< DC 9 masked interrupt status */ #define ADC_MIS_DCMIS10_Msk 0x00040000UL /*!< DC 10 masked interrupt status */ #define ADC_MIS_DCMIS11_Msk 0x00080000UL /*!< DC 11 masked interrupt status */ #define ADC_MIS_DCMIS12_Msk 0x00100000UL /*!< DC 12 masked interrupt status */ #define ADC_MIS_DCMIS13_Msk 0x00200000UL /*!< DC 13 masked interrupt status */ #define ADC_MIS_DCMIS14_Msk 0x00400000UL /*!< DC 14 masked interrupt status */ #define ADC_MIS_DCMIS15_Msk 0x00800000UL /*!< DC 15 masked interrupt status */ #define ADC_MIS_DCMIS16_Msk 0x01000000UL /*!< DC 16 masked interrupt status */ #define ADC_MIS_DCMIS17_Msk 0x02000000UL /*!< DC 17 masked interrupt status */ #define ADC_MIS_DCMIS18_Msk 0x04000000UL /*!< DC 18 masked interrupt status */ #define ADC_MIS_DCMIS19_Msk 0x08000000UL /*!< DC 19 masked interrupt status */ #define ADC_MIS_DCMIS20_Msk 0x10000000UL /*!< DC 20 masked interrupt status */ #define ADC_MIS_DCMIS21_Msk 0x20000000UL /*!< DC 21 masked interrupt status */ #define ADC_MIS_DCMIS22_Msk 0x40000000UL /*!< DC 22 masked interrupt status */ #define ADC_MIS_DCMIS23_Msk 0x80000000UL /*!< DC 23 masked interrupt status */ /*-- IC: Interrupt clear register ----------------------------------------------------------------------------*/ typedef struct { uint32_t SEQIC0 :1; /*!< Sequencer 0 interrupt status clear */ uint32_t SEQIC1 :1; /*!< Sequencer 1 interrupt status clear */ uint32_t SEQIC2 :1; /*!< Sequencer 2 interrupt status clear */ uint32_t SEQIC3 :1; /*!< Sequencer 3 interrupt status clear */ uint32_t SEQIC4 :1; /*!< Sequencer 4 interrupt status clear */ uint32_t SEQIC5 :1; /*!< Sequencer 5 interrupt status clear */ uint32_t SEQIC6 :1; /*!< Sequencer 6 interrupt status clear */ uint32_t SEQIC7 :1; /*!< Sequencer 7 interrupt status clear */ uint32_t DCIC0 :1; /*!< DC 0 interrupt status clear */ uint32_t DCIC1 :1; /*!< DC 1 interrupt status clear */ uint32_t DCIC2 :1; /*!< DC 2 interrupt status clear */ uint32_t DCIC3 :1; /*!< DC 3 interrupt status clear */ uint32_t DCIC4 :1; /*!< DC 4 interrupt status clear */ uint32_t DCIC5 :1; /*!< DC 5 interrupt status clear */ uint32_t DCIC6 :1; /*!< DC 6 interrupt status clear */ uint32_t DCIC7 :1; /*!< DC 7 interrupt status clear */ uint32_t DCIC8 :1; /*!< DC 8 interrupt status clear */ uint32_t DCIC9 :1; /*!< DC 9 interrupt status clear */ uint32_t DCIC10 :1; /*!< DC 10 interrupt status clear */ uint32_t DCIC11 :1; /*!< DC 11 interrupt status clear */ uint32_t DCIC12 :1; /*!< DC 12 interrupt status clear */ uint32_t DCIC13 :1; /*!< DC 13 interrupt status clear */ uint32_t DCIC14 :1; /*!< DC 14 interrupt status clear */ uint32_t DCIC15 :1; /*!< DC 15 interrupt status clear */ uint32_t DCIC16 :1; /*!< DC 16 interrupt status clear */ uint32_t DCIC17 :1; /*!< DC 17 interrupt status clear */ uint32_t DCIC18 :1; /*!< DC 18 interrupt status clear */ uint32_t DCIC19 :1; /*!< DC 19 interrupt status clear */ uint32_t DCIC20 :1; /*!< DC 20 interrupt status clear */ uint32_t DCIC21 :1; /*!< DC 21 interrupt status clear */ uint32_t DCIC22 :1; /*!< DC 22 interrupt status clear */ uint32_t DCIC23 :1; /*!< DC 23 interrupt status clear */ } _ADC_IC_bits; /* Bit field positions: */ #define ADC_IC_SEQIC0_Pos 0 /*!< Sequencer 0 interrupt status clear */ #define ADC_IC_SEQIC1_Pos 1 /*!< Sequencer 1 interrupt status clear */ #define ADC_IC_SEQIC2_Pos 2 /*!< Sequencer 2 interrupt status clear */ #define ADC_IC_SEQIC3_Pos 3 /*!< Sequencer 3 interrupt status clear */ #define ADC_IC_SEQIC4_Pos 4 /*!< Sequencer 4 interrupt status clear */ #define ADC_IC_SEQIC5_Pos 5 /*!< Sequencer 5 interrupt status clear */ #define ADC_IC_SEQIC6_Pos 6 /*!< Sequencer 6 interrupt status clear */ #define ADC_IC_SEQIC7_Pos 7 /*!< Sequencer 7 interrupt status clear */ #define ADC_IC_DCIC0_Pos 8 /*!< DC 0 interrupt status clear */ #define ADC_IC_DCIC1_Pos 9 /*!< DC 1 interrupt status clear */ #define ADC_IC_DCIC2_Pos 10 /*!< DC 2 interrupt status clear */ #define ADC_IC_DCIC3_Pos 11 /*!< DC 3 interrupt status clear */ #define ADC_IC_DCIC4_Pos 12 /*!< DC 4 interrupt status clear */ #define ADC_IC_DCIC5_Pos 13 /*!< DC 5 interrupt status clear */ #define ADC_IC_DCIC6_Pos 14 /*!< DC 6 interrupt status clear */ #define ADC_IC_DCIC7_Pos 15 /*!< DC 7 interrupt status clear */ #define ADC_IC_DCIC8_Pos 16 /*!< DC 8 interrupt status clear */ #define ADC_IC_DCIC9_Pos 17 /*!< DC 9 interrupt status clear */ #define ADC_IC_DCIC10_Pos 18 /*!< DC 10 interrupt status clear */ #define ADC_IC_DCIC11_Pos 19 /*!< DC 11 interrupt status clear */ #define ADC_IC_DCIC12_Pos 20 /*!< DC 12 interrupt status clear */ #define ADC_IC_DCIC13_Pos 21 /*!< DC 13 interrupt status clear */ #define ADC_IC_DCIC14_Pos 22 /*!< DC 14 interrupt status clear */ #define ADC_IC_DCIC15_Pos 23 /*!< DC 15 interrupt status clear */ #define ADC_IC_DCIC16_Pos 24 /*!< DC 16 interrupt status clear */ #define ADC_IC_DCIC17_Pos 25 /*!< DC 17 interrupt status clear */ #define ADC_IC_DCIC18_Pos 26 /*!< DC 18 interrupt status clear */ #define ADC_IC_DCIC19_Pos 27 /*!< DC 19 interrupt status clear */ #define ADC_IC_DCIC20_Pos 28 /*!< DC 20 interrupt status clear */ #define ADC_IC_DCIC21_Pos 29 /*!< DC 21 interrupt status clear */ #define ADC_IC_DCIC22_Pos 30 /*!< DC 22 interrupt status clear */ #define ADC_IC_DCIC23_Pos 31 /*!< DC 23 interrupt status clear */ /* Bit field masks: */ #define ADC_IC_SEQIC0_Msk 0x00000001UL /*!< Sequencer 0 interrupt status clear */ #define ADC_IC_SEQIC1_Msk 0x00000002UL /*!< Sequencer 1 interrupt status clear */ #define ADC_IC_SEQIC2_Msk 0x00000004UL /*!< Sequencer 2 interrupt status clear */ #define ADC_IC_SEQIC3_Msk 0x00000008UL /*!< Sequencer 3 interrupt status clear */ #define ADC_IC_SEQIC4_Msk 0x00000010UL /*!< Sequencer 4 interrupt status clear */ #define ADC_IC_SEQIC5_Msk 0x00000020UL /*!< Sequencer 5 interrupt status clear */ #define ADC_IC_SEQIC6_Msk 0x00000040UL /*!< Sequencer 6 interrupt status clear */ #define ADC_IC_SEQIC7_Msk 0x00000080UL /*!< Sequencer 7 interrupt status clear */ #define ADC_IC_DCIC0_Msk 0x00000100UL /*!< DC 0 interrupt status clear */ #define ADC_IC_DCIC1_Msk 0x00000200UL /*!< DC 1 interrupt status clear */ #define ADC_IC_DCIC2_Msk 0x00000400UL /*!< DC 2 interrupt status clear */ #define ADC_IC_DCIC3_Msk 0x00000800UL /*!< DC 3 interrupt status clear */ #define ADC_IC_DCIC4_Msk 0x00001000UL /*!< DC 4 interrupt status clear */ #define ADC_IC_DCIC5_Msk 0x00002000UL /*!< DC 5 interrupt status clear */ #define ADC_IC_DCIC6_Msk 0x00004000UL /*!< DC 6 interrupt status clear */ #define ADC_IC_DCIC7_Msk 0x00008000UL /*!< DC 7 interrupt status clear */ #define ADC_IC_DCIC8_Msk 0x00010000UL /*!< DC 8 interrupt status clear */ #define ADC_IC_DCIC9_Msk 0x00020000UL /*!< DC 9 interrupt status clear */ #define ADC_IC_DCIC10_Msk 0x00040000UL /*!< DC 10 interrupt status clear */ #define ADC_IC_DCIC11_Msk 0x00080000UL /*!< DC 11 interrupt status clear */ #define ADC_IC_DCIC12_Msk 0x00100000UL /*!< DC 12 interrupt status clear */ #define ADC_IC_DCIC13_Msk 0x00200000UL /*!< DC 13 interrupt status clear */ #define ADC_IC_DCIC14_Msk 0x00400000UL /*!< DC 14 interrupt status clear */ #define ADC_IC_DCIC15_Msk 0x00800000UL /*!< DC 15 interrupt status clear */ #define ADC_IC_DCIC16_Msk 0x01000000UL /*!< DC 16 interrupt status clear */ #define ADC_IC_DCIC17_Msk 0x02000000UL /*!< DC 17 interrupt status clear */ #define ADC_IC_DCIC18_Msk 0x04000000UL /*!< DC 18 interrupt status clear */ #define ADC_IC_DCIC19_Msk 0x08000000UL /*!< DC 19 interrupt status clear */ #define ADC_IC_DCIC20_Msk 0x10000000UL /*!< DC 20 interrupt status clear */ #define ADC_IC_DCIC21_Msk 0x20000000UL /*!< DC 21 interrupt status clear */ #define ADC_IC_DCIC22_Msk 0x40000000UL /*!< DC 22 interrupt status clear */ #define ADC_IC_DCIC23_Msk 0x80000000UL /*!< DC 23 interrupt status clear */ /*-- SEQ: SRQSEL0: Sequencer request ADC channels selection register 0 ----------------------------------------*/ typedef struct { uint32_t RQ0 :6; /*!< Select ADC channel for request 0 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ1 :6; /*!< Select ADC channel for request 1 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ2 :6; /*!< Select ADC channel for request 2 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ3 :6; /*!< Select ADC channel for request 3 */ } _ADC_SEQ_SRQSEL0_bits; /* Bit field positions: */ #define ADC_SEQ_SRQSEL0_RQ0_Pos 0 /*!< Select ADC channel for request 0 */ #define ADC_SEQ_SRQSEL0_RQ1_Pos 8 /*!< Select ADC channel for request 1 */ #define ADC_SEQ_SRQSEL0_RQ2_Pos 16 /*!< Select ADC channel for request 2 */ #define ADC_SEQ_SRQSEL0_RQ3_Pos 24 /*!< Select ADC channel for request 3 */ /* Bit field masks: */ #define ADC_SEQ_SRQSEL0_RQ0_Msk 0x0000003FUL /*!< Select ADC channel for request 0 */ #define ADC_SEQ_SRQSEL0_RQ1_Msk 0x00003F00UL /*!< Select ADC channel for request 1 */ #define ADC_SEQ_SRQSEL0_RQ2_Msk 0x003F0000UL /*!< Select ADC channel for request 2 */ #define ADC_SEQ_SRQSEL0_RQ3_Msk 0x3F000000UL /*!< Select ADC channel for request 3 */ /*-- SEQ: SRQSEL1: Sequencer request ADC channels selection register 1 ----------------------------------------*/ typedef struct { uint32_t RQ4 :6; /*!< Select ADC channel for request 4 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ5 :6; /*!< Select ADC channel for request 5 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ6 :6; /*!< Select ADC channel for request 6 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ7 :6; /*!< Select ADC channel for request 7 */ } _ADC_SEQ_SRQSEL1_bits; /* Bit field positions: */ #define ADC_SEQ_SRQSEL1_RQ4_Pos 0 /*!< Select ADC channel for request 4 */ #define ADC_SEQ_SRQSEL1_RQ5_Pos 8 /*!< Select ADC channel for request 5 */ #define ADC_SEQ_SRQSEL1_RQ6_Pos 16 /*!< Select ADC channel for request 6 */ #define ADC_SEQ_SRQSEL1_RQ7_Pos 24 /*!< Select ADC channel for request 7 */ /* Bit field masks: */ #define ADC_SEQ_SRQSEL1_RQ4_Msk 0x0000003FUL /*!< Select ADC channel for request 4 */ #define ADC_SEQ_SRQSEL1_RQ5_Msk 0x00003F00UL /*!< Select ADC channel for request 5 */ #define ADC_SEQ_SRQSEL1_RQ6_Msk 0x003F0000UL /*!< Select ADC channel for request 6 */ #define ADC_SEQ_SRQSEL1_RQ7_Msk 0x3F000000UL /*!< Select ADC channel for request 7 */ /*-- SEQ: SRQSEL2: Sequencer request ADC channels selection register 2 ----------------------------------------*/ typedef struct { uint32_t RQ8 :6; /*!< Select ADC channel for request 8 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ9 :6; /*!< Select ADC channel for request 9 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ10 :6; /*!< Select ADC channel for request 10 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ11 :6; /*!< Select ADC channel for request 11 */ } _ADC_SEQ_SRQSEL2_bits; /* Bit field positions: */ #define ADC_SEQ_SRQSEL2_RQ8_Pos 0 /*!< Select ADC channel for request 8 */ #define ADC_SEQ_SRQSEL2_RQ9_Pos 8 /*!< Select ADC channel for request 9 */ #define ADC_SEQ_SRQSEL2_RQ10_Pos 16 /*!< Select ADC channel for request 10 */ #define ADC_SEQ_SRQSEL2_RQ11_Pos 24 /*!< Select ADC channel for request 11 */ /* Bit field masks: */ #define ADC_SEQ_SRQSEL2_RQ8_Msk 0x0000003FUL /*!< Select ADC channel for request 8 */ #define ADC_SEQ_SRQSEL2_RQ9_Msk 0x00003F00UL /*!< Select ADC channel for request 9 */ #define ADC_SEQ_SRQSEL2_RQ10_Msk 0x003F0000UL /*!< Select ADC channel for request 10 */ #define ADC_SEQ_SRQSEL2_RQ11_Msk 0x3F000000UL /*!< Select ADC channel for request 11 */ /*-- SEQ: SRQSEL3: Sequencer request ADC channels selection register 3 ----------------------------------------*/ typedef struct { uint32_t RQ12 :6; /*!< Select ADC channel for request 12 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ13 :6; /*!< Select ADC channel for request 13 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ14 :6; /*!< Select ADC channel for request 14 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ15 :6; /*!< Select ADC channel for request 15 */ } _ADC_SEQ_SRQSEL3_bits; /* Bit field positions: */ #define ADC_SEQ_SRQSEL3_RQ12_Pos 0 /*!< Select ADC channel for request 12 */ #define ADC_SEQ_SRQSEL3_RQ13_Pos 8 /*!< Select ADC channel for request 13 */ #define ADC_SEQ_SRQSEL3_RQ14_Pos 16 /*!< Select ADC channel for request 14 */ #define ADC_SEQ_SRQSEL3_RQ15_Pos 24 /*!< Select ADC channel for request 15 */ /* Bit field masks: */ #define ADC_SEQ_SRQSEL3_RQ12_Msk 0x0000003FUL /*!< Select ADC channel for request 12 */ #define ADC_SEQ_SRQSEL3_RQ13_Msk 0x00003F00UL /*!< Select ADC channel for request 13 */ #define ADC_SEQ_SRQSEL3_RQ14_Msk 0x003F0000UL /*!< Select ADC channel for request 14 */ #define ADC_SEQ_SRQSEL3_RQ15_Msk 0x3F000000UL /*!< Select ADC channel for request 15 */ /*-- SEQ: SRQSEL4: Sequencer request ADC channels selection register 4 ----------------------------------------*/ typedef struct { uint32_t RQ16 :6; /*!< Select ADC channel for request 16 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ17 :6; /*!< Select ADC channel for request 17 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ18 :6; /*!< Select ADC channel for request 18 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ19 :6; /*!< Select ADC channel for request 19 */ } _ADC_SEQ_SRQSEL4_bits; /* Bit field positions: */ #define ADC_SEQ_SRQSEL4_RQ16_Pos 0 /*!< Select ADC channel for request 16 */ #define ADC_SEQ_SRQSEL4_RQ17_Pos 8 /*!< Select ADC channel for request 17 */ #define ADC_SEQ_SRQSEL4_RQ18_Pos 16 /*!< Select ADC channel for request 18 */ #define ADC_SEQ_SRQSEL4_RQ19_Pos 24 /*!< Select ADC channel for request 19 */ /* Bit field masks: */ #define ADC_SEQ_SRQSEL4_RQ16_Msk 0x0000003FUL /*!< Select ADC channel for request 16 */ #define ADC_SEQ_SRQSEL4_RQ17_Msk 0x00003F00UL /*!< Select ADC channel for request 17 */ #define ADC_SEQ_SRQSEL4_RQ18_Msk 0x003F0000UL /*!< Select ADC channel for request 18 */ #define ADC_SEQ_SRQSEL4_RQ19_Msk 0x3F000000UL /*!< Select ADC channel for request 19 */ /*-- SEQ: SRQSEL5: Sequencer request ADC channels selection register 5 ----------------------------------------*/ typedef struct { uint32_t RQ20 :6; /*!< Select ADC channel for request 20 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ21 :6; /*!< Select ADC channel for request 21 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ22 :6; /*!< Select ADC channel for request 22 */ uint32_t :2; /*!< RESERVED */ uint32_t RQ23 :6; /*!< Select ADC channel for request 23 */ } _ADC_SEQ_SRQSEL5_bits; /* Bit field positions: */ #define ADC_SEQ_SRQSEL5_RQ20_Pos 0 /*!< Select ADC channel for request 20 */ #define ADC_SEQ_SRQSEL5_RQ21_Pos 8 /*!< Select ADC channel for request 21 */ #define ADC_SEQ_SRQSEL5_RQ22_Pos 16 /*!< Select ADC channel for request 22 */ #define ADC_SEQ_SRQSEL5_RQ23_Pos 24 /*!< Select ADC channel for request 23 */ /* Bit field masks: */ #define ADC_SEQ_SRQSEL5_RQ20_Msk 0x0000003FUL /*!< Select ADC channel for request 20 */ #define ADC_SEQ_SRQSEL5_RQ21_Msk 0x00003F00UL /*!< Select ADC channel for request 21 */ #define ADC_SEQ_SRQSEL5_RQ22_Msk 0x003F0000UL /*!< Select ADC channel for request 22 */ #define ADC_SEQ_SRQSEL5_RQ23_Msk 0x3F000000UL /*!< Select ADC channel for request 23 */ /*-- SEQ: SRQCTL: Sequencer request control register ----------------------------------------------------------*/ typedef struct { uint32_t RQMAX :5; /*!< Request queue max depth */ uint32_t :3; /*!< RESERVED */ uint32_t QAVGEN :1; /*!< Queue avearage (scanning) enable */ uint32_t QAVGVAL :3; /*!< Queue average value */ } _ADC_SEQ_SRQCTL_bits; /* Bit field positions: */ #define ADC_SEQ_SRQCTL_RQMAX_Pos 0 /*!< Request queue max depth */ #define ADC_SEQ_SRQCTL_QAVGEN_Pos 8 /*!< Queue avearage (scanning) enable */ #define ADC_SEQ_SRQCTL_QAVGVAL_Pos 9 /*!< Queue average value */ /* Bit field masks: */ #define ADC_SEQ_SRQCTL_RQMAX_Msk 0x0000001FUL /*!< Request queue max depth */ #define ADC_SEQ_SRQCTL_QAVGEN_Msk 0x00000100UL /*!< Queue avearage (scanning) enable */ #define ADC_SEQ_SRQCTL_QAVGVAL_Msk 0x00000E00UL /*!< Queue average value */ /* Bit field enums: */ typedef enum { ADC_SEQ_SRQCTL_QAVGVAL_Disable = 0x0UL, /*!< Average disabled */ ADC_SEQ_SRQCTL_QAVGVAL_Average2 = 0x1UL, /*!< Average with 2 measures */ ADC_SEQ_SRQCTL_QAVGVAL_Average4 = 0x2UL, /*!< Average with 4 measures */ ADC_SEQ_SRQCTL_QAVGVAL_Average8 = 0x3UL, /*!< Average with 8 measures */ ADC_SEQ_SRQCTL_QAVGVAL_Average16 = 0x4UL, /*!< Average with 16 measures */ ADC_SEQ_SRQCTL_QAVGVAL_Average32 = 0x5UL, /*!< Average with 32 measures */ ADC_SEQ_SRQCTL_QAVGVAL_Average64 = 0x6UL, /*!< Average with 64 measures */ } ADC_SEQ_SRQCTL_QAVGVAL_Enum; /*-- SEQ: SRQSTAT: Sequencer request status register ----------------------------------------------------------*/ typedef struct { uint32_t RQPTR :5; /*!< Pointer to queue current request */ uint32_t :3; /*!< RESERVED */ uint32_t RQBUSY :1; /*!< Active request status */ } _ADC_SEQ_SRQSTAT_bits; /* Bit field positions: */ #define ADC_SEQ_SRQSTAT_RQPTR_Pos 0 /*!< Pointer to queue current request */ #define ADC_SEQ_SRQSTAT_RQBUSY_Pos 8 /*!< Active request status */ /* Bit field masks: */ #define ADC_SEQ_SRQSTAT_RQPTR_Msk 0x0000001FUL /*!< Pointer to queue current request */ #define ADC_SEQ_SRQSTAT_RQBUSY_Msk 0x00000100UL /*!< Active request status */ /*-- SEQ: SDMACTL: Sequencer DMA control register -------------------------------------------------------------*/ typedef struct { uint32_t DMAEN :1; /*!< Enable DMA use */ uint32_t :7; /*!< RESERVED */ uint32_t WMARK :3; /*!< FIFO load threshold for DMA request generation */ } _ADC_SEQ_SDMACTL_bits; /* Bit field positions: */ #define ADC_SEQ_SDMACTL_DMAEN_Pos 0 /*!< Enable DMA use */ #define ADC_SEQ_SDMACTL_WMARK_Pos 8 /*!< FIFO load threshold for DMA request generation */ /* Bit field masks: */ #define ADC_SEQ_SDMACTL_DMAEN_Msk 0x00000001UL /*!< Enable DMA use */ #define ADC_SEQ_SDMACTL_WMARK_Msk 0x00000700UL /*!< FIFO load threshold for DMA request generation */ /* Bit field enums: */ typedef enum { ADC_SEQ_SDMACTL_WMARK_Level1 = 0x1UL, /*!< 1 measure for dma request */ ADC_SEQ_SDMACTL_WMARK_Level2 = 0x2UL, /*!< 2 measures for dma request */ ADC_SEQ_SDMACTL_WMARK_Level4 = 0x3UL, /*!< 4 measures for dma request */ ADC_SEQ_SDMACTL_WMARK_Level8 = 0x4UL, /*!< 8 measures for dma request */ ADC_SEQ_SDMACTL_WMARK_Level16 = 0x5UL, /*!< 16 measures for dma request */ ADC_SEQ_SDMACTL_WMARK_Level32 = 0x6UL, /*!< 32 measures for dma request */ } ADC_SEQ_SDMACTL_WMARK_Enum; /*-- SEQ: SCCTL: Sequencer ADC interrupt and restart counter control register ---------------------------------*/ typedef struct { uint32_t RCNT :8; /*!< Current number of ADC restarts by sequencer */ uint32_t RAVGEN :1; /*!< Average of ADC restarts enable */ uint32_t :7; /*!< RESERVED */ uint32_t ICNT :8; /*!< Number of ADC restarts for interrupt generation */ } _ADC_SEQ_SCCTL_bits; /* Bit field positions: */ #define ADC_SEQ_SCCTL_RCNT_Pos 0 /*!< Current number of ADC restarts by sequencer */ #define ADC_SEQ_SCCTL_RAVGEN_Pos 8 /*!< Average of ADC restarts enable */ #define ADC_SEQ_SCCTL_ICNT_Pos 16 /*!< Number of ADC restarts for interrupt generation */ /* Bit field masks: */ #define ADC_SEQ_SCCTL_RCNT_Msk 0x000000FFUL /*!< Current number of ADC restarts by sequencer */ #define ADC_SEQ_SCCTL_RAVGEN_Msk 0x00000100UL /*!< Average of ADC restarts enable */ #define ADC_SEQ_SCCTL_ICNT_Msk 0x00FF0000UL /*!< Number of ADC restarts for interrupt generation */ /*-- SEQ: SCVAL: Sequencer ADC interrupt and restart counter current value register --------------------------------*/ typedef struct { uint32_t RCNT :8; /*!< Current number of ADC restarts by sequencer */ uint32_t :8; /*!< RESERVED */ uint32_t ICNT :8; /*!< Current number of ADC restarts for interrupt generation */ uint32_t ICLR :1; /*!< Clear interrupt counter */ } _ADC_SEQ_SCVAL_bits; /* Bit field positions: */ #define ADC_SEQ_SCVAL_RCNT_Pos 0 /*!< Current number of ADC restarts by sequencer */ #define ADC_SEQ_SCVAL_ICNT_Pos 16 /*!< Current number of ADC restarts for interrupt generation */ #define ADC_SEQ_SCVAL_ICLR_Pos 24 /*!< Clear interrupt counter */ /* Bit field masks: */ #define ADC_SEQ_SCVAL_RCNT_Msk 0x000000FFUL /*!< Current number of ADC restarts by sequencer */ #define ADC_SEQ_SCVAL_ICNT_Msk 0x00FF0000UL /*!< Current number of ADC restarts for interrupt generation */ #define ADC_SEQ_SCVAL_ICLR_Msk 0x01000000UL /*!< Clear interrupt counter */ /*-- SEQ: SDC: Sequencer digital comparator selection register ------------------------------------------------*/ typedef struct { uint32_t DC0 :1; /*!< Enable DC 0 */ uint32_t DC1 :1; /*!< Enable DC 1 */ uint32_t DC2 :1; /*!< Enable DC 2 */ uint32_t DC3 :1; /*!< Enable DC 3 */ uint32_t DC4 :1; /*!< Enable DC 4 */ uint32_t DC5 :1; /*!< Enable DC 5 */ uint32_t DC6 :1; /*!< Enable DC 6 */ uint32_t DC7 :1; /*!< Enable DC 7 */ uint32_t DC8 :1; /*!< Enable DC 8 */ uint32_t DC9 :1; /*!< Enable DC 9 */ uint32_t DC10 :1; /*!< Enable DC 10 */ uint32_t DC11 :1; /*!< Enable DC 11 */ uint32_t DC12 :1; /*!< Enable DC 12 */ uint32_t DC13 :1; /*!< Enable DC 13 */ uint32_t DC14 :1; /*!< Enable DC 14 */ uint32_t DC15 :1; /*!< Enable DC 15 */ uint32_t DC16 :1; /*!< Enable DC 16 */ uint32_t DC17 :1; /*!< Enable DC 17 */ uint32_t DC18 :1; /*!< Enable DC 18 */ uint32_t DC19 :1; /*!< Enable DC 19 */ uint32_t DC20 :1; /*!< Enable DC 20 */ uint32_t DC21 :1; /*!< Enable DC 21 */ uint32_t DC22 :1; /*!< Enable DC 22 */ uint32_t DC23 :1; /*!< Enable DC 23 */ } _ADC_SEQ_SDC_bits; /* Bit field positions: */ #define ADC_SEQ_SDC_DC0_Pos 0 /*!< Enable DC 0 */ #define ADC_SEQ_SDC_DC1_Pos 1 /*!< Enable DC 1 */ #define ADC_SEQ_SDC_DC2_Pos 2 /*!< Enable DC 2 */ #define ADC_SEQ_SDC_DC3_Pos 3 /*!< Enable DC 3 */ #define ADC_SEQ_SDC_DC4_Pos 4 /*!< Enable DC 4 */ #define ADC_SEQ_SDC_DC5_Pos 5 /*!< Enable DC 5 */ #define ADC_SEQ_SDC_DC6_Pos 6 /*!< Enable DC 6 */ #define ADC_SEQ_SDC_DC7_Pos 7 /*!< Enable DC 7 */ #define ADC_SEQ_SDC_DC8_Pos 8 /*!< Enable DC 8 */ #define ADC_SEQ_SDC_DC9_Pos 9 /*!< Enable DC 9 */ #define ADC_SEQ_SDC_DC10_Pos 10 /*!< Enable DC 10 */ #define ADC_SEQ_SDC_DC11_Pos 11 /*!< Enable DC 11 */ #define ADC_SEQ_SDC_DC12_Pos 12 /*!< Enable DC 12 */ #define ADC_SEQ_SDC_DC13_Pos 13 /*!< Enable DC 13 */ #define ADC_SEQ_SDC_DC14_Pos 14 /*!< Enable DC 14 */ #define ADC_SEQ_SDC_DC15_Pos 15 /*!< Enable DC 15 */ #define ADC_SEQ_SDC_DC16_Pos 16 /*!< Enable DC 16 */ #define ADC_SEQ_SDC_DC17_Pos 17 /*!< Enable DC 17 */ #define ADC_SEQ_SDC_DC18_Pos 18 /*!< Enable DC 18 */ #define ADC_SEQ_SDC_DC19_Pos 19 /*!< Enable DC 19 */ #define ADC_SEQ_SDC_DC20_Pos 20 /*!< Enable DC 20 */ #define ADC_SEQ_SDC_DC21_Pos 21 /*!< Enable DC 21 */ #define ADC_SEQ_SDC_DC22_Pos 22 /*!< Enable DC 22 */ #define ADC_SEQ_SDC_DC23_Pos 23 /*!< Enable DC 23 */ /* Bit field masks: */ #define ADC_SEQ_SDC_DC0_Msk 0x00000001UL /*!< Enable DC 0 */ #define ADC_SEQ_SDC_DC1_Msk 0x00000002UL /*!< Enable DC 1 */ #define ADC_SEQ_SDC_DC2_Msk 0x00000004UL /*!< Enable DC 2 */ #define ADC_SEQ_SDC_DC3_Msk 0x00000008UL /*!< Enable DC 3 */ #define ADC_SEQ_SDC_DC4_Msk 0x00000010UL /*!< Enable DC 4 */ #define ADC_SEQ_SDC_DC5_Msk 0x00000020UL /*!< Enable DC 5 */ #define ADC_SEQ_SDC_DC6_Msk 0x00000040UL /*!< Enable DC 6 */ #define ADC_SEQ_SDC_DC7_Msk 0x00000080UL /*!< Enable DC 7 */ #define ADC_SEQ_SDC_DC8_Msk 0x00000100UL /*!< Enable DC 8 */ #define ADC_SEQ_SDC_DC9_Msk 0x00000200UL /*!< Enable DC 9 */ #define ADC_SEQ_SDC_DC10_Msk 0x00000400UL /*!< Enable DC 10 */ #define ADC_SEQ_SDC_DC11_Msk 0x00000800UL /*!< Enable DC 11 */ #define ADC_SEQ_SDC_DC12_Msk 0x00001000UL /*!< Enable DC 12 */ #define ADC_SEQ_SDC_DC13_Msk 0x00002000UL /*!< Enable DC 13 */ #define ADC_SEQ_SDC_DC14_Msk 0x00004000UL /*!< Enable DC 14 */ #define ADC_SEQ_SDC_DC15_Msk 0x00008000UL /*!< Enable DC 15 */ #define ADC_SEQ_SDC_DC16_Msk 0x00010000UL /*!< Enable DC 16 */ #define ADC_SEQ_SDC_DC17_Msk 0x00020000UL /*!< Enable DC 17 */ #define ADC_SEQ_SDC_DC18_Msk 0x00040000UL /*!< Enable DC 18 */ #define ADC_SEQ_SDC_DC19_Msk 0x00080000UL /*!< Enable DC 19 */ #define ADC_SEQ_SDC_DC20_Msk 0x00100000UL /*!< Enable DC 20 */ #define ADC_SEQ_SDC_DC21_Msk 0x00200000UL /*!< Enable DC 21 */ #define ADC_SEQ_SDC_DC22_Msk 0x00400000UL /*!< Enable DC 22 */ #define ADC_SEQ_SDC_DC23_Msk 0x00800000UL /*!< Enable DC 23 */ /*-- SEQ: SRTMR: Sequencer ADC restart timer register ---------------------------------------------------------*/ typedef struct { uint32_t VAL :24; /*!< Sequencer ADC restart timer value */ uint32_t :7; /*!< RESERVED */ uint32_t NOWAIT :1; /*!< Timer update with no waiting the end of current seq task */ } _ADC_SEQ_SRTMR_bits; /* Bit field positions: */ #define ADC_SEQ_SRTMR_VAL_Pos 0 /*!< Sequencer ADC restart timer value */ #define ADC_SEQ_SRTMR_NOWAIT_Pos 31 /*!< Timer update with no waiting the end of current seq task */ /* Bit field masks: */ #define ADC_SEQ_SRTMR_VAL_Msk 0x00FFFFFFUL /*!< Sequencer ADC restart timer value */ #define ADC_SEQ_SRTMR_NOWAIT_Msk 0x80000000UL /*!< Timer update with no waiting the end of current seq task */ /*-- SEQ: SFLOAD: Sequencer FIFO load status register ---------------------------------------------------------*/ typedef struct { uint32_t VAL :6; /*!< Sequencer FIFO current load value */ } _ADC_SEQ_SFLOAD_bits; /* Bit field positions: */ #define ADC_SEQ_SFLOAD_VAL_Pos 0 /*!< Sequencer FIFO current load value */ /* Bit field masks: */ #define ADC_SEQ_SFLOAD_VAL_Msk 0x0000003FUL /*!< Sequencer FIFO current load value */ /*-- SEQ: SFIFO: Sequencer FIFO register ----------------------------------------------------------------------*/ typedef struct { uint32_t DATA :12; /*!< AD conversion value */ } _ADC_SEQ_SFIFO_bits; /* Bit field positions: */ #define ADC_SEQ_SFIFO_DATA_Pos 0 /*!< AD conversion value */ /* Bit field masks: */ #define ADC_SEQ_SFIFO_DATA_Msk 0x00000FFFUL /*!< AD conversion value */ /*-- DC: DCTL: Digital comparator control register ------------------------------------------------------------*/ typedef struct { uint32_t CIM :2; /*!< DC interrupt generation mode */ uint32_t CIC :2; /*!< DC interrupt generation compare conditions */ uint32_t CIE :1; /*!< Enable DC interrupt generation */ uint32_t :3; /*!< RESERVED */ uint32_t CTM :2; /*!< DC output trigger mode */ uint32_t CTC :2; /*!< DC output trigger compare conditions */ uint32_t CTE :1; /*!< Enable DC output trigger */ uint32_t :3; /*!< RESERVED */ uint32_t CHNL :6; /*!< ADC channel selection */ uint32_t :2; /*!< RESERVED */ uint32_t SRC :1; /*!< Select data source for comparation: ADC module (0) or sequencer(1) */ uint32_t :3; /*!< RESERVED */ uint32_t HWTCLR :1; /*!< Hardware output trigger clear */ } _ADC_DC_DCTL_bits; /* Bit field positions: */ #define ADC_DC_DCTL_CIM_Pos 0 /*!< DC interrupt generation mode */ #define ADC_DC_DCTL_CIC_Pos 2 /*!< DC interrupt generation compare conditions */ #define ADC_DC_DCTL_CIE_Pos 4 /*!< Enable DC interrupt generation */ #define ADC_DC_DCTL_CTM_Pos 8 /*!< DC output trigger mode */ #define ADC_DC_DCTL_CTC_Pos 10 /*!< DC output trigger compare conditions */ #define ADC_DC_DCTL_CTE_Pos 12 /*!< Enable DC output trigger */ #define ADC_DC_DCTL_CHNL_Pos 16 /*!< ADC channel selection */ #define ADC_DC_DCTL_SRC_Pos 24 /*!< Select data source for comparation: ADC module (0) or sequencer(1) */ #define ADC_DC_DCTL_HWTCLR_Pos 28 /*!< Hardware output trigger clear */ /* Bit field masks: */ #define ADC_DC_DCTL_CIM_Msk 0x00000003UL /*!< DC interrupt generation mode */ #define ADC_DC_DCTL_CIC_Msk 0x0000000CUL /*!< DC interrupt generation compare conditions */ #define ADC_DC_DCTL_CIE_Msk 0x00000010UL /*!< Enable DC interrupt generation */ #define ADC_DC_DCTL_CTM_Msk 0x00000300UL /*!< DC output trigger mode */ #define ADC_DC_DCTL_CTC_Msk 0x00000C00UL /*!< DC output trigger compare conditions */ #define ADC_DC_DCTL_CTE_Msk 0x00001000UL /*!< Enable DC output trigger */ #define ADC_DC_DCTL_CHNL_Msk 0x003F0000UL /*!< ADC channel selection */ #define ADC_DC_DCTL_SRC_Msk 0x01000000UL /*!< Select data source for comparation: ADC module (0) or sequencer(1) */ #define ADC_DC_DCTL_HWTCLR_Msk 0x10000000UL /*!< Hardware output trigger clear */ /* Bit field enums: */ typedef enum { ADC_DC_DCTL_CIM_Multiple = 0x0UL, /*!< multiple trigger mode */ ADC_DC_DCTL_CIM_Single = 0x1UL, /*!< single trigger mode */ ADC_DC_DCTL_CIM_MultipleHyst = 0x2UL, /*!< multiple trigger mode with hysteresis */ ADC_DC_DCTL_CIM_SingleHyst = 0x3UL, /*!< single trigger mode with hysteresis */ } ADC_DC_DCTL_CIM_Enum; typedef enum { ADC_DC_DCTL_CIC_Low = 0x0UL, /*!< result lower or equal COMP0 */ ADC_DC_DCTL_CIC_Window = 0x1UL, /*!< result between COMP0 and COMP1 or equal any of them */ ADC_DC_DCTL_CIC_High = 0x2UL, /*!< result higher or equal COMP1 */ } ADC_DC_DCTL_CIC_Enum; typedef enum { ADC_DC_DCTL_CTM_Multiple = 0x0UL, /*!< multiple trigger mode */ ADC_DC_DCTL_CTM_Single = 0x1UL, /*!< single trigger mode */ ADC_DC_DCTL_CTM_MultipleHyst = 0x2UL, /*!< multiple trigger mode with hysteresis */ ADC_DC_DCTL_CTM_SingleHyst = 0x3UL, /*!< single trigger mode with hysteresis */ } ADC_DC_DCTL_CTM_Enum; typedef enum { ADC_DC_DCTL_CTC_Low = 0x0UL, /*!< result lower or equal COMP0 */ ADC_DC_DCTL_CTC_Window = 0x1UL, /*!< result between COMP0 and COMP1 or equal any of them */ ADC_DC_DCTL_CTC_High = 0x2UL, /*!< result higher or equal COMP1 */ } ADC_DC_DCTL_CTC_Enum; /*-- DC: DCMP: Digital comparator range register --------------------------------------------------------------*/ typedef struct { uint32_t CMPL :12; /*!< Low threshold compare value */ uint32_t :4; /*!< RESERVED */ uint32_t CMPH :12; /*!< High threshold compare value */ } _ADC_DC_DCMP_bits; /* Bit field positions: */ #define ADC_DC_DCMP_CMPL_Pos 0 /*!< Low threshold compare value */ #define ADC_DC_DCMP_CMPH_Pos 16 /*!< High threshold compare value */ /* Bit field masks: */ #define ADC_DC_DCMP_CMPL_Msk 0x00000FFFUL /*!< Low threshold compare value */ #define ADC_DC_DCMP_CMPH_Msk 0x0FFF0000UL /*!< High threshold compare value */ /*-- DC: DDATA: Digital comparator last compared data register ------------------------------------------------*/ typedef struct { uint32_t VAL :12; /*!< Value of last compared AD conversion result */ } _ADC_DC_DDATA_bits; /* Bit field positions: */ #define ADC_DC_DDATA_VAL_Pos 0 /*!< Value of last compared AD conversion result */ /* Bit field masks: */ #define ADC_DC_DDATA_VAL_Msk 0x00000FFFUL /*!< Value of last compared AD conversion result */ /*-- ACTL: ACTL: ADC module control register ------------------------------------------------------------------*/ typedef struct { uint32_t ADCEN :1; /*!< Enable ADC module */ uint32_t ADCRDY :1; /*!< ADC ready for conversions */ uint32_t :2; /*!< RESERVED */ uint32_t SELRES :2; /*!< ADC resolution select */ uint32_t :2; /*!< RESERVED */ uint32_t CALEN :1; /*!< */ uint32_t CALLOAD :1; /*!< */ uint32_t CALSTART :1; /*!< */ uint32_t CALBUSY :1; /*!< Enable ADC internal calibration */ uint32_t :4; /*!< RESERVED */ uint32_t CALIN :7; /*!< ADC calibration input value */ uint32_t :1; /*!< RESERVED */ uint32_t CALOUT :7; /*!< ADC calibration output value */ } _ADC_ACTL_ACTL_bits; /* Bit field positions: */ #define ADC_ACTL_ACTL_ADCEN_Pos 0 /*!< Enable ADC module */ #define ADC_ACTL_ACTL_ADCRDY_Pos 1 /*!< ADC ready for conversions */ #define ADC_ACTL_ACTL_SELRES_Pos 4 /*!< ADC resolution select */ #define ADC_ACTL_ACTL_CALEN_Pos 8 /*!< */ #define ADC_ACTL_ACTL_CALLOAD_Pos 9 /*!< */ #define ADC_ACTL_ACTL_CALSTART_Pos 10 /*!< */ #define ADC_ACTL_ACTL_CALBUSY_Pos 11 /*!< Enable ADC internal calibration */ #define ADC_ACTL_ACTL_CALIN_Pos 16 /*!< ADC calibration input value */ #define ADC_ACTL_ACTL_CALOUT_Pos 24 /*!< ADC calibration output value */ /* Bit field masks: */ #define ADC_ACTL_ACTL_ADCEN_Msk 0x00000001UL /*!< Enable ADC module */ #define ADC_ACTL_ACTL_ADCRDY_Msk 0x00000002UL /*!< ADC ready for conversions */ #define ADC_ACTL_ACTL_SELRES_Msk 0x00000030UL /*!< ADC resolution select */ #define ADC_ACTL_ACTL_CALEN_Msk 0x00000100UL /*!< */ #define ADC_ACTL_ACTL_CALLOAD_Msk 0x00000200UL /*!< */ #define ADC_ACTL_ACTL_CALSTART_Msk 0x00000400UL /*!< */ #define ADC_ACTL_ACTL_CALBUSY_Msk 0x00000800UL /*!< Enable ADC internal calibration */ #define ADC_ACTL_ACTL_CALIN_Msk 0x007F0000UL /*!< ADC calibration input value */ #define ADC_ACTL_ACTL_CALOUT_Msk 0x7F000000UL /*!< ADC calibration output value */ /* Bit field enums: */ typedef enum { ADC_ACTL_ACTL_SELRES_6bit = 0x0UL, /*!< 6 bit mode */ ADC_ACTL_ACTL_SELRES_8bit = 0x1UL, /*!< 8 bit mode */ ADC_ACTL_ACTL_SELRES_10bit = 0x2UL, /*!< 10 bit mode */ ADC_ACTL_ACTL_SELRES_12bit = 0x3UL, /*!< 12 bit mode */ } ADC_ACTL_ACTL_SELRES_Enum; /*-- CHCTL: CHCTL: ADC channel control register ---------------------------------------------------------------*/ typedef struct { uint32_t OFFTRIM :9; /*!< ADC channel offset trimm value */ uint32_t :7; /*!< RESERVED */ uint32_t GAINTRIM :9; /*!< ADC channel gain trimm value */ uint32_t :3; /*!< RESERVED */ uint32_t PRIORITY :1; /*!< ADC channel priority level */ } _ADC_CHCTL_CHCTL_bits; /* Bit field positions: */ #define ADC_CHCTL_CHCTL_OFFTRIM_Pos 0 /*!< ADC channel offset trimm value */ #define ADC_CHCTL_CHCTL_GAINTRIM_Pos 16 /*!< ADC channel gain trimm value */ #define ADC_CHCTL_CHCTL_PRIORITY_Pos 28 /*!< ADC channel priority level */ /* Bit field masks: */ #define ADC_CHCTL_CHCTL_OFFTRIM_Msk 0x000001FFUL /*!< ADC channel offset trimm value */ #define ADC_CHCTL_CHCTL_GAINTRIM_Msk 0x01FF0000UL /*!< ADC channel gain trimm value */ #define ADC_CHCTL_CHCTL_PRIORITY_Msk 0x10000000UL /*!< ADC channel priority level */ //Cluster SEQ: typedef struct { union { /*!< Sequencer request ADC channels selection register 0 */ __IO uint32_t SRQSEL0; /*!< SRQSEL0 : type used for word access */ __IO _ADC_SEQ_SRQSEL0_bits SRQSEL0_bit; /*!< SRQSEL0_bit: structure used for bit access */ }; union { /*!< Sequencer request ADC channels selection register 1 */ __IO uint32_t SRQSEL1; /*!< SRQSEL1 : type used for word access */ __IO _ADC_SEQ_SRQSEL1_bits SRQSEL1_bit; /*!< SRQSEL1_bit: structure used for bit access */ }; union { /*!< Sequencer request ADC channels selection register 2 */ __IO uint32_t SRQSEL2; /*!< SRQSEL2 : type used for word access */ __IO _ADC_SEQ_SRQSEL2_bits SRQSEL2_bit; /*!< SRQSEL2_bit: structure used for bit access */ }; union { /*!< Sequencer request ADC channels selection register 3 */ __IO uint32_t SRQSEL3; /*!< SRQSEL3 : type used for word access */ __IO _ADC_SEQ_SRQSEL3_bits SRQSEL3_bit; /*!< SRQSEL3_bit: structure used for bit access */ }; union { /*!< Sequencer request ADC channels selection register 4 */ __IO uint32_t SRQSEL4; /*!< SRQSEL4 : type used for word access */ __IO _ADC_SEQ_SRQSEL4_bits SRQSEL4_bit; /*!< SRQSEL4_bit: structure used for bit access */ }; union { /*!< Sequencer request ADC channels selection register 5 */ __IO uint32_t SRQSEL5; /*!< SRQSEL5 : type used for word access */ __IO _ADC_SEQ_SRQSEL5_bits SRQSEL5_bit; /*!< SRQSEL5_bit: structure used for bit access */ }; union { /*!< Sequencer request control register */ __IO uint32_t SRQCTL; /*!< SRQCTL : type used for word access */ __IO _ADC_SEQ_SRQCTL_bits SRQCTL_bit; /*!< SRQCTL_bit: structure used for bit access */ }; union { /*!< Sequencer request status register */ __IO uint32_t SRQSTAT; /*!< SRQSTAT : type used for word access */ __IO _ADC_SEQ_SRQSTAT_bits SRQSTAT_bit; /*!< SRQSTAT_bit: structure used for bit access */ }; union { /*!< Sequencer DMA control register */ __IO uint32_t SDMACTL; /*!< SDMACTL : type used for word access */ __IO _ADC_SEQ_SDMACTL_bits SDMACTL_bit; /*!< SDMACTL_bit: structure used for bit access */ }; union { /*!< Sequencer ADC interrupt and restart counter control register */ __IO uint32_t SCCTL; /*!< SCCTL : type used for word access */ __IO _ADC_SEQ_SCCTL_bits SCCTL_bit; /*!< SCCTL_bit: structure used for bit access */ }; union { /*!< Sequencer ADC interrupt and restart counter current value register */ __O uint32_t SCVAL; /*!< SCVAL : type used for word access */ __O _ADC_SEQ_SCVAL_bits SCVAL_bit; /*!< SCVAL_bit: structure used for bit access */ }; union { /*!< Sequencer digital comparator selection register */ __IO uint32_t SDC; /*!< SDC : type used for word access */ __IO _ADC_SEQ_SDC_bits SDC_bit; /*!< SDC_bit: structure used for bit access */ }; union { /*!< Sequencer ADC restart timer register */ __IO uint32_t SRTMR; /*!< SRTMR : type used for word access */ __IO _ADC_SEQ_SRTMR_bits SRTMR_bit; /*!< SRTMR_bit: structure used for bit access */ }; union { /*!< Sequencer FIFO load status register */ __I uint32_t SFLOAD; /*!< SFLOAD : type used for word access */ __I _ADC_SEQ_SFLOAD_bits SFLOAD_bit; /*!< SFLOAD_bit: structure used for bit access */ }; union { /*!< Sequencer FIFO register */ __I uint32_t SFIFO; /*!< SFIFO : type used for word access */ __I _ADC_SEQ_SFIFO_bits SFIFO_bit; /*!< SFIFO_bit: structure used for bit access */ }; } _ADC_SEQ_TypeDef; //Cluster DC: typedef struct { union { /*!< Digital comparator control register */ __IO uint32_t DCTL; /*!< DCTL : type used for word access */ __IO _ADC_DC_DCTL_bits DCTL_bit; /*!< DCTL_bit: structure used for bit access */ }; union { /*!< Digital comparator range register */ __IO uint32_t DCMP; /*!< DCMP : type used for word access */ __IO _ADC_DC_DCMP_bits DCMP_bit; /*!< DCMP_bit: structure used for bit access */ }; union { /*!< Digital comparator last compared data register */ __I uint32_t DDATA; /*!< DDATA : type used for word access */ __I _ADC_DC_DDATA_bits DDATA_bit; /*!< DDATA_bit: structure used for bit access */ }; } _ADC_DC_TypeDef; //Cluster ACTL: typedef struct { union { /*!< ADC module control register */ __IO uint32_t ACTL; /*!< ACTL : type used for word access */ __IO _ADC_ACTL_ACTL_bits ACTL_bit; /*!< ACTL_bit: structure used for bit access */ }; } _ADC_ACTL_TypeDef; //Cluster CHCTL: typedef struct { union { /*!< ADC channel control register */ __IO uint32_t CHCTL; /*!< CHCTL : type used for word access */ __IO _ADC_CHCTL_CHCTL_bits CHCTL_bit; /*!< CHCTL_bit: structure used for bit access */ }; } _ADC_CHCTL_TypeDef; typedef struct { union { /*!< Enable sequencer register */ __IO uint32_t SEQEN; /*!< SEQEN : type used for word access */ __IO _ADC_SEQEN_bits SEQEN_bit; /*!< SEQEN_bit: structure used for bit access */ }; union { /*!< Sequencer sync register */ __IO uint32_t SEQSYNC; /*!< SEQSYNC : type used for word access */ __IO _ADC_SEQSYNC_bits SEQSYNC_bit; /*!< SEQSYNC_bit: structure used for bit access */ }; union { /*!< FIFO overflow status register */ __IO uint32_t FSTAT; /*!< FSTAT : type used for word access */ __IO _ADC_FSTAT_bits FSTAT_bit; /*!< FSTAT_bit: structure used for bit access */ }; union { /*!< Busy status register */ __I uint32_t BSTAT; /*!< BSTAT : type used for word access */ __I _ADC_BSTAT_bits BSTAT_bit; /*!< BSTAT_bit: structure used for bit access */ }; union { /*!< Digital comparator output trigger status register */ __O uint32_t DCTRIG; /*!< DCTRIG : type used for word access */ __O _ADC_DCTRIG_bits DCTRIG_bit; /*!< DCTRIG_bit: structure used for bit access */ }; union { /*!< Digital comparator compare event status register */ __O uint32_t DCEV; /*!< DCEV : type used for word access */ __O _ADC_DCEV_bits DCEV_bit; /*!< DCEV_bit: structure used for bit access */ }; union { /*!< Interrupt counter clear control */ __IO uint32_t CICNT; /*!< CICNT : type used for word access */ __IO _ADC_CICNT_bits CICNT_bit; /*!< CICNT_bit: structure used for bit access */ }; union { /*!< Sequencer start event selection register */ __IO uint32_t EMUX; /*!< EMUX : type used for word access */ __IO _ADC_EMUX_bits EMUX_bit; /*!< EMUX_bit: structure used for bit access */ }; union { /*!< Raw interrupt status register */ __I uint32_t RIS; /*!< RIS : type used for word access */ __I _ADC_RIS_bits RIS_bit; /*!< RIS_bit: structure used for bit access */ }; union { /*!< Interrupt mask register */ __IO uint32_t IM; /*!< IM : type used for word access */ __IO _ADC_IM_bits IM_bit; /*!< IM_bit: structure used for bit access */ }; union { /*!< Masked interrupt status and clear register */ __I uint32_t MIS; /*!< MIS : type used for word access */ __I _ADC_MIS_bits MIS_bit; /*!< MIS_bit: structure used for bit access */ }; union { /*!< Interrupt clear register */ __O uint32_t IC; /*!< IC : type used for word access */ __O _ADC_IC_bits IC_bit; /*!< IC_bit: structure used for bit access */ }; __IO uint32_t Reserved0[4]; _ADC_SEQ_TypeDef SEQ[8]; __IO uint32_t Reserved1[120]; _ADC_DC_TypeDef DC[24]; __IO uint32_t Reserved2[8]; _ADC_ACTL_TypeDef ACTL[4]; __IO uint32_t Reserved3[12]; _ADC_CHCTL_TypeDef CHCTL[48]; } ADC_TypeDef; /******************************************************************************/ /* GPIO registers */ /******************************************************************************/ /*-- DATA: Data Input register -------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :16; /*!< Data input */ } _GPIO_DATA_bits; /* Bit field positions: */ #define GPIO_DATA_VAL_Pos 0 /*!< Data input */ /* Bit field masks: */ #define GPIO_DATA_VAL_Msk 0x0000FFFFUL /*!< Data input */ /*-- DATAOUT: Data output register ---------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :16; /*!< Data output */ } _GPIO_DATAOUT_bits; /* Bit field positions: */ #define GPIO_DATAOUT_VAL_Pos 0 /*!< Data output */ /* Bit field masks: */ #define GPIO_DATAOUT_VAL_Msk 0x0000FFFFUL /*!< Data output */ /*-- DATAOUTSET: Data output set bits register ---------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Data output set bit 0 */ uint32_t PIN1 :1; /*!< Data output set bit 1 */ uint32_t PIN2 :1; /*!< Data output set bit 2 */ uint32_t PIN3 :1; /*!< Data output set bit 3 */ uint32_t PIN4 :1; /*!< Data output set bit 4 */ uint32_t PIN5 :1; /*!< Data output set bit 5 */ uint32_t PIN6 :1; /*!< Data output set bit 6 */ uint32_t PIN7 :1; /*!< Data output set bit 7 */ uint32_t PIN8 :1; /*!< Data output set bit 8 */ uint32_t PIN9 :1; /*!< Data output set bit 9 */ uint32_t PIN10 :1; /*!< Data output set bit 10 */ uint32_t PIN11 :1; /*!< Data output set bit 11 */ uint32_t PIN12 :1; /*!< Data output set bit 12 */ uint32_t PIN13 :1; /*!< Data output set bit 13 */ uint32_t PIN14 :1; /*!< Data output set bit 14 */ uint32_t PIN15 :1; /*!< Data output set bit 15 */ } _GPIO_DATAOUTSET_bits; /* Bit field positions: */ #define GPIO_DATAOUTSET_PIN0_Pos 0 /*!< Data output set bit 0 */ #define GPIO_DATAOUTSET_PIN1_Pos 1 /*!< Data output set bit 1 */ #define GPIO_DATAOUTSET_PIN2_Pos 2 /*!< Data output set bit 2 */ #define GPIO_DATAOUTSET_PIN3_Pos 3 /*!< Data output set bit 3 */ #define GPIO_DATAOUTSET_PIN4_Pos 4 /*!< Data output set bit 4 */ #define GPIO_DATAOUTSET_PIN5_Pos 5 /*!< Data output set bit 5 */ #define GPIO_DATAOUTSET_PIN6_Pos 6 /*!< Data output set bit 6 */ #define GPIO_DATAOUTSET_PIN7_Pos 7 /*!< Data output set bit 7 */ #define GPIO_DATAOUTSET_PIN8_Pos 8 /*!< Data output set bit 8 */ #define GPIO_DATAOUTSET_PIN9_Pos 9 /*!< Data output set bit 9 */ #define GPIO_DATAOUTSET_PIN10_Pos 10 /*!< Data output set bit 10 */ #define GPIO_DATAOUTSET_PIN11_Pos 11 /*!< Data output set bit 11 */ #define GPIO_DATAOUTSET_PIN12_Pos 12 /*!< Data output set bit 12 */ #define GPIO_DATAOUTSET_PIN13_Pos 13 /*!< Data output set bit 13 */ #define GPIO_DATAOUTSET_PIN14_Pos 14 /*!< Data output set bit 14 */ #define GPIO_DATAOUTSET_PIN15_Pos 15 /*!< Data output set bit 15 */ /* Bit field masks: */ #define GPIO_DATAOUTSET_PIN0_Msk 0x00000001UL /*!< Data output set bit 0 */ #define GPIO_DATAOUTSET_PIN1_Msk 0x00000002UL /*!< Data output set bit 1 */ #define GPIO_DATAOUTSET_PIN2_Msk 0x00000004UL /*!< Data output set bit 2 */ #define GPIO_DATAOUTSET_PIN3_Msk 0x00000008UL /*!< Data output set bit 3 */ #define GPIO_DATAOUTSET_PIN4_Msk 0x00000010UL /*!< Data output set bit 4 */ #define GPIO_DATAOUTSET_PIN5_Msk 0x00000020UL /*!< Data output set bit 5 */ #define GPIO_DATAOUTSET_PIN6_Msk 0x00000040UL /*!< Data output set bit 6 */ #define GPIO_DATAOUTSET_PIN7_Msk 0x00000080UL /*!< Data output set bit 7 */ #define GPIO_DATAOUTSET_PIN8_Msk 0x00000100UL /*!< Data output set bit 8 */ #define GPIO_DATAOUTSET_PIN9_Msk 0x00000200UL /*!< Data output set bit 9 */ #define GPIO_DATAOUTSET_PIN10_Msk 0x00000400UL /*!< Data output set bit 10 */ #define GPIO_DATAOUTSET_PIN11_Msk 0x00000800UL /*!< Data output set bit 11 */ #define GPIO_DATAOUTSET_PIN12_Msk 0x00001000UL /*!< Data output set bit 12 */ #define GPIO_DATAOUTSET_PIN13_Msk 0x00002000UL /*!< Data output set bit 13 */ #define GPIO_DATAOUTSET_PIN14_Msk 0x00004000UL /*!< Data output set bit 14 */ #define GPIO_DATAOUTSET_PIN15_Msk 0x00008000UL /*!< Data output set bit 15 */ /*-- DATAOUTCLR: Data output clear bits register -------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Data output clear bit 0 */ uint32_t PIN1 :1; /*!< Data output clear bit 1 */ uint32_t PIN2 :1; /*!< Data output clear bit 2 */ uint32_t PIN3 :1; /*!< Data output clear bit 3 */ uint32_t PIN4 :1; /*!< Data output clear bit 4 */ uint32_t PIN5 :1; /*!< Data output clear bit 5 */ uint32_t PIN6 :1; /*!< Data output clear bit 6 */ uint32_t PIN7 :1; /*!< Data output clear bit 7 */ uint32_t PIN8 :1; /*!< Data output clear bit 8 */ uint32_t PIN9 :1; /*!< Data output clear bit 9 */ uint32_t PIN10 :1; /*!< Data output clear bit 10 */ uint32_t PIN11 :1; /*!< Data output clear bit 11 */ uint32_t PIN12 :1; /*!< Data output clear bit 12 */ uint32_t PIN13 :1; /*!< Data output clear bit 13 */ uint32_t PIN14 :1; /*!< Data output clear bit 14 */ uint32_t PIN15 :1; /*!< Data output clear bit 15 */ } _GPIO_DATAOUTCLR_bits; /* Bit field positions: */ #define GPIO_DATAOUTCLR_PIN0_Pos 0 /*!< Data output clear bit 0 */ #define GPIO_DATAOUTCLR_PIN1_Pos 1 /*!< Data output clear bit 1 */ #define GPIO_DATAOUTCLR_PIN2_Pos 2 /*!< Data output clear bit 2 */ #define GPIO_DATAOUTCLR_PIN3_Pos 3 /*!< Data output clear bit 3 */ #define GPIO_DATAOUTCLR_PIN4_Pos 4 /*!< Data output clear bit 4 */ #define GPIO_DATAOUTCLR_PIN5_Pos 5 /*!< Data output clear bit 5 */ #define GPIO_DATAOUTCLR_PIN6_Pos 6 /*!< Data output clear bit 6 */ #define GPIO_DATAOUTCLR_PIN7_Pos 7 /*!< Data output clear bit 7 */ #define GPIO_DATAOUTCLR_PIN8_Pos 8 /*!< Data output clear bit 8 */ #define GPIO_DATAOUTCLR_PIN9_Pos 9 /*!< Data output clear bit 9 */ #define GPIO_DATAOUTCLR_PIN10_Pos 10 /*!< Data output clear bit 10 */ #define GPIO_DATAOUTCLR_PIN11_Pos 11 /*!< Data output clear bit 11 */ #define GPIO_DATAOUTCLR_PIN12_Pos 12 /*!< Data output clear bit 12 */ #define GPIO_DATAOUTCLR_PIN13_Pos 13 /*!< Data output clear bit 13 */ #define GPIO_DATAOUTCLR_PIN14_Pos 14 /*!< Data output clear bit 14 */ #define GPIO_DATAOUTCLR_PIN15_Pos 15 /*!< Data output clear bit 15 */ /* Bit field masks: */ #define GPIO_DATAOUTCLR_PIN0_Msk 0x00000001UL /*!< Data output clear bit 0 */ #define GPIO_DATAOUTCLR_PIN1_Msk 0x00000002UL /*!< Data output clear bit 1 */ #define GPIO_DATAOUTCLR_PIN2_Msk 0x00000004UL /*!< Data output clear bit 2 */ #define GPIO_DATAOUTCLR_PIN3_Msk 0x00000008UL /*!< Data output clear bit 3 */ #define GPIO_DATAOUTCLR_PIN4_Msk 0x00000010UL /*!< Data output clear bit 4 */ #define GPIO_DATAOUTCLR_PIN5_Msk 0x00000020UL /*!< Data output clear bit 5 */ #define GPIO_DATAOUTCLR_PIN6_Msk 0x00000040UL /*!< Data output clear bit 6 */ #define GPIO_DATAOUTCLR_PIN7_Msk 0x00000080UL /*!< Data output clear bit 7 */ #define GPIO_DATAOUTCLR_PIN8_Msk 0x00000100UL /*!< Data output clear bit 8 */ #define GPIO_DATAOUTCLR_PIN9_Msk 0x00000200UL /*!< Data output clear bit 9 */ #define GPIO_DATAOUTCLR_PIN10_Msk 0x00000400UL /*!< Data output clear bit 10 */ #define GPIO_DATAOUTCLR_PIN11_Msk 0x00000800UL /*!< Data output clear bit 11 */ #define GPIO_DATAOUTCLR_PIN12_Msk 0x00001000UL /*!< Data output clear bit 12 */ #define GPIO_DATAOUTCLR_PIN13_Msk 0x00002000UL /*!< Data output clear bit 13 */ #define GPIO_DATAOUTCLR_PIN14_Msk 0x00004000UL /*!< Data output clear bit 14 */ #define GPIO_DATAOUTCLR_PIN15_Msk 0x00008000UL /*!< Data output clear bit 15 */ /*-- DATAOUTTGL: Data output toogle bits register ------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Data output toogle bit 0 */ uint32_t PIN1 :1; /*!< Data output toogle bit 1 */ uint32_t PIN2 :1; /*!< Data output toogle bit 2 */ uint32_t PIN3 :1; /*!< Data output toogle bit 3 */ uint32_t PIN4 :1; /*!< Data output toogle bit 4 */ uint32_t PIN5 :1; /*!< Data output toogle bit 5 */ uint32_t PIN6 :1; /*!< Data output toogle bit 6 */ uint32_t PIN7 :1; /*!< Data output toogle bit 7 */ uint32_t PIN8 :1; /*!< Data output toogle bit 8 */ uint32_t PIN9 :1; /*!< Data output toogle bit 9 */ uint32_t PIN10 :1; /*!< Data output toogle bit 10 */ uint32_t PIN11 :1; /*!< Data output toogle bit 11 */ uint32_t PIN12 :1; /*!< Data output toogle bit 12 */ uint32_t PIN13 :1; /*!< Data output toogle bit 13 */ uint32_t PIN14 :1; /*!< Data output toogle bit 14 */ uint32_t PIN15 :1; /*!< Data output toogle bit 15 */ } _GPIO_DATAOUTTGL_bits; /* Bit field positions: */ #define GPIO_DATAOUTTGL_PIN0_Pos 0 /*!< Data output toogle bit 0 */ #define GPIO_DATAOUTTGL_PIN1_Pos 1 /*!< Data output toogle bit 1 */ #define GPIO_DATAOUTTGL_PIN2_Pos 2 /*!< Data output toogle bit 2 */ #define GPIO_DATAOUTTGL_PIN3_Pos 3 /*!< Data output toogle bit 3 */ #define GPIO_DATAOUTTGL_PIN4_Pos 4 /*!< Data output toogle bit 4 */ #define GPIO_DATAOUTTGL_PIN5_Pos 5 /*!< Data output toogle bit 5 */ #define GPIO_DATAOUTTGL_PIN6_Pos 6 /*!< Data output toogle bit 6 */ #define GPIO_DATAOUTTGL_PIN7_Pos 7 /*!< Data output toogle bit 7 */ #define GPIO_DATAOUTTGL_PIN8_Pos 8 /*!< Data output toogle bit 8 */ #define GPIO_DATAOUTTGL_PIN9_Pos 9 /*!< Data output toogle bit 9 */ #define GPIO_DATAOUTTGL_PIN10_Pos 10 /*!< Data output toogle bit 10 */ #define GPIO_DATAOUTTGL_PIN11_Pos 11 /*!< Data output toogle bit 11 */ #define GPIO_DATAOUTTGL_PIN12_Pos 12 /*!< Data output toogle bit 12 */ #define GPIO_DATAOUTTGL_PIN13_Pos 13 /*!< Data output toogle bit 13 */ #define GPIO_DATAOUTTGL_PIN14_Pos 14 /*!< Data output toogle bit 14 */ #define GPIO_DATAOUTTGL_PIN15_Pos 15 /*!< Data output toogle bit 15 */ /* Bit field masks: */ #define GPIO_DATAOUTTGL_PIN0_Msk 0x00000001UL /*!< Data output toogle bit 0 */ #define GPIO_DATAOUTTGL_PIN1_Msk 0x00000002UL /*!< Data output toogle bit 1 */ #define GPIO_DATAOUTTGL_PIN2_Msk 0x00000004UL /*!< Data output toogle bit 2 */ #define GPIO_DATAOUTTGL_PIN3_Msk 0x00000008UL /*!< Data output toogle bit 3 */ #define GPIO_DATAOUTTGL_PIN4_Msk 0x00000010UL /*!< Data output toogle bit 4 */ #define GPIO_DATAOUTTGL_PIN5_Msk 0x00000020UL /*!< Data output toogle bit 5 */ #define GPIO_DATAOUTTGL_PIN6_Msk 0x00000040UL /*!< Data output toogle bit 6 */ #define GPIO_DATAOUTTGL_PIN7_Msk 0x00000080UL /*!< Data output toogle bit 7 */ #define GPIO_DATAOUTTGL_PIN8_Msk 0x00000100UL /*!< Data output toogle bit 8 */ #define GPIO_DATAOUTTGL_PIN9_Msk 0x00000200UL /*!< Data output toogle bit 9 */ #define GPIO_DATAOUTTGL_PIN10_Msk 0x00000400UL /*!< Data output toogle bit 10 */ #define GPIO_DATAOUTTGL_PIN11_Msk 0x00000800UL /*!< Data output toogle bit 11 */ #define GPIO_DATAOUTTGL_PIN12_Msk 0x00001000UL /*!< Data output toogle bit 12 */ #define GPIO_DATAOUTTGL_PIN13_Msk 0x00002000UL /*!< Data output toogle bit 13 */ #define GPIO_DATAOUTTGL_PIN14_Msk 0x00004000UL /*!< Data output toogle bit 14 */ #define GPIO_DATAOUTTGL_PIN15_Msk 0x00008000UL /*!< Data output toogle bit 15 */ /*-- DENSET: Digital function (PAD) enable register ----------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Digital function (PAD) enable on pin 0 */ uint32_t PIN1 :1; /*!< Digital function (PAD) enable on pin 1 */ uint32_t PIN2 :1; /*!< Digital function (PAD) enable on pin 2 */ uint32_t PIN3 :1; /*!< Digital function (PAD) enable on pin 3 */ uint32_t PIN4 :1; /*!< Digital function (PAD) enable on pin 4 */ uint32_t PIN5 :1; /*!< Digital function (PAD) enable on pin 5 */ uint32_t PIN6 :1; /*!< Digital function (PAD) enable on pin 6 */ uint32_t PIN7 :1; /*!< Digital function (PAD) enable on pin 7 */ uint32_t PIN8 :1; /*!< Digital function (PAD) enable on pin 8 */ uint32_t PIN9 :1; /*!< Digital function (PAD) enable on pin 9 */ uint32_t PIN10 :1; /*!< Digital function (PAD) enable on pin 10 */ uint32_t PIN11 :1; /*!< Digital function (PAD) enable on pin 11 */ uint32_t PIN12 :1; /*!< Digital function (PAD) enable on pin 12 */ uint32_t PIN13 :1; /*!< Digital function (PAD) enable on pin 13 */ uint32_t PIN14 :1; /*!< Digital function (PAD) enable on pin 14 */ uint32_t PIN15 :1; /*!< Digital function (PAD) enable on pin 15 */ } _GPIO_DENSET_bits; /* Bit field positions: */ #define GPIO_DENSET_PIN0_Pos 0 /*!< Digital function (PAD) enable on pin 0 */ #define GPIO_DENSET_PIN1_Pos 1 /*!< Digital function (PAD) enable on pin 1 */ #define GPIO_DENSET_PIN2_Pos 2 /*!< Digital function (PAD) enable on pin 2 */ #define GPIO_DENSET_PIN3_Pos 3 /*!< Digital function (PAD) enable on pin 3 */ #define GPIO_DENSET_PIN4_Pos 4 /*!< Digital function (PAD) enable on pin 4 */ #define GPIO_DENSET_PIN5_Pos 5 /*!< Digital function (PAD) enable on pin 5 */ #define GPIO_DENSET_PIN6_Pos 6 /*!< Digital function (PAD) enable on pin 6 */ #define GPIO_DENSET_PIN7_Pos 7 /*!< Digital function (PAD) enable on pin 7 */ #define GPIO_DENSET_PIN8_Pos 8 /*!< Digital function (PAD) enable on pin 8 */ #define GPIO_DENSET_PIN9_Pos 9 /*!< Digital function (PAD) enable on pin 9 */ #define GPIO_DENSET_PIN10_Pos 10 /*!< Digital function (PAD) enable on pin 10 */ #define GPIO_DENSET_PIN11_Pos 11 /*!< Digital function (PAD) enable on pin 11 */ #define GPIO_DENSET_PIN12_Pos 12 /*!< Digital function (PAD) enable on pin 12 */ #define GPIO_DENSET_PIN13_Pos 13 /*!< Digital function (PAD) enable on pin 13 */ #define GPIO_DENSET_PIN14_Pos 14 /*!< Digital function (PAD) enable on pin 14 */ #define GPIO_DENSET_PIN15_Pos 15 /*!< Digital function (PAD) enable on pin 15 */ /* Bit field masks: */ #define GPIO_DENSET_PIN0_Msk 0x00000001UL /*!< Digital function (PAD) enable on pin 0 */ #define GPIO_DENSET_PIN1_Msk 0x00000002UL /*!< Digital function (PAD) enable on pin 1 */ #define GPIO_DENSET_PIN2_Msk 0x00000004UL /*!< Digital function (PAD) enable on pin 2 */ #define GPIO_DENSET_PIN3_Msk 0x00000008UL /*!< Digital function (PAD) enable on pin 3 */ #define GPIO_DENSET_PIN4_Msk 0x00000010UL /*!< Digital function (PAD) enable on pin 4 */ #define GPIO_DENSET_PIN5_Msk 0x00000020UL /*!< Digital function (PAD) enable on pin 5 */ #define GPIO_DENSET_PIN6_Msk 0x00000040UL /*!< Digital function (PAD) enable on pin 6 */ #define GPIO_DENSET_PIN7_Msk 0x00000080UL /*!< Digital function (PAD) enable on pin 7 */ #define GPIO_DENSET_PIN8_Msk 0x00000100UL /*!< Digital function (PAD) enable on pin 8 */ #define GPIO_DENSET_PIN9_Msk 0x00000200UL /*!< Digital function (PAD) enable on pin 9 */ #define GPIO_DENSET_PIN10_Msk 0x00000400UL /*!< Digital function (PAD) enable on pin 10 */ #define GPIO_DENSET_PIN11_Msk 0x00000800UL /*!< Digital function (PAD) enable on pin 11 */ #define GPIO_DENSET_PIN12_Msk 0x00001000UL /*!< Digital function (PAD) enable on pin 12 */ #define GPIO_DENSET_PIN13_Msk 0x00002000UL /*!< Digital function (PAD) enable on pin 13 */ #define GPIO_DENSET_PIN14_Msk 0x00004000UL /*!< Digital function (PAD) enable on pin 14 */ #define GPIO_DENSET_PIN15_Msk 0x00008000UL /*!< Digital function (PAD) enable on pin 15 */ /*-- DENCLR: Digital function (PAD) disable register ---------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Digital function (PAD) disable on pin 0 */ uint32_t PIN1 :1; /*!< Digital function (PAD) disable on pin 1 */ uint32_t PIN2 :1; /*!< Digital function (PAD) disable on pin 2 */ uint32_t PIN3 :1; /*!< Digital function (PAD) disable on pin 3 */ uint32_t PIN4 :1; /*!< Digital function (PAD) disable on pin 4 */ uint32_t PIN5 :1; /*!< Digital function (PAD) disable on pin 5 */ uint32_t PIN6 :1; /*!< Digital function (PAD) disable on pin 6 */ uint32_t PIN7 :1; /*!< Digital function (PAD) disable on pin 7 */ uint32_t PIN8 :1; /*!< Digital function (PAD) disable on pin 8 */ uint32_t PIN9 :1; /*!< Digital function (PAD) disable on pin 9 */ uint32_t PIN10 :1; /*!< Digital function (PAD) disable on pin 10 */ uint32_t PIN11 :1; /*!< Digital function (PAD) disable on pin 11 */ uint32_t PIN12 :1; /*!< Digital function (PAD) disable on pin 12 */ uint32_t PIN13 :1; /*!< Digital function (PAD) disable on pin 13 */ uint32_t PIN14 :1; /*!< Digital function (PAD) disable on pin 14 */ uint32_t PIN15 :1; /*!< Digital function (PAD) disable on pin 15 */ } _GPIO_DENCLR_bits; /* Bit field positions: */ #define GPIO_DENCLR_PIN0_Pos 0 /*!< Digital function (PAD) disable on pin 0 */ #define GPIO_DENCLR_PIN1_Pos 1 /*!< Digital function (PAD) disable on pin 1 */ #define GPIO_DENCLR_PIN2_Pos 2 /*!< Digital function (PAD) disable on pin 2 */ #define GPIO_DENCLR_PIN3_Pos 3 /*!< Digital function (PAD) disable on pin 3 */ #define GPIO_DENCLR_PIN4_Pos 4 /*!< Digital function (PAD) disable on pin 4 */ #define GPIO_DENCLR_PIN5_Pos 5 /*!< Digital function (PAD) disable on pin 5 */ #define GPIO_DENCLR_PIN6_Pos 6 /*!< Digital function (PAD) disable on pin 6 */ #define GPIO_DENCLR_PIN7_Pos 7 /*!< Digital function (PAD) disable on pin 7 */ #define GPIO_DENCLR_PIN8_Pos 8 /*!< Digital function (PAD) disable on pin 8 */ #define GPIO_DENCLR_PIN9_Pos 9 /*!< Digital function (PAD) disable on pin 9 */ #define GPIO_DENCLR_PIN10_Pos 10 /*!< Digital function (PAD) disable on pin 10 */ #define GPIO_DENCLR_PIN11_Pos 11 /*!< Digital function (PAD) disable on pin 11 */ #define GPIO_DENCLR_PIN12_Pos 12 /*!< Digital function (PAD) disable on pin 12 */ #define GPIO_DENCLR_PIN13_Pos 13 /*!< Digital function (PAD) disable on pin 13 */ #define GPIO_DENCLR_PIN14_Pos 14 /*!< Digital function (PAD) disable on pin 14 */ #define GPIO_DENCLR_PIN15_Pos 15 /*!< Digital function (PAD) disable on pin 15 */ /* Bit field masks: */ #define GPIO_DENCLR_PIN0_Msk 0x00000001UL /*!< Digital function (PAD) disable on pin 0 */ #define GPIO_DENCLR_PIN1_Msk 0x00000002UL /*!< Digital function (PAD) disable on pin 1 */ #define GPIO_DENCLR_PIN2_Msk 0x00000004UL /*!< Digital function (PAD) disable on pin 2 */ #define GPIO_DENCLR_PIN3_Msk 0x00000008UL /*!< Digital function (PAD) disable on pin 3 */ #define GPIO_DENCLR_PIN4_Msk 0x00000010UL /*!< Digital function (PAD) disable on pin 4 */ #define GPIO_DENCLR_PIN5_Msk 0x00000020UL /*!< Digital function (PAD) disable on pin 5 */ #define GPIO_DENCLR_PIN6_Msk 0x00000040UL /*!< Digital function (PAD) disable on pin 6 */ #define GPIO_DENCLR_PIN7_Msk 0x00000080UL /*!< Digital function (PAD) disable on pin 7 */ #define GPIO_DENCLR_PIN8_Msk 0x00000100UL /*!< Digital function (PAD) disable on pin 8 */ #define GPIO_DENCLR_PIN9_Msk 0x00000200UL /*!< Digital function (PAD) disable on pin 9 */ #define GPIO_DENCLR_PIN10_Msk 0x00000400UL /*!< Digital function (PAD) disable on pin 10 */ #define GPIO_DENCLR_PIN11_Msk 0x00000800UL /*!< Digital function (PAD) disable on pin 11 */ #define GPIO_DENCLR_PIN12_Msk 0x00001000UL /*!< Digital function (PAD) disable on pin 12 */ #define GPIO_DENCLR_PIN13_Msk 0x00002000UL /*!< Digital function (PAD) disable on pin 13 */ #define GPIO_DENCLR_PIN14_Msk 0x00004000UL /*!< Digital function (PAD) disable on pin 14 */ #define GPIO_DENCLR_PIN15_Msk 0x00008000UL /*!< Digital function (PAD) disable on pin 15 */ /*-- INMODE: Select input mode register ----------------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :2; /*!< Select input mode for pin 0 */ uint32_t PIN1 :2; /*!< Select input mode for pin 1 */ uint32_t PIN2 :2; /*!< Select input mode for pin 2 */ uint32_t PIN3 :2; /*!< Select input mode for pin 3 */ uint32_t PIN4 :2; /*!< Select input mode for pin 4 */ uint32_t PIN5 :2; /*!< Select input mode for pin 5 */ uint32_t PIN6 :2; /*!< Select input mode for pin 6 */ uint32_t PIN7 :2; /*!< Select input mode for pin 7 */ uint32_t PIN8 :2; /*!< Select input mode for pin 8 */ uint32_t PIN9 :2; /*!< Select input mode for pin 9 */ uint32_t PIN10 :2; /*!< Select input mode for pin 10 */ uint32_t PIN11 :2; /*!< Select input mode for pin 11 */ uint32_t PIN12 :2; /*!< Select input mode for pin 12 */ uint32_t PIN13 :2; /*!< Select input mode for pin 13 */ uint32_t PIN14 :2; /*!< Select input mode for pin 14 */ uint32_t PIN15 :2; /*!< Select input mode for pin 15 */ } _GPIO_INMODE_bits; /* Bit field positions: */ #define GPIO_INMODE_PIN0_Pos 0 /*!< Select input mode for pin 0 */ #define GPIO_INMODE_PIN1_Pos 2 /*!< Select input mode for pin 1 */ #define GPIO_INMODE_PIN2_Pos 4 /*!< Select input mode for pin 2 */ #define GPIO_INMODE_PIN3_Pos 6 /*!< Select input mode for pin 3 */ #define GPIO_INMODE_PIN4_Pos 8 /*!< Select input mode for pin 4 */ #define GPIO_INMODE_PIN5_Pos 10 /*!< Select input mode for pin 5 */ #define GPIO_INMODE_PIN6_Pos 12 /*!< Select input mode for pin 6 */ #define GPIO_INMODE_PIN7_Pos 14 /*!< Select input mode for pin 7 */ #define GPIO_INMODE_PIN8_Pos 16 /*!< Select input mode for pin 8 */ #define GPIO_INMODE_PIN9_Pos 18 /*!< Select input mode for pin 9 */ #define GPIO_INMODE_PIN10_Pos 20 /*!< Select input mode for pin 10 */ #define GPIO_INMODE_PIN11_Pos 22 /*!< Select input mode for pin 11 */ #define GPIO_INMODE_PIN12_Pos 24 /*!< Select input mode for pin 12 */ #define GPIO_INMODE_PIN13_Pos 26 /*!< Select input mode for pin 13 */ #define GPIO_INMODE_PIN14_Pos 28 /*!< Select input mode for pin 14 */ #define GPIO_INMODE_PIN15_Pos 30 /*!< Select input mode for pin 15 */ /* Bit field masks: */ #define GPIO_INMODE_PIN0_Msk 0x00000003UL /*!< Select input mode for pin 0 */ #define GPIO_INMODE_PIN1_Msk 0x0000000CUL /*!< Select input mode for pin 1 */ #define GPIO_INMODE_PIN2_Msk 0x00000030UL /*!< Select input mode for pin 2 */ #define GPIO_INMODE_PIN3_Msk 0x000000C0UL /*!< Select input mode for pin 3 */ #define GPIO_INMODE_PIN4_Msk 0x00000300UL /*!< Select input mode for pin 4 */ #define GPIO_INMODE_PIN5_Msk 0x00000C00UL /*!< Select input mode for pin 5 */ #define GPIO_INMODE_PIN6_Msk 0x00003000UL /*!< Select input mode for pin 6 */ #define GPIO_INMODE_PIN7_Msk 0x0000C000UL /*!< Select input mode for pin 7 */ #define GPIO_INMODE_PIN8_Msk 0x00030000UL /*!< Select input mode for pin 8 */ #define GPIO_INMODE_PIN9_Msk 0x000C0000UL /*!< Select input mode for pin 9 */ #define GPIO_INMODE_PIN10_Msk 0x00300000UL /*!< Select input mode for pin 10 */ #define GPIO_INMODE_PIN11_Msk 0x00C00000UL /*!< Select input mode for pin 11 */ #define GPIO_INMODE_PIN12_Msk 0x03000000UL /*!< Select input mode for pin 12 */ #define GPIO_INMODE_PIN13_Msk 0x0C000000UL /*!< Select input mode for pin 13 */ #define GPIO_INMODE_PIN14_Msk 0x30000000UL /*!< Select input mode for pin 14 */ #define GPIO_INMODE_PIN15_Msk 0xC0000000UL /*!< Select input mode for pin 15 */ /* Bit field enums: */ typedef enum { GPIO_INMODE_PIN0_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN0_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN0_Enum; typedef enum { GPIO_INMODE_PIN1_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN1_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN1_Enum; typedef enum { GPIO_INMODE_PIN2_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN2_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN2_Enum; typedef enum { GPIO_INMODE_PIN3_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN3_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN3_Enum; typedef enum { GPIO_INMODE_PIN4_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN4_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN4_Enum; typedef enum { GPIO_INMODE_PIN5_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN5_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN5_Enum; typedef enum { GPIO_INMODE_PIN6_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN6_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN6_Enum; typedef enum { GPIO_INMODE_PIN7_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN7_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN7_Enum; typedef enum { GPIO_INMODE_PIN8_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN8_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN8_Enum; typedef enum { GPIO_INMODE_PIN9_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN9_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN9_Enum; typedef enum { GPIO_INMODE_PIN10_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN10_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN10_Enum; typedef enum { GPIO_INMODE_PIN11_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN11_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN11_Enum; typedef enum { GPIO_INMODE_PIN12_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN12_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN12_Enum; typedef enum { GPIO_INMODE_PIN13_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN13_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN13_Enum; typedef enum { GPIO_INMODE_PIN14_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN14_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN14_Enum; typedef enum { GPIO_INMODE_PIN15_Schmitt = 0x0UL, /*!< Scmitt buffer */ GPIO_INMODE_PIN15_Disable = 0x3UL, /*!< Input buffer disabled */ } GPIO_INMODE_PIN15_Enum; /*-- PULLMODE: Select pull mode register ---------------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :2; /*!< Select pull mode for pin 0 */ uint32_t PIN1 :2; /*!< Select pull mode for pin 1 */ uint32_t PIN2 :2; /*!< Select pull mode for pin 2 */ uint32_t PIN3 :2; /*!< Select pull mode for pin 3 */ uint32_t PIN4 :2; /*!< Select pull mode for pin 4 */ uint32_t PIN5 :2; /*!< Select pull mode for pin 5 */ uint32_t PIN6 :2; /*!< Select pull mode for pin 6 */ uint32_t PIN7 :2; /*!< Select pull mode for pin 7 */ uint32_t PIN8 :2; /*!< Select pull mode for pin 8 */ uint32_t PIN9 :2; /*!< Select pull mode for pin 9 */ uint32_t PIN10 :2; /*!< Select pull mode for pin 10 */ uint32_t PIN11 :2; /*!< Select pull mode for pin 11 */ uint32_t PIN12 :2; /*!< Select pull mode for pin 12 */ uint32_t PIN13 :2; /*!< Select pull mode for pin 13 */ uint32_t PIN14 :2; /*!< Select pull mode for pin 14 */ uint32_t PIN15 :2; /*!< Select pull mode for pin 15 */ } _GPIO_PULLMODE_bits; /* Bit field positions: */ #define GPIO_PULLMODE_PIN0_Pos 0 /*!< Select pull mode for pin 0 */ #define GPIO_PULLMODE_PIN1_Pos 2 /*!< Select pull mode for pin 1 */ #define GPIO_PULLMODE_PIN2_Pos 4 /*!< Select pull mode for pin 2 */ #define GPIO_PULLMODE_PIN3_Pos 6 /*!< Select pull mode for pin 3 */ #define GPIO_PULLMODE_PIN4_Pos 8 /*!< Select pull mode for pin 4 */ #define GPIO_PULLMODE_PIN5_Pos 10 /*!< Select pull mode for pin 5 */ #define GPIO_PULLMODE_PIN6_Pos 12 /*!< Select pull mode for pin 6 */ #define GPIO_PULLMODE_PIN7_Pos 14 /*!< Select pull mode for pin 7 */ #define GPIO_PULLMODE_PIN8_Pos 16 /*!< Select pull mode for pin 8 */ #define GPIO_PULLMODE_PIN9_Pos 18 /*!< Select pull mode for pin 9 */ #define GPIO_PULLMODE_PIN10_Pos 20 /*!< Select pull mode for pin 10 */ #define GPIO_PULLMODE_PIN11_Pos 22 /*!< Select pull mode for pin 11 */ #define GPIO_PULLMODE_PIN12_Pos 24 /*!< Select pull mode for pin 12 */ #define GPIO_PULLMODE_PIN13_Pos 26 /*!< Select pull mode for pin 13 */ #define GPIO_PULLMODE_PIN14_Pos 28 /*!< Select pull mode for pin 14 */ #define GPIO_PULLMODE_PIN15_Pos 30 /*!< Select pull mode for pin 15 */ /* Bit field masks: */ #define GPIO_PULLMODE_PIN0_Msk 0x00000003UL /*!< Select pull mode for pin 0 */ #define GPIO_PULLMODE_PIN1_Msk 0x0000000CUL /*!< Select pull mode for pin 1 */ #define GPIO_PULLMODE_PIN2_Msk 0x00000030UL /*!< Select pull mode for pin 2 */ #define GPIO_PULLMODE_PIN3_Msk 0x000000C0UL /*!< Select pull mode for pin 3 */ #define GPIO_PULLMODE_PIN4_Msk 0x00000300UL /*!< Select pull mode for pin 4 */ #define GPIO_PULLMODE_PIN5_Msk 0x00000C00UL /*!< Select pull mode for pin 5 */ #define GPIO_PULLMODE_PIN6_Msk 0x00003000UL /*!< Select pull mode for pin 6 */ #define GPIO_PULLMODE_PIN7_Msk 0x0000C000UL /*!< Select pull mode for pin 7 */ #define GPIO_PULLMODE_PIN8_Msk 0x00030000UL /*!< Select pull mode for pin 8 */ #define GPIO_PULLMODE_PIN9_Msk 0x000C0000UL /*!< Select pull mode for pin 9 */ #define GPIO_PULLMODE_PIN10_Msk 0x00300000UL /*!< Select pull mode for pin 10 */ #define GPIO_PULLMODE_PIN11_Msk 0x00C00000UL /*!< Select pull mode for pin 11 */ #define GPIO_PULLMODE_PIN12_Msk 0x03000000UL /*!< Select pull mode for pin 12 */ #define GPIO_PULLMODE_PIN13_Msk 0x0C000000UL /*!< Select pull mode for pin 13 */ #define GPIO_PULLMODE_PIN14_Msk 0x30000000UL /*!< Select pull mode for pin 14 */ #define GPIO_PULLMODE_PIN15_Msk 0xC0000000UL /*!< Select pull mode for pin 15 */ /* Bit field enums: */ typedef enum { GPIO_PULLMODE_PIN0_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN0_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN0_Enum; typedef enum { GPIO_PULLMODE_PIN1_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN1_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN1_Enum; typedef enum { GPIO_PULLMODE_PIN2_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN2_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN2_Enum; typedef enum { GPIO_PULLMODE_PIN3_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN3_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN3_Enum; typedef enum { GPIO_PULLMODE_PIN4_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN4_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN4_Enum; typedef enum { GPIO_PULLMODE_PIN5_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN5_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN5_Enum; typedef enum { GPIO_PULLMODE_PIN6_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN6_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN6_Enum; typedef enum { GPIO_PULLMODE_PIN7_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN7_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN7_Enum; typedef enum { GPIO_PULLMODE_PIN8_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN8_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN8_Enum; typedef enum { GPIO_PULLMODE_PIN9_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN9_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN9_Enum; typedef enum { GPIO_PULLMODE_PIN10_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN10_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN10_Enum; typedef enum { GPIO_PULLMODE_PIN11_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN11_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN11_Enum; typedef enum { GPIO_PULLMODE_PIN12_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN12_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN12_Enum; typedef enum { GPIO_PULLMODE_PIN13_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN13_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN13_Enum; typedef enum { GPIO_PULLMODE_PIN14_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN14_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN14_Enum; typedef enum { GPIO_PULLMODE_PIN15_Disable = 0x0UL, /*!< Pull disabled */ GPIO_PULLMODE_PIN15_PU = 0x1UL, /*!< Pull-up */ } GPIO_PULLMODE_PIN15_Enum; /*-- OUTMODE: Select output mode register --------------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :2; /*!< Select output mode for pin 0 */ uint32_t PIN1 :2; /*!< Select output mode for pin 1 */ uint32_t PIN2 :2; /*!< Select output mode for pin 2 */ uint32_t PIN3 :2; /*!< Select output mode for pin 3 */ uint32_t PIN4 :2; /*!< Select output mode for pin 4 */ uint32_t PIN5 :2; /*!< Select output mode for pin 5 */ uint32_t PIN6 :2; /*!< Select output mode for pin 6 */ uint32_t PIN7 :2; /*!< Select output mode for pin 7 */ uint32_t PIN8 :2; /*!< Select output mode for pin 8 */ uint32_t PIN9 :2; /*!< Select output mode for pin 9 */ uint32_t PIN10 :2; /*!< Select output mode for pin 10 */ uint32_t PIN11 :2; /*!< Select output mode for pin 11 */ uint32_t PIN12 :2; /*!< Select output mode for pin 12 */ uint32_t PIN13 :2; /*!< Select output mode for pin 13 */ uint32_t PIN14 :2; /*!< Select output mode for pin 14 */ uint32_t PIN15 :2; /*!< Select output mode for pin 15 */ } _GPIO_OUTMODE_bits; /* Bit field positions: */ #define GPIO_OUTMODE_PIN0_Pos 0 /*!< Select output mode for pin 0 */ #define GPIO_OUTMODE_PIN1_Pos 2 /*!< Select output mode for pin 1 */ #define GPIO_OUTMODE_PIN2_Pos 4 /*!< Select output mode for pin 2 */ #define GPIO_OUTMODE_PIN3_Pos 6 /*!< Select output mode for pin 3 */ #define GPIO_OUTMODE_PIN4_Pos 8 /*!< Select output mode for pin 4 */ #define GPIO_OUTMODE_PIN5_Pos 10 /*!< Select output mode for pin 5 */ #define GPIO_OUTMODE_PIN6_Pos 12 /*!< Select output mode for pin 6 */ #define GPIO_OUTMODE_PIN7_Pos 14 /*!< Select output mode for pin 7 */ #define GPIO_OUTMODE_PIN8_Pos 16 /*!< Select output mode for pin 8 */ #define GPIO_OUTMODE_PIN9_Pos 18 /*!< Select output mode for pin 9 */ #define GPIO_OUTMODE_PIN10_Pos 20 /*!< Select output mode for pin 10 */ #define GPIO_OUTMODE_PIN11_Pos 22 /*!< Select output mode for pin 11 */ #define GPIO_OUTMODE_PIN12_Pos 24 /*!< Select output mode for pin 12 */ #define GPIO_OUTMODE_PIN13_Pos 26 /*!< Select output mode for pin 13 */ #define GPIO_OUTMODE_PIN14_Pos 28 /*!< Select output mode for pin 14 */ #define GPIO_OUTMODE_PIN15_Pos 30 /*!< Select output mode for pin 15 */ /* Bit field masks: */ #define GPIO_OUTMODE_PIN0_Msk 0x00000003UL /*!< Select output mode for pin 0 */ #define GPIO_OUTMODE_PIN1_Msk 0x0000000CUL /*!< Select output mode for pin 1 */ #define GPIO_OUTMODE_PIN2_Msk 0x00000030UL /*!< Select output mode for pin 2 */ #define GPIO_OUTMODE_PIN3_Msk 0x000000C0UL /*!< Select output mode for pin 3 */ #define GPIO_OUTMODE_PIN4_Msk 0x00000300UL /*!< Select output mode for pin 4 */ #define GPIO_OUTMODE_PIN5_Msk 0x00000C00UL /*!< Select output mode for pin 5 */ #define GPIO_OUTMODE_PIN6_Msk 0x00003000UL /*!< Select output mode for pin 6 */ #define GPIO_OUTMODE_PIN7_Msk 0x0000C000UL /*!< Select output mode for pin 7 */ #define GPIO_OUTMODE_PIN8_Msk 0x00030000UL /*!< Select output mode for pin 8 */ #define GPIO_OUTMODE_PIN9_Msk 0x000C0000UL /*!< Select output mode for pin 9 */ #define GPIO_OUTMODE_PIN10_Msk 0x00300000UL /*!< Select output mode for pin 10 */ #define GPIO_OUTMODE_PIN11_Msk 0x00C00000UL /*!< Select output mode for pin 11 */ #define GPIO_OUTMODE_PIN12_Msk 0x03000000UL /*!< Select output mode for pin 12 */ #define GPIO_OUTMODE_PIN13_Msk 0x0C000000UL /*!< Select output mode for pin 13 */ #define GPIO_OUTMODE_PIN14_Msk 0x30000000UL /*!< Select output mode for pin 14 */ #define GPIO_OUTMODE_PIN15_Msk 0xC0000000UL /*!< Select output mode for pin 15 */ /* Bit field enums: */ typedef enum { GPIO_OUTMODE_PIN0_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN0_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN0_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN0_Enum; typedef enum { GPIO_OUTMODE_PIN1_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN1_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN1_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN1_Enum; typedef enum { GPIO_OUTMODE_PIN2_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN2_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN2_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN2_Enum; typedef enum { GPIO_OUTMODE_PIN3_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN3_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN3_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN3_Enum; typedef enum { GPIO_OUTMODE_PIN4_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN4_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN4_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN4_Enum; typedef enum { GPIO_OUTMODE_PIN5_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN5_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN5_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN5_Enum; typedef enum { GPIO_OUTMODE_PIN6_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN6_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN6_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN6_Enum; typedef enum { GPIO_OUTMODE_PIN7_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN7_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN7_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN7_Enum; typedef enum { GPIO_OUTMODE_PIN8_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN8_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN8_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN8_Enum; typedef enum { GPIO_OUTMODE_PIN9_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN9_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN9_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN9_Enum; typedef enum { GPIO_OUTMODE_PIN10_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN10_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN10_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN10_Enum; typedef enum { GPIO_OUTMODE_PIN11_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN11_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN11_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN11_Enum; typedef enum { GPIO_OUTMODE_PIN12_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN12_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN12_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN12_Enum; typedef enum { GPIO_OUTMODE_PIN13_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN13_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN13_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN13_Enum; typedef enum { GPIO_OUTMODE_PIN14_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN14_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN14_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN14_Enum; typedef enum { GPIO_OUTMODE_PIN15_PP = 0x0UL, /*!< Push-pull output */ GPIO_OUTMODE_PIN15_OD = 0x1UL, /*!< Open drain output */ GPIO_OUTMODE_PIN15_OS = 0x2UL, /*!< Open source output */ } GPIO_OUTMODE_PIN15_Enum; /*-- DRIVEMODE: Select drive mode register -------------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :2; /*!< Select drive mode for pin 0 */ uint32_t PIN1 :2; /*!< Select drive mode for pin 1 */ uint32_t PIN2 :2; /*!< Select drive mode for pin 2 */ uint32_t PIN3 :2; /*!< Select drive mode for pin 3 */ uint32_t PIN4 :2; /*!< Select drive mode for pin 4 */ uint32_t PIN5 :2; /*!< Select drive mode for pin 5 */ uint32_t PIN6 :2; /*!< Select drive mode for pin 6 */ uint32_t PIN7 :2; /*!< Select drive mode for pin 7 */ uint32_t PIN8 :2; /*!< Select drive mode for pin 8 */ uint32_t PIN9 :2; /*!< Select drive mode for pin 9 */ uint32_t PIN10 :2; /*!< Select drive mode for pin 10 */ uint32_t PIN11 :2; /*!< Select drive mode for pin 11 */ uint32_t PIN12 :2; /*!< Select drive mode for pin 12 */ uint32_t PIN13 :2; /*!< Select drive mode for pin 13 */ uint32_t PIN14 :2; /*!< Select drive mode for pin 14 */ uint32_t PIN15 :2; /*!< Select drive mode for pin 15 */ } _GPIO_DRIVEMODE_bits; /* Bit field positions: */ #define GPIO_DRIVEMODE_PIN0_Pos 0 /*!< Select drive mode for pin 0 */ #define GPIO_DRIVEMODE_PIN1_Pos 2 /*!< Select drive mode for pin 1 */ #define GPIO_DRIVEMODE_PIN2_Pos 4 /*!< Select drive mode for pin 2 */ #define GPIO_DRIVEMODE_PIN3_Pos 6 /*!< Select drive mode for pin 3 */ #define GPIO_DRIVEMODE_PIN4_Pos 8 /*!< Select drive mode for pin 4 */ #define GPIO_DRIVEMODE_PIN5_Pos 10 /*!< Select drive mode for pin 5 */ #define GPIO_DRIVEMODE_PIN6_Pos 12 /*!< Select drive mode for pin 6 */ #define GPIO_DRIVEMODE_PIN7_Pos 14 /*!< Select drive mode for pin 7 */ #define GPIO_DRIVEMODE_PIN8_Pos 16 /*!< Select drive mode for pin 8 */ #define GPIO_DRIVEMODE_PIN9_Pos 18 /*!< Select drive mode for pin 9 */ #define GPIO_DRIVEMODE_PIN10_Pos 20 /*!< Select drive mode for pin 10 */ #define GPIO_DRIVEMODE_PIN11_Pos 22 /*!< Select drive mode for pin 11 */ #define GPIO_DRIVEMODE_PIN12_Pos 24 /*!< Select drive mode for pin 12 */ #define GPIO_DRIVEMODE_PIN13_Pos 26 /*!< Select drive mode for pin 13 */ #define GPIO_DRIVEMODE_PIN14_Pos 28 /*!< Select drive mode for pin 14 */ #define GPIO_DRIVEMODE_PIN15_Pos 30 /*!< Select drive mode for pin 15 */ /* Bit field masks: */ #define GPIO_DRIVEMODE_PIN0_Msk 0x00000003UL /*!< Select drive mode for pin 0 */ #define GPIO_DRIVEMODE_PIN1_Msk 0x0000000CUL /*!< Select drive mode for pin 1 */ #define GPIO_DRIVEMODE_PIN2_Msk 0x00000030UL /*!< Select drive mode for pin 2 */ #define GPIO_DRIVEMODE_PIN3_Msk 0x000000C0UL /*!< Select drive mode for pin 3 */ #define GPIO_DRIVEMODE_PIN4_Msk 0x00000300UL /*!< Select drive mode for pin 4 */ #define GPIO_DRIVEMODE_PIN5_Msk 0x00000C00UL /*!< Select drive mode for pin 5 */ #define GPIO_DRIVEMODE_PIN6_Msk 0x00003000UL /*!< Select drive mode for pin 6 */ #define GPIO_DRIVEMODE_PIN7_Msk 0x0000C000UL /*!< Select drive mode for pin 7 */ #define GPIO_DRIVEMODE_PIN8_Msk 0x00030000UL /*!< Select drive mode for pin 8 */ #define GPIO_DRIVEMODE_PIN9_Msk 0x000C0000UL /*!< Select drive mode for pin 9 */ #define GPIO_DRIVEMODE_PIN10_Msk 0x00300000UL /*!< Select drive mode for pin 10 */ #define GPIO_DRIVEMODE_PIN11_Msk 0x00C00000UL /*!< Select drive mode for pin 11 */ #define GPIO_DRIVEMODE_PIN12_Msk 0x03000000UL /*!< Select drive mode for pin 12 */ #define GPIO_DRIVEMODE_PIN13_Msk 0x0C000000UL /*!< Select drive mode for pin 13 */ #define GPIO_DRIVEMODE_PIN14_Msk 0x30000000UL /*!< Select drive mode for pin 14 */ #define GPIO_DRIVEMODE_PIN15_Msk 0xC0000000UL /*!< Select drive mode for pin 15 */ /* Bit field enums: */ typedef enum { GPIO_DRIVEMODE_PIN0_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN0_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN0_Enum; typedef enum { GPIO_DRIVEMODE_PIN1_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN1_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN1_Enum; typedef enum { GPIO_DRIVEMODE_PIN2_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN2_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN2_Enum; typedef enum { GPIO_DRIVEMODE_PIN3_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN3_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN3_Enum; typedef enum { GPIO_DRIVEMODE_PIN4_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN4_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN4_Enum; typedef enum { GPIO_DRIVEMODE_PIN5_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN5_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN5_Enum; typedef enum { GPIO_DRIVEMODE_PIN6_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN6_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN6_Enum; typedef enum { GPIO_DRIVEMODE_PIN7_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN7_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN7_Enum; typedef enum { GPIO_DRIVEMODE_PIN8_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN8_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN8_Enum; typedef enum { GPIO_DRIVEMODE_PIN9_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN9_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN9_Enum; typedef enum { GPIO_DRIVEMODE_PIN10_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN10_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN10_Enum; typedef enum { GPIO_DRIVEMODE_PIN11_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN11_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN11_Enum; typedef enum { GPIO_DRIVEMODE_PIN12_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN12_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN12_Enum; typedef enum { GPIO_DRIVEMODE_PIN13_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN13_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN13_Enum; typedef enum { GPIO_DRIVEMODE_PIN14_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN14_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN14_Enum; typedef enum { GPIO_DRIVEMODE_PIN15_HS = 0x0UL, /*!< High strength */ GPIO_DRIVEMODE_PIN15_LS = 0x2UL, /*!< Low strength */ } GPIO_DRIVEMODE_PIN15_Enum; /*-- OUTENSET: Output enable register ------------------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Output enable for pin 0 */ uint32_t PIN1 :1; /*!< Output enable for pin 1 */ uint32_t PIN2 :1; /*!< Output enable for pin 2 */ uint32_t PIN3 :1; /*!< Output enable for pin 3 */ uint32_t PIN4 :1; /*!< Output enable for pin 4 */ uint32_t PIN5 :1; /*!< Output enable for pin 5 */ uint32_t PIN6 :1; /*!< Output enable for pin 6 */ uint32_t PIN7 :1; /*!< Output enable for pin 7 */ uint32_t PIN8 :1; /*!< Output enable for pin 8 */ uint32_t PIN9 :1; /*!< Output enable for pin 9 */ uint32_t PIN10 :1; /*!< Output enable for pin 10 */ uint32_t PIN11 :1; /*!< Output enable for pin 11 */ uint32_t PIN12 :1; /*!< Output enable for pin 12 */ uint32_t PIN13 :1; /*!< Output enable for pin 13 */ uint32_t PIN14 :1; /*!< Output enable for pin 14 */ uint32_t PIN15 :1; /*!< Output enable for pin 15 */ } _GPIO_OUTENSET_bits; /* Bit field positions: */ #define GPIO_OUTENSET_PIN0_Pos 0 /*!< Output enable for pin 0 */ #define GPIO_OUTENSET_PIN1_Pos 1 /*!< Output enable for pin 1 */ #define GPIO_OUTENSET_PIN2_Pos 2 /*!< Output enable for pin 2 */ #define GPIO_OUTENSET_PIN3_Pos 3 /*!< Output enable for pin 3 */ #define GPIO_OUTENSET_PIN4_Pos 4 /*!< Output enable for pin 4 */ #define GPIO_OUTENSET_PIN5_Pos 5 /*!< Output enable for pin 5 */ #define GPIO_OUTENSET_PIN6_Pos 6 /*!< Output enable for pin 6 */ #define GPIO_OUTENSET_PIN7_Pos 7 /*!< Output enable for pin 7 */ #define GPIO_OUTENSET_PIN8_Pos 8 /*!< Output enable for pin 8 */ #define GPIO_OUTENSET_PIN9_Pos 9 /*!< Output enable for pin 9 */ #define GPIO_OUTENSET_PIN10_Pos 10 /*!< Output enable for pin 10 */ #define GPIO_OUTENSET_PIN11_Pos 11 /*!< Output enable for pin 11 */ #define GPIO_OUTENSET_PIN12_Pos 12 /*!< Output enable for pin 12 */ #define GPIO_OUTENSET_PIN13_Pos 13 /*!< Output enable for pin 13 */ #define GPIO_OUTENSET_PIN14_Pos 14 /*!< Output enable for pin 14 */ #define GPIO_OUTENSET_PIN15_Pos 15 /*!< Output enable for pin 15 */ /* Bit field masks: */ #define GPIO_OUTENSET_PIN0_Msk 0x00000001UL /*!< Output enable for pin 0 */ #define GPIO_OUTENSET_PIN1_Msk 0x00000002UL /*!< Output enable for pin 1 */ #define GPIO_OUTENSET_PIN2_Msk 0x00000004UL /*!< Output enable for pin 2 */ #define GPIO_OUTENSET_PIN3_Msk 0x00000008UL /*!< Output enable for pin 3 */ #define GPIO_OUTENSET_PIN4_Msk 0x00000010UL /*!< Output enable for pin 4 */ #define GPIO_OUTENSET_PIN5_Msk 0x00000020UL /*!< Output enable for pin 5 */ #define GPIO_OUTENSET_PIN6_Msk 0x00000040UL /*!< Output enable for pin 6 */ #define GPIO_OUTENSET_PIN7_Msk 0x00000080UL /*!< Output enable for pin 7 */ #define GPIO_OUTENSET_PIN8_Msk 0x00000100UL /*!< Output enable for pin 8 */ #define GPIO_OUTENSET_PIN9_Msk 0x00000200UL /*!< Output enable for pin 9 */ #define GPIO_OUTENSET_PIN10_Msk 0x00000400UL /*!< Output enable for pin 10 */ #define GPIO_OUTENSET_PIN11_Msk 0x00000800UL /*!< Output enable for pin 11 */ #define GPIO_OUTENSET_PIN12_Msk 0x00001000UL /*!< Output enable for pin 12 */ #define GPIO_OUTENSET_PIN13_Msk 0x00002000UL /*!< Output enable for pin 13 */ #define GPIO_OUTENSET_PIN14_Msk 0x00004000UL /*!< Output enable for pin 14 */ #define GPIO_OUTENSET_PIN15_Msk 0x00008000UL /*!< Output enable for pin 15 */ /*-- OUTENCLR: Output disable register -----------------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Output disable for pin 0 */ uint32_t PIN1 :1; /*!< Output disable for pin 1 */ uint32_t PIN2 :1; /*!< Output disable for pin 2 */ uint32_t PIN3 :1; /*!< Output disable for pin 3 */ uint32_t PIN4 :1; /*!< Output disable for pin 4 */ uint32_t PIN5 :1; /*!< Output disable for pin 5 */ uint32_t PIN6 :1; /*!< Output disable for pin 6 */ uint32_t PIN7 :1; /*!< Output disable for pin 7 */ uint32_t PIN8 :1; /*!< Output disable for pin 8 */ uint32_t PIN9 :1; /*!< Output disable for pin 9 */ uint32_t PIN10 :1; /*!< Output disable for pin 10 */ uint32_t PIN11 :1; /*!< Output disable for pin 11 */ uint32_t PIN12 :1; /*!< Output disable for pin 12 */ uint32_t PIN13 :1; /*!< Output disable for pin 13 */ uint32_t PIN14 :1; /*!< Output disable for pin 14 */ uint32_t PIN15 :1; /*!< Output disable for pin 15 */ } _GPIO_OUTENCLR_bits; /* Bit field positions: */ #define GPIO_OUTENCLR_PIN0_Pos 0 /*!< Output disable for pin 0 */ #define GPIO_OUTENCLR_PIN1_Pos 1 /*!< Output disable for pin 1 */ #define GPIO_OUTENCLR_PIN2_Pos 2 /*!< Output disable for pin 2 */ #define GPIO_OUTENCLR_PIN3_Pos 3 /*!< Output disable for pin 3 */ #define GPIO_OUTENCLR_PIN4_Pos 4 /*!< Output disable for pin 4 */ #define GPIO_OUTENCLR_PIN5_Pos 5 /*!< Output disable for pin 5 */ #define GPIO_OUTENCLR_PIN6_Pos 6 /*!< Output disable for pin 6 */ #define GPIO_OUTENCLR_PIN7_Pos 7 /*!< Output disable for pin 7 */ #define GPIO_OUTENCLR_PIN8_Pos 8 /*!< Output disable for pin 8 */ #define GPIO_OUTENCLR_PIN9_Pos 9 /*!< Output disable for pin 9 */ #define GPIO_OUTENCLR_PIN10_Pos 10 /*!< Output disable for pin 10 */ #define GPIO_OUTENCLR_PIN11_Pos 11 /*!< Output disable for pin 11 */ #define GPIO_OUTENCLR_PIN12_Pos 12 /*!< Output disable for pin 12 */ #define GPIO_OUTENCLR_PIN13_Pos 13 /*!< Output disable for pin 13 */ #define GPIO_OUTENCLR_PIN14_Pos 14 /*!< Output disable for pin 14 */ #define GPIO_OUTENCLR_PIN15_Pos 15 /*!< Output disable for pin 15 */ /* Bit field masks: */ #define GPIO_OUTENCLR_PIN0_Msk 0x00000001UL /*!< Output disable for pin 0 */ #define GPIO_OUTENCLR_PIN1_Msk 0x00000002UL /*!< Output disable for pin 1 */ #define GPIO_OUTENCLR_PIN2_Msk 0x00000004UL /*!< Output disable for pin 2 */ #define GPIO_OUTENCLR_PIN3_Msk 0x00000008UL /*!< Output disable for pin 3 */ #define GPIO_OUTENCLR_PIN4_Msk 0x00000010UL /*!< Output disable for pin 4 */ #define GPIO_OUTENCLR_PIN5_Msk 0x00000020UL /*!< Output disable for pin 5 */ #define GPIO_OUTENCLR_PIN6_Msk 0x00000040UL /*!< Output disable for pin 6 */ #define GPIO_OUTENCLR_PIN7_Msk 0x00000080UL /*!< Output disable for pin 7 */ #define GPIO_OUTENCLR_PIN8_Msk 0x00000100UL /*!< Output disable for pin 8 */ #define GPIO_OUTENCLR_PIN9_Msk 0x00000200UL /*!< Output disable for pin 9 */ #define GPIO_OUTENCLR_PIN10_Msk 0x00000400UL /*!< Output disable for pin 10 */ #define GPIO_OUTENCLR_PIN11_Msk 0x00000800UL /*!< Output disable for pin 11 */ #define GPIO_OUTENCLR_PIN12_Msk 0x00001000UL /*!< Output disable for pin 12 */ #define GPIO_OUTENCLR_PIN13_Msk 0x00002000UL /*!< Output disable for pin 13 */ #define GPIO_OUTENCLR_PIN14_Msk 0x00004000UL /*!< Output disable for pin 14 */ #define GPIO_OUTENCLR_PIN15_Msk 0x00008000UL /*!< Output disable for pin 15 */ /*-- ALTFUNCSET: Alternative function enable register --------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Alternative function enable for pin 0 */ uint32_t PIN1 :1; /*!< Alternative function enable for pin 1 */ uint32_t PIN2 :1; /*!< Alternative function enable for pin 2 */ uint32_t PIN3 :1; /*!< Alternative function enable for pin 3 */ uint32_t PIN4 :1; /*!< Alternative function enable for pin 4 */ uint32_t PIN5 :1; /*!< Alternative function enable for pin 5 */ uint32_t PIN6 :1; /*!< Alternative function enable for pin 6 */ uint32_t PIN7 :1; /*!< Alternative function enable for pin 7 */ uint32_t PIN8 :1; /*!< Alternative function enable for pin 8 */ uint32_t PIN9 :1; /*!< Alternative function enable for pin 9 */ uint32_t PIN10 :1; /*!< Alternative function enable for pin 10 */ uint32_t PIN11 :1; /*!< Alternative function enable for pin 11 */ uint32_t PIN12 :1; /*!< Alternative function enable for pin 12 */ uint32_t PIN13 :1; /*!< Alternative function enable for pin 13 */ uint32_t PIN14 :1; /*!< Alternative function enable for pin 14 */ uint32_t PIN15 :1; /*!< Alternative function enable for pin 15 */ } _GPIO_ALTFUNCSET_bits; /* Bit field positions: */ #define GPIO_ALTFUNCSET_PIN0_Pos 0 /*!< Alternative function enable for pin 0 */ #define GPIO_ALTFUNCSET_PIN1_Pos 1 /*!< Alternative function enable for pin 1 */ #define GPIO_ALTFUNCSET_PIN2_Pos 2 /*!< Alternative function enable for pin 2 */ #define GPIO_ALTFUNCSET_PIN3_Pos 3 /*!< Alternative function enable for pin 3 */ #define GPIO_ALTFUNCSET_PIN4_Pos 4 /*!< Alternative function enable for pin 4 */ #define GPIO_ALTFUNCSET_PIN5_Pos 5 /*!< Alternative function enable for pin 5 */ #define GPIO_ALTFUNCSET_PIN6_Pos 6 /*!< Alternative function enable for pin 6 */ #define GPIO_ALTFUNCSET_PIN7_Pos 7 /*!< Alternative function enable for pin 7 */ #define GPIO_ALTFUNCSET_PIN8_Pos 8 /*!< Alternative function enable for pin 8 */ #define GPIO_ALTFUNCSET_PIN9_Pos 9 /*!< Alternative function enable for pin 9 */ #define GPIO_ALTFUNCSET_PIN10_Pos 10 /*!< Alternative function enable for pin 10 */ #define GPIO_ALTFUNCSET_PIN11_Pos 11 /*!< Alternative function enable for pin 11 */ #define GPIO_ALTFUNCSET_PIN12_Pos 12 /*!< Alternative function enable for pin 12 */ #define GPIO_ALTFUNCSET_PIN13_Pos 13 /*!< Alternative function enable for pin 13 */ #define GPIO_ALTFUNCSET_PIN14_Pos 14 /*!< Alternative function enable for pin 14 */ #define GPIO_ALTFUNCSET_PIN15_Pos 15 /*!< Alternative function enable for pin 15 */ /* Bit field masks: */ #define GPIO_ALTFUNCSET_PIN0_Msk 0x00000001UL /*!< Alternative function enable for pin 0 */ #define GPIO_ALTFUNCSET_PIN1_Msk 0x00000002UL /*!< Alternative function enable for pin 1 */ #define GPIO_ALTFUNCSET_PIN2_Msk 0x00000004UL /*!< Alternative function enable for pin 2 */ #define GPIO_ALTFUNCSET_PIN3_Msk 0x00000008UL /*!< Alternative function enable for pin 3 */ #define GPIO_ALTFUNCSET_PIN4_Msk 0x00000010UL /*!< Alternative function enable for pin 4 */ #define GPIO_ALTFUNCSET_PIN5_Msk 0x00000020UL /*!< Alternative function enable for pin 5 */ #define GPIO_ALTFUNCSET_PIN6_Msk 0x00000040UL /*!< Alternative function enable for pin 6 */ #define GPIO_ALTFUNCSET_PIN7_Msk 0x00000080UL /*!< Alternative function enable for pin 7 */ #define GPIO_ALTFUNCSET_PIN8_Msk 0x00000100UL /*!< Alternative function enable for pin 8 */ #define GPIO_ALTFUNCSET_PIN9_Msk 0x00000200UL /*!< Alternative function enable for pin 9 */ #define GPIO_ALTFUNCSET_PIN10_Msk 0x00000400UL /*!< Alternative function enable for pin 10 */ #define GPIO_ALTFUNCSET_PIN11_Msk 0x00000800UL /*!< Alternative function enable for pin 11 */ #define GPIO_ALTFUNCSET_PIN12_Msk 0x00001000UL /*!< Alternative function enable for pin 12 */ #define GPIO_ALTFUNCSET_PIN13_Msk 0x00002000UL /*!< Alternative function enable for pin 13 */ #define GPIO_ALTFUNCSET_PIN14_Msk 0x00004000UL /*!< Alternative function enable for pin 14 */ #define GPIO_ALTFUNCSET_PIN15_Msk 0x00008000UL /*!< Alternative function enable for pin 15 */ /*-- ALTFUNCCLR: Alternative function disable register -------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Alternative function disable for pin 0 */ uint32_t PIN1 :1; /*!< Alternative function disable for pin 1 */ uint32_t PIN2 :1; /*!< Alternative function disable for pin 2 */ uint32_t PIN3 :1; /*!< Alternative function disable for pin 3 */ uint32_t PIN4 :1; /*!< Alternative function disable for pin 4 */ uint32_t PIN5 :1; /*!< Alternative function disable for pin 5 */ uint32_t PIN6 :1; /*!< Alternative function disable for pin 6 */ uint32_t PIN7 :1; /*!< Alternative function disable for pin 7 */ uint32_t PIN8 :1; /*!< Alternative function disable for pin 8 */ uint32_t PIN9 :1; /*!< Alternative function disable for pin 9 */ uint32_t PIN10 :1; /*!< Alternative function disable for pin 10 */ uint32_t PIN11 :1; /*!< Alternative function disable for pin 11 */ uint32_t PIN12 :1; /*!< Alternative function disable for pin 12 */ uint32_t PIN13 :1; /*!< Alternative function disable for pin 13 */ uint32_t PIN14 :1; /*!< Alternative function disable for pin 14 */ uint32_t PIN15 :1; /*!< Alternative function disable for pin 15 */ } _GPIO_ALTFUNCCLR_bits; /* Bit field positions: */ #define GPIO_ALTFUNCCLR_PIN0_Pos 0 /*!< Alternative function disable for pin 0 */ #define GPIO_ALTFUNCCLR_PIN1_Pos 1 /*!< Alternative function disable for pin 1 */ #define GPIO_ALTFUNCCLR_PIN2_Pos 2 /*!< Alternative function disable for pin 2 */ #define GPIO_ALTFUNCCLR_PIN3_Pos 3 /*!< Alternative function disable for pin 3 */ #define GPIO_ALTFUNCCLR_PIN4_Pos 4 /*!< Alternative function disable for pin 4 */ #define GPIO_ALTFUNCCLR_PIN5_Pos 5 /*!< Alternative function disable for pin 5 */ #define GPIO_ALTFUNCCLR_PIN6_Pos 6 /*!< Alternative function disable for pin 6 */ #define GPIO_ALTFUNCCLR_PIN7_Pos 7 /*!< Alternative function disable for pin 7 */ #define GPIO_ALTFUNCCLR_PIN8_Pos 8 /*!< Alternative function disable for pin 8 */ #define GPIO_ALTFUNCCLR_PIN9_Pos 9 /*!< Alternative function disable for pin 9 */ #define GPIO_ALTFUNCCLR_PIN10_Pos 10 /*!< Alternative function disable for pin 10 */ #define GPIO_ALTFUNCCLR_PIN11_Pos 11 /*!< Alternative function disable for pin 11 */ #define GPIO_ALTFUNCCLR_PIN12_Pos 12 /*!< Alternative function disable for pin 12 */ #define GPIO_ALTFUNCCLR_PIN13_Pos 13 /*!< Alternative function disable for pin 13 */ #define GPIO_ALTFUNCCLR_PIN14_Pos 14 /*!< Alternative function disable for pin 14 */ #define GPIO_ALTFUNCCLR_PIN15_Pos 15 /*!< Alternative function disable for pin 15 */ /* Bit field masks: */ #define GPIO_ALTFUNCCLR_PIN0_Msk 0x00000001UL /*!< Alternative function disable for pin 0 */ #define GPIO_ALTFUNCCLR_PIN1_Msk 0x00000002UL /*!< Alternative function disable for pin 1 */ #define GPIO_ALTFUNCCLR_PIN2_Msk 0x00000004UL /*!< Alternative function disable for pin 2 */ #define GPIO_ALTFUNCCLR_PIN3_Msk 0x00000008UL /*!< Alternative function disable for pin 3 */ #define GPIO_ALTFUNCCLR_PIN4_Msk 0x00000010UL /*!< Alternative function disable for pin 4 */ #define GPIO_ALTFUNCCLR_PIN5_Msk 0x00000020UL /*!< Alternative function disable for pin 5 */ #define GPIO_ALTFUNCCLR_PIN6_Msk 0x00000040UL /*!< Alternative function disable for pin 6 */ #define GPIO_ALTFUNCCLR_PIN7_Msk 0x00000080UL /*!< Alternative function disable for pin 7 */ #define GPIO_ALTFUNCCLR_PIN8_Msk 0x00000100UL /*!< Alternative function disable for pin 8 */ #define GPIO_ALTFUNCCLR_PIN9_Msk 0x00000200UL /*!< Alternative function disable for pin 9 */ #define GPIO_ALTFUNCCLR_PIN10_Msk 0x00000400UL /*!< Alternative function disable for pin 10 */ #define GPIO_ALTFUNCCLR_PIN11_Msk 0x00000800UL /*!< Alternative function disable for pin 11 */ #define GPIO_ALTFUNCCLR_PIN12_Msk 0x00001000UL /*!< Alternative function disable for pin 12 */ #define GPIO_ALTFUNCCLR_PIN13_Msk 0x00002000UL /*!< Alternative function disable for pin 13 */ #define GPIO_ALTFUNCCLR_PIN14_Msk 0x00004000UL /*!< Alternative function disable for pin 14 */ #define GPIO_ALTFUNCCLR_PIN15_Msk 0x00008000UL /*!< Alternative function disable for pin 15 */ /*-- ALTFUNCNUM0: Alternative function number register -------------------------------------------------------*/ typedef struct { uint32_t PIN0 :4; /*!< Select altfunc number for pin 0 */ uint32_t PIN1 :4; /*!< Select altfunc number for pin 1 */ uint32_t PIN2 :4; /*!< Select altfunc number for pin 2 */ uint32_t PIN3 :4; /*!< Select altfunc number for pin 3 */ uint32_t PIN4 :4; /*!< Select altfunc number for pin 4 */ uint32_t PIN5 :4; /*!< Select altfunc number for pin 5 */ uint32_t PIN6 :4; /*!< Select altfunc number for pin 6 */ uint32_t PIN7 :4; /*!< Select altfunc number for pin 7 */ } _GPIO_ALTFUNCNUM0_bits; /* Bit field positions: */ #define GPIO_ALTFUNCNUM0_PIN0_Pos 0 /*!< Select altfunc number for pin 0 */ #define GPIO_ALTFUNCNUM0_PIN1_Pos 4 /*!< Select altfunc number for pin 1 */ #define GPIO_ALTFUNCNUM0_PIN2_Pos 8 /*!< Select altfunc number for pin 2 */ #define GPIO_ALTFUNCNUM0_PIN3_Pos 12 /*!< Select altfunc number for pin 3 */ #define GPIO_ALTFUNCNUM0_PIN4_Pos 16 /*!< Select altfunc number for pin 4 */ #define GPIO_ALTFUNCNUM0_PIN5_Pos 20 /*!< Select altfunc number for pin 5 */ #define GPIO_ALTFUNCNUM0_PIN6_Pos 24 /*!< Select altfunc number for pin 6 */ #define GPIO_ALTFUNCNUM0_PIN7_Pos 28 /*!< Select altfunc number for pin 7 */ /* Bit field masks: */ #define GPIO_ALTFUNCNUM0_PIN0_Msk 0x0000000FUL /*!< Select altfunc number for pin 0 */ #define GPIO_ALTFUNCNUM0_PIN1_Msk 0x000000F0UL /*!< Select altfunc number for pin 1 */ #define GPIO_ALTFUNCNUM0_PIN2_Msk 0x00000F00UL /*!< Select altfunc number for pin 2 */ #define GPIO_ALTFUNCNUM0_PIN3_Msk 0x0000F000UL /*!< Select altfunc number for pin 3 */ #define GPIO_ALTFUNCNUM0_PIN4_Msk 0x000F0000UL /*!< Select altfunc number for pin 4 */ #define GPIO_ALTFUNCNUM0_PIN5_Msk 0x00F00000UL /*!< Select altfunc number for pin 5 */ #define GPIO_ALTFUNCNUM0_PIN6_Msk 0x0F000000UL /*!< Select altfunc number for pin 6 */ #define GPIO_ALTFUNCNUM0_PIN7_Msk 0xF0000000UL /*!< Select altfunc number for pin 7 */ /* Bit field enums: */ typedef enum { GPIO_ALTFUNCNUM0_PIN0_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM0_PIN0_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM0_PIN0_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM0_PIN0_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM0_PIN0_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM0_PIN0_Enum; typedef enum { GPIO_ALTFUNCNUM0_PIN1_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM0_PIN1_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM0_PIN1_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM0_PIN1_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM0_PIN1_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM0_PIN1_Enum; typedef enum { GPIO_ALTFUNCNUM0_PIN2_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM0_PIN2_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM0_PIN2_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM0_PIN2_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM0_PIN2_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM0_PIN2_Enum; typedef enum { GPIO_ALTFUNCNUM0_PIN3_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM0_PIN3_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM0_PIN3_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM0_PIN3_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM0_PIN3_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM0_PIN3_Enum; typedef enum { GPIO_ALTFUNCNUM0_PIN4_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM0_PIN4_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM0_PIN4_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM0_PIN4_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM0_PIN4_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM0_PIN4_Enum; typedef enum { GPIO_ALTFUNCNUM0_PIN5_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM0_PIN5_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM0_PIN5_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM0_PIN5_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM0_PIN5_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM0_PIN5_Enum; typedef enum { GPIO_ALTFUNCNUM0_PIN6_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM0_PIN6_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM0_PIN6_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM0_PIN6_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM0_PIN6_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM0_PIN6_Enum; typedef enum { GPIO_ALTFUNCNUM0_PIN7_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM0_PIN7_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM0_PIN7_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM0_PIN7_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM0_PIN7_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM0_PIN7_Enum; /*-- ALTFUNCNUM1: Alternative function number register -------------------------------------------------------*/ typedef struct { uint32_t PIN8 :4; /*!< Select altfunc number for pin 8 */ uint32_t PIN9 :4; /*!< Select altfunc number for pin 9 */ uint32_t PIN10 :4; /*!< Select altfunc number for pin 10 */ uint32_t PIN11 :4; /*!< Select altfunc number for pin 11 */ uint32_t PIN12 :4; /*!< Select altfunc number for pin 12 */ uint32_t PIN13 :4; /*!< Select altfunc number for pin 13 */ uint32_t PIN14 :4; /*!< Select altfunc number for pin 14 */ uint32_t PIN15 :4; /*!< Select altfunc number for pin 15 */ } _GPIO_ALTFUNCNUM1_bits; /* Bit field positions: */ #define GPIO_ALTFUNCNUM1_PIN8_Pos 0 /*!< Select altfunc number for pin 8 */ #define GPIO_ALTFUNCNUM1_PIN9_Pos 4 /*!< Select altfunc number for pin 9 */ #define GPIO_ALTFUNCNUM1_PIN10_Pos 8 /*!< Select altfunc number for pin 10 */ #define GPIO_ALTFUNCNUM1_PIN11_Pos 12 /*!< Select altfunc number for pin 11 */ #define GPIO_ALTFUNCNUM1_PIN12_Pos 16 /*!< Select altfunc number for pin 12 */ #define GPIO_ALTFUNCNUM1_PIN13_Pos 20 /*!< Select altfunc number for pin 13 */ #define GPIO_ALTFUNCNUM1_PIN14_Pos 24 /*!< Select altfunc number for pin 14 */ #define GPIO_ALTFUNCNUM1_PIN15_Pos 28 /*!< Select altfunc number for pin 15 */ /* Bit field masks: */ #define GPIO_ALTFUNCNUM1_PIN8_Msk 0x0000000FUL /*!< Select altfunc number for pin 8 */ #define GPIO_ALTFUNCNUM1_PIN9_Msk 0x000000F0UL /*!< Select altfunc number for pin 9 */ #define GPIO_ALTFUNCNUM1_PIN10_Msk 0x00000F00UL /*!< Select altfunc number for pin 10 */ #define GPIO_ALTFUNCNUM1_PIN11_Msk 0x0000F000UL /*!< Select altfunc number for pin 11 */ #define GPIO_ALTFUNCNUM1_PIN12_Msk 0x000F0000UL /*!< Select altfunc number for pin 12 */ #define GPIO_ALTFUNCNUM1_PIN13_Msk 0x00F00000UL /*!< Select altfunc number for pin 13 */ #define GPIO_ALTFUNCNUM1_PIN14_Msk 0x0F000000UL /*!< Select altfunc number for pin 14 */ #define GPIO_ALTFUNCNUM1_PIN15_Msk 0xF0000000UL /*!< Select altfunc number for pin 15 */ /* Bit field enums: */ typedef enum { GPIO_ALTFUNCNUM1_PIN8_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM1_PIN8_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM1_PIN8_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM1_PIN8_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM1_PIN8_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM1_PIN8_Enum; typedef enum { GPIO_ALTFUNCNUM1_PIN9_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM1_PIN9_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM1_PIN9_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM1_PIN9_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM1_PIN9_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM1_PIN9_Enum; typedef enum { GPIO_ALTFUNCNUM1_PIN10_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM1_PIN10_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM1_PIN10_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM1_PIN10_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM1_PIN10_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM1_PIN10_Enum; typedef enum { GPIO_ALTFUNCNUM1_PIN11_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM1_PIN11_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM1_PIN11_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM1_PIN11_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM1_PIN11_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM1_PIN11_Enum; typedef enum { GPIO_ALTFUNCNUM1_PIN12_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM1_PIN12_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM1_PIN12_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM1_PIN12_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM1_PIN12_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM1_PIN12_Enum; typedef enum { GPIO_ALTFUNCNUM1_PIN13_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM1_PIN13_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM1_PIN13_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM1_PIN13_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM1_PIN13_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM1_PIN13_Enum; typedef enum { GPIO_ALTFUNCNUM1_PIN14_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM1_PIN14_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM1_PIN14_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM1_PIN14_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM1_PIN14_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM1_PIN14_Enum; typedef enum { GPIO_ALTFUNCNUM1_PIN15_Disable = 0x0UL, /*!< Altfunc disabled */ GPIO_ALTFUNCNUM1_PIN15_AF1 = 0x1UL, /*!< Altfunc 1 enable */ GPIO_ALTFUNCNUM1_PIN15_AF2 = 0x2UL, /*!< Altfunc 2 enable */ GPIO_ALTFUNCNUM1_PIN15_AF3 = 0x3UL, /*!< Altfunc 3 enable */ GPIO_ALTFUNCNUM1_PIN15_AF4 = 0x4UL, /*!< Altfunc 4 enable */ } GPIO_ALTFUNCNUM1_PIN15_Enum; /*-- SYNCSET: Additional double flip-flop syncronization enable register -------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 0 */ uint32_t PIN1 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 1 */ uint32_t PIN2 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 2 */ uint32_t PIN3 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 3 */ uint32_t PIN4 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 4 */ uint32_t PIN5 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 5 */ uint32_t PIN6 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 6 */ uint32_t PIN7 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 7 */ uint32_t PIN8 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 8 */ uint32_t PIN9 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 9 */ uint32_t PIN10 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 10 */ uint32_t PIN11 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 11 */ uint32_t PIN12 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 12 */ uint32_t PIN13 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 13 */ uint32_t PIN14 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 14 */ uint32_t PIN15 :1; /*!< Additional double flip-flop syncronization buffer enable for pin 15 */ } _GPIO_SYNCSET_bits; /* Bit field positions: */ #define GPIO_SYNCSET_PIN0_Pos 0 /*!< Additional double flip-flop syncronization buffer enable for pin 0 */ #define GPIO_SYNCSET_PIN1_Pos 1 /*!< Additional double flip-flop syncronization buffer enable for pin 1 */ #define GPIO_SYNCSET_PIN2_Pos 2 /*!< Additional double flip-flop syncronization buffer enable for pin 2 */ #define GPIO_SYNCSET_PIN3_Pos 3 /*!< Additional double flip-flop syncronization buffer enable for pin 3 */ #define GPIO_SYNCSET_PIN4_Pos 4 /*!< Additional double flip-flop syncronization buffer enable for pin 4 */ #define GPIO_SYNCSET_PIN5_Pos 5 /*!< Additional double flip-flop syncronization buffer enable for pin 5 */ #define GPIO_SYNCSET_PIN6_Pos 6 /*!< Additional double flip-flop syncronization buffer enable for pin 6 */ #define GPIO_SYNCSET_PIN7_Pos 7 /*!< Additional double flip-flop syncronization buffer enable for pin 7 */ #define GPIO_SYNCSET_PIN8_Pos 8 /*!< Additional double flip-flop syncronization buffer enable for pin 8 */ #define GPIO_SYNCSET_PIN9_Pos 9 /*!< Additional double flip-flop syncronization buffer enable for pin 9 */ #define GPIO_SYNCSET_PIN10_Pos 10 /*!< Additional double flip-flop syncronization buffer enable for pin 10 */ #define GPIO_SYNCSET_PIN11_Pos 11 /*!< Additional double flip-flop syncronization buffer enable for pin 11 */ #define GPIO_SYNCSET_PIN12_Pos 12 /*!< Additional double flip-flop syncronization buffer enable for pin 12 */ #define GPIO_SYNCSET_PIN13_Pos 13 /*!< Additional double flip-flop syncronization buffer enable for pin 13 */ #define GPIO_SYNCSET_PIN14_Pos 14 /*!< Additional double flip-flop syncronization buffer enable for pin 14 */ #define GPIO_SYNCSET_PIN15_Pos 15 /*!< Additional double flip-flop syncronization buffer enable for pin 15 */ /* Bit field masks: */ #define GPIO_SYNCSET_PIN0_Msk 0x00000001UL /*!< Additional double flip-flop syncronization buffer enable for pin 0 */ #define GPIO_SYNCSET_PIN1_Msk 0x00000002UL /*!< Additional double flip-flop syncronization buffer enable for pin 1 */ #define GPIO_SYNCSET_PIN2_Msk 0x00000004UL /*!< Additional double flip-flop syncronization buffer enable for pin 2 */ #define GPIO_SYNCSET_PIN3_Msk 0x00000008UL /*!< Additional double flip-flop syncronization buffer enable for pin 3 */ #define GPIO_SYNCSET_PIN4_Msk 0x00000010UL /*!< Additional double flip-flop syncronization buffer enable for pin 4 */ #define GPIO_SYNCSET_PIN5_Msk 0x00000020UL /*!< Additional double flip-flop syncronization buffer enable for pin 5 */ #define GPIO_SYNCSET_PIN6_Msk 0x00000040UL /*!< Additional double flip-flop syncronization buffer enable for pin 6 */ #define GPIO_SYNCSET_PIN7_Msk 0x00000080UL /*!< Additional double flip-flop syncronization buffer enable for pin 7 */ #define GPIO_SYNCSET_PIN8_Msk 0x00000100UL /*!< Additional double flip-flop syncronization buffer enable for pin 8 */ #define GPIO_SYNCSET_PIN9_Msk 0x00000200UL /*!< Additional double flip-flop syncronization buffer enable for pin 9 */ #define GPIO_SYNCSET_PIN10_Msk 0x00000400UL /*!< Additional double flip-flop syncronization buffer enable for pin 10 */ #define GPIO_SYNCSET_PIN11_Msk 0x00000800UL /*!< Additional double flip-flop syncronization buffer enable for pin 11 */ #define GPIO_SYNCSET_PIN12_Msk 0x00001000UL /*!< Additional double flip-flop syncronization buffer enable for pin 12 */ #define GPIO_SYNCSET_PIN13_Msk 0x00002000UL /*!< Additional double flip-flop syncronization buffer enable for pin 13 */ #define GPIO_SYNCSET_PIN14_Msk 0x00004000UL /*!< Additional double flip-flop syncronization buffer enable for pin 14 */ #define GPIO_SYNCSET_PIN15_Msk 0x00008000UL /*!< Additional double flip-flop syncronization buffer enable for pin 15 */ /*-- SYNCCLR: Additional double flip-flop syncronization disable register ------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Additional double flip-flop syncronization disable for pin 0 */ uint32_t PIN1 :1; /*!< Additional double flip-flop syncronization disable for pin 1 */ uint32_t PIN2 :1; /*!< Additional double flip-flop syncronization disable for pin 2 */ uint32_t PIN3 :1; /*!< Additional double flip-flop syncronization disable for pin 3 */ uint32_t PIN4 :1; /*!< Additional double flip-flop syncronization disable for pin 4 */ uint32_t PIN5 :1; /*!< Additional double flip-flop syncronization disable for pin 5 */ uint32_t PIN6 :1; /*!< Additional double flip-flop syncronization disable for pin 6 */ uint32_t PIN7 :1; /*!< Additional double flip-flop syncronization disable for pin 7 */ uint32_t PIN8 :1; /*!< Additional double flip-flop syncronization disable for pin 8 */ uint32_t PIN9 :1; /*!< Additional double flip-flop syncronization disable for pin 9 */ uint32_t PIN10 :1; /*!< Additional double flip-flop syncronization disable for pin 10 */ uint32_t PIN11 :1; /*!< Additional double flip-flop syncronization disable for pin 11 */ uint32_t PIN12 :1; /*!< Additional double flip-flop syncronization disable for pin 12 */ uint32_t PIN13 :1; /*!< Additional double flip-flop syncronization disable for pin 13 */ uint32_t PIN14 :1; /*!< Additional double flip-flop syncronization disable for pin 14 */ uint32_t PIN15 :1; /*!< Additional double flip-flop syncronization disable for pin 15 */ } _GPIO_SYNCCLR_bits; /* Bit field positions: */ #define GPIO_SYNCCLR_PIN0_Pos 0 /*!< Additional double flip-flop syncronization disable for pin 0 */ #define GPIO_SYNCCLR_PIN1_Pos 1 /*!< Additional double flip-flop syncronization disable for pin 1 */ #define GPIO_SYNCCLR_PIN2_Pos 2 /*!< Additional double flip-flop syncronization disable for pin 2 */ #define GPIO_SYNCCLR_PIN3_Pos 3 /*!< Additional double flip-flop syncronization disable for pin 3 */ #define GPIO_SYNCCLR_PIN4_Pos 4 /*!< Additional double flip-flop syncronization disable for pin 4 */ #define GPIO_SYNCCLR_PIN5_Pos 5 /*!< Additional double flip-flop syncronization disable for pin 5 */ #define GPIO_SYNCCLR_PIN6_Pos 6 /*!< Additional double flip-flop syncronization disable for pin 6 */ #define GPIO_SYNCCLR_PIN7_Pos 7 /*!< Additional double flip-flop syncronization disable for pin 7 */ #define GPIO_SYNCCLR_PIN8_Pos 8 /*!< Additional double flip-flop syncronization disable for pin 8 */ #define GPIO_SYNCCLR_PIN9_Pos 9 /*!< Additional double flip-flop syncronization disable for pin 9 */ #define GPIO_SYNCCLR_PIN10_Pos 10 /*!< Additional double flip-flop syncronization disable for pin 10 */ #define GPIO_SYNCCLR_PIN11_Pos 11 /*!< Additional double flip-flop syncronization disable for pin 11 */ #define GPIO_SYNCCLR_PIN12_Pos 12 /*!< Additional double flip-flop syncronization disable for pin 12 */ #define GPIO_SYNCCLR_PIN13_Pos 13 /*!< Additional double flip-flop syncronization disable for pin 13 */ #define GPIO_SYNCCLR_PIN14_Pos 14 /*!< Additional double flip-flop syncronization disable for pin 14 */ #define GPIO_SYNCCLR_PIN15_Pos 15 /*!< Additional double flip-flop syncronization disable for pin 15 */ /* Bit field masks: */ #define GPIO_SYNCCLR_PIN0_Msk 0x00000001UL /*!< Additional double flip-flop syncronization disable for pin 0 */ #define GPIO_SYNCCLR_PIN1_Msk 0x00000002UL /*!< Additional double flip-flop syncronization disable for pin 1 */ #define GPIO_SYNCCLR_PIN2_Msk 0x00000004UL /*!< Additional double flip-flop syncronization disable for pin 2 */ #define GPIO_SYNCCLR_PIN3_Msk 0x00000008UL /*!< Additional double flip-flop syncronization disable for pin 3 */ #define GPIO_SYNCCLR_PIN4_Msk 0x00000010UL /*!< Additional double flip-flop syncronization disable for pin 4 */ #define GPIO_SYNCCLR_PIN5_Msk 0x00000020UL /*!< Additional double flip-flop syncronization disable for pin 5 */ #define GPIO_SYNCCLR_PIN6_Msk 0x00000040UL /*!< Additional double flip-flop syncronization disable for pin 6 */ #define GPIO_SYNCCLR_PIN7_Msk 0x00000080UL /*!< Additional double flip-flop syncronization disable for pin 7 */ #define GPIO_SYNCCLR_PIN8_Msk 0x00000100UL /*!< Additional double flip-flop syncronization disable for pin 8 */ #define GPIO_SYNCCLR_PIN9_Msk 0x00000200UL /*!< Additional double flip-flop syncronization disable for pin 9 */ #define GPIO_SYNCCLR_PIN10_Msk 0x00000400UL /*!< Additional double flip-flop syncronization disable for pin 10 */ #define GPIO_SYNCCLR_PIN11_Msk 0x00000800UL /*!< Additional double flip-flop syncronization disable for pin 11 */ #define GPIO_SYNCCLR_PIN12_Msk 0x00001000UL /*!< Additional double flip-flop syncronization disable for pin 12 */ #define GPIO_SYNCCLR_PIN13_Msk 0x00002000UL /*!< Additional double flip-flop syncronization disable for pin 13 */ #define GPIO_SYNCCLR_PIN14_Msk 0x00004000UL /*!< Additional double flip-flop syncronization disable for pin 14 */ #define GPIO_SYNCCLR_PIN15_Msk 0x00008000UL /*!< Additional double flip-flop syncronization disable for pin 15 */ /*-- QUALSET: Qualifier enable register ----------------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Qualifier enable for pin 0 */ uint32_t PIN1 :1; /*!< Qualifier enable for pin 1 */ uint32_t PIN2 :1; /*!< Qualifier enable for pin 2 */ uint32_t PIN3 :1; /*!< Qualifier enable for pin 3 */ uint32_t PIN4 :1; /*!< Qualifier enable for pin 4 */ uint32_t PIN5 :1; /*!< Qualifier enable for pin 5 */ uint32_t PIN6 :1; /*!< Qualifier enable for pin 6 */ uint32_t PIN7 :1; /*!< Qualifier enable for pin 7 */ uint32_t PIN8 :1; /*!< Qualifier enable for pin 8 */ uint32_t PIN9 :1; /*!< Qualifier enable for pin 9 */ uint32_t PIN10 :1; /*!< Qualifier enable for pin 10 */ uint32_t PIN11 :1; /*!< Qualifier enable for pin 11 */ uint32_t PIN12 :1; /*!< Qualifier enable for pin 12 */ uint32_t PIN13 :1; /*!< Qualifier enable for pin 13 */ uint32_t PIN14 :1; /*!< Qualifier enable for pin 14 */ uint32_t PIN15 :1; /*!< Qualifier enable for pin 15 */ } _GPIO_QUALSET_bits; /* Bit field positions: */ #define GPIO_QUALSET_PIN0_Pos 0 /*!< Qualifier enable for pin 0 */ #define GPIO_QUALSET_PIN1_Pos 1 /*!< Qualifier enable for pin 1 */ #define GPIO_QUALSET_PIN2_Pos 2 /*!< Qualifier enable for pin 2 */ #define GPIO_QUALSET_PIN3_Pos 3 /*!< Qualifier enable for pin 3 */ #define GPIO_QUALSET_PIN4_Pos 4 /*!< Qualifier enable for pin 4 */ #define GPIO_QUALSET_PIN5_Pos 5 /*!< Qualifier enable for pin 5 */ #define GPIO_QUALSET_PIN6_Pos 6 /*!< Qualifier enable for pin 6 */ #define GPIO_QUALSET_PIN7_Pos 7 /*!< Qualifier enable for pin 7 */ #define GPIO_QUALSET_PIN8_Pos 8 /*!< Qualifier enable for pin 8 */ #define GPIO_QUALSET_PIN9_Pos 9 /*!< Qualifier enable for pin 9 */ #define GPIO_QUALSET_PIN10_Pos 10 /*!< Qualifier enable for pin 10 */ #define GPIO_QUALSET_PIN11_Pos 11 /*!< Qualifier enable for pin 11 */ #define GPIO_QUALSET_PIN12_Pos 12 /*!< Qualifier enable for pin 12 */ #define GPIO_QUALSET_PIN13_Pos 13 /*!< Qualifier enable for pin 13 */ #define GPIO_QUALSET_PIN14_Pos 14 /*!< Qualifier enable for pin 14 */ #define GPIO_QUALSET_PIN15_Pos 15 /*!< Qualifier enable for pin 15 */ /* Bit field masks: */ #define GPIO_QUALSET_PIN0_Msk 0x00000001UL /*!< Qualifier enable for pin 0 */ #define GPIO_QUALSET_PIN1_Msk 0x00000002UL /*!< Qualifier enable for pin 1 */ #define GPIO_QUALSET_PIN2_Msk 0x00000004UL /*!< Qualifier enable for pin 2 */ #define GPIO_QUALSET_PIN3_Msk 0x00000008UL /*!< Qualifier enable for pin 3 */ #define GPIO_QUALSET_PIN4_Msk 0x00000010UL /*!< Qualifier enable for pin 4 */ #define GPIO_QUALSET_PIN5_Msk 0x00000020UL /*!< Qualifier enable for pin 5 */ #define GPIO_QUALSET_PIN6_Msk 0x00000040UL /*!< Qualifier enable for pin 6 */ #define GPIO_QUALSET_PIN7_Msk 0x00000080UL /*!< Qualifier enable for pin 7 */ #define GPIO_QUALSET_PIN8_Msk 0x00000100UL /*!< Qualifier enable for pin 8 */ #define GPIO_QUALSET_PIN9_Msk 0x00000200UL /*!< Qualifier enable for pin 9 */ #define GPIO_QUALSET_PIN10_Msk 0x00000400UL /*!< Qualifier enable for pin 10 */ #define GPIO_QUALSET_PIN11_Msk 0x00000800UL /*!< Qualifier enable for pin 11 */ #define GPIO_QUALSET_PIN12_Msk 0x00001000UL /*!< Qualifier enable for pin 12 */ #define GPIO_QUALSET_PIN13_Msk 0x00002000UL /*!< Qualifier enable for pin 13 */ #define GPIO_QUALSET_PIN14_Msk 0x00004000UL /*!< Qualifier enable for pin 14 */ #define GPIO_QUALSET_PIN15_Msk 0x00008000UL /*!< Qualifier enable for pin 15 */ /*-- QUALCLR: Qualifier disable register ---------------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Qualifier disable for pin 0 */ uint32_t PIN1 :1; /*!< Qualifier disable for pin 1 */ uint32_t PIN2 :1; /*!< Qualifier disable for pin 2 */ uint32_t PIN3 :1; /*!< Qualifier disable for pin 3 */ uint32_t PIN4 :1; /*!< Qualifier disable for pin 4 */ uint32_t PIN5 :1; /*!< Qualifier disable for pin 5 */ uint32_t PIN6 :1; /*!< Qualifier disable for pin 6 */ uint32_t PIN7 :1; /*!< Qualifier disable for pin 7 */ uint32_t PIN8 :1; /*!< Qualifier disable for pin 8 */ uint32_t PIN9 :1; /*!< Qualifier disable for pin 9 */ uint32_t PIN10 :1; /*!< Qualifier disable for pin 10 */ uint32_t PIN11 :1; /*!< Qualifier disable for pin 11 */ uint32_t PIN12 :1; /*!< Qualifier disable for pin 12 */ uint32_t PIN13 :1; /*!< Qualifier disable for pin 13 */ uint32_t PIN14 :1; /*!< Qualifier disable for pin 14 */ uint32_t PIN15 :1; /*!< Qualifier disable for pin 15 */ } _GPIO_QUALCLR_bits; /* Bit field positions: */ #define GPIO_QUALCLR_PIN0_Pos 0 /*!< Qualifier disable for pin 0 */ #define GPIO_QUALCLR_PIN1_Pos 1 /*!< Qualifier disable for pin 1 */ #define GPIO_QUALCLR_PIN2_Pos 2 /*!< Qualifier disable for pin 2 */ #define GPIO_QUALCLR_PIN3_Pos 3 /*!< Qualifier disable for pin 3 */ #define GPIO_QUALCLR_PIN4_Pos 4 /*!< Qualifier disable for pin 4 */ #define GPIO_QUALCLR_PIN5_Pos 5 /*!< Qualifier disable for pin 5 */ #define GPIO_QUALCLR_PIN6_Pos 6 /*!< Qualifier disable for pin 6 */ #define GPIO_QUALCLR_PIN7_Pos 7 /*!< Qualifier disable for pin 7 */ #define GPIO_QUALCLR_PIN8_Pos 8 /*!< Qualifier disable for pin 8 */ #define GPIO_QUALCLR_PIN9_Pos 9 /*!< Qualifier disable for pin 9 */ #define GPIO_QUALCLR_PIN10_Pos 10 /*!< Qualifier disable for pin 10 */ #define GPIO_QUALCLR_PIN11_Pos 11 /*!< Qualifier disable for pin 11 */ #define GPIO_QUALCLR_PIN12_Pos 12 /*!< Qualifier disable for pin 12 */ #define GPIO_QUALCLR_PIN13_Pos 13 /*!< Qualifier disable for pin 13 */ #define GPIO_QUALCLR_PIN14_Pos 14 /*!< Qualifier disable for pin 14 */ #define GPIO_QUALCLR_PIN15_Pos 15 /*!< Qualifier disable for pin 15 */ /* Bit field masks: */ #define GPIO_QUALCLR_PIN0_Msk 0x00000001UL /*!< Qualifier disable for pin 0 */ #define GPIO_QUALCLR_PIN1_Msk 0x00000002UL /*!< Qualifier disable for pin 1 */ #define GPIO_QUALCLR_PIN2_Msk 0x00000004UL /*!< Qualifier disable for pin 2 */ #define GPIO_QUALCLR_PIN3_Msk 0x00000008UL /*!< Qualifier disable for pin 3 */ #define GPIO_QUALCLR_PIN4_Msk 0x00000010UL /*!< Qualifier disable for pin 4 */ #define GPIO_QUALCLR_PIN5_Msk 0x00000020UL /*!< Qualifier disable for pin 5 */ #define GPIO_QUALCLR_PIN6_Msk 0x00000040UL /*!< Qualifier disable for pin 6 */ #define GPIO_QUALCLR_PIN7_Msk 0x00000080UL /*!< Qualifier disable for pin 7 */ #define GPIO_QUALCLR_PIN8_Msk 0x00000100UL /*!< Qualifier disable for pin 8 */ #define GPIO_QUALCLR_PIN9_Msk 0x00000200UL /*!< Qualifier disable for pin 9 */ #define GPIO_QUALCLR_PIN10_Msk 0x00000400UL /*!< Qualifier disable for pin 10 */ #define GPIO_QUALCLR_PIN11_Msk 0x00000800UL /*!< Qualifier disable for pin 11 */ #define GPIO_QUALCLR_PIN12_Msk 0x00001000UL /*!< Qualifier disable for pin 12 */ #define GPIO_QUALCLR_PIN13_Msk 0x00002000UL /*!< Qualifier disable for pin 13 */ #define GPIO_QUALCLR_PIN14_Msk 0x00004000UL /*!< Qualifier disable for pin 14 */ #define GPIO_QUALCLR_PIN15_Msk 0x00008000UL /*!< Qualifier disable for pin 15 */ /*-- QUALMODESET: Qualifier mode set register ----------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Qualifier mode set for pin 0 */ uint32_t PIN1 :1; /*!< Qualifier mode set for pin 1 */ uint32_t PIN2 :1; /*!< Qualifier mode set for pin 2 */ uint32_t PIN3 :1; /*!< Qualifier mode set for pin 3 */ uint32_t PIN4 :1; /*!< Qualifier mode set for pin 4 */ uint32_t PIN5 :1; /*!< Qualifier mode set for pin 5 */ uint32_t PIN6 :1; /*!< Qualifier mode set for pin 6 */ uint32_t PIN7 :1; /*!< Qualifier mode set for pin 7 */ uint32_t PIN8 :1; /*!< Qualifier mode set for pin 8 */ uint32_t PIN9 :1; /*!< Qualifier mode set for pin 9 */ uint32_t PIN10 :1; /*!< Qualifier mode set for pin 10 */ uint32_t PIN11 :1; /*!< Qualifier mode set for pin 11 */ uint32_t PIN12 :1; /*!< Qualifier mode set for pin 12 */ uint32_t PIN13 :1; /*!< Qualifier mode set for pin 13 */ uint32_t PIN14 :1; /*!< Qualifier mode set for pin 14 */ uint32_t PIN15 :1; /*!< Qualifier mode set for pin 15 */ } _GPIO_QUALMODESET_bits; /* Bit field positions: */ #define GPIO_QUALMODESET_PIN0_Pos 0 /*!< Qualifier mode set for pin 0 */ #define GPIO_QUALMODESET_PIN1_Pos 1 /*!< Qualifier mode set for pin 1 */ #define GPIO_QUALMODESET_PIN2_Pos 2 /*!< Qualifier mode set for pin 2 */ #define GPIO_QUALMODESET_PIN3_Pos 3 /*!< Qualifier mode set for pin 3 */ #define GPIO_QUALMODESET_PIN4_Pos 4 /*!< Qualifier mode set for pin 4 */ #define GPIO_QUALMODESET_PIN5_Pos 5 /*!< Qualifier mode set for pin 5 */ #define GPIO_QUALMODESET_PIN6_Pos 6 /*!< Qualifier mode set for pin 6 */ #define GPIO_QUALMODESET_PIN7_Pos 7 /*!< Qualifier mode set for pin 7 */ #define GPIO_QUALMODESET_PIN8_Pos 8 /*!< Qualifier mode set for pin 8 */ #define GPIO_QUALMODESET_PIN9_Pos 9 /*!< Qualifier mode set for pin 9 */ #define GPIO_QUALMODESET_PIN10_Pos 10 /*!< Qualifier mode set for pin 10 */ #define GPIO_QUALMODESET_PIN11_Pos 11 /*!< Qualifier mode set for pin 11 */ #define GPIO_QUALMODESET_PIN12_Pos 12 /*!< Qualifier mode set for pin 12 */ #define GPIO_QUALMODESET_PIN13_Pos 13 /*!< Qualifier mode set for pin 13 */ #define GPIO_QUALMODESET_PIN14_Pos 14 /*!< Qualifier mode set for pin 14 */ #define GPIO_QUALMODESET_PIN15_Pos 15 /*!< Qualifier mode set for pin 15 */ /* Bit field masks: */ #define GPIO_QUALMODESET_PIN0_Msk 0x00000001UL /*!< Qualifier mode set for pin 0 */ #define GPIO_QUALMODESET_PIN1_Msk 0x00000002UL /*!< Qualifier mode set for pin 1 */ #define GPIO_QUALMODESET_PIN2_Msk 0x00000004UL /*!< Qualifier mode set for pin 2 */ #define GPIO_QUALMODESET_PIN3_Msk 0x00000008UL /*!< Qualifier mode set for pin 3 */ #define GPIO_QUALMODESET_PIN4_Msk 0x00000010UL /*!< Qualifier mode set for pin 4 */ #define GPIO_QUALMODESET_PIN5_Msk 0x00000020UL /*!< Qualifier mode set for pin 5 */ #define GPIO_QUALMODESET_PIN6_Msk 0x00000040UL /*!< Qualifier mode set for pin 6 */ #define GPIO_QUALMODESET_PIN7_Msk 0x00000080UL /*!< Qualifier mode set for pin 7 */ #define GPIO_QUALMODESET_PIN8_Msk 0x00000100UL /*!< Qualifier mode set for pin 8 */ #define GPIO_QUALMODESET_PIN9_Msk 0x00000200UL /*!< Qualifier mode set for pin 9 */ #define GPIO_QUALMODESET_PIN10_Msk 0x00000400UL /*!< Qualifier mode set for pin 10 */ #define GPIO_QUALMODESET_PIN11_Msk 0x00000800UL /*!< Qualifier mode set for pin 11 */ #define GPIO_QUALMODESET_PIN12_Msk 0x00001000UL /*!< Qualifier mode set for pin 12 */ #define GPIO_QUALMODESET_PIN13_Msk 0x00002000UL /*!< Qualifier mode set for pin 13 */ #define GPIO_QUALMODESET_PIN14_Msk 0x00004000UL /*!< Qualifier mode set for pin 14 */ #define GPIO_QUALMODESET_PIN15_Msk 0x00008000UL /*!< Qualifier mode set for pin 15 */ /*-- QUALMODECLR: Qualifier mode clear register --------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Qualifier mode clear for pin 0 */ uint32_t PIN1 :1; /*!< Qualifier mode clear for pin 1 */ uint32_t PIN2 :1; /*!< Qualifier mode clear for pin 2 */ uint32_t PIN3 :1; /*!< Qualifier mode clear for pin 3 */ uint32_t PIN4 :1; /*!< Qualifier mode clear for pin 4 */ uint32_t PIN5 :1; /*!< Qualifier mode clear for pin 5 */ uint32_t PIN6 :1; /*!< Qualifier mode clear for pin 6 */ uint32_t PIN7 :1; /*!< Qualifier mode clear for pin 7 */ uint32_t PIN8 :1; /*!< Qualifier mode clear for pin 8 */ uint32_t PIN9 :1; /*!< Qualifier mode clear for pin 9 */ uint32_t PIN10 :1; /*!< Qualifier mode clear for pin 10 */ uint32_t PIN11 :1; /*!< Qualifier mode clear for pin 11 */ uint32_t PIN12 :1; /*!< Qualifier mode clear for pin 12 */ uint32_t PIN13 :1; /*!< Qualifier mode clear for pin 13 */ uint32_t PIN14 :1; /*!< Qualifier mode clear for pin 14 */ uint32_t PIN15 :1; /*!< Qualifier mode clear for pin 15 */ } _GPIO_QUALMODECLR_bits; /* Bit field positions: */ #define GPIO_QUALMODECLR_PIN0_Pos 0 /*!< Qualifier mode clear for pin 0 */ #define GPIO_QUALMODECLR_PIN1_Pos 1 /*!< Qualifier mode clear for pin 1 */ #define GPIO_QUALMODECLR_PIN2_Pos 2 /*!< Qualifier mode clear for pin 2 */ #define GPIO_QUALMODECLR_PIN3_Pos 3 /*!< Qualifier mode clear for pin 3 */ #define GPIO_QUALMODECLR_PIN4_Pos 4 /*!< Qualifier mode clear for pin 4 */ #define GPIO_QUALMODECLR_PIN5_Pos 5 /*!< Qualifier mode clear for pin 5 */ #define GPIO_QUALMODECLR_PIN6_Pos 6 /*!< Qualifier mode clear for pin 6 */ #define GPIO_QUALMODECLR_PIN7_Pos 7 /*!< Qualifier mode clear for pin 7 */ #define GPIO_QUALMODECLR_PIN8_Pos 8 /*!< Qualifier mode clear for pin 8 */ #define GPIO_QUALMODECLR_PIN9_Pos 9 /*!< Qualifier mode clear for pin 9 */ #define GPIO_QUALMODECLR_PIN10_Pos 10 /*!< Qualifier mode clear for pin 10 */ #define GPIO_QUALMODECLR_PIN11_Pos 11 /*!< Qualifier mode clear for pin 11 */ #define GPIO_QUALMODECLR_PIN12_Pos 12 /*!< Qualifier mode clear for pin 12 */ #define GPIO_QUALMODECLR_PIN13_Pos 13 /*!< Qualifier mode clear for pin 13 */ #define GPIO_QUALMODECLR_PIN14_Pos 14 /*!< Qualifier mode clear for pin 14 */ #define GPIO_QUALMODECLR_PIN15_Pos 15 /*!< Qualifier mode clear for pin 15 */ /* Bit field masks: */ #define GPIO_QUALMODECLR_PIN0_Msk 0x00000001UL /*!< Qualifier mode clear for pin 0 */ #define GPIO_QUALMODECLR_PIN1_Msk 0x00000002UL /*!< Qualifier mode clear for pin 1 */ #define GPIO_QUALMODECLR_PIN2_Msk 0x00000004UL /*!< Qualifier mode clear for pin 2 */ #define GPIO_QUALMODECLR_PIN3_Msk 0x00000008UL /*!< Qualifier mode clear for pin 3 */ #define GPIO_QUALMODECLR_PIN4_Msk 0x00000010UL /*!< Qualifier mode clear for pin 4 */ #define GPIO_QUALMODECLR_PIN5_Msk 0x00000020UL /*!< Qualifier mode clear for pin 5 */ #define GPIO_QUALMODECLR_PIN6_Msk 0x00000040UL /*!< Qualifier mode clear for pin 6 */ #define GPIO_QUALMODECLR_PIN7_Msk 0x00000080UL /*!< Qualifier mode clear for pin 7 */ #define GPIO_QUALMODECLR_PIN8_Msk 0x00000100UL /*!< Qualifier mode clear for pin 8 */ #define GPIO_QUALMODECLR_PIN9_Msk 0x00000200UL /*!< Qualifier mode clear for pin 9 */ #define GPIO_QUALMODECLR_PIN10_Msk 0x00000400UL /*!< Qualifier mode clear for pin 10 */ #define GPIO_QUALMODECLR_PIN11_Msk 0x00000800UL /*!< Qualifier mode clear for pin 11 */ #define GPIO_QUALMODECLR_PIN12_Msk 0x00001000UL /*!< Qualifier mode clear for pin 12 */ #define GPIO_QUALMODECLR_PIN13_Msk 0x00002000UL /*!< Qualifier mode clear for pin 13 */ #define GPIO_QUALMODECLR_PIN14_Msk 0x00004000UL /*!< Qualifier mode clear for pin 14 */ #define GPIO_QUALMODECLR_PIN15_Msk 0x00008000UL /*!< Qualifier mode clear for pin 15 */ /*-- QUALSAMPLE: Qualifier sample period register ------------------------------------------------------------*/ typedef struct { uint32_t VAL :20; /*!< Qualifier sample period */ } _GPIO_QUALSAMPLE_bits; /* Bit field positions: */ #define GPIO_QUALSAMPLE_VAL_Pos 0 /*!< Qualifier sample period */ /* Bit field masks: */ #define GPIO_QUALSAMPLE_VAL_Msk 0x000FFFFFUL /*!< Qualifier sample period */ /*-- INTENSET: Interrupt enable register ---------------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Interrupt enable for pin 0 */ uint32_t PIN1 :1; /*!< Interrupt enable for pin 1 */ uint32_t PIN2 :1; /*!< Interrupt enable for pin 2 */ uint32_t PIN3 :1; /*!< Interrupt enable for pin 3 */ uint32_t PIN4 :1; /*!< Interrupt enable for pin 4 */ uint32_t PIN5 :1; /*!< Interrupt enable for pin 5 */ uint32_t PIN6 :1; /*!< Interrupt enable for pin 6 */ uint32_t PIN7 :1; /*!< Interrupt enable for pin 7 */ uint32_t PIN8 :1; /*!< Interrupt enable for pin 8 */ uint32_t PIN9 :1; /*!< Interrupt enable for pin 9 */ uint32_t PIN10 :1; /*!< Interrupt enable for pin 10 */ uint32_t PIN11 :1; /*!< Interrupt enable for pin 11 */ uint32_t PIN12 :1; /*!< Interrupt enable for pin 12 */ uint32_t PIN13 :1; /*!< Interrupt enable for pin 13 */ uint32_t PIN14 :1; /*!< Interrupt enable for pin 14 */ uint32_t PIN15 :1; /*!< Interrupt enable for pin 15 */ } _GPIO_INTENSET_bits; /* Bit field positions: */ #define GPIO_INTENSET_PIN0_Pos 0 /*!< Interrupt enable for pin 0 */ #define GPIO_INTENSET_PIN1_Pos 1 /*!< Interrupt enable for pin 1 */ #define GPIO_INTENSET_PIN2_Pos 2 /*!< Interrupt enable for pin 2 */ #define GPIO_INTENSET_PIN3_Pos 3 /*!< Interrupt enable for pin 3 */ #define GPIO_INTENSET_PIN4_Pos 4 /*!< Interrupt enable for pin 4 */ #define GPIO_INTENSET_PIN5_Pos 5 /*!< Interrupt enable for pin 5 */ #define GPIO_INTENSET_PIN6_Pos 6 /*!< Interrupt enable for pin 6 */ #define GPIO_INTENSET_PIN7_Pos 7 /*!< Interrupt enable for pin 7 */ #define GPIO_INTENSET_PIN8_Pos 8 /*!< Interrupt enable for pin 8 */ #define GPIO_INTENSET_PIN9_Pos 9 /*!< Interrupt enable for pin 9 */ #define GPIO_INTENSET_PIN10_Pos 10 /*!< Interrupt enable for pin 10 */ #define GPIO_INTENSET_PIN11_Pos 11 /*!< Interrupt enable for pin 11 */ #define GPIO_INTENSET_PIN12_Pos 12 /*!< Interrupt enable for pin 12 */ #define GPIO_INTENSET_PIN13_Pos 13 /*!< Interrupt enable for pin 13 */ #define GPIO_INTENSET_PIN14_Pos 14 /*!< Interrupt enable for pin 14 */ #define GPIO_INTENSET_PIN15_Pos 15 /*!< Interrupt enable for pin 15 */ /* Bit field masks: */ #define GPIO_INTENSET_PIN0_Msk 0x00000001UL /*!< Interrupt enable for pin 0 */ #define GPIO_INTENSET_PIN1_Msk 0x00000002UL /*!< Interrupt enable for pin 1 */ #define GPIO_INTENSET_PIN2_Msk 0x00000004UL /*!< Interrupt enable for pin 2 */ #define GPIO_INTENSET_PIN3_Msk 0x00000008UL /*!< Interrupt enable for pin 3 */ #define GPIO_INTENSET_PIN4_Msk 0x00000010UL /*!< Interrupt enable for pin 4 */ #define GPIO_INTENSET_PIN5_Msk 0x00000020UL /*!< Interrupt enable for pin 5 */ #define GPIO_INTENSET_PIN6_Msk 0x00000040UL /*!< Interrupt enable for pin 6 */ #define GPIO_INTENSET_PIN7_Msk 0x00000080UL /*!< Interrupt enable for pin 7 */ #define GPIO_INTENSET_PIN8_Msk 0x00000100UL /*!< Interrupt enable for pin 8 */ #define GPIO_INTENSET_PIN9_Msk 0x00000200UL /*!< Interrupt enable for pin 9 */ #define GPIO_INTENSET_PIN10_Msk 0x00000400UL /*!< Interrupt enable for pin 10 */ #define GPIO_INTENSET_PIN11_Msk 0x00000800UL /*!< Interrupt enable for pin 11 */ #define GPIO_INTENSET_PIN12_Msk 0x00001000UL /*!< Interrupt enable for pin 12 */ #define GPIO_INTENSET_PIN13_Msk 0x00002000UL /*!< Interrupt enable for pin 13 */ #define GPIO_INTENSET_PIN14_Msk 0x00004000UL /*!< Interrupt enable for pin 14 */ #define GPIO_INTENSET_PIN15_Msk 0x00008000UL /*!< Interrupt enable for pin 15 */ /*-- INTENCLR: Interrupt disable register --------------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Interrupt disable for pin 0 */ uint32_t PIN1 :1; /*!< Interrupt disable for pin 1 */ uint32_t PIN2 :1; /*!< Interrupt disable for pin 2 */ uint32_t PIN3 :1; /*!< Interrupt disable for pin 3 */ uint32_t PIN4 :1; /*!< Interrupt disable for pin 4 */ uint32_t PIN5 :1; /*!< Interrupt disable for pin 5 */ uint32_t PIN6 :1; /*!< Interrupt disable for pin 6 */ uint32_t PIN7 :1; /*!< Interrupt disable for pin 7 */ uint32_t PIN8 :1; /*!< Interrupt disable for pin 8 */ uint32_t PIN9 :1; /*!< Interrupt disable for pin 9 */ uint32_t PIN10 :1; /*!< Interrupt disable for pin 10 */ uint32_t PIN11 :1; /*!< Interrupt disable for pin 11 */ uint32_t PIN12 :1; /*!< Interrupt disable for pin 12 */ uint32_t PIN13 :1; /*!< Interrupt disable for pin 13 */ uint32_t PIN14 :1; /*!< Interrupt disable for pin 14 */ uint32_t PIN15 :1; /*!< Interrupt disable for pin 15 */ } _GPIO_INTENCLR_bits; /* Bit field positions: */ #define GPIO_INTENCLR_PIN0_Pos 0 /*!< Interrupt disable for pin 0 */ #define GPIO_INTENCLR_PIN1_Pos 1 /*!< Interrupt disable for pin 1 */ #define GPIO_INTENCLR_PIN2_Pos 2 /*!< Interrupt disable for pin 2 */ #define GPIO_INTENCLR_PIN3_Pos 3 /*!< Interrupt disable for pin 3 */ #define GPIO_INTENCLR_PIN4_Pos 4 /*!< Interrupt disable for pin 4 */ #define GPIO_INTENCLR_PIN5_Pos 5 /*!< Interrupt disable for pin 5 */ #define GPIO_INTENCLR_PIN6_Pos 6 /*!< Interrupt disable for pin 6 */ #define GPIO_INTENCLR_PIN7_Pos 7 /*!< Interrupt disable for pin 7 */ #define GPIO_INTENCLR_PIN8_Pos 8 /*!< Interrupt disable for pin 8 */ #define GPIO_INTENCLR_PIN9_Pos 9 /*!< Interrupt disable for pin 9 */ #define GPIO_INTENCLR_PIN10_Pos 10 /*!< Interrupt disable for pin 10 */ #define GPIO_INTENCLR_PIN11_Pos 11 /*!< Interrupt disable for pin 11 */ #define GPIO_INTENCLR_PIN12_Pos 12 /*!< Interrupt disable for pin 12 */ #define GPIO_INTENCLR_PIN13_Pos 13 /*!< Interrupt disable for pin 13 */ #define GPIO_INTENCLR_PIN14_Pos 14 /*!< Interrupt disable for pin 14 */ #define GPIO_INTENCLR_PIN15_Pos 15 /*!< Interrupt disable for pin 15 */ /* Bit field masks: */ #define GPIO_INTENCLR_PIN0_Msk 0x00000001UL /*!< Interrupt disable for pin 0 */ #define GPIO_INTENCLR_PIN1_Msk 0x00000002UL /*!< Interrupt disable for pin 1 */ #define GPIO_INTENCLR_PIN2_Msk 0x00000004UL /*!< Interrupt disable for pin 2 */ #define GPIO_INTENCLR_PIN3_Msk 0x00000008UL /*!< Interrupt disable for pin 3 */ #define GPIO_INTENCLR_PIN4_Msk 0x00000010UL /*!< Interrupt disable for pin 4 */ #define GPIO_INTENCLR_PIN5_Msk 0x00000020UL /*!< Interrupt disable for pin 5 */ #define GPIO_INTENCLR_PIN6_Msk 0x00000040UL /*!< Interrupt disable for pin 6 */ #define GPIO_INTENCLR_PIN7_Msk 0x00000080UL /*!< Interrupt disable for pin 7 */ #define GPIO_INTENCLR_PIN8_Msk 0x00000100UL /*!< Interrupt disable for pin 8 */ #define GPIO_INTENCLR_PIN9_Msk 0x00000200UL /*!< Interrupt disable for pin 9 */ #define GPIO_INTENCLR_PIN10_Msk 0x00000400UL /*!< Interrupt disable for pin 10 */ #define GPIO_INTENCLR_PIN11_Msk 0x00000800UL /*!< Interrupt disable for pin 11 */ #define GPIO_INTENCLR_PIN12_Msk 0x00001000UL /*!< Interrupt disable for pin 12 */ #define GPIO_INTENCLR_PIN13_Msk 0x00002000UL /*!< Interrupt disable for pin 13 */ #define GPIO_INTENCLR_PIN14_Msk 0x00004000UL /*!< Interrupt disable for pin 14 */ #define GPIO_INTENCLR_PIN15_Msk 0x00008000UL /*!< Interrupt disable for pin 15 */ /*-- INTTYPESET: Interrupt type set register -----------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Interrupt type set for pin 0 */ uint32_t PIN1 :1; /*!< Interrupt type set for pin 1 */ uint32_t PIN2 :1; /*!< Interrupt type set for pin 2 */ uint32_t PIN3 :1; /*!< Interrupt type set for pin 3 */ uint32_t PIN4 :1; /*!< Interrupt type set for pin 4 */ uint32_t PIN5 :1; /*!< Interrupt type set for pin 5 */ uint32_t PIN6 :1; /*!< Interrupt type set for pin 6 */ uint32_t PIN7 :1; /*!< Interrupt type set for pin 7 */ uint32_t PIN8 :1; /*!< Interrupt type set for pin 8 */ uint32_t PIN9 :1; /*!< Interrupt type set for pin 9 */ uint32_t PIN10 :1; /*!< Interrupt type set for pin 10 */ uint32_t PIN11 :1; /*!< Interrupt type set for pin 11 */ uint32_t PIN12 :1; /*!< Interrupt type set for pin 12 */ uint32_t PIN13 :1; /*!< Interrupt type set for pin 13 */ uint32_t PIN14 :1; /*!< Interrupt type set for pin 14 */ uint32_t PIN15 :1; /*!< Interrupt type set for pin 15 */ } _GPIO_INTTYPESET_bits; /* Bit field positions: */ #define GPIO_INTTYPESET_PIN0_Pos 0 /*!< Interrupt type set for pin 0 */ #define GPIO_INTTYPESET_PIN1_Pos 1 /*!< Interrupt type set for pin 1 */ #define GPIO_INTTYPESET_PIN2_Pos 2 /*!< Interrupt type set for pin 2 */ #define GPIO_INTTYPESET_PIN3_Pos 3 /*!< Interrupt type set for pin 3 */ #define GPIO_INTTYPESET_PIN4_Pos 4 /*!< Interrupt type set for pin 4 */ #define GPIO_INTTYPESET_PIN5_Pos 5 /*!< Interrupt type set for pin 5 */ #define GPIO_INTTYPESET_PIN6_Pos 6 /*!< Interrupt type set for pin 6 */ #define GPIO_INTTYPESET_PIN7_Pos 7 /*!< Interrupt type set for pin 7 */ #define GPIO_INTTYPESET_PIN8_Pos 8 /*!< Interrupt type set for pin 8 */ #define GPIO_INTTYPESET_PIN9_Pos 9 /*!< Interrupt type set for pin 9 */ #define GPIO_INTTYPESET_PIN10_Pos 10 /*!< Interrupt type set for pin 10 */ #define GPIO_INTTYPESET_PIN11_Pos 11 /*!< Interrupt type set for pin 11 */ #define GPIO_INTTYPESET_PIN12_Pos 12 /*!< Interrupt type set for pin 12 */ #define GPIO_INTTYPESET_PIN13_Pos 13 /*!< Interrupt type set for pin 13 */ #define GPIO_INTTYPESET_PIN14_Pos 14 /*!< Interrupt type set for pin 14 */ #define GPIO_INTTYPESET_PIN15_Pos 15 /*!< Interrupt type set for pin 15 */ /* Bit field masks: */ #define GPIO_INTTYPESET_PIN0_Msk 0x00000001UL /*!< Interrupt type set for pin 0 */ #define GPIO_INTTYPESET_PIN1_Msk 0x00000002UL /*!< Interrupt type set for pin 1 */ #define GPIO_INTTYPESET_PIN2_Msk 0x00000004UL /*!< Interrupt type set for pin 2 */ #define GPIO_INTTYPESET_PIN3_Msk 0x00000008UL /*!< Interrupt type set for pin 3 */ #define GPIO_INTTYPESET_PIN4_Msk 0x00000010UL /*!< Interrupt type set for pin 4 */ #define GPIO_INTTYPESET_PIN5_Msk 0x00000020UL /*!< Interrupt type set for pin 5 */ #define GPIO_INTTYPESET_PIN6_Msk 0x00000040UL /*!< Interrupt type set for pin 6 */ #define GPIO_INTTYPESET_PIN7_Msk 0x00000080UL /*!< Interrupt type set for pin 7 */ #define GPIO_INTTYPESET_PIN8_Msk 0x00000100UL /*!< Interrupt type set for pin 8 */ #define GPIO_INTTYPESET_PIN9_Msk 0x00000200UL /*!< Interrupt type set for pin 9 */ #define GPIO_INTTYPESET_PIN10_Msk 0x00000400UL /*!< Interrupt type set for pin 10 */ #define GPIO_INTTYPESET_PIN11_Msk 0x00000800UL /*!< Interrupt type set for pin 11 */ #define GPIO_INTTYPESET_PIN12_Msk 0x00001000UL /*!< Interrupt type set for pin 12 */ #define GPIO_INTTYPESET_PIN13_Msk 0x00002000UL /*!< Interrupt type set for pin 13 */ #define GPIO_INTTYPESET_PIN14_Msk 0x00004000UL /*!< Interrupt type set for pin 14 */ #define GPIO_INTTYPESET_PIN15_Msk 0x00008000UL /*!< Interrupt type set for pin 15 */ /*-- INTTYPECLR: Interrupt type clear register ---------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Interrupt type clear for pin 0 */ uint32_t PIN1 :1; /*!< Interrupt type clear for pin 1 */ uint32_t PIN2 :1; /*!< Interrupt type clear for pin 2 */ uint32_t PIN3 :1; /*!< Interrupt type clear for pin 3 */ uint32_t PIN4 :1; /*!< Interrupt type clear for pin 4 */ uint32_t PIN5 :1; /*!< Interrupt type clear for pin 5 */ uint32_t PIN6 :1; /*!< Interrupt type clear for pin 6 */ uint32_t PIN7 :1; /*!< Interrupt type clear for pin 7 */ uint32_t PIN8 :1; /*!< Interrupt type clear for pin 8 */ uint32_t PIN9 :1; /*!< Interrupt type clear for pin 9 */ uint32_t PIN10 :1; /*!< Interrupt type clear for pin 10 */ uint32_t PIN11 :1; /*!< Interrupt type clear for pin 11 */ uint32_t PIN12 :1; /*!< Interrupt type clear for pin 12 */ uint32_t PIN13 :1; /*!< Interrupt type clear for pin 13 */ uint32_t PIN14 :1; /*!< Interrupt type clear for pin 14 */ uint32_t PIN15 :1; /*!< Interrupt type clear for pin 15 */ } _GPIO_INTTYPECLR_bits; /* Bit field positions: */ #define GPIO_INTTYPECLR_PIN0_Pos 0 /*!< Interrupt type clear for pin 0 */ #define GPIO_INTTYPECLR_PIN1_Pos 1 /*!< Interrupt type clear for pin 1 */ #define GPIO_INTTYPECLR_PIN2_Pos 2 /*!< Interrupt type clear for pin 2 */ #define GPIO_INTTYPECLR_PIN3_Pos 3 /*!< Interrupt type clear for pin 3 */ #define GPIO_INTTYPECLR_PIN4_Pos 4 /*!< Interrupt type clear for pin 4 */ #define GPIO_INTTYPECLR_PIN5_Pos 5 /*!< Interrupt type clear for pin 5 */ #define GPIO_INTTYPECLR_PIN6_Pos 6 /*!< Interrupt type clear for pin 6 */ #define GPIO_INTTYPECLR_PIN7_Pos 7 /*!< Interrupt type clear for pin 7 */ #define GPIO_INTTYPECLR_PIN8_Pos 8 /*!< Interrupt type clear for pin 8 */ #define GPIO_INTTYPECLR_PIN9_Pos 9 /*!< Interrupt type clear for pin 9 */ #define GPIO_INTTYPECLR_PIN10_Pos 10 /*!< Interrupt type clear for pin 10 */ #define GPIO_INTTYPECLR_PIN11_Pos 11 /*!< Interrupt type clear for pin 11 */ #define GPIO_INTTYPECLR_PIN12_Pos 12 /*!< Interrupt type clear for pin 12 */ #define GPIO_INTTYPECLR_PIN13_Pos 13 /*!< Interrupt type clear for pin 13 */ #define GPIO_INTTYPECLR_PIN14_Pos 14 /*!< Interrupt type clear for pin 14 */ #define GPIO_INTTYPECLR_PIN15_Pos 15 /*!< Interrupt type clear for pin 15 */ /* Bit field masks: */ #define GPIO_INTTYPECLR_PIN0_Msk 0x00000001UL /*!< Interrupt type clear for pin 0 */ #define GPIO_INTTYPECLR_PIN1_Msk 0x00000002UL /*!< Interrupt type clear for pin 1 */ #define GPIO_INTTYPECLR_PIN2_Msk 0x00000004UL /*!< Interrupt type clear for pin 2 */ #define GPIO_INTTYPECLR_PIN3_Msk 0x00000008UL /*!< Interrupt type clear for pin 3 */ #define GPIO_INTTYPECLR_PIN4_Msk 0x00000010UL /*!< Interrupt type clear for pin 4 */ #define GPIO_INTTYPECLR_PIN5_Msk 0x00000020UL /*!< Interrupt type clear for pin 5 */ #define GPIO_INTTYPECLR_PIN6_Msk 0x00000040UL /*!< Interrupt type clear for pin 6 */ #define GPIO_INTTYPECLR_PIN7_Msk 0x00000080UL /*!< Interrupt type clear for pin 7 */ #define GPIO_INTTYPECLR_PIN8_Msk 0x00000100UL /*!< Interrupt type clear for pin 8 */ #define GPIO_INTTYPECLR_PIN9_Msk 0x00000200UL /*!< Interrupt type clear for pin 9 */ #define GPIO_INTTYPECLR_PIN10_Msk 0x00000400UL /*!< Interrupt type clear for pin 10 */ #define GPIO_INTTYPECLR_PIN11_Msk 0x00000800UL /*!< Interrupt type clear for pin 11 */ #define GPIO_INTTYPECLR_PIN12_Msk 0x00001000UL /*!< Interrupt type clear for pin 12 */ #define GPIO_INTTYPECLR_PIN13_Msk 0x00002000UL /*!< Interrupt type clear for pin 13 */ #define GPIO_INTTYPECLR_PIN14_Msk 0x00004000UL /*!< Interrupt type clear for pin 14 */ #define GPIO_INTTYPECLR_PIN15_Msk 0x00008000UL /*!< Interrupt type clear for pin 15 */ /*-- INTPOLSET: Interrupt polarity set register --------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Interrupt polarity set for pin 0 */ uint32_t PIN1 :1; /*!< Interrupt polarity set for pin 1 */ uint32_t PIN2 :1; /*!< Interrupt polarity set for pin 2 */ uint32_t PIN3 :1; /*!< Interrupt polarity set for pin 3 */ uint32_t PIN4 :1; /*!< Interrupt polarity set for pin 4 */ uint32_t PIN5 :1; /*!< Interrupt polarity set for pin 5 */ uint32_t PIN6 :1; /*!< Interrupt polarity set for pin 6 */ uint32_t PIN7 :1; /*!< Interrupt polarity set for pin 7 */ uint32_t PIN8 :1; /*!< Interrupt polarity set for pin 8 */ uint32_t PIN9 :1; /*!< Interrupt polarity set for pin 9 */ uint32_t PIN10 :1; /*!< Interrupt polarity set for pin 10 */ uint32_t PIN11 :1; /*!< Interrupt polarity set for pin 11 */ uint32_t PIN12 :1; /*!< Interrupt polarity set for pin 12 */ uint32_t PIN13 :1; /*!< Interrupt polarity set for pin 13 */ uint32_t PIN14 :1; /*!< Interrupt polarity set for pin 14 */ uint32_t PIN15 :1; /*!< Interrupt polarity set for pin 15 */ } _GPIO_INTPOLSET_bits; /* Bit field positions: */ #define GPIO_INTPOLSET_PIN0_Pos 0 /*!< Interrupt polarity set for pin 0 */ #define GPIO_INTPOLSET_PIN1_Pos 1 /*!< Interrupt polarity set for pin 1 */ #define GPIO_INTPOLSET_PIN2_Pos 2 /*!< Interrupt polarity set for pin 2 */ #define GPIO_INTPOLSET_PIN3_Pos 3 /*!< Interrupt polarity set for pin 3 */ #define GPIO_INTPOLSET_PIN4_Pos 4 /*!< Interrupt polarity set for pin 4 */ #define GPIO_INTPOLSET_PIN5_Pos 5 /*!< Interrupt polarity set for pin 5 */ #define GPIO_INTPOLSET_PIN6_Pos 6 /*!< Interrupt polarity set for pin 6 */ #define GPIO_INTPOLSET_PIN7_Pos 7 /*!< Interrupt polarity set for pin 7 */ #define GPIO_INTPOLSET_PIN8_Pos 8 /*!< Interrupt polarity set for pin 8 */ #define GPIO_INTPOLSET_PIN9_Pos 9 /*!< Interrupt polarity set for pin 9 */ #define GPIO_INTPOLSET_PIN10_Pos 10 /*!< Interrupt polarity set for pin 10 */ #define GPIO_INTPOLSET_PIN11_Pos 11 /*!< Interrupt polarity set for pin 11 */ #define GPIO_INTPOLSET_PIN12_Pos 12 /*!< Interrupt polarity set for pin 12 */ #define GPIO_INTPOLSET_PIN13_Pos 13 /*!< Interrupt polarity set for pin 13 */ #define GPIO_INTPOLSET_PIN14_Pos 14 /*!< Interrupt polarity set for pin 14 */ #define GPIO_INTPOLSET_PIN15_Pos 15 /*!< Interrupt polarity set for pin 15 */ /* Bit field masks: */ #define GPIO_INTPOLSET_PIN0_Msk 0x00000001UL /*!< Interrupt polarity set for pin 0 */ #define GPIO_INTPOLSET_PIN1_Msk 0x00000002UL /*!< Interrupt polarity set for pin 1 */ #define GPIO_INTPOLSET_PIN2_Msk 0x00000004UL /*!< Interrupt polarity set for pin 2 */ #define GPIO_INTPOLSET_PIN3_Msk 0x00000008UL /*!< Interrupt polarity set for pin 3 */ #define GPIO_INTPOLSET_PIN4_Msk 0x00000010UL /*!< Interrupt polarity set for pin 4 */ #define GPIO_INTPOLSET_PIN5_Msk 0x00000020UL /*!< Interrupt polarity set for pin 5 */ #define GPIO_INTPOLSET_PIN6_Msk 0x00000040UL /*!< Interrupt polarity set for pin 6 */ #define GPIO_INTPOLSET_PIN7_Msk 0x00000080UL /*!< Interrupt polarity set for pin 7 */ #define GPIO_INTPOLSET_PIN8_Msk 0x00000100UL /*!< Interrupt polarity set for pin 8 */ #define GPIO_INTPOLSET_PIN9_Msk 0x00000200UL /*!< Interrupt polarity set for pin 9 */ #define GPIO_INTPOLSET_PIN10_Msk 0x00000400UL /*!< Interrupt polarity set for pin 10 */ #define GPIO_INTPOLSET_PIN11_Msk 0x00000800UL /*!< Interrupt polarity set for pin 11 */ #define GPIO_INTPOLSET_PIN12_Msk 0x00001000UL /*!< Interrupt polarity set for pin 12 */ #define GPIO_INTPOLSET_PIN13_Msk 0x00002000UL /*!< Interrupt polarity set for pin 13 */ #define GPIO_INTPOLSET_PIN14_Msk 0x00004000UL /*!< Interrupt polarity set for pin 14 */ #define GPIO_INTPOLSET_PIN15_Msk 0x00008000UL /*!< Interrupt polarity set for pin 15 */ /*-- INTPOLCLR: Interrupt polarity clear register ------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Interrupt polarity clear for pin 0 */ uint32_t PIN1 :1; /*!< Interrupt polarity clear for pin 1 */ uint32_t PIN2 :1; /*!< Interrupt polarity clear for pin 2 */ uint32_t PIN3 :1; /*!< Interrupt polarity clear for pin 3 */ uint32_t PIN4 :1; /*!< Interrupt polarity clear for pin 4 */ uint32_t PIN5 :1; /*!< Interrupt polarity clear for pin 5 */ uint32_t PIN6 :1; /*!< Interrupt polarity clear for pin 6 */ uint32_t PIN7 :1; /*!< Interrupt polarity clear for pin 7 */ uint32_t PIN8 :1; /*!< Interrupt polarity clear for pin 8 */ uint32_t PIN9 :1; /*!< Interrupt polarity clear for pin 9 */ uint32_t PIN10 :1; /*!< Interrupt polarity clear for pin 10 */ uint32_t PIN11 :1; /*!< Interrupt polarity clear for pin 11 */ uint32_t PIN12 :1; /*!< Interrupt polarity clear for pin 12 */ uint32_t PIN13 :1; /*!< Interrupt polarity clear for pin 13 */ uint32_t PIN14 :1; /*!< Interrupt polarity clear for pin 14 */ uint32_t PIN15 :1; /*!< Interrupt polarity clear for pin 15 */ } _GPIO_INTPOLCLR_bits; /* Bit field positions: */ #define GPIO_INTPOLCLR_PIN0_Pos 0 /*!< Interrupt polarity clear for pin 0 */ #define GPIO_INTPOLCLR_PIN1_Pos 1 /*!< Interrupt polarity clear for pin 1 */ #define GPIO_INTPOLCLR_PIN2_Pos 2 /*!< Interrupt polarity clear for pin 2 */ #define GPIO_INTPOLCLR_PIN3_Pos 3 /*!< Interrupt polarity clear for pin 3 */ #define GPIO_INTPOLCLR_PIN4_Pos 4 /*!< Interrupt polarity clear for pin 4 */ #define GPIO_INTPOLCLR_PIN5_Pos 5 /*!< Interrupt polarity clear for pin 5 */ #define GPIO_INTPOLCLR_PIN6_Pos 6 /*!< Interrupt polarity clear for pin 6 */ #define GPIO_INTPOLCLR_PIN7_Pos 7 /*!< Interrupt polarity clear for pin 7 */ #define GPIO_INTPOLCLR_PIN8_Pos 8 /*!< Interrupt polarity clear for pin 8 */ #define GPIO_INTPOLCLR_PIN9_Pos 9 /*!< Interrupt polarity clear for pin 9 */ #define GPIO_INTPOLCLR_PIN10_Pos 10 /*!< Interrupt polarity clear for pin 10 */ #define GPIO_INTPOLCLR_PIN11_Pos 11 /*!< Interrupt polarity clear for pin 11 */ #define GPIO_INTPOLCLR_PIN12_Pos 12 /*!< Interrupt polarity clear for pin 12 */ #define GPIO_INTPOLCLR_PIN13_Pos 13 /*!< Interrupt polarity clear for pin 13 */ #define GPIO_INTPOLCLR_PIN14_Pos 14 /*!< Interrupt polarity clear for pin 14 */ #define GPIO_INTPOLCLR_PIN15_Pos 15 /*!< Interrupt polarity clear for pin 15 */ /* Bit field masks: */ #define GPIO_INTPOLCLR_PIN0_Msk 0x00000001UL /*!< Interrupt polarity clear for pin 0 */ #define GPIO_INTPOLCLR_PIN1_Msk 0x00000002UL /*!< Interrupt polarity clear for pin 1 */ #define GPIO_INTPOLCLR_PIN2_Msk 0x00000004UL /*!< Interrupt polarity clear for pin 2 */ #define GPIO_INTPOLCLR_PIN3_Msk 0x00000008UL /*!< Interrupt polarity clear for pin 3 */ #define GPIO_INTPOLCLR_PIN4_Msk 0x00000010UL /*!< Interrupt polarity clear for pin 4 */ #define GPIO_INTPOLCLR_PIN5_Msk 0x00000020UL /*!< Interrupt polarity clear for pin 5 */ #define GPIO_INTPOLCLR_PIN6_Msk 0x00000040UL /*!< Interrupt polarity clear for pin 6 */ #define GPIO_INTPOLCLR_PIN7_Msk 0x00000080UL /*!< Interrupt polarity clear for pin 7 */ #define GPIO_INTPOLCLR_PIN8_Msk 0x00000100UL /*!< Interrupt polarity clear for pin 8 */ #define GPIO_INTPOLCLR_PIN9_Msk 0x00000200UL /*!< Interrupt polarity clear for pin 9 */ #define GPIO_INTPOLCLR_PIN10_Msk 0x00000400UL /*!< Interrupt polarity clear for pin 10 */ #define GPIO_INTPOLCLR_PIN11_Msk 0x00000800UL /*!< Interrupt polarity clear for pin 11 */ #define GPIO_INTPOLCLR_PIN12_Msk 0x00001000UL /*!< Interrupt polarity clear for pin 12 */ #define GPIO_INTPOLCLR_PIN13_Msk 0x00002000UL /*!< Interrupt polarity clear for pin 13 */ #define GPIO_INTPOLCLR_PIN14_Msk 0x00004000UL /*!< Interrupt polarity clear for pin 14 */ #define GPIO_INTPOLCLR_PIN15_Msk 0x00008000UL /*!< Interrupt polarity clear for pin 15 */ /*-- INTEDGESET: Interrupt every edge set register -----------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Interrupt every edge set for pin 0 */ uint32_t PIN1 :1; /*!< Interrupt every edge set for pin 1 */ uint32_t PIN2 :1; /*!< Interrupt every edge set for pin 2 */ uint32_t PIN3 :1; /*!< Interrupt every edge set for pin 3 */ uint32_t PIN4 :1; /*!< Interrupt every edge set for pin 4 */ uint32_t PIN5 :1; /*!< Interrupt every edge set for pin 5 */ uint32_t PIN6 :1; /*!< Interrupt every edge set for pin 6 */ uint32_t PIN7 :1; /*!< Interrupt every edge set for pin 7 */ uint32_t PIN8 :1; /*!< Interrupt every edge set for pin 8 */ uint32_t PIN9 :1; /*!< Interrupt every edge set for pin 9 */ uint32_t PIN10 :1; /*!< Interrupt every edge set for pin 10 */ uint32_t PIN11 :1; /*!< Interrupt every edge set for pin 11 */ uint32_t PIN12 :1; /*!< Interrupt every edge set for pin 12 */ uint32_t PIN13 :1; /*!< Interrupt every edge set for pin 13 */ uint32_t PIN14 :1; /*!< Interrupt every edge set for pin 14 */ uint32_t PIN15 :1; /*!< Interrupt every edge set for pin 15 */ } _GPIO_INTEDGESET_bits; /* Bit field positions: */ #define GPIO_INTEDGESET_PIN0_Pos 0 /*!< Interrupt every edge set for pin 0 */ #define GPIO_INTEDGESET_PIN1_Pos 1 /*!< Interrupt every edge set for pin 1 */ #define GPIO_INTEDGESET_PIN2_Pos 2 /*!< Interrupt every edge set for pin 2 */ #define GPIO_INTEDGESET_PIN3_Pos 3 /*!< Interrupt every edge set for pin 3 */ #define GPIO_INTEDGESET_PIN4_Pos 4 /*!< Interrupt every edge set for pin 4 */ #define GPIO_INTEDGESET_PIN5_Pos 5 /*!< Interrupt every edge set for pin 5 */ #define GPIO_INTEDGESET_PIN6_Pos 6 /*!< Interrupt every edge set for pin 6 */ #define GPIO_INTEDGESET_PIN7_Pos 7 /*!< Interrupt every edge set for pin 7 */ #define GPIO_INTEDGESET_PIN8_Pos 8 /*!< Interrupt every edge set for pin 8 */ #define GPIO_INTEDGESET_PIN9_Pos 9 /*!< Interrupt every edge set for pin 9 */ #define GPIO_INTEDGESET_PIN10_Pos 10 /*!< Interrupt every edge set for pin 10 */ #define GPIO_INTEDGESET_PIN11_Pos 11 /*!< Interrupt every edge set for pin 11 */ #define GPIO_INTEDGESET_PIN12_Pos 12 /*!< Interrupt every edge set for pin 12 */ #define GPIO_INTEDGESET_PIN13_Pos 13 /*!< Interrupt every edge set for pin 13 */ #define GPIO_INTEDGESET_PIN14_Pos 14 /*!< Interrupt every edge set for pin 14 */ #define GPIO_INTEDGESET_PIN15_Pos 15 /*!< Interrupt every edge set for pin 15 */ /* Bit field masks: */ #define GPIO_INTEDGESET_PIN0_Msk 0x00000001UL /*!< Interrupt every edge set for pin 0 */ #define GPIO_INTEDGESET_PIN1_Msk 0x00000002UL /*!< Interrupt every edge set for pin 1 */ #define GPIO_INTEDGESET_PIN2_Msk 0x00000004UL /*!< Interrupt every edge set for pin 2 */ #define GPIO_INTEDGESET_PIN3_Msk 0x00000008UL /*!< Interrupt every edge set for pin 3 */ #define GPIO_INTEDGESET_PIN4_Msk 0x00000010UL /*!< Interrupt every edge set for pin 4 */ #define GPIO_INTEDGESET_PIN5_Msk 0x00000020UL /*!< Interrupt every edge set for pin 5 */ #define GPIO_INTEDGESET_PIN6_Msk 0x00000040UL /*!< Interrupt every edge set for pin 6 */ #define GPIO_INTEDGESET_PIN7_Msk 0x00000080UL /*!< Interrupt every edge set for pin 7 */ #define GPIO_INTEDGESET_PIN8_Msk 0x00000100UL /*!< Interrupt every edge set for pin 8 */ #define GPIO_INTEDGESET_PIN9_Msk 0x00000200UL /*!< Interrupt every edge set for pin 9 */ #define GPIO_INTEDGESET_PIN10_Msk 0x00000400UL /*!< Interrupt every edge set for pin 10 */ #define GPIO_INTEDGESET_PIN11_Msk 0x00000800UL /*!< Interrupt every edge set for pin 11 */ #define GPIO_INTEDGESET_PIN12_Msk 0x00001000UL /*!< Interrupt every edge set for pin 12 */ #define GPIO_INTEDGESET_PIN13_Msk 0x00002000UL /*!< Interrupt every edge set for pin 13 */ #define GPIO_INTEDGESET_PIN14_Msk 0x00004000UL /*!< Interrupt every edge set for pin 14 */ #define GPIO_INTEDGESET_PIN15_Msk 0x00008000UL /*!< Interrupt every edge set for pin 15 */ /*-- INTEDGECLR: Interrupt every edge clear register ---------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Interrupt every edge clear for pin 0 */ uint32_t PIN1 :1; /*!< Interrupt every edge clear for pin 1 */ uint32_t PIN2 :1; /*!< Interrupt every edge clear for pin 2 */ uint32_t PIN3 :1; /*!< Interrupt every edge clear for pin 3 */ uint32_t PIN4 :1; /*!< Interrupt every edge clear for pin 4 */ uint32_t PIN5 :1; /*!< Interrupt every edge clear for pin 5 */ uint32_t PIN6 :1; /*!< Interrupt every edge clear for pin 6 */ uint32_t PIN7 :1; /*!< Interrupt every edge clear for pin 7 */ uint32_t PIN8 :1; /*!< Interrupt every edge clear for pin 8 */ uint32_t PIN9 :1; /*!< Interrupt every edge clear for pin 9 */ uint32_t PIN10 :1; /*!< Interrupt every edge clear for pin 10 */ uint32_t PIN11 :1; /*!< Interrupt every edge clear for pin 11 */ uint32_t PIN12 :1; /*!< Interrupt every edge clear for pin 12 */ uint32_t PIN13 :1; /*!< Interrupt every edge clear for pin 13 */ uint32_t PIN14 :1; /*!< Interrupt every edge clear for pin 14 */ uint32_t PIN15 :1; /*!< Interrupt every edge clear for pin 15 */ } _GPIO_INTEDGECLR_bits; /* Bit field positions: */ #define GPIO_INTEDGECLR_PIN0_Pos 0 /*!< Interrupt every edge clear for pin 0 */ #define GPIO_INTEDGECLR_PIN1_Pos 1 /*!< Interrupt every edge clear for pin 1 */ #define GPIO_INTEDGECLR_PIN2_Pos 2 /*!< Interrupt every edge clear for pin 2 */ #define GPIO_INTEDGECLR_PIN3_Pos 3 /*!< Interrupt every edge clear for pin 3 */ #define GPIO_INTEDGECLR_PIN4_Pos 4 /*!< Interrupt every edge clear for pin 4 */ #define GPIO_INTEDGECLR_PIN5_Pos 5 /*!< Interrupt every edge clear for pin 5 */ #define GPIO_INTEDGECLR_PIN6_Pos 6 /*!< Interrupt every edge clear for pin 6 */ #define GPIO_INTEDGECLR_PIN7_Pos 7 /*!< Interrupt every edge clear for pin 7 */ #define GPIO_INTEDGECLR_PIN8_Pos 8 /*!< Interrupt every edge clear for pin 8 */ #define GPIO_INTEDGECLR_PIN9_Pos 9 /*!< Interrupt every edge clear for pin 9 */ #define GPIO_INTEDGECLR_PIN10_Pos 10 /*!< Interrupt every edge clear for pin 10 */ #define GPIO_INTEDGECLR_PIN11_Pos 11 /*!< Interrupt every edge clear for pin 11 */ #define GPIO_INTEDGECLR_PIN12_Pos 12 /*!< Interrupt every edge clear for pin 12 */ #define GPIO_INTEDGECLR_PIN13_Pos 13 /*!< Interrupt every edge clear for pin 13 */ #define GPIO_INTEDGECLR_PIN14_Pos 14 /*!< Interrupt every edge clear for pin 14 */ #define GPIO_INTEDGECLR_PIN15_Pos 15 /*!< Interrupt every edge clear for pin 15 */ /* Bit field masks: */ #define GPIO_INTEDGECLR_PIN0_Msk 0x00000001UL /*!< Interrupt every edge clear for pin 0 */ #define GPIO_INTEDGECLR_PIN1_Msk 0x00000002UL /*!< Interrupt every edge clear for pin 1 */ #define GPIO_INTEDGECLR_PIN2_Msk 0x00000004UL /*!< Interrupt every edge clear for pin 2 */ #define GPIO_INTEDGECLR_PIN3_Msk 0x00000008UL /*!< Interrupt every edge clear for pin 3 */ #define GPIO_INTEDGECLR_PIN4_Msk 0x00000010UL /*!< Interrupt every edge clear for pin 4 */ #define GPIO_INTEDGECLR_PIN5_Msk 0x00000020UL /*!< Interrupt every edge clear for pin 5 */ #define GPIO_INTEDGECLR_PIN6_Msk 0x00000040UL /*!< Interrupt every edge clear for pin 6 */ #define GPIO_INTEDGECLR_PIN7_Msk 0x00000080UL /*!< Interrupt every edge clear for pin 7 */ #define GPIO_INTEDGECLR_PIN8_Msk 0x00000100UL /*!< Interrupt every edge clear for pin 8 */ #define GPIO_INTEDGECLR_PIN9_Msk 0x00000200UL /*!< Interrupt every edge clear for pin 9 */ #define GPIO_INTEDGECLR_PIN10_Msk 0x00000400UL /*!< Interrupt every edge clear for pin 10 */ #define GPIO_INTEDGECLR_PIN11_Msk 0x00000800UL /*!< Interrupt every edge clear for pin 11 */ #define GPIO_INTEDGECLR_PIN12_Msk 0x00001000UL /*!< Interrupt every edge clear for pin 12 */ #define GPIO_INTEDGECLR_PIN13_Msk 0x00002000UL /*!< Interrupt every edge clear for pin 13 */ #define GPIO_INTEDGECLR_PIN14_Msk 0x00004000UL /*!< Interrupt every edge clear for pin 14 */ #define GPIO_INTEDGECLR_PIN15_Msk 0x00008000UL /*!< Interrupt every edge clear for pin 15 */ /*-- INTSTATUS: Interrupt status -----------------------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Interrupt status of pin 0 */ uint32_t PIN1 :1; /*!< Interrupt status of pin 1 */ uint32_t PIN2 :1; /*!< Interrupt status of pin 2 */ uint32_t PIN3 :1; /*!< Interrupt status of pin 3 */ uint32_t PIN4 :1; /*!< Interrupt status of pin 4 */ uint32_t PIN5 :1; /*!< Interrupt status of pin 5 */ uint32_t PIN6 :1; /*!< Interrupt status of pin 6 */ uint32_t PIN7 :1; /*!< Interrupt status of pin 7 */ uint32_t PIN8 :1; /*!< Interrupt status of pin 8 */ uint32_t PIN9 :1; /*!< Interrupt status of pin 9 */ uint32_t PIN10 :1; /*!< Interrupt status of pin 10 */ uint32_t PIN11 :1; /*!< Interrupt status of pin 11 */ uint32_t PIN12 :1; /*!< Interrupt status of pin 12 */ uint32_t PIN13 :1; /*!< Interrupt status of pin 13 */ uint32_t PIN14 :1; /*!< Interrupt status of pin 14 */ uint32_t PIN15 :1; /*!< Interrupt status of pin 15 */ } _GPIO_INTSTATUS_bits; /* Bit field positions: */ #define GPIO_INTSTATUS_PIN0_Pos 0 /*!< Interrupt status of pin 0 */ #define GPIO_INTSTATUS_PIN1_Pos 1 /*!< Interrupt status of pin 1 */ #define GPIO_INTSTATUS_PIN2_Pos 2 /*!< Interrupt status of pin 2 */ #define GPIO_INTSTATUS_PIN3_Pos 3 /*!< Interrupt status of pin 3 */ #define GPIO_INTSTATUS_PIN4_Pos 4 /*!< Interrupt status of pin 4 */ #define GPIO_INTSTATUS_PIN5_Pos 5 /*!< Interrupt status of pin 5 */ #define GPIO_INTSTATUS_PIN6_Pos 6 /*!< Interrupt status of pin 6 */ #define GPIO_INTSTATUS_PIN7_Pos 7 /*!< Interrupt status of pin 7 */ #define GPIO_INTSTATUS_PIN8_Pos 8 /*!< Interrupt status of pin 8 */ #define GPIO_INTSTATUS_PIN9_Pos 9 /*!< Interrupt status of pin 9 */ #define GPIO_INTSTATUS_PIN10_Pos 10 /*!< Interrupt status of pin 10 */ #define GPIO_INTSTATUS_PIN11_Pos 11 /*!< Interrupt status of pin 11 */ #define GPIO_INTSTATUS_PIN12_Pos 12 /*!< Interrupt status of pin 12 */ #define GPIO_INTSTATUS_PIN13_Pos 13 /*!< Interrupt status of pin 13 */ #define GPIO_INTSTATUS_PIN14_Pos 14 /*!< Interrupt status of pin 14 */ #define GPIO_INTSTATUS_PIN15_Pos 15 /*!< Interrupt status of pin 15 */ /* Bit field masks: */ #define GPIO_INTSTATUS_PIN0_Msk 0x00000001UL /*!< Interrupt status of pin 0 */ #define GPIO_INTSTATUS_PIN1_Msk 0x00000002UL /*!< Interrupt status of pin 1 */ #define GPIO_INTSTATUS_PIN2_Msk 0x00000004UL /*!< Interrupt status of pin 2 */ #define GPIO_INTSTATUS_PIN3_Msk 0x00000008UL /*!< Interrupt status of pin 3 */ #define GPIO_INTSTATUS_PIN4_Msk 0x00000010UL /*!< Interrupt status of pin 4 */ #define GPIO_INTSTATUS_PIN5_Msk 0x00000020UL /*!< Interrupt status of pin 5 */ #define GPIO_INTSTATUS_PIN6_Msk 0x00000040UL /*!< Interrupt status of pin 6 */ #define GPIO_INTSTATUS_PIN7_Msk 0x00000080UL /*!< Interrupt status of pin 7 */ #define GPIO_INTSTATUS_PIN8_Msk 0x00000100UL /*!< Interrupt status of pin 8 */ #define GPIO_INTSTATUS_PIN9_Msk 0x00000200UL /*!< Interrupt status of pin 9 */ #define GPIO_INTSTATUS_PIN10_Msk 0x00000400UL /*!< Interrupt status of pin 10 */ #define GPIO_INTSTATUS_PIN11_Msk 0x00000800UL /*!< Interrupt status of pin 11 */ #define GPIO_INTSTATUS_PIN12_Msk 0x00001000UL /*!< Interrupt status of pin 12 */ #define GPIO_INTSTATUS_PIN13_Msk 0x00002000UL /*!< Interrupt status of pin 13 */ #define GPIO_INTSTATUS_PIN14_Msk 0x00004000UL /*!< Interrupt status of pin 14 */ #define GPIO_INTSTATUS_PIN15_Msk 0x00008000UL /*!< Interrupt status of pin 15 */ /*-- DMAREQSET: DMA request enable register ------------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< DMA request enable for pin 0 */ uint32_t PIN1 :1; /*!< DMA request enable for pin 1 */ uint32_t PIN2 :1; /*!< DMA request enable for pin 2 */ uint32_t PIN3 :1; /*!< DMA request enable for pin 3 */ uint32_t PIN4 :1; /*!< DMA request enable for pin 4 */ uint32_t PIN5 :1; /*!< DMA request enable for pin 5 */ uint32_t PIN6 :1; /*!< DMA request enable for pin 6 */ uint32_t PIN7 :1; /*!< DMA request enable for pin 7 */ uint32_t PIN8 :1; /*!< DMA request enable for pin 8 */ uint32_t PIN9 :1; /*!< DMA request enable for pin 9 */ uint32_t PIN10 :1; /*!< DMA request enable for pin 10 */ uint32_t PIN11 :1; /*!< DMA request enable for pin 11 */ uint32_t PIN12 :1; /*!< DMA request enable for pin 12 */ uint32_t PIN13 :1; /*!< DMA request enable for pin 13 */ uint32_t PIN14 :1; /*!< DMA request enable for pin 14 */ uint32_t PIN15 :1; /*!< DMA request enable for pin 15 */ } _GPIO_DMAREQSET_bits; /* Bit field positions: */ #define GPIO_DMAREQSET_PIN0_Pos 0 /*!< DMA request enable for pin 0 */ #define GPIO_DMAREQSET_PIN1_Pos 1 /*!< DMA request enable for pin 1 */ #define GPIO_DMAREQSET_PIN2_Pos 2 /*!< DMA request enable for pin 2 */ #define GPIO_DMAREQSET_PIN3_Pos 3 /*!< DMA request enable for pin 3 */ #define GPIO_DMAREQSET_PIN4_Pos 4 /*!< DMA request enable for pin 4 */ #define GPIO_DMAREQSET_PIN5_Pos 5 /*!< DMA request enable for pin 5 */ #define GPIO_DMAREQSET_PIN6_Pos 6 /*!< DMA request enable for pin 6 */ #define GPIO_DMAREQSET_PIN7_Pos 7 /*!< DMA request enable for pin 7 */ #define GPIO_DMAREQSET_PIN8_Pos 8 /*!< DMA request enable for pin 8 */ #define GPIO_DMAREQSET_PIN9_Pos 9 /*!< DMA request enable for pin 9 */ #define GPIO_DMAREQSET_PIN10_Pos 10 /*!< DMA request enable for pin 10 */ #define GPIO_DMAREQSET_PIN11_Pos 11 /*!< DMA request enable for pin 11 */ #define GPIO_DMAREQSET_PIN12_Pos 12 /*!< DMA request enable for pin 12 */ #define GPIO_DMAREQSET_PIN13_Pos 13 /*!< DMA request enable for pin 13 */ #define GPIO_DMAREQSET_PIN14_Pos 14 /*!< DMA request enable for pin 14 */ #define GPIO_DMAREQSET_PIN15_Pos 15 /*!< DMA request enable for pin 15 */ /* Bit field masks: */ #define GPIO_DMAREQSET_PIN0_Msk 0x00000001UL /*!< DMA request enable for pin 0 */ #define GPIO_DMAREQSET_PIN1_Msk 0x00000002UL /*!< DMA request enable for pin 1 */ #define GPIO_DMAREQSET_PIN2_Msk 0x00000004UL /*!< DMA request enable for pin 2 */ #define GPIO_DMAREQSET_PIN3_Msk 0x00000008UL /*!< DMA request enable for pin 3 */ #define GPIO_DMAREQSET_PIN4_Msk 0x00000010UL /*!< DMA request enable for pin 4 */ #define GPIO_DMAREQSET_PIN5_Msk 0x00000020UL /*!< DMA request enable for pin 5 */ #define GPIO_DMAREQSET_PIN6_Msk 0x00000040UL /*!< DMA request enable for pin 6 */ #define GPIO_DMAREQSET_PIN7_Msk 0x00000080UL /*!< DMA request enable for pin 7 */ #define GPIO_DMAREQSET_PIN8_Msk 0x00000100UL /*!< DMA request enable for pin 8 */ #define GPIO_DMAREQSET_PIN9_Msk 0x00000200UL /*!< DMA request enable for pin 9 */ #define GPIO_DMAREQSET_PIN10_Msk 0x00000400UL /*!< DMA request enable for pin 10 */ #define GPIO_DMAREQSET_PIN11_Msk 0x00000800UL /*!< DMA request enable for pin 11 */ #define GPIO_DMAREQSET_PIN12_Msk 0x00001000UL /*!< DMA request enable for pin 12 */ #define GPIO_DMAREQSET_PIN13_Msk 0x00002000UL /*!< DMA request enable for pin 13 */ #define GPIO_DMAREQSET_PIN14_Msk 0x00004000UL /*!< DMA request enable for pin 14 */ #define GPIO_DMAREQSET_PIN15_Msk 0x00008000UL /*!< DMA request enable for pin 15 */ /*-- DMAREQCLR: DMA request disable register -----------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< DMA request disable for pin 0 */ uint32_t PIN1 :1; /*!< DMA request disable for pin 1 */ uint32_t PIN2 :1; /*!< DMA request disable for pin 2 */ uint32_t PIN3 :1; /*!< DMA request disable for pin 3 */ uint32_t PIN4 :1; /*!< DMA request disable for pin 4 */ uint32_t PIN5 :1; /*!< DMA request disable for pin 5 */ uint32_t PIN6 :1; /*!< DMA request disable for pin 6 */ uint32_t PIN7 :1; /*!< DMA request disable for pin 7 */ uint32_t PIN8 :1; /*!< DMA request disable for pin 8 */ uint32_t PIN9 :1; /*!< DMA request disable for pin 9 */ uint32_t PIN10 :1; /*!< DMA request disable for pin 10 */ uint32_t PIN11 :1; /*!< DMA request disable for pin 11 */ uint32_t PIN12 :1; /*!< DMA request disable for pin 12 */ uint32_t PIN13 :1; /*!< DMA request disable for pin 13 */ uint32_t PIN14 :1; /*!< DMA request disable for pin 14 */ uint32_t PIN15 :1; /*!< DMA request disable for pin 15 */ } _GPIO_DMAREQCLR_bits; /* Bit field positions: */ #define GPIO_DMAREQCLR_PIN0_Pos 0 /*!< DMA request disable for pin 0 */ #define GPIO_DMAREQCLR_PIN1_Pos 1 /*!< DMA request disable for pin 1 */ #define GPIO_DMAREQCLR_PIN2_Pos 2 /*!< DMA request disable for pin 2 */ #define GPIO_DMAREQCLR_PIN3_Pos 3 /*!< DMA request disable for pin 3 */ #define GPIO_DMAREQCLR_PIN4_Pos 4 /*!< DMA request disable for pin 4 */ #define GPIO_DMAREQCLR_PIN5_Pos 5 /*!< DMA request disable for pin 5 */ #define GPIO_DMAREQCLR_PIN6_Pos 6 /*!< DMA request disable for pin 6 */ #define GPIO_DMAREQCLR_PIN7_Pos 7 /*!< DMA request disable for pin 7 */ #define GPIO_DMAREQCLR_PIN8_Pos 8 /*!< DMA request disable for pin 8 */ #define GPIO_DMAREQCLR_PIN9_Pos 9 /*!< DMA request disable for pin 9 */ #define GPIO_DMAREQCLR_PIN10_Pos 10 /*!< DMA request disable for pin 10 */ #define GPIO_DMAREQCLR_PIN11_Pos 11 /*!< DMA request disable for pin 11 */ #define GPIO_DMAREQCLR_PIN12_Pos 12 /*!< DMA request disable for pin 12 */ #define GPIO_DMAREQCLR_PIN13_Pos 13 /*!< DMA request disable for pin 13 */ #define GPIO_DMAREQCLR_PIN14_Pos 14 /*!< DMA request disable for pin 14 */ #define GPIO_DMAREQCLR_PIN15_Pos 15 /*!< DMA request disable for pin 15 */ /* Bit field masks: */ #define GPIO_DMAREQCLR_PIN0_Msk 0x00000001UL /*!< DMA request disable for pin 0 */ #define GPIO_DMAREQCLR_PIN1_Msk 0x00000002UL /*!< DMA request disable for pin 1 */ #define GPIO_DMAREQCLR_PIN2_Msk 0x00000004UL /*!< DMA request disable for pin 2 */ #define GPIO_DMAREQCLR_PIN3_Msk 0x00000008UL /*!< DMA request disable for pin 3 */ #define GPIO_DMAREQCLR_PIN4_Msk 0x00000010UL /*!< DMA request disable for pin 4 */ #define GPIO_DMAREQCLR_PIN5_Msk 0x00000020UL /*!< DMA request disable for pin 5 */ #define GPIO_DMAREQCLR_PIN6_Msk 0x00000040UL /*!< DMA request disable for pin 6 */ #define GPIO_DMAREQCLR_PIN7_Msk 0x00000080UL /*!< DMA request disable for pin 7 */ #define GPIO_DMAREQCLR_PIN8_Msk 0x00000100UL /*!< DMA request disable for pin 8 */ #define GPIO_DMAREQCLR_PIN9_Msk 0x00000200UL /*!< DMA request disable for pin 9 */ #define GPIO_DMAREQCLR_PIN10_Msk 0x00000400UL /*!< DMA request disable for pin 10 */ #define GPIO_DMAREQCLR_PIN11_Msk 0x00000800UL /*!< DMA request disable for pin 11 */ #define GPIO_DMAREQCLR_PIN12_Msk 0x00001000UL /*!< DMA request disable for pin 12 */ #define GPIO_DMAREQCLR_PIN13_Msk 0x00002000UL /*!< DMA request disable for pin 13 */ #define GPIO_DMAREQCLR_PIN14_Msk 0x00004000UL /*!< DMA request disable for pin 14 */ #define GPIO_DMAREQCLR_PIN15_Msk 0x00008000UL /*!< DMA request disable for pin 15 */ /*-- ADCSOCSET: ADC Start Of Conversion enable register ------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< ADC SOC enable for pin 0 */ uint32_t PIN1 :1; /*!< ADC SOC enable for pin 1 */ uint32_t PIN2 :1; /*!< ADC SOC enable for pin 2 */ uint32_t PIN3 :1; /*!< ADC SOC enable for pin 3 */ uint32_t PIN4 :1; /*!< ADC SOC enable for pin 4 */ uint32_t PIN5 :1; /*!< ADC SOC enable for pin 5 */ uint32_t PIN6 :1; /*!< ADC SOC enable for pin 6 */ uint32_t PIN7 :1; /*!< ADC SOC enable for pin 7 */ uint32_t PIN8 :1; /*!< ADC SOC enable for pin 8 */ uint32_t PIN9 :1; /*!< ADC SOC enable for pin 9 */ uint32_t PIN10 :1; /*!< ADC SOC enable for pin 10 */ uint32_t PIN11 :1; /*!< ADC SOC enable for pin 11 */ uint32_t PIN12 :1; /*!< ADC SOC enable for pin 12 */ uint32_t PIN13 :1; /*!< ADC SOC enable for pin 13 */ uint32_t PIN14 :1; /*!< ADC SOC enable for pin 14 */ uint32_t PIN15 :1; /*!< ADC SOC enable for pin 15 */ } _GPIO_ADCSOCSET_bits; /* Bit field positions: */ #define GPIO_ADCSOCSET_PIN0_Pos 0 /*!< ADC SOC enable for pin 0 */ #define GPIO_ADCSOCSET_PIN1_Pos 1 /*!< ADC SOC enable for pin 1 */ #define GPIO_ADCSOCSET_PIN2_Pos 2 /*!< ADC SOC enable for pin 2 */ #define GPIO_ADCSOCSET_PIN3_Pos 3 /*!< ADC SOC enable for pin 3 */ #define GPIO_ADCSOCSET_PIN4_Pos 4 /*!< ADC SOC enable for pin 4 */ #define GPIO_ADCSOCSET_PIN5_Pos 5 /*!< ADC SOC enable for pin 5 */ #define GPIO_ADCSOCSET_PIN6_Pos 6 /*!< ADC SOC enable for pin 6 */ #define GPIO_ADCSOCSET_PIN7_Pos 7 /*!< ADC SOC enable for pin 7 */ #define GPIO_ADCSOCSET_PIN8_Pos 8 /*!< ADC SOC enable for pin 8 */ #define GPIO_ADCSOCSET_PIN9_Pos 9 /*!< ADC SOC enable for pin 9 */ #define GPIO_ADCSOCSET_PIN10_Pos 10 /*!< ADC SOC enable for pin 10 */ #define GPIO_ADCSOCSET_PIN11_Pos 11 /*!< ADC SOC enable for pin 11 */ #define GPIO_ADCSOCSET_PIN12_Pos 12 /*!< ADC SOC enable for pin 12 */ #define GPIO_ADCSOCSET_PIN13_Pos 13 /*!< ADC SOC enable for pin 13 */ #define GPIO_ADCSOCSET_PIN14_Pos 14 /*!< ADC SOC enable for pin 14 */ #define GPIO_ADCSOCSET_PIN15_Pos 15 /*!< ADC SOC enable for pin 15 */ /* Bit field masks: */ #define GPIO_ADCSOCSET_PIN0_Msk 0x00000001UL /*!< ADC SOC enable for pin 0 */ #define GPIO_ADCSOCSET_PIN1_Msk 0x00000002UL /*!< ADC SOC enable for pin 1 */ #define GPIO_ADCSOCSET_PIN2_Msk 0x00000004UL /*!< ADC SOC enable for pin 2 */ #define GPIO_ADCSOCSET_PIN3_Msk 0x00000008UL /*!< ADC SOC enable for pin 3 */ #define GPIO_ADCSOCSET_PIN4_Msk 0x00000010UL /*!< ADC SOC enable for pin 4 */ #define GPIO_ADCSOCSET_PIN5_Msk 0x00000020UL /*!< ADC SOC enable for pin 5 */ #define GPIO_ADCSOCSET_PIN6_Msk 0x00000040UL /*!< ADC SOC enable for pin 6 */ #define GPIO_ADCSOCSET_PIN7_Msk 0x00000080UL /*!< ADC SOC enable for pin 7 */ #define GPIO_ADCSOCSET_PIN8_Msk 0x00000100UL /*!< ADC SOC enable for pin 8 */ #define GPIO_ADCSOCSET_PIN9_Msk 0x00000200UL /*!< ADC SOC enable for pin 9 */ #define GPIO_ADCSOCSET_PIN10_Msk 0x00000400UL /*!< ADC SOC enable for pin 10 */ #define GPIO_ADCSOCSET_PIN11_Msk 0x00000800UL /*!< ADC SOC enable for pin 11 */ #define GPIO_ADCSOCSET_PIN12_Msk 0x00001000UL /*!< ADC SOC enable for pin 12 */ #define GPIO_ADCSOCSET_PIN13_Msk 0x00002000UL /*!< ADC SOC enable for pin 13 */ #define GPIO_ADCSOCSET_PIN14_Msk 0x00004000UL /*!< ADC SOC enable for pin 14 */ #define GPIO_ADCSOCSET_PIN15_Msk 0x00008000UL /*!< ADC SOC enable for pin 15 */ /*-- ADCSOCCLR: ADC Start Of Conversion disable register -----------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< ADC SOC disable for pin 0 */ uint32_t PIN1 :1; /*!< ADC SOC disable for pin 1 */ uint32_t PIN2 :1; /*!< ADC SOC disable for pin 2 */ uint32_t PIN3 :1; /*!< ADC SOC disable for pin 3 */ uint32_t PIN4 :1; /*!< ADC SOC disable for pin 4 */ uint32_t PIN5 :1; /*!< ADC SOC disable for pin 5 */ uint32_t PIN6 :1; /*!< ADC SOC disable for pin 6 */ uint32_t PIN7 :1; /*!< ADC SOC disable for pin 7 */ uint32_t PIN8 :1; /*!< ADC SOC disable for pin 8 */ uint32_t PIN9 :1; /*!< ADC SOC disable for pin 9 */ uint32_t PIN10 :1; /*!< ADC SOC disable for pin 10 */ uint32_t PIN11 :1; /*!< ADC SOC disable for pin 11 */ uint32_t PIN12 :1; /*!< ADC SOC disable for pin 12 */ uint32_t PIN13 :1; /*!< ADC SOC disable for pin 13 */ uint32_t PIN14 :1; /*!< ADC SOC disable for pin 14 */ uint32_t PIN15 :1; /*!< ADC SOC disable for pin 15 */ } _GPIO_ADCSOCCLR_bits; /* Bit field positions: */ #define GPIO_ADCSOCCLR_PIN0_Pos 0 /*!< ADC SOC disable for pin 0 */ #define GPIO_ADCSOCCLR_PIN1_Pos 1 /*!< ADC SOC disable for pin 1 */ #define GPIO_ADCSOCCLR_PIN2_Pos 2 /*!< ADC SOC disable for pin 2 */ #define GPIO_ADCSOCCLR_PIN3_Pos 3 /*!< ADC SOC disable for pin 3 */ #define GPIO_ADCSOCCLR_PIN4_Pos 4 /*!< ADC SOC disable for pin 4 */ #define GPIO_ADCSOCCLR_PIN5_Pos 5 /*!< ADC SOC disable for pin 5 */ #define GPIO_ADCSOCCLR_PIN6_Pos 6 /*!< ADC SOC disable for pin 6 */ #define GPIO_ADCSOCCLR_PIN7_Pos 7 /*!< ADC SOC disable for pin 7 */ #define GPIO_ADCSOCCLR_PIN8_Pos 8 /*!< ADC SOC disable for pin 8 */ #define GPIO_ADCSOCCLR_PIN9_Pos 9 /*!< ADC SOC disable for pin 9 */ #define GPIO_ADCSOCCLR_PIN10_Pos 10 /*!< ADC SOC disable for pin 10 */ #define GPIO_ADCSOCCLR_PIN11_Pos 11 /*!< ADC SOC disable for pin 11 */ #define GPIO_ADCSOCCLR_PIN12_Pos 12 /*!< ADC SOC disable for pin 12 */ #define GPIO_ADCSOCCLR_PIN13_Pos 13 /*!< ADC SOC disable for pin 13 */ #define GPIO_ADCSOCCLR_PIN14_Pos 14 /*!< ADC SOC disable for pin 14 */ #define GPIO_ADCSOCCLR_PIN15_Pos 15 /*!< ADC SOC disable for pin 15 */ /* Bit field masks: */ #define GPIO_ADCSOCCLR_PIN0_Msk 0x00000001UL /*!< ADC SOC disable for pin 0 */ #define GPIO_ADCSOCCLR_PIN1_Msk 0x00000002UL /*!< ADC SOC disable for pin 1 */ #define GPIO_ADCSOCCLR_PIN2_Msk 0x00000004UL /*!< ADC SOC disable for pin 2 */ #define GPIO_ADCSOCCLR_PIN3_Msk 0x00000008UL /*!< ADC SOC disable for pin 3 */ #define GPIO_ADCSOCCLR_PIN4_Msk 0x00000010UL /*!< ADC SOC disable for pin 4 */ #define GPIO_ADCSOCCLR_PIN5_Msk 0x00000020UL /*!< ADC SOC disable for pin 5 */ #define GPIO_ADCSOCCLR_PIN6_Msk 0x00000040UL /*!< ADC SOC disable for pin 6 */ #define GPIO_ADCSOCCLR_PIN7_Msk 0x00000080UL /*!< ADC SOC disable for pin 7 */ #define GPIO_ADCSOCCLR_PIN8_Msk 0x00000100UL /*!< ADC SOC disable for pin 8 */ #define GPIO_ADCSOCCLR_PIN9_Msk 0x00000200UL /*!< ADC SOC disable for pin 9 */ #define GPIO_ADCSOCCLR_PIN10_Msk 0x00000400UL /*!< ADC SOC disable for pin 10 */ #define GPIO_ADCSOCCLR_PIN11_Msk 0x00000800UL /*!< ADC SOC disable for pin 11 */ #define GPIO_ADCSOCCLR_PIN12_Msk 0x00001000UL /*!< ADC SOC disable for pin 12 */ #define GPIO_ADCSOCCLR_PIN13_Msk 0x00002000UL /*!< ADC SOC disable for pin 13 */ #define GPIO_ADCSOCCLR_PIN14_Msk 0x00004000UL /*!< ADC SOC disable for pin 14 */ #define GPIO_ADCSOCCLR_PIN15_Msk 0x00008000UL /*!< ADC SOC disable for pin 15 */ /*-- RXEVSET: Core RXEV request enable register --------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< RXEV enable for pin 0 */ uint32_t PIN1 :1; /*!< RXEV enable for pin 1 */ uint32_t PIN2 :1; /*!< RXEV enable for pin 2 */ uint32_t PIN3 :1; /*!< RXEV enable for pin 3 */ uint32_t PIN4 :1; /*!< RXEV enable for pin 4 */ uint32_t PIN5 :1; /*!< RXEV enable for pin 5 */ uint32_t PIN6 :1; /*!< RXEV enable for pin 6 */ uint32_t PIN7 :1; /*!< RXEV enable for pin 7 */ uint32_t PIN8 :1; /*!< RXEV enable for pin 8 */ uint32_t PIN9 :1; /*!< RXEV enable for pin 9 */ uint32_t PIN10 :1; /*!< RXEV enable for pin 10 */ uint32_t PIN11 :1; /*!< RXEV enable for pin 11 */ uint32_t PIN12 :1; /*!< RXEV enable for pin 12 */ uint32_t PIN13 :1; /*!< RXEV enable for pin 13 */ uint32_t PIN14 :1; /*!< RXEV enable for pin 14 */ uint32_t PIN15 :1; /*!< RXEV enable for pin 15 */ } _GPIO_RXEVSET_bits; /* Bit field positions: */ #define GPIO_RXEVSET_PIN0_Pos 0 /*!< RXEV enable for pin 0 */ #define GPIO_RXEVSET_PIN1_Pos 1 /*!< RXEV enable for pin 1 */ #define GPIO_RXEVSET_PIN2_Pos 2 /*!< RXEV enable for pin 2 */ #define GPIO_RXEVSET_PIN3_Pos 3 /*!< RXEV enable for pin 3 */ #define GPIO_RXEVSET_PIN4_Pos 4 /*!< RXEV enable for pin 4 */ #define GPIO_RXEVSET_PIN5_Pos 5 /*!< RXEV enable for pin 5 */ #define GPIO_RXEVSET_PIN6_Pos 6 /*!< RXEV enable for pin 6 */ #define GPIO_RXEVSET_PIN7_Pos 7 /*!< RXEV enable for pin 7 */ #define GPIO_RXEVSET_PIN8_Pos 8 /*!< RXEV enable for pin 8 */ #define GPIO_RXEVSET_PIN9_Pos 9 /*!< RXEV enable for pin 9 */ #define GPIO_RXEVSET_PIN10_Pos 10 /*!< RXEV enable for pin 10 */ #define GPIO_RXEVSET_PIN11_Pos 11 /*!< RXEV enable for pin 11 */ #define GPIO_RXEVSET_PIN12_Pos 12 /*!< RXEV enable for pin 12 */ #define GPIO_RXEVSET_PIN13_Pos 13 /*!< RXEV enable for pin 13 */ #define GPIO_RXEVSET_PIN14_Pos 14 /*!< RXEV enable for pin 14 */ #define GPIO_RXEVSET_PIN15_Pos 15 /*!< RXEV enable for pin 15 */ /* Bit field masks: */ #define GPIO_RXEVSET_PIN0_Msk 0x00000001UL /*!< RXEV enable for pin 0 */ #define GPIO_RXEVSET_PIN1_Msk 0x00000002UL /*!< RXEV enable for pin 1 */ #define GPIO_RXEVSET_PIN2_Msk 0x00000004UL /*!< RXEV enable for pin 2 */ #define GPIO_RXEVSET_PIN3_Msk 0x00000008UL /*!< RXEV enable for pin 3 */ #define GPIO_RXEVSET_PIN4_Msk 0x00000010UL /*!< RXEV enable for pin 4 */ #define GPIO_RXEVSET_PIN5_Msk 0x00000020UL /*!< RXEV enable for pin 5 */ #define GPIO_RXEVSET_PIN6_Msk 0x00000040UL /*!< RXEV enable for pin 6 */ #define GPIO_RXEVSET_PIN7_Msk 0x00000080UL /*!< RXEV enable for pin 7 */ #define GPIO_RXEVSET_PIN8_Msk 0x00000100UL /*!< RXEV enable for pin 8 */ #define GPIO_RXEVSET_PIN9_Msk 0x00000200UL /*!< RXEV enable for pin 9 */ #define GPIO_RXEVSET_PIN10_Msk 0x00000400UL /*!< RXEV enable for pin 10 */ #define GPIO_RXEVSET_PIN11_Msk 0x00000800UL /*!< RXEV enable for pin 11 */ #define GPIO_RXEVSET_PIN12_Msk 0x00001000UL /*!< RXEV enable for pin 12 */ #define GPIO_RXEVSET_PIN13_Msk 0x00002000UL /*!< RXEV enable for pin 13 */ #define GPIO_RXEVSET_PIN14_Msk 0x00004000UL /*!< RXEV enable for pin 14 */ #define GPIO_RXEVSET_PIN15_Msk 0x00008000UL /*!< RXEV enable for pin 15 */ /*-- RXEVCLR: Core RXEV request disable register -------------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< RXEV disable for pin 0 */ uint32_t PIN1 :1; /*!< RXEV disable for pin 1 */ uint32_t PIN2 :1; /*!< RXEV disable for pin 2 */ uint32_t PIN3 :1; /*!< RXEV disable for pin 3 */ uint32_t PIN4 :1; /*!< RXEV disable for pin 4 */ uint32_t PIN5 :1; /*!< RXEV disable for pin 5 */ uint32_t PIN6 :1; /*!< RXEV disable for pin 6 */ uint32_t PIN7 :1; /*!< RXEV disable for pin 7 */ uint32_t PIN8 :1; /*!< RXEV disable for pin 8 */ uint32_t PIN9 :1; /*!< RXEV disable for pin 9 */ uint32_t PIN10 :1; /*!< RXEV disable for pin 10 */ uint32_t PIN11 :1; /*!< RXEV disable for pin 11 */ uint32_t PIN12 :1; /*!< RXEV disable for pin 12 */ uint32_t PIN13 :1; /*!< RXEV disable for pin 13 */ uint32_t PIN14 :1; /*!< RXEV disable for pin 14 */ uint32_t PIN15 :1; /*!< RXEV disable for pin 15 */ } _GPIO_RXEVCLR_bits; /* Bit field positions: */ #define GPIO_RXEVCLR_PIN0_Pos 0 /*!< RXEV disable for pin 0 */ #define GPIO_RXEVCLR_PIN1_Pos 1 /*!< RXEV disable for pin 1 */ #define GPIO_RXEVCLR_PIN2_Pos 2 /*!< RXEV disable for pin 2 */ #define GPIO_RXEVCLR_PIN3_Pos 3 /*!< RXEV disable for pin 3 */ #define GPIO_RXEVCLR_PIN4_Pos 4 /*!< RXEV disable for pin 4 */ #define GPIO_RXEVCLR_PIN5_Pos 5 /*!< RXEV disable for pin 5 */ #define GPIO_RXEVCLR_PIN6_Pos 6 /*!< RXEV disable for pin 6 */ #define GPIO_RXEVCLR_PIN7_Pos 7 /*!< RXEV disable for pin 7 */ #define GPIO_RXEVCLR_PIN8_Pos 8 /*!< RXEV disable for pin 8 */ #define GPIO_RXEVCLR_PIN9_Pos 9 /*!< RXEV disable for pin 9 */ #define GPIO_RXEVCLR_PIN10_Pos 10 /*!< RXEV disable for pin 10 */ #define GPIO_RXEVCLR_PIN11_Pos 11 /*!< RXEV disable for pin 11 */ #define GPIO_RXEVCLR_PIN12_Pos 12 /*!< RXEV disable for pin 12 */ #define GPIO_RXEVCLR_PIN13_Pos 13 /*!< RXEV disable for pin 13 */ #define GPIO_RXEVCLR_PIN14_Pos 14 /*!< RXEV disable for pin 14 */ #define GPIO_RXEVCLR_PIN15_Pos 15 /*!< RXEV disable for pin 15 */ /* Bit field masks: */ #define GPIO_RXEVCLR_PIN0_Msk 0x00000001UL /*!< RXEV disable for pin 0 */ #define GPIO_RXEVCLR_PIN1_Msk 0x00000002UL /*!< RXEV disable for pin 1 */ #define GPIO_RXEVCLR_PIN2_Msk 0x00000004UL /*!< RXEV disable for pin 2 */ #define GPIO_RXEVCLR_PIN3_Msk 0x00000008UL /*!< RXEV disable for pin 3 */ #define GPIO_RXEVCLR_PIN4_Msk 0x00000010UL /*!< RXEV disable for pin 4 */ #define GPIO_RXEVCLR_PIN5_Msk 0x00000020UL /*!< RXEV disable for pin 5 */ #define GPIO_RXEVCLR_PIN6_Msk 0x00000040UL /*!< RXEV disable for pin 6 */ #define GPIO_RXEVCLR_PIN7_Msk 0x00000080UL /*!< RXEV disable for pin 7 */ #define GPIO_RXEVCLR_PIN8_Msk 0x00000100UL /*!< RXEV disable for pin 8 */ #define GPIO_RXEVCLR_PIN9_Msk 0x00000200UL /*!< RXEV disable for pin 9 */ #define GPIO_RXEVCLR_PIN10_Msk 0x00000400UL /*!< RXEV disable for pin 10 */ #define GPIO_RXEVCLR_PIN11_Msk 0x00000800UL /*!< RXEV disable for pin 11 */ #define GPIO_RXEVCLR_PIN12_Msk 0x00001000UL /*!< RXEV disable for pin 12 */ #define GPIO_RXEVCLR_PIN13_Msk 0x00002000UL /*!< RXEV disable for pin 13 */ #define GPIO_RXEVCLR_PIN14_Msk 0x00004000UL /*!< RXEV disable for pin 14 */ #define GPIO_RXEVCLR_PIN15_Msk 0x00008000UL /*!< RXEV disable for pin 15 */ /*-- LOCKKEY: Key register to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE) --------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Key to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE) */ } _GPIO_LOCKKEY_bits; /* Bit field positions: */ #define GPIO_LOCKKEY_VAL_Pos 0 /*!< Key to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE) */ /* Bit field masks: */ #define GPIO_LOCKKEY_VAL_Msk 0xFFFFFFFFUL /*!< Key to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE) */ /* Bit field enums: */ typedef enum { GPIO_LOCKKEY_VAL_LOCK = -286331154, /*!< 0xEEEEEEEE, key to lock registers */ GPIO_LOCKKEY_VAL_UNLOCK = -1377117202, /*!< 0xADEADBEE, key to unlock registers */ } GPIO_LOCKKEY_VAL_Enum; /*-- LOCKSTAT: Write LOCKSET/LOCKCLR enable status register --------------------------------------------------*/ typedef struct { uint32_t WREN :1; /*!< Write LOCKSET/LOCKCLR enable status */ } _GPIO_LOCKSTAT_bits; /* Bit field positions: */ #define GPIO_LOCKSTAT_WREN_Pos 0 /*!< Write LOCKSET/LOCKCLR enable status */ /* Bit field masks: */ #define GPIO_LOCKSTAT_WREN_Msk 0x00000001UL /*!< Write LOCKSET/LOCKCLR enable status */ /*-- LOCKSET: Lock pins configuration enable register --------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Lock configuration enable for pin 0 */ uint32_t PIN1 :1; /*!< Lock configuration enable for pin 1 */ uint32_t PIN2 :1; /*!< Lock configuration enable for pin 2 */ uint32_t PIN3 :1; /*!< Lock configuration enable for pin 3 */ uint32_t PIN4 :1; /*!< Lock configuration enable for pin 4 */ uint32_t PIN5 :1; /*!< Lock configuration enable for pin 5 */ uint32_t PIN6 :1; /*!< Lock configuration enable for pin 6 */ uint32_t PIN7 :1; /*!< Lock configuration enable for pin 7 */ uint32_t PIN8 :1; /*!< Lock configuration enable for pin 8 */ uint32_t PIN9 :1; /*!< Lock configuration enable for pin 9 */ uint32_t PIN10 :1; /*!< Lock configuration enable for pin 10 */ uint32_t PIN11 :1; /*!< Lock configuration enable for pin 11 */ uint32_t PIN12 :1; /*!< Lock configuration enable for pin 12 */ uint32_t PIN13 :1; /*!< Lock configuration enable for pin 13 */ uint32_t PIN14 :1; /*!< Lock configuration enable for pin 14 */ uint32_t PIN15 :1; /*!< Lock configuration enable for pin 15 */ } _GPIO_LOCKSET_bits; /* Bit field positions: */ #define GPIO_LOCKSET_PIN0_Pos 0 /*!< Lock configuration enable for pin 0 */ #define GPIO_LOCKSET_PIN1_Pos 1 /*!< Lock configuration enable for pin 1 */ #define GPIO_LOCKSET_PIN2_Pos 2 /*!< Lock configuration enable for pin 2 */ #define GPIO_LOCKSET_PIN3_Pos 3 /*!< Lock configuration enable for pin 3 */ #define GPIO_LOCKSET_PIN4_Pos 4 /*!< Lock configuration enable for pin 4 */ #define GPIO_LOCKSET_PIN5_Pos 5 /*!< Lock configuration enable for pin 5 */ #define GPIO_LOCKSET_PIN6_Pos 6 /*!< Lock configuration enable for pin 6 */ #define GPIO_LOCKSET_PIN7_Pos 7 /*!< Lock configuration enable for pin 7 */ #define GPIO_LOCKSET_PIN8_Pos 8 /*!< Lock configuration enable for pin 8 */ #define GPIO_LOCKSET_PIN9_Pos 9 /*!< Lock configuration enable for pin 9 */ #define GPIO_LOCKSET_PIN10_Pos 10 /*!< Lock configuration enable for pin 10 */ #define GPIO_LOCKSET_PIN11_Pos 11 /*!< Lock configuration enable for pin 11 */ #define GPIO_LOCKSET_PIN12_Pos 12 /*!< Lock configuration enable for pin 12 */ #define GPIO_LOCKSET_PIN13_Pos 13 /*!< Lock configuration enable for pin 13 */ #define GPIO_LOCKSET_PIN14_Pos 14 /*!< Lock configuration enable for pin 14 */ #define GPIO_LOCKSET_PIN15_Pos 15 /*!< Lock configuration enable for pin 15 */ /* Bit field masks: */ #define GPIO_LOCKSET_PIN0_Msk 0x00000001UL /*!< Lock configuration enable for pin 0 */ #define GPIO_LOCKSET_PIN1_Msk 0x00000002UL /*!< Lock configuration enable for pin 1 */ #define GPIO_LOCKSET_PIN2_Msk 0x00000004UL /*!< Lock configuration enable for pin 2 */ #define GPIO_LOCKSET_PIN3_Msk 0x00000008UL /*!< Lock configuration enable for pin 3 */ #define GPIO_LOCKSET_PIN4_Msk 0x00000010UL /*!< Lock configuration enable for pin 4 */ #define GPIO_LOCKSET_PIN5_Msk 0x00000020UL /*!< Lock configuration enable for pin 5 */ #define GPIO_LOCKSET_PIN6_Msk 0x00000040UL /*!< Lock configuration enable for pin 6 */ #define GPIO_LOCKSET_PIN7_Msk 0x00000080UL /*!< Lock configuration enable for pin 7 */ #define GPIO_LOCKSET_PIN8_Msk 0x00000100UL /*!< Lock configuration enable for pin 8 */ #define GPIO_LOCKSET_PIN9_Msk 0x00000200UL /*!< Lock configuration enable for pin 9 */ #define GPIO_LOCKSET_PIN10_Msk 0x00000400UL /*!< Lock configuration enable for pin 10 */ #define GPIO_LOCKSET_PIN11_Msk 0x00000800UL /*!< Lock configuration enable for pin 11 */ #define GPIO_LOCKSET_PIN12_Msk 0x00001000UL /*!< Lock configuration enable for pin 12 */ #define GPIO_LOCKSET_PIN13_Msk 0x00002000UL /*!< Lock configuration enable for pin 13 */ #define GPIO_LOCKSET_PIN14_Msk 0x00004000UL /*!< Lock configuration enable for pin 14 */ #define GPIO_LOCKSET_PIN15_Msk 0x00008000UL /*!< Lock configuration enable for pin 15 */ /*-- LOCKCLR: Lock pins configuration disable register -------------------------------------------------------*/ typedef struct { uint32_t PIN0 :1; /*!< Lock configuration disable for pin 0 */ uint32_t PIN1 :1; /*!< Lock configuration disable for pin 1 */ uint32_t PIN2 :1; /*!< Lock configuration disable for pin 2 */ uint32_t PIN3 :1; /*!< Lock configuration disable for pin 3 */ uint32_t PIN4 :1; /*!< Lock configuration disable for pin 4 */ uint32_t PIN5 :1; /*!< Lock configuration disable for pin 5 */ uint32_t PIN6 :1; /*!< Lock configuration disable for pin 6 */ uint32_t PIN7 :1; /*!< Lock configuration disable for pin 7 */ uint32_t PIN8 :1; /*!< Lock configuration disable for pin 8 */ uint32_t PIN9 :1; /*!< Lock configuration disable for pin 9 */ uint32_t PIN10 :1; /*!< Lock configuration disable for pin 10 */ uint32_t PIN11 :1; /*!< Lock configuration disable for pin 11 */ uint32_t PIN12 :1; /*!< Lock configuration disable for pin 12 */ uint32_t PIN13 :1; /*!< Lock configuration disable for pin 13 */ uint32_t PIN14 :1; /*!< Lock configuration disable for pin 14 */ uint32_t PIN15 :1; /*!< Lock configuration disable for pin 15 */ } _GPIO_LOCKCLR_bits; /* Bit field positions: */ #define GPIO_LOCKCLR_PIN0_Pos 0 /*!< Lock configuration disable for pin 0 */ #define GPIO_LOCKCLR_PIN1_Pos 1 /*!< Lock configuration disable for pin 1 */ #define GPIO_LOCKCLR_PIN2_Pos 2 /*!< Lock configuration disable for pin 2 */ #define GPIO_LOCKCLR_PIN3_Pos 3 /*!< Lock configuration disable for pin 3 */ #define GPIO_LOCKCLR_PIN4_Pos 4 /*!< Lock configuration disable for pin 4 */ #define GPIO_LOCKCLR_PIN5_Pos 5 /*!< Lock configuration disable for pin 5 */ #define GPIO_LOCKCLR_PIN6_Pos 6 /*!< Lock configuration disable for pin 6 */ #define GPIO_LOCKCLR_PIN7_Pos 7 /*!< Lock configuration disable for pin 7 */ #define GPIO_LOCKCLR_PIN8_Pos 8 /*!< Lock configuration disable for pin 8 */ #define GPIO_LOCKCLR_PIN9_Pos 9 /*!< Lock configuration disable for pin 9 */ #define GPIO_LOCKCLR_PIN10_Pos 10 /*!< Lock configuration disable for pin 10 */ #define GPIO_LOCKCLR_PIN11_Pos 11 /*!< Lock configuration disable for pin 11 */ #define GPIO_LOCKCLR_PIN12_Pos 12 /*!< Lock configuration disable for pin 12 */ #define GPIO_LOCKCLR_PIN13_Pos 13 /*!< Lock configuration disable for pin 13 */ #define GPIO_LOCKCLR_PIN14_Pos 14 /*!< Lock configuration disable for pin 14 */ #define GPIO_LOCKCLR_PIN15_Pos 15 /*!< Lock configuration disable for pin 15 */ /* Bit field masks: */ #define GPIO_LOCKCLR_PIN0_Msk 0x00000001UL /*!< Lock configuration disable for pin 0 */ #define GPIO_LOCKCLR_PIN1_Msk 0x00000002UL /*!< Lock configuration disable for pin 1 */ #define GPIO_LOCKCLR_PIN2_Msk 0x00000004UL /*!< Lock configuration disable for pin 2 */ #define GPIO_LOCKCLR_PIN3_Msk 0x00000008UL /*!< Lock configuration disable for pin 3 */ #define GPIO_LOCKCLR_PIN4_Msk 0x00000010UL /*!< Lock configuration disable for pin 4 */ #define GPIO_LOCKCLR_PIN5_Msk 0x00000020UL /*!< Lock configuration disable for pin 5 */ #define GPIO_LOCKCLR_PIN6_Msk 0x00000040UL /*!< Lock configuration disable for pin 6 */ #define GPIO_LOCKCLR_PIN7_Msk 0x00000080UL /*!< Lock configuration disable for pin 7 */ #define GPIO_LOCKCLR_PIN8_Msk 0x00000100UL /*!< Lock configuration disable for pin 8 */ #define GPIO_LOCKCLR_PIN9_Msk 0x00000200UL /*!< Lock configuration disable for pin 9 */ #define GPIO_LOCKCLR_PIN10_Msk 0x00000400UL /*!< Lock configuration disable for pin 10 */ #define GPIO_LOCKCLR_PIN11_Msk 0x00000800UL /*!< Lock configuration disable for pin 11 */ #define GPIO_LOCKCLR_PIN12_Msk 0x00001000UL /*!< Lock configuration disable for pin 12 */ #define GPIO_LOCKCLR_PIN13_Msk 0x00002000UL /*!< Lock configuration disable for pin 13 */ #define GPIO_LOCKCLR_PIN14_Msk 0x00004000UL /*!< Lock configuration disable for pin 14 */ #define GPIO_LOCKCLR_PIN15_Msk 0x00008000UL /*!< Lock configuration disable for pin 15 */ /*-- MASKLB: MASKLB: Mask register low byte of port -----------------------------------------------------------*/ typedef struct { uint32_t VAL :8; /*!< Mask low byte */ } _GPIO_MASKLB_MASKLB_bits; /* Bit field positions: */ #define GPIO_MASKLB_MASKLB_VAL_Pos 0 /*!< Mask low byte */ /* Bit field masks: */ #define GPIO_MASKLB_MASKLB_VAL_Msk 0x000000FFUL /*!< Mask low byte */ /*-- MASKHB: MASKHB: Mask register High byte of port ----------------------------------------------------------*/ typedef struct { uint32_t :8; /*!< RESERVED */ uint32_t VAL :8; /*!< Mask high byte */ } _GPIO_MASKHB_MASKHB_bits; /* Bit field positions: */ #define GPIO_MASKHB_MASKHB_VAL_Pos 8 /*!< Mask high byte */ /* Bit field masks: */ #define GPIO_MASKHB_MASKHB_VAL_Msk 0x0000FF00UL /*!< Mask high byte */ //Cluster MASKLB: typedef struct { union { /*!< Mask register low byte of port */ __IO uint32_t MASKLB; /*!< MASKLB : type used for word access */ __IO _GPIO_MASKLB_MASKLB_bits MASKLB_bit; /*!< MASKLB_bit: structure used for bit access */ }; } _GPIO_MASKLB_TypeDef; //Cluster MASKHB: typedef struct { union { /*!< Mask register High byte of port */ __IO uint32_t MASKHB; /*!< MASKHB : type used for word access */ __IO _GPIO_MASKHB_MASKHB_bits MASKHB_bit; /*!< MASKHB_bit: structure used for bit access */ }; } _GPIO_MASKHB_TypeDef; typedef struct { union { /*!< Data Input register */ __I uint32_t DATA; /*!< DATA : type used for word access */ __I _GPIO_DATA_bits DATA_bit; /*!< DATA_bit: structure used for bit access */ }; union { /*!< Data output register */ __IO uint32_t DATAOUT; /*!< DATAOUT : type used for word access */ __IO _GPIO_DATAOUT_bits DATAOUT_bit; /*!< DATAOUT_bit: structure used for bit access */ }; union { /*!< Data output set bits register */ __O uint32_t DATAOUTSET; /*!< DATAOUTSET : type used for word access */ __O _GPIO_DATAOUTSET_bits DATAOUTSET_bit; /*!< DATAOUTSET_bit: structure used for bit access */ }; union { /*!< Data output clear bits register */ __O uint32_t DATAOUTCLR; /*!< DATAOUTCLR : type used for word access */ __O _GPIO_DATAOUTCLR_bits DATAOUTCLR_bit; /*!< DATAOUTCLR_bit: structure used for bit access */ }; union { /*!< Data output toogle bits register */ __O uint32_t DATAOUTTGL; /*!< DATAOUTTGL : type used for word access */ __O _GPIO_DATAOUTTGL_bits DATAOUTTGL_bit; /*!< DATAOUTTGL_bit: structure used for bit access */ }; union { /*!< Digital function (PAD) enable register */ __IO uint32_t DENSET; /*!< DENSET : type used for word access */ __IO _GPIO_DENSET_bits DENSET_bit; /*!< DENSET_bit: structure used for bit access */ }; union { /*!< Digital function (PAD) disable register */ __O uint32_t DENCLR; /*!< DENCLR : type used for word access */ __O _GPIO_DENCLR_bits DENCLR_bit; /*!< DENCLR_bit: structure used for bit access */ }; union { /*!< Select input mode register */ __IO uint32_t INMODE; /*!< INMODE : type used for word access */ __IO _GPIO_INMODE_bits INMODE_bit; /*!< INMODE_bit: structure used for bit access */ }; union { /*!< Select pull mode register */ __IO uint32_t PULLMODE; /*!< PULLMODE : type used for word access */ __IO _GPIO_PULLMODE_bits PULLMODE_bit; /*!< PULLMODE_bit: structure used for bit access */ }; union { /*!< Select output mode register */ __IO uint32_t OUTMODE; /*!< OUTMODE : type used for word access */ __IO _GPIO_OUTMODE_bits OUTMODE_bit; /*!< OUTMODE_bit: structure used for bit access */ }; union { /*!< Select drive mode register */ __IO uint32_t DRIVEMODE; /*!< DRIVEMODE : type used for word access */ __IO _GPIO_DRIVEMODE_bits DRIVEMODE_bit; /*!< DRIVEMODE_bit: structure used for bit access */ }; union { /*!< Output enable register */ __IO uint32_t OUTENSET; /*!< OUTENSET : type used for word access */ __IO _GPIO_OUTENSET_bits OUTENSET_bit; /*!< OUTENSET_bit: structure used for bit access */ }; union { /*!< Output disable register */ __O uint32_t OUTENCLR; /*!< OUTENCLR : type used for word access */ __O _GPIO_OUTENCLR_bits OUTENCLR_bit; /*!< OUTENCLR_bit: structure used for bit access */ }; union { /*!< Alternative function enable register */ __IO uint32_t ALTFUNCSET; /*!< ALTFUNCSET : type used for word access */ __IO _GPIO_ALTFUNCSET_bits ALTFUNCSET_bit; /*!< ALTFUNCSET_bit: structure used for bit access */ }; union { /*!< Alternative function disable register */ __O uint32_t ALTFUNCCLR; /*!< ALTFUNCCLR : type used for word access */ __O _GPIO_ALTFUNCCLR_bits ALTFUNCCLR_bit; /*!< ALTFUNCCLR_bit: structure used for bit access */ }; union { /*!< Alternative function number register */ __IO uint32_t ALTFUNCNUM0; /*!< ALTFUNCNUM0 : type used for word access */ __IO _GPIO_ALTFUNCNUM0_bits ALTFUNCNUM0_bit; /*!< ALTFUNCNUM0_bit: structure used for bit access */ }; union { /*!< Alternative function number register */ __IO uint32_t ALTFUNCNUM1; /*!< ALTFUNCNUM1 : type used for word access */ __IO _GPIO_ALTFUNCNUM1_bits ALTFUNCNUM1_bit; /*!< ALTFUNCNUM1_bit: structure used for bit access */ }; union { /*!< Additional double flip-flop syncronization enable register */ __IO uint32_t SYNCSET; /*!< SYNCSET : type used for word access */ __IO _GPIO_SYNCSET_bits SYNCSET_bit; /*!< SYNCSET_bit: structure used for bit access */ }; union { /*!< Additional double flip-flop syncronization disable register */ __O uint32_t SYNCCLR; /*!< SYNCCLR : type used for word access */ __O _GPIO_SYNCCLR_bits SYNCCLR_bit; /*!< SYNCCLR_bit: structure used for bit access */ }; union { /*!< Qualifier enable register */ __IO uint32_t QUALSET; /*!< QUALSET : type used for word access */ __IO _GPIO_QUALSET_bits QUALSET_bit; /*!< QUALSET_bit: structure used for bit access */ }; union { /*!< Qualifier disable register */ __O uint32_t QUALCLR; /*!< QUALCLR : type used for word access */ __O _GPIO_QUALCLR_bits QUALCLR_bit; /*!< QUALCLR_bit: structure used for bit access */ }; union { /*!< Qualifier mode set register */ __IO uint32_t QUALMODESET; /*!< QUALMODESET : type used for word access */ __IO _GPIO_QUALMODESET_bits QUALMODESET_bit; /*!< QUALMODESET_bit: structure used for bit access */ }; union { /*!< Qualifier mode clear register */ __O uint32_t QUALMODECLR; /*!< QUALMODECLR : type used for word access */ __O _GPIO_QUALMODECLR_bits QUALMODECLR_bit; /*!< QUALMODECLR_bit: structure used for bit access */ }; union { /*!< Qualifier sample period register */ __IO uint32_t QUALSAMPLE; /*!< QUALSAMPLE : type used for word access */ __IO _GPIO_QUALSAMPLE_bits QUALSAMPLE_bit; /*!< QUALSAMPLE_bit: structure used for bit access */ }; union { /*!< Interrupt enable register */ __IO uint32_t INTENSET; /*!< INTENSET : type used for word access */ __IO _GPIO_INTENSET_bits INTENSET_bit; /*!< INTENSET_bit: structure used for bit access */ }; union { /*!< Interrupt disable register */ __O uint32_t INTENCLR; /*!< INTENCLR : type used for word access */ __O _GPIO_INTENCLR_bits INTENCLR_bit; /*!< INTENCLR_bit: structure used for bit access */ }; union { /*!< Interrupt type set register */ __IO uint32_t INTTYPESET; /*!< INTTYPESET : type used for word access */ __IO _GPIO_INTTYPESET_bits INTTYPESET_bit; /*!< INTTYPESET_bit: structure used for bit access */ }; union { /*!< Interrupt type clear register */ __O uint32_t INTTYPECLR; /*!< INTTYPECLR : type used for word access */ __O _GPIO_INTTYPECLR_bits INTTYPECLR_bit; /*!< INTTYPECLR_bit: structure used for bit access */ }; union { /*!< Interrupt polarity set register */ __IO uint32_t INTPOLSET; /*!< INTPOLSET : type used for word access */ __IO _GPIO_INTPOLSET_bits INTPOLSET_bit; /*!< INTPOLSET_bit: structure used for bit access */ }; union { /*!< Interrupt polarity clear register */ __O uint32_t INTPOLCLR; /*!< INTPOLCLR : type used for word access */ __O _GPIO_INTPOLCLR_bits INTPOLCLR_bit; /*!< INTPOLCLR_bit: structure used for bit access */ }; union { /*!< Interrupt every edge set register */ __IO uint32_t INTEDGESET; /*!< INTEDGESET : type used for word access */ __IO _GPIO_INTEDGESET_bits INTEDGESET_bit; /*!< INTEDGESET_bit: structure used for bit access */ }; union { /*!< Interrupt every edge clear register */ __O uint32_t INTEDGECLR; /*!< INTEDGECLR : type used for word access */ __O _GPIO_INTEDGECLR_bits INTEDGECLR_bit; /*!< INTEDGECLR_bit: structure used for bit access */ }; union { /*!< Interrupt status */ __IO uint32_t INTSTATUS; /*!< INTSTATUS : type used for word access */ __IO _GPIO_INTSTATUS_bits INTSTATUS_bit; /*!< INTSTATUS_bit: structure used for bit access */ }; union { /*!< DMA request enable register */ __IO uint32_t DMAREQSET; /*!< DMAREQSET : type used for word access */ __IO _GPIO_DMAREQSET_bits DMAREQSET_bit; /*!< DMAREQSET_bit: structure used for bit access */ }; union { /*!< DMA request disable register */ __O uint32_t DMAREQCLR; /*!< DMAREQCLR : type used for word access */ __O _GPIO_DMAREQCLR_bits DMAREQCLR_bit; /*!< DMAREQCLR_bit: structure used for bit access */ }; union { /*!< ADC Start Of Conversion enable register */ __IO uint32_t ADCSOCSET; /*!< ADCSOCSET : type used for word access */ __IO _GPIO_ADCSOCSET_bits ADCSOCSET_bit; /*!< ADCSOCSET_bit: structure used for bit access */ }; union { /*!< ADC Start Of Conversion disable register */ __O uint32_t ADCSOCCLR; /*!< ADCSOCCLR : type used for word access */ __O _GPIO_ADCSOCCLR_bits ADCSOCCLR_bit; /*!< ADCSOCCLR_bit: structure used for bit access */ }; union { /*!< Core RXEV request enable register */ __IO uint32_t RXEVSET; /*!< RXEVSET : type used for word access */ __IO _GPIO_RXEVSET_bits RXEVSET_bit; /*!< RXEVSET_bit: structure used for bit access */ }; union { /*!< Core RXEV request disable register */ __O uint32_t RXEVCLR; /*!< RXEVCLR : type used for word access */ __O _GPIO_RXEVCLR_bits RXEVCLR_bit; /*!< RXEVCLR_bit: structure used for bit access */ }; union { union { /*!< Key register to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE) */ __O uint32_t LOCKKEY; /*!< LOCKKEY : type used for word access */ __O _GPIO_LOCKKEY_bits LOCKKEY_bit; /*!< LOCKKEY_bit: structure used for bit access */ }; struct { union { /*!< Write LOCKSET/LOCKCLR enable status register */ __I uint32_t LOCKSTAT; /*!< LOCKSTAT : type used for word access */ __I _GPIO_LOCKSTAT_bits LOCKSTAT_bit; /*!< LOCKSTAT_bit: structure used for bit access */ }; }; }; union { /*!< Lock pins configuration enable register */ __IO uint32_t LOCKSET; /*!< LOCKSET : type used for word access */ __IO _GPIO_LOCKSET_bits LOCKSET_bit; /*!< LOCKSET_bit: structure used for bit access */ }; union { /*!< Lock pins configuration disable register */ __O uint32_t LOCKCLR; /*!< LOCKCLR : type used for word access */ __O _GPIO_LOCKCLR_bits LOCKCLR_bit; /*!< LOCKCLR_bit: structure used for bit access */ }; __IO uint32_t Reserved0[214]; _GPIO_MASKLB_TypeDef MASKLB[256]; _GPIO_MASKHB_TypeDef MASKHB[256]; } GPIO_TypeDef; /******************************************************************************/ /* TUART registers */ /******************************************************************************/ /*-- DATA: Data value register -------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :8; /*!< Received/Transmitted data character */ } _TUART_DATA_bits; /* Bit field positions: */ #define TUART_DATA_VAL_Pos 0 /*!< Received/Transmitted data character */ /* Bit field masks: */ #define TUART_DATA_VAL_Msk 0x000000FFUL /*!< Received/Transmitted data character */ /*-- STATE: State register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t TXF :1; /*!< TX buffer full */ uint32_t RXF :1; /*!< RX buffer full */ uint32_t TO :1; /*!< TX buffer overrun */ uint32_t RO :1; /*!< RX buffer overrun */ } _TUART_STATE_bits; /* Bit field positions: */ #define TUART_STATE_TXF_Pos 0 /*!< TX buffer full */ #define TUART_STATE_RXF_Pos 1 /*!< RX buffer full */ #define TUART_STATE_TO_Pos 2 /*!< TX buffer overrun */ #define TUART_STATE_RO_Pos 3 /*!< RX buffer overrun */ /* Bit field masks: */ #define TUART_STATE_TXF_Msk 0x00000001UL /*!< TX buffer full */ #define TUART_STATE_RXF_Msk 0x00000002UL /*!< RX buffer full */ #define TUART_STATE_TO_Msk 0x00000004UL /*!< TX buffer overrun */ #define TUART_STATE_RO_Msk 0x00000008UL /*!< RX buffer overrun */ /*-- CTRL: Control register ----------------------------------------------------------------------------------*/ typedef struct { uint32_t TXEN :1; /*!< TX enable */ uint32_t RXEN :1; /*!< RX enable */ uint32_t TXIEN :1; /*!< TX interrupt enable */ uint32_t RXIEN :1; /*!< RX interrupt enable */ uint32_t TOIEN :1; /*!< TX overrun interrupt enable */ uint32_t ROIEN :1; /*!< RX overrun interrupt enable */ } _TUART_CTRL_bits; /* Bit field positions: */ #define TUART_CTRL_TXEN_Pos 0 /*!< TX enable */ #define TUART_CTRL_RXEN_Pos 1 /*!< RX enable */ #define TUART_CTRL_TXIEN_Pos 2 /*!< TX interrupt enable */ #define TUART_CTRL_RXIEN_Pos 3 /*!< RX interrupt enable */ #define TUART_CTRL_TOIEN_Pos 4 /*!< TX overrun interrupt enable */ #define TUART_CTRL_ROIEN_Pos 5 /*!< RX overrun interrupt enable */ /* Bit field masks: */ #define TUART_CTRL_TXEN_Msk 0x00000001UL /*!< TX enable */ #define TUART_CTRL_RXEN_Msk 0x00000002UL /*!< RX enable */ #define TUART_CTRL_TXIEN_Msk 0x00000004UL /*!< TX interrupt enable */ #define TUART_CTRL_RXIEN_Msk 0x00000008UL /*!< RX interrupt enable */ #define TUART_CTRL_TOIEN_Msk 0x00000010UL /*!< TX overrun interrupt enable */ #define TUART_CTRL_ROIEN_Msk 0x00000020UL /*!< RX overrun interrupt enable */ /*-- INTSTATUS: Interrupt status register --------------------------------------------------------------------*/ typedef struct { uint32_t TXIS :1; /*!< TX interrupt status */ uint32_t RXIS :1; /*!< RX interrupt status */ uint32_t TOIS :1; /*!< TX overrun interrupt status */ uint32_t ROIS :1; /*!< RX overrun interrupt status */ } _TUART_INTSTATUS_bits; /* Bit field positions: */ #define TUART_INTSTATUS_TXIS_Pos 0 /*!< TX interrupt status */ #define TUART_INTSTATUS_RXIS_Pos 1 /*!< RX interrupt status */ #define TUART_INTSTATUS_TOIS_Pos 2 /*!< TX overrun interrupt status */ #define TUART_INTSTATUS_ROIS_Pos 3 /*!< RX overrun interrupt status */ /* Bit field masks: */ #define TUART_INTSTATUS_TXIS_Msk 0x00000001UL /*!< TX interrupt status */ #define TUART_INTSTATUS_RXIS_Msk 0x00000002UL /*!< RX interrupt status */ #define TUART_INTSTATUS_TOIS_Msk 0x00000004UL /*!< TX overrun interrupt status */ #define TUART_INTSTATUS_ROIS_Msk 0x00000008UL /*!< RX overrun interrupt status */ /*-- BAUDDIV: Baudrate Divider register ----------------------------------------------------------------------*/ typedef struct { uint32_t VAL :20; /*!< Baud rate divider. The minimum number is 16. */ } _TUART_BAUDDIV_bits; /* Bit field positions: */ #define TUART_BAUDDIV_VAL_Pos 0 /*!< Baud rate divider. The minimum number is 16. */ /* Bit field masks: */ #define TUART_BAUDDIV_VAL_Msk 0x000FFFFFUL /*!< Baud rate divider. The minimum number is 16. */ typedef struct { union { /*!< Data value register */ __IO uint32_t DATA; /*!< DATA : type used for word access */ __IO _TUART_DATA_bits DATA_bit; /*!< DATA_bit: structure used for bit access */ }; union { /*!< State register */ __IO uint32_t STATE; /*!< STATE : type used for word access */ __IO _TUART_STATE_bits STATE_bit; /*!< STATE_bit: structure used for bit access */ }; union { /*!< Control register */ __IO uint32_t CTRL; /*!< CTRL : type used for word access */ __IO _TUART_CTRL_bits CTRL_bit; /*!< CTRL_bit: structure used for bit access */ }; union { /*!< Interrupt status register */ __IO uint32_t INTSTATUS; /*!< INTSTATUS : type used for word access */ __IO _TUART_INTSTATUS_bits INTSTATUS_bit; /*!< INTSTATUS_bit: structure used for bit access */ }; union { /*!< Baudrate Divider register */ __IO uint32_t BAUDDIV; /*!< BAUDDIV : type used for word access */ __IO _TUART_BAUDDIV_bits BAUDDIV_bit; /*!< BAUDDIV_bit: structure used for bit access */ }; } TUART_TypeDef; /******************************************************************************/ /* OWI registers */ /******************************************************************************/ /*-- CTRL0: Control 0 Register -------------------------------------------------------------------------------*/ typedef struct { uint32_t EN :1; /*!< Enable OWI */ uint32_t :15; /*!< RESERVED */ uint32_t DIV :16; /*!< Clock divider value for one tick */ } _OWI_CTRL0_bits; /* Bit field positions: */ #define OWI_CTRL0_EN_Pos 0 /*!< Enable OWI */ #define OWI_CTRL0_DIV_Pos 16 /*!< Clock divider value for one tick */ /* Bit field masks: */ #define OWI_CTRL0_EN_Msk 0x00000001UL /*!< Enable OWI */ #define OWI_CTRL0_DIV_Msk 0xFFFF0000UL /*!< Clock divider value for one tick */ /*-- CTRL1: Control 1 Register -------------------------------------------------------------------------------*/ typedef struct { uint32_t OBPER :8; /*!< One bit period in ticks */ uint32_t RSTPER :8; /*!< Reset period in ticks */ uint32_t PRESPER :8; /*!< Presence period in ticks */ } _OWI_CTRL1_bits; /* Bit field positions: */ #define OWI_CTRL1_OBPER_Pos 0 /*!< One bit period in ticks */ #define OWI_CTRL1_RSTPER_Pos 8 /*!< Reset period in ticks */ #define OWI_CTRL1_PRESPER_Pos 16 /*!< Presence period in ticks */ /* Bit field masks: */ #define OWI_CTRL1_OBPER_Msk 0x000000FFUL /*!< One bit period in ticks */ #define OWI_CTRL1_RSTPER_Msk 0x0000FF00UL /*!< Reset period in ticks */ #define OWI_CTRL1_PRESPER_Msk 0x00FF0000UL /*!< Presence period in ticks */ /*-- STAT: Status register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t DONE :1; /*!< Operation DONE Flag for interrupt */ uint32_t BUSY :1; /*!< Busy flag status */ uint32_t PRES :1; /*!< Presence flag status after reset sequence */ } _OWI_STAT_bits; /* Bit field positions: */ #define OWI_STAT_DONE_Pos 0 /*!< Operation DONE Flag for interrupt */ #define OWI_STAT_BUSY_Pos 1 /*!< Busy flag status */ #define OWI_STAT_PRES_Pos 2 /*!< Presence flag status after reset sequence */ /* Bit field masks: */ #define OWI_STAT_DONE_Msk 0x00000001UL /*!< Operation DONE Flag for interrupt */ #define OWI_STAT_BUSY_Msk 0x00000002UL /*!< Busy flag status */ #define OWI_STAT_PRES_Msk 0x00000004UL /*!< Presence flag status after reset sequence */ /*-- IRQ: Interrupt Control Register -------------------------------------------------------------------------*/ typedef struct { uint32_t EN :1; /*!< Enable interrupt DONE operation */ } _OWI_IRQ_bits; /* Bit field positions: */ #define OWI_IRQ_EN_Pos 0 /*!< Enable interrupt DONE operation */ /* Bit field masks: */ #define OWI_IRQ_EN_Msk 0x00000001UL /*!< Enable interrupt DONE operation */ /*-- DATA: Data register -------------------------------------------------------------------------------------*/ typedef struct { uint32_t DATA :8; /*!< Data register. On write - init tx write operation. On read - get read value after RDCMD done. */ } _OWI_DATA_bits; /* Bit field positions: */ #define OWI_DATA_DATA_Pos 0 /*!< Data register. On write - init tx write operation. On read - get read value after RDCMD done. */ /* Bit field masks: */ #define OWI_DATA_DATA_Msk 0x000000FFUL /*!< Data register. On write - init tx write operation. On read - get read value after RDCMD done. */ /*-- CMD: Command Regiser ------------------------------------------------------------------------------------*/ typedef struct { uint32_t RDCMD :1; /*!< Initialize read command */ uint32_t RSTCMD :1; /*!< Initialize reset sequence command */ } _OWI_CMD_bits; /* Bit field positions: */ #define OWI_CMD_RDCMD_Pos 0 /*!< Initialize read command */ #define OWI_CMD_RSTCMD_Pos 1 /*!< Initialize reset sequence command */ /* Bit field masks: */ #define OWI_CMD_RDCMD_Msk 0x00000001UL /*!< Initialize read command */ #define OWI_CMD_RSTCMD_Msk 0x00000002UL /*!< Initialize reset sequence command */ typedef struct { union { /*!< Control 0 Register */ __IO uint32_t CTRL0; /*!< CTRL0 : type used for word access */ __IO _OWI_CTRL0_bits CTRL0_bit; /*!< CTRL0_bit: structure used for bit access */ }; union { /*!< Control 1 Register */ __IO uint32_t CTRL1; /*!< CTRL1 : type used for word access */ __IO _OWI_CTRL1_bits CTRL1_bit; /*!< CTRL1_bit: structure used for bit access */ }; union { /*!< Status register */ __IO uint32_t STAT; /*!< STAT : type used for word access */ __IO _OWI_STAT_bits STAT_bit; /*!< STAT_bit: structure used for bit access */ }; union { /*!< Interrupt Control Register */ __IO uint32_t IRQ; /*!< IRQ : type used for word access */ __IO _OWI_IRQ_bits IRQ_bit; /*!< IRQ_bit: structure used for bit access */ }; union { /*!< Data register */ __IO uint32_t DATA; /*!< DATA : type used for word access */ __IO _OWI_DATA_bits DATA_bit; /*!< DATA_bit: structure used for bit access */ }; union { /*!< Command Regiser */ __O uint32_t CMD; /*!< CMD : type used for word access */ __O _OWI_CMD_bits CMD_bit; /*!< CMD_bit: structure used for bit access */ }; } OWI_TypeDef; /******************************************************************************/ /* UART registers */ /******************************************************************************/ /*-- DR: Data Register ---------------------------------------------------------------------------------------*/ typedef struct { uint32_t DATA :8; /*!< Received/Transmitted data character */ uint32_t FE :1; /*!< Framing error */ uint32_t PE :1; /*!< Parity error */ uint32_t BE :1; /*!< Break error */ uint32_t OE :1; /*!< Overrun error */ } _UART_DR_bits; /* Bit field positions: */ #define UART_DR_DATA_Pos 0 /*!< Received/Transmitted data character */ #define UART_DR_FE_Pos 8 /*!< Framing error */ #define UART_DR_PE_Pos 9 /*!< Parity error */ #define UART_DR_BE_Pos 10 /*!< Break error */ #define UART_DR_OE_Pos 11 /*!< Overrun error */ /* Bit field masks: */ #define UART_DR_DATA_Msk 0x000000FFUL /*!< Received/Transmitted data character */ #define UART_DR_FE_Msk 0x00000100UL /*!< Framing error */ #define UART_DR_PE_Msk 0x00000200UL /*!< Parity error */ #define UART_DR_BE_Msk 0x00000400UL /*!< Break error */ #define UART_DR_OE_Msk 0x00000800UL /*!< Overrun error */ /*-- RSR: Receive Status Register/Error Clear Register -------------------------------------------------------*/ typedef struct { uint32_t FE :1; /*!< Framing error */ uint32_t PE :1; /*!< Parity error */ uint32_t BE :1; /*!< Break error */ uint32_t OE :1; /*!< Overrun error */ } _UART_RSR_bits; /* Bit field positions: */ #define UART_RSR_FE_Pos 0 /*!< Framing error */ #define UART_RSR_PE_Pos 1 /*!< Parity error */ #define UART_RSR_BE_Pos 2 /*!< Break error */ #define UART_RSR_OE_Pos 3 /*!< Overrun error */ /* Bit field masks: */ #define UART_RSR_FE_Msk 0x00000001UL /*!< Framing error */ #define UART_RSR_PE_Msk 0x00000002UL /*!< Parity error */ #define UART_RSR_BE_Msk 0x00000004UL /*!< Break error */ #define UART_RSR_OE_Msk 0x00000008UL /*!< Overrun error */ /*-- FR: Flag Register ---------------------------------------------------------------------------------------*/ typedef struct { uint32_t CTS :1; /*!< Clear to send */ uint32_t DSR :1; /*!< Data set ready */ uint32_t DCD :1; /*!< Data carrier detect */ uint32_t BUSY :1; /*!< UART busy */ uint32_t RXFE :1; /*!< Receive FIFO empty */ uint32_t TXFF :1; /*!< Transmit FIFO full */ uint32_t RXFF :1; /*!< Receive FIFO full */ uint32_t TXFE :1; /*!< Transmit FIFO empty */ uint32_t RI :1; /*!< Ring indicator */ } _UART_FR_bits; /* Bit field positions: */ #define UART_FR_CTS_Pos 0 /*!< Clear to send */ #define UART_FR_DSR_Pos 1 /*!< Data set ready */ #define UART_FR_DCD_Pos 2 /*!< Data carrier detect */ #define UART_FR_BUSY_Pos 3 /*!< UART busy */ #define UART_FR_RXFE_Pos 4 /*!< Receive FIFO empty */ #define UART_FR_TXFF_Pos 5 /*!< Transmit FIFO full */ #define UART_FR_RXFF_Pos 6 /*!< Receive FIFO full */ #define UART_FR_TXFE_Pos 7 /*!< Transmit FIFO empty */ #define UART_FR_RI_Pos 8 /*!< Ring indicator */ /* Bit field masks: */ #define UART_FR_CTS_Msk 0x00000001UL /*!< Clear to send */ #define UART_FR_DSR_Msk 0x00000002UL /*!< Data set ready */ #define UART_FR_DCD_Msk 0x00000004UL /*!< Data carrier detect */ #define UART_FR_BUSY_Msk 0x00000008UL /*!< UART busy */ #define UART_FR_RXFE_Msk 0x00000010UL /*!< Receive FIFO empty */ #define UART_FR_TXFF_Msk 0x00000020UL /*!< Transmit FIFO full */ #define UART_FR_RXFF_Msk 0x00000040UL /*!< Receive FIFO full */ #define UART_FR_TXFE_Msk 0x00000080UL /*!< Transmit FIFO empty */ #define UART_FR_RI_Msk 0x00000100UL /*!< Ring indicator */ /*-- ILPR: IrDA Low-Power Counter Register -------------------------------------------------------------------*/ typedef struct { uint32_t ILPDVSR :8; /*!< 8-bit low-power divisor value */ } _UART_ILPR_bits; /* Bit field positions: */ #define UART_ILPR_ILPDVSR_Pos 0 /*!< 8-bit low-power divisor value */ /* Bit field masks: */ #define UART_ILPR_ILPDVSR_Msk 0x000000FFUL /*!< 8-bit low-power divisor value */ /*-- IBRD: Integer Baud Rate Register ------------------------------------------------------------------------*/ typedef struct { uint32_t DIVINT :16; /*!< The integer baud rate divisor */ } _UART_IBRD_bits; /* Bit field positions: */ #define UART_IBRD_DIVINT_Pos 0 /*!< The integer baud rate divisor */ /* Bit field masks: */ #define UART_IBRD_DIVINT_Msk 0x0000FFFFUL /*!< The integer baud rate divisor */ /*-- FBRD: Fractional Baud Rate Register ---------------------------------------------------------------------*/ typedef struct { uint32_t DIVFRAC :6; /*!< The fractional baud rate divisor */ } _UART_FBRD_bits; /* Bit field positions: */ #define UART_FBRD_DIVFRAC_Pos 0 /*!< The fractional baud rate divisor */ /* Bit field masks: */ #define UART_FBRD_DIVFRAC_Msk 0x0000003FUL /*!< The fractional baud rate divisor */ /*-- LCRH: Line Control Register -----------------------------------------------------------------------------*/ typedef struct { uint32_t BRK :1; /*!< Send break */ uint32_t PEN :1; /*!< Parity enable */ uint32_t EPS :1; /*!< Even parity select */ uint32_t STP2 :1; /*!< Two stop bits select */ uint32_t FEN :1; /*!< Enable FIFOs */ uint32_t WLEN :2; /*!< Word length */ uint32_t SPS :1; /*!< Stick parity select */ } _UART_LCRH_bits; /* Bit field positions: */ #define UART_LCRH_BRK_Pos 0 /*!< Send break */ #define UART_LCRH_PEN_Pos 1 /*!< Parity enable */ #define UART_LCRH_EPS_Pos 2 /*!< Even parity select */ #define UART_LCRH_STP2_Pos 3 /*!< Two stop bits select */ #define UART_LCRH_FEN_Pos 4 /*!< Enable FIFOs */ #define UART_LCRH_WLEN_Pos 5 /*!< Word length */ #define UART_LCRH_SPS_Pos 7 /*!< Stick parity select */ /* Bit field masks: */ #define UART_LCRH_BRK_Msk 0x00000001UL /*!< Send break */ #define UART_LCRH_PEN_Msk 0x00000002UL /*!< Parity enable */ #define UART_LCRH_EPS_Msk 0x00000004UL /*!< Even parity select */ #define UART_LCRH_STP2_Msk 0x00000008UL /*!< Two stop bits select */ #define UART_LCRH_FEN_Msk 0x00000010UL /*!< Enable FIFOs */ #define UART_LCRH_WLEN_Msk 0x00000060UL /*!< Word length */ #define UART_LCRH_SPS_Msk 0x00000080UL /*!< Stick parity select */ /* Bit field enums: */ typedef enum { UART_LCRH_WLEN_5bit = 0x0UL, /*!< 5 bit in informational word */ UART_LCRH_WLEN_6bit = 0x1UL, /*!< 6 bit in informational word */ UART_LCRH_WLEN_7bit = 0x2UL, /*!< 7 bit in informational word */ UART_LCRH_WLEN_8bit = 0x3UL, /*!< 8 bit in informational word */ } UART_LCRH_WLEN_Enum; /*-- CR: Control Register ------------------------------------------------------------------------------------*/ typedef struct { uint32_t UARTEN :1; /*!< UART enable */ uint32_t :7; /*!< RESERVED */ uint32_t TXE :1; /*!< Transmit enable */ uint32_t RXE :1; /*!< Receive enable */ uint32_t DTR :1; /*!< Data transmit ready */ uint32_t RTS :1; /*!< Request to send */ uint32_t :2; /*!< RESERVED */ uint32_t RTSEN :1; /*!< RTS hardware flow control enable */ uint32_t CTSEN :1; /*!< CTS hardware flow control enable */ } _UART_CR_bits; /* Bit field positions: */ #define UART_CR_UARTEN_Pos 0 /*!< UART enable */ #define UART_CR_TXE_Pos 8 /*!< Transmit enable */ #define UART_CR_RXE_Pos 9 /*!< Receive enable */ #define UART_CR_DTR_Pos 10 /*!< Data transmit ready */ #define UART_CR_RTS_Pos 11 /*!< Request to send */ #define UART_CR_RTSEN_Pos 14 /*!< RTS hardware flow control enable */ #define UART_CR_CTSEN_Pos 15 /*!< CTS hardware flow control enable */ /* Bit field masks: */ #define UART_CR_UARTEN_Msk 0x00000001UL /*!< UART enable */ #define UART_CR_TXE_Msk 0x00000100UL /*!< Transmit enable */ #define UART_CR_RXE_Msk 0x00000200UL /*!< Receive enable */ #define UART_CR_DTR_Msk 0x00000400UL /*!< Data transmit ready */ #define UART_CR_RTS_Msk 0x00000800UL /*!< Request to send */ #define UART_CR_RTSEN_Msk 0x00004000UL /*!< RTS hardware flow control enable */ #define UART_CR_CTSEN_Msk 0x00008000UL /*!< CTS hardware flow control enable */ /*-- IFLS: Interrupt FIFO Level Select Register --------------------------------------------------------------*/ typedef struct { uint32_t TXIFLSEL :3; /*!< Transmit interrupt FIFO level select */ uint32_t RXIFLSEL :3; /*!< Receive interrupt FIFO level select */ } _UART_IFLS_bits; /* Bit field positions: */ #define UART_IFLS_TXIFLSEL_Pos 0 /*!< Transmit interrupt FIFO level select */ #define UART_IFLS_RXIFLSEL_Pos 3 /*!< Receive interrupt FIFO level select */ /* Bit field masks: */ #define UART_IFLS_TXIFLSEL_Msk 0x00000007UL /*!< Transmit interrupt FIFO level select */ #define UART_IFLS_RXIFLSEL_Msk 0x00000038UL /*!< Receive interrupt FIFO level select */ /* Bit field enums: */ typedef enum { UART_IFLS_TXIFLSEL_Lvl18 = 0x0UL, /*!< interrupt on 1/8 */ UART_IFLS_TXIFLSEL_Lvl14 = 0x1UL, /*!< interrupt on 1/4 */ UART_IFLS_TXIFLSEL_Lvl12 = 0x2UL, /*!< interrupt on 1/2 */ UART_IFLS_TXIFLSEL_Lvl34 = 0x3UL, /*!< interrupt on 3/4 */ UART_IFLS_TXIFLSEL_Lvl78 = 0x4UL, /*!< interrupt on 7/8 */ } UART_IFLS_TXIFLSEL_Enum; typedef enum { UART_IFLS_RXIFLSEL_Lvl18 = 0x0UL, /*!< interrupt on 1/8 */ UART_IFLS_RXIFLSEL_Lvl14 = 0x1UL, /*!< interrupt on 1/4 */ UART_IFLS_RXIFLSEL_Lvl12 = 0x2UL, /*!< interrupt on 1/2 */ UART_IFLS_RXIFLSEL_Lvl34 = 0x3UL, /*!< interrupt on 3/4 */ UART_IFLS_RXIFLSEL_Lvl78 = 0x4UL, /*!< interrupt on 7/8 */ } UART_IFLS_RXIFLSEL_Enum; /*-- IMSC: Interrupt Mask Set/Clear Register -----------------------------------------------------------------*/ typedef struct { uint32_t RIMIM :1; /*!< nUARTRI modem interrupt mask */ uint32_t CTSMIM :1; /*!< nUARTCTS modem interrupt mask */ uint32_t DCDMIM :1; /*!< nUARTDCD modem interrupt mask */ uint32_t DSRMIM :1; /*!< nUARTDSR modem interrupt mask */ uint32_t RXIM :1; /*!< Receive interrupt mask */ uint32_t TXIM :1; /*!< Transmit interrupt mask */ uint32_t RTIM :1; /*!< Receive timeout interrupt mask */ uint32_t FERIM :1; /*!< Framing error interrupt mask */ uint32_t PERIM :1; /*!< Parity error interrupt mask */ uint32_t BERIM :1; /*!< Break error interrupt mask */ uint32_t OERIM :1; /*!< Overrun error interrupt mask */ uint32_t TDIM :1; /*!< Transmit done interrupt mask */ } _UART_IMSC_bits; /* Bit field positions: */ #define UART_IMSC_RIMIM_Pos 0 /*!< nUARTRI modem interrupt mask */ #define UART_IMSC_CTSMIM_Pos 1 /*!< nUARTCTS modem interrupt mask */ #define UART_IMSC_DCDMIM_Pos 2 /*!< nUARTDCD modem interrupt mask */ #define UART_IMSC_DSRMIM_Pos 3 /*!< nUARTDSR modem interrupt mask */ #define UART_IMSC_RXIM_Pos 4 /*!< Receive interrupt mask */ #define UART_IMSC_TXIM_Pos 5 /*!< Transmit interrupt mask */ #define UART_IMSC_RTIM_Pos 6 /*!< Receive timeout interrupt mask */ #define UART_IMSC_FERIM_Pos 7 /*!< Framing error interrupt mask */ #define UART_IMSC_PERIM_Pos 8 /*!< Parity error interrupt mask */ #define UART_IMSC_BERIM_Pos 9 /*!< Break error interrupt mask */ #define UART_IMSC_OERIM_Pos 10 /*!< Overrun error interrupt mask */ #define UART_IMSC_TDIM_Pos 11 /*!< Transmit done interrupt mask */ /* Bit field masks: */ #define UART_IMSC_RIMIM_Msk 0x00000001UL /*!< nUARTRI modem interrupt mask */ #define UART_IMSC_CTSMIM_Msk 0x00000002UL /*!< nUARTCTS modem interrupt mask */ #define UART_IMSC_DCDMIM_Msk 0x00000004UL /*!< nUARTDCD modem interrupt mask */ #define UART_IMSC_DSRMIM_Msk 0x00000008UL /*!< nUARTDSR modem interrupt mask */ #define UART_IMSC_RXIM_Msk 0x00000010UL /*!< Receive interrupt mask */ #define UART_IMSC_TXIM_Msk 0x00000020UL /*!< Transmit interrupt mask */ #define UART_IMSC_RTIM_Msk 0x00000040UL /*!< Receive timeout interrupt mask */ #define UART_IMSC_FERIM_Msk 0x00000080UL /*!< Framing error interrupt mask */ #define UART_IMSC_PERIM_Msk 0x00000100UL /*!< Parity error interrupt mask */ #define UART_IMSC_BERIM_Msk 0x00000200UL /*!< Break error interrupt mask */ #define UART_IMSC_OERIM_Msk 0x00000400UL /*!< Overrun error interrupt mask */ #define UART_IMSC_TDIM_Msk 0x00000800UL /*!< Transmit done interrupt mask */ /*-- RIS: Raw Interrupt Status Register ----------------------------------------------------------------------*/ typedef struct { uint32_t RIRMIS :1; /*!< nUARTRI modem interrupt status */ uint32_t CTSRMIS :1; /*!< nUARTCTS modem interrupt status */ uint32_t DCDRMIS :1; /*!< nUARTDCD modem interrupt status */ uint32_t DSRRMIS :1; /*!< nUARTDSR modem interrupt status */ uint32_t RXRIS :1; /*!< Receive interrupt status */ uint32_t TXRIS :1; /*!< Transmit interrupt status */ uint32_t RTRIS :1; /*!< Receive timeout interrupt status */ uint32_t FERIS :1; /*!< Framing error interrupt status */ uint32_t PERIS :1; /*!< Parity error interrupt status */ uint32_t BERIS :1; /*!< Break error interrupt status */ uint32_t OERIS :1; /*!< Overrun error interrupt status */ uint32_t TDRIS :1; /*!< Transmit done raw interrupt status */ } _UART_RIS_bits; /* Bit field positions: */ #define UART_RIS_RIRMIS_Pos 0 /*!< nUARTRI modem interrupt status */ #define UART_RIS_CTSRMIS_Pos 1 /*!< nUARTCTS modem interrupt status */ #define UART_RIS_DCDRMIS_Pos 2 /*!< nUARTDCD modem interrupt status */ #define UART_RIS_DSRRMIS_Pos 3 /*!< nUARTDSR modem interrupt status */ #define UART_RIS_RXRIS_Pos 4 /*!< Receive interrupt status */ #define UART_RIS_TXRIS_Pos 5 /*!< Transmit interrupt status */ #define UART_RIS_RTRIS_Pos 6 /*!< Receive timeout interrupt status */ #define UART_RIS_FERIS_Pos 7 /*!< Framing error interrupt status */ #define UART_RIS_PERIS_Pos 8 /*!< Parity error interrupt status */ #define UART_RIS_BERIS_Pos 9 /*!< Break error interrupt status */ #define UART_RIS_OERIS_Pos 10 /*!< Overrun error interrupt status */ #define UART_RIS_TDRIS_Pos 11 /*!< Transmit done raw interrupt status */ /* Bit field masks: */ #define UART_RIS_RIRMIS_Msk 0x00000001UL /*!< nUARTRI modem interrupt status */ #define UART_RIS_CTSRMIS_Msk 0x00000002UL /*!< nUARTCTS modem interrupt status */ #define UART_RIS_DCDRMIS_Msk 0x00000004UL /*!< nUARTDCD modem interrupt status */ #define UART_RIS_DSRRMIS_Msk 0x00000008UL /*!< nUARTDSR modem interrupt status */ #define UART_RIS_RXRIS_Msk 0x00000010UL /*!< Receive interrupt status */ #define UART_RIS_TXRIS_Msk 0x00000020UL /*!< Transmit interrupt status */ #define UART_RIS_RTRIS_Msk 0x00000040UL /*!< Receive timeout interrupt status */ #define UART_RIS_FERIS_Msk 0x00000080UL /*!< Framing error interrupt status */ #define UART_RIS_PERIS_Msk 0x00000100UL /*!< Parity error interrupt status */ #define UART_RIS_BERIS_Msk 0x00000200UL /*!< Break error interrupt status */ #define UART_RIS_OERIS_Msk 0x00000400UL /*!< Overrun error interrupt status */ #define UART_RIS_TDRIS_Msk 0x00000800UL /*!< Transmit done raw interrupt status */ /*-- MIS: Masked Interrupt Status Register -------------------------------------------------------------------*/ typedef struct { uint32_t RIMMIS :1; /*!< nUARTRI modem masked interrupt status */ uint32_t CTSMMIS :1; /*!< nUARTCTS modem masked interrupt status */ uint32_t DCDMMIS :1; /*!< nUARTDCD modem masked interrupt status */ uint32_t DSRMMIS :1; /*!< nUARTDSR modem masked interrupt status */ uint32_t RXMIS :1; /*!< Receive masked interrupt status */ uint32_t TXMIS :1; /*!< Transmit masked interrupt status */ uint32_t RTMIS :1; /*!< Receive timeout masked interrupt status */ uint32_t FEMIS :1; /*!< Framing error masked interrupt status */ uint32_t PEMIS :1; /*!< Parity error masked interrupt status */ uint32_t BEMIS :1; /*!< Break error masked interrupt status */ uint32_t OEMIS :1; /*!< Overrun error masked interrupt status */ uint32_t TDMIS :1; /*!< Transmit done masked interrupt status */ } _UART_MIS_bits; /* Bit field positions: */ #define UART_MIS_RIMMIS_Pos 0 /*!< nUARTRI modem masked interrupt status */ #define UART_MIS_CTSMMIS_Pos 1 /*!< nUARTCTS modem masked interrupt status */ #define UART_MIS_DCDMMIS_Pos 2 /*!< nUARTDCD modem masked interrupt status */ #define UART_MIS_DSRMMIS_Pos 3 /*!< nUARTDSR modem masked interrupt status */ #define UART_MIS_RXMIS_Pos 4 /*!< Receive masked interrupt status */ #define UART_MIS_TXMIS_Pos 5 /*!< Transmit masked interrupt status */ #define UART_MIS_RTMIS_Pos 6 /*!< Receive timeout masked interrupt status */ #define UART_MIS_FEMIS_Pos 7 /*!< Framing error masked interrupt status */ #define UART_MIS_PEMIS_Pos 8 /*!< Parity error masked interrupt status */ #define UART_MIS_BEMIS_Pos 9 /*!< Break error masked interrupt status */ #define UART_MIS_OEMIS_Pos 10 /*!< Overrun error masked interrupt status */ #define UART_MIS_TDMIS_Pos 11 /*!< Transmit done masked interrupt status */ /* Bit field masks: */ #define UART_MIS_RIMMIS_Msk 0x00000001UL /*!< nUARTRI modem masked interrupt status */ #define UART_MIS_CTSMMIS_Msk 0x00000002UL /*!< nUARTCTS modem masked interrupt status */ #define UART_MIS_DCDMMIS_Msk 0x00000004UL /*!< nUARTDCD modem masked interrupt status */ #define UART_MIS_DSRMMIS_Msk 0x00000008UL /*!< nUARTDSR modem masked interrupt status */ #define UART_MIS_RXMIS_Msk 0x00000010UL /*!< Receive masked interrupt status */ #define UART_MIS_TXMIS_Msk 0x00000020UL /*!< Transmit masked interrupt status */ #define UART_MIS_RTMIS_Msk 0x00000040UL /*!< Receive timeout masked interrupt status */ #define UART_MIS_FEMIS_Msk 0x00000080UL /*!< Framing error masked interrupt status */ #define UART_MIS_PEMIS_Msk 0x00000100UL /*!< Parity error masked interrupt status */ #define UART_MIS_BEMIS_Msk 0x00000200UL /*!< Break error masked interrupt status */ #define UART_MIS_OEMIS_Msk 0x00000400UL /*!< Overrun error masked interrupt status */ #define UART_MIS_TDMIS_Msk 0x00000800UL /*!< Transmit done masked interrupt status */ /*-- ICR: Interrupt Clear Register ---------------------------------------------------------------------------*/ typedef struct { uint32_t RIMIC :1; /*!< nUARTRI modem interrupt clear */ uint32_t CTSMIC :1; /*!< nUARTCTS modem interrupt clear */ uint32_t DCDMIC :1; /*!< nUARTDCD modem interrupt clear */ uint32_t DSRMIC :1; /*!< nUARTDSR modem interrupt clear */ uint32_t RXIC :1; /*!< Receive interrupt clear */ uint32_t TXIC :1; /*!< Transmit interrupt clear */ uint32_t RTIC :1; /*!< Receive timeout interrupt clear */ uint32_t FEIC :1; /*!< Framing error interrupt clear */ uint32_t PEIC :1; /*!< Parity error interrupt clear */ uint32_t BEIC :1; /*!< Break error interrupt clear */ uint32_t OEIC :1; /*!< Overrun error interrupt clear */ uint32_t TDIC :1; /*!< Transmit done interrupt clear */ } _UART_ICR_bits; /* Bit field positions: */ #define UART_ICR_RIMIC_Pos 0 /*!< nUARTRI modem interrupt clear */ #define UART_ICR_CTSMIC_Pos 1 /*!< nUARTCTS modem interrupt clear */ #define UART_ICR_DCDMIC_Pos 2 /*!< nUARTDCD modem interrupt clear */ #define UART_ICR_DSRMIC_Pos 3 /*!< nUARTDSR modem interrupt clear */ #define UART_ICR_RXIC_Pos 4 /*!< Receive interrupt clear */ #define UART_ICR_TXIC_Pos 5 /*!< Transmit interrupt clear */ #define UART_ICR_RTIC_Pos 6 /*!< Receive timeout interrupt clear */ #define UART_ICR_FEIC_Pos 7 /*!< Framing error interrupt clear */ #define UART_ICR_PEIC_Pos 8 /*!< Parity error interrupt clear */ #define UART_ICR_BEIC_Pos 9 /*!< Break error interrupt clear */ #define UART_ICR_OEIC_Pos 10 /*!< Overrun error interrupt clear */ #define UART_ICR_TDIC_Pos 11 /*!< Transmit done interrupt clear */ /* Bit field masks: */ #define UART_ICR_RIMIC_Msk 0x00000001UL /*!< nUARTRI modem interrupt clear */ #define UART_ICR_CTSMIC_Msk 0x00000002UL /*!< nUARTCTS modem interrupt clear */ #define UART_ICR_DCDMIC_Msk 0x00000004UL /*!< nUARTDCD modem interrupt clear */ #define UART_ICR_DSRMIC_Msk 0x00000008UL /*!< nUARTDSR modem interrupt clear */ #define UART_ICR_RXIC_Msk 0x00000010UL /*!< Receive interrupt clear */ #define UART_ICR_TXIC_Msk 0x00000020UL /*!< Transmit interrupt clear */ #define UART_ICR_RTIC_Msk 0x00000040UL /*!< Receive timeout interrupt clear */ #define UART_ICR_FEIC_Msk 0x00000080UL /*!< Framing error interrupt clear */ #define UART_ICR_PEIC_Msk 0x00000100UL /*!< Parity error interrupt clear */ #define UART_ICR_BEIC_Msk 0x00000200UL /*!< Break error interrupt clear */ #define UART_ICR_OEIC_Msk 0x00000400UL /*!< Overrun error interrupt clear */ #define UART_ICR_TDIC_Msk 0x00000800UL /*!< Transmit done interrupt clear */ /*-- DMACR: DMA Control Register -----------------------------------------------------------------------------*/ typedef struct { uint32_t RXDMAE :1; /*!< Receive DMA enable */ uint32_t TXDMAE :1; /*!< Transmit DMA enable */ uint32_t DMAONERR :1; /*!< DMA on error */ } _UART_DMACR_bits; /* Bit field positions: */ #define UART_DMACR_RXDMAE_Pos 0 /*!< Receive DMA enable */ #define UART_DMACR_TXDMAE_Pos 1 /*!< Transmit DMA enable */ #define UART_DMACR_DMAONERR_Pos 2 /*!< DMA on error */ /* Bit field masks: */ #define UART_DMACR_RXDMAE_Msk 0x00000001UL /*!< Receive DMA enable */ #define UART_DMACR_TXDMAE_Msk 0x00000002UL /*!< Transmit DMA enable */ #define UART_DMACR_DMAONERR_Msk 0x00000004UL /*!< DMA on error */ typedef struct { union { /*!< Data Register */ __IO uint32_t DR; /*!< DR : type used for word access */ __IO _UART_DR_bits DR_bit; /*!< DR_bit: structure used for bit access */ }; union { /*!< Receive Status Register/Error Clear Register */ __IO uint32_t RSR; /*!< RSR : type used for word access */ __IO _UART_RSR_bits RSR_bit; /*!< RSR_bit: structure used for bit access */ }; __IO uint32_t Reserved0[4]; union { /*!< Flag Register */ __I uint32_t FR; /*!< FR : type used for word access */ __I _UART_FR_bits FR_bit; /*!< FR_bit: structure used for bit access */ }; __IO uint32_t Reserved1; union { /*!< IrDA Low-Power Counter Register */ __IO uint32_t ILPR; /*!< ILPR : type used for word access */ __IO _UART_ILPR_bits ILPR_bit; /*!< ILPR_bit: structure used for bit access */ }; union { /*!< Integer Baud Rate Register */ __IO uint32_t IBRD; /*!< IBRD : type used for word access */ __IO _UART_IBRD_bits IBRD_bit; /*!< IBRD_bit: structure used for bit access */ }; union { /*!< Fractional Baud Rate Register */ __IO uint32_t FBRD; /*!< FBRD : type used for word access */ __IO _UART_FBRD_bits FBRD_bit; /*!< FBRD_bit: structure used for bit access */ }; union { /*!< Line Control Register */ __IO uint32_t LCRH; /*!< LCRH : type used for word access */ __IO _UART_LCRH_bits LCRH_bit; /*!< LCRH_bit: structure used for bit access */ }; union { /*!< Control Register */ __IO uint32_t CR; /*!< CR : type used for word access */ __IO _UART_CR_bits CR_bit; /*!< CR_bit: structure used for bit access */ }; union { /*!< Interrupt FIFO Level Select Register */ __IO uint32_t IFLS; /*!< IFLS : type used for word access */ __IO _UART_IFLS_bits IFLS_bit; /*!< IFLS_bit: structure used for bit access */ }; union { /*!< Interrupt Mask Set/Clear Register */ __IO uint32_t IMSC; /*!< IMSC : type used for word access */ __IO _UART_IMSC_bits IMSC_bit; /*!< IMSC_bit: structure used for bit access */ }; union { /*!< Raw Interrupt Status Register */ __I uint32_t RIS; /*!< RIS : type used for word access */ __I _UART_RIS_bits RIS_bit; /*!< RIS_bit: structure used for bit access */ }; union { /*!< Masked Interrupt Status Register */ __I uint32_t MIS; /*!< MIS : type used for word access */ __I _UART_MIS_bits MIS_bit; /*!< MIS_bit: structure used for bit access */ }; union { /*!< Interrupt Clear Register */ __O uint32_t ICR; /*!< ICR : type used for word access */ __O _UART_ICR_bits ICR_bit; /*!< ICR_bit: structure used for bit access */ }; union { /*!< DMA Control Register */ __IO uint32_t DMACR; /*!< DMACR : type used for word access */ __IO _UART_DMACR_bits DMACR_bit; /*!< DMACR_bit: structure used for bit access */ }; } UART_TypeDef; /******************************************************************************/ /* DMA registers */ /******************************************************************************/ /*-- STATUS: Status DMA register -----------------------------------------------------------------------------*/ typedef struct { uint32_t MASTEREN :1; /*!< Indicate enable DMA */ uint32_t :3; /*!< RESERVED */ uint32_t STATE :4; /*!< State of DMA */ uint32_t :8; /*!< RESERVED */ uint32_t CHNLS :5; /*!< Number channel DMA (write: N-1) */ } _DMA_STATUS_bits; /* Bit field positions: */ #define DMA_STATUS_MASTEREN_Pos 0 /*!< Indicate enable DMA */ #define DMA_STATUS_STATE_Pos 4 /*!< State of DMA */ #define DMA_STATUS_CHNLS_Pos 16 /*!< Number channel DMA (write: N-1) */ /* Bit field masks: */ #define DMA_STATUS_MASTEREN_Msk 0x00000001UL /*!< Indicate enable DMA */ #define DMA_STATUS_STATE_Msk 0x000000F0UL /*!< State of DMA */ #define DMA_STATUS_CHNLS_Msk 0x001F0000UL /*!< Number channel DMA (write: N-1) */ /* Bit field enums: */ typedef enum { DMA_STATUS_STATE_Free = 0x0UL, /*!< At rest */ DMA_STATUS_STATE_ReadConfigData = 0x1UL, /*!< Reading the config data structure */ DMA_STATUS_STATE_ReadSrcDataEndPtr = 0x2UL, /*!< Reading sourse data end pointer */ DMA_STATUS_STATE_ReadDstDataEndPtr = 0x3UL, /*!< Reading destination data end pointer */ DMA_STATUS_STATE_ReadSrcData = 0x4UL, /*!< Reading source data */ DMA_STATUS_STATE_WrireDstData = 0x5UL, /*!< Writing data to the destination */ DMA_STATUS_STATE_WaitReq = 0x6UL, /*!< Waiting for a request */ DMA_STATUS_STATE_WriteConfigData = 0x7UL, /*!< Write config structure of the channel */ DMA_STATUS_STATE_Pause = 0x8UL, /*!< Suspended */ DMA_STATUS_STATE_Done = 0x9UL, /*!< Executed */ DMA_STATUS_STATE_PeriphScatGath = 0xAUL, /*!< mode "peripheral scather-gather" */ } DMA_STATUS_STATE_Enum; /*-- CFG: DMA configuration register -------------------------------------------------------------------------*/ typedef struct { uint32_t MASTEREN :1; /*!< Enable DMA */ uint32_t :4; /*!< RESERVED */ uint32_t CHPROT :3; /*!< Sets the AHB-Lite protection */ } _DMA_CFG_bits; /* Bit field positions: */ #define DMA_CFG_MASTEREN_Pos 0 /*!< Enable DMA */ #define DMA_CFG_CHPROT_Pos 5 /*!< Sets the AHB-Lite protection */ /* Bit field masks: */ #define DMA_CFG_MASTEREN_Msk 0x00000001UL /*!< Enable DMA */ #define DMA_CFG_CHPROT_Msk 0x000000E0UL /*!< Sets the AHB-Lite protection */ /*-- BASEPTR: Channel control data base pointer --------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Base address of the primary control data */ } _DMA_BASEPTR_bits; /* Bit field positions: */ #define DMA_BASEPTR_VAL_Pos 0 /*!< Base address of the primary control data */ /* Bit field masks: */ #define DMA_BASEPTR_VAL_Msk 0xFFFFFFFFUL /*!< Base address of the primary control data */ /*-- ALTBASEPTR: Channel alternate control data base pointer -------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Base address of alternative control data */ } _DMA_ALTBASEPTR_bits; /* Bit field positions: */ #define DMA_ALTBASEPTR_VAL_Pos 0 /*!< Base address of alternative control data */ /* Bit field masks: */ #define DMA_ALTBASEPTR_VAL_Msk 0xFFFFFFFFUL /*!< Base address of alternative control data */ /*-- WAITONREQ: Channel wait on request status ---------------------------------------------------------------*/ typedef struct { uint32_t CH0 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH1 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH2 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH3 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH4 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH5 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH6 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH7 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH8 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH9 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH10 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH11 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH12 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH13 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH14 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH15 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH16 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH17 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH18 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH19 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH20 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH21 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH22 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH23 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH24 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH25 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH26 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH27 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH28 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH29 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH30 :1; /*!< Returns the status of the DMA request signals */ uint32_t CH31 :1; /*!< Returns the status of the DMA request signals */ } _DMA_WAITONREQ_bits; /* Bit field positions: */ #define DMA_WAITONREQ_CH0_Pos 0 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH1_Pos 1 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH2_Pos 2 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH3_Pos 3 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH4_Pos 4 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH5_Pos 5 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH6_Pos 6 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH7_Pos 7 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH8_Pos 8 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH9_Pos 9 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH10_Pos 10 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH11_Pos 11 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH12_Pos 12 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH13_Pos 13 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH14_Pos 14 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH15_Pos 15 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH16_Pos 16 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH17_Pos 17 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH18_Pos 18 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH19_Pos 19 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH20_Pos 20 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH21_Pos 21 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH22_Pos 22 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH23_Pos 23 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH24_Pos 24 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH25_Pos 25 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH26_Pos 26 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH27_Pos 27 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH28_Pos 28 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH29_Pos 29 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH30_Pos 30 /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH31_Pos 31 /*!< Returns the status of the DMA request signals */ /* Bit field masks: */ #define DMA_WAITONREQ_CH0_Msk 0x00000001UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH1_Msk 0x00000002UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH2_Msk 0x00000004UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH3_Msk 0x00000008UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH4_Msk 0x00000010UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH5_Msk 0x00000020UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH6_Msk 0x00000040UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH7_Msk 0x00000080UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH8_Msk 0x00000100UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH9_Msk 0x00000200UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH10_Msk 0x00000400UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH11_Msk 0x00000800UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH12_Msk 0x00001000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH13_Msk 0x00002000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH14_Msk 0x00004000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH15_Msk 0x00008000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH16_Msk 0x00010000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH17_Msk 0x00020000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH18_Msk 0x00040000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH19_Msk 0x00080000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH20_Msk 0x00100000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH21_Msk 0x00200000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH22_Msk 0x00400000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH23_Msk 0x00800000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH24_Msk 0x01000000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH25_Msk 0x02000000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH26_Msk 0x04000000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH27_Msk 0x08000000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH28_Msk 0x10000000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH29_Msk 0x20000000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH30_Msk 0x40000000UL /*!< Returns the status of the DMA request signals */ #define DMA_WAITONREQ_CH31_Msk 0x80000000UL /*!< Returns the status of the DMA request signals */ /*-- SWREQ: Channel software request -------------------------------------------------------------------------*/ typedef struct { uint32_t CH0 :1; /*!< Set software request on channel */ uint32_t CH1 :1; /*!< Set software request on channel */ uint32_t CH2 :1; /*!< Set software request on channel */ uint32_t CH3 :1; /*!< Set software request on channel */ uint32_t CH4 :1; /*!< Set software request on channel */ uint32_t CH5 :1; /*!< Set software request on channel */ uint32_t CH6 :1; /*!< Set software request on channel */ uint32_t CH7 :1; /*!< Set software request on channel */ uint32_t CH8 :1; /*!< Set software request on channel */ uint32_t CH9 :1; /*!< Set software request on channel */ uint32_t CH10 :1; /*!< Set software request on channel */ uint32_t CH11 :1; /*!< Set software request on channel */ uint32_t CH12 :1; /*!< Set software request on channel */ uint32_t CH13 :1; /*!< Set software request on channel */ uint32_t CH14 :1; /*!< Set software request on channel */ uint32_t CH15 :1; /*!< Set software request on channel */ uint32_t CH16 :1; /*!< Set software request on channel */ uint32_t CH17 :1; /*!< Set software request on channel */ uint32_t CH18 :1; /*!< Set software request on channel */ uint32_t CH19 :1; /*!< Set software request on channel */ uint32_t CH20 :1; /*!< Set software request on channel */ uint32_t CH21 :1; /*!< Set software request on channel */ uint32_t CH22 :1; /*!< Set software request on channel */ uint32_t CH23 :1; /*!< Set software request on channel */ uint32_t CH24 :1; /*!< Set software request on channel */ uint32_t CH25 :1; /*!< Set software request on channel */ uint32_t CH26 :1; /*!< Set software request on channel */ uint32_t CH27 :1; /*!< Set software request on channel */ uint32_t CH28 :1; /*!< Set software request on channel */ uint32_t CH29 :1; /*!< Set software request on channel */ uint32_t CH30 :1; /*!< Set software request on channel */ uint32_t CH31 :1; /*!< Set software request on channel */ } _DMA_SWREQ_bits; /* Bit field positions: */ #define DMA_SWREQ_CH0_Pos 0 /*!< Set software request on channel */ #define DMA_SWREQ_CH1_Pos 1 /*!< Set software request on channel */ #define DMA_SWREQ_CH2_Pos 2 /*!< Set software request on channel */ #define DMA_SWREQ_CH3_Pos 3 /*!< Set software request on channel */ #define DMA_SWREQ_CH4_Pos 4 /*!< Set software request on channel */ #define DMA_SWREQ_CH5_Pos 5 /*!< Set software request on channel */ #define DMA_SWREQ_CH6_Pos 6 /*!< Set software request on channel */ #define DMA_SWREQ_CH7_Pos 7 /*!< Set software request on channel */ #define DMA_SWREQ_CH8_Pos 8 /*!< Set software request on channel */ #define DMA_SWREQ_CH9_Pos 9 /*!< Set software request on channel */ #define DMA_SWREQ_CH10_Pos 10 /*!< Set software request on channel */ #define DMA_SWREQ_CH11_Pos 11 /*!< Set software request on channel */ #define DMA_SWREQ_CH12_Pos 12 /*!< Set software request on channel */ #define DMA_SWREQ_CH13_Pos 13 /*!< Set software request on channel */ #define DMA_SWREQ_CH14_Pos 14 /*!< Set software request on channel */ #define DMA_SWREQ_CH15_Pos 15 /*!< Set software request on channel */ #define DMA_SWREQ_CH16_Pos 16 /*!< Set software request on channel */ #define DMA_SWREQ_CH17_Pos 17 /*!< Set software request on channel */ #define DMA_SWREQ_CH18_Pos 18 /*!< Set software request on channel */ #define DMA_SWREQ_CH19_Pos 19 /*!< Set software request on channel */ #define DMA_SWREQ_CH20_Pos 20 /*!< Set software request on channel */ #define DMA_SWREQ_CH21_Pos 21 /*!< Set software request on channel */ #define DMA_SWREQ_CH22_Pos 22 /*!< Set software request on channel */ #define DMA_SWREQ_CH23_Pos 23 /*!< Set software request on channel */ #define DMA_SWREQ_CH24_Pos 24 /*!< Set software request on channel */ #define DMA_SWREQ_CH25_Pos 25 /*!< Set software request on channel */ #define DMA_SWREQ_CH26_Pos 26 /*!< Set software request on channel */ #define DMA_SWREQ_CH27_Pos 27 /*!< Set software request on channel */ #define DMA_SWREQ_CH28_Pos 28 /*!< Set software request on channel */ #define DMA_SWREQ_CH29_Pos 29 /*!< Set software request on channel */ #define DMA_SWREQ_CH30_Pos 30 /*!< Set software request on channel */ #define DMA_SWREQ_CH31_Pos 31 /*!< Set software request on channel */ /* Bit field masks: */ #define DMA_SWREQ_CH0_Msk 0x00000001UL /*!< Set software request on channel */ #define DMA_SWREQ_CH1_Msk 0x00000002UL /*!< Set software request on channel */ #define DMA_SWREQ_CH2_Msk 0x00000004UL /*!< Set software request on channel */ #define DMA_SWREQ_CH3_Msk 0x00000008UL /*!< Set software request on channel */ #define DMA_SWREQ_CH4_Msk 0x00000010UL /*!< Set software request on channel */ #define DMA_SWREQ_CH5_Msk 0x00000020UL /*!< Set software request on channel */ #define DMA_SWREQ_CH6_Msk 0x00000040UL /*!< Set software request on channel */ #define DMA_SWREQ_CH7_Msk 0x00000080UL /*!< Set software request on channel */ #define DMA_SWREQ_CH8_Msk 0x00000100UL /*!< Set software request on channel */ #define DMA_SWREQ_CH9_Msk 0x00000200UL /*!< Set software request on channel */ #define DMA_SWREQ_CH10_Msk 0x00000400UL /*!< Set software request on channel */ #define DMA_SWREQ_CH11_Msk 0x00000800UL /*!< Set software request on channel */ #define DMA_SWREQ_CH12_Msk 0x00001000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH13_Msk 0x00002000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH14_Msk 0x00004000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH15_Msk 0x00008000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH16_Msk 0x00010000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH17_Msk 0x00020000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH18_Msk 0x00040000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH19_Msk 0x00080000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH20_Msk 0x00100000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH21_Msk 0x00200000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH22_Msk 0x00400000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH23_Msk 0x00800000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH24_Msk 0x01000000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH25_Msk 0x02000000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH26_Msk 0x04000000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH27_Msk 0x08000000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH28_Msk 0x10000000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH29_Msk 0x20000000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH30_Msk 0x40000000UL /*!< Set software request on channel */ #define DMA_SWREQ_CH31_Msk 0x80000000UL /*!< Set software request on channel */ /*-- USEBURSTSET: Channel useburst set -----------------------------------------------------------------------*/ typedef struct { uint32_t CH0 :1; /*!< Enable single requests */ uint32_t CH1 :1; /*!< Enable single requests */ uint32_t CH2 :1; /*!< Enable single requests */ uint32_t CH3 :1; /*!< Enable single requests */ uint32_t CH4 :1; /*!< Enable single requests */ uint32_t CH5 :1; /*!< Enable single requests */ uint32_t CH6 :1; /*!< Enable single requests */ uint32_t CH7 :1; /*!< Enable single requests */ uint32_t CH8 :1; /*!< Enable single requests */ uint32_t CH9 :1; /*!< Enable single requests */ uint32_t CH10 :1; /*!< Enable single requests */ uint32_t CH11 :1; /*!< Enable single requests */ uint32_t CH12 :1; /*!< Enable single requests */ uint32_t CH13 :1; /*!< Enable single requests */ uint32_t CH14 :1; /*!< Enable single requests */ uint32_t CH15 :1; /*!< Enable single requests */ uint32_t CH16 :1; /*!< Enable single requests */ uint32_t CH17 :1; /*!< Enable single requests */ uint32_t CH18 :1; /*!< Enable single requests */ uint32_t CH19 :1; /*!< Enable single requests */ uint32_t CH20 :1; /*!< Enable single requests */ uint32_t CH21 :1; /*!< Enable single requests */ uint32_t CH22 :1; /*!< Enable single requests */ uint32_t CH23 :1; /*!< Enable single requests */ uint32_t CH24 :1; /*!< Enable single requests */ uint32_t CH25 :1; /*!< Enable single requests */ uint32_t CH26 :1; /*!< Enable single requests */ uint32_t CH27 :1; /*!< Enable single requests */ uint32_t CH28 :1; /*!< Enable single requests */ uint32_t CH29 :1; /*!< Enable single requests */ uint32_t CH30 :1; /*!< Enable single requests */ uint32_t CH31 :1; /*!< Enable single requests */ } _DMA_USEBURSTSET_bits; /* Bit field positions: */ #define DMA_USEBURSTSET_CH0_Pos 0 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH1_Pos 1 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH2_Pos 2 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH3_Pos 3 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH4_Pos 4 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH5_Pos 5 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH6_Pos 6 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH7_Pos 7 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH8_Pos 8 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH9_Pos 9 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH10_Pos 10 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH11_Pos 11 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH12_Pos 12 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH13_Pos 13 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH14_Pos 14 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH15_Pos 15 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH16_Pos 16 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH17_Pos 17 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH18_Pos 18 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH19_Pos 19 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH20_Pos 20 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH21_Pos 21 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH22_Pos 22 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH23_Pos 23 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH24_Pos 24 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH25_Pos 25 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH26_Pos 26 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH27_Pos 27 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH28_Pos 28 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH29_Pos 29 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH30_Pos 30 /*!< Enable single requests */ #define DMA_USEBURSTSET_CH31_Pos 31 /*!< Enable single requests */ /* Bit field masks: */ #define DMA_USEBURSTSET_CH0_Msk 0x00000001UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH1_Msk 0x00000002UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH2_Msk 0x00000004UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH3_Msk 0x00000008UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH4_Msk 0x00000010UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH5_Msk 0x00000020UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH6_Msk 0x00000040UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH7_Msk 0x00000080UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH8_Msk 0x00000100UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH9_Msk 0x00000200UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH10_Msk 0x00000400UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH11_Msk 0x00000800UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH12_Msk 0x00001000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH13_Msk 0x00002000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH14_Msk 0x00004000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH15_Msk 0x00008000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH16_Msk 0x00010000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH17_Msk 0x00020000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH18_Msk 0x00040000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH19_Msk 0x00080000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH20_Msk 0x00100000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH21_Msk 0x00200000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH22_Msk 0x00400000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH23_Msk 0x00800000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH24_Msk 0x01000000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH25_Msk 0x02000000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH26_Msk 0x04000000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH27_Msk 0x08000000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH28_Msk 0x10000000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH29_Msk 0x20000000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH30_Msk 0x40000000UL /*!< Enable single requests */ #define DMA_USEBURSTSET_CH31_Msk 0x80000000UL /*!< Enable single requests */ /*-- USEBURSTCLR: Channel useburst clear ---------------------------------------------------------------------*/ typedef struct { uint32_t CH0 :1; /*!< Disable single requests */ uint32_t CH1 :1; /*!< Disable single requests */ uint32_t CH2 :1; /*!< Disable single requests */ uint32_t CH3 :1; /*!< Disable single requests */ uint32_t CH4 :1; /*!< Disable single requests */ uint32_t CH5 :1; /*!< Disable single requests */ uint32_t CH6 :1; /*!< Disable single requests */ uint32_t CH7 :1; /*!< Disable single requests */ uint32_t CH8 :1; /*!< Disable single requests */ uint32_t CH9 :1; /*!< Disable single requests */ uint32_t CH10 :1; /*!< Disable single requests */ uint32_t CH11 :1; /*!< Disable single requests */ uint32_t CH12 :1; /*!< Disable single requests */ uint32_t CH13 :1; /*!< Disable single requests */ uint32_t CH14 :1; /*!< Disable single requests */ uint32_t CH15 :1; /*!< Disable single requests */ uint32_t CH16 :1; /*!< Disable single requests */ uint32_t CH17 :1; /*!< Disable single requests */ uint32_t CH18 :1; /*!< Disable single requests */ uint32_t CH19 :1; /*!< Disable single requests */ uint32_t CH20 :1; /*!< Disable single requests */ uint32_t CH21 :1; /*!< Disable single requests */ uint32_t CH22 :1; /*!< Disable single requests */ uint32_t CH23 :1; /*!< Disable single requests */ uint32_t CH24 :1; /*!< Disable single requests */ uint32_t CH25 :1; /*!< Disable single requests */ uint32_t CH26 :1; /*!< Disable single requests */ uint32_t CH27 :1; /*!< Disable single requests */ uint32_t CH28 :1; /*!< Disable single requests */ uint32_t CH29 :1; /*!< Disable single requests */ uint32_t CH30 :1; /*!< Disable single requests */ uint32_t CH31 :1; /*!< Disable single requests */ } _DMA_USEBURSTCLR_bits; /* Bit field positions: */ #define DMA_USEBURSTCLR_CH0_Pos 0 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH1_Pos 1 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH2_Pos 2 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH3_Pos 3 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH4_Pos 4 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH5_Pos 5 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH6_Pos 6 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH7_Pos 7 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH8_Pos 8 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH9_Pos 9 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH10_Pos 10 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH11_Pos 11 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH12_Pos 12 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH13_Pos 13 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH14_Pos 14 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH15_Pos 15 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH16_Pos 16 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH17_Pos 17 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH18_Pos 18 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH19_Pos 19 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH20_Pos 20 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH21_Pos 21 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH22_Pos 22 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH23_Pos 23 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH24_Pos 24 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH25_Pos 25 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH26_Pos 26 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH27_Pos 27 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH28_Pos 28 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH29_Pos 29 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH30_Pos 30 /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH31_Pos 31 /*!< Disable single requests */ /* Bit field masks: */ #define DMA_USEBURSTCLR_CH0_Msk 0x00000001UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH1_Msk 0x00000002UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH2_Msk 0x00000004UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH3_Msk 0x00000008UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH4_Msk 0x00000010UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH5_Msk 0x00000020UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH6_Msk 0x00000040UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH7_Msk 0x00000080UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH8_Msk 0x00000100UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH9_Msk 0x00000200UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH10_Msk 0x00000400UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH11_Msk 0x00000800UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH12_Msk 0x00001000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH13_Msk 0x00002000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH14_Msk 0x00004000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH15_Msk 0x00008000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH16_Msk 0x00010000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH17_Msk 0x00020000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH18_Msk 0x00040000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH19_Msk 0x00080000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH20_Msk 0x00100000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH21_Msk 0x00200000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH22_Msk 0x00400000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH23_Msk 0x00800000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH24_Msk 0x01000000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH25_Msk 0x02000000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH26_Msk 0x04000000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH27_Msk 0x08000000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH28_Msk 0x10000000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH29_Msk 0x20000000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH30_Msk 0x40000000UL /*!< Disable single requests */ #define DMA_USEBURSTCLR_CH31_Msk 0x80000000UL /*!< Disable single requests */ /*-- REQMASKSET: Channel request mask set --------------------------------------------------------------------*/ typedef struct { uint32_t CH0 :1; /*!< External requests are enabled for channel */ uint32_t CH1 :1; /*!< External requests are enabled for channel */ uint32_t CH2 :1; /*!< External requests are enabled for channel */ uint32_t CH3 :1; /*!< External requests are enabled for channel */ uint32_t CH4 :1; /*!< External requests are enabled for channel */ uint32_t CH5 :1; /*!< External requests are enabled for channel */ uint32_t CH6 :1; /*!< External requests are enabled for channel */ uint32_t CH7 :1; /*!< External requests are enabled for channel */ uint32_t CH8 :1; /*!< External requests are enabled for channel */ uint32_t CH9 :1; /*!< External requests are enabled for channel */ uint32_t CH10 :1; /*!< External requests are enabled for channel */ uint32_t CH11 :1; /*!< External requests are enabled for channel */ uint32_t CH12 :1; /*!< External requests are enabled for channel */ uint32_t CH13 :1; /*!< External requests are enabled for channel */ uint32_t CH14 :1; /*!< External requests are enabled for channel */ uint32_t CH15 :1; /*!< External requests are enabled for channel */ uint32_t CH16 :1; /*!< External requests are enabled for channel */ uint32_t CH17 :1; /*!< External requests are enabled for channel */ uint32_t CH18 :1; /*!< External requests are enabled for channel */ uint32_t CH19 :1; /*!< External requests are enabled for channel */ uint32_t CH20 :1; /*!< External requests are enabled for channel */ uint32_t CH21 :1; /*!< External requests are enabled for channel */ uint32_t CH22 :1; /*!< External requests are enabled for channel */ uint32_t CH23 :1; /*!< External requests are enabled for channel */ uint32_t CH24 :1; /*!< External requests are enabled for channel */ uint32_t CH25 :1; /*!< External requests are enabled for channel */ uint32_t CH26 :1; /*!< External requests are enabled for channel */ uint32_t CH27 :1; /*!< External requests are enabled for channel */ uint32_t CH28 :1; /*!< External requests are enabled for channel */ uint32_t CH29 :1; /*!< External requests are enabled for channel */ uint32_t CH30 :1; /*!< External requests are enabled for channel */ uint32_t CH31 :1; /*!< External requests are enabled for channel */ } _DMA_REQMASKSET_bits; /* Bit field positions: */ #define DMA_REQMASKSET_CH0_Pos 0 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH1_Pos 1 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH2_Pos 2 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH3_Pos 3 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH4_Pos 4 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH5_Pos 5 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH6_Pos 6 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH7_Pos 7 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH8_Pos 8 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH9_Pos 9 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH10_Pos 10 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH11_Pos 11 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH12_Pos 12 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH13_Pos 13 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH14_Pos 14 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH15_Pos 15 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH16_Pos 16 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH17_Pos 17 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH18_Pos 18 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH19_Pos 19 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH20_Pos 20 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH21_Pos 21 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH22_Pos 22 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH23_Pos 23 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH24_Pos 24 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH25_Pos 25 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH26_Pos 26 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH27_Pos 27 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH28_Pos 28 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH29_Pos 29 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH30_Pos 30 /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH31_Pos 31 /*!< External requests are enabled for channel */ /* Bit field masks: */ #define DMA_REQMASKSET_CH0_Msk 0x00000001UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH1_Msk 0x00000002UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH2_Msk 0x00000004UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH3_Msk 0x00000008UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH4_Msk 0x00000010UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH5_Msk 0x00000020UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH6_Msk 0x00000040UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH7_Msk 0x00000080UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH8_Msk 0x00000100UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH9_Msk 0x00000200UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH10_Msk 0x00000400UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH11_Msk 0x00000800UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH12_Msk 0x00001000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH13_Msk 0x00002000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH14_Msk 0x00004000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH15_Msk 0x00008000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH16_Msk 0x00010000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH17_Msk 0x00020000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH18_Msk 0x00040000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH19_Msk 0x00080000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH20_Msk 0x00100000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH21_Msk 0x00200000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH22_Msk 0x00400000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH23_Msk 0x00800000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH24_Msk 0x01000000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH25_Msk 0x02000000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH26_Msk 0x04000000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH27_Msk 0x08000000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH28_Msk 0x10000000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH29_Msk 0x20000000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH30_Msk 0x40000000UL /*!< External requests are enabled for channel */ #define DMA_REQMASKSET_CH31_Msk 0x80000000UL /*!< External requests are enabled for channel */ /*-- REQMASKCLR: Channel request mask clear ------------------------------------------------------------------*/ typedef struct { uint32_t CH0 :1; /*!< External requests are disabled for channel */ uint32_t CH1 :1; /*!< External requests are disabled for channel */ uint32_t CH2 :1; /*!< External requests are disabled for channel */ uint32_t CH3 :1; /*!< External requests are disabled for channel */ uint32_t CH4 :1; /*!< External requests are disabled for channel */ uint32_t CH5 :1; /*!< External requests are disabled for channel */ uint32_t CH6 :1; /*!< External requests are disabled for channel */ uint32_t CH7 :1; /*!< External requests are disabled for channel */ uint32_t CH8 :1; /*!< External requests are disabled for channel */ uint32_t CH9 :1; /*!< External requests are disabled for channel */ uint32_t CH10 :1; /*!< External requests are disabled for channel */ uint32_t CH11 :1; /*!< External requests are disabled for channel */ uint32_t CH12 :1; /*!< External requests are disabled for channel */ uint32_t CH13 :1; /*!< External requests are disabled for channel */ uint32_t CH14 :1; /*!< External requests are disabled for channel */ uint32_t CH15 :1; /*!< External requests are disabled for channel */ uint32_t CH16 :1; /*!< External requests are disabled for channel */ uint32_t CH17 :1; /*!< External requests are disabled for channel */ uint32_t CH18 :1; /*!< External requests are disabled for channel */ uint32_t CH19 :1; /*!< External requests are disabled for channel */ uint32_t CH20 :1; /*!< External requests are disabled for channel */ uint32_t CH21 :1; /*!< External requests are disabled for channel */ uint32_t CH22 :1; /*!< External requests are disabled for channel */ uint32_t CH23 :1; /*!< External requests are disabled for channel */ uint32_t CH24 :1; /*!< External requests are disabled for channel */ uint32_t CH25 :1; /*!< External requests are disabled for channel */ uint32_t CH26 :1; /*!< External requests are disabled for channel */ uint32_t CH27 :1; /*!< External requests are disabled for channel */ uint32_t CH28 :1; /*!< External requests are disabled for channel */ uint32_t CH29 :1; /*!< External requests are disabled for channel */ uint32_t CH30 :1; /*!< External requests are disabled for channel */ uint32_t CH31 :1; /*!< External requests are disabled for channel */ } _DMA_REQMASKCLR_bits; /* Bit field positions: */ #define DMA_REQMASKCLR_CH0_Pos 0 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH1_Pos 1 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH2_Pos 2 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH3_Pos 3 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH4_Pos 4 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH5_Pos 5 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH6_Pos 6 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH7_Pos 7 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH8_Pos 8 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH9_Pos 9 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH10_Pos 10 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH11_Pos 11 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH12_Pos 12 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH13_Pos 13 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH14_Pos 14 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH15_Pos 15 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH16_Pos 16 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH17_Pos 17 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH18_Pos 18 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH19_Pos 19 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH20_Pos 20 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH21_Pos 21 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH22_Pos 22 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH23_Pos 23 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH24_Pos 24 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH25_Pos 25 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH26_Pos 26 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH27_Pos 27 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH28_Pos 28 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH29_Pos 29 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH30_Pos 30 /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH31_Pos 31 /*!< External requests are disabled for channel */ /* Bit field masks: */ #define DMA_REQMASKCLR_CH0_Msk 0x00000001UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH1_Msk 0x00000002UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH2_Msk 0x00000004UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH3_Msk 0x00000008UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH4_Msk 0x00000010UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH5_Msk 0x00000020UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH6_Msk 0x00000040UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH7_Msk 0x00000080UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH8_Msk 0x00000100UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH9_Msk 0x00000200UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH10_Msk 0x00000400UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH11_Msk 0x00000800UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH12_Msk 0x00001000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH13_Msk 0x00002000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH14_Msk 0x00004000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH15_Msk 0x00008000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH16_Msk 0x00010000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH17_Msk 0x00020000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH18_Msk 0x00040000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH19_Msk 0x00080000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH20_Msk 0x00100000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH21_Msk 0x00200000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH22_Msk 0x00400000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH23_Msk 0x00800000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH24_Msk 0x01000000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH25_Msk 0x02000000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH26_Msk 0x04000000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH27_Msk 0x08000000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH28_Msk 0x10000000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH29_Msk 0x20000000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH30_Msk 0x40000000UL /*!< External requests are disabled for channel */ #define DMA_REQMASKCLR_CH31_Msk 0x80000000UL /*!< External requests are disabled for channel */ /*-- ENSET: Channel enable set -------------------------------------------------------------------------------*/ typedef struct { uint32_t CH0 :1; /*!< Enable channel */ uint32_t CH1 :1; /*!< Enable channel */ uint32_t CH2 :1; /*!< Enable channel */ uint32_t CH3 :1; /*!< Enable channel */ uint32_t CH4 :1; /*!< Enable channel */ uint32_t CH5 :1; /*!< Enable channel */ uint32_t CH6 :1; /*!< Enable channel */ uint32_t CH7 :1; /*!< Enable channel */ uint32_t CH8 :1; /*!< Enable channel */ uint32_t CH9 :1; /*!< Enable channel */ uint32_t CH10 :1; /*!< Enable channel */ uint32_t CH11 :1; /*!< Enable channel */ uint32_t CH12 :1; /*!< Enable channel */ uint32_t CH13 :1; /*!< Enable channel */ uint32_t CH14 :1; /*!< Enable channel */ uint32_t CH15 :1; /*!< Enable channel */ uint32_t CH16 :1; /*!< Enable channel */ uint32_t CH17 :1; /*!< Enable channel */ uint32_t CH18 :1; /*!< Enable channel */ uint32_t CH19 :1; /*!< Enable channel */ uint32_t CH20 :1; /*!< Enable channel */ uint32_t CH21 :1; /*!< Enable channel */ uint32_t CH22 :1; /*!< Enable channel */ uint32_t CH23 :1; /*!< Enable channel */ uint32_t CH24 :1; /*!< Enable channel */ uint32_t CH25 :1; /*!< Enable channel */ uint32_t CH26 :1; /*!< Enable channel */ uint32_t CH27 :1; /*!< Enable channel */ uint32_t CH28 :1; /*!< Enable channel */ uint32_t CH29 :1; /*!< Enable channel */ uint32_t CH30 :1; /*!< Enable channel */ uint32_t CH31 :1; /*!< Enable channel */ } _DMA_ENSET_bits; /* Bit field positions: */ #define DMA_ENSET_CH0_Pos 0 /*!< Enable channel */ #define DMA_ENSET_CH1_Pos 1 /*!< Enable channel */ #define DMA_ENSET_CH2_Pos 2 /*!< Enable channel */ #define DMA_ENSET_CH3_Pos 3 /*!< Enable channel */ #define DMA_ENSET_CH4_Pos 4 /*!< Enable channel */ #define DMA_ENSET_CH5_Pos 5 /*!< Enable channel */ #define DMA_ENSET_CH6_Pos 6 /*!< Enable channel */ #define DMA_ENSET_CH7_Pos 7 /*!< Enable channel */ #define DMA_ENSET_CH8_Pos 8 /*!< Enable channel */ #define DMA_ENSET_CH9_Pos 9 /*!< Enable channel */ #define DMA_ENSET_CH10_Pos 10 /*!< Enable channel */ #define DMA_ENSET_CH11_Pos 11 /*!< Enable channel */ #define DMA_ENSET_CH12_Pos 12 /*!< Enable channel */ #define DMA_ENSET_CH13_Pos 13 /*!< Enable channel */ #define DMA_ENSET_CH14_Pos 14 /*!< Enable channel */ #define DMA_ENSET_CH15_Pos 15 /*!< Enable channel */ #define DMA_ENSET_CH16_Pos 16 /*!< Enable channel */ #define DMA_ENSET_CH17_Pos 17 /*!< Enable channel */ #define DMA_ENSET_CH18_Pos 18 /*!< Enable channel */ #define DMA_ENSET_CH19_Pos 19 /*!< Enable channel */ #define DMA_ENSET_CH20_Pos 20 /*!< Enable channel */ #define DMA_ENSET_CH21_Pos 21 /*!< Enable channel */ #define DMA_ENSET_CH22_Pos 22 /*!< Enable channel */ #define DMA_ENSET_CH23_Pos 23 /*!< Enable channel */ #define DMA_ENSET_CH24_Pos 24 /*!< Enable channel */ #define DMA_ENSET_CH25_Pos 25 /*!< Enable channel */ #define DMA_ENSET_CH26_Pos 26 /*!< Enable channel */ #define DMA_ENSET_CH27_Pos 27 /*!< Enable channel */ #define DMA_ENSET_CH28_Pos 28 /*!< Enable channel */ #define DMA_ENSET_CH29_Pos 29 /*!< Enable channel */ #define DMA_ENSET_CH30_Pos 30 /*!< Enable channel */ #define DMA_ENSET_CH31_Pos 31 /*!< Enable channel */ /* Bit field masks: */ #define DMA_ENSET_CH0_Msk 0x00000001UL /*!< Enable channel */ #define DMA_ENSET_CH1_Msk 0x00000002UL /*!< Enable channel */ #define DMA_ENSET_CH2_Msk 0x00000004UL /*!< Enable channel */ #define DMA_ENSET_CH3_Msk 0x00000008UL /*!< Enable channel */ #define DMA_ENSET_CH4_Msk 0x00000010UL /*!< Enable channel */ #define DMA_ENSET_CH5_Msk 0x00000020UL /*!< Enable channel */ #define DMA_ENSET_CH6_Msk 0x00000040UL /*!< Enable channel */ #define DMA_ENSET_CH7_Msk 0x00000080UL /*!< Enable channel */ #define DMA_ENSET_CH8_Msk 0x00000100UL /*!< Enable channel */ #define DMA_ENSET_CH9_Msk 0x00000200UL /*!< Enable channel */ #define DMA_ENSET_CH10_Msk 0x00000400UL /*!< Enable channel */ #define DMA_ENSET_CH11_Msk 0x00000800UL /*!< Enable channel */ #define DMA_ENSET_CH12_Msk 0x00001000UL /*!< Enable channel */ #define DMA_ENSET_CH13_Msk 0x00002000UL /*!< Enable channel */ #define DMA_ENSET_CH14_Msk 0x00004000UL /*!< Enable channel */ #define DMA_ENSET_CH15_Msk 0x00008000UL /*!< Enable channel */ #define DMA_ENSET_CH16_Msk 0x00010000UL /*!< Enable channel */ #define DMA_ENSET_CH17_Msk 0x00020000UL /*!< Enable channel */ #define DMA_ENSET_CH18_Msk 0x00040000UL /*!< Enable channel */ #define DMA_ENSET_CH19_Msk 0x00080000UL /*!< Enable channel */ #define DMA_ENSET_CH20_Msk 0x00100000UL /*!< Enable channel */ #define DMA_ENSET_CH21_Msk 0x00200000UL /*!< Enable channel */ #define DMA_ENSET_CH22_Msk 0x00400000UL /*!< Enable channel */ #define DMA_ENSET_CH23_Msk 0x00800000UL /*!< Enable channel */ #define DMA_ENSET_CH24_Msk 0x01000000UL /*!< Enable channel */ #define DMA_ENSET_CH25_Msk 0x02000000UL /*!< Enable channel */ #define DMA_ENSET_CH26_Msk 0x04000000UL /*!< Enable channel */ #define DMA_ENSET_CH27_Msk 0x08000000UL /*!< Enable channel */ #define DMA_ENSET_CH28_Msk 0x10000000UL /*!< Enable channel */ #define DMA_ENSET_CH29_Msk 0x20000000UL /*!< Enable channel */ #define DMA_ENSET_CH30_Msk 0x40000000UL /*!< Enable channel */ #define DMA_ENSET_CH31_Msk 0x80000000UL /*!< Enable channel */ /*-- ENCLR: Channel enable clear -----------------------------------------------------------------------------*/ typedef struct { uint32_t CH0 :1; /*!< Disable channel */ uint32_t CH1 :1; /*!< Disable channel */ uint32_t CH2 :1; /*!< Disable channel */ uint32_t CH3 :1; /*!< Disable channel */ uint32_t CH4 :1; /*!< Disable channel */ uint32_t CH5 :1; /*!< Disable channel */ uint32_t CH6 :1; /*!< Disable channel */ uint32_t CH7 :1; /*!< Disable channel */ uint32_t CH8 :1; /*!< Disable channel */ uint32_t CH9 :1; /*!< Disable channel */ uint32_t CH10 :1; /*!< Disable channel */ uint32_t CH11 :1; /*!< Disable channel */ uint32_t CH12 :1; /*!< Disable channel */ uint32_t CH13 :1; /*!< Disable channel */ uint32_t CH14 :1; /*!< Disable channel */ uint32_t CH15 :1; /*!< Disable channel */ uint32_t CH16 :1; /*!< Disable channel */ uint32_t CH17 :1; /*!< Disable channel */ uint32_t CH18 :1; /*!< Disable channel */ uint32_t CH19 :1; /*!< Disable channel */ uint32_t CH20 :1; /*!< Disable channel */ uint32_t CH21 :1; /*!< Disable channel */ uint32_t CH22 :1; /*!< Disable channel */ uint32_t CH23 :1; /*!< Disable channel */ uint32_t CH24 :1; /*!< Disable channel */ uint32_t CH25 :1; /*!< Disable channel */ uint32_t CH26 :1; /*!< Disable channel */ uint32_t CH27 :1; /*!< Disable channel */ uint32_t CH28 :1; /*!< Disable channel */ uint32_t CH29 :1; /*!< Disable channel */ uint32_t CH30 :1; /*!< Disable channel */ uint32_t CH31 :1; /*!< Disable channel */ } _DMA_ENCLR_bits; /* Bit field positions: */ #define DMA_ENCLR_CH0_Pos 0 /*!< Disable channel */ #define DMA_ENCLR_CH1_Pos 1 /*!< Disable channel */ #define DMA_ENCLR_CH2_Pos 2 /*!< Disable channel */ #define DMA_ENCLR_CH3_Pos 3 /*!< Disable channel */ #define DMA_ENCLR_CH4_Pos 4 /*!< Disable channel */ #define DMA_ENCLR_CH5_Pos 5 /*!< Disable channel */ #define DMA_ENCLR_CH6_Pos 6 /*!< Disable channel */ #define DMA_ENCLR_CH7_Pos 7 /*!< Disable channel */ #define DMA_ENCLR_CH8_Pos 8 /*!< Disable channel */ #define DMA_ENCLR_CH9_Pos 9 /*!< Disable channel */ #define DMA_ENCLR_CH10_Pos 10 /*!< Disable channel */ #define DMA_ENCLR_CH11_Pos 11 /*!< Disable channel */ #define DMA_ENCLR_CH12_Pos 12 /*!< Disable channel */ #define DMA_ENCLR_CH13_Pos 13 /*!< Disable channel */ #define DMA_ENCLR_CH14_Pos 14 /*!< Disable channel */ #define DMA_ENCLR_CH15_Pos 15 /*!< Disable channel */ #define DMA_ENCLR_CH16_Pos 16 /*!< Disable channel */ #define DMA_ENCLR_CH17_Pos 17 /*!< Disable channel */ #define DMA_ENCLR_CH18_Pos 18 /*!< Disable channel */ #define DMA_ENCLR_CH19_Pos 19 /*!< Disable channel */ #define DMA_ENCLR_CH20_Pos 20 /*!< Disable channel */ #define DMA_ENCLR_CH21_Pos 21 /*!< Disable channel */ #define DMA_ENCLR_CH22_Pos 22 /*!< Disable channel */ #define DMA_ENCLR_CH23_Pos 23 /*!< Disable channel */ #define DMA_ENCLR_CH24_Pos 24 /*!< Disable channel */ #define DMA_ENCLR_CH25_Pos 25 /*!< Disable channel */ #define DMA_ENCLR_CH26_Pos 26 /*!< Disable channel */ #define DMA_ENCLR_CH27_Pos 27 /*!< Disable channel */ #define DMA_ENCLR_CH28_Pos 28 /*!< Disable channel */ #define DMA_ENCLR_CH29_Pos 29 /*!< Disable channel */ #define DMA_ENCLR_CH30_Pos 30 /*!< Disable channel */ #define DMA_ENCLR_CH31_Pos 31 /*!< Disable channel */ /* Bit field masks: */ #define DMA_ENCLR_CH0_Msk 0x00000001UL /*!< Disable channel */ #define DMA_ENCLR_CH1_Msk 0x00000002UL /*!< Disable channel */ #define DMA_ENCLR_CH2_Msk 0x00000004UL /*!< Disable channel */ #define DMA_ENCLR_CH3_Msk 0x00000008UL /*!< Disable channel */ #define DMA_ENCLR_CH4_Msk 0x00000010UL /*!< Disable channel */ #define DMA_ENCLR_CH5_Msk 0x00000020UL /*!< Disable channel */ #define DMA_ENCLR_CH6_Msk 0x00000040UL /*!< Disable channel */ #define DMA_ENCLR_CH7_Msk 0x00000080UL /*!< Disable channel */ #define DMA_ENCLR_CH8_Msk 0x00000100UL /*!< Disable channel */ #define DMA_ENCLR_CH9_Msk 0x00000200UL /*!< Disable channel */ #define DMA_ENCLR_CH10_Msk 0x00000400UL /*!< Disable channel */ #define DMA_ENCLR_CH11_Msk 0x00000800UL /*!< Disable channel */ #define DMA_ENCLR_CH12_Msk 0x00001000UL /*!< Disable channel */ #define DMA_ENCLR_CH13_Msk 0x00002000UL /*!< Disable channel */ #define DMA_ENCLR_CH14_Msk 0x00004000UL /*!< Disable channel */ #define DMA_ENCLR_CH15_Msk 0x00008000UL /*!< Disable channel */ #define DMA_ENCLR_CH16_Msk 0x00010000UL /*!< Disable channel */ #define DMA_ENCLR_CH17_Msk 0x00020000UL /*!< Disable channel */ #define DMA_ENCLR_CH18_Msk 0x00040000UL /*!< Disable channel */ #define DMA_ENCLR_CH19_Msk 0x00080000UL /*!< Disable channel */ #define DMA_ENCLR_CH20_Msk 0x00100000UL /*!< Disable channel */ #define DMA_ENCLR_CH21_Msk 0x00200000UL /*!< Disable channel */ #define DMA_ENCLR_CH22_Msk 0x00400000UL /*!< Disable channel */ #define DMA_ENCLR_CH23_Msk 0x00800000UL /*!< Disable channel */ #define DMA_ENCLR_CH24_Msk 0x01000000UL /*!< Disable channel */ #define DMA_ENCLR_CH25_Msk 0x02000000UL /*!< Disable channel */ #define DMA_ENCLR_CH26_Msk 0x04000000UL /*!< Disable channel */ #define DMA_ENCLR_CH27_Msk 0x08000000UL /*!< Disable channel */ #define DMA_ENCLR_CH28_Msk 0x10000000UL /*!< Disable channel */ #define DMA_ENCLR_CH29_Msk 0x20000000UL /*!< Disable channel */ #define DMA_ENCLR_CH30_Msk 0x40000000UL /*!< Disable channel */ #define DMA_ENCLR_CH31_Msk 0x80000000UL /*!< Disable channel */ /*-- PRIALTSET: Channel primary-alternate set ----------------------------------------------------------------*/ typedef struct { uint32_t CH0 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH1 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH2 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH3 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH4 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH5 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH6 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH7 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH8 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH9 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH10 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH11 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH12 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH13 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH14 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH15 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH16 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH17 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH18 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH19 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH20 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH21 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH22 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH23 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH24 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH25 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH26 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH27 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH28 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH29 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH30 :1; /*!< Set primary / alternate channel control data structure */ uint32_t CH31 :1; /*!< Set primary / alternate channel control data structure */ } _DMA_PRIALTSET_bits; /* Bit field positions: */ #define DMA_PRIALTSET_CH0_Pos 0 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH1_Pos 1 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH2_Pos 2 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH3_Pos 3 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH4_Pos 4 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH5_Pos 5 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH6_Pos 6 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH7_Pos 7 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH8_Pos 8 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH9_Pos 9 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH10_Pos 10 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH11_Pos 11 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH12_Pos 12 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH13_Pos 13 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH14_Pos 14 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH15_Pos 15 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH16_Pos 16 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH17_Pos 17 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH18_Pos 18 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH19_Pos 19 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH20_Pos 20 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH21_Pos 21 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH22_Pos 22 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH23_Pos 23 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH24_Pos 24 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH25_Pos 25 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH26_Pos 26 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH27_Pos 27 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH28_Pos 28 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH29_Pos 29 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH30_Pos 30 /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH31_Pos 31 /*!< Set primary / alternate channel control data structure */ /* Bit field masks: */ #define DMA_PRIALTSET_CH0_Msk 0x00000001UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH1_Msk 0x00000002UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH2_Msk 0x00000004UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH3_Msk 0x00000008UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH4_Msk 0x00000010UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH5_Msk 0x00000020UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH6_Msk 0x00000040UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH7_Msk 0x00000080UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH8_Msk 0x00000100UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH9_Msk 0x00000200UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH10_Msk 0x00000400UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH11_Msk 0x00000800UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH12_Msk 0x00001000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH13_Msk 0x00002000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH14_Msk 0x00004000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH15_Msk 0x00008000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH16_Msk 0x00010000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH17_Msk 0x00020000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH18_Msk 0x00040000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH19_Msk 0x00080000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH20_Msk 0x00100000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH21_Msk 0x00200000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH22_Msk 0x00400000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH23_Msk 0x00800000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH24_Msk 0x01000000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH25_Msk 0x02000000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH26_Msk 0x04000000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH27_Msk 0x08000000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH28_Msk 0x10000000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH29_Msk 0x20000000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH30_Msk 0x40000000UL /*!< Set primary / alternate channel control data structure */ #define DMA_PRIALTSET_CH31_Msk 0x80000000UL /*!< Set primary / alternate channel control data structure */ /*-- PRIALTCLR: Channel primary-alternate clear --------------------------------------------------------------*/ typedef struct { uint32_t CH0 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH1 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH2 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH3 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH4 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH5 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH6 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH7 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH8 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH9 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH10 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH11 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH12 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH13 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH14 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH15 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH16 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH17 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH18 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH19 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH20 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH21 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH22 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH23 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH24 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH25 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH26 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH27 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH28 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH29 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH30 :1; /*!< Clear primary / alternate channel control data structure */ uint32_t CH31 :1; /*!< Clear primary / alternate channel control data structure */ } _DMA_PRIALTCLR_bits; /* Bit field positions: */ #define DMA_PRIALTCLR_CH0_Pos 0 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH1_Pos 1 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH2_Pos 2 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH3_Pos 3 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH4_Pos 4 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH5_Pos 5 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH6_Pos 6 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH7_Pos 7 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH8_Pos 8 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH9_Pos 9 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH10_Pos 10 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH11_Pos 11 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH12_Pos 12 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH13_Pos 13 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH14_Pos 14 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH15_Pos 15 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH16_Pos 16 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH17_Pos 17 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH18_Pos 18 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH19_Pos 19 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH20_Pos 20 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH21_Pos 21 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH22_Pos 22 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH23_Pos 23 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH24_Pos 24 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH25_Pos 25 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH26_Pos 26 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH27_Pos 27 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH28_Pos 28 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH29_Pos 29 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH30_Pos 30 /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH31_Pos 31 /*!< Clear primary / alternate channel control data structure */ /* Bit field masks: */ #define DMA_PRIALTCLR_CH0_Msk 0x00000001UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH1_Msk 0x00000002UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH2_Msk 0x00000004UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH3_Msk 0x00000008UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH4_Msk 0x00000010UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH5_Msk 0x00000020UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH6_Msk 0x00000040UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH7_Msk 0x00000080UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH8_Msk 0x00000100UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH9_Msk 0x00000200UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH10_Msk 0x00000400UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH11_Msk 0x00000800UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH12_Msk 0x00001000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH13_Msk 0x00002000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH14_Msk 0x00004000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH15_Msk 0x00008000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH16_Msk 0x00010000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH17_Msk 0x00020000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH18_Msk 0x00040000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH19_Msk 0x00080000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH20_Msk 0x00100000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH21_Msk 0x00200000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH22_Msk 0x00400000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH23_Msk 0x00800000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH24_Msk 0x01000000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH25_Msk 0x02000000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH26_Msk 0x04000000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH27_Msk 0x08000000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH28_Msk 0x10000000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH29_Msk 0x20000000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH30_Msk 0x40000000UL /*!< Clear primary / alternate channel control data structure */ #define DMA_PRIALTCLR_CH31_Msk 0x80000000UL /*!< Clear primary / alternate channel control data structure */ /*-- PRIORITYSET: Channel priority set -----------------------------------------------------------------------*/ typedef struct { uint32_t CH0 :1; /*!< Set the priority of channel */ uint32_t CH1 :1; /*!< Set the priority of channel */ uint32_t CH2 :1; /*!< Set the priority of channel */ uint32_t CH3 :1; /*!< Set the priority of channel */ uint32_t CH4 :1; /*!< Set the priority of channel */ uint32_t CH5 :1; /*!< Set the priority of channel */ uint32_t CH6 :1; /*!< Set the priority of channel */ uint32_t CH7 :1; /*!< Set the priority of channel */ uint32_t CH8 :1; /*!< Set the priority of channel */ uint32_t CH9 :1; /*!< Set the priority of channel */ uint32_t CH10 :1; /*!< Set the priority of channel */ uint32_t CH11 :1; /*!< Set the priority of channel */ uint32_t CH12 :1; /*!< Set the priority of channel */ uint32_t CH13 :1; /*!< Set the priority of channel */ uint32_t CH14 :1; /*!< Set the priority of channel */ uint32_t CH15 :1; /*!< Set the priority of channel */ uint32_t CH16 :1; /*!< Set the priority of channel */ uint32_t CH17 :1; /*!< Set the priority of channel */ uint32_t CH18 :1; /*!< Set the priority of channel */ uint32_t CH19 :1; /*!< Set the priority of channel */ uint32_t CH20 :1; /*!< Set the priority of channel */ uint32_t CH21 :1; /*!< Set the priority of channel */ uint32_t CH22 :1; /*!< Set the priority of channel */ uint32_t CH23 :1; /*!< Set the priority of channel */ uint32_t CH24 :1; /*!< Set the priority of channel */ uint32_t CH25 :1; /*!< Set the priority of channel */ uint32_t CH26 :1; /*!< Set the priority of channel */ uint32_t CH27 :1; /*!< Set the priority of channel */ uint32_t CH28 :1; /*!< Set the priority of channel */ uint32_t CH29 :1; /*!< Set the priority of channel */ uint32_t CH30 :1; /*!< Set the priority of channel */ uint32_t CH31 :1; /*!< Set the priority of channel */ } _DMA_PRIORITYSET_bits; /* Bit field positions: */ #define DMA_PRIORITYSET_CH0_Pos 0 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH1_Pos 1 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH2_Pos 2 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH3_Pos 3 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH4_Pos 4 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH5_Pos 5 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH6_Pos 6 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH7_Pos 7 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH8_Pos 8 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH9_Pos 9 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH10_Pos 10 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH11_Pos 11 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH12_Pos 12 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH13_Pos 13 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH14_Pos 14 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH15_Pos 15 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH16_Pos 16 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH17_Pos 17 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH18_Pos 18 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH19_Pos 19 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH20_Pos 20 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH21_Pos 21 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH22_Pos 22 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH23_Pos 23 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH24_Pos 24 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH25_Pos 25 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH26_Pos 26 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH27_Pos 27 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH28_Pos 28 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH29_Pos 29 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH30_Pos 30 /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH31_Pos 31 /*!< Set the priority of channel */ /* Bit field masks: */ #define DMA_PRIORITYSET_CH0_Msk 0x00000001UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH1_Msk 0x00000002UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH2_Msk 0x00000004UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH3_Msk 0x00000008UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH4_Msk 0x00000010UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH5_Msk 0x00000020UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH6_Msk 0x00000040UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH7_Msk 0x00000080UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH8_Msk 0x00000100UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH9_Msk 0x00000200UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH10_Msk 0x00000400UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH11_Msk 0x00000800UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH12_Msk 0x00001000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH13_Msk 0x00002000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH14_Msk 0x00004000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH15_Msk 0x00008000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH16_Msk 0x00010000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH17_Msk 0x00020000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH18_Msk 0x00040000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH19_Msk 0x00080000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH20_Msk 0x00100000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH21_Msk 0x00200000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH22_Msk 0x00400000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH23_Msk 0x00800000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH24_Msk 0x01000000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH25_Msk 0x02000000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH26_Msk 0x04000000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH27_Msk 0x08000000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH28_Msk 0x10000000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH29_Msk 0x20000000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH30_Msk 0x40000000UL /*!< Set the priority of channel */ #define DMA_PRIORITYSET_CH31_Msk 0x80000000UL /*!< Set the priority of channel */ /*-- PRIORITYCLR: Channel priority clear ---------------------------------------------------------------------*/ typedef struct { uint32_t CH0 :1; /*!< Clear the priority */ uint32_t CH1 :1; /*!< Clear the priority */ uint32_t CH2 :1; /*!< Clear the priority */ uint32_t CH3 :1; /*!< Clear the priority */ uint32_t CH4 :1; /*!< Clear the priority */ uint32_t CH5 :1; /*!< Clear the priority */ uint32_t CH6 :1; /*!< Clear the priority */ uint32_t CH7 :1; /*!< Clear the priority */ uint32_t CH8 :1; /*!< Clear the priority */ uint32_t CH9 :1; /*!< Clear the priority */ uint32_t CH10 :1; /*!< Clear the priority */ uint32_t CH11 :1; /*!< Clear the priority */ uint32_t CH12 :1; /*!< Clear the priority */ uint32_t CH13 :1; /*!< Clear the priority */ uint32_t CH14 :1; /*!< Clear the priority */ uint32_t CH15 :1; /*!< Clear the priority */ uint32_t CH16 :1; /*!< Clear the priority */ uint32_t CH17 :1; /*!< Clear the priority */ uint32_t CH18 :1; /*!< Clear the priority */ uint32_t CH19 :1; /*!< Clear the priority */ uint32_t CH20 :1; /*!< Clear the priority */ uint32_t CH21 :1; /*!< Clear the priority */ uint32_t CH22 :1; /*!< Clear the priority */ uint32_t CH23 :1; /*!< Clear the priority */ uint32_t CH24 :1; /*!< Clear the priority */ uint32_t CH25 :1; /*!< Clear the priority */ uint32_t CH26 :1; /*!< Clear the priority */ uint32_t CH27 :1; /*!< Clear the priority */ uint32_t CH28 :1; /*!< Clear the priority */ uint32_t CH29 :1; /*!< Clear the priority */ uint32_t CH30 :1; /*!< Clear the priority */ uint32_t CH31 :1; /*!< Clear the priority */ } _DMA_PRIORITYCLR_bits; /* Bit field positions: */ #define DMA_PRIORITYCLR_CH0_Pos 0 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH1_Pos 1 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH2_Pos 2 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH3_Pos 3 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH4_Pos 4 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH5_Pos 5 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH6_Pos 6 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH7_Pos 7 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH8_Pos 8 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH9_Pos 9 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH10_Pos 10 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH11_Pos 11 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH12_Pos 12 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH13_Pos 13 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH14_Pos 14 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH15_Pos 15 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH16_Pos 16 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH17_Pos 17 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH18_Pos 18 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH19_Pos 19 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH20_Pos 20 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH21_Pos 21 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH22_Pos 22 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH23_Pos 23 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH24_Pos 24 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH25_Pos 25 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH26_Pos 26 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH27_Pos 27 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH28_Pos 28 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH29_Pos 29 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH30_Pos 30 /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH31_Pos 31 /*!< Clear the priority */ /* Bit field masks: */ #define DMA_PRIORITYCLR_CH0_Msk 0x00000001UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH1_Msk 0x00000002UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH2_Msk 0x00000004UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH3_Msk 0x00000008UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH4_Msk 0x00000010UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH5_Msk 0x00000020UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH6_Msk 0x00000040UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH7_Msk 0x00000080UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH8_Msk 0x00000100UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH9_Msk 0x00000200UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH10_Msk 0x00000400UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH11_Msk 0x00000800UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH12_Msk 0x00001000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH13_Msk 0x00002000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH14_Msk 0x00004000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH15_Msk 0x00008000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH16_Msk 0x00010000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH17_Msk 0x00020000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH18_Msk 0x00040000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH19_Msk 0x00080000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH20_Msk 0x00100000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH21_Msk 0x00200000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH22_Msk 0x00400000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH23_Msk 0x00800000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH24_Msk 0x01000000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH25_Msk 0x02000000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH26_Msk 0x04000000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH27_Msk 0x08000000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH28_Msk 0x10000000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH29_Msk 0x20000000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH30_Msk 0x40000000UL /*!< Clear the priority */ #define DMA_PRIORITYCLR_CH31_Msk 0x80000000UL /*!< Clear the priority */ /*-- CIRCULARSET: Channel circular set -----------------------------------------------------------------------*/ typedef struct { uint32_t CH0 :1; /*!< Set the channel circular mode */ uint32_t CH1 :1; /*!< Set the channel circular mode */ uint32_t CH2 :1; /*!< Set the channel circular mode */ uint32_t CH3 :1; /*!< Set the channel circular mode */ uint32_t CH4 :1; /*!< Set the channel circular mode */ uint32_t CH5 :1; /*!< Set the channel circular mode */ uint32_t CH6 :1; /*!< Set the channel circular mode */ uint32_t CH7 :1; /*!< Set the channel circular mode */ uint32_t CH8 :1; /*!< Set the channel circular mode */ uint32_t CH9 :1; /*!< Set the channel circular mode */ uint32_t CH10 :1; /*!< Set the channel circular mode */ uint32_t CH11 :1; /*!< Set the channel circular mode */ uint32_t CH12 :1; /*!< Set the channel circular mode */ uint32_t CH13 :1; /*!< Set the channel circular mode */ uint32_t CH14 :1; /*!< Set the channel circular mode */ uint32_t CH15 :1; /*!< Set the channel circular mode */ uint32_t CH16 :1; /*!< Set the channel circular mode */ uint32_t CH17 :1; /*!< Set the channel circular mode */ uint32_t CH18 :1; /*!< Set the channel circular mode */ uint32_t CH19 :1; /*!< Set the channel circular mode */ uint32_t CH20 :1; /*!< Set the channel circular mode */ uint32_t CH21 :1; /*!< Set the channel circular mode */ uint32_t CH22 :1; /*!< Set the channel circular mode */ uint32_t CH23 :1; /*!< Set the channel circular mode */ uint32_t CH24 :1; /*!< Set the channel circular mode */ uint32_t CH25 :1; /*!< Set the channel circular mode */ uint32_t CH26 :1; /*!< Set the channel circular mode */ uint32_t CH27 :1; /*!< Set the channel circular mode */ uint32_t CH28 :1; /*!< Set the channel circular mode */ uint32_t CH29 :1; /*!< Set the channel circular mode */ uint32_t CH30 :1; /*!< Set the channel circular mode */ uint32_t CH31 :1; /*!< Set the channel circular mode */ } _DMA_CIRCULARSET_bits; /* Bit field positions: */ #define DMA_CIRCULARSET_CH0_Pos 0 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH1_Pos 1 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH2_Pos 2 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH3_Pos 3 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH4_Pos 4 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH5_Pos 5 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH6_Pos 6 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH7_Pos 7 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH8_Pos 8 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH9_Pos 9 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH10_Pos 10 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH11_Pos 11 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH12_Pos 12 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH13_Pos 13 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH14_Pos 14 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH15_Pos 15 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH16_Pos 16 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH17_Pos 17 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH18_Pos 18 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH19_Pos 19 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH20_Pos 20 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH21_Pos 21 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH22_Pos 22 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH23_Pos 23 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH24_Pos 24 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH25_Pos 25 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH26_Pos 26 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH27_Pos 27 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH28_Pos 28 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH29_Pos 29 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH30_Pos 30 /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH31_Pos 31 /*!< Set the channel circular mode */ /* Bit field masks: */ #define DMA_CIRCULARSET_CH0_Msk 0x00000001UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH1_Msk 0x00000002UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH2_Msk 0x00000004UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH3_Msk 0x00000008UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH4_Msk 0x00000010UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH5_Msk 0x00000020UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH6_Msk 0x00000040UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH7_Msk 0x00000080UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH8_Msk 0x00000100UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH9_Msk 0x00000200UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH10_Msk 0x00000400UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH11_Msk 0x00000800UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH12_Msk 0x00001000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH13_Msk 0x00002000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH14_Msk 0x00004000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH15_Msk 0x00008000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH16_Msk 0x00010000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH17_Msk 0x00020000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH18_Msk 0x00040000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH19_Msk 0x00080000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH20_Msk 0x00100000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH21_Msk 0x00200000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH22_Msk 0x00400000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH23_Msk 0x00800000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH24_Msk 0x01000000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH25_Msk 0x02000000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH26_Msk 0x04000000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH27_Msk 0x08000000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH28_Msk 0x10000000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH29_Msk 0x20000000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH30_Msk 0x40000000UL /*!< Set the channel circular mode */ #define DMA_CIRCULARSET_CH31_Msk 0x80000000UL /*!< Set the channel circular mode */ /*-- CIRCULARCLR: Channel circular clear ---------------------------------------------------------------------*/ typedef struct { uint32_t CH0 :1; /*!< Clear the channel circular mode */ uint32_t CH1 :1; /*!< Clear the channel circular mode */ uint32_t CH2 :1; /*!< Clear the channel circular mode */ uint32_t CH3 :1; /*!< Clear the channel circular mode */ uint32_t CH4 :1; /*!< Clear the channel circular mode */ uint32_t CH5 :1; /*!< Clear the channel circular mode */ uint32_t CH6 :1; /*!< Clear the channel circular mode */ uint32_t CH7 :1; /*!< Clear the channel circular mode */ uint32_t CH8 :1; /*!< Clear the channel circular mode */ uint32_t CH9 :1; /*!< Clear the channel circular mode */ uint32_t CH10 :1; /*!< Clear the channel circular mode */ uint32_t CH11 :1; /*!< Clear the channel circular mode */ uint32_t CH12 :1; /*!< Clear the channel circular mode */ uint32_t CH13 :1; /*!< Clear the channel circular mode */ uint32_t CH14 :1; /*!< Clear the channel circular mode */ uint32_t CH15 :1; /*!< Clear the channel circular mode */ uint32_t CH16 :1; /*!< Clear the channel circular mode */ uint32_t CH17 :1; /*!< Clear the channel circular mode */ uint32_t CH18 :1; /*!< Clear the channel circular mode */ uint32_t CH19 :1; /*!< Clear the channel circular mode */ uint32_t CH20 :1; /*!< Clear the channel circular mode */ uint32_t CH21 :1; /*!< Clear the channel circular mode */ uint32_t CH22 :1; /*!< Clear the channel circular mode */ uint32_t CH23 :1; /*!< Clear the channel circular mode */ uint32_t CH24 :1; /*!< Clear the channel circular mode */ uint32_t CH25 :1; /*!< Clear the channel circular mode */ uint32_t CH26 :1; /*!< Clear the channel circular mode */ uint32_t CH27 :1; /*!< Clear the channel circular mode */ uint32_t CH28 :1; /*!< Clear the channel circular mode */ uint32_t CH29 :1; /*!< Clear the channel circular mode */ uint32_t CH30 :1; /*!< Clear the channel circular mode */ uint32_t CH31 :1; /*!< Clear the channel circular mode */ } _DMA_CIRCULARCLR_bits; /* Bit field positions: */ #define DMA_CIRCULARCLR_CH0_Pos 0 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH1_Pos 1 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH2_Pos 2 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH3_Pos 3 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH4_Pos 4 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH5_Pos 5 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH6_Pos 6 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH7_Pos 7 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH8_Pos 8 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH9_Pos 9 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH10_Pos 10 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH11_Pos 11 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH12_Pos 12 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH13_Pos 13 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH14_Pos 14 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH15_Pos 15 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH16_Pos 16 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH17_Pos 17 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH18_Pos 18 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH19_Pos 19 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH20_Pos 20 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH21_Pos 21 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH22_Pos 22 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH23_Pos 23 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH24_Pos 24 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH25_Pos 25 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH26_Pos 26 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH27_Pos 27 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH28_Pos 28 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH29_Pos 29 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH30_Pos 30 /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH31_Pos 31 /*!< Clear the channel circular mode */ /* Bit field masks: */ #define DMA_CIRCULARCLR_CH0_Msk 0x00000001UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH1_Msk 0x00000002UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH2_Msk 0x00000004UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH3_Msk 0x00000008UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH4_Msk 0x00000010UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH5_Msk 0x00000020UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH6_Msk 0x00000040UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH7_Msk 0x00000080UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH8_Msk 0x00000100UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH9_Msk 0x00000200UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH10_Msk 0x00000400UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH11_Msk 0x00000800UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH12_Msk 0x00001000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH13_Msk 0x00002000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH14_Msk 0x00004000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH15_Msk 0x00008000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH16_Msk 0x00010000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH17_Msk 0x00020000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH18_Msk 0x00040000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH19_Msk 0x00080000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH20_Msk 0x00100000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH21_Msk 0x00200000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH22_Msk 0x00400000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH23_Msk 0x00800000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH24_Msk 0x01000000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH25_Msk 0x02000000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH26_Msk 0x04000000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH27_Msk 0x08000000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH28_Msk 0x10000000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH29_Msk 0x20000000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH30_Msk 0x40000000UL /*!< Clear the channel circular mode */ #define DMA_CIRCULARCLR_CH31_Msk 0x80000000UL /*!< Clear the channel circular mode */ /*-- ERRCLR: Bus error register ------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :1; /*!< Indicate Error on bus AHB-Lite */ } _DMA_ERRCLR_bits; /* Bit field positions: */ #define DMA_ERRCLR_VAL_Pos 0 /*!< Indicate Error on bus AHB-Lite */ /* Bit field masks: */ #define DMA_ERRCLR_VAL_Msk 0x00000001UL /*!< Indicate Error on bus AHB-Lite */ typedef struct { union { /*!< Status DMA register */ __I uint32_t STATUS; /*!< STATUS : type used for word access */ __I _DMA_STATUS_bits STATUS_bit; /*!< STATUS_bit: structure used for bit access */ }; union { /*!< DMA configuration register */ __O uint32_t CFG; /*!< CFG : type used for word access */ __O _DMA_CFG_bits CFG_bit; /*!< CFG_bit: structure used for bit access */ }; union { /*!< Channel control data base pointer */ __IO uint32_t BASEPTR; /*!< BASEPTR : type used for word access */ __IO _DMA_BASEPTR_bits BASEPTR_bit; /*!< BASEPTR_bit: structure used for bit access */ }; union { /*!< Channel alternate control data base pointer */ __I uint32_t ALTBASEPTR; /*!< ALTBASEPTR : type used for word access */ __I _DMA_ALTBASEPTR_bits ALTBASEPTR_bit; /*!< ALTBASEPTR_bit: structure used for bit access */ }; union { /*!< Channel wait on request status */ __I uint32_t WAITONREQ; /*!< WAITONREQ : type used for word access */ __I _DMA_WAITONREQ_bits WAITONREQ_bit; /*!< WAITONREQ_bit: structure used for bit access */ }; union { /*!< Channel software request */ __O uint32_t SWREQ; /*!< SWREQ : type used for word access */ __O _DMA_SWREQ_bits SWREQ_bit; /*!< SWREQ_bit: structure used for bit access */ }; union { /*!< Channel useburst set */ __IO uint32_t USEBURSTSET; /*!< USEBURSTSET : type used for word access */ __IO _DMA_USEBURSTSET_bits USEBURSTSET_bit; /*!< USEBURSTSET_bit: structure used for bit access */ }; union { /*!< Channel useburst clear */ __O uint32_t USEBURSTCLR; /*!< USEBURSTCLR : type used for word access */ __O _DMA_USEBURSTCLR_bits USEBURSTCLR_bit; /*!< USEBURSTCLR_bit: structure used for bit access */ }; union { /*!< Channel request mask set */ __IO uint32_t REQMASKSET; /*!< REQMASKSET : type used for word access */ __IO _DMA_REQMASKSET_bits REQMASKSET_bit; /*!< REQMASKSET_bit: structure used for bit access */ }; union { /*!< Channel request mask clear */ __O uint32_t REQMASKCLR; /*!< REQMASKCLR : type used for word access */ __O _DMA_REQMASKCLR_bits REQMASKCLR_bit; /*!< REQMASKCLR_bit: structure used for bit access */ }; union { /*!< Channel enable set */ __IO uint32_t ENSET; /*!< ENSET : type used for word access */ __IO _DMA_ENSET_bits ENSET_bit; /*!< ENSET_bit: structure used for bit access */ }; union { /*!< Channel enable clear */ __O uint32_t ENCLR; /*!< ENCLR : type used for word access */ __O _DMA_ENCLR_bits ENCLR_bit; /*!< ENCLR_bit: structure used for bit access */ }; union { /*!< Channel primary-alternate set */ __IO uint32_t PRIALTSET; /*!< PRIALTSET : type used for word access */ __IO _DMA_PRIALTSET_bits PRIALTSET_bit; /*!< PRIALTSET_bit: structure used for bit access */ }; union { /*!< Channel primary-alternate clear */ __O uint32_t PRIALTCLR; /*!< PRIALTCLR : type used for word access */ __O _DMA_PRIALTCLR_bits PRIALTCLR_bit; /*!< PRIALTCLR_bit: structure used for bit access */ }; union { /*!< Channel priority set */ __IO uint32_t PRIORITYSET; /*!< PRIORITYSET : type used for word access */ __IO _DMA_PRIORITYSET_bits PRIORITYSET_bit; /*!< PRIORITYSET_bit: structure used for bit access */ }; union { /*!< Channel priority clear */ __O uint32_t PRIORITYCLR; /*!< PRIORITYCLR : type used for word access */ __O _DMA_PRIORITYCLR_bits PRIORITYCLR_bit; /*!< PRIORITYCLR_bit: structure used for bit access */ }; union { /*!< Channel circular set */ __IO uint32_t CIRCULARSET; /*!< CIRCULARSET : type used for word access */ __IO _DMA_CIRCULARSET_bits CIRCULARSET_bit; /*!< CIRCULARSET_bit: structure used for bit access */ }; union { /*!< Channel circular clear */ __O uint32_t CIRCULARCLR; /*!< CIRCULARCLR : type used for word access */ __O _DMA_CIRCULARCLR_bits CIRCULARCLR_bit; /*!< CIRCULARCLR_bit: structure used for bit access */ }; __IO uint32_t Reserved0; union { /*!< Bus error register */ __IO uint32_t ERRCLR; /*!< ERRCLR : type used for word access */ __IO _DMA_ERRCLR_bits ERRCLR_bit; /*!< ERRCLR_bit: structure used for bit access */ }; } DMA_TypeDef; /******************************************************************************/ /* MFLASH registers */ /******************************************************************************/ /*-- ADDR: Address Register ----------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :21; /*!< Address value for flash operations */ } _MFLASH_ADDR_bits; /* Bit field positions: */ #define MFLASH_ADDR_VAL_Pos 0 /*!< Address value for flash operations */ /* Bit field masks: */ #define MFLASH_ADDR_VAL_Msk 0x001FFFFFUL /*!< Address value for flash operations */ /*-- DATA: DATA: Data Register --------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Data register value for flash operations */ } _MFLASH_DATA_DATA_bits; /* Bit field positions: */ #define MFLASH_DATA_DATA_VAL_Pos 0 /*!< Data register value for flash operations */ /* Bit field masks: */ #define MFLASH_DATA_DATA_VAL_Msk 0xFFFFFFFFUL /*!< Data register value for flash operations */ /*-- CMD: Command Register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t RD :1; /*!< Read enable command */ uint32_t WR :1; /*!< Write enable command */ uint32_t ERSEC :1; /*!< Erase sector enable command */ uint32_t ALLSEC :1; /*!< Select all sectors for erase */ uint32_t :4; /*!< RESERVED */ uint32_t NVRON :1; /*!< NVR access bit */ uint32_t :7; /*!< RESERVED */ uint32_t KEY :16; /*!< Magic Key for flash access "C0DE" */ } _MFLASH_CMD_bits; /* Bit field positions: */ #define MFLASH_CMD_RD_Pos 0 /*!< Read enable command */ #define MFLASH_CMD_WR_Pos 1 /*!< Write enable command */ #define MFLASH_CMD_ERSEC_Pos 2 /*!< Erase sector enable command */ #define MFLASH_CMD_ALLSEC_Pos 3 /*!< Select all sectors for erase */ #define MFLASH_CMD_NVRON_Pos 8 /*!< NVR access bit */ #define MFLASH_CMD_KEY_Pos 16 /*!< Magic Key for flash access "C0DE" */ /* Bit field masks: */ #define MFLASH_CMD_RD_Msk 0x00000001UL /*!< Read enable command */ #define MFLASH_CMD_WR_Msk 0x00000002UL /*!< Write enable command */ #define MFLASH_CMD_ERSEC_Msk 0x00000004UL /*!< Erase sector enable command */ #define MFLASH_CMD_ALLSEC_Msk 0x00000008UL /*!< Select all sectors for erase */ #define MFLASH_CMD_NVRON_Msk 0x00000100UL /*!< NVR access bit */ #define MFLASH_CMD_KEY_Msk 0xFFFF0000UL /*!< Magic Key for flash access "C0DE" */ /* Bit field enums: */ typedef enum { MFLASH_CMD_KEY_Access = 0xC0DEUL, /*!< magic Key for flash access */ } MFLASH_CMD_KEY_Enum; /*-- STAT: Status Register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t BUSY :1; /*!< Busy status bit when command is processing */ uint32_t IRQF :1; /*!< IRQ Flag set when command done. Set by hardware only if IRQEN bit is set. */ } _MFLASH_STAT_bits; /* Bit field positions: */ #define MFLASH_STAT_BUSY_Pos 0 /*!< Busy status bit when command is processing */ #define MFLASH_STAT_IRQF_Pos 1 /*!< IRQ Flag set when command done. Set by hardware only if IRQEN bit is set. */ /* Bit field masks: */ #define MFLASH_STAT_BUSY_Msk 0x00000001UL /*!< Busy status bit when command is processing */ #define MFLASH_STAT_IRQF_Msk 0x00000002UL /*!< IRQ Flag set when command done. Set by hardware only if IRQEN bit is set. */ /*-- CTRL: Control Register ----------------------------------------------------------------------------------*/ typedef struct { uint32_t :1; /*!< RESERVED */ uint32_t ICEN :1; /*!< I-Cache enable bit */ uint32_t DCEN :1; /*!< D-Cache enable bit */ uint32_t :1; /*!< RESERVED */ uint32_t IRQEN :1; /*!< Interrupt enable bit */ uint32_t :3; /*!< RESERVED */ uint32_t IFLUSH :1; /*!< Flush I-Cache request bit */ uint32_t DFLUSH :1; /*!< Flush D-Cache request bit */ uint32_t :6; /*!< RESERVED */ uint32_t LAT :4; /*!< */ } _MFLASH_CTRL_bits; /* Bit field positions: */ #define MFLASH_CTRL_ICEN_Pos 1 /*!< I-Cache enable bit */ #define MFLASH_CTRL_DCEN_Pos 2 /*!< D-Cache enable bit */ #define MFLASH_CTRL_IRQEN_Pos 4 /*!< Interrupt enable bit */ #define MFLASH_CTRL_IFLUSH_Pos 8 /*!< Flush I-Cache request bit */ #define MFLASH_CTRL_DFLUSH_Pos 9 /*!< Flush D-Cache request bit */ #define MFLASH_CTRL_LAT_Pos 16 /*!< */ /* Bit field masks: */ #define MFLASH_CTRL_ICEN_Msk 0x00000002UL /*!< I-Cache enable bit */ #define MFLASH_CTRL_DCEN_Msk 0x00000004UL /*!< D-Cache enable bit */ #define MFLASH_CTRL_IRQEN_Msk 0x00000010UL /*!< Interrupt enable bit */ #define MFLASH_CTRL_IFLUSH_Msk 0x00000100UL /*!< Flush I-Cache request bit */ #define MFLASH_CTRL_DFLUSH_Msk 0x00000200UL /*!< Flush D-Cache request bit */ #define MFLASH_CTRL_LAT_Msk 0x000F0000UL /*!< */ /*-- ICSTAT: I-CACHE Status Register -------------------------------------------------------------------------*/ typedef struct { uint32_t BUSY :1; /*!< I-Cache busy */ } _MFLASH_ICSTAT_bits; /* Bit field positions: */ #define MFLASH_ICSTAT_BUSY_Pos 0 /*!< I-Cache busy */ /* Bit field masks: */ #define MFLASH_ICSTAT_BUSY_Msk 0x00000001UL /*!< I-Cache busy */ /*-- DCSTAT: D-CACHE Status Register -------------------------------------------------------------------------*/ typedef struct { uint32_t BUSY :1; /*!< D-Cache busy */ } _MFLASH_DCSTAT_bits; /* Bit field positions: */ #define MFLASH_DCSTAT_BUSY_Pos 0 /*!< D-Cache busy */ /* Bit field masks: */ #define MFLASH_DCSTAT_BUSY_Msk 0x00000001UL /*!< D-Cache busy */ //Cluster DATA: typedef struct { union { /*!< Data Register */ __IO uint32_t DATA; /*!< DATA : type used for word access */ __IO _MFLASH_DATA_DATA_bits DATA_bit; /*!< DATA_bit: structure used for bit access */ }; } _MFLASH_DATA_TypeDef; typedef struct { union { /*!< Address Register */ __IO uint32_t ADDR; /*!< ADDR : type used for word access */ __IO _MFLASH_ADDR_bits ADDR_bit; /*!< ADDR_bit: structure used for bit access */ }; _MFLASH_DATA_TypeDef DATA[16]; union { /*!< Command Register */ __IO uint32_t CMD; /*!< CMD : type used for word access */ __IO _MFLASH_CMD_bits CMD_bit; /*!< CMD_bit: structure used for bit access */ }; union { /*!< Status Register */ __IO uint32_t STAT; /*!< STAT : type used for word access */ __IO _MFLASH_STAT_bits STAT_bit; /*!< STAT_bit: structure used for bit access */ }; union { /*!< Control Register */ __IO uint32_t CTRL; /*!< CTRL : type used for word access */ __IO _MFLASH_CTRL_bits CTRL_bit; /*!< CTRL_bit: structure used for bit access */ }; union { /*!< I-CACHE Status Register */ __I uint32_t ICSTAT; /*!< ICSTAT : type used for word access */ __I _MFLASH_ICSTAT_bits ICSTAT_bit; /*!< ICSTAT_bit: structure used for bit access */ }; union { /*!< D-CACHE Status Register */ __I uint32_t DCSTAT; /*!< DCSTAT : type used for word access */ __I _MFLASH_DCSTAT_bits DCSTAT_bit; /*!< DCSTAT_bit: structure used for bit access */ }; } MFLASH_TypeDef; /******************************************************************************/ /* BFLASH registers */ /******************************************************************************/ /*-- ADDR: Address Register ----------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :19; /*!< Address value for flash operations */ } _BFLASH_ADDR_bits; /* Bit field positions: */ #define BFLASH_ADDR_VAL_Pos 0 /*!< Address value for flash operations */ /* Bit field masks: */ #define BFLASH_ADDR_VAL_Msk 0x0007FFFFUL /*!< Address value for flash operations */ /*-- DATA: DATA: Data Register --------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Data register value for flash operations */ } _BFLASH_DATA_DATA_bits; /* Bit field positions: */ #define BFLASH_DATA_DATA_VAL_Pos 0 /*!< Data register value for flash operations */ /* Bit field masks: */ #define BFLASH_DATA_DATA_VAL_Msk 0xFFFFFFFFUL /*!< Data register value for flash operations */ /*-- CMD: Command Register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t RD :1; /*!< Read enable command */ uint32_t WR :1; /*!< Write enable command */ uint32_t ERSEC :1; /*!< Erase sector enable command */ uint32_t ALLSEC :1; /*!< Enable Erase all flash memory */ uint32_t :4; /*!< RESERVED */ uint32_t NVRON :1; /*!< INFO access bit */ uint32_t :7; /*!< RESERVED */ uint32_t KEY :16; /*!< Magic Key for flash access "C0DE" */ } _BFLASH_CMD_bits; /* Bit field positions: */ #define BFLASH_CMD_RD_Pos 0 /*!< Read enable command */ #define BFLASH_CMD_WR_Pos 1 /*!< Write enable command */ #define BFLASH_CMD_ERSEC_Pos 2 /*!< Erase sector enable command */ #define BFLASH_CMD_ALLSEC_Pos 3 /*!< Enable Erase all flash memory */ #define BFLASH_CMD_NVRON_Pos 8 /*!< INFO access bit */ #define BFLASH_CMD_KEY_Pos 16 /*!< Magic Key for flash access "C0DE" */ /* Bit field masks: */ #define BFLASH_CMD_RD_Msk 0x00000001UL /*!< Read enable command */ #define BFLASH_CMD_WR_Msk 0x00000002UL /*!< Write enable command */ #define BFLASH_CMD_ERSEC_Msk 0x00000004UL /*!< Erase sector enable command */ #define BFLASH_CMD_ALLSEC_Msk 0x00000008UL /*!< Enable Erase all flash memory */ #define BFLASH_CMD_NVRON_Msk 0x00000100UL /*!< INFO access bit */ #define BFLASH_CMD_KEY_Msk 0xFFFF0000UL /*!< Magic Key for flash access "C0DE" */ /* Bit field enums: */ typedef enum { BFLASH_CMD_KEY_Access = 0xC0DEUL, /*!< magic Key for flash access */ } BFLASH_CMD_KEY_Enum; /*-- STAT: Status Register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t BUSY :1; /*!< Busy status bit when command is processing */ uint32_t IRQF :1; /*!< IRQ Flag set when command done. Set by hardware only if IRQEN bit is set. */ } _BFLASH_STAT_bits; /* Bit field positions: */ #define BFLASH_STAT_BUSY_Pos 0 /*!< Busy status bit when command is processing */ #define BFLASH_STAT_IRQF_Pos 1 /*!< IRQ Flag set when command done. Set by hardware only if IRQEN bit is set. */ /* Bit field masks: */ #define BFLASH_STAT_BUSY_Msk 0x00000001UL /*!< Busy status bit when command is processing */ #define BFLASH_STAT_IRQF_Msk 0x00000002UL /*!< IRQ Flag set when command done. Set by hardware only if IRQEN bit is set. */ /*-- CTRL: Control Register ----------------------------------------------------------------------------------*/ typedef struct { uint32_t :4; /*!< RESERVED */ uint32_t IRQEN :1; /*!< Interrupt enable bit */ uint32_t :11; /*!< RESERVED */ uint32_t LAT :4; /*!< Flash latency */ } _BFLASH_CTRL_bits; /* Bit field positions: */ #define BFLASH_CTRL_IRQEN_Pos 4 /*!< Interrupt enable bit */ #define BFLASH_CTRL_LAT_Pos 16 /*!< Flash latency */ /* Bit field masks: */ #define BFLASH_CTRL_IRQEN_Msk 0x00000010UL /*!< Interrupt enable bit */ #define BFLASH_CTRL_LAT_Msk 0x000F0000UL /*!< Flash latency */ //Cluster DATA: typedef struct { union { /*!< Data Register */ __IO uint32_t DATA; /*!< DATA : type used for word access */ __IO _BFLASH_DATA_DATA_bits DATA_bit; /*!< DATA_bit: structure used for bit access */ }; } _BFLASH_DATA_TypeDef; typedef struct { union { /*!< Address Register */ __IO uint32_t ADDR; /*!< ADDR : type used for word access */ __IO _BFLASH_ADDR_bits ADDR_bit; /*!< ADDR_bit: structure used for bit access */ }; _BFLASH_DATA_TypeDef DATA[4]; __IO uint32_t Reserved0[12]; union { /*!< Command Register */ __IO uint32_t CMD; /*!< CMD : type used for word access */ __IO _BFLASH_CMD_bits CMD_bit; /*!< CMD_bit: structure used for bit access */ }; union { /*!< Status Register */ __IO uint32_t STAT; /*!< STAT : type used for word access */ __IO _BFLASH_STAT_bits STAT_bit; /*!< STAT_bit: structure used for bit access */ }; union { /*!< Control Register */ __IO uint32_t CTRL; /*!< CTRL : type used for word access */ __IO _BFLASH_CTRL_bits CTRL_bit; /*!< CTRL_bit: structure used for bit access */ }; } BFLASH_TypeDef; /******************************************************************************/ /* EXTMEM registers */ /******************************************************************************/ /*-- WINCFG: WINCFG: Window Configuration ---------------------------------------------------------------------*/ typedef struct { uint32_t MODE :1; /*!< 8/16 bit mode. When 1 - 16 bit mode enabled */ uint32_t :7; /*!< RESERVED */ uint32_t RDCYC :4; /*!< Additional Read cycles */ uint32_t :4; /*!< RESERVED */ uint32_t WRCYC :4; /*!< Additional Write cycles */ uint32_t :4; /*!< RESERVED */ uint32_t TACYC :4; /*!< Turnaround cycles */ } _EXTMEM_WINCFG_WINCFG_bits; /* Bit field positions: */ #define EXTMEM_WINCFG_WINCFG_MODE_Pos 0 /*!< 8/16 bit mode. When 1 - 16 bit mode enabled */ #define EXTMEM_WINCFG_WINCFG_RDCYC_Pos 8 /*!< Additional Read cycles */ #define EXTMEM_WINCFG_WINCFG_WRCYC_Pos 16 /*!< Additional Write cycles */ #define EXTMEM_WINCFG_WINCFG_TACYC_Pos 24 /*!< Turnaround cycles */ /* Bit field masks: */ #define EXTMEM_WINCFG_WINCFG_MODE_Msk 0x00000001UL /*!< 8/16 bit mode. When 1 - 16 bit mode enabled */ #define EXTMEM_WINCFG_WINCFG_RDCYC_Msk 0x00000F00UL /*!< Additional Read cycles */ #define EXTMEM_WINCFG_WINCFG_WRCYC_Msk 0x000F0000UL /*!< Additional Write cycles */ #define EXTMEM_WINCFG_WINCFG_TACYC_Msk 0x0F000000UL /*!< Turnaround cycles */ //Cluster WINCFG: typedef struct { union { /*!< Window Configuration */ __IO uint32_t WINCFG; /*!< WINCFG : type used for word access */ __IO _EXTMEM_WINCFG_WINCFG_bits WINCFG_bit; /*!< WINCFG_bit: structure used for bit access */ }; } _EXTMEM_WINCFG_TypeDef; typedef struct { _EXTMEM_WINCFG_TypeDef WINCFG[8]; } EXTMEM_TypeDef; /******************************************************************************/ /* PWM registers */ /******************************************************************************/ /*-- TBCTL: Time-Base Control Register -----------------------------------------------------------------------*/ typedef struct { uint32_t CTRMODE :2; /*!< Counter mode */ uint32_t PHSEN :1; /*!< Counter register load from phase register enable */ uint32_t PRDLD :1; /*!< Active period register load from shadow register select */ uint32_t SYNCOSEL :2; /*!< Synchronization Output Select. These bits select the source of the PWM_SYNCO signal. */ uint32_t SWFSYNC :1; /*!< Software forced synchronization pulse */ uint32_t HSPCLKDIV :3; /*!< High speed time-base clock prescale bits */ uint32_t CLKDIV :3; /*!< Time-base clock prescale bits */ uint32_t PHSDIR :1; /*!< Phase direction bit */ uint32_t FREESOFT :2; /*!< Emulation mode bits - select the behavior of the time-base counter during emulation events */ uint32_t SHDWGLOB :1; /*!< Global enabe for all shadow loads */ } _PWM_TBCTL_bits; /* Bit field positions: */ #define PWM_TBCTL_CTRMODE_Pos 0 /*!< Counter mode */ #define PWM_TBCTL_PHSEN_Pos 2 /*!< Counter register load from phase register enable */ #define PWM_TBCTL_PRDLD_Pos 3 /*!< Active period register load from shadow register select */ #define PWM_TBCTL_SYNCOSEL_Pos 4 /*!< Synchronization Output Select. These bits select the source of the PWM_SYNCO signal. */ #define PWM_TBCTL_SWFSYNC_Pos 6 /*!< Software forced synchronization pulse */ #define PWM_TBCTL_HSPCLKDIV_Pos 7 /*!< High speed time-base clock prescale bits */ #define PWM_TBCTL_CLKDIV_Pos 10 /*!< Time-base clock prescale bits */ #define PWM_TBCTL_PHSDIR_Pos 13 /*!< Phase direction bit */ #define PWM_TBCTL_FREESOFT_Pos 14 /*!< Emulation mode bits - select the behavior of the time-base counter during emulation events */ #define PWM_TBCTL_SHDWGLOB_Pos 16 /*!< Global enabe for all shadow loads */ /* Bit field masks: */ #define PWM_TBCTL_CTRMODE_Msk 0x00000003UL /*!< Counter mode */ #define PWM_TBCTL_PHSEN_Msk 0x00000004UL /*!< Counter register load from phase register enable */ #define PWM_TBCTL_PRDLD_Msk 0x00000008UL /*!< Active period register load from shadow register select */ #define PWM_TBCTL_SYNCOSEL_Msk 0x00000030UL /*!< Synchronization Output Select. These bits select the source of the PWM_SYNCO signal. */ #define PWM_TBCTL_SWFSYNC_Msk 0x00000040UL /*!< Software forced synchronization pulse */ #define PWM_TBCTL_HSPCLKDIV_Msk 0x00000380UL /*!< High speed time-base clock prescale bits */ #define PWM_TBCTL_CLKDIV_Msk 0x00001C00UL /*!< Time-base clock prescale bits */ #define PWM_TBCTL_PHSDIR_Msk 0x00002000UL /*!< Phase direction bit */ #define PWM_TBCTL_FREESOFT_Msk 0x0000C000UL /*!< Emulation mode bits - select the behavior of the time-base counter during emulation events */ #define PWM_TBCTL_SHDWGLOB_Msk 0x00010000UL /*!< Global enabe for all shadow loads */ /* Bit field enums: */ typedef enum { PWM_TBCTL_CTRMODE_Up = 0x0UL, /*!< count direction up */ PWM_TBCTL_CTRMODE_Down = 0x1UL, /*!< count direction down */ PWM_TBCTL_CTRMODE_UpDown = 0x2UL, /*!< count direction up-down */ PWM_TBCTL_CTRMODE_Stop = 0x3UL, /*!< counter stopped */ } PWM_TBCTL_CTRMODE_Enum; typedef enum { PWM_TBCTL_SYNCOSEL_SYNCI = 0x0UL, /*!< PWM_SYNCI is source for PWM_SYNCO */ PWM_TBCTL_SYNCOSEL_CTREqZero = 0x1UL, /*!< CTR = 0000h is source for PWM_SYNCO */ PWM_TBCTL_SYNCOSEL_CTREqCMPB = 0x2UL, /*!< CTR = CMPB is source for PWM_SYNCO */ PWM_TBCTL_SYNCOSEL_Disable = 0x3UL, /*!< PWM_SYNCO generation disabled */ } PWM_TBCTL_SYNCOSEL_Enum; typedef enum { PWM_TBCTL_HSPCLKDIV_Div1 = 0x0UL, /*!< clock not divided */ PWM_TBCTL_HSPCLKDIV_Div2 = 0x1UL, /*!< clock divided by 2 */ PWM_TBCTL_HSPCLKDIV_Div4 = 0x2UL, /*!< clock divided by 4 */ PWM_TBCTL_HSPCLKDIV_Div6 = 0x3UL, /*!< clock divided by 6 */ PWM_TBCTL_HSPCLKDIV_Div8 = 0x4UL, /*!< clock divided by 8 */ PWM_TBCTL_HSPCLKDIV_Div10 = 0x5UL, /*!< clock divided by 10 */ PWM_TBCTL_HSPCLKDIV_Div12 = 0x6UL, /*!< clock divided by 12 */ PWM_TBCTL_HSPCLKDIV_Div14 = 0x7UL, /*!< clock divided by 14 */ } PWM_TBCTL_HSPCLKDIV_Enum; typedef enum { PWM_TBCTL_CLKDIV_Div1 = 0x0UL, /*!< clock not divided */ PWM_TBCTL_CLKDIV_Div2 = 0x1UL, /*!< clock divided by 2 */ PWM_TBCTL_CLKDIV_Div4 = 0x2UL, /*!< clock divided by 4 */ PWM_TBCTL_CLKDIV_Div8 = 0x3UL, /*!< clock divided by 8 */ PWM_TBCTL_CLKDIV_Div16 = 0x4UL, /*!< clock divided by 16 */ PWM_TBCTL_CLKDIV_Div32 = 0x5UL, /*!< clock divided by 32 */ PWM_TBCTL_CLKDIV_Div64 = 0x6UL, /*!< clock divided by 64 */ PWM_TBCTL_CLKDIV_Div128 = 0x7UL, /*!< clock divided by 128 */ } PWM_TBCTL_CLKDIV_Enum; typedef enum { PWM_TBCTL_FREESOFT_StopAtTBCLK = 0x0UL, /*!< stop timer at next TBCLK tact */ PWM_TBCTL_FREESOFT_StopAtPeriod = 0x1UL, /*!< stop timer when period ends */ PWM_TBCTL_FREESOFT_FreeRun = 0x2UL, /*!< free run mode */ } PWM_TBCTL_FREESOFT_Enum; /*-- TBSTS: Time-Base Status Register ------------------------------------------------------------------------*/ typedef struct { uint32_t CTRDIR :1; /*!< Time-Base counter direction status bit */ uint32_t SYNCI :1; /*!< Input synchronization latched status bit */ uint32_t CTRMAX :1; /*!< Time-Base counter max latched status bit */ } _PWM_TBSTS_bits; /* Bit field positions: */ #define PWM_TBSTS_CTRDIR_Pos 0 /*!< Time-Base counter direction status bit */ #define PWM_TBSTS_SYNCI_Pos 1 /*!< Input synchronization latched status bit */ #define PWM_TBSTS_CTRMAX_Pos 2 /*!< Time-Base counter max latched status bit */ /* Bit field masks: */ #define PWM_TBSTS_CTRDIR_Msk 0x00000001UL /*!< Time-Base counter direction status bit */ #define PWM_TBSTS_SYNCI_Msk 0x00000002UL /*!< Input synchronization latched status bit */ #define PWM_TBSTS_CTRMAX_Msk 0x00000004UL /*!< Time-Base counter max latched status bit */ /*-- TBPHS: Time-Base Phase Register -------------------------------------------------------------------------*/ typedef struct { uint32_t :8; /*!< RESERVED */ uint32_t TBPHSHR :8; /*!< Time-base counter phase in High-Resolution mode */ uint32_t TBPHS :16; /*!< Time-base counter phase */ } _PWM_TBPHS_bits; /* Bit field positions: */ #define PWM_TBPHS_TBPHSHR_Pos 8 /*!< Time-base counter phase in High-Resolution mode */ #define PWM_TBPHS_TBPHS_Pos 16 /*!< Time-base counter phase */ /* Bit field masks: */ #define PWM_TBPHS_TBPHSHR_Msk 0x0000FF00UL /*!< Time-base counter phase in High-Resolution mode */ #define PWM_TBPHS_TBPHS_Msk 0xFFFF0000UL /*!< Time-base counter phase */ /*-- TBCTR: Time-Base Counter Register -----------------------------------------------------------------------*/ typedef struct { uint32_t VAL :16; /*!< Current time-base counter value */ } _PWM_TBCTR_bits; /* Bit field positions: */ #define PWM_TBCTR_VAL_Pos 0 /*!< Current time-base counter value */ /* Bit field masks: */ #define PWM_TBCTR_VAL_Msk 0x0000FFFFUL /*!< Current time-base counter value */ /*-- TBPRD: Time-Base Period Register ------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :16; /*!< Period of the time-base counter */ } _PWM_TBPRD_bits; /* Bit field positions: */ #define PWM_TBPRD_VAL_Pos 0 /*!< Period of the time-base counter */ /* Bit field masks: */ #define PWM_TBPRD_VAL_Msk 0x0000FFFFUL /*!< Period of the time-base counter */ /*-- CMPCTL: Counter-Compare Control Register ----------------------------------------------------------------*/ typedef struct { uint32_t LOADAMODE :2; /*!< Active CMPA load from shadow select mode */ uint32_t LOADBMODE :2; /*!< Active CMPB load from shadow select mode */ uint32_t SHDWAMODE :1; /*!< CMPA register operating mode */ uint32_t :1; /*!< RESERVED */ uint32_t SHDWBMODE :1; /*!< CMPB register operating mode */ uint32_t :1; /*!< RESERVED */ uint32_t SHDWAFULL :1; /*!< CMPA shadow register full status flag */ uint32_t SHDWBFULL :1; /*!< CMPB shadow register full status flag */ } _PWM_CMPCTL_bits; /* Bit field positions: */ #define PWM_CMPCTL_LOADAMODE_Pos 0 /*!< Active CMPA load from shadow select mode */ #define PWM_CMPCTL_LOADBMODE_Pos 2 /*!< Active CMPB load from shadow select mode */ #define PWM_CMPCTL_SHDWAMODE_Pos 4 /*!< CMPA register operating mode */ #define PWM_CMPCTL_SHDWBMODE_Pos 6 /*!< CMPB register operating mode */ #define PWM_CMPCTL_SHDWAFULL_Pos 8 /*!< CMPA shadow register full status flag */ #define PWM_CMPCTL_SHDWBFULL_Pos 9 /*!< CMPB shadow register full status flag */ /* Bit field masks: */ #define PWM_CMPCTL_LOADAMODE_Msk 0x00000003UL /*!< Active CMPA load from shadow select mode */ #define PWM_CMPCTL_LOADBMODE_Msk 0x0000000CUL /*!< Active CMPB load from shadow select mode */ #define PWM_CMPCTL_SHDWAMODE_Msk 0x00000010UL /*!< CMPA register operating mode */ #define PWM_CMPCTL_SHDWBMODE_Msk 0x00000040UL /*!< CMPB register operating mode */ #define PWM_CMPCTL_SHDWAFULL_Msk 0x00000100UL /*!< CMPA shadow register full status flag */ #define PWM_CMPCTL_SHDWBFULL_Msk 0x00000200UL /*!< CMPB shadow register full status flag */ /* Bit field enums: */ typedef enum { PWM_CMPCTL_LOADAMODE_CTREqZero = 0x0UL, /*!< shadow load for CMPx (x=A,B) when CTR = 0 */ PWM_CMPCTL_LOADAMODE_CTREqPRD = 0x1UL, /*!< shadow load for CMPx (x=A,B) when CTR = PRD */ PWM_CMPCTL_LOADAMODE_CTREqZeroPRD = 0x2UL, /*!< shadow load for CMPx (x=A,B) when CTR = 0 or CTR = PRD */ PWM_CMPCTL_LOADAMODE_Disable = 0x3UL, /*!< shadow load for CMPx (x=A,B) disabled */ } PWM_CMPCTL_LOADAMODE_Enum; typedef enum { PWM_CMPCTL_LOADBMODE_CTREqZero = 0x0UL, /*!< shadow load for CMPx (x=A,B) when CTR = 0 */ PWM_CMPCTL_LOADBMODE_CTREqPRD = 0x1UL, /*!< shadow load for CMPx (x=A,B) when CTR = PRD */ PWM_CMPCTL_LOADBMODE_CTREqZeroPRD = 0x2UL, /*!< shadow load for CMPx (x=A,B) when CTR = 0 or CTR = PRD */ PWM_CMPCTL_LOADBMODE_Disable = 0x3UL, /*!< shadow load for CMPx (x=A,B) disabled */ } PWM_CMPCTL_LOADBMODE_Enum; /*-- CMPA: Counter-Compare A Register ------------------------------------------------------------------------*/ typedef struct { uint32_t :8; /*!< RESERVED */ uint32_t CMPAHR :8; /*!< The value compared to the time-base counter (TBCTR) in High-Resolution mode */ uint32_t CMPA :16; /*!< The value compared to the time-base counter (TBCTR) */ } _PWM_CMPA_bits; /* Bit field positions: */ #define PWM_CMPA_CMPAHR_Pos 8 /*!< The value compared to the time-base counter (TBCTR) in High-Resolution mode */ #define PWM_CMPA_CMPA_Pos 16 /*!< The value compared to the time-base counter (TBCTR) */ /* Bit field masks: */ #define PWM_CMPA_CMPAHR_Msk 0x0000FF00UL /*!< The value compared to the time-base counter (TBCTR) in High-Resolution mode */ #define PWM_CMPA_CMPA_Msk 0xFFFF0000UL /*!< The value compared to the time-base counter (TBCTR) */ /*-- CMPB: Counter-Compare B Register ------------------------------------------------------------------------*/ typedef struct { uint32_t :16; /*!< RESERVED */ uint32_t CMPB :16; /*!< The value compared to the time-base counter (TBCTR) */ } _PWM_CMPB_bits; /* Bit field positions: */ #define PWM_CMPB_CMPB_Pos 16 /*!< The value compared to the time-base counter (TBCTR) */ /* Bit field masks: */ #define PWM_CMPB_CMPB_Msk 0xFFFF0000UL /*!< The value compared to the time-base counter (TBCTR) */ /*-- AQCTLA: Action-Qualifier Output A Control Register ------------------------------------------------------*/ typedef struct { uint32_t ZRO :2; /*!< Action when counter equals zero */ uint32_t PRD :2; /*!< Action when the counter equals the period */ uint32_t CAU :2; /*!< Action when the counter equals the active CMPA register and the counter is incrementing */ uint32_t CAD :2; /*!< Action when the counter equals the active CMPA register and the counter is decrementing */ uint32_t CBU :2; /*!< Action when the counter equals the active CMPB register and the counter is incrementing */ uint32_t CBD :2; /*!< Action when the time-base counter equals the active CMPB register and the counter is decrementing */ } _PWM_AQCTLA_bits; /* Bit field positions: */ #define PWM_AQCTLA_ZRO_Pos 0 /*!< Action when counter equals zero */ #define PWM_AQCTLA_PRD_Pos 2 /*!< Action when the counter equals the period */ #define PWM_AQCTLA_CAU_Pos 4 /*!< Action when the counter equals the active CMPA register and the counter is incrementing */ #define PWM_AQCTLA_CAD_Pos 6 /*!< Action when the counter equals the active CMPA register and the counter is decrementing */ #define PWM_AQCTLA_CBU_Pos 8 /*!< Action when the counter equals the active CMPB register and the counter is incrementing */ #define PWM_AQCTLA_CBD_Pos 10 /*!< Action when the time-base counter equals the active CMPB register and the counter is decrementing */ /* Bit field masks: */ #define PWM_AQCTLA_ZRO_Msk 0x00000003UL /*!< Action when counter equals zero */ #define PWM_AQCTLA_PRD_Msk 0x0000000CUL /*!< Action when the counter equals the period */ #define PWM_AQCTLA_CAU_Msk 0x00000030UL /*!< Action when the counter equals the active CMPA register and the counter is incrementing */ #define PWM_AQCTLA_CAD_Msk 0x000000C0UL /*!< Action when the counter equals the active CMPA register and the counter is decrementing */ #define PWM_AQCTLA_CBU_Msk 0x00000300UL /*!< Action when the counter equals the active CMPB register and the counter is incrementing */ #define PWM_AQCTLA_CBD_Msk 0x00000C00UL /*!< Action when the time-base counter equals the active CMPB register and the counter is decrementing */ /* Bit field enums: */ typedef enum { PWM_AQCTLA_ZRO_NoAction = 0x0UL, /*!< no action */ PWM_AQCTLA_ZRO_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQCTLA_ZRO_Set = 0x2UL, /*!< set PWMA/PWMB */ PWM_AQCTLA_ZRO_Toogle = 0x3UL, /*!< inverse PWMA/PWMB */ } PWM_AQCTLA_ZRO_Enum; typedef enum { PWM_AQCTLA_PRD_NoAction = 0x0UL, /*!< no action */ PWM_AQCTLA_PRD_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQCTLA_PRD_Set = 0x2UL, /*!< set PWMA/PWMB */ PWM_AQCTLA_PRD_Toogle = 0x3UL, /*!< inverse PWMA/PWMB */ } PWM_AQCTLA_PRD_Enum; typedef enum { PWM_AQCTLA_CAU_NoAction = 0x0UL, /*!< no action */ PWM_AQCTLA_CAU_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQCTLA_CAU_Set = 0x2UL, /*!< set PWMA/PWMB */ PWM_AQCTLA_CAU_Toogle = 0x3UL, /*!< inverse PWMA/PWMB */ } PWM_AQCTLA_CAU_Enum; typedef enum { PWM_AQCTLA_CAD_NoAction = 0x0UL, /*!< no action */ PWM_AQCTLA_CAD_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQCTLA_CAD_Set = 0x2UL, /*!< set PWMA/PWMB */ PWM_AQCTLA_CAD_Toogle = 0x3UL, /*!< inverse PWMA/PWMB */ } PWM_AQCTLA_CAD_Enum; typedef enum { PWM_AQCTLA_CBU_NoAction = 0x0UL, /*!< no action */ PWM_AQCTLA_CBU_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQCTLA_CBU_Set = 0x2UL, /*!< set PWMA/PWMB */ PWM_AQCTLA_CBU_Toogle = 0x3UL, /*!< inverse PWMA/PWMB */ } PWM_AQCTLA_CBU_Enum; typedef enum { PWM_AQCTLA_CBD_NoAction = 0x0UL, /*!< no action */ PWM_AQCTLA_CBD_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQCTLA_CBD_Set = 0x2UL, /*!< set PWMA/PWMB */ PWM_AQCTLA_CBD_Toogle = 0x3UL, /*!< inverse PWMA/PWMB */ } PWM_AQCTLA_CBD_Enum; /*-- AQCTLB: Action-Qualifier Output B Control Register ------------------------------------------------------*/ typedef struct { uint32_t ZRO :2; /*!< Action when counter equals zero */ uint32_t PRD :2; /*!< Action when the counter equals the period */ uint32_t CAU :2; /*!< Action when the counter equals the active CMPA register and the counter is incrementing */ uint32_t CAD :2; /*!< Action when the counter equals the active CMPA register and the counter is decrementing */ uint32_t CBU :2; /*!< Action when the counter equals the active CMPB register and the counter is incrementing */ uint32_t CBD :2; /*!< Action when the time-base counter equals the active CMPB register and the counter is decrementing */ } _PWM_AQCTLB_bits; /* Bit field positions: */ #define PWM_AQCTLB_ZRO_Pos 0 /*!< Action when counter equals zero */ #define PWM_AQCTLB_PRD_Pos 2 /*!< Action when the counter equals the period */ #define PWM_AQCTLB_CAU_Pos 4 /*!< Action when the counter equals the active CMPA register and the counter is incrementing */ #define PWM_AQCTLB_CAD_Pos 6 /*!< Action when the counter equals the active CMPA register and the counter is decrementing */ #define PWM_AQCTLB_CBU_Pos 8 /*!< Action when the counter equals the active CMPB register and the counter is incrementing */ #define PWM_AQCTLB_CBD_Pos 10 /*!< Action when the time-base counter equals the active CMPB register and the counter is decrementing */ /* Bit field masks: */ #define PWM_AQCTLB_ZRO_Msk 0x00000003UL /*!< Action when counter equals zero */ #define PWM_AQCTLB_PRD_Msk 0x0000000CUL /*!< Action when the counter equals the period */ #define PWM_AQCTLB_CAU_Msk 0x00000030UL /*!< Action when the counter equals the active CMPA register and the counter is incrementing */ #define PWM_AQCTLB_CAD_Msk 0x000000C0UL /*!< Action when the counter equals the active CMPA register and the counter is decrementing */ #define PWM_AQCTLB_CBU_Msk 0x00000300UL /*!< Action when the counter equals the active CMPB register and the counter is incrementing */ #define PWM_AQCTLB_CBD_Msk 0x00000C00UL /*!< Action when the time-base counter equals the active CMPB register and the counter is decrementing */ /* Bit field enums: */ typedef enum { PWM_AQCTLB_ZRO_NoAction = 0x0UL, /*!< no action */ PWM_AQCTLB_ZRO_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQCTLB_ZRO_Set = 0x2UL, /*!< set PWMA/PWMB */ PWM_AQCTLB_ZRO_Toogle = 0x3UL, /*!< inverse PWMA/PWMB */ } PWM_AQCTLB_ZRO_Enum; typedef enum { PWM_AQCTLB_PRD_NoAction = 0x0UL, /*!< no action */ PWM_AQCTLB_PRD_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQCTLB_PRD_Set = 0x2UL, /*!< set PWMA/PWMB */ PWM_AQCTLB_PRD_Toogle = 0x3UL, /*!< inverse PWMA/PWMB */ } PWM_AQCTLB_PRD_Enum; typedef enum { PWM_AQCTLB_CAU_NoAction = 0x0UL, /*!< no action */ PWM_AQCTLB_CAU_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQCTLB_CAU_Set = 0x2UL, /*!< set PWMA/PWMB */ PWM_AQCTLB_CAU_Toogle = 0x3UL, /*!< inverse PWMA/PWMB */ } PWM_AQCTLB_CAU_Enum; typedef enum { PWM_AQCTLB_CAD_NoAction = 0x0UL, /*!< no action */ PWM_AQCTLB_CAD_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQCTLB_CAD_Set = 0x2UL, /*!< set PWMA/PWMB */ PWM_AQCTLB_CAD_Toogle = 0x3UL, /*!< inverse PWMA/PWMB */ } PWM_AQCTLB_CAD_Enum; typedef enum { PWM_AQCTLB_CBU_NoAction = 0x0UL, /*!< no action */ PWM_AQCTLB_CBU_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQCTLB_CBU_Set = 0x2UL, /*!< set PWMA/PWMB */ PWM_AQCTLB_CBU_Toogle = 0x3UL, /*!< inverse PWMA/PWMB */ } PWM_AQCTLB_CBU_Enum; typedef enum { PWM_AQCTLB_CBD_NoAction = 0x0UL, /*!< no action */ PWM_AQCTLB_CBD_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQCTLB_CBD_Set = 0x2UL, /*!< set PWMA/PWMB */ PWM_AQCTLB_CBD_Toogle = 0x3UL, /*!< inverse PWMA/PWMB */ } PWM_AQCTLB_CBD_Enum; /*-- AQSFRC: Action-Qualifier Software Force Register --------------------------------------------------------*/ typedef struct { uint32_t ACTSFA :2; /*!< Action when one-time software force A is invoked */ uint32_t OTSFA :1; /*!< One-time software forced event on output A */ uint32_t ACTSFB :2; /*!< Action when one-time software force B is invoked */ uint32_t OTSFB :1; /*!< One-time software forced event on output B */ uint32_t RLDCSF :2; /*!< AQCSFRC active register reload from shadow options */ } _PWM_AQSFRC_bits; /* Bit field positions: */ #define PWM_AQSFRC_ACTSFA_Pos 0 /*!< Action when one-time software force A is invoked */ #define PWM_AQSFRC_OTSFA_Pos 2 /*!< One-time software forced event on output A */ #define PWM_AQSFRC_ACTSFB_Pos 3 /*!< Action when one-time software force B is invoked */ #define PWM_AQSFRC_OTSFB_Pos 5 /*!< One-time software forced event on output B */ #define PWM_AQSFRC_RLDCSF_Pos 6 /*!< AQCSFRC active register reload from shadow options */ /* Bit field masks: */ #define PWM_AQSFRC_ACTSFA_Msk 0x00000003UL /*!< Action when one-time software force A is invoked */ #define PWM_AQSFRC_OTSFA_Msk 0x00000004UL /*!< One-time software forced event on output A */ #define PWM_AQSFRC_ACTSFB_Msk 0x00000018UL /*!< Action when one-time software force B is invoked */ #define PWM_AQSFRC_OTSFB_Msk 0x00000020UL /*!< One-time software forced event on output B */ #define PWM_AQSFRC_RLDCSF_Msk 0x000000C0UL /*!< AQCSFRC active register reload from shadow options */ /* Bit field enums: */ typedef enum { PWM_AQSFRC_ACTSFA_NoAction = 0x0UL, /*!< no action */ PWM_AQSFRC_ACTSFA_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQSFRC_ACTSFA_Set = 0x2UL, /*!< set PWMA/PWMB */ PWM_AQSFRC_ACTSFA_Toogle = 0x3UL, /*!< inverse PWMA/PWMB */ } PWM_AQSFRC_ACTSFA_Enum; typedef enum { PWM_AQSFRC_ACTSFB_NoAction = 0x0UL, /*!< no action */ PWM_AQSFRC_ACTSFB_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQSFRC_ACTSFB_Set = 0x2UL, /*!< set PWMA/PWMB */ PWM_AQSFRC_ACTSFB_Toogle = 0x3UL, /*!< inverse PWMA/PWMB */ } PWM_AQSFRC_ACTSFB_Enum; typedef enum { PWM_AQSFRC_RLDCSF_CTREqZero = 0x0UL, /*!< load when CTR = 0 */ PWM_AQSFRC_RLDCSF_CTREqPRD = 0x1UL, /*!< load when CTR = PRD */ PWM_AQSFRC_RLDCSF_CTREqZeroPRD = 0x2UL, /*!< load when CTR = 0 or CTR = PRD */ PWM_AQSFRC_RLDCSF_NoShadow = 0x3UL, /*!< load immediatelly */ } PWM_AQSFRC_RLDCSF_Enum; /*-- AQCSFRC: Action-Qualifier Continuous Software Force Register --------------------------------------------*/ typedef struct { uint32_t CSFA :2; /*!< Continuous software force on output A */ uint32_t CSFB :2; /*!< Continuous software force on output B */ } _PWM_AQCSFRC_bits; /* Bit field positions: */ #define PWM_AQCSFRC_CSFA_Pos 0 /*!< Continuous software force on output A */ #define PWM_AQCSFRC_CSFB_Pos 2 /*!< Continuous software force on output B */ /* Bit field masks: */ #define PWM_AQCSFRC_CSFA_Msk 0x00000003UL /*!< Continuous software force on output A */ #define PWM_AQCSFRC_CSFB_Msk 0x0000000CUL /*!< Continuous software force on output B */ /* Bit field enums: */ typedef enum { PWM_AQCSFRC_CSFA_NoAction = 0x0UL, /*!< no action */ PWM_AQCSFRC_CSFA_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQCSFRC_CSFA_Set = 0x2UL, /*!< set PWMA/PWMB */ } PWM_AQCSFRC_CSFA_Enum; typedef enum { PWM_AQCSFRC_CSFB_NoAction = 0x0UL, /*!< no action */ PWM_AQCSFRC_CSFB_Clear = 0x1UL, /*!< clear PWMA/PWMB */ PWM_AQCSFRC_CSFB_Set = 0x2UL, /*!< set PWMA/PWMB */ } PWM_AQCSFRC_CSFB_Enum; /*-- DBCTL: Dead-Band Generator Control Register -------------------------------------------------------------*/ typedef struct { uint32_t OUTMODE :2; /*!< Dead-band output mode control */ uint32_t POLSEL :2; /*!< Polarity select control */ uint32_t INMODE :2; /*!< Dead band input mode control */ } _PWM_DBCTL_bits; /* Bit field positions: */ #define PWM_DBCTL_OUTMODE_Pos 0 /*!< Dead-band output mode control */ #define PWM_DBCTL_POLSEL_Pos 2 /*!< Polarity select control */ #define PWM_DBCTL_INMODE_Pos 4 /*!< Dead band input mode control */ /* Bit field masks: */ #define PWM_DBCTL_OUTMODE_Msk 0x00000003UL /*!< Dead-band output mode control */ #define PWM_DBCTL_POLSEL_Msk 0x0000000CUL /*!< Polarity select control */ #define PWM_DBCTL_INMODE_Msk 0x00000030UL /*!< Dead band input mode control */ /* Bit field enums: */ typedef enum { PWM_DBCTL_OUTMODE_NoSpec = 0x0UL, /*!< edge for deadtime is no specified */ PWM_DBCTL_OUTMODE_BNeg = 0x1UL, /*!< deadtime on PWMB negedge */ PWM_DBCTL_OUTMODE_APos = 0x2UL, /*!< deadtime on PWMA posedge */ PWM_DBCTL_OUTMODE_Apos_BNeg = 0x3UL, /*!< deadtime on PWMA posedge and PWMB negedge */ } PWM_DBCTL_OUTMODE_Enum; typedef enum { PWM_DBCTL_POLSEL_InvDisable = 0x0UL, /*!< inverse disabled */ PWM_DBCTL_POLSEL_InvA = 0x1UL, /*!< inverse on PWMA */ PWM_DBCTL_POLSEL_InvB = 0x2UL, /*!< inverse on PWMB */ PWM_DBCTL_POLSEL_InvAB = 0x3UL, /*!< inverse on PWMA and PWMB */ } PWM_DBCTL_POLSEL_Enum; typedef enum { PWM_DBCTL_INMODE_APosNeg = 0x0UL, /*!< PWMA is used for posedge and negedge control */ PWM_DBCTL_INMODE_ANeg_BPos = 0x1UL, /*!< PWMA is used for negedge and PWMB is used for posedge control */ PWM_DBCTL_INMODE_APos_BNeg = 0x2UL, /*!< PWMA is used for posedge and PWMB is used for negedge control */ PWM_DBCTL_INMODE_BPosNeg = 0x3UL, /*!< PWMB is used for posedge and negedge control */ } PWM_DBCTL_INMODE_Enum; /*-- DBRED: Dead-Band Generator Rising Edge Delay Register ---------------------------------------------------*/ typedef struct { uint32_t DEL :10; /*!< Rising edge delay count */ } _PWM_DBRED_bits; /* Bit field positions: */ #define PWM_DBRED_DEL_Pos 0 /*!< Rising edge delay count */ /* Bit field masks: */ #define PWM_DBRED_DEL_Msk 0x000003FFUL /*!< Rising edge delay count */ /*-- DBFED: Dead-Band Generator Falling Edge Delay Register --------------------------------------------------*/ typedef struct { uint32_t DEL :10; /*!< Falling edge delay count */ } _PWM_DBFED_bits; /* Bit field positions: */ #define PWM_DBFED_DEL_Pos 0 /*!< Falling edge delay count */ /* Bit field masks: */ #define PWM_DBFED_DEL_Msk 0x000003FFUL /*!< Falling edge delay count */ /*-- TZSEL: Trip-Zone Select Register ------------------------------------------------------------------------*/ typedef struct { uint32_t CBC0 :1; /*!< Cycle-by-Cycle trip-zone 0 enable */ uint32_t CBC1 :1; /*!< Cycle-by-Cycle trip-zone 1 enable */ uint32_t CBC2 :1; /*!< Cycle-by-Cycle trip-zone 2 enable */ uint32_t CBC3 :1; /*!< Cycle-by-Cycle trip-zone 3 enable */ uint32_t CBC4 :1; /*!< Cycle-by-Cycle trip-zone 4 enable */ uint32_t CBC5 :1; /*!< Cycle-by-Cycle trip-zone 5 enable */ uint32_t :2; /*!< RESERVED */ uint32_t OST0 :1; /*!< One-Shot trip-zone 0 enable */ uint32_t OST1 :1; /*!< One-Shot trip-zone 1 enable */ uint32_t OST2 :1; /*!< One-Shot trip-zone 2 enable */ uint32_t OST3 :1; /*!< One-Shot trip-zone 3 enable */ uint32_t OST4 :1; /*!< One-Shot trip-zone 4 enable */ uint32_t OST5 :1; /*!< One-Shot trip-zone 5 enable */ } _PWM_TZSEL_bits; /* Bit field positions: */ #define PWM_TZSEL_CBC0_Pos 0 /*!< Cycle-by-Cycle trip-zone 0 enable */ #define PWM_TZSEL_CBC1_Pos 1 /*!< Cycle-by-Cycle trip-zone 1 enable */ #define PWM_TZSEL_CBC2_Pos 2 /*!< Cycle-by-Cycle trip-zone 2 enable */ #define PWM_TZSEL_CBC3_Pos 3 /*!< Cycle-by-Cycle trip-zone 3 enable */ #define PWM_TZSEL_CBC4_Pos 4 /*!< Cycle-by-Cycle trip-zone 4 enable */ #define PWM_TZSEL_CBC5_Pos 5 /*!< Cycle-by-Cycle trip-zone 5 enable */ #define PWM_TZSEL_OST0_Pos 8 /*!< One-Shot trip-zone 0 enable */ #define PWM_TZSEL_OST1_Pos 9 /*!< One-Shot trip-zone 1 enable */ #define PWM_TZSEL_OST2_Pos 10 /*!< One-Shot trip-zone 2 enable */ #define PWM_TZSEL_OST3_Pos 11 /*!< One-Shot trip-zone 3 enable */ #define PWM_TZSEL_OST4_Pos 12 /*!< One-Shot trip-zone 4 enable */ #define PWM_TZSEL_OST5_Pos 13 /*!< One-Shot trip-zone 5 enable */ /* Bit field masks: */ #define PWM_TZSEL_CBC0_Msk 0x00000001UL /*!< Cycle-by-Cycle trip-zone 0 enable */ #define PWM_TZSEL_CBC1_Msk 0x00000002UL /*!< Cycle-by-Cycle trip-zone 1 enable */ #define PWM_TZSEL_CBC2_Msk 0x00000004UL /*!< Cycle-by-Cycle trip-zone 2 enable */ #define PWM_TZSEL_CBC3_Msk 0x00000008UL /*!< Cycle-by-Cycle trip-zone 3 enable */ #define PWM_TZSEL_CBC4_Msk 0x00000010UL /*!< Cycle-by-Cycle trip-zone 4 enable */ #define PWM_TZSEL_CBC5_Msk 0x00000020UL /*!< Cycle-by-Cycle trip-zone 5 enable */ #define PWM_TZSEL_OST0_Msk 0x00000100UL /*!< One-Shot trip-zone 0 enable */ #define PWM_TZSEL_OST1_Msk 0x00000200UL /*!< One-Shot trip-zone 1 enable */ #define PWM_TZSEL_OST2_Msk 0x00000400UL /*!< One-Shot trip-zone 2 enable */ #define PWM_TZSEL_OST3_Msk 0x00000800UL /*!< One-Shot trip-zone 3 enable */ #define PWM_TZSEL_OST4_Msk 0x00001000UL /*!< One-Shot trip-zone 4 enable */ #define PWM_TZSEL_OST5_Msk 0x00002000UL /*!< One-Shot trip-zone 5 enable */ /*-- TZCTL: Trip-Zone Control Register -----------------------------------------------------------------------*/ typedef struct { uint32_t TZA :2; /*!< When a trip event occurs the following action is taken on output A */ uint32_t TZB :2; /*!< When a trip event occurs the following action is taken on output B */ } _PWM_TZCTL_bits; /* Bit field positions: */ #define PWM_TZCTL_TZA_Pos 0 /*!< When a trip event occurs the following action is taken on output A */ #define PWM_TZCTL_TZB_Pos 2 /*!< When a trip event occurs the following action is taken on output B */ /* Bit field masks: */ #define PWM_TZCTL_TZA_Msk 0x00000003UL /*!< When a trip event occurs the following action is taken on output A */ #define PWM_TZCTL_TZB_Msk 0x0000000CUL /*!< When a trip event occurs the following action is taken on output B */ /* Bit field enums: */ typedef enum { PWM_TZCTL_TZA_Z = 0x0UL, /*!< PWMA/PWMB go to Z on failture */ PWM_TZCTL_TZA_Set = 0x1UL, /*!< PWMA/PWMB go to 1 on failture */ PWM_TZCTL_TZA_Clear = 0x2UL, /*!< PWMA/PWMB go to 0 on failture */ PWM_TZCTL_TZA_NoAction = 0x3UL, /*!< no action on failture */ } PWM_TZCTL_TZA_Enum; typedef enum { PWM_TZCTL_TZB_Z = 0x0UL, /*!< PWMA/PWMB go to Z on failture */ PWM_TZCTL_TZB_Set = 0x1UL, /*!< PWMA/PWMB go to 1 on failture */ PWM_TZCTL_TZB_Clear = 0x2UL, /*!< PWMA/PWMB go to 0 on failture */ PWM_TZCTL_TZB_NoAction = 0x3UL, /*!< no action on failture */ } PWM_TZCTL_TZB_Enum; /*-- TZEINT: Trip-Zone Enable Interrupt Register -------------------------------------------------------------*/ typedef struct { uint32_t :1; /*!< RESERVED */ uint32_t CBC :1; /*!< Trip-zone Cycle-by-Cycle interrupt enable */ uint32_t OST :1; /*!< Trip-zone One-Shot interrupt enable */ } _PWM_TZEINT_bits; /* Bit field positions: */ #define PWM_TZEINT_CBC_Pos 1 /*!< Trip-zone Cycle-by-Cycle interrupt enable */ #define PWM_TZEINT_OST_Pos 2 /*!< Trip-zone One-Shot interrupt enable */ /* Bit field masks: */ #define PWM_TZEINT_CBC_Msk 0x00000002UL /*!< Trip-zone Cycle-by-Cycle interrupt enable */ #define PWM_TZEINT_OST_Msk 0x00000004UL /*!< Trip-zone One-Shot interrupt enable */ /*-- TZFLG: Trip-Zone Flag Register --------------------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< Latched trip interrupt status flag */ uint32_t CBC :1; /*!< Latched status flag for Cycle-By-Cycle trip event */ uint32_t OST :1; /*!< Latched status flag for a One-Shot trip event */ } _PWM_TZFLG_bits; /* Bit field positions: */ #define PWM_TZFLG_INT_Pos 0 /*!< Latched trip interrupt status flag */ #define PWM_TZFLG_CBC_Pos 1 /*!< Latched status flag for Cycle-By-Cycle trip event */ #define PWM_TZFLG_OST_Pos 2 /*!< Latched status flag for a One-Shot trip event */ /* Bit field masks: */ #define PWM_TZFLG_INT_Msk 0x00000001UL /*!< Latched trip interrupt status flag */ #define PWM_TZFLG_CBC_Msk 0x00000002UL /*!< Latched status flag for Cycle-By-Cycle trip event */ #define PWM_TZFLG_OST_Msk 0x00000004UL /*!< Latched status flag for a One-Shot trip event */ /*-- TZCLR: Trip-Zone Clear Register -------------------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< Clear trip-zone interrupt flag */ uint32_t CBC :1; /*!< Clear flag for Cycle-By-Cycle trip latch */ uint32_t OST :1; /*!< Clear flag for One-Shot trip latch */ } _PWM_TZCLR_bits; /* Bit field positions: */ #define PWM_TZCLR_INT_Pos 0 /*!< Clear trip-zone interrupt flag */ #define PWM_TZCLR_CBC_Pos 1 /*!< Clear flag for Cycle-By-Cycle trip latch */ #define PWM_TZCLR_OST_Pos 2 /*!< Clear flag for One-Shot trip latch */ /* Bit field masks: */ #define PWM_TZCLR_INT_Msk 0x00000001UL /*!< Clear trip-zone interrupt flag */ #define PWM_TZCLR_CBC_Msk 0x00000002UL /*!< Clear flag for Cycle-By-Cycle trip latch */ #define PWM_TZCLR_OST_Msk 0x00000004UL /*!< Clear flag for One-Shot trip latch */ /*-- TZFRC: Trip-Zone Force Register -------------------------------------------------------------------------*/ typedef struct { uint32_t :1; /*!< RESERVED */ uint32_t CBC :1; /*!< Force a Cycle-by-Cycle trip event via software */ uint32_t OST :1; /*!< Force a One-Shot trip event via software */ } _PWM_TZFRC_bits; /* Bit field positions: */ #define PWM_TZFRC_CBC_Pos 1 /*!< Force a Cycle-by-Cycle trip event via software */ #define PWM_TZFRC_OST_Pos 2 /*!< Force a One-Shot trip event via software */ /* Bit field masks: */ #define PWM_TZFRC_CBC_Msk 0x00000002UL /*!< Force a Cycle-by-Cycle trip event via software */ #define PWM_TZFRC_OST_Msk 0x00000004UL /*!< Force a One-Shot trip event via software */ /*-- ETSEL: Event-Trigger Selection Register -----------------------------------------------------------------*/ typedef struct { uint32_t INTSEL :3; /*!< PWM_INT interrupt selection options */ uint32_t INTEN :1; /*!< Enable PWM_INT interrupt generation */ uint32_t :4; /*!< RESERVED */ uint32_t SOCASEL :3; /*!< PWM_SOCA selection Options */ uint32_t SOCAEN :1; /*!< Enable the ADC start of conversion A PWM_SOCA pulse */ uint32_t SOCBSEL :3; /*!< PWM_SOCB selection Options */ uint32_t SOCBEN :1; /*!< Enable the ADC start of conversion B PWM_SOCB pulse */ uint32_t DRQASEL :3; /*!< PWM A DMA request event selection */ uint32_t DRQAEN :1; /*!< Enable the DMA request from PWM A */ uint32_t DRQBSEL :3; /*!< PWM B DMA request event selection */ uint32_t DRQBEN :1; /*!< Enable the DMA request from PWM B */ } _PWM_ETSEL_bits; /* Bit field positions: */ #define PWM_ETSEL_INTSEL_Pos 0 /*!< PWM_INT interrupt selection options */ #define PWM_ETSEL_INTEN_Pos 3 /*!< Enable PWM_INT interrupt generation */ #define PWM_ETSEL_SOCASEL_Pos 8 /*!< PWM_SOCA selection Options */ #define PWM_ETSEL_SOCAEN_Pos 11 /*!< Enable the ADC start of conversion A PWM_SOCA pulse */ #define PWM_ETSEL_SOCBSEL_Pos 12 /*!< PWM_SOCB selection Options */ #define PWM_ETSEL_SOCBEN_Pos 15 /*!< Enable the ADC start of conversion B PWM_SOCB pulse */ #define PWM_ETSEL_DRQASEL_Pos 16 /*!< PWM A DMA request event selection */ #define PWM_ETSEL_DRQAEN_Pos 19 /*!< Enable the DMA request from PWM A */ #define PWM_ETSEL_DRQBSEL_Pos 20 /*!< PWM B DMA request event selection */ #define PWM_ETSEL_DRQBEN_Pos 23 /*!< Enable the DMA request from PWM B */ /* Bit field masks: */ #define PWM_ETSEL_INTSEL_Msk 0x00000007UL /*!< PWM_INT interrupt selection options */ #define PWM_ETSEL_INTEN_Msk 0x00000008UL /*!< Enable PWM_INT interrupt generation */ #define PWM_ETSEL_SOCASEL_Msk 0x00000700UL /*!< PWM_SOCA selection Options */ #define PWM_ETSEL_SOCAEN_Msk 0x00000800UL /*!< Enable the ADC start of conversion A PWM_SOCA pulse */ #define PWM_ETSEL_SOCBSEL_Msk 0x00007000UL /*!< PWM_SOCB selection Options */ #define PWM_ETSEL_SOCBEN_Msk 0x00008000UL /*!< Enable the ADC start of conversion B PWM_SOCB pulse */ #define PWM_ETSEL_DRQASEL_Msk 0x00070000UL /*!< PWM A DMA request event selection */ #define PWM_ETSEL_DRQAEN_Msk 0x00080000UL /*!< Enable the DMA request from PWM A */ #define PWM_ETSEL_DRQBSEL_Msk 0x00700000UL /*!< PWM B DMA request event selection */ #define PWM_ETSEL_DRQBEN_Msk 0x00800000UL /*!< Enable the DMA request from PWM B */ /* Bit field enums: */ typedef enum { PWM_ETSEL_INTSEL_CTREqZero = 0x1UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 */ PWM_ETSEL_INTSEL_CTREqPRD = 0x2UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD */ PWM_ETSEL_INTSEL_CTREqCMPA_OnUp = 0x4UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up */ PWM_ETSEL_INTSEL_CTREqCMPA_OnDown = 0x5UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down */ PWM_ETSEL_INTSEL_CTREqCMPB_OnUp = 0x6UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up */ PWM_ETSEL_INTSEL_CTREqCMPB_OnDown = 0x7UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down */ } PWM_ETSEL_INTSEL_Enum; typedef enum { PWM_ETSEL_SOCASEL_CTREqZero = 0x1UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 */ PWM_ETSEL_SOCASEL_CTREqPRD = 0x2UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD */ PWM_ETSEL_SOCASEL_CTREqCMPA_OnUp = 0x4UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up */ PWM_ETSEL_SOCASEL_CTREqCMPA_OnDown = 0x5UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down */ PWM_ETSEL_SOCASEL_CTREqCMPB_OnUp = 0x6UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up */ PWM_ETSEL_SOCASEL_CTREqCMPB_OnDown = 0x7UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down */ } PWM_ETSEL_SOCASEL_Enum; typedef enum { PWM_ETSEL_SOCBSEL_CTREqZero = 0x1UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 */ PWM_ETSEL_SOCBSEL_CTREqPRD = 0x2UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD */ PWM_ETSEL_SOCBSEL_CTREqCMPA_OnUp = 0x4UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up */ PWM_ETSEL_SOCBSEL_CTREqCMPA_OnDown = 0x5UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down */ PWM_ETSEL_SOCBSEL_CTREqCMPB_OnUp = 0x6UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up */ PWM_ETSEL_SOCBSEL_CTREqCMPB_OnDown = 0x7UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down */ } PWM_ETSEL_SOCBSEL_Enum; typedef enum { PWM_ETSEL_DRQASEL_CTREqZero = 0x1UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 */ PWM_ETSEL_DRQASEL_CTREqPRD = 0x2UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD */ PWM_ETSEL_DRQASEL_CTREqCMPA_OnUp = 0x4UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up */ PWM_ETSEL_DRQASEL_CTREqCMPA_OnDown = 0x5UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down */ PWM_ETSEL_DRQASEL_CTREqCMPB_OnUp = 0x6UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up */ PWM_ETSEL_DRQASEL_CTREqCMPB_OnDown = 0x7UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down */ } PWM_ETSEL_DRQASEL_Enum; typedef enum { PWM_ETSEL_DRQBSEL_CTREqZero = 0x1UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 */ PWM_ETSEL_DRQBSEL_CTREqPRD = 0x2UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD */ PWM_ETSEL_DRQBSEL_CTREqCMPA_OnUp = 0x4UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up */ PWM_ETSEL_DRQBSEL_CTREqCMPA_OnDown = 0x5UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down */ PWM_ETSEL_DRQBSEL_CTREqCMPB_OnUp = 0x6UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up */ PWM_ETSEL_DRQBSEL_CTREqCMPB_OnDown = 0x7UL, /*!< generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down */ } PWM_ETSEL_DRQBSEL_Enum; /*-- ETPS: Event-Trigger Prescale Register -------------------------------------------------------------------*/ typedef struct { uint32_t INTPRD :2; /*!< PWM interrupt (PWM_INT) period select */ uint32_t INTCNT :2; /*!< PWM interrupt event (PWM_INT) counter register */ uint32_t :4; /*!< RESERVED */ uint32_t SOCAPRD :2; /*!< PWM ADC Start-of-Conversion A event (PWM_SOCA) period select */ uint32_t SOCACNT :2; /*!< PWM ADC Start-of-Conversion A event (PWM_SOCA) counter register */ uint32_t SOCBPRD :2; /*!< PWM ADC Start-of-Conversion B event (PWM_SOCB) period select */ uint32_t SOCBCNT :2; /*!< PWM ADC Start-of-Conversion B event (PWM_SOCB) counter register */ uint32_t DRQAPRD :2; /*!< PWM DMA request A period select */ uint32_t DRQACNT :2; /*!< PWM DMA request event A counter */ uint32_t DRQBPRD :2; /*!< PWM DMA request B period select */ uint32_t DRQBCNT :2; /*!< PWM DMA request event B counter */ } _PWM_ETPS_bits; /* Bit field positions: */ #define PWM_ETPS_INTPRD_Pos 0 /*!< PWM interrupt (PWM_INT) period select */ #define PWM_ETPS_INTCNT_Pos 2 /*!< PWM interrupt event (PWM_INT) counter register */ #define PWM_ETPS_SOCAPRD_Pos 8 /*!< PWM ADC Start-of-Conversion A event (PWM_SOCA) period select */ #define PWM_ETPS_SOCACNT_Pos 10 /*!< PWM ADC Start-of-Conversion A event (PWM_SOCA) counter register */ #define PWM_ETPS_SOCBPRD_Pos 12 /*!< PWM ADC Start-of-Conversion B event (PWM_SOCB) period select */ #define PWM_ETPS_SOCBCNT_Pos 14 /*!< PWM ADC Start-of-Conversion B event (PWM_SOCB) counter register */ #define PWM_ETPS_DRQAPRD_Pos 16 /*!< PWM DMA request A period select */ #define PWM_ETPS_DRQACNT_Pos 18 /*!< PWM DMA request event A counter */ #define PWM_ETPS_DRQBPRD_Pos 20 /*!< PWM DMA request B period select */ #define PWM_ETPS_DRQBCNT_Pos 22 /*!< PWM DMA request event B counter */ /* Bit field masks: */ #define PWM_ETPS_INTPRD_Msk 0x00000003UL /*!< PWM interrupt (PWM_INT) period select */ #define PWM_ETPS_INTCNT_Msk 0x0000000CUL /*!< PWM interrupt event (PWM_INT) counter register */ #define PWM_ETPS_SOCAPRD_Msk 0x00000300UL /*!< PWM ADC Start-of-Conversion A event (PWM_SOCA) period select */ #define PWM_ETPS_SOCACNT_Msk 0x00000C00UL /*!< PWM ADC Start-of-Conversion A event (PWM_SOCA) counter register */ #define PWM_ETPS_SOCBPRD_Msk 0x00003000UL /*!< PWM ADC Start-of-Conversion B event (PWM_SOCB) period select */ #define PWM_ETPS_SOCBCNT_Msk 0x0000C000UL /*!< PWM ADC Start-of-Conversion B event (PWM_SOCB) counter register */ #define PWM_ETPS_DRQAPRD_Msk 0x00030000UL /*!< PWM DMA request A period select */ #define PWM_ETPS_DRQACNT_Msk 0x000C0000UL /*!< PWM DMA request event A counter */ #define PWM_ETPS_DRQBPRD_Msk 0x00300000UL /*!< PWM DMA request B period select */ #define PWM_ETPS_DRQBCNT_Msk 0x00C00000UL /*!< PWM DMA request event B counter */ /*-- ETFLG: Event-Trigger Flag Register ----------------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< Latched PWM Interrupt (PWM_INT) status flag */ uint32_t :1; /*!< RESERVED */ uint32_t SOCA :1; /*!< Latched PWM ADC Start-of-Conversion A (PWM_SOCA) status flag */ uint32_t SOCB :1; /*!< Latched PWM ADC Start-of-Conversion B (PWM_SOCB) status flag */ uint32_t DRQA :1; /*!< Latched PWM DMA request A status flag */ uint32_t DRQB :1; /*!< Latched PWM DMA request B status flag */ } _PWM_ETFLG_bits; /* Bit field positions: */ #define PWM_ETFLG_INT_Pos 0 /*!< Latched PWM Interrupt (PWM_INT) status flag */ #define PWM_ETFLG_SOCA_Pos 2 /*!< Latched PWM ADC Start-of-Conversion A (PWM_SOCA) status flag */ #define PWM_ETFLG_SOCB_Pos 3 /*!< Latched PWM ADC Start-of-Conversion B (PWM_SOCB) status flag */ #define PWM_ETFLG_DRQA_Pos 4 /*!< Latched PWM DMA request A status flag */ #define PWM_ETFLG_DRQB_Pos 5 /*!< Latched PWM DMA request B status flag */ /* Bit field masks: */ #define PWM_ETFLG_INT_Msk 0x00000001UL /*!< Latched PWM Interrupt (PWM_INT) status flag */ #define PWM_ETFLG_SOCA_Msk 0x00000004UL /*!< Latched PWM ADC Start-of-Conversion A (PWM_SOCA) status flag */ #define PWM_ETFLG_SOCB_Msk 0x00000008UL /*!< Latched PWM ADC Start-of-Conversion B (PWM_SOCB) status flag */ #define PWM_ETFLG_DRQA_Msk 0x00000010UL /*!< Latched PWM DMA request A status flag */ #define PWM_ETFLG_DRQB_Msk 0x00000020UL /*!< Latched PWM DMA request B status flag */ /*-- ETCLR: Event-Trigger Clear Register ---------------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< Latched PWM Interrupt (PWM_INT) flag clear bit */ uint32_t :1; /*!< RESERVED */ uint32_t SOCA :1; /*!< Latched PWM ADC Start-of-Conversion A (PWM_SOCA) flag clear bit */ uint32_t SOCB :1; /*!< Latched PWM ADC Start-of-Conversion B (PWM_SOCB) flag clear bit */ uint32_t DRQA :1; /*!< Latched PWM DMA request A flag clear bit */ uint32_t DRQB :1; /*!< Latched PWM DMA request B flag clear bit */ } _PWM_ETCLR_bits; /* Bit field positions: */ #define PWM_ETCLR_INT_Pos 0 /*!< Latched PWM Interrupt (PWM_INT) flag clear bit */ #define PWM_ETCLR_SOCA_Pos 2 /*!< Latched PWM ADC Start-of-Conversion A (PWM_SOCA) flag clear bit */ #define PWM_ETCLR_SOCB_Pos 3 /*!< Latched PWM ADC Start-of-Conversion B (PWM_SOCB) flag clear bit */ #define PWM_ETCLR_DRQA_Pos 4 /*!< Latched PWM DMA request A flag clear bit */ #define PWM_ETCLR_DRQB_Pos 5 /*!< Latched PWM DMA request B flag clear bit */ /* Bit field masks: */ #define PWM_ETCLR_INT_Msk 0x00000001UL /*!< Latched PWM Interrupt (PWM_INT) flag clear bit */ #define PWM_ETCLR_SOCA_Msk 0x00000004UL /*!< Latched PWM ADC Start-of-Conversion A (PWM_SOCA) flag clear bit */ #define PWM_ETCLR_SOCB_Msk 0x00000008UL /*!< Latched PWM ADC Start-of-Conversion B (PWM_SOCB) flag clear bit */ #define PWM_ETCLR_DRQA_Msk 0x00000010UL /*!< Latched PWM DMA request A flag clear bit */ #define PWM_ETCLR_DRQB_Msk 0x00000020UL /*!< Latched PWM DMA request B flag clear bit */ /*-- ETFRC: Event-Trigger Force Register ---------------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< PWM_INT force bit. */ uint32_t :1; /*!< RESERVED */ uint32_t SOCA :1; /*!< PWM_SOCA force bit */ uint32_t SOCB :1; /*!< PWM_SOCB force bit */ uint32_t DRQA :1; /*!< PWM DMA request A force bit */ uint32_t DRQB :1; /*!< PWM DMA request B force bit */ } _PWM_ETFRC_bits; /* Bit field positions: */ #define PWM_ETFRC_INT_Pos 0 /*!< PWM_INT force bit. */ #define PWM_ETFRC_SOCA_Pos 2 /*!< PWM_SOCA force bit */ #define PWM_ETFRC_SOCB_Pos 3 /*!< PWM_SOCB force bit */ #define PWM_ETFRC_DRQA_Pos 4 /*!< PWM DMA request A force bit */ #define PWM_ETFRC_DRQB_Pos 5 /*!< PWM DMA request B force bit */ /* Bit field masks: */ #define PWM_ETFRC_INT_Msk 0x00000001UL /*!< PWM_INT force bit. */ #define PWM_ETFRC_SOCA_Msk 0x00000004UL /*!< PWM_SOCA force bit */ #define PWM_ETFRC_SOCB_Msk 0x00000008UL /*!< PWM_SOCB force bit */ #define PWM_ETFRC_DRQA_Msk 0x00000010UL /*!< PWM DMA request A force bit */ #define PWM_ETFRC_DRQB_Msk 0x00000020UL /*!< PWM DMA request B force bit */ /*-- PCCTL: PWM-Chopper Control Register ---------------------------------------------------------------------*/ typedef struct { uint32_t CHPEN :1; /*!< PWM-chopping enable */ uint32_t OSTWTH :4; /*!< One-Shot pulse width */ uint32_t CHPFREQ :3; /*!< Chopping clock frequency */ uint32_t CHPDUTY :3; /*!< Chopping clock duty cycle */ } _PWM_PCCTL_bits; /* Bit field positions: */ #define PWM_PCCTL_CHPEN_Pos 0 /*!< PWM-chopping enable */ #define PWM_PCCTL_OSTWTH_Pos 1 /*!< One-Shot pulse width */ #define PWM_PCCTL_CHPFREQ_Pos 5 /*!< Chopping clock frequency */ #define PWM_PCCTL_CHPDUTY_Pos 8 /*!< Chopping clock duty cycle */ /* Bit field masks: */ #define PWM_PCCTL_CHPEN_Msk 0x00000001UL /*!< PWM-chopping enable */ #define PWM_PCCTL_OSTWTH_Msk 0x0000001EUL /*!< One-Shot pulse width */ #define PWM_PCCTL_CHPFREQ_Msk 0x000000E0UL /*!< Chopping clock frequency */ #define PWM_PCCTL_CHPDUTY_Msk 0x00000700UL /*!< Chopping clock duty cycle */ /* Bit field enums: */ typedef enum { PWM_PCCTL_CHPFREQ_Div1 = 0x0UL, /*!< sync frequency divide by 1 */ PWM_PCCTL_CHPFREQ_Div2 = 0x1UL, /*!< sync frequency divide by 2 */ PWM_PCCTL_CHPFREQ_Div3 = 0x2UL, /*!< sync frequency divide by 3 */ PWM_PCCTL_CHPFREQ_Div4 = 0x3UL, /*!< sync frequency divide by 4 */ PWM_PCCTL_CHPFREQ_Div5 = 0x4UL, /*!< sync frequency divide by 5 */ PWM_PCCTL_CHPFREQ_Div6 = 0x5UL, /*!< sync frequency divide by 6 */ PWM_PCCTL_CHPFREQ_Div7 = 0x6UL, /*!< sync frequency divide by 7 */ PWM_PCCTL_CHPFREQ_Div8 = 0x7UL, /*!< sync frequency divide by 8 */ } PWM_PCCTL_CHPFREQ_Enum; typedef enum { PWM_PCCTL_CHPDUTY_Duty_1_8 = 0x0UL, /*!< duty 1/8 */ PWM_PCCTL_CHPDUTY_Duty_2_8 = 0x1UL, /*!< duty 2/8 */ PWM_PCCTL_CHPDUTY_Duty_3_8 = 0x2UL, /*!< duty 3/8 */ PWM_PCCTL_CHPDUTY_Duty_4_8 = 0x3UL, /*!< duty 4/8 */ PWM_PCCTL_CHPDUTY_Duty_5_8 = 0x4UL, /*!< duty 5/8 */ PWM_PCCTL_CHPDUTY_Duty_6_8 = 0x5UL, /*!< duty 6/8 */ PWM_PCCTL_CHPDUTY_Duty_7_8 = 0x6UL, /*!< duty 7/8 */ } PWM_PCCTL_CHPDUTY_Enum; /*-- HRCTL: High-Resolution Control Register -----------------------------------------------------------------*/ typedef struct { uint32_t EDGMODEA :2; /*!< Edge selecting for delay on chanel A */ uint32_t CTLMODEA :1; /*!< Register specifies the delay select on chanel A */ uint32_t HRLOAD :1; /*!< CMPAHR register shadow load mode */ uint32_t EDGMODEB :2; /*!< Edge selecting for delay on chanel B */ uint32_t CTLMODEB :1; /*!< Register specifies the delay select on chanel B */ uint32_t :1; /*!< RESERVED */ uint32_t DELAYCALA :2; /*!< Delay calibration flags of chanel A */ uint32_t DELAYCALB :2; /*!< Delay calibration flags of chanel B */ } _PWM_HRCTL_bits; /* Bit field positions: */ #define PWM_HRCTL_EDGMODEA_Pos 0 /*!< Edge selecting for delay on chanel A */ #define PWM_HRCTL_CTLMODEA_Pos 2 /*!< Register specifies the delay select on chanel A */ #define PWM_HRCTL_HRLOAD_Pos 3 /*!< CMPAHR register shadow load mode */ #define PWM_HRCTL_EDGMODEB_Pos 4 /*!< Edge selecting for delay on chanel B */ #define PWM_HRCTL_CTLMODEB_Pos 6 /*!< Register specifies the delay select on chanel B */ #define PWM_HRCTL_DELAYCALA_Pos 8 /*!< Delay calibration flags of chanel A */ #define PWM_HRCTL_DELAYCALB_Pos 10 /*!< Delay calibration flags of chanel B */ /* Bit field masks: */ #define PWM_HRCTL_EDGMODEA_Msk 0x00000003UL /*!< Edge selecting for delay on chanel A */ #define PWM_HRCTL_CTLMODEA_Msk 0x00000004UL /*!< Register specifies the delay select on chanel A */ #define PWM_HRCTL_HRLOAD_Msk 0x00000008UL /*!< CMPAHR register shadow load mode */ #define PWM_HRCTL_EDGMODEB_Msk 0x00000030UL /*!< Edge selecting for delay on chanel B */ #define PWM_HRCTL_CTLMODEB_Msk 0x00000040UL /*!< Register specifies the delay select on chanel B */ #define PWM_HRCTL_DELAYCALA_Msk 0x00000300UL /*!< Delay calibration flags of chanel A */ #define PWM_HRCTL_DELAYCALB_Msk 0x00000C00UL /*!< Delay calibration flags of chanel B */ /* Bit field enums: */ typedef enum { PWM_HRCTL_EDGMODEA_PosEdge = 0x1UL, /*!< posedge will be delayed */ PWM_HRCTL_EDGMODEA_NegEdge = 0x2UL, /*!< negedge will be delayed */ PWM_HRCTL_EDGMODEA_BothEdge = 0x3UL, /*!< posedge and negedge will be delayed */ } PWM_HRCTL_EDGMODEA_Enum; typedef enum { PWM_HRCTL_CTLMODEA_CMPAHR = 0x0UL, /*!< delay source in CMPA reg */ PWM_HRCTL_CTLMODEA_TBPHSHR = 0x1UL, /*!< delay source in TBPHS reg */ } PWM_HRCTL_CTLMODEA_Enum; typedef enum { PWM_HRCTL_EDGMODEB_PosEdge = 0x1UL, /*!< posedge will be delayed */ PWM_HRCTL_EDGMODEB_NegEdge = 0x2UL, /*!< negedge will be delayed */ PWM_HRCTL_EDGMODEB_BothEdge = 0x3UL, /*!< posedge and negedge will be delayed */ } PWM_HRCTL_EDGMODEB_Enum; typedef enum { PWM_HRCTL_CTLMODEB_CMPAHR = 0x0UL, /*!< delay source in CMPA reg */ PWM_HRCTL_CTLMODEB_TBPHSHR = 0x1UL, /*!< delay source in TBPHS reg */ } PWM_HRCTL_CTLMODEB_Enum; /*-- FWDTH: Filter Width select Register ---------------------------------------------------------------------*/ typedef struct { uint32_t VAL :8; /*!< Pulse filter width selection */ } _PWM_FWDTH_bits; /* Bit field positions: */ #define PWM_FWDTH_VAL_Pos 0 /*!< Pulse filter width selection */ /* Bit field masks: */ #define PWM_FWDTH_VAL_Msk 0x000000FFUL /*!< Pulse filter width selection */ /*-- HDSEL0: Hold Detector event Select Register 0 -----------------------------------------------------------*/ typedef struct { uint32_t ADCDC0 :1; /*!< Hold detector event by ADC Digital Comparator 0 enable */ uint32_t ADCDC1 :1; /*!< Hold detector event by ADC Digital Comparator 1 enable */ uint32_t ADCDC2 :1; /*!< Hold detector event by ADC Digital Comparator 2 enable */ uint32_t ADCDC3 :1; /*!< Hold detector event by ADC Digital Comparator 3 enable */ uint32_t ADCDC4 :1; /*!< Hold detector event by ADC Digital Comparator 4 enable */ uint32_t ADCDC5 :1; /*!< Hold detector event by ADC Digital Comparator 5 enable */ uint32_t ADCDC6 :1; /*!< Hold detector event by ADC Digital Comparator 6 enable */ uint32_t ADCDC7 :1; /*!< Hold detector event by ADC Digital Comparator 7 enable */ uint32_t ADCDC8 :1; /*!< Hold detector event by ADC Digital Comparator 8 enable */ uint32_t ADCDC9 :1; /*!< Hold detector event by ADC Digital Comparator 9 enable */ uint32_t ADCDC10 :1; /*!< Hold detector event by ADC Digital Comparator 10 enable */ uint32_t ADCDC11 :1; /*!< Hold detector event by ADC Digital Comparator 11 enable */ uint32_t ADCDC12 :1; /*!< Hold detector event by ADC Digital Comparator 12 enable */ uint32_t ADCDC13 :1; /*!< Hold detector event by ADC Digital Comparator 13 enable */ uint32_t ADCDC14 :1; /*!< Hold detector event by ADC Digital Comparator 14 enable */ uint32_t ADCDC15 :1; /*!< Hold detector event by ADC Digital Comparator 15 enable */ uint32_t ADCDC16 :1; /*!< Hold detector event by ADC Digital Comparator 16 enable */ uint32_t ADCDC17 :1; /*!< Hold detector event by ADC Digital Comparator 17 enable */ uint32_t ADCDC18 :1; /*!< Hold detector event by ADC Digital Comparator 18 enable */ uint32_t ADCDC19 :1; /*!< Hold detector event by ADC Digital Comparator 19 enable */ uint32_t ADCDC20 :1; /*!< Hold detector event by ADC Digital Comparator 20 enable */ uint32_t ADCDC21 :1; /*!< Hold detector event by ADC Digital Comparator 21 enable */ uint32_t ADCDC22 :1; /*!< Hold detector event by ADC Digital Comparator 22 enable */ uint32_t ADCDC23 :1; /*!< Hold detector event by ADC Digital Comparator 23 enable */ } _PWM_HDSEL0_bits; /* Bit field positions: */ #define PWM_HDSEL0_ADCDC0_Pos 0 /*!< Hold detector event by ADC Digital Comparator 0 enable */ #define PWM_HDSEL0_ADCDC1_Pos 1 /*!< Hold detector event by ADC Digital Comparator 1 enable */ #define PWM_HDSEL0_ADCDC2_Pos 2 /*!< Hold detector event by ADC Digital Comparator 2 enable */ #define PWM_HDSEL0_ADCDC3_Pos 3 /*!< Hold detector event by ADC Digital Comparator 3 enable */ #define PWM_HDSEL0_ADCDC4_Pos 4 /*!< Hold detector event by ADC Digital Comparator 4 enable */ #define PWM_HDSEL0_ADCDC5_Pos 5 /*!< Hold detector event by ADC Digital Comparator 5 enable */ #define PWM_HDSEL0_ADCDC6_Pos 6 /*!< Hold detector event by ADC Digital Comparator 6 enable */ #define PWM_HDSEL0_ADCDC7_Pos 7 /*!< Hold detector event by ADC Digital Comparator 7 enable */ #define PWM_HDSEL0_ADCDC8_Pos 8 /*!< Hold detector event by ADC Digital Comparator 8 enable */ #define PWM_HDSEL0_ADCDC9_Pos 9 /*!< Hold detector event by ADC Digital Comparator 9 enable */ #define PWM_HDSEL0_ADCDC10_Pos 10 /*!< Hold detector event by ADC Digital Comparator 10 enable */ #define PWM_HDSEL0_ADCDC11_Pos 11 /*!< Hold detector event by ADC Digital Comparator 11 enable */ #define PWM_HDSEL0_ADCDC12_Pos 12 /*!< Hold detector event by ADC Digital Comparator 12 enable */ #define PWM_HDSEL0_ADCDC13_Pos 13 /*!< Hold detector event by ADC Digital Comparator 13 enable */ #define PWM_HDSEL0_ADCDC14_Pos 14 /*!< Hold detector event by ADC Digital Comparator 14 enable */ #define PWM_HDSEL0_ADCDC15_Pos 15 /*!< Hold detector event by ADC Digital Comparator 15 enable */ #define PWM_HDSEL0_ADCDC16_Pos 16 /*!< Hold detector event by ADC Digital Comparator 16 enable */ #define PWM_HDSEL0_ADCDC17_Pos 17 /*!< Hold detector event by ADC Digital Comparator 17 enable */ #define PWM_HDSEL0_ADCDC18_Pos 18 /*!< Hold detector event by ADC Digital Comparator 18 enable */ #define PWM_HDSEL0_ADCDC19_Pos 19 /*!< Hold detector event by ADC Digital Comparator 19 enable */ #define PWM_HDSEL0_ADCDC20_Pos 20 /*!< Hold detector event by ADC Digital Comparator 20 enable */ #define PWM_HDSEL0_ADCDC21_Pos 21 /*!< Hold detector event by ADC Digital Comparator 21 enable */ #define PWM_HDSEL0_ADCDC22_Pos 22 /*!< Hold detector event by ADC Digital Comparator 22 enable */ #define PWM_HDSEL0_ADCDC23_Pos 23 /*!< Hold detector event by ADC Digital Comparator 23 enable */ /* Bit field masks: */ #define PWM_HDSEL0_ADCDC0_Msk 0x00000001UL /*!< Hold detector event by ADC Digital Comparator 0 enable */ #define PWM_HDSEL0_ADCDC1_Msk 0x00000002UL /*!< Hold detector event by ADC Digital Comparator 1 enable */ #define PWM_HDSEL0_ADCDC2_Msk 0x00000004UL /*!< Hold detector event by ADC Digital Comparator 2 enable */ #define PWM_HDSEL0_ADCDC3_Msk 0x00000008UL /*!< Hold detector event by ADC Digital Comparator 3 enable */ #define PWM_HDSEL0_ADCDC4_Msk 0x00000010UL /*!< Hold detector event by ADC Digital Comparator 4 enable */ #define PWM_HDSEL0_ADCDC5_Msk 0x00000020UL /*!< Hold detector event by ADC Digital Comparator 5 enable */ #define PWM_HDSEL0_ADCDC6_Msk 0x00000040UL /*!< Hold detector event by ADC Digital Comparator 6 enable */ #define PWM_HDSEL0_ADCDC7_Msk 0x00000080UL /*!< Hold detector event by ADC Digital Comparator 7 enable */ #define PWM_HDSEL0_ADCDC8_Msk 0x00000100UL /*!< Hold detector event by ADC Digital Comparator 8 enable */ #define PWM_HDSEL0_ADCDC9_Msk 0x00000200UL /*!< Hold detector event by ADC Digital Comparator 9 enable */ #define PWM_HDSEL0_ADCDC10_Msk 0x00000400UL /*!< Hold detector event by ADC Digital Comparator 10 enable */ #define PWM_HDSEL0_ADCDC11_Msk 0x00000800UL /*!< Hold detector event by ADC Digital Comparator 11 enable */ #define PWM_HDSEL0_ADCDC12_Msk 0x00001000UL /*!< Hold detector event by ADC Digital Comparator 12 enable */ #define PWM_HDSEL0_ADCDC13_Msk 0x00002000UL /*!< Hold detector event by ADC Digital Comparator 13 enable */ #define PWM_HDSEL0_ADCDC14_Msk 0x00004000UL /*!< Hold detector event by ADC Digital Comparator 14 enable */ #define PWM_HDSEL0_ADCDC15_Msk 0x00008000UL /*!< Hold detector event by ADC Digital Comparator 15 enable */ #define PWM_HDSEL0_ADCDC16_Msk 0x00010000UL /*!< Hold detector event by ADC Digital Comparator 16 enable */ #define PWM_HDSEL0_ADCDC17_Msk 0x00020000UL /*!< Hold detector event by ADC Digital Comparator 17 enable */ #define PWM_HDSEL0_ADCDC18_Msk 0x00040000UL /*!< Hold detector event by ADC Digital Comparator 18 enable */ #define PWM_HDSEL0_ADCDC19_Msk 0x00080000UL /*!< Hold detector event by ADC Digital Comparator 19 enable */ #define PWM_HDSEL0_ADCDC20_Msk 0x00100000UL /*!< Hold detector event by ADC Digital Comparator 20 enable */ #define PWM_HDSEL0_ADCDC21_Msk 0x00200000UL /*!< Hold detector event by ADC Digital Comparator 21 enable */ #define PWM_HDSEL0_ADCDC22_Msk 0x00400000UL /*!< Hold detector event by ADC Digital Comparator 22 enable */ #define PWM_HDSEL0_ADCDC23_Msk 0x00800000UL /*!< Hold detector event by ADC Digital Comparator 23 enable */ /*-- HDSEL1: Hold Detector event Select Register 1 -----------------------------------------------------------*/ typedef struct { uint32_t SDFMH0 :1; /*!< Hold detector event by SDFM CMP0 signal Hi enable */ uint32_t SDFMH1 :1; /*!< Hold detector event by SDFM CMP1 signal Hi enable */ uint32_t SDFMH2 :1; /*!< Hold detector event by SDFM CMP2 signal Hi enable */ uint32_t SDFMH3 :1; /*!< Hold detector event by SDFM CMP3 signal Hi enable */ uint32_t SDFML0 :1; /*!< Hold detector event by SDFM CMP0 signal Low enable */ uint32_t SDFML1 :1; /*!< Hold detector event by SDFM CMP1 signal Low enable */ uint32_t SDFML2 :1; /*!< Hold detector event by SDFM CMP2 signal Low enable */ uint32_t SDFML3 :1; /*!< Hold detector event by SDFM CMP3 signal Low enable */ uint32_t SDFMZ0 :1; /*!< Hold detector event by SDFM CMP0 signal Hi-Z enable */ uint32_t SDFMZ1 :1; /*!< Hold detector event by SDFM CMP1 signal Hi-Z enable */ uint32_t SDFMZ2 :1; /*!< Hold detector event by SDFM CMP2 signal Hi-Z enable */ uint32_t SDFMZ3 :1; /*!< Hold detector event by SDFM CMP3 signal Hi-Z enable */ } _PWM_HDSEL1_bits; /* Bit field positions: */ #define PWM_HDSEL1_SDFMH0_Pos 0 /*!< Hold detector event by SDFM CMP0 signal Hi enable */ #define PWM_HDSEL1_SDFMH1_Pos 1 /*!< Hold detector event by SDFM CMP1 signal Hi enable */ #define PWM_HDSEL1_SDFMH2_Pos 2 /*!< Hold detector event by SDFM CMP2 signal Hi enable */ #define PWM_HDSEL1_SDFMH3_Pos 3 /*!< Hold detector event by SDFM CMP3 signal Hi enable */ #define PWM_HDSEL1_SDFML0_Pos 4 /*!< Hold detector event by SDFM CMP0 signal Low enable */ #define PWM_HDSEL1_SDFML1_Pos 5 /*!< Hold detector event by SDFM CMP1 signal Low enable */ #define PWM_HDSEL1_SDFML2_Pos 6 /*!< Hold detector event by SDFM CMP2 signal Low enable */ #define PWM_HDSEL1_SDFML3_Pos 7 /*!< Hold detector event by SDFM CMP3 signal Low enable */ #define PWM_HDSEL1_SDFMZ0_Pos 8 /*!< Hold detector event by SDFM CMP0 signal Hi-Z enable */ #define PWM_HDSEL1_SDFMZ1_Pos 9 /*!< Hold detector event by SDFM CMP1 signal Hi-Z enable */ #define PWM_HDSEL1_SDFMZ2_Pos 10 /*!< Hold detector event by SDFM CMP2 signal Hi-Z enable */ #define PWM_HDSEL1_SDFMZ3_Pos 11 /*!< Hold detector event by SDFM CMP3 signal Hi-Z enable */ /* Bit field masks: */ #define PWM_HDSEL1_SDFMH0_Msk 0x00000001UL /*!< Hold detector event by SDFM CMP0 signal Hi enable */ #define PWM_HDSEL1_SDFMH1_Msk 0x00000002UL /*!< Hold detector event by SDFM CMP1 signal Hi enable */ #define PWM_HDSEL1_SDFMH2_Msk 0x00000004UL /*!< Hold detector event by SDFM CMP2 signal Hi enable */ #define PWM_HDSEL1_SDFMH3_Msk 0x00000008UL /*!< Hold detector event by SDFM CMP3 signal Hi enable */ #define PWM_HDSEL1_SDFML0_Msk 0x00000010UL /*!< Hold detector event by SDFM CMP0 signal Low enable */ #define PWM_HDSEL1_SDFML1_Msk 0x00000020UL /*!< Hold detector event by SDFM CMP1 signal Low enable */ #define PWM_HDSEL1_SDFML2_Msk 0x00000040UL /*!< Hold detector event by SDFM CMP2 signal Low enable */ #define PWM_HDSEL1_SDFML3_Msk 0x00000080UL /*!< Hold detector event by SDFM CMP3 signal Low enable */ #define PWM_HDSEL1_SDFMZ0_Msk 0x00000100UL /*!< Hold detector event by SDFM CMP0 signal Hi-Z enable */ #define PWM_HDSEL1_SDFMZ1_Msk 0x00000200UL /*!< Hold detector event by SDFM CMP1 signal Hi-Z enable */ #define PWM_HDSEL1_SDFMZ2_Msk 0x00000400UL /*!< Hold detector event by SDFM CMP2 signal Hi-Z enable */ #define PWM_HDSEL1_SDFMZ3_Msk 0x00000800UL /*!< Hold detector event by SDFM CMP3 signal Hi-Z enable */ /*-- HDCTL: Hold Detector Control register -------------------------------------------------------------------*/ typedef struct { uint32_t HDA :2; /*!< Action when hold detection A is invoked */ uint32_t HDB :2; /*!< Action when hold detection B is invoked */ uint32_t :4; /*!< RESERVED */ uint32_t CBC :1; /*!< Cycle-by-Cycle hold detector enable */ uint32_t :3; /*!< RESERVED */ uint32_t OST :1; /*!< One-Shot hold detector enable */ } _PWM_HDCTL_bits; /* Bit field positions: */ #define PWM_HDCTL_HDA_Pos 0 /*!< Action when hold detection A is invoked */ #define PWM_HDCTL_HDB_Pos 2 /*!< Action when hold detection B is invoked */ #define PWM_HDCTL_CBC_Pos 8 /*!< Cycle-by-Cycle hold detector enable */ #define PWM_HDCTL_OST_Pos 12 /*!< One-Shot hold detector enable */ /* Bit field masks: */ #define PWM_HDCTL_HDA_Msk 0x00000003UL /*!< Action when hold detection A is invoked */ #define PWM_HDCTL_HDB_Msk 0x0000000CUL /*!< Action when hold detection B is invoked */ #define PWM_HDCTL_CBC_Msk 0x00000100UL /*!< Cycle-by-Cycle hold detector enable */ #define PWM_HDCTL_OST_Msk 0x00001000UL /*!< One-Shot hold detector enable */ /* Bit field enums: */ typedef enum { PWM_HDCTL_HDA_Set = 0x1UL, /*!< PWMA/PWMB go to 1 on failture */ PWM_HDCTL_HDA_Clear = 0x2UL, /*!< PWMA/PWMB go to 0 on failture */ PWM_HDCTL_HDA_NoAction = 0x3UL, /*!< no action on failture */ } PWM_HDCTL_HDA_Enum; typedef enum { PWM_HDCTL_HDB_Set = 0x1UL, /*!< PWMA/PWMB go to 1 on failture */ PWM_HDCTL_HDB_Clear = 0x2UL, /*!< PWMA/PWMB go to 0 on failture */ PWM_HDCTL_HDB_NoAction = 0x3UL, /*!< no action on failture */ } PWM_HDCTL_HDB_Enum; /*-- HDEINT: Hold Detector Enable Interrupt Register ---------------------------------------------------------*/ typedef struct { uint32_t :1; /*!< RESERVED */ uint32_t CBC :1; /*!< Hold detector Cycle-by-Cycle interrupt enable */ uint32_t OST :1; /*!< Hold detector One-Shot interrupt enable */ } _PWM_HDEINT_bits; /* Bit field positions: */ #define PWM_HDEINT_CBC_Pos 1 /*!< Hold detector Cycle-by-Cycle interrupt enable */ #define PWM_HDEINT_OST_Pos 2 /*!< Hold detector One-Shot interrupt enable */ /* Bit field masks: */ #define PWM_HDEINT_CBC_Msk 0x00000002UL /*!< Hold detector Cycle-by-Cycle interrupt enable */ #define PWM_HDEINT_OST_Msk 0x00000004UL /*!< Hold detector One-Shot interrupt enable */ /*-- HDFLG: Hold Detector Flag Register ----------------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< Latched hold detector interrupt status flag */ uint32_t CBC :1; /*!< Latched status flag for hold detector Cycle-by-Cycle event */ uint32_t OST :1; /*!< Latched status flag for hold detector One-Shot event */ } _PWM_HDFLG_bits; /* Bit field positions: */ #define PWM_HDFLG_INT_Pos 0 /*!< Latched hold detector interrupt status flag */ #define PWM_HDFLG_CBC_Pos 1 /*!< Latched status flag for hold detector Cycle-by-Cycle event */ #define PWM_HDFLG_OST_Pos 2 /*!< Latched status flag for hold detector One-Shot event */ /* Bit field masks: */ #define PWM_HDFLG_INT_Msk 0x00000001UL /*!< Latched hold detector interrupt status flag */ #define PWM_HDFLG_CBC_Msk 0x00000002UL /*!< Latched status flag for hold detector Cycle-by-Cycle event */ #define PWM_HDFLG_OST_Msk 0x00000004UL /*!< Latched status flag for hold detector One-Shot event */ /*-- HDCLR: Register clear HD flag ---------------------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< Clear hold detector interrupt flag */ uint32_t CBC :1; /*!< Clear flag for Cycle-By-Cycle hold detector latch */ uint32_t OST :1; /*!< Clear flag for One-Shot hold detector latch */ } _PWM_HDCLR_bits; /* Bit field positions: */ #define PWM_HDCLR_INT_Pos 0 /*!< Clear hold detector interrupt flag */ #define PWM_HDCLR_CBC_Pos 1 /*!< Clear flag for Cycle-By-Cycle hold detector latch */ #define PWM_HDCLR_OST_Pos 2 /*!< Clear flag for One-Shot hold detector latch */ /* Bit field masks: */ #define PWM_HDCLR_INT_Msk 0x00000001UL /*!< Clear hold detector interrupt flag */ #define PWM_HDCLR_CBC_Msk 0x00000002UL /*!< Clear flag for Cycle-By-Cycle hold detector latch */ #define PWM_HDCLR_OST_Msk 0x00000004UL /*!< Clear flag for One-Shot hold detector latch */ /*-- HDFRC: Hold Detector Force Register ---------------------------------------------------------------------*/ typedef struct { uint32_t :1; /*!< RESERVED */ uint32_t CBC :1; /*!< Force a Cycle-by-Cycle hold detector event via software */ uint32_t OST :1; /*!< Force a One-Shot hold detector event via software */ } _PWM_HDFRC_bits; /* Bit field positions: */ #define PWM_HDFRC_CBC_Pos 1 /*!< Force a Cycle-by-Cycle hold detector event via software */ #define PWM_HDFRC_OST_Pos 2 /*!< Force a One-Shot hold detector event via software */ /* Bit field masks: */ #define PWM_HDFRC_CBC_Msk 0x00000002UL /*!< Force a Cycle-by-Cycle hold detector event via software */ #define PWM_HDFRC_OST_Msk 0x00000004UL /*!< Force a One-Shot hold detector event via software */ /*-- HDINTCLR: Hold Detector Interrupt pending Clear Register ------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< Clear HD interrupt pending */ } _PWM_HDINTCLR_bits; /* Bit field positions: */ #define PWM_HDINTCLR_INT_Pos 0 /*!< Clear HD interrupt pending */ /* Bit field masks: */ #define PWM_HDINTCLR_INT_Msk 0x00000001UL /*!< Clear HD interrupt pending */ /*-- TZINTCLR: Trip-Zone Interrupt pending Clear Register ----------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< Clear TZ interrupt pending */ } _PWM_TZINTCLR_bits; /* Bit field positions: */ #define PWM_TZINTCLR_INT_Pos 0 /*!< Clear TZ interrupt pending */ /* Bit field masks: */ #define PWM_TZINTCLR_INT_Msk 0x00000001UL /*!< Clear TZ interrupt pending */ /*-- INTCLR: PWM Interrupt pending Clear Register ------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< Clear interrupt pending */ } _PWM_INTCLR_bits; /* Bit field positions: */ #define PWM_INTCLR_INT_Pos 0 /*!< Clear interrupt pending */ /* Bit field masks: */ #define PWM_INTCLR_INT_Msk 0x00000001UL /*!< Clear interrupt pending */ typedef struct { union { /*!< Time-Base Control Register */ __IO uint32_t TBCTL; /*!< TBCTL : type used for word access */ __IO _PWM_TBCTL_bits TBCTL_bit; /*!< TBCTL_bit: structure used for bit access */ }; union { /*!< Time-Base Status Register */ __IO uint32_t TBSTS; /*!< TBSTS : type used for word access */ __IO _PWM_TBSTS_bits TBSTS_bit; /*!< TBSTS_bit: structure used for bit access */ }; union { /*!< Time-Base Phase Register */ __IO uint32_t TBPHS; /*!< TBPHS : type used for word access */ __IO _PWM_TBPHS_bits TBPHS_bit; /*!< TBPHS_bit: structure used for bit access */ }; union { /*!< Time-Base Counter Register */ __IO uint32_t TBCTR; /*!< TBCTR : type used for word access */ __IO _PWM_TBCTR_bits TBCTR_bit; /*!< TBCTR_bit: structure used for bit access */ }; union { /*!< Time-Base Period Register */ __IO uint32_t TBPRD; /*!< TBPRD : type used for word access */ __IO _PWM_TBPRD_bits TBPRD_bit; /*!< TBPRD_bit: structure used for bit access */ }; union { /*!< Counter-Compare Control Register */ __IO uint32_t CMPCTL; /*!< CMPCTL : type used for word access */ __IO _PWM_CMPCTL_bits CMPCTL_bit; /*!< CMPCTL_bit: structure used for bit access */ }; union { /*!< Counter-Compare A Register */ __IO uint32_t CMPA; /*!< CMPA : type used for word access */ __IO _PWM_CMPA_bits CMPA_bit; /*!< CMPA_bit: structure used for bit access */ }; union { /*!< Counter-Compare B Register */ __IO uint32_t CMPB; /*!< CMPB : type used for word access */ __IO _PWM_CMPB_bits CMPB_bit; /*!< CMPB_bit: structure used for bit access */ }; union { /*!< Action-Qualifier Output A Control Register */ __IO uint32_t AQCTLA; /*!< AQCTLA : type used for word access */ __IO _PWM_AQCTLA_bits AQCTLA_bit; /*!< AQCTLA_bit: structure used for bit access */ }; union { /*!< Action-Qualifier Output B Control Register */ __IO uint32_t AQCTLB; /*!< AQCTLB : type used for word access */ __IO _PWM_AQCTLB_bits AQCTLB_bit; /*!< AQCTLB_bit: structure used for bit access */ }; union { /*!< Action-Qualifier Software Force Register */ __IO uint32_t AQSFRC; /*!< AQSFRC : type used for word access */ __IO _PWM_AQSFRC_bits AQSFRC_bit; /*!< AQSFRC_bit: structure used for bit access */ }; union { /*!< Action-Qualifier Continuous Software Force Register */ __IO uint32_t AQCSFRC; /*!< AQCSFRC : type used for word access */ __IO _PWM_AQCSFRC_bits AQCSFRC_bit; /*!< AQCSFRC_bit: structure used for bit access */ }; union { /*!< Dead-Band Generator Control Register */ __IO uint32_t DBCTL; /*!< DBCTL : type used for word access */ __IO _PWM_DBCTL_bits DBCTL_bit; /*!< DBCTL_bit: structure used for bit access */ }; union { /*!< Dead-Band Generator Rising Edge Delay Register */ __IO uint32_t DBRED; /*!< DBRED : type used for word access */ __IO _PWM_DBRED_bits DBRED_bit; /*!< DBRED_bit: structure used for bit access */ }; union { /*!< Dead-Band Generator Falling Edge Delay Register */ __IO uint32_t DBFED; /*!< DBFED : type used for word access */ __IO _PWM_DBFED_bits DBFED_bit; /*!< DBFED_bit: structure used for bit access */ }; union { /*!< Trip-Zone Select Register */ __IO uint32_t TZSEL; /*!< TZSEL : type used for word access */ __IO _PWM_TZSEL_bits TZSEL_bit; /*!< TZSEL_bit: structure used for bit access */ }; union { /*!< Trip-Zone Control Register */ __IO uint32_t TZCTL; /*!< TZCTL : type used for word access */ __IO _PWM_TZCTL_bits TZCTL_bit; /*!< TZCTL_bit: structure used for bit access */ }; union { /*!< Trip-Zone Enable Interrupt Register */ __IO uint32_t TZEINT; /*!< TZEINT : type used for word access */ __IO _PWM_TZEINT_bits TZEINT_bit; /*!< TZEINT_bit: structure used for bit access */ }; union { /*!< Trip-Zone Flag Register */ __I uint32_t TZFLG; /*!< TZFLG : type used for word access */ __I _PWM_TZFLG_bits TZFLG_bit; /*!< TZFLG_bit: structure used for bit access */ }; union { /*!< Trip-Zone Clear Register */ __O uint32_t TZCLR; /*!< TZCLR : type used for word access */ __O _PWM_TZCLR_bits TZCLR_bit; /*!< TZCLR_bit: structure used for bit access */ }; union { /*!< Trip-Zone Force Register */ __O uint32_t TZFRC; /*!< TZFRC : type used for word access */ __O _PWM_TZFRC_bits TZFRC_bit; /*!< TZFRC_bit: structure used for bit access */ }; union { /*!< Event-Trigger Selection Register */ __IO uint32_t ETSEL; /*!< ETSEL : type used for word access */ __IO _PWM_ETSEL_bits ETSEL_bit; /*!< ETSEL_bit: structure used for bit access */ }; union { /*!< Event-Trigger Prescale Register */ __IO uint32_t ETPS; /*!< ETPS : type used for word access */ __IO _PWM_ETPS_bits ETPS_bit; /*!< ETPS_bit: structure used for bit access */ }; union { /*!< Event-Trigger Flag Register */ __I uint32_t ETFLG; /*!< ETFLG : type used for word access */ __I _PWM_ETFLG_bits ETFLG_bit; /*!< ETFLG_bit: structure used for bit access */ }; union { /*!< Event-Trigger Clear Register */ __O uint32_t ETCLR; /*!< ETCLR : type used for word access */ __O _PWM_ETCLR_bits ETCLR_bit; /*!< ETCLR_bit: structure used for bit access */ }; union { /*!< Event-Trigger Force Register */ __O uint32_t ETFRC; /*!< ETFRC : type used for word access */ __O _PWM_ETFRC_bits ETFRC_bit; /*!< ETFRC_bit: structure used for bit access */ }; union { /*!< PWM-Chopper Control Register */ __IO uint32_t PCCTL; /*!< PCCTL : type used for word access */ __IO _PWM_PCCTL_bits PCCTL_bit; /*!< PCCTL_bit: structure used for bit access */ }; union { /*!< High-Resolution Control Register */ __IO uint32_t HRCTL; /*!< HRCTL : type used for word access */ __IO _PWM_HRCTL_bits HRCTL_bit; /*!< HRCTL_bit: structure used for bit access */ }; union { /*!< Filter Width select Register */ __IO uint32_t FWDTH; /*!< FWDTH : type used for word access */ __IO _PWM_FWDTH_bits FWDTH_bit; /*!< FWDTH_bit: structure used for bit access */ }; union { /*!< Hold Detector event Select Register 0 */ __IO uint32_t HDSEL0; /*!< HDSEL0 : type used for word access */ __IO _PWM_HDSEL0_bits HDSEL0_bit; /*!< HDSEL0_bit: structure used for bit access */ }; union { /*!< Hold Detector event Select Register 1 */ __IO uint32_t HDSEL1; /*!< HDSEL1 : type used for word access */ __IO _PWM_HDSEL1_bits HDSEL1_bit; /*!< HDSEL1_bit: structure used for bit access */ }; union { /*!< Hold Detector Control register */ __IO uint32_t HDCTL; /*!< HDCTL : type used for word access */ __IO _PWM_HDCTL_bits HDCTL_bit; /*!< HDCTL_bit: structure used for bit access */ }; union { /*!< Hold Detector Enable Interrupt Register */ __IO uint32_t HDEINT; /*!< HDEINT : type used for word access */ __IO _PWM_HDEINT_bits HDEINT_bit; /*!< HDEINT_bit: structure used for bit access */ }; union { /*!< Hold Detector Flag Register */ __I uint32_t HDFLG; /*!< HDFLG : type used for word access */ __I _PWM_HDFLG_bits HDFLG_bit; /*!< HDFLG_bit: structure used for bit access */ }; union { /*!< Register clear HD flag */ __O uint32_t HDCLR; /*!< HDCLR : type used for word access */ __O _PWM_HDCLR_bits HDCLR_bit; /*!< HDCLR_bit: structure used for bit access */ }; union { /*!< Hold Detector Force Register */ __O uint32_t HDFRC; /*!< HDFRC : type used for word access */ __O _PWM_HDFRC_bits HDFRC_bit; /*!< HDFRC_bit: structure used for bit access */ }; union { /*!< Hold Detector Interrupt pending Clear Register */ __O uint32_t HDINTCLR; /*!< HDINTCLR : type used for word access */ __O _PWM_HDINTCLR_bits HDINTCLR_bit; /*!< HDINTCLR_bit: structure used for bit access */ }; union { /*!< Trip-Zone Interrupt pending Clear Register */ __O uint32_t TZINTCLR; /*!< TZINTCLR : type used for word access */ __O _PWM_TZINTCLR_bits TZINTCLR_bit; /*!< TZINTCLR_bit: structure used for bit access */ }; union { /*!< PWM Interrupt pending Clear Register */ __O uint32_t INTCLR; /*!< INTCLR : type used for word access */ __O _PWM_INTCLR_bits INTCLR_bit; /*!< INTCLR_bit: structure used for bit access */ }; } PWM_TypeDef; /******************************************************************************/ /* ETH registers */ /******************************************************************************/ /*-- MAC1: MAC configuration register 1 ----------------------------------------------------------------------*/ typedef struct { uint32_t RXENABLE :1; /*!< Frame reception enable bit */ uint32_t PASSALL :1; /*!< Bit control PASS */ uint32_t RXPAUSE :1; /*!< Enable receiving a pause as part of Frame */ uint32_t TXPAUSE :1; /*!< Enable transmission pauses Frame */ uint32_t LOOPBACK :1; /*!< Bit activate reception of packets transmitted back through MACReceive-interface */ uint32_t :3; /*!< RESERVED */ uint32_t RESETTFUN :1; /*!< Reset bit logic devices packet */ uint32_t RESETTMCS :1; /*!< Reset bit device MAC layer, responsible for managing addresses in information transmission Reset bit device MAC layer, responsible for managing addresses in information transmission */ uint32_t RESETRFUN :1; /*!< Reset bit logic devices receive packets */ uint32_t RESETRMCS :1; /*!< Reset bit device MAC layer, responsible for managing the filtering addresses of packets received */ uint32_t :2; /*!< RESERVED */ uint32_t SIMRESET :1; /*!< Reset bit random number generator transmitting device */ uint32_t SOFTRESET :1; /*!< Reset bit block MAC Ethernet Controller */ } _ETH_MAC1_bits; /* Bit field positions: */ #define ETH_MAC1_RXENABLE_Pos 0 /*!< Frame reception enable bit */ #define ETH_MAC1_PASSALL_Pos 1 /*!< Bit control PASS */ #define ETH_MAC1_RXPAUSE_Pos 2 /*!< Enable receiving a pause as part of Frame */ #define ETH_MAC1_TXPAUSE_Pos 3 /*!< Enable transmission pauses Frame */ #define ETH_MAC1_LOOPBACK_Pos 4 /*!< Bit activate reception of packets transmitted back through MACReceive-interface */ #define ETH_MAC1_RESETTFUN_Pos 8 /*!< Reset bit logic devices packet */ #define ETH_MAC1_RESETTMCS_Pos 9 /*!< Reset bit device MAC layer, responsible for managing addresses in information transmission Reset bit device MAC layer, responsible for managing addresses in information transmission */ #define ETH_MAC1_RESETRFUN_Pos 10 /*!< Reset bit logic devices receive packets */ #define ETH_MAC1_RESETRMCS_Pos 11 /*!< Reset bit device MAC layer, responsible for managing the filtering addresses of packets received */ #define ETH_MAC1_SIMRESET_Pos 14 /*!< Reset bit random number generator transmitting device */ #define ETH_MAC1_SOFTRESET_Pos 15 /*!< Reset bit block MAC Ethernet Controller */ /* Bit field masks: */ #define ETH_MAC1_RXENABLE_Msk 0x00000001UL /*!< Frame reception enable bit */ #define ETH_MAC1_PASSALL_Msk 0x00000002UL /*!< Bit control PASS */ #define ETH_MAC1_RXPAUSE_Msk 0x00000004UL /*!< Enable receiving a pause as part of Frame */ #define ETH_MAC1_TXPAUSE_Msk 0x00000008UL /*!< Enable transmission pauses Frame */ #define ETH_MAC1_LOOPBACK_Msk 0x00000010UL /*!< Bit activate reception of packets transmitted back through MACReceive-interface */ #define ETH_MAC1_RESETTFUN_Msk 0x00000100UL /*!< Reset bit logic devices packet */ #define ETH_MAC1_RESETTMCS_Msk 0x00000200UL /*!< Reset bit device MAC layer, responsible for managing addresses in information transmission Reset bit device MAC layer, responsible for managing addresses in information transmission */ #define ETH_MAC1_RESETRFUN_Msk 0x00000400UL /*!< Reset bit logic devices receive packets */ #define ETH_MAC1_RESETRMCS_Msk 0x00000800UL /*!< Reset bit device MAC layer, responsible for managing the filtering addresses of packets received */ #define ETH_MAC1_SIMRESET_Msk 0x00004000UL /*!< Reset bit random number generator transmitting device */ #define ETH_MAC1_SOFTRESET_Msk 0x00008000UL /*!< Reset bit block MAC Ethernet Controller */ /*-- MAC2: MAC configuration register 2 ----------------------------------------------------------------------*/ typedef struct { uint32_t FULLDUPLEX :1; /*!< Mode Select bit MAC-run operations */ uint32_t LENGTHCHECK :1; /*!< Enable bit komparatsii length Frame */ uint32_t HUGEFRAME :1; /*!< Enable Bit Frame reception and transmission of arbitrary length */ uint32_t DELAYCRC :1; /*!< Enable bit adding a 4-byte CRC */ uint32_t CRCENABLE :1; /*!< Enable bit CRC inserter */ uint32_t PADENABLE :1; /*!< Bit resolution and functioning bits AUTOPAD VLANPAD */ uint32_t VLANPAD :1; /*!< Enable bit short additions Frame */ uint32_t AUTOPAD :1; /*!< Bit enable automatic determination of type Frame */ uint32_t PUREPRE :1; /*!< Bit enable validation preamble */ uint32_t LONGPRE :1; /*!< Select bit preamble length packets received */ uint32_t :2; /*!< RESERVED */ uint32_t NOBACKOFF :1; /*!< Bit parameter setting retransmission in conflict */ uint32_t BPNOBACKOFF :1; /*!< Enable bit retransmission in conflict */ uint32_t EXCESSDEF :1; /*!< Mode Select bit packet processing */ } _ETH_MAC2_bits; /* Bit field positions: */ #define ETH_MAC2_FULLDUPLEX_Pos 0 /*!< Mode Select bit MAC-run operations */ #define ETH_MAC2_LENGTHCHECK_Pos 1 /*!< Enable bit komparatsii length Frame */ #define ETH_MAC2_HUGEFRAME_Pos 2 /*!< Enable Bit Frame reception and transmission of arbitrary length */ #define ETH_MAC2_DELAYCRC_Pos 3 /*!< Enable bit adding a 4-byte CRC */ #define ETH_MAC2_CRCENABLE_Pos 4 /*!< Enable bit CRC inserter */ #define ETH_MAC2_PADENABLE_Pos 5 /*!< Bit resolution and functioning bits AUTOPAD VLANPAD */ #define ETH_MAC2_VLANPAD_Pos 6 /*!< Enable bit short additions Frame */ #define ETH_MAC2_AUTOPAD_Pos 7 /*!< Bit enable automatic determination of type Frame */ #define ETH_MAC2_PUREPRE_Pos 8 /*!< Bit enable validation preamble */ #define ETH_MAC2_LONGPRE_Pos 9 /*!< Select bit preamble length packets received */ #define ETH_MAC2_NOBACKOFF_Pos 12 /*!< Bit parameter setting retransmission in conflict */ #define ETH_MAC2_BPNOBACKOFF_Pos 13 /*!< Enable bit retransmission in conflict */ #define ETH_MAC2_EXCESSDEF_Pos 14 /*!< Mode Select bit packet processing */ /* Bit field masks: */ #define ETH_MAC2_FULLDUPLEX_Msk 0x00000001UL /*!< Mode Select bit MAC-run operations */ #define ETH_MAC2_LENGTHCHECK_Msk 0x00000002UL /*!< Enable bit komparatsii length Frame */ #define ETH_MAC2_HUGEFRAME_Msk 0x00000004UL /*!< Enable Bit Frame reception and transmission of arbitrary length */ #define ETH_MAC2_DELAYCRC_Msk 0x00000008UL /*!< Enable bit adding a 4-byte CRC */ #define ETH_MAC2_CRCENABLE_Msk 0x00000010UL /*!< Enable bit CRC inserter */ #define ETH_MAC2_PADENABLE_Msk 0x00000020UL /*!< Bit resolution and functioning bits AUTOPAD VLANPAD */ #define ETH_MAC2_VLANPAD_Msk 0x00000040UL /*!< Enable bit short additions Frame */ #define ETH_MAC2_AUTOPAD_Msk 0x00000080UL /*!< Bit enable automatic determination of type Frame */ #define ETH_MAC2_PUREPRE_Msk 0x00000100UL /*!< Bit enable validation preamble */ #define ETH_MAC2_LONGPRE_Msk 0x00000200UL /*!< Select bit preamble length packets received */ #define ETH_MAC2_NOBACKOFF_Msk 0x00001000UL /*!< Bit parameter setting retransmission in conflict */ #define ETH_MAC2_BPNOBACKOFF_Msk 0x00002000UL /*!< Enable bit retransmission in conflict */ #define ETH_MAC2_EXCESSDEF_Msk 0x00004000UL /*!< Mode Select bit packet processing */ /*-- IPGT: Back-to-Back Inter-Packet-Gap Register ------------------------------------------------------------*/ typedef struct { uint32_t BTBIPG :7; /*!< Field specifying the minimum time between the end of transmission of the last nibble packet before transmission of the next packet */ } _ETH_IPGT_bits; /* Bit field positions: */ #define ETH_IPGT_BTBIPG_Pos 0 /*!< Field specifying the minimum time between the end of transmission of the last nibble packet before transmission of the next packet */ /* Bit field masks: */ #define ETH_IPGT_BTBIPG_Msk 0x0000007FUL /*!< Field specifying the minimum time between the end of transmission of the last nibble packet before transmission of the next packet */ /*-- IPGR: Register Non-Back-to-Back Inter-Packet-Gap --------------------------------------------------------*/ typedef struct { uint32_t NBTBIPGP2 :7; /*!< Non-back-to-back Inter-Packet-Gap part 2 */ uint32_t :1; /*!< RESERVED */ uint32_t NBTBIPGP1 :7; /*!< Non-back-to-back Inter-Packet-Gap part 1 - option carrier sense */ } _ETH_IPGR_bits; /* Bit field positions: */ #define ETH_IPGR_NBTBIPGP2_Pos 0 /*!< Non-back-to-back Inter-Packet-Gap part 2 */ #define ETH_IPGR_NBTBIPGP1_Pos 8 /*!< Non-back-to-back Inter-Packet-Gap part 1 - option carrier sense */ /* Bit field masks: */ #define ETH_IPGR_NBTBIPGP2_Msk 0x0000007FUL /*!< Non-back-to-back Inter-Packet-Gap part 2 */ #define ETH_IPGR_NBTBIPGP1_Msk 0x00007F00UL /*!< Non-back-to-back Inter-Packet-Gap part 1 - option carrier sense */ /*-- CLRT: Register collision window -------------------------------------------------------------------------*/ typedef struct { uint32_t RETRMAX :4; /*!< */ uint32_t :4; /*!< RESERVED */ uint32_t COLLWIN :6; /*!< */ } _ETH_CLRT_bits; /* Bit field positions: */ #define ETH_CLRT_RETRMAX_Pos 0 /*!< */ #define ETH_CLRT_COLLWIN_Pos 8 /*!< */ /* Bit field masks: */ #define ETH_CLRT_RETRMAX_Msk 0x0000000FUL /*!< */ #define ETH_CLRT_COLLWIN_Msk 0x00003F00UL /*!< */ /*-- MAXF: Register the upper limit size Frame ---------------------------------------------------------------*/ typedef struct { uint32_t MAXFRLEN :16; /*!< Frame maximum length */ } _ETH_MAXF_bits; /* Bit field positions: */ #define ETH_MAXF_MAXFRLEN_Pos 0 /*!< Frame maximum length */ /* Bit field masks: */ #define ETH_MAXF_MAXFRLEN_Msk 0x0000FFFFUL /*!< Frame maximum length */ /*-- SUPP: Register PHY-support interface --------------------------------------------------------------------*/ typedef struct { uint32_t BITMODE :1; /*!< Activated mode 10BASE-T ENDEC */ uint32_t ENBLJABBER :1; /*!< Enable bit of protection against incorrect data transmission mode 10T ENDEC */ uint32_t :1; /*!< RESERVED */ uint32_t RESET10T :1; /*!< Reset bit module, which converts the MII nibble streams into a serial bit stream mode transceiver 10T */ uint32_t LINKFAIL :1; /*!< Bit resolution modeling */ uint32_t NOCIPHER :1; /*!< Select encryption */ uint32_t FORCEQUIET :1; /*!< enable encryption */ uint32_t RESET100X :1; /*!< Reset bit of the module that contains the logic of the encoder / decoder bit characters 4/5 bits */ uint32_t SPEED :1; /*!< Bits set the operating speed simplified MII */ uint32_t :2; /*!< RESERVED */ uint32_t RESETRMII :1; /*!< Reset bit simplified logic MII */ uint32_t PHYMODE :1; /*!< Bit configuration consistent with MI SMII-connected devices */ uint32_t :2; /*!< RESERVED */ uint32_t RESETINT :1; /*!< Reset bit of the physical interface */ } _ETH_SUPP_bits; /* Bit field positions: */ #define ETH_SUPP_BITMODE_Pos 0 /*!< Activated mode 10BASE-T ENDEC */ #define ETH_SUPP_ENBLJABBER_Pos 1 /*!< Enable bit of protection against incorrect data transmission mode 10T ENDEC */ #define ETH_SUPP_RESET10T_Pos 3 /*!< Reset bit module, which converts the MII nibble streams into a serial bit stream mode transceiver 10T */ #define ETH_SUPP_LINKFAIL_Pos 4 /*!< Bit resolution modeling */ #define ETH_SUPP_NOCIPHER_Pos 5 /*!< Select encryption */ #define ETH_SUPP_FORCEQUIET_Pos 6 /*!< enable encryption */ #define ETH_SUPP_RESET100X_Pos 7 /*!< Reset bit of the module that contains the logic of the encoder / decoder bit characters 4/5 bits */ #define ETH_SUPP_SPEED_Pos 8 /*!< Bits set the operating speed simplified MII */ #define ETH_SUPP_RESETRMII_Pos 11 /*!< Reset bit simplified logic MII */ #define ETH_SUPP_PHYMODE_Pos 12 /*!< Bit configuration consistent with MI SMII-connected devices */ #define ETH_SUPP_RESETINT_Pos 15 /*!< Reset bit of the physical interface */ /* Bit field masks: */ #define ETH_SUPP_BITMODE_Msk 0x00000001UL /*!< Activated mode 10BASE-T ENDEC */ #define ETH_SUPP_ENBLJABBER_Msk 0x00000002UL /*!< Enable bit of protection against incorrect data transmission mode 10T ENDEC */ #define ETH_SUPP_RESET10T_Msk 0x00000008UL /*!< Reset bit module, which converts the MII nibble streams into a serial bit stream mode transceiver 10T */ #define ETH_SUPP_LINKFAIL_Msk 0x00000010UL /*!< Bit resolution modeling */ #define ETH_SUPP_NOCIPHER_Msk 0x00000020UL /*!< Select encryption */ #define ETH_SUPP_FORCEQUIET_Msk 0x00000040UL /*!< enable encryption */ #define ETH_SUPP_RESET100X_Msk 0x00000080UL /*!< Reset bit of the module that contains the logic of the encoder / decoder bit characters 4/5 bits */ #define ETH_SUPP_SPEED_Msk 0x00000100UL /*!< Bits set the operating speed simplified MII */ #define ETH_SUPP_RESETRMII_Msk 0x00000800UL /*!< Reset bit simplified logic MII */ #define ETH_SUPP_PHYMODE_Msk 0x00001000UL /*!< Bit configuration consistent with MI SMII-connected devices */ #define ETH_SUPP_RESETINT_Msk 0x00008000UL /*!< Reset bit of the physical interface */ /*-- MCFG: Configuration control register MII ----------------------------------------------------------------*/ typedef struct { uint32_t SCANINC :1; /*!< Reading module addresses all MII PHY */ uint32_t NOPRE :1; /*!< Control bit preamble */ uint32_t CLKSEL :3; /*!< Selection field frequency divider */ uint32_t :10; /*!< RESERVED */ uint32_t RESETMGMT :1; /*!< Reset bit MII management module */ } _ETH_MCFG_bits; /* Bit field positions: */ #define ETH_MCFG_SCANINC_Pos 0 /*!< Reading module addresses all MII PHY */ #define ETH_MCFG_NOPRE_Pos 1 /*!< Control bit preamble */ #define ETH_MCFG_CLKSEL_Pos 2 /*!< Selection field frequency divider */ #define ETH_MCFG_RESETMGMT_Pos 15 /*!< Reset bit MII management module */ /* Bit field masks: */ #define ETH_MCFG_SCANINC_Msk 0x00000001UL /*!< Reading module addresses all MII PHY */ #define ETH_MCFG_NOPRE_Msk 0x00000002UL /*!< Control bit preamble */ #define ETH_MCFG_CLKSEL_Msk 0x0000001CUL /*!< Selection field frequency divider */ #define ETH_MCFG_RESETMGMT_Msk 0x00008000UL /*!< Reset bit MII management module */ /* Bit field enums: */ typedef enum { ETH_MCFG_CLKSEL_Div4 = 0x0UL, /*!< 1/4 divider */ ETH_MCFG_CLKSEL_Div6 = 0x2UL, /*!< 1/6 divider */ ETH_MCFG_CLKSEL_Div8 = 0x3UL, /*!< 1/8 divider */ ETH_MCFG_CLKSEL_Div10 = 0x4UL, /*!< 1/10 divider */ ETH_MCFG_CLKSEL_Div14 = 0x5UL, /*!< 1/14 divider */ ETH_MCFG_CLKSEL_Div20 = 0x6UL, /*!< 1/20 divider */ ETH_MCFG_CLKSEL_Div28 = 0x7UL, /*!< 1/28 divider */ } ETH_MCFG_CLKSEL_Enum; /*-- MCMD: Command register MII ------------------------------------------------------------------------------*/ typedef struct { uint32_t READ :1; /*!< Single execution of read cycles */ uint32_t SCAN :1; /*!< Continuous performance of read cycles */ } _ETH_MCMD_bits; /* Bit field positions: */ #define ETH_MCMD_READ_Pos 0 /*!< Single execution of read cycles */ #define ETH_MCMD_SCAN_Pos 1 /*!< Continuous performance of read cycles */ /* Bit field masks: */ #define ETH_MCMD_READ_Msk 0x00000001UL /*!< Single execution of read cycles */ #define ETH_MCMD_SCAN_Msk 0x00000002UL /*!< Continuous performance of read cycles */ /*-- MADR: MII address register ------------------------------------------------------------------------------*/ typedef struct { uint32_t REGADDR :5; /*!< The 5-bit register address PHY-device */ uint32_t :3; /*!< RESERVED */ uint32_t PHYADDR :5; /*!< The 5-bit address PHY-device */ } _ETH_MADR_bits; /* Bit field positions: */ #define ETH_MADR_REGADDR_Pos 0 /*!< The 5-bit register address PHY-device */ #define ETH_MADR_PHYADDR_Pos 8 /*!< The 5-bit address PHY-device */ /* Bit field masks: */ #define ETH_MADR_REGADDR_Msk 0x0000001FUL /*!< The 5-bit register address PHY-device */ #define ETH_MADR_PHYADDR_Msk 0x00001F00UL /*!< The 5-bit address PHY-device */ /*-- MWTD: Register data written in MII ----------------------------------------------------------------------*/ typedef struct { uint32_t WDATA :16; /*!< Field data */ } _ETH_MWTD_bits; /* Bit field positions: */ #define ETH_MWTD_WDATA_Pos 0 /*!< Field data */ /* Bit field masks: */ #define ETH_MWTD_WDATA_Msk 0x0000FFFFUL /*!< Field data */ /*-- MRDD: Register read data from MII -----------------------------------------------------------------------*/ typedef struct { uint32_t RDATA :16; /*!< After reading the control module of the MII PHY-device */ } _ETH_MRDD_bits; /* Bit field positions: */ #define ETH_MRDD_RDATA_Pos 0 /*!< After reading the control module of the MII PHY-device */ /* Bit field masks: */ #define ETH_MRDD_RDATA_Msk 0x0000FFFFUL /*!< After reading the control module of the MII PHY-device */ /*-- MIND: MII status register flags -------------------------------------------------------------------------*/ typedef struct { uint32_t BUSY :1; /*!< Flag continuing cycle of the read / write control MII */ uint32_t SCAN :1; /*!< Flag ongoing scan operation (continue reading cycles control MII) */ uint32_t NOTVALID :1; /*!< Flag unfinished read cycle MII (inaccessibility of data to be read) */ uint32_t LINKFAIL :1; /*!< Failure flag control MII (PHY device management) */ } _ETH_MIND_bits; /* Bit field positions: */ #define ETH_MIND_BUSY_Pos 0 /*!< Flag continuing cycle of the read / write control MII */ #define ETH_MIND_SCAN_Pos 1 /*!< Flag ongoing scan operation (continue reading cycles control MII) */ #define ETH_MIND_NOTVALID_Pos 2 /*!< Flag unfinished read cycle MII (inaccessibility of data to be read) */ #define ETH_MIND_LINKFAIL_Pos 3 /*!< Failure flag control MII (PHY device management) */ /* Bit field masks: */ #define ETH_MIND_BUSY_Msk 0x00000001UL /*!< Flag continuing cycle of the read / write control MII */ #define ETH_MIND_SCAN_Msk 0x00000002UL /*!< Flag ongoing scan operation (continue reading cycles control MII) */ #define ETH_MIND_NOTVALID_Msk 0x00000004UL /*!< Flag unfinished read cycle MII (inaccessibility of data to be read) */ #define ETH_MIND_LINKFAIL_Msk 0x00000008UL /*!< Failure flag control MII (PHY device management) */ /*-- SMII: MII controller status register --------------------------------------------------------------------*/ typedef struct { uint32_t SPEED :1; /*!< Speed Indicator */ uint32_t DUPLEX :1; /*!< Mode indicator */ uint32_t LINK :1; /*!< Status Indicator LINK */ uint32_t JABBER :1; /*!< Flag of conditions Jabber */ uint32_t CLASH :1; /*!< Flag of the selected mode */ } _ETH_SMII_bits; /* Bit field positions: */ #define ETH_SMII_SPEED_Pos 0 /*!< Speed Indicator */ #define ETH_SMII_DUPLEX_Pos 1 /*!< Mode indicator */ #define ETH_SMII_LINK_Pos 2 /*!< Status Indicator LINK */ #define ETH_SMII_JABBER_Pos 3 /*!< Flag of conditions Jabber */ #define ETH_SMII_CLASH_Pos 4 /*!< Flag of the selected mode */ /* Bit field masks: */ #define ETH_SMII_SPEED_Msk 0x00000001UL /*!< Speed Indicator */ #define ETH_SMII_DUPLEX_Msk 0x00000002UL /*!< Mode indicator */ #define ETH_SMII_LINK_Msk 0x00000004UL /*!< Status Indicator LINK */ #define ETH_SMII_JABBER_Msk 0x00000008UL /*!< Flag of conditions Jabber */ #define ETH_SMII_CLASH_Msk 0x00000010UL /*!< Flag of the selected mode */ /*-- FIFOCFG: MIIFIFO configurate register -------------------------------------------------------------------*/ typedef struct { uint32_t RST :5; /*!< Reset MIIFIFO */ uint32_t :3; /*!< RESERVED */ uint32_t ENREQ :5; /*!< Enable request MIIFIFO */ uint32_t :3; /*!< RESERVED */ uint32_t ENRPLY :5; /*!< Indicate enable MIIFIFO */ } _ETH_FIFOCFG_bits; /* Bit field positions: */ #define ETH_FIFOCFG_RST_Pos 0 /*!< Reset MIIFIFO */ #define ETH_FIFOCFG_ENREQ_Pos 8 /*!< Enable request MIIFIFO */ #define ETH_FIFOCFG_ENRPLY_Pos 16 /*!< Indicate enable MIIFIFO */ /* Bit field masks: */ #define ETH_FIFOCFG_RST_Msk 0x0000001FUL /*!< Reset MIIFIFO */ #define ETH_FIFOCFG_ENREQ_Msk 0x00001F00UL /*!< Enable request MIIFIFO */ #define ETH_FIFOCFG_ENRPLY_Msk 0x001F0000UL /*!< Indicate enable MIIFIFO */ /* Bit field enums: */ typedef enum { ETH_FIFOCFG_ENREQ_Disable = 0x0UL, /*!< disable MIIFIFO requests */ ETH_FIFOCFG_ENREQ_Enable = 0x1FUL, /*!< enable MIIFIFO requests */ } ETH_FIFOCFG_ENREQ_Enum; typedef enum { ETH_FIFOCFG_ENRPLY_Disable = 0x0UL, /*!< disable MIIFIFO modules */ ETH_FIFOCFG_ENRPLY_Enable = 0x1FUL, /*!< enable MIIFIFO modules */ } ETH_FIFOCFG_ENRPLY_Enum; /*-- SA0: Station address register 0 -------------------------------------------------------------------------*/ typedef struct { uint32_t STADDRB2 :8; /*!< 2nd octet of the station address */ uint32_t STADDRB1 :8; /*!< 1st octet of the station address */ } _ETH_SA0_bits; /* Bit field positions: */ #define ETH_SA0_STADDRB2_Pos 0 /*!< 2nd octet of the station address */ #define ETH_SA0_STADDRB1_Pos 8 /*!< 1st octet of the station address */ /* Bit field masks: */ #define ETH_SA0_STADDRB2_Msk 0x000000FFUL /*!< 2nd octet of the station address */ #define ETH_SA0_STADDRB1_Msk 0x0000FF00UL /*!< 1st octet of the station address */ /*-- SA1: Station address register 1 -------------------------------------------------------------------------*/ typedef struct { uint32_t STADDRB4 :8; /*!< 4th octet of the station address */ uint32_t STADDRB3 :8; /*!< The third octet of the station address */ } _ETH_SA1_bits; /* Bit field positions: */ #define ETH_SA1_STADDRB4_Pos 0 /*!< 4th octet of the station address */ #define ETH_SA1_STADDRB3_Pos 8 /*!< The third octet of the station address */ /* Bit field masks: */ #define ETH_SA1_STADDRB4_Msk 0x000000FFUL /*!< 4th octet of the station address */ #define ETH_SA1_STADDRB3_Msk 0x0000FF00UL /*!< The third octet of the station address */ /*-- SA2: Station address register 2 -------------------------------------------------------------------------*/ typedef struct { uint32_t STADDRB6 :8; /*!< 6th octet station */ uint32_t STADDRB5 :8; /*!< 5th octet station */ } _ETH_SA2_bits; /* Bit field positions: */ #define ETH_SA2_STADDRB6_Pos 0 /*!< 6th octet station */ #define ETH_SA2_STADDRB5_Pos 8 /*!< 5th octet station */ /* Bit field masks: */ #define ETH_SA2_STADDRB6_Msk 0x000000FFUL /*!< 6th octet station */ #define ETH_SA2_STADDRB5_Msk 0x0000FF00UL /*!< 5th octet station */ /*-- DMATXCTRL: DMA transmit control register ----------------------------------------------------------------*/ typedef struct { uint32_t TXENABLE :1; /*!< Enable bit DMA device to transmit packets */ } _ETH_DMATXCTRL_bits; /* Bit field positions: */ #define ETH_DMATXCTRL_TXENABLE_Pos 0 /*!< Enable bit DMA device to transmit packets */ /* Bit field masks: */ #define ETH_DMATXCTRL_TXENABLE_Msk 0x00000001UL /*!< Enable bit DMA device to transmit packets */ /*-- DMATXDESCR: Pointer to transmit descriptor register -----------------------------------------------------*/ typedef struct { uint32_t :2; /*!< RESERVED */ uint32_t DADDR :30; /*!< Memory register address field, which will be recorded with the first transeived packet */ } _ETH_DMATXDESCR_bits; /* Bit field positions: */ #define ETH_DMATXDESCR_DADDR_Pos 2 /*!< Memory register address field, which will be recorded with the first transeived packet */ /* Bit field masks: */ #define ETH_DMATXDESCR_DADDR_Msk 0xFFFFFFFCUL /*!< Memory register address field, which will be recorded with the first transeived packet */ /*-- DMATXSTAT: Status transmission register -----------------------------------------------------------------*/ typedef struct { uint32_t TXPKTSENT :1; /*!< Flag successfully transmit one or more packets */ uint32_t TXUNDERRUN :1; /*!< Data Indicator */ uint32_t :1; /*!< RESERVED */ uint32_t BUSERROR :1; /*!< Flag a bus error */ uint32_t :12; /*!< RESERVED */ uint32_t TXPKTCOUNT :8; /*!< 8-bit counter of transmitted packets */ } _ETH_DMATXSTAT_bits; /* Bit field positions: */ #define ETH_DMATXSTAT_TXPKTSENT_Pos 0 /*!< Flag successfully transmit one or more packets */ #define ETH_DMATXSTAT_TXUNDERRUN_Pos 1 /*!< Data Indicator */ #define ETH_DMATXSTAT_BUSERROR_Pos 3 /*!< Flag a bus error */ #define ETH_DMATXSTAT_TXPKTCOUNT_Pos 16 /*!< 8-bit counter of transmitted packets */ /* Bit field masks: */ #define ETH_DMATXSTAT_TXPKTSENT_Msk 0x00000001UL /*!< Flag successfully transmit one or more packets */ #define ETH_DMATXSTAT_TXUNDERRUN_Msk 0x00000002UL /*!< Data Indicator */ #define ETH_DMATXSTAT_BUSERROR_Msk 0x00000008UL /*!< Flag a bus error */ #define ETH_DMATXSTAT_TXPKTCOUNT_Msk 0x00FF0000UL /*!< 8-bit counter of transmitted packets */ /*-- DMARXCTRL: Control receive register ---------------------------------------------------------------------*/ typedef struct { uint32_t RXENABLE :1; /*!< Enable receive */ } _ETH_DMARXCTRL_bits; /* Bit field positions: */ #define ETH_DMARXCTRL_RXENABLE_Pos 0 /*!< Enable receive */ /* Bit field masks: */ #define ETH_DMARXCTRL_RXENABLE_Msk 0x00000001UL /*!< Enable receive */ /*-- DMARXDESCR: Pointer receive descriptor register ---------------------------------------------------------*/ typedef struct { uint32_t :2; /*!< RESERVED */ uint32_t DADDR :30; /*!< Memory register address field, which will be recorded with the first received packet */ } _ETH_DMARXDESCR_bits; /* Bit field positions: */ #define ETH_DMARXDESCR_DADDR_Pos 2 /*!< Memory register address field, which will be recorded with the first received packet */ /* Bit field masks: */ #define ETH_DMARXDESCR_DADDR_Msk 0xFFFFFFFCUL /*!< Memory register address field, which will be recorded with the first received packet */ /*-- DMARXSTAT: Status receiving register --------------------------------------------------------------------*/ typedef struct { uint32_t RXPKTREC :1; /*!< Flag successfully receive one or more packets */ uint32_t :1; /*!< RESERVED */ uint32_t RXOVERFLOW :1; /*!< Data Indicator */ uint32_t BUSERROR :1; /*!< Flag a bus error */ uint32_t :12; /*!< RESERVED */ uint32_t RXPKTCOUNT :8; /*!< 8-bit counter of received packets */ } _ETH_DMARXSTAT_bits; /* Bit field positions: */ #define ETH_DMARXSTAT_RXPKTREC_Pos 0 /*!< Flag successfully receive one or more packets */ #define ETH_DMARXSTAT_RXOVERFLOW_Pos 2 /*!< Data Indicator */ #define ETH_DMARXSTAT_BUSERROR_Pos 3 /*!< Flag a bus error */ #define ETH_DMARXSTAT_RXPKTCOUNT_Pos 16 /*!< 8-bit counter of received packets */ /* Bit field masks: */ #define ETH_DMARXSTAT_RXPKTREC_Msk 0x00000001UL /*!< Flag successfully receive one or more packets */ #define ETH_DMARXSTAT_RXOVERFLOW_Msk 0x00000004UL /*!< Data Indicator */ #define ETH_DMARXSTAT_BUSERROR_Msk 0x00000008UL /*!< Flag a bus error */ #define ETH_DMARXSTAT_RXPKTCOUNT_Msk 0x00FF0000UL /*!< 8-bit counter of received packets */ /*-- DMAINTMASK: Mask interrupt register ---------------------------------------------------------------------*/ typedef struct { uint32_t TXPKTSENT :1; /*!< */ uint32_t TXUNDERRUN :1; /*!< */ uint32_t :1; /*!< RESERVED */ uint32_t BUSERRTX :1; /*!< */ uint32_t RXPKTREC :1; /*!< */ uint32_t :1; /*!< RESERVED */ uint32_t RXOVER :1; /*!< */ uint32_t BUSERRRX :1; /*!< */ } _ETH_DMAINTMASK_bits; /* Bit field positions: */ #define ETH_DMAINTMASK_TXPKTSENT_Pos 0 /*!< */ #define ETH_DMAINTMASK_TXUNDERRUN_Pos 1 /*!< */ #define ETH_DMAINTMASK_BUSERRTX_Pos 3 /*!< */ #define ETH_DMAINTMASK_RXPKTREC_Pos 4 /*!< */ #define ETH_DMAINTMASK_RXOVER_Pos 6 /*!< */ #define ETH_DMAINTMASK_BUSERRRX_Pos 7 /*!< */ /* Bit field masks: */ #define ETH_DMAINTMASK_TXPKTSENT_Msk 0x00000001UL /*!< */ #define ETH_DMAINTMASK_TXUNDERRUN_Msk 0x00000002UL /*!< */ #define ETH_DMAINTMASK_BUSERRTX_Msk 0x00000008UL /*!< */ #define ETH_DMAINTMASK_RXPKTREC_Msk 0x00000010UL /*!< */ #define ETH_DMAINTMASK_RXOVER_Msk 0x00000040UL /*!< */ #define ETH_DMAINTMASK_BUSERRRX_Msk 0x00000080UL /*!< */ /*-- DMAINT: Interrupt register ------------------------------------------------------------------------------*/ typedef struct { uint32_t TXPKTSENT :1; /*!< */ uint32_t TXUNDERRUN :1; /*!< */ uint32_t :1; /*!< RESERVED */ uint32_t BUSERRTX :1; /*!< */ uint32_t RXPKTREC :1; /*!< */ uint32_t :1; /*!< RESERVED */ uint32_t RXOVER :1; /*!< */ uint32_t BUSERRRX :1; /*!< */ } _ETH_DMAINT_bits; /* Bit field positions: */ #define ETH_DMAINT_TXPKTSENT_Pos 0 /*!< */ #define ETH_DMAINT_TXUNDERRUN_Pos 1 /*!< */ #define ETH_DMAINT_BUSERRTX_Pos 3 /*!< */ #define ETH_DMAINT_RXPKTREC_Pos 4 /*!< */ #define ETH_DMAINT_RXOVER_Pos 6 /*!< */ #define ETH_DMAINT_BUSERRRX_Pos 7 /*!< */ /* Bit field masks: */ #define ETH_DMAINT_TXPKTSENT_Msk 0x00000001UL /*!< */ #define ETH_DMAINT_TXUNDERRUN_Msk 0x00000002UL /*!< */ #define ETH_DMAINT_BUSERRTX_Msk 0x00000008UL /*!< */ #define ETH_DMAINT_RXPKTREC_Msk 0x00000010UL /*!< */ #define ETH_DMAINT_RXOVER_Msk 0x00000040UL /*!< */ #define ETH_DMAINT_BUSERRRX_Msk 0x00000080UL /*!< */ typedef struct { union { /*!< MAC configuration register 1 */ __IO uint32_t MAC1; /*!< MAC1 : type used for word access */ __IO _ETH_MAC1_bits MAC1_bit; /*!< MAC1_bit: structure used for bit access */ }; union { /*!< MAC configuration register 2 */ __IO uint32_t MAC2; /*!< MAC2 : type used for word access */ __IO _ETH_MAC2_bits MAC2_bit; /*!< MAC2_bit: structure used for bit access */ }; union { /*!< Back-to-Back Inter-Packet-Gap Register */ __IO uint32_t IPGT; /*!< IPGT : type used for word access */ __IO _ETH_IPGT_bits IPGT_bit; /*!< IPGT_bit: structure used for bit access */ }; union { /*!< Register Non-Back-to-Back Inter-Packet-Gap */ __IO uint32_t IPGR; /*!< IPGR : type used for word access */ __IO _ETH_IPGR_bits IPGR_bit; /*!< IPGR_bit: structure used for bit access */ }; union { /*!< Register collision window */ __IO uint32_t CLRT; /*!< CLRT : type used for word access */ __IO _ETH_CLRT_bits CLRT_bit; /*!< CLRT_bit: structure used for bit access */ }; union { /*!< Register the upper limit size Frame */ __IO uint32_t MAXF; /*!< MAXF : type used for word access */ __IO _ETH_MAXF_bits MAXF_bit; /*!< MAXF_bit: structure used for bit access */ }; union { /*!< Register PHY-support interface */ __IO uint32_t SUPP; /*!< SUPP : type used for word access */ __IO _ETH_SUPP_bits SUPP_bit; /*!< SUPP_bit: structure used for bit access */ }; __IO uint32_t Reserved0; union { /*!< Configuration control register MII */ __IO uint32_t MCFG; /*!< MCFG : type used for word access */ __IO _ETH_MCFG_bits MCFG_bit; /*!< MCFG_bit: structure used for bit access */ }; union { /*!< Command register MII */ __IO uint32_t MCMD; /*!< MCMD : type used for word access */ __IO _ETH_MCMD_bits MCMD_bit; /*!< MCMD_bit: structure used for bit access */ }; union { /*!< MII address register */ __IO uint32_t MADR; /*!< MADR : type used for word access */ __IO _ETH_MADR_bits MADR_bit; /*!< MADR_bit: structure used for bit access */ }; union { /*!< Register data written in MII */ __O uint32_t MWTD; /*!< MWTD : type used for word access */ __O _ETH_MWTD_bits MWTD_bit; /*!< MWTD_bit: structure used for bit access */ }; union { /*!< Register read data from MII */ __I uint32_t MRDD; /*!< MRDD : type used for word access */ __I _ETH_MRDD_bits MRDD_bit; /*!< MRDD_bit: structure used for bit access */ }; union { /*!< MII status register flags */ __I uint32_t MIND; /*!< MIND : type used for word access */ __I _ETH_MIND_bits MIND_bit; /*!< MIND_bit: structure used for bit access */ }; union { /*!< MII controller status register */ __I uint32_t SMII; /*!< SMII : type used for word access */ __I _ETH_SMII_bits SMII_bit; /*!< SMII_bit: structure used for bit access */ }; union { /*!< MIIFIFO configurate register */ __IO uint32_t FIFOCFG; /*!< FIFOCFG : type used for word access */ __IO _ETH_FIFOCFG_bits FIFOCFG_bit; /*!< FIFOCFG_bit: structure used for bit access */ }; union { /*!< Station address register 0 */ __IO uint32_t SA0; /*!< SA0 : type used for word access */ __IO _ETH_SA0_bits SA0_bit; /*!< SA0_bit: structure used for bit access */ }; union { /*!< Station address register 1 */ __IO uint32_t SA1; /*!< SA1 : type used for word access */ __IO _ETH_SA1_bits SA1_bit; /*!< SA1_bit: structure used for bit access */ }; union { /*!< Station address register 2 */ __IO uint32_t SA2; /*!< SA2 : type used for word access */ __IO _ETH_SA2_bits SA2_bit; /*!< SA2_bit: structure used for bit access */ }; __IO uint32_t Reserved1[77]; union { /*!< DMA transmit control register */ __IO uint32_t DMATXCTRL; /*!< DMATXCTRL : type used for word access */ __IO _ETH_DMATXCTRL_bits DMATXCTRL_bit; /*!< DMATXCTRL_bit: structure used for bit access */ }; union { /*!< Pointer to transmit descriptor register */ __IO uint32_t DMATXDESCR; /*!< DMATXDESCR : type used for word access */ __IO _ETH_DMATXDESCR_bits DMATXDESCR_bit; /*!< DMATXDESCR_bit: structure used for bit access */ }; union { /*!< Status transmission register */ __IO uint32_t DMATXSTAT; /*!< DMATXSTAT : type used for word access */ __IO _ETH_DMATXSTAT_bits DMATXSTAT_bit; /*!< DMATXSTAT_bit: structure used for bit access */ }; union { /*!< Control receive register */ __IO uint32_t DMARXCTRL; /*!< DMARXCTRL : type used for word access */ __IO _ETH_DMARXCTRL_bits DMARXCTRL_bit; /*!< DMARXCTRL_bit: structure used for bit access */ }; union { /*!< Pointer receive descriptor register */ __IO uint32_t DMARXDESCR; /*!< DMARXDESCR : type used for word access */ __IO _ETH_DMARXDESCR_bits DMARXDESCR_bit; /*!< DMARXDESCR_bit: structure used for bit access */ }; union { /*!< Status receiving register */ __IO uint32_t DMARXSTAT; /*!< DMARXSTAT : type used for word access */ __IO _ETH_DMARXSTAT_bits DMARXSTAT_bit; /*!< DMARXSTAT_bit: structure used for bit access */ }; union { /*!< Mask interrupt register */ __IO uint32_t DMAINTMASK; /*!< DMAINTMASK : type used for word access */ __IO _ETH_DMAINTMASK_bits DMAINTMASK_bit; /*!< DMAINTMASK_bit: structure used for bit access */ }; union { /*!< Interrupt register */ __I uint32_t DMAINT; /*!< DMAINT : type used for word access */ __I _ETH_DMAINT_bits DMAINT_bit; /*!< DMAINT_bit: structure used for bit access */ }; } ETH_TypeDef; /******************************************************************************/ /* SPI registers */ /******************************************************************************/ /*-- CR0: Control register 0 ---------------------------------------------------------------------------------*/ typedef struct { uint32_t DSS :4; /*!< Size of data */ uint32_t FRF :2; /*!< Select protocol */ uint32_t SPO :1; /*!< Polarity SSPCLKOUT */ uint32_t SPH :1; /*!< Phase SSPCLKOUT */ uint32_t SCR :8; /*!< Value divider */ } _SPI_CR0_bits; /* Bit field positions: */ #define SPI_CR0_DSS_Pos 0 /*!< Size of data */ #define SPI_CR0_FRF_Pos 4 /*!< Select protocol */ #define SPI_CR0_SPO_Pos 6 /*!< Polarity SSPCLKOUT */ #define SPI_CR0_SPH_Pos 7 /*!< Phase SSPCLKOUT */ #define SPI_CR0_SCR_Pos 8 /*!< Value divider */ /* Bit field masks: */ #define SPI_CR0_DSS_Msk 0x0000000FUL /*!< Size of data */ #define SPI_CR0_FRF_Msk 0x00000030UL /*!< Select protocol */ #define SPI_CR0_SPO_Msk 0x00000040UL /*!< Polarity SSPCLKOUT */ #define SPI_CR0_SPH_Msk 0x00000080UL /*!< Phase SSPCLKOUT */ #define SPI_CR0_SCR_Msk 0x0000FF00UL /*!< Value divider */ /* Bit field enums: */ typedef enum { SPI_CR0_DSS_4bit = 0x3UL, /*!< data size 4 bit */ SPI_CR0_DSS_5bit = 0x4UL, /*!< data size 5 bit */ SPI_CR0_DSS_6bit = 0x5UL, /*!< data size 6 bit */ SPI_CR0_DSS_7bit = 0x6UL, /*!< data size 7 bit */ SPI_CR0_DSS_8bit = 0x7UL, /*!< data size 8 bit */ SPI_CR0_DSS_9bit = 0x8UL, /*!< data size 9 bit */ SPI_CR0_DSS_10bit = 0x9UL, /*!< data size 10 bit */ SPI_CR0_DSS_11bit = 0xAUL, /*!< data size 11 bit */ SPI_CR0_DSS_12bit = 0xBUL, /*!< data size 12 bit */ SPI_CR0_DSS_13bit = 0xCUL, /*!< data size 13 bit */ SPI_CR0_DSS_14bit = 0xDUL, /*!< data size 14 bit */ SPI_CR0_DSS_15bit = 0xEUL, /*!< data size 15 bit */ SPI_CR0_DSS_16bit = 0xFUL, /*!< data size 16 bit */ } SPI_CR0_DSS_Enum; typedef enum { SPI_CR0_FRF_SPI = 0x0UL, /*!< SPI of Motorola */ SPI_CR0_FRF_SSI = 0x1UL, /*!< SSI of Texas Instruments */ SPI_CR0_FRF_Microwire = 0x2UL, /*!< Microwire of National Semiconductor */ } SPI_CR0_FRF_Enum; /*-- CR1: Control register 1 ---------------------------------------------------------------------------------*/ typedef struct { uint32_t :1; /*!< RESERVED */ uint32_t SSE :1; /*!< Enable transceiver */ uint32_t MS :1; /*!< Select mode */ uint32_t SOD :1; /*!< Disable bit data */ uint32_t :4; /*!< RESERVED */ uint32_t RXIFLSEL :4; /*!< Receive interrupt FIFO level select */ uint32_t TXIFLSEL :4; /*!< Transmit interrupt FIFO level select */ } _SPI_CR1_bits; /* Bit field positions: */ #define SPI_CR1_SSE_Pos 1 /*!< Enable transceiver */ #define SPI_CR1_MS_Pos 2 /*!< Select mode */ #define SPI_CR1_SOD_Pos 3 /*!< Disable bit data */ #define SPI_CR1_RXIFLSEL_Pos 8 /*!< Receive interrupt FIFO level select */ #define SPI_CR1_TXIFLSEL_Pos 12 /*!< Transmit interrupt FIFO level select */ /* Bit field masks: */ #define SPI_CR1_SSE_Msk 0x00000002UL /*!< Enable transceiver */ #define SPI_CR1_MS_Msk 0x00000004UL /*!< Select mode */ #define SPI_CR1_SOD_Msk 0x00000008UL /*!< Disable bit data */ #define SPI_CR1_RXIFLSEL_Msk 0x00000F00UL /*!< Receive interrupt FIFO level select */ #define SPI_CR1_TXIFLSEL_Msk 0x0000F000UL /*!< Transmit interrupt FIFO level select */ /*-- DR: Data register ---------------------------------------------------------------------------------------*/ typedef struct { uint32_t DATA :16; /*!< */ } _SPI_DR_bits; /* Bit field positions: */ #define SPI_DR_DATA_Pos 0 /*!< */ /* Bit field masks: */ #define SPI_DR_DATA_Msk 0x0000FFFFUL /*!< */ /*-- SR: State register --------------------------------------------------------------------------------------*/ typedef struct { uint32_t TFE :1; /*!< FIFO buffer empty flag transmitter */ uint32_t TNF :1; /*!< Indicator the transmitter FIFO buffer is not full */ uint32_t RNE :1; /*!< Indicate not empty receive buffer */ uint32_t RFF :1; /*!< Indicate full receive buffer */ uint32_t BSY :1; /*!< Activity flag */ } _SPI_SR_bits; /* Bit field positions: */ #define SPI_SR_TFE_Pos 0 /*!< FIFO buffer empty flag transmitter */ #define SPI_SR_TNF_Pos 1 /*!< Indicator the transmitter FIFO buffer is not full */ #define SPI_SR_RNE_Pos 2 /*!< Indicate not empty receive buffer */ #define SPI_SR_RFF_Pos 3 /*!< Indicate full receive buffer */ #define SPI_SR_BSY_Pos 4 /*!< Activity flag */ /* Bit field masks: */ #define SPI_SR_TFE_Msk 0x00000001UL /*!< FIFO buffer empty flag transmitter */ #define SPI_SR_TNF_Msk 0x00000002UL /*!< Indicator the transmitter FIFO buffer is not full */ #define SPI_SR_RNE_Msk 0x00000004UL /*!< Indicate not empty receive buffer */ #define SPI_SR_RFF_Msk 0x00000008UL /*!< Indicate full receive buffer */ #define SPI_SR_BSY_Msk 0x00000010UL /*!< Activity flag */ /*-- CPSR: Clock division factor register --------------------------------------------------------------------*/ typedef struct { uint32_t CPSDVSR :8; /*!< Clock division factor. Bit0 always 0 */ } _SPI_CPSR_bits; /* Bit field positions: */ #define SPI_CPSR_CPSDVSR_Pos 0 /*!< Clock division factor. Bit0 always 0 */ /* Bit field masks: */ #define SPI_CPSR_CPSDVSR_Msk 0x000000FFUL /*!< Clock division factor. Bit0 always 0 */ /*-- IMSC: Mask interrupt register ---------------------------------------------------------------------------*/ typedef struct { uint32_t RORIM :1; /*!< Interrupt mask bit SSPRORINTR buffer overflow receiver */ uint32_t RTIM :1; /*!< Interrupt mask bit SSPRTINTR timeout receiver */ uint32_t RXIM :1; /*!< SSPRXINTR interrupt mask bit to fill 50% or less of the receiver FIFO buffer */ uint32_t TXIM :1; /*!< SSPTXINTR interrupt mask bit to fill 50% or less of the FIFO buffer of the transmitter */ } _SPI_IMSC_bits; /* Bit field positions: */ #define SPI_IMSC_RORIM_Pos 0 /*!< Interrupt mask bit SSPRORINTR buffer overflow receiver */ #define SPI_IMSC_RTIM_Pos 1 /*!< Interrupt mask bit SSPRTINTR timeout receiver */ #define SPI_IMSC_RXIM_Pos 2 /*!< SSPRXINTR interrupt mask bit to fill 50% or less of the receiver FIFO buffer */ #define SPI_IMSC_TXIM_Pos 3 /*!< SSPTXINTR interrupt mask bit to fill 50% or less of the FIFO buffer of the transmitter */ /* Bit field masks: */ #define SPI_IMSC_RORIM_Msk 0x00000001UL /*!< Interrupt mask bit SSPRORINTR buffer overflow receiver */ #define SPI_IMSC_RTIM_Msk 0x00000002UL /*!< Interrupt mask bit SSPRTINTR timeout receiver */ #define SPI_IMSC_RXIM_Msk 0x00000004UL /*!< SSPRXINTR interrupt mask bit to fill 50% or less of the receiver FIFO buffer */ #define SPI_IMSC_TXIM_Msk 0x00000008UL /*!< SSPTXINTR interrupt mask bit to fill 50% or less of the FIFO buffer of the transmitter */ /*-- RIS: Status register interrupt without mask -------------------------------------------------------------*/ typedef struct { uint32_t RORRIS :1; /*!< Interrupt status before masking SSPRORINTR */ uint32_t RTRIS :1; /*!< Interrupt status before masking SSPRTINTR */ uint32_t RXRIS :1; /*!< Interrupt status before masking SSPRXINTR */ uint32_t TXRIS :1; /*!< Interrupt status before masking SSPTXINTR */ } _SPI_RIS_bits; /* Bit field positions: */ #define SPI_RIS_RORRIS_Pos 0 /*!< Interrupt status before masking SSPRORINTR */ #define SPI_RIS_RTRIS_Pos 1 /*!< Interrupt status before masking SSPRTINTR */ #define SPI_RIS_RXRIS_Pos 2 /*!< Interrupt status before masking SSPRXINTR */ #define SPI_RIS_TXRIS_Pos 3 /*!< Interrupt status before masking SSPTXINTR */ /* Bit field masks: */ #define SPI_RIS_RORRIS_Msk 0x00000001UL /*!< Interrupt status before masking SSPRORINTR */ #define SPI_RIS_RTRIS_Msk 0x00000002UL /*!< Interrupt status before masking SSPRTINTR */ #define SPI_RIS_RXRIS_Msk 0x00000004UL /*!< Interrupt status before masking SSPRXINTR */ #define SPI_RIS_TXRIS_Msk 0x00000008UL /*!< Interrupt status before masking SSPTXINTR */ /*-- MIS: Status register interrupt masking account ----------------------------------------------------------*/ typedef struct { uint32_t RORMIS :1; /*!< Masked interrupt status SSPRORINTR */ uint32_t RTMIS :1; /*!< Masked interrupt status SSPRTINTR */ uint32_t RXMIS :1; /*!< Masked interrupt status SSPRXINTR */ uint32_t TXMIS :1; /*!< Masked interrupt status SSPTXINTR */ } _SPI_MIS_bits; /* Bit field positions: */ #define SPI_MIS_RORMIS_Pos 0 /*!< Masked interrupt status SSPRORINTR */ #define SPI_MIS_RTMIS_Pos 1 /*!< Masked interrupt status SSPRTINTR */ #define SPI_MIS_RXMIS_Pos 2 /*!< Masked interrupt status SSPRXINTR */ #define SPI_MIS_TXMIS_Pos 3 /*!< Masked interrupt status SSPTXINTR */ /* Bit field masks: */ #define SPI_MIS_RORMIS_Msk 0x00000001UL /*!< Masked interrupt status SSPRORINTR */ #define SPI_MIS_RTMIS_Msk 0x00000002UL /*!< Masked interrupt status SSPRTINTR */ #define SPI_MIS_RXMIS_Msk 0x00000004UL /*!< Masked interrupt status SSPRXINTR */ #define SPI_MIS_TXMIS_Msk 0x00000008UL /*!< Masked interrupt status SSPTXINTR */ /*-- ICR: Register reset interrupt ---------------------------------------------------------------------------*/ typedef struct { uint32_t RORIC :1; /*!< Reset interrupt SSPRORINTR */ uint32_t RTIC :1; /*!< Reset interrupt SSPRTINTR */ } _SPI_ICR_bits; /* Bit field positions: */ #define SPI_ICR_RORIC_Pos 0 /*!< Reset interrupt SSPRORINTR */ #define SPI_ICR_RTIC_Pos 1 /*!< Reset interrupt SSPRTINTR */ /* Bit field masks: */ #define SPI_ICR_RORIC_Msk 0x00000001UL /*!< Reset interrupt SSPRORINTR */ #define SPI_ICR_RTIC_Msk 0x00000002UL /*!< Reset interrupt SSPRTINTR */ /*-- DMACR: Control register DMA -----------------------------------------------------------------------------*/ typedef struct { uint32_t RXDMAE :1; /*!< DMA enable bit at reception */ uint32_t TXDMAE :1; /*!< DMA enable bit transmission */ } _SPI_DMACR_bits; /* Bit field positions: */ #define SPI_DMACR_RXDMAE_Pos 0 /*!< DMA enable bit at reception */ #define SPI_DMACR_TXDMAE_Pos 1 /*!< DMA enable bit transmission */ /* Bit field masks: */ #define SPI_DMACR_RXDMAE_Msk 0x00000001UL /*!< DMA enable bit at reception */ #define SPI_DMACR_TXDMAE_Msk 0x00000002UL /*!< DMA enable bit transmission */ typedef struct { union { /*!< Control register 0 */ __IO uint32_t CR0; /*!< CR0 : type used for word access */ __IO _SPI_CR0_bits CR0_bit; /*!< CR0_bit: structure used for bit access */ }; union { /*!< Control register 1 */ __IO uint32_t CR1; /*!< CR1 : type used for word access */ __IO _SPI_CR1_bits CR1_bit; /*!< CR1_bit: structure used for bit access */ }; union { /*!< Data register */ __IO uint32_t DR; /*!< DR : type used for word access */ __IO _SPI_DR_bits DR_bit; /*!< DR_bit: structure used for bit access */ }; union { /*!< State register */ __I uint32_t SR; /*!< SR : type used for word access */ __I _SPI_SR_bits SR_bit; /*!< SR_bit: structure used for bit access */ }; union { /*!< Clock division factor register */ __IO uint32_t CPSR; /*!< CPSR : type used for word access */ __IO _SPI_CPSR_bits CPSR_bit; /*!< CPSR_bit: structure used for bit access */ }; union { /*!< Mask interrupt register */ __IO uint32_t IMSC; /*!< IMSC : type used for word access */ __IO _SPI_IMSC_bits IMSC_bit; /*!< IMSC_bit: structure used for bit access */ }; union { /*!< Status register interrupt without mask */ __I uint32_t RIS; /*!< RIS : type used for word access */ __I _SPI_RIS_bits RIS_bit; /*!< RIS_bit: structure used for bit access */ }; union { /*!< Status register interrupt masking account */ __I uint32_t MIS; /*!< MIS : type used for word access */ __I _SPI_MIS_bits MIS_bit; /*!< MIS_bit: structure used for bit access */ }; union { /*!< Register reset interrupt */ __O uint32_t ICR; /*!< ICR : type used for word access */ __O _SPI_ICR_bits ICR_bit; /*!< ICR_bit: structure used for bit access */ }; union { /*!< Control register DMA */ __IO uint32_t DMACR; /*!< DMACR : type used for word access */ __IO _SPI_DMACR_bits DMACR_bit; /*!< DMACR_bit: structure used for bit access */ }; } SPI_TypeDef; /******************************************************************************/ /* CAN registers */ /******************************************************************************/ /*-- CLC: Frequency control register -------------------------------------------------------------------------*/ typedef struct { uint32_t DISR :1; /*!< OFF module CAN */ uint32_t DISS :1; /*!< State CAN */ } _CAN_CLC_bits; /* Bit field positions: */ #define CAN_CLC_DISR_Pos 0 /*!< OFF module CAN */ #define CAN_CLC_DISS_Pos 1 /*!< State CAN */ /* Bit field masks: */ #define CAN_CLC_DISR_Msk 0x00000001UL /*!< OFF module CAN */ #define CAN_CLC_DISS_Msk 0x00000002UL /*!< State CAN */ /*-- ID: Identity register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t MODREV :8; /*!< Number of modifications of the CAN */ uint32_t MODTYPE :8; /*!< Digit capacity CAN */ uint32_t MODNUM :16; /*!< Identification number CAN */ } _CAN_ID_bits; /* Bit field positions: */ #define CAN_ID_MODREV_Pos 0 /*!< Number of modifications of the CAN */ #define CAN_ID_MODTYPE_Pos 8 /*!< Digit capacity CAN */ #define CAN_ID_MODNUM_Pos 16 /*!< Identification number CAN */ /* Bit field masks: */ #define CAN_ID_MODREV_Msk 0x000000FFUL /*!< Number of modifications of the CAN */ #define CAN_ID_MODTYPE_Msk 0x0000FF00UL /*!< Digit capacity CAN */ #define CAN_ID_MODNUM_Msk 0xFFFF0000UL /*!< Identification number CAN */ /*-- FDR: Register divider -----------------------------------------------------------------------------------*/ typedef struct { uint32_t STEP :10; /*!< Step divider */ uint32_t :1; /*!< RESERVED */ uint32_t SM :1; /*!< Select the transition mode Suspend */ uint32_t SC :2; /*!< Configuration of the frequency divider in mode Suspend */ uint32_t DM :2; /*!< Mode setting of the frequency divider */ uint32_t RESULT :10; /*!< Count frequency divider */ uint32_t :4; /*!< RESERVED */ uint32_t ENHW :1; /*!< Control bit synchronization */ uint32_t DISCLK :1; /*!< Disable bit internal clock */ } _CAN_FDR_bits; /* Bit field positions: */ #define CAN_FDR_STEP_Pos 0 /*!< Step divider */ #define CAN_FDR_SM_Pos 11 /*!< Select the transition mode Suspend */ #define CAN_FDR_SC_Pos 12 /*!< Configuration of the frequency divider in mode Suspend */ #define CAN_FDR_DM_Pos 14 /*!< Mode setting of the frequency divider */ #define CAN_FDR_RESULT_Pos 16 /*!< Count frequency divider */ #define CAN_FDR_ENHW_Pos 30 /*!< Control bit synchronization */ #define CAN_FDR_DISCLK_Pos 31 /*!< Disable bit internal clock */ /* Bit field masks: */ #define CAN_FDR_STEP_Msk 0x000003FFUL /*!< Step divider */ #define CAN_FDR_SM_Msk 0x00000800UL /*!< Select the transition mode Suspend */ #define CAN_FDR_SC_Msk 0x00003000UL /*!< Configuration of the frequency divider in mode Suspend */ #define CAN_FDR_DM_Msk 0x0000C000UL /*!< Mode setting of the frequency divider */ #define CAN_FDR_RESULT_Msk 0x03FF0000UL /*!< Count frequency divider */ #define CAN_FDR_ENHW_Msk 0x40000000UL /*!< Control bit synchronization */ #define CAN_FDR_DISCLK_Msk 0x80000000UL /*!< Disable bit internal clock */ /* Bit field enums: */ typedef enum { CAN_FDR_DM_Disable = 0x0UL, /*!< counter disabled */ CAN_FDR_DM_NormalMode = 0x1UL, /*!< normal operation mode */ CAN_FDR_DM_DividerMode = 0x2UL, /*!< divider operation mode */ } CAN_FDR_DM_Enum; /*-- LIST: LIST: Register list0 -------------------------------------------------------------------------------*/ typedef struct { uint32_t BEGIN :8; /*!< Number of the first message object */ uint32_t END :8; /*!< Number of the last message object */ uint32_t SIZE :8; /*!< List size */ uint32_t EMPTY :1; /*!< Indicate empty list */ } _CAN_LIST_LIST_bits; /* Bit field positions: */ #define CAN_LIST_LIST_BEGIN_Pos 0 /*!< Number of the first message object */ #define CAN_LIST_LIST_END_Pos 8 /*!< Number of the last message object */ #define CAN_LIST_LIST_SIZE_Pos 16 /*!< List size */ #define CAN_LIST_LIST_EMPTY_Pos 24 /*!< Indicate empty list */ /* Bit field masks: */ #define CAN_LIST_LIST_BEGIN_Msk 0x000000FFUL /*!< Number of the first message object */ #define CAN_LIST_LIST_END_Msk 0x0000FF00UL /*!< Number of the last message object */ #define CAN_LIST_LIST_SIZE_Msk 0x00FF0000UL /*!< List size */ #define CAN_LIST_LIST_EMPTY_Msk 0x01000000UL /*!< Indicate empty list */ /*-- MSPND: MSPND: Register waiting interrupts0 ---------------------------------------------------------------*/ typedef struct { uint32_t PND :32; /*!< Field waiting interrupts */ } _CAN_MSPND_MSPND_bits; /* Bit field positions: */ #define CAN_MSPND_MSPND_PND_Pos 0 /*!< Field waiting interrupts */ /* Bit field masks: */ #define CAN_MSPND_MSPND_PND_Msk 0xFFFFFFFFUL /*!< Field waiting interrupts */ /*-- MSID: MSID: Register messages index0 ---------------------------------------------------------------------*/ typedef struct { uint32_t INDEX :6; /*!< */ } _CAN_MSID_MSID_bits; /* Bit field positions: */ #define CAN_MSID_MSID_INDEX_Pos 0 /*!< */ /* Bit field masks: */ #define CAN_MSID_MSID_INDEX_Msk 0x0000003FUL /*!< */ /*-- MSIMASK: Mask register message index --------------------------------------------------------------------*/ typedef struct { uint32_t IM :32; /*!< Mask for waiting bit messages */ } _CAN_MSIMASK_bits; /* Bit field positions: */ #define CAN_MSIMASK_IM_Pos 0 /*!< Mask for waiting bit messages */ /* Bit field masks: */ #define CAN_MSIMASK_IM_Msk 0xFFFFFFFFUL /*!< Mask for waiting bit messages */ /*-- PANCTR: Register command panel --------------------------------------------------------------------------*/ typedef struct { uint32_t PANCMD :8; /*!< Command panel */ uint32_t BUSY :1; /*!< Busy flag panels arguments (waiting to be written at the end of the command) */ uint32_t RBUSY :1; /*!< Busy flag panels arguments (running the command list, the result of which will be recorded in PANAR1 and PANAR2) */ uint32_t :6; /*!< RESERVED */ uint32_t PANAR1 :8; /*!< Panel argument 8 */ uint32_t PANAR2 :8; /*!< Panel argument 9 */ } _CAN_PANCTR_bits; /* Bit field positions: */ #define CAN_PANCTR_PANCMD_Pos 0 /*!< Command panel */ #define CAN_PANCTR_BUSY_Pos 8 /*!< Busy flag panels arguments (waiting to be written at the end of the command) */ #define CAN_PANCTR_RBUSY_Pos 9 /*!< Busy flag panels arguments (running the command list, the result of which will be recorded in PANAR1 and PANAR2) */ #define CAN_PANCTR_PANAR1_Pos 16 /*!< Panel argument 8 */ #define CAN_PANCTR_PANAR2_Pos 24 /*!< Panel argument 9 */ /* Bit field masks: */ #define CAN_PANCTR_PANCMD_Msk 0x000000FFUL /*!< Command panel */ #define CAN_PANCTR_BUSY_Msk 0x00000100UL /*!< Busy flag panels arguments (waiting to be written at the end of the command) */ #define CAN_PANCTR_RBUSY_Msk 0x00000200UL /*!< Busy flag panels arguments (running the command list, the result of which will be recorded in PANAR1 and PANAR2) */ #define CAN_PANCTR_PANAR1_Msk 0x00FF0000UL /*!< Panel argument 8 */ #define CAN_PANCTR_PANAR2_Msk 0xFF000000UL /*!< Panel argument 9 */ /*-- MCR: ---------------------------------------------------------------------------------------------------*/ typedef struct { uint32_t :12; /*!< RESERVED */ uint32_t MPSEL :4; /*!< Field task position after waiting message bit transmit / receive messages */ } _CAN_MCR_bits; /* Bit field positions: */ #define CAN_MCR_MPSEL_Pos 12 /*!< Field task position after waiting message bit transmit / receive messages */ /* Bit field masks: */ #define CAN_MCR_MPSEL_Msk 0x0000F000UL /*!< Field task position after waiting message bit transmit / receive messages */ /*-- MITR: Interrupt register --------------------------------------------------------------------------------*/ typedef struct { uint32_t IT :16; /*!< Field generate interrupt */ } _CAN_MITR_bits; /* Bit field positions: */ #define CAN_MITR_IT_Pos 0 /*!< Field generate interrupt */ /* Bit field masks: */ #define CAN_MITR_IT_Msk 0x0000FFFFUL /*!< Field generate interrupt */ /*-- Node: NCR: Register control node0 ------------------------------------------------------------------------*/ typedef struct { uint32_t INIT :1; /*!< Node initialization */ uint32_t TRIE :1; /*!< Interrupt enable bit of the assembly at the end of the transmission / reception */ uint32_t LECIE :1; /*!< Interrupt enable bit of the assembly when it detects the last error code */ uint32_t ALIE :1; /*!< Enable interrupt ALERT from node */ uint32_t CANDIS :1; /*!< Off node */ uint32_t :1; /*!< RESERVED */ uint32_t CCE :1; /*!< Permission node configuration changes */ uint32_t CALM :1; /*!< Activate the node analysis */ } _CAN_Node_NCR_bits; /* Bit field positions: */ #define CAN_Node_NCR_INIT_Pos 0 /*!< Node initialization */ #define CAN_Node_NCR_TRIE_Pos 1 /*!< Interrupt enable bit of the assembly at the end of the transmission / reception */ #define CAN_Node_NCR_LECIE_Pos 2 /*!< Interrupt enable bit of the assembly when it detects the last error code */ #define CAN_Node_NCR_ALIE_Pos 3 /*!< Enable interrupt ALERT from node */ #define CAN_Node_NCR_CANDIS_Pos 4 /*!< Off node */ #define CAN_Node_NCR_CCE_Pos 6 /*!< Permission node configuration changes */ #define CAN_Node_NCR_CALM_Pos 7 /*!< Activate the node analysis */ /* Bit field masks: */ #define CAN_Node_NCR_INIT_Msk 0x00000001UL /*!< Node initialization */ #define CAN_Node_NCR_TRIE_Msk 0x00000002UL /*!< Interrupt enable bit of the assembly at the end of the transmission / reception */ #define CAN_Node_NCR_LECIE_Msk 0x00000004UL /*!< Interrupt enable bit of the assembly when it detects the last error code */ #define CAN_Node_NCR_ALIE_Msk 0x00000008UL /*!< Enable interrupt ALERT from node */ #define CAN_Node_NCR_CANDIS_Msk 0x00000010UL /*!< Off node */ #define CAN_Node_NCR_CCE_Msk 0x00000040UL /*!< Permission node configuration changes */ #define CAN_Node_NCR_CALM_Msk 0x00000080UL /*!< Activate the node analysis */ /*-- Node: NSR: Register state node0 --------------------------------------------------------------------------*/ typedef struct { uint32_t LEC :3; /*!< Last error code */ uint32_t TXOK :1; /*!< Flag successful message transmission */ uint32_t RXOK :1; /*!< Flag successful reception of messages */ uint32_t ALERT :1; /*!< Warning flag ALERT */ uint32_t EWRN :1; /*!< Flag critical errors */ uint32_t BOFF :1; /*!< Status flag 'is disconnected from the bus' */ uint32_t LLE :1; /*!< Error flag list */ uint32_t LOE :1; /*!< Error Flag Room list */ } _CAN_Node_NSR_bits; /* Bit field positions: */ #define CAN_Node_NSR_LEC_Pos 0 /*!< Last error code */ #define CAN_Node_NSR_TXOK_Pos 3 /*!< Flag successful message transmission */ #define CAN_Node_NSR_RXOK_Pos 4 /*!< Flag successful reception of messages */ #define CAN_Node_NSR_ALERT_Pos 5 /*!< Warning flag ALERT */ #define CAN_Node_NSR_EWRN_Pos 6 /*!< Flag critical errors */ #define CAN_Node_NSR_BOFF_Pos 7 /*!< Status flag 'is disconnected from the bus' */ #define CAN_Node_NSR_LLE_Pos 8 /*!< Error flag list */ #define CAN_Node_NSR_LOE_Pos 9 /*!< Error Flag Room list */ /* Bit field masks: */ #define CAN_Node_NSR_LEC_Msk 0x00000007UL /*!< Last error code */ #define CAN_Node_NSR_TXOK_Msk 0x00000008UL /*!< Flag successful message transmission */ #define CAN_Node_NSR_RXOK_Msk 0x00000010UL /*!< Flag successful reception of messages */ #define CAN_Node_NSR_ALERT_Msk 0x00000020UL /*!< Warning flag ALERT */ #define CAN_Node_NSR_EWRN_Msk 0x00000040UL /*!< Flag critical errors */ #define CAN_Node_NSR_BOFF_Msk 0x00000080UL /*!< Status flag 'is disconnected from the bus' */ #define CAN_Node_NSR_LLE_Msk 0x00000100UL /*!< Error flag list */ #define CAN_Node_NSR_LOE_Msk 0x00000200UL /*!< Error Flag Room list */ /* Bit field enums: */ typedef enum { CAN_Node_NSR_LEC_NoErr = 0x0UL, /*!< no error */ CAN_Node_NSR_LEC_StuffErr = 0x1UL, /*!< stuff error */ CAN_Node_NSR_LEC_FormErr = 0x2UL, /*!< form error */ CAN_Node_NSR_LEC_AckErr = 0x3UL, /*!< acknowlegment error */ CAN_Node_NSR_LEC_Bit1Err = 0x4UL, /*!< bit 1 error */ CAN_Node_NSR_LEC_Bit0Err = 0x5UL, /*!< bit 0 error */ CAN_Node_NSR_LEC_CRCErr = 0x6UL, /*!< CRC error */ CAN_Node_NSR_LEC_WriteEn = 0x7UL, /*!< enable hardware write */ } CAN_Node_NSR_LEC_Enum; /*-- Node: NIPR: Interrupt pointer register node0 -------------------------------------------------------------*/ typedef struct { uint32_t ALINP :4; /*!< */ uint32_t LECINP :4; /*!< */ uint32_t TRINP :4; /*!< */ uint32_t CFCINP :4; /*!< */ } _CAN_Node_NIPR_bits; /* Bit field positions: */ #define CAN_Node_NIPR_ALINP_Pos 0 /*!< */ #define CAN_Node_NIPR_LECINP_Pos 4 /*!< */ #define CAN_Node_NIPR_TRINP_Pos 8 /*!< */ #define CAN_Node_NIPR_CFCINP_Pos 12 /*!< */ /* Bit field masks: */ #define CAN_Node_NIPR_ALINP_Msk 0x0000000FUL /*!< */ #define CAN_Node_NIPR_LECINP_Msk 0x000000F0UL /*!< */ #define CAN_Node_NIPR_TRINP_Msk 0x00000F00UL /*!< */ #define CAN_Node_NIPR_CFCINP_Msk 0x0000F000UL /*!< */ /*-- Node: NPCR: Port control register node0 ------------------------------------------------------------------*/ typedef struct { uint32_t :8; /*!< RESERVED */ uint32_t LBM :1; /*!< Enable mode Loop-Back */ } _CAN_Node_NPCR_bits; /* Bit field positions: */ #define CAN_Node_NPCR_LBM_Pos 8 /*!< Enable mode Loop-Back */ /* Bit field masks: */ #define CAN_Node_NPCR_LBM_Msk 0x00000100UL /*!< Enable mode Loop-Back */ /*-- Node: NBTR: Timing register bits 0 -----------------------------------------------------------------------*/ typedef struct { uint32_t BRP :6; /*!< Prescaler rate */ uint32_t SJW :2; /*!< Transition width resynchronization */ uint32_t TSEG1 :4; /*!< Parameter 1 */ uint32_t TSEG2 :3; /*!< Parameter 2 */ uint32_t DIV8 :1; /*!< Frequency divider by 8 */ } _CAN_Node_NBTR_bits; /* Bit field positions: */ #define CAN_Node_NBTR_BRP_Pos 0 /*!< Prescaler rate */ #define CAN_Node_NBTR_SJW_Pos 6 /*!< Transition width resynchronization */ #define CAN_Node_NBTR_TSEG1_Pos 8 /*!< Parameter 1 */ #define CAN_Node_NBTR_TSEG2_Pos 12 /*!< Parameter 2 */ #define CAN_Node_NBTR_DIV8_Pos 15 /*!< Frequency divider by 8 */ /* Bit field masks: */ #define CAN_Node_NBTR_BRP_Msk 0x0000003FUL /*!< Prescaler rate */ #define CAN_Node_NBTR_SJW_Msk 0x000000C0UL /*!< Transition width resynchronization */ #define CAN_Node_NBTR_TSEG1_Msk 0x00000F00UL /*!< Parameter 1 */ #define CAN_Node_NBTR_TSEG2_Msk 0x00007000UL /*!< Parameter 2 */ #define CAN_Node_NBTR_DIV8_Msk 0x00008000UL /*!< Frequency divider by 8 */ /*-- Node: NECNT: Counter error register node0 ----------------------------------------------------------------*/ typedef struct { uint32_t REC :8; /*!< Receive Error Counter field messages */ uint32_t TEC :8; /*!< Counter field messaging error */ uint32_t EWRNLVL :8; /*!< Error limit at which a flag is set in the register EWRN NSR */ uint32_t LETD :1; /*!< Flag last transmission errors */ uint32_t LEINC :1; /*!< Indicator increment at the last error */ } _CAN_Node_NECNT_bits; /* Bit field positions: */ #define CAN_Node_NECNT_REC_Pos 0 /*!< Receive Error Counter field messages */ #define CAN_Node_NECNT_TEC_Pos 8 /*!< Counter field messaging error */ #define CAN_Node_NECNT_EWRNLVL_Pos 16 /*!< Error limit at which a flag is set in the register EWRN NSR */ #define CAN_Node_NECNT_LETD_Pos 24 /*!< Flag last transmission errors */ #define CAN_Node_NECNT_LEINC_Pos 25 /*!< Indicator increment at the last error */ /* Bit field masks: */ #define CAN_Node_NECNT_REC_Msk 0x000000FFUL /*!< Receive Error Counter field messages */ #define CAN_Node_NECNT_TEC_Msk 0x0000FF00UL /*!< Counter field messaging error */ #define CAN_Node_NECNT_EWRNLVL_Msk 0x00FF0000UL /*!< Error limit at which a flag is set in the register EWRN NSR */ #define CAN_Node_NECNT_LETD_Msk 0x01000000UL /*!< Flag last transmission errors */ #define CAN_Node_NECNT_LEINC_Msk 0x02000000UL /*!< Indicator increment at the last error */ /*-- Node: NFCR: Register message counter node0 ---------------------------------------------------------------*/ typedef struct { uint32_t CFC :16; /*!< Field of the message counter */ uint32_t CFSEL :3; /*!< Field parameter setting mode selected message counter */ uint32_t CFMOD :2; /*!< Field task mode message counter */ uint32_t :1; /*!< RESERVED */ uint32_t CFCIE :1; /*!< Interrupt enable bit of the message counter */ uint32_t CFCOV :1; /*!< Counter overflow flag messages */ } _CAN_Node_NFCR_bits; /* Bit field positions: */ #define CAN_Node_NFCR_CFC_Pos 0 /*!< Field of the message counter */ #define CAN_Node_NFCR_CFSEL_Pos 16 /*!< Field parameter setting mode selected message counter */ #define CAN_Node_NFCR_CFMOD_Pos 19 /*!< Field task mode message counter */ #define CAN_Node_NFCR_CFCIE_Pos 22 /*!< Interrupt enable bit of the message counter */ #define CAN_Node_NFCR_CFCOV_Pos 23 /*!< Counter overflow flag messages */ /* Bit field masks: */ #define CAN_Node_NFCR_CFC_Msk 0x0000FFFFUL /*!< Field of the message counter */ #define CAN_Node_NFCR_CFSEL_Msk 0x00070000UL /*!< Field parameter setting mode selected message counter */ #define CAN_Node_NFCR_CFMOD_Msk 0x00180000UL /*!< Field task mode message counter */ #define CAN_Node_NFCR_CFCIE_Msk 0x00400000UL /*!< Interrupt enable bit of the message counter */ #define CAN_Node_NFCR_CFCOV_Msk 0x00800000UL /*!< Counter overflow flag messages */ //Cluster LIST: typedef struct { union { /*!< Register list0 */ __I uint32_t LIST; /*!< LIST : type used for word access */ __I _CAN_LIST_LIST_bits LIST_bit; /*!< LIST_bit: structure used for bit access */ }; } _CAN_LIST_TypeDef; //Cluster MSPND: typedef struct { union { /*!< Register waiting interrupts0 */ __IO uint32_t MSPND; /*!< MSPND : type used for word access */ __IO _CAN_MSPND_MSPND_bits MSPND_bit; /*!< MSPND_bit: structure used for bit access */ }; } _CAN_MSPND_TypeDef; //Cluster MSID: typedef struct { union { /*!< Register messages index0 */ __I uint32_t MSID; /*!< MSID : type used for word access */ __I _CAN_MSID_MSID_bits MSID_bit; /*!< MSID_bit: structure used for bit access */ }; } _CAN_MSID_TypeDef; //Cluster Node: typedef struct { union { /*!< Register control node0 */ __IO uint32_t NCR; /*!< NCR : type used for word access */ __IO _CAN_Node_NCR_bits NCR_bit; /*!< NCR_bit: structure used for bit access */ }; union { /*!< Register state node0 */ __IO uint32_t NSR; /*!< NSR : type used for word access */ __IO _CAN_Node_NSR_bits NSR_bit; /*!< NSR_bit: structure used for bit access */ }; union { /*!< Interrupt pointer register node0 */ __IO uint32_t NIPR; /*!< NIPR : type used for word access */ __IO _CAN_Node_NIPR_bits NIPR_bit; /*!< NIPR_bit: structure used for bit access */ }; union { /*!< Port control register node0 */ __IO uint32_t NPCR; /*!< NPCR : type used for word access */ __IO _CAN_Node_NPCR_bits NPCR_bit; /*!< NPCR_bit: structure used for bit access */ }; union { /*!< Timing register bits 0 */ __IO uint32_t NBTR; /*!< NBTR : type used for word access */ __IO _CAN_Node_NBTR_bits NBTR_bit; /*!< NBTR_bit: structure used for bit access */ }; union { /*!< Counter error register node0 */ __IO uint32_t NECNT; /*!< NECNT : type used for word access */ __IO _CAN_Node_NECNT_bits NECNT_bit; /*!< NECNT_bit: structure used for bit access */ }; union { /*!< Register message counter node0 */ __IO uint32_t NFCR; /*!< NFCR : type used for word access */ __IO _CAN_Node_NFCR_bits NFCR_bit; /*!< NFCR_bit: structure used for bit access */ }; __IO uint32_t Reserved0[57]; } _CAN_Node_TypeDef; typedef struct { union { /*!< Frequency control register */ __IO uint32_t CLC; /*!< CLC : type used for word access */ __IO _CAN_CLC_bits CLC_bit; /*!< CLC_bit: structure used for bit access */ }; __IO uint32_t Reserved0; union { /*!< Identity register */ __IO uint32_t ID; /*!< ID : type used for word access */ __IO _CAN_ID_bits ID_bit; /*!< ID_bit: structure used for bit access */ }; union { /*!< Register divider */ __IO uint32_t FDR; /*!< FDR : type used for word access */ __IO _CAN_FDR_bits FDR_bit; /*!< FDR_bit: structure used for bit access */ }; __IO uint32_t Reserved1[60]; _CAN_LIST_TypeDef LIST[8]; __IO uint32_t Reserved2[8]; _CAN_MSPND_TypeDef MSPND[8]; __IO uint32_t Reserved3[8]; _CAN_MSID_TypeDef MSID[8]; __IO uint32_t Reserved4[8]; union { /*!< Mask register message index */ __IO uint32_t MSIMASK; /*!< MSIMASK : type used for word access */ __IO _CAN_MSIMASK_bits MSIMASK_bit; /*!< MSIMASK_bit: structure used for bit access */ }; union { /*!< Register command panel */ __IO uint32_t PANCTR; /*!< PANCTR : type used for word access */ __IO _CAN_PANCTR_bits PANCTR_bit; /*!< PANCTR_bit: structure used for bit access */ }; union { /*!< */ __IO uint32_t MCR; /*!< MCR : type used for word access */ __IO _CAN_MCR_bits MCR_bit; /*!< MCR_bit: structure used for bit access */ }; union { /*!< Interrupt register */ __O uint32_t MITR; /*!< MITR : type used for word access */ __O _CAN_MITR_bits MITR_bit; /*!< MITR_bit: structure used for bit access */ }; __IO uint32_t Reserved5[12]; _CAN_Node_TypeDef Node[2]; } CAN_TypeDef; /******************************************************************************/ /* CANMSG registers */ /******************************************************************************/ /*-- Msg: MOFCR: Register control the operation of the message object 0 ---------------------------------------*/ typedef struct { uint32_t MMC :4; /*!< */ uint32_t :4; /*!< RESERVED */ uint32_t GDFS :1; /*!< */ uint32_t IDC :1; /*!< */ uint32_t DLCC :1; /*!< */ uint32_t DATC :1; /*!< */ uint32_t :4; /*!< RESERVED */ uint32_t RXIE :1; /*!< Interrupt enable after taking the messages */ uint32_t TXIE :1; /*!< Interrupt enable at the end of the message */ uint32_t OVIE :1; /*!< Interrupt enable FIFO to fill the message object 0 */ uint32_t :1; /*!< RESERVED */ uint32_t FRREN :1; /*!< Enable remote request */ uint32_t RMM :1; /*!< Enable remote monitoring of the communication object */ uint32_t SDT :1; /*!< Bit single of the message object 0 participation in shipment */ uint32_t STT :1; /*!< Bit single data transfer */ uint32_t DLC :4; /*!< Data length code */ } _CANMSG_Msg_MOFCR_bits; /* Bit field positions: */ #define CANMSG_Msg_MOFCR_MMC_Pos 0 /*!< */ #define CANMSG_Msg_MOFCR_GDFS_Pos 8 /*!< */ #define CANMSG_Msg_MOFCR_IDC_Pos 9 /*!< */ #define CANMSG_Msg_MOFCR_DLCC_Pos 10 /*!< */ #define CANMSG_Msg_MOFCR_DATC_Pos 11 /*!< */ #define CANMSG_Msg_MOFCR_RXIE_Pos 16 /*!< Interrupt enable after taking the messages */ #define CANMSG_Msg_MOFCR_TXIE_Pos 17 /*!< Interrupt enable at the end of the message */ #define CANMSG_Msg_MOFCR_OVIE_Pos 18 /*!< Interrupt enable FIFO to fill the message object 0 */ #define CANMSG_Msg_MOFCR_FRREN_Pos 20 /*!< Enable remote request */ #define CANMSG_Msg_MOFCR_RMM_Pos 21 /*!< Enable remote monitoring of the communication object */ #define CANMSG_Msg_MOFCR_SDT_Pos 22 /*!< Bit single of the message object 0 participation in shipment */ #define CANMSG_Msg_MOFCR_STT_Pos 23 /*!< Bit single data transfer */ #define CANMSG_Msg_MOFCR_DLC_Pos 24 /*!< Data length code */ /* Bit field masks: */ #define CANMSG_Msg_MOFCR_MMC_Msk 0x0000000FUL /*!< */ #define CANMSG_Msg_MOFCR_GDFS_Msk 0x00000100UL /*!< */ #define CANMSG_Msg_MOFCR_IDC_Msk 0x00000200UL /*!< */ #define CANMSG_Msg_MOFCR_DLCC_Msk 0x00000400UL /*!< */ #define CANMSG_Msg_MOFCR_DATC_Msk 0x00000800UL /*!< */ #define CANMSG_Msg_MOFCR_RXIE_Msk 0x00010000UL /*!< Interrupt enable after taking the messages */ #define CANMSG_Msg_MOFCR_TXIE_Msk 0x00020000UL /*!< Interrupt enable at the end of the message */ #define CANMSG_Msg_MOFCR_OVIE_Msk 0x00040000UL /*!< Interrupt enable FIFO to fill the message object 0 */ #define CANMSG_Msg_MOFCR_FRREN_Msk 0x00100000UL /*!< Enable remote request */ #define CANMSG_Msg_MOFCR_RMM_Msk 0x00200000UL /*!< Enable remote monitoring of the communication object */ #define CANMSG_Msg_MOFCR_SDT_Msk 0x00400000UL /*!< Bit single of the message object 0 participation in shipment */ #define CANMSG_Msg_MOFCR_STT_Msk 0x00800000UL /*!< Bit single data transfer */ #define CANMSG_Msg_MOFCR_DLC_Msk 0x0F000000UL /*!< Data length code */ /* Bit field enums: */ typedef enum { CANMSG_Msg_MOFCR_MMC_MsgObj = 0x0UL, /*!< message object */ CANMSG_Msg_MOFCR_MMC_RXObj = 0x1UL, /*!< receiver FIFO structure object */ CANMSG_Msg_MOFCR_MMC_TXObj = 0x2UL, /*!< transmitter FIFO structure object */ CANMSG_Msg_MOFCR_MMC_SlaveTXObj = 0x3UL, /*!< transmitter FIFO structure slave object */ CANMSG_Msg_MOFCR_MMC_SrcObj = 0x4UL, /*!< gateway source object */ } CANMSG_Msg_MOFCR_MMC_Enum; /*-- Msg: MOFGPR: Pointer register FIFO / gateway message object 0 --------------------------------------------*/ typedef struct { uint32_t BOT :8; /*!< FIFO pointer to the lower element */ uint32_t TOP :8; /*!< FIFO pointer to the top element */ uint32_t CUR :8; /*!< A pointer to the current object within the FIFO or gateway */ uint32_t SEL :8; /*!< Object pointer message */ } _CANMSG_Msg_MOFGPR_bits; /* Bit field positions: */ #define CANMSG_Msg_MOFGPR_BOT_Pos 0 /*!< FIFO pointer to the lower element */ #define CANMSG_Msg_MOFGPR_TOP_Pos 8 /*!< FIFO pointer to the top element */ #define CANMSG_Msg_MOFGPR_CUR_Pos 16 /*!< A pointer to the current object within the FIFO or gateway */ #define CANMSG_Msg_MOFGPR_SEL_Pos 24 /*!< Object pointer message */ /* Bit field masks: */ #define CANMSG_Msg_MOFGPR_BOT_Msk 0x000000FFUL /*!< FIFO pointer to the lower element */ #define CANMSG_Msg_MOFGPR_TOP_Msk 0x0000FF00UL /*!< FIFO pointer to the top element */ #define CANMSG_Msg_MOFGPR_CUR_Msk 0x00FF0000UL /*!< A pointer to the current object within the FIFO or gateway */ #define CANMSG_Msg_MOFGPR_SEL_Msk 0xFF000000UL /*!< Object pointer message */ /*-- Msg: MOIPR: Pointer register interrupt message object 0 --------------------------------------------------*/ typedef struct { uint32_t RXINP :4; /*!< Pointer interrupt line to interrupt after receiving */ uint32_t TXINP :4; /*!< Pointer interrupt line to interrupt after transfer */ uint32_t MPN :8; /*!< Number message waiting bit */ uint32_t CFCVAL :16; /*!< Number of frames */ } _CANMSG_Msg_MOIPR_bits; /* Bit field positions: */ #define CANMSG_Msg_MOIPR_RXINP_Pos 0 /*!< Pointer interrupt line to interrupt after receiving */ #define CANMSG_Msg_MOIPR_TXINP_Pos 4 /*!< Pointer interrupt line to interrupt after transfer */ #define CANMSG_Msg_MOIPR_MPN_Pos 8 /*!< Number message waiting bit */ #define CANMSG_Msg_MOIPR_CFCVAL_Pos 16 /*!< Number of frames */ /* Bit field masks: */ #define CANMSG_Msg_MOIPR_RXINP_Msk 0x0000000FUL /*!< Pointer interrupt line to interrupt after receiving */ #define CANMSG_Msg_MOIPR_TXINP_Msk 0x000000F0UL /*!< Pointer interrupt line to interrupt after transfer */ #define CANMSG_Msg_MOIPR_MPN_Msk 0x0000FF00UL /*!< Number message waiting bit */ #define CANMSG_Msg_MOIPR_CFCVAL_Msk 0xFFFF0000UL /*!< Number of frames */ /*-- Msg: MOAMR: Mask register message object 0 ---------------------------------------------------------------*/ typedef struct { uint32_t AM :29; /*!< Mask ID */ uint32_t MIDE :1; /*!< Mask bit IDE message */ } _CANMSG_Msg_MOAMR_bits; /* Bit field positions: */ #define CANMSG_Msg_MOAMR_AM_Pos 0 /*!< Mask ID */ #define CANMSG_Msg_MOAMR_MIDE_Pos 29 /*!< Mask bit IDE message */ /* Bit field masks: */ #define CANMSG_Msg_MOAMR_AM_Msk 0x1FFFFFFFUL /*!< Mask ID */ #define CANMSG_Msg_MOAMR_MIDE_Msk 0x20000000UL /*!< Mask bit IDE message */ /*-- Msg: MODATAL: Low data registers of the message object 0 -------------------------------------------------*/ typedef struct { uint32_t DB0 :8; /*!< Zero byte data */ uint32_t DB1 :8; /*!< The first data byte */ uint32_t DB2 :8; /*!< Second data byte */ uint32_t DB3 :8; /*!< The third data byte */ } _CANMSG_Msg_MODATAL_bits; /* Bit field positions: */ #define CANMSG_Msg_MODATAL_DB0_Pos 0 /*!< Zero byte data */ #define CANMSG_Msg_MODATAL_DB1_Pos 8 /*!< The first data byte */ #define CANMSG_Msg_MODATAL_DB2_Pos 16 /*!< Second data byte */ #define CANMSG_Msg_MODATAL_DB3_Pos 24 /*!< The third data byte */ /* Bit field masks: */ #define CANMSG_Msg_MODATAL_DB0_Msk 0x000000FFUL /*!< Zero byte data */ #define CANMSG_Msg_MODATAL_DB1_Msk 0x0000FF00UL /*!< The first data byte */ #define CANMSG_Msg_MODATAL_DB2_Msk 0x00FF0000UL /*!< Second data byte */ #define CANMSG_Msg_MODATAL_DB3_Msk 0xFF000000UL /*!< The third data byte */ /*-- Msg: MODATAH: High data registers of the message object 0 ------------------------------------------------*/ typedef struct { uint32_t DB4 :8; /*!< The fourth data byte */ uint32_t DB5 :8; /*!< Fifth byte data */ uint32_t DB6 :8; /*!< Sixth byte data */ uint32_t DB7 :8; /*!< Seventh byte of data */ } _CANMSG_Msg_MODATAH_bits; /* Bit field positions: */ #define CANMSG_Msg_MODATAH_DB4_Pos 0 /*!< The fourth data byte */ #define CANMSG_Msg_MODATAH_DB5_Pos 8 /*!< Fifth byte data */ #define CANMSG_Msg_MODATAH_DB6_Pos 16 /*!< Sixth byte data */ #define CANMSG_Msg_MODATAH_DB7_Pos 24 /*!< Seventh byte of data */ /* Bit field masks: */ #define CANMSG_Msg_MODATAH_DB4_Msk 0x000000FFUL /*!< The fourth data byte */ #define CANMSG_Msg_MODATAH_DB5_Msk 0x0000FF00UL /*!< Fifth byte data */ #define CANMSG_Msg_MODATAH_DB6_Msk 0x00FF0000UL /*!< Sixth byte data */ #define CANMSG_Msg_MODATAH_DB7_Msk 0xFF000000UL /*!< Seventh byte of data */ /*-- Msg: MOAR: Register arbitration message object 0 ---------------------------------------------------------*/ typedef struct { uint32_t ID :29; /*!< Object ID message 0 */ uint32_t IDE :1; /*!< Bit extension identifier of the message object 0 */ uint32_t PRI :2; /*!< Priority class */ } _CANMSG_Msg_MOAR_bits; /* Bit field positions: */ #define CANMSG_Msg_MOAR_ID_Pos 0 /*!< Object ID message 0 */ #define CANMSG_Msg_MOAR_IDE_Pos 29 /*!< Bit extension identifier of the message object 0 */ #define CANMSG_Msg_MOAR_PRI_Pos 30 /*!< Priority class */ /* Bit field masks: */ #define CANMSG_Msg_MOAR_ID_Msk 0x1FFFFFFFUL /*!< Object ID message 0 */ #define CANMSG_Msg_MOAR_IDE_Msk 0x20000000UL /*!< Bit extension identifier of the message object 0 */ #define CANMSG_Msg_MOAR_PRI_Msk 0xC0000000UL /*!< Priority class */ /*-- Msg: MOCTR: Control register Message object 0 ------------------------------------------------------------*/ typedef struct { uint32_t RESRXPND :1; /*!< Reset bit RXPND */ uint32_t RESTXPND :1; /*!< Reset bit TXPND */ uint32_t RESRXUPD :1; /*!< Reset bit RXUPD */ uint32_t RESNEWDAT :1; /*!< Reset bit NEWDAT */ uint32_t RESMSGLST :1; /*!< Reset bit MSGLST */ uint32_t RESMSGVAL :1; /*!< Reset bit MSGVAL */ uint32_t RESRTSEL :1; /*!< Reset bit RTSEL */ uint32_t RESRXEN :1; /*!< Reset bit RXEN */ uint32_t RESTXRQ :1; /*!< Reset bit TXRQ */ uint32_t RESTXEN0 :1; /*!< Reset bit TXEN0 */ uint32_t RESTXEN1 :1; /*!< Reset bit TXEN1 */ uint32_t RESDIR :1; /*!< Reset bit DIR */ uint32_t :4; /*!< RESERVED */ uint32_t SETRXPND :1; /*!< Set bit RXPND */ uint32_t SETTXPND :1; /*!< Set bit TXPND */ uint32_t SETRXUPD :1; /*!< Set bit RXUPD */ uint32_t SETNEWDAT :1; /*!< Set bit NEWDAT */ uint32_t SETMSGLST :1; /*!< Set bit MSGLST */ uint32_t SETMSGVAL :1; /*!< Set bit MSGVAL */ uint32_t SETRTSEL :1; /*!< Set bit RTSEL */ uint32_t SETRXEN :1; /*!< Set bit RXEN */ uint32_t SETTXRQ :1; /*!< Set bit TXRQ */ uint32_t SETTXEN0 :1; /*!< Set bit TXEN0 */ uint32_t SETTXEN1 :1; /*!< Set bit TXEN1 */ uint32_t SETDIR :1; /*!< Set bit DIR */ } _CANMSG_Msg_MOCTR_bits; /* Bit field positions: */ #define CANMSG_Msg_MOCTR_RESRXPND_Pos 0 /*!< Reset bit RXPND */ #define CANMSG_Msg_MOCTR_RESTXPND_Pos 1 /*!< Reset bit TXPND */ #define CANMSG_Msg_MOCTR_RESRXUPD_Pos 2 /*!< Reset bit RXUPD */ #define CANMSG_Msg_MOCTR_RESNEWDAT_Pos 3 /*!< Reset bit NEWDAT */ #define CANMSG_Msg_MOCTR_RESMSGLST_Pos 4 /*!< Reset bit MSGLST */ #define CANMSG_Msg_MOCTR_RESMSGVAL_Pos 5 /*!< Reset bit MSGVAL */ #define CANMSG_Msg_MOCTR_RESRTSEL_Pos 6 /*!< Reset bit RTSEL */ #define CANMSG_Msg_MOCTR_RESRXEN_Pos 7 /*!< Reset bit RXEN */ #define CANMSG_Msg_MOCTR_RESTXRQ_Pos 8 /*!< Reset bit TXRQ */ #define CANMSG_Msg_MOCTR_RESTXEN0_Pos 9 /*!< Reset bit TXEN0 */ #define CANMSG_Msg_MOCTR_RESTXEN1_Pos 10 /*!< Reset bit TXEN1 */ #define CANMSG_Msg_MOCTR_RESDIR_Pos 11 /*!< Reset bit DIR */ #define CANMSG_Msg_MOCTR_SETRXPND_Pos 16 /*!< Set bit RXPND */ #define CANMSG_Msg_MOCTR_SETTXPND_Pos 17 /*!< Set bit TXPND */ #define CANMSG_Msg_MOCTR_SETRXUPD_Pos 18 /*!< Set bit RXUPD */ #define CANMSG_Msg_MOCTR_SETNEWDAT_Pos 19 /*!< Set bit NEWDAT */ #define CANMSG_Msg_MOCTR_SETMSGLST_Pos 20 /*!< Set bit MSGLST */ #define CANMSG_Msg_MOCTR_SETMSGVAL_Pos 21 /*!< Set bit MSGVAL */ #define CANMSG_Msg_MOCTR_SETRTSEL_Pos 22 /*!< Set bit RTSEL */ #define CANMSG_Msg_MOCTR_SETRXEN_Pos 23 /*!< Set bit RXEN */ #define CANMSG_Msg_MOCTR_SETTXRQ_Pos 24 /*!< Set bit TXRQ */ #define CANMSG_Msg_MOCTR_SETTXEN0_Pos 25 /*!< Set bit TXEN0 */ #define CANMSG_Msg_MOCTR_SETTXEN1_Pos 26 /*!< Set bit TXEN1 */ #define CANMSG_Msg_MOCTR_SETDIR_Pos 27 /*!< Set bit DIR */ /* Bit field masks: */ #define CANMSG_Msg_MOCTR_RESRXPND_Msk 0x00000001UL /*!< Reset bit RXPND */ #define CANMSG_Msg_MOCTR_RESTXPND_Msk 0x00000002UL /*!< Reset bit TXPND */ #define CANMSG_Msg_MOCTR_RESRXUPD_Msk 0x00000004UL /*!< Reset bit RXUPD */ #define CANMSG_Msg_MOCTR_RESNEWDAT_Msk 0x00000008UL /*!< Reset bit NEWDAT */ #define CANMSG_Msg_MOCTR_RESMSGLST_Msk 0x00000010UL /*!< Reset bit MSGLST */ #define CANMSG_Msg_MOCTR_RESMSGVAL_Msk 0x00000020UL /*!< Reset bit MSGVAL */ #define CANMSG_Msg_MOCTR_RESRTSEL_Msk 0x00000040UL /*!< Reset bit RTSEL */ #define CANMSG_Msg_MOCTR_RESRXEN_Msk 0x00000080UL /*!< Reset bit RXEN */ #define CANMSG_Msg_MOCTR_RESTXRQ_Msk 0x00000100UL /*!< Reset bit TXRQ */ #define CANMSG_Msg_MOCTR_RESTXEN0_Msk 0x00000200UL /*!< Reset bit TXEN0 */ #define CANMSG_Msg_MOCTR_RESTXEN1_Msk 0x00000400UL /*!< Reset bit TXEN1 */ #define CANMSG_Msg_MOCTR_RESDIR_Msk 0x00000800UL /*!< Reset bit DIR */ #define CANMSG_Msg_MOCTR_SETRXPND_Msk 0x00010000UL /*!< Set bit RXPND */ #define CANMSG_Msg_MOCTR_SETTXPND_Msk 0x00020000UL /*!< Set bit TXPND */ #define CANMSG_Msg_MOCTR_SETRXUPD_Msk 0x00040000UL /*!< Set bit RXUPD */ #define CANMSG_Msg_MOCTR_SETNEWDAT_Msk 0x00080000UL /*!< Set bit NEWDAT */ #define CANMSG_Msg_MOCTR_SETMSGLST_Msk 0x00100000UL /*!< Set bit MSGLST */ #define CANMSG_Msg_MOCTR_SETMSGVAL_Msk 0x00200000UL /*!< Set bit MSGVAL */ #define CANMSG_Msg_MOCTR_SETRTSEL_Msk 0x00400000UL /*!< Set bit RTSEL */ #define CANMSG_Msg_MOCTR_SETRXEN_Msk 0x00800000UL /*!< Set bit RXEN */ #define CANMSG_Msg_MOCTR_SETTXRQ_Msk 0x01000000UL /*!< Set bit TXRQ */ #define CANMSG_Msg_MOCTR_SETTXEN0_Msk 0x02000000UL /*!< Set bit TXEN0 */ #define CANMSG_Msg_MOCTR_SETTXEN1_Msk 0x04000000UL /*!< Set bit TXEN1 */ #define CANMSG_Msg_MOCTR_SETDIR_Msk 0x08000000UL /*!< Set bit DIR */ /*-- Msg: MOSTAT: Status register of the message object 0 -----------------------------------------------------*/ typedef struct { uint32_t RXPND :1; /*!< Indicator deadline */ uint32_t TXPND :1; /*!< Indicator end of transmission */ uint32_t RXUPD :1; /*!< Indicator changes */ uint32_t NEWDAT :1; /*!< New data indicator */ uint32_t MSGLST :1; /*!< Bit message loss */ uint32_t MSGVAL :1; /*!< Activity bit of the message object 0 */ uint32_t RTSEL :1; /*!< The indication of transmission / reception */ uint32_t RXEN :1; /*!< Bits allow reception */ uint32_t TXRQ :1; /*!< Initiate transmission */ uint32_t TXEN0 :1; /*!< Enable bit transmission frame */ uint32_t TXEN1 :1; /*!< Enable bit transmission frame */ uint32_t DIR :1; /*!< Bit allocation */ uint32_t LIST :4; /*!< Number list the message object 0 */ uint32_t PPREV :8; /*!< Pointer to the previous entry */ uint32_t PNEXT :8; /*!< Pointer to the next item in the list */ } _CANMSG_Msg_MOSTAT_bits; /* Bit field positions: */ #define CANMSG_Msg_MOSTAT_RXPND_Pos 0 /*!< Indicator deadline */ #define CANMSG_Msg_MOSTAT_TXPND_Pos 1 /*!< Indicator end of transmission */ #define CANMSG_Msg_MOSTAT_RXUPD_Pos 2 /*!< Indicator changes */ #define CANMSG_Msg_MOSTAT_NEWDAT_Pos 3 /*!< New data indicator */ #define CANMSG_Msg_MOSTAT_MSGLST_Pos 4 /*!< Bit message loss */ #define CANMSG_Msg_MOSTAT_MSGVAL_Pos 5 /*!< Activity bit of the message object 0 */ #define CANMSG_Msg_MOSTAT_RTSEL_Pos 6 /*!< The indication of transmission / reception */ #define CANMSG_Msg_MOSTAT_RXEN_Pos 7 /*!< Bits allow reception */ #define CANMSG_Msg_MOSTAT_TXRQ_Pos 8 /*!< Initiate transmission */ #define CANMSG_Msg_MOSTAT_TXEN0_Pos 9 /*!< Enable bit transmission frame */ #define CANMSG_Msg_MOSTAT_TXEN1_Pos 10 /*!< Enable bit transmission frame */ #define CANMSG_Msg_MOSTAT_DIR_Pos 11 /*!< Bit allocation */ #define CANMSG_Msg_MOSTAT_LIST_Pos 12 /*!< Number list the message object 0 */ #define CANMSG_Msg_MOSTAT_PPREV_Pos 16 /*!< Pointer to the previous entry */ #define CANMSG_Msg_MOSTAT_PNEXT_Pos 24 /*!< Pointer to the next item in the list */ /* Bit field masks: */ #define CANMSG_Msg_MOSTAT_RXPND_Msk 0x00000001UL /*!< Indicator deadline */ #define CANMSG_Msg_MOSTAT_TXPND_Msk 0x00000002UL /*!< Indicator end of transmission */ #define CANMSG_Msg_MOSTAT_RXUPD_Msk 0x00000004UL /*!< Indicator changes */ #define CANMSG_Msg_MOSTAT_NEWDAT_Msk 0x00000008UL /*!< New data indicator */ #define CANMSG_Msg_MOSTAT_MSGLST_Msk 0x00000010UL /*!< Bit message loss */ #define CANMSG_Msg_MOSTAT_MSGVAL_Msk 0x00000020UL /*!< Activity bit of the message object 0 */ #define CANMSG_Msg_MOSTAT_RTSEL_Msk 0x00000040UL /*!< The indication of transmission / reception */ #define CANMSG_Msg_MOSTAT_RXEN_Msk 0x00000080UL /*!< Bits allow reception */ #define CANMSG_Msg_MOSTAT_TXRQ_Msk 0x00000100UL /*!< Initiate transmission */ #define CANMSG_Msg_MOSTAT_TXEN0_Msk 0x00000200UL /*!< Enable bit transmission frame */ #define CANMSG_Msg_MOSTAT_TXEN1_Msk 0x00000400UL /*!< Enable bit transmission frame */ #define CANMSG_Msg_MOSTAT_DIR_Msk 0x00000800UL /*!< Bit allocation */ #define CANMSG_Msg_MOSTAT_LIST_Msk 0x0000F000UL /*!< Number list the message object 0 */ #define CANMSG_Msg_MOSTAT_PPREV_Msk 0x00FF0000UL /*!< Pointer to the previous entry */ #define CANMSG_Msg_MOSTAT_PNEXT_Msk 0xFF000000UL /*!< Pointer to the next item in the list */ //Cluster Msg: typedef struct { union { /*!< Register control the operation of the message object 0 */ __IO uint32_t MOFCR; /*!< MOFCR : type used for word access */ __IO _CANMSG_Msg_MOFCR_bits MOFCR_bit; /*!< MOFCR_bit: structure used for bit access */ }; union { /*!< Pointer register FIFO / gateway message object 0 */ __IO uint32_t MOFGPR; /*!< MOFGPR : type used for word access */ __IO _CANMSG_Msg_MOFGPR_bits MOFGPR_bit; /*!< MOFGPR_bit: structure used for bit access */ }; union { /*!< Pointer register interrupt message object 0 */ __IO uint32_t MOIPR; /*!< MOIPR : type used for word access */ __IO _CANMSG_Msg_MOIPR_bits MOIPR_bit; /*!< MOIPR_bit: structure used for bit access */ }; union { /*!< Mask register message object 0 */ __IO uint32_t MOAMR; /*!< MOAMR : type used for word access */ __IO _CANMSG_Msg_MOAMR_bits MOAMR_bit; /*!< MOAMR_bit: structure used for bit access */ }; union { /*!< Low data registers of the message object 0 */ __IO uint32_t MODATAL; /*!< MODATAL : type used for word access */ __IO _CANMSG_Msg_MODATAL_bits MODATAL_bit; /*!< MODATAL_bit: structure used for bit access */ }; union { /*!< High data registers of the message object 0 */ __IO uint32_t MODATAH; /*!< MODATAH : type used for word access */ __IO _CANMSG_Msg_MODATAH_bits MODATAH_bit; /*!< MODATAH_bit: structure used for bit access */ }; union { /*!< Register arbitration message object 0 */ __IO uint32_t MOAR; /*!< MOAR : type used for word access */ __IO _CANMSG_Msg_MOAR_bits MOAR_bit; /*!< MOAR_bit: structure used for bit access */ }; union { union { /*!< Control register Message object 0 */ __O uint32_t MOCTR; /*!< MOCTR : type used for word access */ __O _CANMSG_Msg_MOCTR_bits MOCTR_bit; /*!< MOCTR_bit: structure used for bit access */ }; union { /*!< Status register of the message object 0 */ __I uint32_t MOSTAT; /*!< MOSTAT : type used for word access */ __I _CANMSG_Msg_MOSTAT_bits MOSTAT_bit; /*!< MOSTAT_bit: structure used for bit access */ }; }; } _CANMSG_Msg_TypeDef; typedef struct { _CANMSG_Msg_TypeDef Msg[256]; } CANMSG_TypeDef; /******************************************************************************/ /* I2C registers */ /******************************************************************************/ /*-- SDA: Data register --------------------------------------------------------------------------------------*/ typedef struct { uint32_t DATA :8; /*!< Data field */ } _I2C_SDA_bits; /* Bit field positions: */ #define I2C_SDA_DATA_Pos 0 /*!< Data field */ /* Bit field masks: */ #define I2C_SDA_DATA_Msk 0x000000FFUL /*!< Data field */ /*-- ST: Status register -------------------------------------------------------------------------------------*/ typedef struct { uint32_t MODE :6; /*!< Status code */ uint32_t :1; /*!< RESERVED */ uint32_t INT :1; /*!< Interrupt flag */ } _I2C_ST_bits; /* Bit field positions: */ #define I2C_ST_MODE_Pos 0 /*!< Status code */ #define I2C_ST_INT_Pos 7 /*!< Interrupt flag */ /* Bit field masks: */ #define I2C_ST_MODE_Msk 0x0000003FUL /*!< Status code */ #define I2C_ST_INT_Msk 0x00000080UL /*!< Interrupt flag */ /* Bit field enums: */ typedef enum { I2C_ST_MODE_IDLE = 0x0UL, /*!< General - Idle, no valid status information available */ I2C_ST_MODE_STDONE = 0x1UL, /*!< FS master - Start condition generated */ I2C_ST_MODE_RSDONE = 0x2UL, /*!< FS master - Repeated start condition generated */ I2C_ST_MODE_IDLARL = 0x3UL, /*!< FS master - Arbitration lost, unaddressed slave mode entered */ I2C_ST_MODE_MTADPA = 0x4UL, /*!< FS master transmit - Slave address sent, positive ACK */ I2C_ST_MODE_MTADNA = 0x5UL, /*!< FS master transmit - Slave address sent, negative ACK */ I2C_ST_MODE_MTDAPA = 0x6UL, /*!< FS master transmit - Data byte sent, positive ACK */ I2C_ST_MODE_MTDANA = 0x7UL, /*!< FS master transmit - Data byte sent, negative ACK */ I2C_ST_MODE_MRADPA = 0x8UL, /*!< FS master receive - Slave addres sent, positive ACK */ I2C_ST_MODE_MRADNA = 0x9UL, /*!< FS master receive - Slave addres sent, negative ACK */ I2C_ST_MODE_MRDAPA = 0xAUL, /*!< FS master receive - Data byte received, positive ACK */ I2C_ST_MODE_MRDANA = 0xBUL, /*!< FS master receive - Data byte received, negative ACK */ I2C_ST_MODE_MTMCER = 0xCUL, /*!< FS master - Mastercode transmitted, error detected (positive ACK) */ I2C_ST_MODE_SRADPA = 0x10UL, /*!< FS slave receive - Slave address received, positive ACK */ I2C_ST_MODE_SRAAPA = 0x11UL, /*!< FS slave receive - Slave address received after arbitration loss, positive ACK */ I2C_ST_MODE_SRDAPA = 0x12UL, /*!< FS slave receive - Data byte received, positive ACK */ I2C_ST_MODE_SRDANA = 0x13UL, /*!< FS slave receive - Data byte received, negative ACK */ I2C_ST_MODE_STADPA = 0x14UL, /*!< FS slave transmit - Slave address received, positive ACK */ I2C_ST_MODE_STAAPA = 0x15UL, /*!< FS slave transmit - Slave address received, negative ACK */ I2C_ST_MODE_STDAPA = 0x16UL, /*!< FS slave transmit - Data byte sent, positive ACK */ I2C_ST_MODE_STDANA = 0x17UL, /*!< FS slave transmit - Data byte sent, negative ACK */ I2C_ST_MODE_SATADP = 0x18UL, /*!< FS slave transmit alert response - Alert response address received, positive ACK */ I2C_ST_MODE_SATAAP = 0x19UL, /*!< FS slave transmit alert response - Alert response address received after arbitration loss, positive ACK */ I2C_ST_MODE_SATDAP = 0x1AUL, /*!< FS slave transmit alert response - Alert response data byte sent, positive ACK */ I2C_ST_MODE_SATDAN = 0x1BUL, /*!< FS slave transmit alert response - Alert response data byte sent, negative ACK */ I2C_ST_MODE_SSTOP = 0x1CUL, /*!< FS slave - Slave mode stop condition detected */ I2C_ST_MODE_SGADPA = 0x1DUL, /*!< FS slave - Global call address received, positive ACK */ I2C_ST_MODE_SDAAPA = 0x1EUL, /*!< FS slave - Global call address received after arbitration loss, positive ACK */ I2C_ST_MODE_BERROR = 0x1FUL, /*!< General - Bus error detected (invalid start or stop condition */ I2C_ST_MODE_HMTMCOK = 0x21UL, /*!< HS master - Master code transmitted OK - switched to HS mode */ I2C_ST_MODE_HRSDONE = 0x22UL, /*!< HS master - Repeated start condition generated */ I2C_ST_MODE_HIDLARL = 0x23UL, /*!< HS master - Arbitration lost, HS unaddressed slave mode entered */ I2C_ST_MODE_HMTADPA = 0x24UL, /*!< HS master transmit - Slave address sent, positive ACK */ I2C_ST_MODE_HMTADNA = 0x25UL, /*!< HS master transmit - Slave address sent, negative ACK */ I2C_ST_MODE_HMTDAPA = 0x26UL, /*!< HS master transmit - Data byte sent, positive ACK */ I2C_ST_MODE_HMTDANA = 0x27UL, /*!< HS master transmit - Data byte sent, negative ACK */ I2C_ST_MODE_HMRADPA = 0x28UL, /*!< HS master receive - Slave address sent, positive ACK */ I2C_ST_MODE_HMRADNA = 0x29UL, /*!< HS master receive - Slave address sent, negative ACK */ I2C_ST_MODE_HMRDAPA = 0x2AUL, /*!< HS master receive - Data byte received, positive ACK */ I2C_ST_MODE_HMRDANA = 0x2BUL, /*!< HS master receive - Data byte received, negative ACK */ I2C_ST_MODE_HSRADPA = 0x30UL, /*!< HS slave receive - Slave address received, positive ACK */ I2C_ST_MODE_HSRDAPA = 0x32UL, /*!< HS slave receive - Data byte received, positive ACK */ I2C_ST_MODE_HSRDANA = 0x33UL, /*!< HS slave receive - Data byte received, negative ACK */ I2C_ST_MODE_HSTADPA = 0x34UL, /*!< HS slave transmit - Slave address received, positive ACK */ I2C_ST_MODE_HSTDAPA = 0x36UL, /*!< HS slave transmit - Data byte sent, positive ACK */ I2C_ST_MODE_HSTDANA = 0x37UL, /*!< HS slave transmit - Data byte sent, negative ACK */ } I2C_ST_MODE_Enum; /*-- CST: Status and control register ------------------------------------------------------------------------*/ typedef struct { uint32_t BB :1; /*!< Flag employment bus */ uint32_t TOCDIV :2; /*!< Coeff. div */ uint32_t TOERR :1; /*!< Flag error simple bus */ uint32_t TSDA :1; /*!< Bit test SDA */ uint32_t TGSCL :1; /*!< Bit switch SCL */ uint32_t PECNEXT :1; /*!< Bit control transmit CRC */ uint32_t PECFAULT :1; /*!< Error flag */ } _I2C_CST_bits; /* Bit field positions: */ #define I2C_CST_BB_Pos 0 /*!< Flag employment bus */ #define I2C_CST_TOCDIV_Pos 1 /*!< Coeff. div */ #define I2C_CST_TOERR_Pos 3 /*!< Flag error simple bus */ #define I2C_CST_TSDA_Pos 4 /*!< Bit test SDA */ #define I2C_CST_TGSCL_Pos 5 /*!< Bit switch SCL */ #define I2C_CST_PECNEXT_Pos 6 /*!< Bit control transmit CRC */ #define I2C_CST_PECFAULT_Pos 7 /*!< Error flag */ /* Bit field masks: */ #define I2C_CST_BB_Msk 0x00000001UL /*!< Flag employment bus */ #define I2C_CST_TOCDIV_Msk 0x00000006UL /*!< Coeff. div */ #define I2C_CST_TOERR_Msk 0x00000008UL /*!< Flag error simple bus */ #define I2C_CST_TSDA_Msk 0x00000010UL /*!< Bit test SDA */ #define I2C_CST_TGSCL_Msk 0x00000020UL /*!< Bit switch SCL */ #define I2C_CST_PECNEXT_Msk 0x00000040UL /*!< Bit control transmit CRC */ #define I2C_CST_PECFAULT_Msk 0x00000080UL /*!< Error flag */ /* Bit field enums: */ typedef enum { I2C_CST_TOCDIV_Disable = 0x0UL, /*!< disable clock */ I2C_CST_TOCDIV_Div4 = 0x1UL, /*!< clock divided by 4 */ I2C_CST_TOCDIV_Div8 = 0x2UL, /*!< clock divided by 8 */ I2C_CST_TOCDIV_Div16 = 0x3UL, /*!< clock divided by 16 */ } I2C_CST_TOCDIV_Enum; /*-- CTL0: Control register 0 --------------------------------------------------------------------------------*/ typedef struct { uint32_t START :1; /*!< Start bit */ uint32_t STOP :1; /*!< Stop bit */ uint32_t INTEN :1; /*!< Interrupt enable bit */ uint32_t :1; /*!< RESERVED */ uint32_t ACK :1; /*!< Acknowledgment bit reception */ uint32_t GCMEN :1; /*!< Control bit part a response to the general call address */ uint32_t SMBARE :1; /*!< Control bit part a response to the response address */ uint32_t CLRST :1; /*!< Bit reset flag interrupt */ } _I2C_CTL0_bits; /* Bit field positions: */ #define I2C_CTL0_START_Pos 0 /*!< Start bit */ #define I2C_CTL0_STOP_Pos 1 /*!< Stop bit */ #define I2C_CTL0_INTEN_Pos 2 /*!< Interrupt enable bit */ #define I2C_CTL0_ACK_Pos 4 /*!< Acknowledgment bit reception */ #define I2C_CTL0_GCMEN_Pos 5 /*!< Control bit part a response to the general call address */ #define I2C_CTL0_SMBARE_Pos 6 /*!< Control bit part a response to the response address */ #define I2C_CTL0_CLRST_Pos 7 /*!< Bit reset flag interrupt */ /* Bit field masks: */ #define I2C_CTL0_START_Msk 0x00000001UL /*!< Start bit */ #define I2C_CTL0_STOP_Msk 0x00000002UL /*!< Stop bit */ #define I2C_CTL0_INTEN_Msk 0x00000004UL /*!< Interrupt enable bit */ #define I2C_CTL0_ACK_Msk 0x00000010UL /*!< Acknowledgment bit reception */ #define I2C_CTL0_GCMEN_Msk 0x00000020UL /*!< Control bit part a response to the general call address */ #define I2C_CTL0_SMBARE_Msk 0x00000040UL /*!< Control bit part a response to the response address */ #define I2C_CTL0_CLRST_Msk 0x00000080UL /*!< Bit reset flag interrupt */ /*-- ADDR: Register own address ------------------------------------------------------------------------------*/ typedef struct { uint32_t ADDR :7; /*!< Own 7-bit address */ uint32_t SAEN :1; /*!< Enable bit address recognition */ } _I2C_ADDR_bits; /* Bit field positions: */ #define I2C_ADDR_ADDR_Pos 0 /*!< Own 7-bit address */ #define I2C_ADDR_SAEN_Pos 7 /*!< Enable bit address recognition */ /* Bit field masks: */ #define I2C_ADDR_ADDR_Msk 0x0000007FUL /*!< Own 7-bit address */ #define I2C_ADDR_SAEN_Msk 0x00000080UL /*!< Enable bit address recognition */ /*-- CTL1: Control register 1 --------------------------------------------------------------------------------*/ typedef struct { uint32_t ENABLE :1; /*!< Enable I2C */ uint32_t SCLFRQ :7; /*!< Field frequency selection signal at pin SCL in master mode (bits [6:0]) */ } _I2C_CTL1_bits; /* Bit field positions: */ #define I2C_CTL1_ENABLE_Pos 0 /*!< Enable I2C */ #define I2C_CTL1_SCLFRQ_Pos 1 /*!< Field frequency selection signal at pin SCL in master mode (bits [6:0]) */ /* Bit field masks: */ #define I2C_CTL1_ENABLE_Msk 0x00000001UL /*!< Enable I2C */ #define I2C_CTL1_SCLFRQ_Msk 0x000000FEUL /*!< Field frequency selection signal at pin SCL in master mode (bits [6:0]) */ /*-- TOPR: Prescaler load register ---------------------------------------------------------------------------*/ typedef struct { uint32_t SMBTOPR :8; /*!< Prescaler reload value field */ } _I2C_TOPR_bits; /* Bit field positions: */ #define I2C_TOPR_SMBTOPR_Pos 0 /*!< Prescaler reload value field */ /* Bit field masks: */ #define I2C_TOPR_SMBTOPR_Msk 0x000000FFUL /*!< Prescaler reload value field */ /*-- CTL2: Control register 2 --------------------------------------------------------------------------------*/ typedef struct { uint32_t S10ADR :3; /*!< Upper bits of 10-bit slave address */ uint32_t S10EN :1; /*!< Bit enabled 10-bit addressing slave */ uint32_t HSDIV :4; /*!< Field frequency selection signal at pin SCL in HS master mode (bits [3:0]) */ } _I2C_CTL2_bits; /* Bit field positions: */ #define I2C_CTL2_S10ADR_Pos 0 /*!< Upper bits of 10-bit slave address */ #define I2C_CTL2_S10EN_Pos 3 /*!< Bit enabled 10-bit addressing slave */ #define I2C_CTL2_HSDIV_Pos 4 /*!< Field frequency selection signal at pin SCL in HS master mode (bits [3:0]) */ /* Bit field masks: */ #define I2C_CTL2_S10ADR_Msk 0x00000007UL /*!< Upper bits of 10-bit slave address */ #define I2C_CTL2_S10EN_Msk 0x00000008UL /*!< Bit enabled 10-bit addressing slave */ #define I2C_CTL2_HSDIV_Msk 0x000000F0UL /*!< Field frequency selection signal at pin SCL in HS master mode (bits [3:0]) */ /*-- CTL3: Control register 3 --------------------------------------------------------------------------------*/ typedef struct { uint32_t SCLFRQ :8; /*!< Field frequency selection signal at pin SCL in master mode (bits [14:7]) */ } _I2C_CTL3_bits; /* Bit field positions: */ #define I2C_CTL3_SCLFRQ_Pos 0 /*!< Field frequency selection signal at pin SCL in master mode (bits [14:7]) */ /* Bit field masks: */ #define I2C_CTL3_SCLFRQ_Msk 0x000000FFUL /*!< Field frequency selection signal at pin SCL in master mode (bits [14:7]) */ /*-- CTL4: Control Register 4 --------------------------------------------------------------------------------*/ typedef struct { uint32_t HSDIV :8; /*!< Field frequency selection signal at pin SCL in HS master mode (bits [11:4]) */ } _I2C_CTL4_bits; /* Bit field positions: */ #define I2C_CTL4_HSDIV_Pos 0 /*!< Field frequency selection signal at pin SCL in HS master mode (bits [11:4]) */ /* Bit field masks: */ #define I2C_CTL4_HSDIV_Msk 0x000000FFUL /*!< Field frequency selection signal at pin SCL in HS master mode (bits [11:4]) */ typedef struct { union { /*!< Data register */ __IO uint32_t SDA; /*!< SDA : type used for word access */ __IO _I2C_SDA_bits SDA_bit; /*!< SDA_bit: structure used for bit access */ }; union { /*!< Status register */ __O uint32_t ST; /*!< ST : type used for word access */ __O _I2C_ST_bits ST_bit; /*!< ST_bit: structure used for bit access */ }; union { /*!< Status and control register */ __IO uint32_t CST; /*!< CST : type used for word access */ __IO _I2C_CST_bits CST_bit; /*!< CST_bit: structure used for bit access */ }; union { /*!< Control register 0 */ __IO uint32_t CTL0; /*!< CTL0 : type used for word access */ __IO _I2C_CTL0_bits CTL0_bit; /*!< CTL0_bit: structure used for bit access */ }; union { /*!< Register own address */ __IO uint32_t ADDR; /*!< ADDR : type used for word access */ __IO _I2C_ADDR_bits ADDR_bit; /*!< ADDR_bit: structure used for bit access */ }; union { /*!< Control register 1 */ __IO uint32_t CTL1; /*!< CTL1 : type used for word access */ __IO _I2C_CTL1_bits CTL1_bit; /*!< CTL1_bit: structure used for bit access */ }; union { /*!< Prescaler load register */ __IO uint32_t TOPR; /*!< TOPR : type used for word access */ __IO _I2C_TOPR_bits TOPR_bit; /*!< TOPR_bit: structure used for bit access */ }; union { /*!< Control register 2 */ __IO uint32_t CTL2; /*!< CTL2 : type used for word access */ __IO _I2C_CTL2_bits CTL2_bit; /*!< CTL2_bit: structure used for bit access */ }; union { /*!< Control register 3 */ __IO uint32_t CTL3; /*!< CTL3 : type used for word access */ __IO _I2C_CTL3_bits CTL3_bit; /*!< CTL3_bit: structure used for bit access */ }; union { /*!< Control Register 4 */ __IO uint32_t CTL4; /*!< CTL4 : type used for word access */ __IO _I2C_CTL4_bits CTL4_bit; /*!< CTL4_bit: structure used for bit access */ }; } I2C_TypeDef; /******************************************************************************/ /* ECAP registers */ /******************************************************************************/ /*-- TSCTR: Counter register ---------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Counter value */ } _ECAP_TSCTR_bits; /* Bit field positions: */ #define ECAP_TSCTR_VAL_Pos 0 /*!< Counter value */ /* Bit field masks: */ #define ECAP_TSCTR_VAL_Msk 0xFFFFFFFFUL /*!< Counter value */ /*-- CTRPHS: Counter Phase Sync register ---------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _ECAP_CTRPHS_bits; /* Bit field positions: */ #define ECAP_CTRPHS_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define ECAP_CTRPHS_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- CAP0: Capture register 0 --------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Capture 0 value */ } _ECAP_CAP0_bits; /* Bit field positions: */ #define ECAP_CAP0_VAL_Pos 0 /*!< Capture 0 value */ /* Bit field masks: */ #define ECAP_CAP0_VAL_Msk 0xFFFFFFFFUL /*!< Capture 0 value */ /*-- PRD: Period register ------------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Period value in APWM mode */ } _ECAP_PRD_bits; /* Bit field positions: */ #define ECAP_PRD_VAL_Pos 0 /*!< Period value in APWM mode */ /* Bit field masks: */ #define ECAP_PRD_VAL_Msk 0xFFFFFFFFUL /*!< Period value in APWM mode */ /*-- CAP1: Capture register 1 --------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Capture 1 value */ } _ECAP_CAP1_bits; /* Bit field positions: */ #define ECAP_CAP1_VAL_Pos 0 /*!< Capture 1 value */ /* Bit field masks: */ #define ECAP_CAP1_VAL_Msk 0xFFFFFFFFUL /*!< Capture 1 value */ /*-- CMP: Compare register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Compare value in APWM mode */ } _ECAP_CMP_bits; /* Bit field positions: */ #define ECAP_CMP_VAL_Pos 0 /*!< Compare value in APWM mode */ /* Bit field masks: */ #define ECAP_CMP_VAL_Msk 0xFFFFFFFFUL /*!< Compare value in APWM mode */ /*-- CAP2: Capture register 2 --------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Capture 2 value */ } _ECAP_CAP2_bits; /* Bit field positions: */ #define ECAP_CAP2_VAL_Pos 0 /*!< Capture 2 value */ /* Bit field masks: */ #define ECAP_CAP2_VAL_Msk 0xFFFFFFFFUL /*!< Capture 2 value */ /*-- PRDSHDW: Period shadow register -------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Period shadow value in APWM mode */ } _ECAP_PRDSHDW_bits; /* Bit field positions: */ #define ECAP_PRDSHDW_VAL_Pos 0 /*!< Period shadow value in APWM mode */ /* Bit field masks: */ #define ECAP_PRDSHDW_VAL_Msk 0xFFFFFFFFUL /*!< Period shadow value in APWM mode */ /*-- CAP3: Capture register 3 --------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Capture 3 value */ } _ECAP_CAP3_bits; /* Bit field positions: */ #define ECAP_CAP3_VAL_Pos 0 /*!< Capture 3 value */ /* Bit field masks: */ #define ECAP_CAP3_VAL_Msk 0xFFFFFFFFUL /*!< Capture 3 value */ /*-- CMPSHDW: Compare shadow register ------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Compare shadow value in APWM mode */ } _ECAP_CMPSHDW_bits; /* Bit field positions: */ #define ECAP_CMPSHDW_VAL_Pos 0 /*!< Compare shadow value in APWM mode */ /* Bit field masks: */ #define ECAP_CMPSHDW_VAL_Msk 0xFFFFFFFFUL /*!< Compare shadow value in APWM mode */ /*-- ECCTL0: Capture control register 0 ---------------------------------------------------------------------*/ typedef struct { uint32_t CAP0POL :1; /*!< Polarity select for capture 0 */ uint32_t CTRRST0 :1; /*!< Reset counter after event 0 */ uint32_t CAP1POL :1; /*!< Polarity select for capture 1 */ uint32_t CTRRST1 :1; /*!< Reset counter after event 1 */ uint32_t CAP2POL :1; /*!< Polarity select for capture 2 */ uint32_t CTRRST2 :1; /*!< Reset counter after event 2 */ uint32_t CAP3POL :1; /*!< Polarity select for capture 3 */ uint32_t CTRRST3 :1; /*!< Reset counter after event 3 */ uint32_t CAPLDEN :1; /*!< enable capture */ uint32_t PRESCALE :5; /*!< Prescaler value */ uint32_t FREESOFT :2; /*!< Emulation mode control */ } _ECAP_ECCTL0_bits; /* Bit field positions: */ #define ECAP_ECCTL0_CAP0POL_Pos 0 /*!< Polarity select for capture 0 */ #define ECAP_ECCTL0_CTRRST0_Pos 1 /*!< Reset counter after event 0 */ #define ECAP_ECCTL0_CAP1POL_Pos 2 /*!< Polarity select for capture 1 */ #define ECAP_ECCTL0_CTRRST1_Pos 3 /*!< Reset counter after event 1 */ #define ECAP_ECCTL0_CAP2POL_Pos 4 /*!< Polarity select for capture 2 */ #define ECAP_ECCTL0_CTRRST2_Pos 5 /*!< Reset counter after event 2 */ #define ECAP_ECCTL0_CAP3POL_Pos 6 /*!< Polarity select for capture 3 */ #define ECAP_ECCTL0_CTRRST3_Pos 7 /*!< Reset counter after event 3 */ #define ECAP_ECCTL0_CAPLDEN_Pos 8 /*!< enable capture */ #define ECAP_ECCTL0_PRESCALE_Pos 9 /*!< Prescaler value */ #define ECAP_ECCTL0_FREESOFT_Pos 14 /*!< Emulation mode control */ /* Bit field masks: */ #define ECAP_ECCTL0_CAP0POL_Msk 0x00000001UL /*!< Polarity select for capture 0 */ #define ECAP_ECCTL0_CTRRST0_Msk 0x00000002UL /*!< Reset counter after event 0 */ #define ECAP_ECCTL0_CAP1POL_Msk 0x00000004UL /*!< Polarity select for capture 1 */ #define ECAP_ECCTL0_CTRRST1_Msk 0x00000008UL /*!< Reset counter after event 1 */ #define ECAP_ECCTL0_CAP2POL_Msk 0x00000010UL /*!< Polarity select for capture 2 */ #define ECAP_ECCTL0_CTRRST2_Msk 0x00000020UL /*!< Reset counter after event 2 */ #define ECAP_ECCTL0_CAP3POL_Msk 0x00000040UL /*!< Polarity select for capture 3 */ #define ECAP_ECCTL0_CTRRST3_Msk 0x00000080UL /*!< Reset counter after event 3 */ #define ECAP_ECCTL0_CAPLDEN_Msk 0x00000100UL /*!< enable capture */ #define ECAP_ECCTL0_PRESCALE_Msk 0x00003E00UL /*!< Prescaler value */ #define ECAP_ECCTL0_FREESOFT_Msk 0x0000C000UL /*!< Emulation mode control */ /* Bit field enums: */ typedef enum { ECAP_ECCTL0_FREESOFT_Stop = 0x0UL, /*!< stop timer immedeatelly */ ECAP_ECCTL0_FREESOFT_StopAtZero = 0x1UL, /*!< stop timer when reach zero */ } ECAP_ECCTL0_FREESOFT_Enum; /*-- ECCTL1: Capture control register 1 ----------------------------------------------------------------------*/ typedef struct { uint32_t CONTOST :1; /*!< Capture mode */ uint32_t STOPWRAP :2; /*!< Stop compare value */ uint32_t REARM :1; /*!< Reset and enable controller, capture reg load */ uint32_t TSCTRSTOP :1; /*!< Enable Timer */ uint32_t SYNCIEN :1; /*!< Sync in enable */ uint32_t SYNCOSEL :2; /*!< SYNCO source selection */ uint32_t SWSYNC :1; /*!< Software timers sync */ uint32_t CAPAPWM :1; /*!< Capture mode or APWM mode */ uint32_t APWMPOL :1; /*!< High/low level APWM */ } _ECAP_ECCTL1_bits; /* Bit field positions: */ #define ECAP_ECCTL1_CONTOST_Pos 0 /*!< Capture mode */ #define ECAP_ECCTL1_STOPWRAP_Pos 1 /*!< Stop compare value */ #define ECAP_ECCTL1_REARM_Pos 3 /*!< Reset and enable controller, capture reg load */ #define ECAP_ECCTL1_TSCTRSTOP_Pos 4 /*!< Enable Timer */ #define ECAP_ECCTL1_SYNCIEN_Pos 5 /*!< Sync in enable */ #define ECAP_ECCTL1_SYNCOSEL_Pos 6 /*!< SYNCO source selection */ #define ECAP_ECCTL1_SWSYNC_Pos 8 /*!< Software timers sync */ #define ECAP_ECCTL1_CAPAPWM_Pos 9 /*!< Capture mode or APWM mode */ #define ECAP_ECCTL1_APWMPOL_Pos 10 /*!< High/low level APWM */ /* Bit field masks: */ #define ECAP_ECCTL1_CONTOST_Msk 0x00000001UL /*!< Capture mode */ #define ECAP_ECCTL1_STOPWRAP_Msk 0x00000006UL /*!< Stop compare value */ #define ECAP_ECCTL1_REARM_Msk 0x00000008UL /*!< Reset and enable controller, capture reg load */ #define ECAP_ECCTL1_TSCTRSTOP_Msk 0x00000010UL /*!< Enable Timer */ #define ECAP_ECCTL1_SYNCIEN_Msk 0x00000020UL /*!< Sync in enable */ #define ECAP_ECCTL1_SYNCOSEL_Msk 0x000000C0UL /*!< SYNCO source selection */ #define ECAP_ECCTL1_SWSYNC_Msk 0x00000100UL /*!< Software timers sync */ #define ECAP_ECCTL1_CAPAPWM_Msk 0x00000200UL /*!< Capture mode or APWM mode */ #define ECAP_ECCTL1_APWMPOL_Msk 0x00000400UL /*!< High/low level APWM */ /* Bit field enums: */ typedef enum { ECAP_ECCTL1_SYNCOSEL_Bypass = 0x0UL, /*!< sync in connected with sync out */ ECAP_ECCTL1_SYNCOSEL_CTREqPrd = 0x1UL, /*!< sync out generated when CTR = PRD */ ECAP_ECCTL1_SYNCOSEL_Disable = 0x2UL, /*!< sync out generate disabled */ } ECAP_ECCTL1_SYNCOSEL_Enum; /*-- ECEINT: Interrupt mask register -------------------------------------------------------------------------*/ typedef struct { uint32_t :1; /*!< RESERVED */ uint32_t CEVT0 :1; /*!< enable int CEVT0 */ uint32_t CEVT1 :1; /*!< enable int CEVT1 */ uint32_t CEVT2 :1; /*!< enable int CEVT2 */ uint32_t CEVT3 :1; /*!< enable int CEVT3 */ uint32_t CTROVF :1; /*!< enable int CTR_OVF */ uint32_t CTRPRD :1; /*!< enable int CTR=PRD */ uint32_t CTRCMP :1; /*!< enable int CTR=CMP */ } _ECAP_ECEINT_bits; /* Bit field positions: */ #define ECAP_ECEINT_CEVT0_Pos 1 /*!< enable int CEVT0 */ #define ECAP_ECEINT_CEVT1_Pos 2 /*!< enable int CEVT1 */ #define ECAP_ECEINT_CEVT2_Pos 3 /*!< enable int CEVT2 */ #define ECAP_ECEINT_CEVT3_Pos 4 /*!< enable int CEVT3 */ #define ECAP_ECEINT_CTROVF_Pos 5 /*!< enable int CTR_OVF */ #define ECAP_ECEINT_CTRPRD_Pos 6 /*!< enable int CTR=PRD */ #define ECAP_ECEINT_CTRCMP_Pos 7 /*!< enable int CTR=CMP */ /* Bit field masks: */ #define ECAP_ECEINT_CEVT0_Msk 0x00000002UL /*!< enable int CEVT0 */ #define ECAP_ECEINT_CEVT1_Msk 0x00000004UL /*!< enable int CEVT1 */ #define ECAP_ECEINT_CEVT2_Msk 0x00000008UL /*!< enable int CEVT2 */ #define ECAP_ECEINT_CEVT3_Msk 0x00000010UL /*!< enable int CEVT3 */ #define ECAP_ECEINT_CTROVF_Msk 0x00000020UL /*!< enable int CTR_OVF */ #define ECAP_ECEINT_CTRPRD_Msk 0x00000040UL /*!< enable int CTR=PRD */ #define ECAP_ECEINT_CTRCMP_Msk 0x00000080UL /*!< enable int CTR=CMP */ /*-- ECFLG: Interrupt status register ------------------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< indicate global interrupt */ uint32_t CEVT0 :1; /*!< Hap interrupt CEVT0 */ uint32_t CEVT1 :1; /*!< Hap interrupt CEVT1 */ uint32_t CEVT2 :1; /*!< Hap interrupt CEVT2 */ uint32_t CEVT3 :1; /*!< Hap interrupt CEVT3 */ uint32_t CTROVF :1; /*!< Hap interrupt CTROVF */ uint32_t CTRPRD :1; /*!< Hap interrupt CTR=PRD */ uint32_t CTRCMP :1; /*!< Hap interrupt CTR=CMP */ } _ECAP_ECFLG_bits; /* Bit field positions: */ #define ECAP_ECFLG_INT_Pos 0 /*!< indicate global interrupt */ #define ECAP_ECFLG_CEVT0_Pos 1 /*!< Hap interrupt CEVT0 */ #define ECAP_ECFLG_CEVT1_Pos 2 /*!< Hap interrupt CEVT1 */ #define ECAP_ECFLG_CEVT2_Pos 3 /*!< Hap interrupt CEVT2 */ #define ECAP_ECFLG_CEVT3_Pos 4 /*!< Hap interrupt CEVT3 */ #define ECAP_ECFLG_CTROVF_Pos 5 /*!< Hap interrupt CTROVF */ #define ECAP_ECFLG_CTRPRD_Pos 6 /*!< Hap interrupt CTR=PRD */ #define ECAP_ECFLG_CTRCMP_Pos 7 /*!< Hap interrupt CTR=CMP */ /* Bit field masks: */ #define ECAP_ECFLG_INT_Msk 0x00000001UL /*!< indicate global interrupt */ #define ECAP_ECFLG_CEVT0_Msk 0x00000002UL /*!< Hap interrupt CEVT0 */ #define ECAP_ECFLG_CEVT1_Msk 0x00000004UL /*!< Hap interrupt CEVT1 */ #define ECAP_ECFLG_CEVT2_Msk 0x00000008UL /*!< Hap interrupt CEVT2 */ #define ECAP_ECFLG_CEVT3_Msk 0x00000010UL /*!< Hap interrupt CEVT3 */ #define ECAP_ECFLG_CTROVF_Msk 0x00000020UL /*!< Hap interrupt CTROVF */ #define ECAP_ECFLG_CTRPRD_Msk 0x00000040UL /*!< Hap interrupt CTR=PRD */ #define ECAP_ECFLG_CTRCMP_Msk 0x00000080UL /*!< Hap interrupt CTR=CMP */ /*-- ECCLR: Clear interrupt register -------------------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< reset global interrupt */ uint32_t CEVT0 :1; /*!< reset intstatus */ uint32_t CEVT1 :1; /*!< reset intstatus */ uint32_t CEVT2 :1; /*!< reset intstatus */ uint32_t CEVT3 :1; /*!< reset intstatus */ uint32_t CTROVF :1; /*!< reset intstatus */ uint32_t CTRPRD :1; /*!< reset intstatus */ uint32_t CTRCMP :1; /*!< reset intstatus */ } _ECAP_ECCLR_bits; /* Bit field positions: */ #define ECAP_ECCLR_INT_Pos 0 /*!< reset global interrupt */ #define ECAP_ECCLR_CEVT0_Pos 1 /*!< reset intstatus */ #define ECAP_ECCLR_CEVT1_Pos 2 /*!< reset intstatus */ #define ECAP_ECCLR_CEVT2_Pos 3 /*!< reset intstatus */ #define ECAP_ECCLR_CEVT3_Pos 4 /*!< reset intstatus */ #define ECAP_ECCLR_CTROVF_Pos 5 /*!< reset intstatus */ #define ECAP_ECCLR_CTRPRD_Pos 6 /*!< reset intstatus */ #define ECAP_ECCLR_CTRCMP_Pos 7 /*!< reset intstatus */ /* Bit field masks: */ #define ECAP_ECCLR_INT_Msk 0x00000001UL /*!< reset global interrupt */ #define ECAP_ECCLR_CEVT0_Msk 0x00000002UL /*!< reset intstatus */ #define ECAP_ECCLR_CEVT1_Msk 0x00000004UL /*!< reset intstatus */ #define ECAP_ECCLR_CEVT2_Msk 0x00000008UL /*!< reset intstatus */ #define ECAP_ECCLR_CEVT3_Msk 0x00000010UL /*!< reset intstatus */ #define ECAP_ECCLR_CTROVF_Msk 0x00000020UL /*!< reset intstatus */ #define ECAP_ECCLR_CTRPRD_Msk 0x00000040UL /*!< reset intstatus */ #define ECAP_ECCLR_CTRCMP_Msk 0x00000080UL /*!< reset intstatus */ /*-- ECFRC: Force interrupt register -------------------------------------------------------------------------*/ typedef struct { uint32_t :1; /*!< RESERVED */ uint32_t CEVT0 :1; /*!< gen test interrupt */ uint32_t CEVT1 :1; /*!< gen test interrupt */ uint32_t CEVT2 :1; /*!< gen test interrupt */ uint32_t CEVT3 :1; /*!< gen test interrupt */ uint32_t CTROVF :1; /*!< gen test interrupt */ uint32_t CTRPRD :1; /*!< gen test interrupt */ uint32_t CTRCMP :1; /*!< gen test interrupt */ } _ECAP_ECFRC_bits; /* Bit field positions: */ #define ECAP_ECFRC_CEVT0_Pos 1 /*!< gen test interrupt */ #define ECAP_ECFRC_CEVT1_Pos 2 /*!< gen test interrupt */ #define ECAP_ECFRC_CEVT2_Pos 3 /*!< gen test interrupt */ #define ECAP_ECFRC_CEVT3_Pos 4 /*!< gen test interrupt */ #define ECAP_ECFRC_CTROVF_Pos 5 /*!< gen test interrupt */ #define ECAP_ECFRC_CTRPRD_Pos 6 /*!< gen test interrupt */ #define ECAP_ECFRC_CTRCMP_Pos 7 /*!< gen test interrupt */ /* Bit field masks: */ #define ECAP_ECFRC_CEVT0_Msk 0x00000002UL /*!< gen test interrupt */ #define ECAP_ECFRC_CEVT1_Msk 0x00000004UL /*!< gen test interrupt */ #define ECAP_ECFRC_CEVT2_Msk 0x00000008UL /*!< gen test interrupt */ #define ECAP_ECFRC_CEVT3_Msk 0x00000010UL /*!< gen test interrupt */ #define ECAP_ECFRC_CTROVF_Msk 0x00000020UL /*!< gen test interrupt */ #define ECAP_ECFRC_CTRPRD_Msk 0x00000040UL /*!< gen test interrupt */ #define ECAP_ECFRC_CTRCMP_Msk 0x00000080UL /*!< gen test interrupt */ /*-- PEINT: Active interrupt status register -----------------------------------------------------------------*/ typedef struct { uint32_t PEINT :1; /*!< active interrupt flag */ } _ECAP_PEINT_bits; /* Bit field positions: */ #define ECAP_PEINT_PEINT_Pos 0 /*!< active interrupt flag */ /* Bit field masks: */ #define ECAP_PEINT_PEINT_Msk 0x00000001UL /*!< active interrupt flag */ typedef struct { union { /*!< Counter register */ __IO uint32_t TSCTR; /*!< TSCTR : type used for word access */ __IO _ECAP_TSCTR_bits TSCTR_bit; /*!< TSCTR_bit: structure used for bit access */ }; union { /*!< Counter Phase Sync register */ __IO uint32_t CTRPHS; /*!< CTRPHS : type used for word access */ __IO _ECAP_CTRPHS_bits CTRPHS_bit; /*!< CTRPHS_bit: structure used for bit access */ }; union { union { /*!< Capture register 0 */ __IO uint32_t CAP0; /*!< CAP0 : type used for word access */ __IO _ECAP_CAP0_bits CAP0_bit; /*!< CAP0_bit: structure used for bit access */ }; struct { union { /*!< Period register */ __IO uint32_t PRD; /*!< PRD : type used for word access */ __IO _ECAP_PRD_bits PRD_bit; /*!< PRD_bit: structure used for bit access */ }; }; }; union { union { /*!< Capture register 1 */ __IO uint32_t CAP1; /*!< CAP1 : type used for word access */ __IO _ECAP_CAP1_bits CAP1_bit; /*!< CAP1_bit: structure used for bit access */ }; struct { union { /*!< Compare register */ __IO uint32_t CMP; /*!< CMP : type used for word access */ __IO _ECAP_CMP_bits CMP_bit; /*!< CMP_bit: structure used for bit access */ }; }; }; union { union { /*!< Capture register 2 */ __IO uint32_t CAP2; /*!< CAP2 : type used for word access */ __IO _ECAP_CAP2_bits CAP2_bit; /*!< CAP2_bit: structure used for bit access */ }; struct { union { /*!< Period shadow register */ __IO uint32_t PRDSHDW; /*!< PRDSHDW : type used for word access */ __IO _ECAP_PRDSHDW_bits PRDSHDW_bit; /*!< PRDSHDW_bit: structure used for bit access */ }; }; }; union { union { /*!< Capture register 3 */ __IO uint32_t CAP3; /*!< CAP3 : type used for word access */ __IO _ECAP_CAP3_bits CAP3_bit; /*!< CAP3_bit: structure used for bit access */ }; struct { union { /*!< Compare shadow register */ __IO uint32_t CMPSHDW; /*!< CMPSHDW : type used for word access */ __IO _ECAP_CMPSHDW_bits CMPSHDW_bit; /*!< CMPSHDW_bit: structure used for bit access */ }; }; }; __IO uint32_t Reserved0[4]; union { /*!< Capture control register 0 */ __IO uint32_t ECCTL0; /*!< ECCTL0 : type used for word access */ __IO _ECAP_ECCTL0_bits ECCTL0_bit; /*!< ECCTL0_bit: structure used for bit access */ }; union { /*!< Capture control register 1 */ __IO uint32_t ECCTL1; /*!< ECCTL1 : type used for word access */ __IO _ECAP_ECCTL1_bits ECCTL1_bit; /*!< ECCTL1_bit: structure used for bit access */ }; union { /*!< Interrupt mask register */ __IO uint32_t ECEINT; /*!< ECEINT : type used for word access */ __IO _ECAP_ECEINT_bits ECEINT_bit; /*!< ECEINT_bit: structure used for bit access */ }; union { /*!< Interrupt status register */ __I uint32_t ECFLG; /*!< ECFLG : type used for word access */ __I _ECAP_ECFLG_bits ECFLG_bit; /*!< ECFLG_bit: structure used for bit access */ }; union { /*!< Clear interrupt register */ __O uint32_t ECCLR; /*!< ECCLR : type used for word access */ __O _ECAP_ECCLR_bits ECCLR_bit; /*!< ECCLR_bit: structure used for bit access */ }; union { /*!< Force interrupt register */ __O uint32_t ECFRC; /*!< ECFRC : type used for word access */ __O _ECAP_ECFRC_bits ECFRC_bit; /*!< ECFRC_bit: structure used for bit access */ }; union { /*!< Active interrupt status register */ __IO uint32_t PEINT; /*!< PEINT : type used for word access */ __IO _ECAP_PEINT_bits PEINT_bit; /*!< PEINT_bit: structure used for bit access */ }; } ECAP_TypeDef; /******************************************************************************/ /* QEP registers */ /******************************************************************************/ /*-- QPOSCNT: Position Counter register ----------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QPOSCNT_bits; /* Bit field positions: */ #define QEP_QPOSCNT_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QPOSCNT_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- QPOSINIT: Position Counter Initialization register ------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QPOSINIT_bits; /* Bit field positions: */ #define QEP_QPOSINIT_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QPOSINIT_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- QPOSMAX: Maximum Position Count register ----------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QPOSMAX_bits; /* Bit field positions: */ #define QEP_QPOSMAX_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QPOSMAX_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- QPOSCMP: Position-compare register ----------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QPOSCMP_bits; /* Bit field positions: */ #define QEP_QPOSCMP_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QPOSCMP_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- QPOSILAT: Index Position Latch register -----------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QPOSILAT_bits; /* Bit field positions: */ #define QEP_QPOSILAT_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QPOSILAT_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- QPOSSLAT: Strobe Position Latch register ----------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QPOSSLAT_bits; /* Bit field positions: */ #define QEP_QPOSSLAT_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QPOSSLAT_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- QPOSLAT: Position Counter Latch register ----------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QPOSLAT_bits; /* Bit field positions: */ #define QEP_QPOSLAT_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QPOSLAT_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- QUTMR: Unit Timer register ------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QUTMR_bits; /* Bit field positions: */ #define QEP_QUTMR_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QUTMR_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- QUPRD: Unit Period register -----------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QUPRD_bits; /* Bit field positions: */ #define QEP_QUPRD_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QUPRD_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- QWDTMR: Watchdog Timer register -------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QWDTMR_bits; /* Bit field positions: */ #define QEP_QWDTMR_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QWDTMR_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- QWDPRD: Watchdog Period register ------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QWDPRD_bits; /* Bit field positions: */ #define QEP_QWDPRD_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QWDPRD_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- QDECCTL: Decoder Control register -----------------------------------------------------------------------*/ typedef struct { uint32_t :5; /*!< RESERVED */ uint32_t QSP :1; /*!< QEPS input polarity */ uint32_t QIP :1; /*!< QEPI input polarity */ uint32_t QBP :1; /*!< QEPB input polarity */ uint32_t QAP :1; /*!< QEPA input polarity */ uint32_t IGATE :1; /*!< Index pulse gating option */ uint32_t SWAP :1; /*!< Swap quadrature clock inputs */ uint32_t XCR :1; /*!< External clock rate */ uint32_t SPSEL :1; /*!< Sync output pin selection */ uint32_t SOEN :1; /*!< Sync output-enable */ uint32_t QSRC :2; /*!< Position-counter source selection */ } _QEP_QDECCTL_bits; /* Bit field positions: */ #define QEP_QDECCTL_QSP_Pos 5 /*!< QEPS input polarity */ #define QEP_QDECCTL_QIP_Pos 6 /*!< QEPI input polarity */ #define QEP_QDECCTL_QBP_Pos 7 /*!< QEPB input polarity */ #define QEP_QDECCTL_QAP_Pos 8 /*!< QEPA input polarity */ #define QEP_QDECCTL_IGATE_Pos 9 /*!< Index pulse gating option */ #define QEP_QDECCTL_SWAP_Pos 10 /*!< Swap quadrature clock inputs */ #define QEP_QDECCTL_XCR_Pos 11 /*!< External clock rate */ #define QEP_QDECCTL_SPSEL_Pos 12 /*!< Sync output pin selection */ #define QEP_QDECCTL_SOEN_Pos 13 /*!< Sync output-enable */ #define QEP_QDECCTL_QSRC_Pos 14 /*!< Position-counter source selection */ /* Bit field masks: */ #define QEP_QDECCTL_QSP_Msk 0x00000020UL /*!< QEPS input polarity */ #define QEP_QDECCTL_QIP_Msk 0x00000040UL /*!< QEPI input polarity */ #define QEP_QDECCTL_QBP_Msk 0x00000080UL /*!< QEPB input polarity */ #define QEP_QDECCTL_QAP_Msk 0x00000100UL /*!< QEPA input polarity */ #define QEP_QDECCTL_IGATE_Msk 0x00000200UL /*!< Index pulse gating option */ #define QEP_QDECCTL_SWAP_Msk 0x00000400UL /*!< Swap quadrature clock inputs */ #define QEP_QDECCTL_XCR_Msk 0x00000800UL /*!< External clock rate */ #define QEP_QDECCTL_SPSEL_Msk 0x00001000UL /*!< Sync output pin selection */ #define QEP_QDECCTL_SOEN_Msk 0x00002000UL /*!< Sync output-enable */ #define QEP_QDECCTL_QSRC_Msk 0x0000C000UL /*!< Position-counter source selection */ /* Bit field enums: */ typedef enum { QEP_QDECCTL_QSRC_Quad = 0x0UL, /*!< quadrature mode */ QEP_QDECCTL_QSRC_CountDir = 0x1UL, /*!< count/direction mode */ QEP_QDECCTL_QSRC_Up = 0x2UL, /*!< count up */ QEP_QDECCTL_QSRC_Down = 0x3UL, /*!< count down */ } QEP_QDECCTL_QSRC_Enum; /*-- QEPCTL: Control register --------------------------------------------------------------------------------*/ typedef struct { uint32_t WDE :1; /*!< QEP watchdog enable */ uint32_t UTE :1; /*!< QEP unit timer enable */ uint32_t QCLM :1; /*!< QEP capture latch mode */ uint32_t QPEN :1; /*!< Quadrature position counter enable/software reset */ uint32_t IEL :2; /*!< Index event latch of position counter (software index marker) */ uint32_t SEL :1; /*!< Strobe event latch of position counter */ uint32_t SWI :1; /*!< Software initialization of position counter */ uint32_t IEI :2; /*!< Index event initialization of position counter */ uint32_t SEI :2; /*!< Strobe event initialization of position counter */ uint32_t PCRM :2; /*!< Position counter reset mode */ uint32_t FREESOFT :2; /*!< Emulation Control Bits */ } _QEP_QEPCTL_bits; /* Bit field positions: */ #define QEP_QEPCTL_WDE_Pos 0 /*!< QEP watchdog enable */ #define QEP_QEPCTL_UTE_Pos 1 /*!< QEP unit timer enable */ #define QEP_QEPCTL_QCLM_Pos 2 /*!< QEP capture latch mode */ #define QEP_QEPCTL_QPEN_Pos 3 /*!< Quadrature position counter enable/software reset */ #define QEP_QEPCTL_IEL_Pos 4 /*!< Index event latch of position counter (software index marker) */ #define QEP_QEPCTL_SEL_Pos 6 /*!< Strobe event latch of position counter */ #define QEP_QEPCTL_SWI_Pos 7 /*!< Software initialization of position counter */ #define QEP_QEPCTL_IEI_Pos 8 /*!< Index event initialization of position counter */ #define QEP_QEPCTL_SEI_Pos 10 /*!< Strobe event initialization of position counter */ #define QEP_QEPCTL_PCRM_Pos 12 /*!< Position counter reset mode */ #define QEP_QEPCTL_FREESOFT_Pos 14 /*!< Emulation Control Bits */ /* Bit field masks: */ #define QEP_QEPCTL_WDE_Msk 0x00000001UL /*!< QEP watchdog enable */ #define QEP_QEPCTL_UTE_Msk 0x00000002UL /*!< QEP unit timer enable */ #define QEP_QEPCTL_QCLM_Msk 0x00000004UL /*!< QEP capture latch mode */ #define QEP_QEPCTL_QPEN_Msk 0x00000008UL /*!< Quadrature position counter enable/software reset */ #define QEP_QEPCTL_IEL_Msk 0x00000030UL /*!< Index event latch of position counter (software index marker) */ #define QEP_QEPCTL_SEL_Msk 0x00000040UL /*!< Strobe event latch of position counter */ #define QEP_QEPCTL_SWI_Msk 0x00000080UL /*!< Software initialization of position counter */ #define QEP_QEPCTL_IEI_Msk 0x00000300UL /*!< Index event initialization of position counter */ #define QEP_QEPCTL_SEI_Msk 0x00000C00UL /*!< Strobe event initialization of position counter */ #define QEP_QEPCTL_PCRM_Msk 0x00003000UL /*!< Position counter reset mode */ #define QEP_QEPCTL_FREESOFT_Msk 0x0000C000UL /*!< Emulation Control Bits */ /* Bit field enums: */ typedef enum { QEP_QEPCTL_IEL_NoLatch = 0x0UL, /*!< no position counter latch */ QEP_QEPCTL_IEL_IndPos = 0x1UL, /*!< latch on index signal posedge */ QEP_QEPCTL_IEL_IndNeg = 0x2UL, /*!< latch on index signal negedge */ QEP_QEPCTL_IEL_IndMark = 0x3UL, /*!< latch on index marker */ } QEP_QEPCTL_IEL_Enum; typedef enum { QEP_QEPCTL_IEI_NoInit = 0x0UL, /*!< no initialization */ QEP_QEPCTL_IEI_QEPIPos = 0x2UL, /*!< init on posedge QEPI */ QEP_QEPCTL_IEI_QEPINeg = 0x3UL, /*!< init on negedge QEPI */ } QEP_QEPCTL_IEI_Enum; typedef enum { QEP_QEPCTL_SEI_NoInit = 0x0UL, /*!< no initialization */ QEP_QEPCTL_SEI_QEPSPos = 0x2UL, /*!< init on posedge QEPI */ QEP_QEPCTL_SEI_QEPSDir = 0x3UL, /*!< init depends on direction - on posedge if direction is up, on negedge if direction is down */ } QEP_QEPCTL_SEI_Enum; typedef enum { QEP_QEPCTL_PCRM_Ind = 0x0UL, /*!< reset on index */ QEP_QEPCTL_PCRM_PosMax = 0x1UL, /*!< reset on max position count */ QEP_QEPCTL_PCRM_FirstInd = 0x2UL, /*!< reset on the first index */ QEP_QEPCTL_PCRM_Time = 0x3UL, /*!< reset on time counter */ } QEP_QEPCTL_PCRM_Enum; typedef enum { QEP_QEPCTL_FREESOFT_Stop = 0x0UL, /*!< counters are blocked */ QEP_QEPCTL_FREESOFT_StopAtOvf = 0x1UL, /*!< stop after overflow */ QEP_QEPCTL_FREESOFT_Free = 0x2UL, /*!< no count stop in debug mode */ } QEP_QEPCTL_FREESOFT_Enum; /*-- QCAPCTL: Capture Control register -----------------------------------------------------------------------*/ typedef struct { uint32_t UPPS :4; /*!< Unit position event prescaler */ uint32_t CCPS :3; /*!< QEP capture timer clock prescaler */ uint32_t SELEVENT :1; /*!< Reset timer control */ uint32_t :7; /*!< RESERVED */ uint32_t CEN :1; /*!< Enable eQEP capture */ uint32_t EPSLD :1; /*!< Enhanced prescalers load */ } _QEP_QCAPCTL_bits; /* Bit field positions: */ #define QEP_QCAPCTL_UPPS_Pos 0 /*!< Unit position event prescaler */ #define QEP_QCAPCTL_CCPS_Pos 4 /*!< QEP capture timer clock prescaler */ #define QEP_QCAPCTL_SELEVENT_Pos 7 /*!< Reset timer control */ #define QEP_QCAPCTL_CEN_Pos 15 /*!< Enable eQEP capture */ #define QEP_QCAPCTL_EPSLD_Pos 16 /*!< Enhanced prescalers load */ /* Bit field masks: */ #define QEP_QCAPCTL_UPPS_Msk 0x0000000FUL /*!< Unit position event prescaler */ #define QEP_QCAPCTL_CCPS_Msk 0x00000070UL /*!< QEP capture timer clock prescaler */ #define QEP_QCAPCTL_SELEVENT_Msk 0x00000080UL /*!< Reset timer control */ #define QEP_QCAPCTL_CEN_Msk 0x00008000UL /*!< Enable eQEP capture */ #define QEP_QCAPCTL_EPSLD_Msk 0x00010000UL /*!< Enhanced prescalers load */ /* Bit field enums: */ typedef enum { QEP_QCAPCTL_UPPS_Disable = 0x0UL, /*!< quad signal not divided */ QEP_QCAPCTL_UPPS_Div2 = 0x1UL, /*!< quad signal divided by 2 */ QEP_QCAPCTL_UPPS_Div4 = 0x2UL, /*!< quad signal divided by 4 */ QEP_QCAPCTL_UPPS_Div8 = 0x3UL, /*!< quad signal divided by 8 */ QEP_QCAPCTL_UPPS_Div16 = 0x4UL, /*!< quad signal divided by 16 */ QEP_QCAPCTL_UPPS_Div32 = 0x5UL, /*!< quad signal divided by 32 */ QEP_QCAPCTL_UPPS_Div64 = 0x6UL, /*!< quad signal divided by 64 */ QEP_QCAPCTL_UPPS_Div128 = 0x7UL, /*!< quad signal divided by 128 */ QEP_QCAPCTL_UPPS_Div256 = 0x8UL, /*!< quad signal divided by 256 */ QEP_QCAPCTL_UPPS_Div512 = 0x9UL, /*!< quad signal divided by 512 */ QEP_QCAPCTL_UPPS_Div1024 = 0xAUL, /*!< quad signal divided by 1024 */ QEP_QCAPCTL_UPPS_Div2048 = 0xBUL, /*!< quad signal divided by 2048 */ } QEP_QCAPCTL_UPPS_Enum; typedef enum { QEP_QCAPCTL_CCPS_Disable = 0x0UL, /*!< no divider */ QEP_QCAPCTL_CCPS_Div2 = 0x1UL, /*!< sysclk divided by 2 */ QEP_QCAPCTL_CCPS_Div4 = 0x2UL, /*!< sysclk divided by 4 */ QEP_QCAPCTL_CCPS_Div8 = 0x3UL, /*!< sysclk divided by 8 */ QEP_QCAPCTL_CCPS_Div16 = 0x4UL, /*!< sysclk divided by 16 */ QEP_QCAPCTL_CCPS_Div32 = 0x5UL, /*!< sysclk divided by 32 */ QEP_QCAPCTL_CCPS_Div64 = 0x6UL, /*!< sysclk divided by 64 */ QEP_QCAPCTL_CCPS_Div128 = 0x7UL, /*!< sysclk divided by 128 */ } QEP_QCAPCTL_CCPS_Enum; /*-- QPOSCTL: Position-compare Control register --------------------------------------------------------------*/ typedef struct { uint32_t PCSPW :12; /*!< Select-position-compare sync output pulse width */ uint32_t PCE :1; /*!< Position-compare enable/disable */ uint32_t PCPOL :1; /*!< Polarity of sync output */ uint32_t PCLOAD :1; /*!< Position-compare shadow load mode */ uint32_t PCSHDW :1; /*!< Position-compare shadow enable */ } _QEP_QPOSCTL_bits; /* Bit field positions: */ #define QEP_QPOSCTL_PCSPW_Pos 0 /*!< Select-position-compare sync output pulse width */ #define QEP_QPOSCTL_PCE_Pos 12 /*!< Position-compare enable/disable */ #define QEP_QPOSCTL_PCPOL_Pos 13 /*!< Polarity of sync output */ #define QEP_QPOSCTL_PCLOAD_Pos 14 /*!< Position-compare shadow load mode */ #define QEP_QPOSCTL_PCSHDW_Pos 15 /*!< Position-compare shadow enable */ /* Bit field masks: */ #define QEP_QPOSCTL_PCSPW_Msk 0x00000FFFUL /*!< Select-position-compare sync output pulse width */ #define QEP_QPOSCTL_PCE_Msk 0x00001000UL /*!< Position-compare enable/disable */ #define QEP_QPOSCTL_PCPOL_Msk 0x00002000UL /*!< Polarity of sync output */ #define QEP_QPOSCTL_PCLOAD_Msk 0x00004000UL /*!< Position-compare shadow load mode */ #define QEP_QPOSCTL_PCSHDW_Msk 0x00008000UL /*!< Position-compare shadow enable */ /*-- QEINT: Interrupt Enable register ------------------------------------------------------------------------*/ typedef struct { uint32_t :1; /*!< RESERVED */ uint32_t PCE :1; /*!< Position counter error interrupt enable */ uint32_t QPE :1; /*!< Quadrature phase error interrupt enable */ uint32_t QDC :1; /*!< Quadrature direction change interrupt enable */ uint32_t WTO :1; /*!< Watchdog time out interrupt enable */ uint32_t PCU :1; /*!< Position counter underflow interrupt enable */ uint32_t PCO :1; /*!< Position counter overflow interrupt enable */ uint32_t PCR :1; /*!< Position-compare ready interrupt enable */ uint32_t PCM :1; /*!< Position-compare match interrupt enable */ uint32_t SEL :1; /*!< Strobe event latch interrupt enable */ uint32_t IEL :1; /*!< Index event latch interrupt enable */ uint32_t UTO :1; /*!< Unit time out interrupt enable */ } _QEP_QEINT_bits; /* Bit field positions: */ #define QEP_QEINT_PCE_Pos 1 /*!< Position counter error interrupt enable */ #define QEP_QEINT_QPE_Pos 2 /*!< Quadrature phase error interrupt enable */ #define QEP_QEINT_QDC_Pos 3 /*!< Quadrature direction change interrupt enable */ #define QEP_QEINT_WTO_Pos 4 /*!< Watchdog time out interrupt enable */ #define QEP_QEINT_PCU_Pos 5 /*!< Position counter underflow interrupt enable */ #define QEP_QEINT_PCO_Pos 6 /*!< Position counter overflow interrupt enable */ #define QEP_QEINT_PCR_Pos 7 /*!< Position-compare ready interrupt enable */ #define QEP_QEINT_PCM_Pos 8 /*!< Position-compare match interrupt enable */ #define QEP_QEINT_SEL_Pos 9 /*!< Strobe event latch interrupt enable */ #define QEP_QEINT_IEL_Pos 10 /*!< Index event latch interrupt enable */ #define QEP_QEINT_UTO_Pos 11 /*!< Unit time out interrupt enable */ /* Bit field masks: */ #define QEP_QEINT_PCE_Msk 0x00000002UL /*!< Position counter error interrupt enable */ #define QEP_QEINT_QPE_Msk 0x00000004UL /*!< Quadrature phase error interrupt enable */ #define QEP_QEINT_QDC_Msk 0x00000008UL /*!< Quadrature direction change interrupt enable */ #define QEP_QEINT_WTO_Msk 0x00000010UL /*!< Watchdog time out interrupt enable */ #define QEP_QEINT_PCU_Msk 0x00000020UL /*!< Position counter underflow interrupt enable */ #define QEP_QEINT_PCO_Msk 0x00000040UL /*!< Position counter overflow interrupt enable */ #define QEP_QEINT_PCR_Msk 0x00000080UL /*!< Position-compare ready interrupt enable */ #define QEP_QEINT_PCM_Msk 0x00000100UL /*!< Position-compare match interrupt enable */ #define QEP_QEINT_SEL_Msk 0x00000200UL /*!< Strobe event latch interrupt enable */ #define QEP_QEINT_IEL_Msk 0x00000400UL /*!< Index event latch interrupt enable */ #define QEP_QEINT_UTO_Msk 0x00000800UL /*!< Unit time out interrupt enable */ /*-- QFLG: Interrupt Flag register ---------------------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< Global interrupt status flag */ uint32_t PCE :1; /*!< Position counter error interrupt flag */ uint32_t QPE :1; /*!< Quadrature phase error interrupt flag */ uint32_t QDC :1; /*!< Quadrature direction change interrupt flag */ uint32_t WTO :1; /*!< Watchdog timeout interrupt flag */ uint32_t PCU :1; /*!< Position counter underflow interrupt flag */ uint32_t PCO :1; /*!< Position counter overflow interrupt flag */ uint32_t PCR :1; /*!< Position-compare ready interrupt flag */ uint32_t PCM :1; /*!< QEP compare match event interrupt flag */ uint32_t SEL :1; /*!< Strobe event latch interrupt flag */ uint32_t IEL :1; /*!< Index event latch interrupt flag */ uint32_t UTO :1; /*!< Unit time out interrupt flag */ uint32_t :4; /*!< RESERVED */ uint32_t QFLGLAT :12; /*!< Latches QFLG[11:0] on every QPOSCNT read */ } _QEP_QFLG_bits; /* Bit field positions: */ #define QEP_QFLG_INT_Pos 0 /*!< Global interrupt status flag */ #define QEP_QFLG_PCE_Pos 1 /*!< Position counter error interrupt flag */ #define QEP_QFLG_QPE_Pos 2 /*!< Quadrature phase error interrupt flag */ #define QEP_QFLG_QDC_Pos 3 /*!< Quadrature direction change interrupt flag */ #define QEP_QFLG_WTO_Pos 4 /*!< Watchdog timeout interrupt flag */ #define QEP_QFLG_PCU_Pos 5 /*!< Position counter underflow interrupt flag */ #define QEP_QFLG_PCO_Pos 6 /*!< Position counter overflow interrupt flag */ #define QEP_QFLG_PCR_Pos 7 /*!< Position-compare ready interrupt flag */ #define QEP_QFLG_PCM_Pos 8 /*!< QEP compare match event interrupt flag */ #define QEP_QFLG_SEL_Pos 9 /*!< Strobe event latch interrupt flag */ #define QEP_QFLG_IEL_Pos 10 /*!< Index event latch interrupt flag */ #define QEP_QFLG_UTO_Pos 11 /*!< Unit time out interrupt flag */ #define QEP_QFLG_QFLGLAT_Pos 16 /*!< Latches QFLG[11:0] on every QPOSCNT read */ /* Bit field masks: */ #define QEP_QFLG_INT_Msk 0x00000001UL /*!< Global interrupt status flag */ #define QEP_QFLG_PCE_Msk 0x00000002UL /*!< Position counter error interrupt flag */ #define QEP_QFLG_QPE_Msk 0x00000004UL /*!< Quadrature phase error interrupt flag */ #define QEP_QFLG_QDC_Msk 0x00000008UL /*!< Quadrature direction change interrupt flag */ #define QEP_QFLG_WTO_Msk 0x00000010UL /*!< Watchdog timeout interrupt flag */ #define QEP_QFLG_PCU_Msk 0x00000020UL /*!< Position counter underflow interrupt flag */ #define QEP_QFLG_PCO_Msk 0x00000040UL /*!< Position counter overflow interrupt flag */ #define QEP_QFLG_PCR_Msk 0x00000080UL /*!< Position-compare ready interrupt flag */ #define QEP_QFLG_PCM_Msk 0x00000100UL /*!< QEP compare match event interrupt flag */ #define QEP_QFLG_SEL_Msk 0x00000200UL /*!< Strobe event latch interrupt flag */ #define QEP_QFLG_IEL_Msk 0x00000400UL /*!< Index event latch interrupt flag */ #define QEP_QFLG_UTO_Msk 0x00000800UL /*!< Unit time out interrupt flag */ #define QEP_QFLG_QFLGLAT_Msk 0x0FFF0000UL /*!< Latches QFLG[11:0] on every QPOSCNT read */ /*-- QCLR: Interrupt Clear register --------------------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< Global interrupt clear flag */ uint32_t PCE :1; /*!< Clear position counter error interrupt flag */ uint32_t QPE :1; /*!< Clear quadrature phase error interrupt flag */ uint32_t QDC :1; /*!< Clear quadrature direction change interrupt flag */ uint32_t WTO :1; /*!< Clear watchdog timeout interrupt flag */ uint32_t PCU :1; /*!< Clear position counter underflow interrupt flag */ uint32_t PCO :1; /*!< Clear position counter overflow interrupt flag */ uint32_t PCR :1; /*!< Clear position-compare ready interrupt flag */ uint32_t PCM :1; /*!< Clear eQEP compare match event interrupt flag */ uint32_t SEL :1; /*!< Clear strobe event latch interrupt flag */ uint32_t IEL :1; /*!< Clear index event latch interrupt flag */ uint32_t UTO :1; /*!< Clear unit time out interrupt flag */ } _QEP_QCLR_bits; /* Bit field positions: */ #define QEP_QCLR_INT_Pos 0 /*!< Global interrupt clear flag */ #define QEP_QCLR_PCE_Pos 1 /*!< Clear position counter error interrupt flag */ #define QEP_QCLR_QPE_Pos 2 /*!< Clear quadrature phase error interrupt flag */ #define QEP_QCLR_QDC_Pos 3 /*!< Clear quadrature direction change interrupt flag */ #define QEP_QCLR_WTO_Pos 4 /*!< Clear watchdog timeout interrupt flag */ #define QEP_QCLR_PCU_Pos 5 /*!< Clear position counter underflow interrupt flag */ #define QEP_QCLR_PCO_Pos 6 /*!< Clear position counter overflow interrupt flag */ #define QEP_QCLR_PCR_Pos 7 /*!< Clear position-compare ready interrupt flag */ #define QEP_QCLR_PCM_Pos 8 /*!< Clear eQEP compare match event interrupt flag */ #define QEP_QCLR_SEL_Pos 9 /*!< Clear strobe event latch interrupt flag */ #define QEP_QCLR_IEL_Pos 10 /*!< Clear index event latch interrupt flag */ #define QEP_QCLR_UTO_Pos 11 /*!< Clear unit time out interrupt flag */ /* Bit field masks: */ #define QEP_QCLR_INT_Msk 0x00000001UL /*!< Global interrupt clear flag */ #define QEP_QCLR_PCE_Msk 0x00000002UL /*!< Clear position counter error interrupt flag */ #define QEP_QCLR_QPE_Msk 0x00000004UL /*!< Clear quadrature phase error interrupt flag */ #define QEP_QCLR_QDC_Msk 0x00000008UL /*!< Clear quadrature direction change interrupt flag */ #define QEP_QCLR_WTO_Msk 0x00000010UL /*!< Clear watchdog timeout interrupt flag */ #define QEP_QCLR_PCU_Msk 0x00000020UL /*!< Clear position counter underflow interrupt flag */ #define QEP_QCLR_PCO_Msk 0x00000040UL /*!< Clear position counter overflow interrupt flag */ #define QEP_QCLR_PCR_Msk 0x00000080UL /*!< Clear position-compare ready interrupt flag */ #define QEP_QCLR_PCM_Msk 0x00000100UL /*!< Clear eQEP compare match event interrupt flag */ #define QEP_QCLR_SEL_Msk 0x00000200UL /*!< Clear strobe event latch interrupt flag */ #define QEP_QCLR_IEL_Msk 0x00000400UL /*!< Clear index event latch interrupt flag */ #define QEP_QCLR_UTO_Msk 0x00000800UL /*!< Clear unit time out interrupt flag */ /*-- QFRC: Interrupt Force register --------------------------------------------------------------------------*/ typedef struct { uint32_t :1; /*!< RESERVED */ uint32_t PCE :1; /*!< Force position counter error interrupt */ uint32_t QPE :1; /*!< Force quadrature phase error interrupt */ uint32_t QDC :1; /*!< Force quadrature direction change interrupt */ uint32_t WTO :1; /*!< Force watchdog time out interrupt */ uint32_t PCU :1; /*!< Force position counter underflow interrupt */ uint32_t PCO :1; /*!< Force position counter overflow interrupt */ uint32_t PCR :1; /*!< Force position-compare ready interrupt */ uint32_t PCM :1; /*!< Force position-compare match interrupt */ uint32_t SEL :1; /*!< Force strobe event latch interrupt */ uint32_t IEL :1; /*!< Force index event latch interrupt */ uint32_t UTO :1; /*!< Force unit time out interrupt */ } _QEP_QFRC_bits; /* Bit field positions: */ #define QEP_QFRC_PCE_Pos 1 /*!< Force position counter error interrupt */ #define QEP_QFRC_QPE_Pos 2 /*!< Force quadrature phase error interrupt */ #define QEP_QFRC_QDC_Pos 3 /*!< Force quadrature direction change interrupt */ #define QEP_QFRC_WTO_Pos 4 /*!< Force watchdog time out interrupt */ #define QEP_QFRC_PCU_Pos 5 /*!< Force position counter underflow interrupt */ #define QEP_QFRC_PCO_Pos 6 /*!< Force position counter overflow interrupt */ #define QEP_QFRC_PCR_Pos 7 /*!< Force position-compare ready interrupt */ #define QEP_QFRC_PCM_Pos 8 /*!< Force position-compare match interrupt */ #define QEP_QFRC_SEL_Pos 9 /*!< Force strobe event latch interrupt */ #define QEP_QFRC_IEL_Pos 10 /*!< Force index event latch interrupt */ #define QEP_QFRC_UTO_Pos 11 /*!< Force unit time out interrupt */ /* Bit field masks: */ #define QEP_QFRC_PCE_Msk 0x00000002UL /*!< Force position counter error interrupt */ #define QEP_QFRC_QPE_Msk 0x00000004UL /*!< Force quadrature phase error interrupt */ #define QEP_QFRC_QDC_Msk 0x00000008UL /*!< Force quadrature direction change interrupt */ #define QEP_QFRC_WTO_Msk 0x00000010UL /*!< Force watchdog time out interrupt */ #define QEP_QFRC_PCU_Msk 0x00000020UL /*!< Force position counter underflow interrupt */ #define QEP_QFRC_PCO_Msk 0x00000040UL /*!< Force position counter overflow interrupt */ #define QEP_QFRC_PCR_Msk 0x00000080UL /*!< Force position-compare ready interrupt */ #define QEP_QFRC_PCM_Msk 0x00000100UL /*!< Force position-compare match interrupt */ #define QEP_QFRC_SEL_Msk 0x00000200UL /*!< Force strobe event latch interrupt */ #define QEP_QFRC_IEL_Msk 0x00000400UL /*!< Force index event latch interrupt */ #define QEP_QFRC_UTO_Msk 0x00000800UL /*!< Force unit time out interrupt */ /*-- QEPSTS: Status register ---------------------------------------------------------------------------------*/ typedef struct { uint32_t PCEF :1; /*!< Position counter error flag */ uint32_t FIMF :1; /*!< First index marker flag */ uint32_t CDEF :1; /*!< Capture direction error flag */ uint32_t COEF :1; /*!< Capture overflow error flag */ uint32_t QDLF :1; /*!< QEP direction latch flag */ uint32_t QDF :1; /*!< Quadrature direction flag */ uint32_t FIDF :1; /*!< Direction on the first index marker */ uint32_t UPEVNT :1; /*!< Unit position event flag */ uint32_t DCF :1; /*!< Direction change flag */ } _QEP_QEPSTS_bits; /* Bit field positions: */ #define QEP_QEPSTS_PCEF_Pos 0 /*!< Position counter error flag */ #define QEP_QEPSTS_FIMF_Pos 1 /*!< First index marker flag */ #define QEP_QEPSTS_CDEF_Pos 2 /*!< Capture direction error flag */ #define QEP_QEPSTS_COEF_Pos 3 /*!< Capture overflow error flag */ #define QEP_QEPSTS_QDLF_Pos 4 /*!< QEP direction latch flag */ #define QEP_QEPSTS_QDF_Pos 5 /*!< Quadrature direction flag */ #define QEP_QEPSTS_FIDF_Pos 6 /*!< Direction on the first index marker */ #define QEP_QEPSTS_UPEVNT_Pos 7 /*!< Unit position event flag */ #define QEP_QEPSTS_DCF_Pos 8 /*!< Direction change flag */ /* Bit field masks: */ #define QEP_QEPSTS_PCEF_Msk 0x00000001UL /*!< Position counter error flag */ #define QEP_QEPSTS_FIMF_Msk 0x00000002UL /*!< First index marker flag */ #define QEP_QEPSTS_CDEF_Msk 0x00000004UL /*!< Capture direction error flag */ #define QEP_QEPSTS_COEF_Msk 0x00000008UL /*!< Capture overflow error flag */ #define QEP_QEPSTS_QDLF_Msk 0x00000010UL /*!< QEP direction latch flag */ #define QEP_QEPSTS_QDF_Msk 0x00000020UL /*!< Quadrature direction flag */ #define QEP_QEPSTS_FIDF_Msk 0x00000040UL /*!< Direction on the first index marker */ #define QEP_QEPSTS_UPEVNT_Msk 0x00000080UL /*!< Unit position event flag */ #define QEP_QEPSTS_DCF_Msk 0x00000100UL /*!< Direction change flag */ /*-- QCTMR: Capture Timer register ---------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QCTMR_bits; /* Bit field positions: */ #define QEP_QCTMR_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QCTMR_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- QCPRD: Capture Period register --------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QCPRD_bits; /* Bit field positions: */ #define QEP_QCPRD_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QCPRD_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- QCTMRLAT: Capture Timer Latch register ------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QCTMRLAT_bits; /* Bit field positions: */ #define QEP_QCTMRLAT_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QCTMRLAT_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- QCPRDLAT: Capture Period Latch register -----------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< */ } _QEP_QCPRDLAT_bits; /* Bit field positions: */ #define QEP_QCPRDLAT_VAL_Pos 0 /*!< */ /* Bit field masks: */ #define QEP_QCPRDLAT_VAL_Msk 0xFFFFFFFFUL /*!< */ /*-- DMAREQ: DMA request register ----------------------------------------------------------------------------*/ typedef struct { uint32_t DMAEN :1; /*!< DMA request enable */ } _QEP_DMAREQ_bits; /* Bit field positions: */ #define QEP_DMAREQ_DMAEN_Pos 0 /*!< DMA request enable */ /* Bit field masks: */ #define QEP_DMAREQ_DMAEN_Msk 0x00000001UL /*!< DMA request enable */ /*-- INTCLR: Clear active interrupt register -----------------------------------------------------------------*/ typedef struct { uint32_t INT :1; /*!< Active interrupt by read, write 1 to clear interrupt */ } _QEP_INTCLR_bits; /* Bit field positions: */ #define QEP_INTCLR_INT_Pos 0 /*!< Active interrupt by read, write 1 to clear interrupt */ /* Bit field masks: */ #define QEP_INTCLR_INT_Msk 0x00000001UL /*!< Active interrupt by read, write 1 to clear interrupt */ typedef struct { union { /*!< Position Counter register */ __IO uint32_t QPOSCNT; /*!< QPOSCNT : type used for word access */ __IO _QEP_QPOSCNT_bits QPOSCNT_bit; /*!< QPOSCNT_bit: structure used for bit access */ }; union { /*!< Position Counter Initialization register */ __IO uint32_t QPOSINIT; /*!< QPOSINIT : type used for word access */ __IO _QEP_QPOSINIT_bits QPOSINIT_bit; /*!< QPOSINIT_bit: structure used for bit access */ }; union { /*!< Maximum Position Count register */ __IO uint32_t QPOSMAX; /*!< QPOSMAX : type used for word access */ __IO _QEP_QPOSMAX_bits QPOSMAX_bit; /*!< QPOSMAX_bit: structure used for bit access */ }; union { /*!< Position-compare register */ __IO uint32_t QPOSCMP; /*!< QPOSCMP : type used for word access */ __IO _QEP_QPOSCMP_bits QPOSCMP_bit; /*!< QPOSCMP_bit: structure used for bit access */ }; union { /*!< Index Position Latch register */ __I uint32_t QPOSILAT; /*!< QPOSILAT : type used for word access */ __I _QEP_QPOSILAT_bits QPOSILAT_bit; /*!< QPOSILAT_bit: structure used for bit access */ }; union { /*!< Strobe Position Latch register */ __I uint32_t QPOSSLAT; /*!< QPOSSLAT : type used for word access */ __I _QEP_QPOSSLAT_bits QPOSSLAT_bit; /*!< QPOSSLAT_bit: structure used for bit access */ }; union { /*!< Position Counter Latch register */ __I uint32_t QPOSLAT; /*!< QPOSLAT : type used for word access */ __I _QEP_QPOSLAT_bits QPOSLAT_bit; /*!< QPOSLAT_bit: structure used for bit access */ }; union { /*!< Unit Timer register */ __IO uint32_t QUTMR; /*!< QUTMR : type used for word access */ __IO _QEP_QUTMR_bits QUTMR_bit; /*!< QUTMR_bit: structure used for bit access */ }; union { /*!< Unit Period register */ __IO uint32_t QUPRD; /*!< QUPRD : type used for word access */ __IO _QEP_QUPRD_bits QUPRD_bit; /*!< QUPRD_bit: structure used for bit access */ }; union { /*!< Watchdog Timer register */ __IO uint32_t QWDTMR; /*!< QWDTMR : type used for word access */ __IO _QEP_QWDTMR_bits QWDTMR_bit; /*!< QWDTMR_bit: structure used for bit access */ }; union { /*!< Watchdog Period register */ __IO uint32_t QWDPRD; /*!< QWDPRD : type used for word access */ __IO _QEP_QWDPRD_bits QWDPRD_bit; /*!< QWDPRD_bit: structure used for bit access */ }; union { /*!< Decoder Control register */ __IO uint32_t QDECCTL; /*!< QDECCTL : type used for word access */ __IO _QEP_QDECCTL_bits QDECCTL_bit; /*!< QDECCTL_bit: structure used for bit access */ }; union { /*!< Control register */ __IO uint32_t QEPCTL; /*!< QEPCTL : type used for word access */ __IO _QEP_QEPCTL_bits QEPCTL_bit; /*!< QEPCTL_bit: structure used for bit access */ }; union { /*!< Capture Control register */ __IO uint32_t QCAPCTL; /*!< QCAPCTL : type used for word access */ __IO _QEP_QCAPCTL_bits QCAPCTL_bit; /*!< QCAPCTL_bit: structure used for bit access */ }; union { /*!< Position-compare Control register */ __IO uint32_t QPOSCTL; /*!< QPOSCTL : type used for word access */ __IO _QEP_QPOSCTL_bits QPOSCTL_bit; /*!< QPOSCTL_bit: structure used for bit access */ }; union { /*!< Interrupt Enable register */ __IO uint32_t QEINT; /*!< QEINT : type used for word access */ __IO _QEP_QEINT_bits QEINT_bit; /*!< QEINT_bit: structure used for bit access */ }; union { /*!< Interrupt Flag register */ __I uint32_t QFLG; /*!< QFLG : type used for word access */ __I _QEP_QFLG_bits QFLG_bit; /*!< QFLG_bit: structure used for bit access */ }; union { /*!< Interrupt Clear register */ __O uint32_t QCLR; /*!< QCLR : type used for word access */ __O _QEP_QCLR_bits QCLR_bit; /*!< QCLR_bit: structure used for bit access */ }; union { /*!< Interrupt Force register */ __O uint32_t QFRC; /*!< QFRC : type used for word access */ __O _QEP_QFRC_bits QFRC_bit; /*!< QFRC_bit: structure used for bit access */ }; union { /*!< Status register */ __IO uint32_t QEPSTS; /*!< QEPSTS : type used for word access */ __IO _QEP_QEPSTS_bits QEPSTS_bit; /*!< QEPSTS_bit: structure used for bit access */ }; union { /*!< Capture Timer register */ __IO uint32_t QCTMR; /*!< QCTMR : type used for word access */ __IO _QEP_QCTMR_bits QCTMR_bit; /*!< QCTMR_bit: structure used for bit access */ }; union { /*!< Capture Period register */ __IO uint32_t QCPRD; /*!< QCPRD : type used for word access */ __IO _QEP_QCPRD_bits QCPRD_bit; /*!< QCPRD_bit: structure used for bit access */ }; union { /*!< Capture Timer Latch register */ __I uint32_t QCTMRLAT; /*!< QCTMRLAT : type used for word access */ __I _QEP_QCTMRLAT_bits QCTMRLAT_bit; /*!< QCTMRLAT_bit: structure used for bit access */ }; union { /*!< Capture Period Latch register */ __I uint32_t QCPRDLAT; /*!< QCPRDLAT : type used for word access */ __I _QEP_QCPRDLAT_bits QCPRDLAT_bit; /*!< QCPRDLAT_bit: structure used for bit access */ }; union { /*!< DMA request register */ __IO uint32_t DMAREQ; /*!< DMAREQ : type used for word access */ __IO _QEP_DMAREQ_bits DMAREQ_bit; /*!< DMAREQ_bit: structure used for bit access */ }; __IO uint32_t Reserved0[3]; union { /*!< Clear active interrupt register */ __IO uint32_t INTCLR; /*!< INTCLR : type used for word access */ __IO _QEP_INTCLR_bits INTCLR_bit; /*!< INTCLR_bit: structure used for bit access */ }; } QEP_TypeDef; /******************************************************************************/ /* MILSTD registers */ /******************************************************************************/ /*-- IR: BSI interrupt register ------------------------------------------------------------------------------*/ typedef struct { uint32_t BCEV :1; /*!< BC transfer event interrupt */ uint32_t BCD :1; /*!< BC DMA error */ uint32_t BCWK :1; /*!< BC timer interrupt */ uint32_t :5; /*!< RESERVED */ uint32_t RTEV :1; /*!< RT transfer event interrupt */ uint32_t RTD :1; /*!< RT DMA error */ uint32_t RTTE :1; /*!< RT table access error */ uint32_t :5; /*!< RESERVED */ uint32_t BMD :1; /*!< BM DMA error */ uint32_t BMTOF :1; /*!< BM timer overflow */ } _MILSTD_IR_bits; /* Bit field positions: */ #define MILSTD_IR_BCEV_Pos 0 /*!< BC transfer event interrupt */ #define MILSTD_IR_BCD_Pos 1 /*!< BC DMA error */ #define MILSTD_IR_BCWK_Pos 2 /*!< BC timer interrupt */ #define MILSTD_IR_RTEV_Pos 8 /*!< RT transfer event interrupt */ #define MILSTD_IR_RTD_Pos 9 /*!< RT DMA error */ #define MILSTD_IR_RTTE_Pos 10 /*!< RT table access error */ #define MILSTD_IR_BMD_Pos 16 /*!< BM DMA error */ #define MILSTD_IR_BMTOF_Pos 17 /*!< BM timer overflow */ /* Bit field masks: */ #define MILSTD_IR_BCEV_Msk 0x00000001UL /*!< BC transfer event interrupt */ #define MILSTD_IR_BCD_Msk 0x00000002UL /*!< BC DMA error */ #define MILSTD_IR_BCWK_Msk 0x00000004UL /*!< BC timer interrupt */ #define MILSTD_IR_RTEV_Msk 0x00000100UL /*!< RT transfer event interrupt */ #define MILSTD_IR_RTD_Msk 0x00000200UL /*!< RT DMA error */ #define MILSTD_IR_RTTE_Msk 0x00000400UL /*!< RT table access error */ #define MILSTD_IR_BMD_Msk 0x00010000UL /*!< BM DMA error */ #define MILSTD_IR_BMTOF_Msk 0x00020000UL /*!< BM timer overflow */ /*-- IENR: BSI interrupt enable register ---------------------------------------------------------------------*/ typedef struct { uint32_t BCEVE :1; /*!< BCEVE interrupt enable */ uint32_t BCDE :1; /*!< BCD interrupt enable */ uint32_t BCWKE :1; /*!< BCWK interrupt enable */ uint32_t :5; /*!< RESERVED */ uint32_t RTEVE :1; /*!< RTEV interrupt enable */ uint32_t RTDE :1; /*!< RTD interrupt enable */ uint32_t RTTEE :1; /*!< RTTE interrupt enable */ uint32_t :5; /*!< RESERVED */ uint32_t BMDE :1; /*!< BMD interrupt enable */ uint32_t BMTOE :1; /*!< BMTOF interrupt enable */ } _MILSTD_IENR_bits; /* Bit field positions: */ #define MILSTD_IENR_BCEVE_Pos 0 /*!< BCEVE interrupt enable */ #define MILSTD_IENR_BCDE_Pos 1 /*!< BCD interrupt enable */ #define MILSTD_IENR_BCWKE_Pos 2 /*!< BCWK interrupt enable */ #define MILSTD_IENR_RTEVE_Pos 8 /*!< RTEV interrupt enable */ #define MILSTD_IENR_RTDE_Pos 9 /*!< RTD interrupt enable */ #define MILSTD_IENR_RTTEE_Pos 10 /*!< RTTE interrupt enable */ #define MILSTD_IENR_BMDE_Pos 16 /*!< BMD interrupt enable */ #define MILSTD_IENR_BMTOE_Pos 17 /*!< BMTOF interrupt enable */ /* Bit field masks: */ #define MILSTD_IENR_BCEVE_Msk 0x00000001UL /*!< BCEVE interrupt enable */ #define MILSTD_IENR_BCDE_Msk 0x00000002UL /*!< BCD interrupt enable */ #define MILSTD_IENR_BCWKE_Msk 0x00000004UL /*!< BCWK interrupt enable */ #define MILSTD_IENR_RTEVE_Msk 0x00000100UL /*!< RTEV interrupt enable */ #define MILSTD_IENR_RTDE_Msk 0x00000200UL /*!< RTD interrupt enable */ #define MILSTD_IENR_RTTEE_Msk 0x00000400UL /*!< RTTE interrupt enable */ #define MILSTD_IENR_BMDE_Msk 0x00010000UL /*!< BMD interrupt enable */ #define MILSTD_IENR_BMTOE_Msk 0x00020000UL /*!< BMTOF interrupt enable */ /*-- HCON: BSI hardware configuration register ---------------------------------------------------------------*/ typedef struct { uint32_t CCFREQ :8; /*!< Codec clock frequency */ uint32_t SCLK :1; /*!< Same clock */ uint32_t ENDIAN :2; /*!< AHB Endianness */ uint32_t XKEYS :1; /*!< Enable safety keys */ uint32_t :19; /*!< RESERVED */ uint32_t MOD :1; /*!< Modified */ } _MILSTD_HCON_bits; /* Bit field positions: */ #define MILSTD_HCON_CCFREQ_Pos 0 /*!< Codec clock frequency */ #define MILSTD_HCON_SCLK_Pos 8 /*!< Same clock */ #define MILSTD_HCON_ENDIAN_Pos 9 /*!< AHB Endianness */ #define MILSTD_HCON_XKEYS_Pos 11 /*!< Enable safety keys */ #define MILSTD_HCON_MOD_Pos 31 /*!< Modified */ /* Bit field masks: */ #define MILSTD_HCON_CCFREQ_Msk 0x000000FFUL /*!< Codec clock frequency */ #define MILSTD_HCON_SCLK_Msk 0x00000100UL /*!< Same clock */ #define MILSTD_HCON_ENDIAN_Msk 0x00000600UL /*!< AHB Endianness */ #define MILSTD_HCON_XKEYS_Msk 0x00000800UL /*!< Enable safety keys */ #define MILSTD_HCON_MOD_Msk 0x80000000UL /*!< Modified */ /*-- BCSTCON: BC status and config register ------------------------------------------------------------------*/ typedef struct { uint32_t SCST :3; /*!< Schedule state */ uint32_t SCADL :5; /*!< Schedule address low bits */ uint32_t ASST :2; /*!< Asynchronous list state */ uint32_t :1; /*!< RESERVED */ uint32_t ASADL :5; /*!< Asynchronous list address low bits */ uint32_t BCCHK :1; /*!< Check broadcast */ uint32_t :11; /*!< RESERVED */ uint32_t BCFEAT :3; /*!< BC features */ uint32_t BCSUP :1; /*!< BC supported */ } _MILSTD_BCSTCON_bits; /* Bit field positions: */ #define MILSTD_BCSTCON_SCST_Pos 0 /*!< Schedule state */ #define MILSTD_BCSTCON_SCADL_Pos 3 /*!< Schedule address low bits */ #define MILSTD_BCSTCON_ASST_Pos 8 /*!< Asynchronous list state */ #define MILSTD_BCSTCON_ASADL_Pos 11 /*!< Asynchronous list address low bits */ #define MILSTD_BCSTCON_BCCHK_Pos 16 /*!< Check broadcast */ #define MILSTD_BCSTCON_BCFEAT_Pos 28 /*!< BC features */ #define MILSTD_BCSTCON_BCSUP_Pos 31 /*!< BC supported */ /* Bit field masks: */ #define MILSTD_BCSTCON_SCST_Msk 0x00000007UL /*!< Schedule state */ #define MILSTD_BCSTCON_SCADL_Msk 0x000000F8UL /*!< Schedule address low bits */ #define MILSTD_BCSTCON_ASST_Msk 0x00000300UL /*!< Asynchronous list state */ #define MILSTD_BCSTCON_ASADL_Msk 0x0000F800UL /*!< Asynchronous list address low bits */ #define MILSTD_BCSTCON_BCCHK_Msk 0x00010000UL /*!< Check broadcast */ #define MILSTD_BCSTCON_BCFEAT_Msk 0x70000000UL /*!< BC features */ #define MILSTD_BCSTCON_BCSUP_Msk 0x80000000UL /*!< BC supported */ /*-- BCACT: BC action register -------------------------------------------------------------------------------*/ typedef struct { uint32_t SCSRT :1; /*!< Schedule start */ uint32_t SCSUS :1; /*!< Schedule suspend */ uint32_t SCSTP :1; /*!< Schedule stop */ uint32_t SETT :1; /*!< Set external trigger */ uint32_t CLRT :1; /*!< Clear external trigger */ uint32_t :3; /*!< RESERVED */ uint32_t ASSRT :1; /*!< Asynchronous list start */ uint32_t ASSTP :1; /*!< Asynchronous list stop */ uint32_t :6; /*!< RESERVED */ uint32_t BCKEY :16; /*!< BC safety code */ } _MILSTD_BCACT_bits; /* Bit field positions: */ #define MILSTD_BCACT_SCSRT_Pos 0 /*!< Schedule start */ #define MILSTD_BCACT_SCSUS_Pos 1 /*!< Schedule suspend */ #define MILSTD_BCACT_SCSTP_Pos 2 /*!< Schedule stop */ #define MILSTD_BCACT_SETT_Pos 3 /*!< Set external trigger */ #define MILSTD_BCACT_CLRT_Pos 4 /*!< Clear external trigger */ #define MILSTD_BCACT_ASSRT_Pos 8 /*!< Asynchronous list start */ #define MILSTD_BCACT_ASSTP_Pos 9 /*!< Asynchronous list stop */ #define MILSTD_BCACT_BCKEY_Pos 16 /*!< BC safety code */ /* Bit field masks: */ #define MILSTD_BCACT_SCSRT_Msk 0x00000001UL /*!< Schedule start */ #define MILSTD_BCACT_SCSUS_Msk 0x00000002UL /*!< Schedule suspend */ #define MILSTD_BCACT_SCSTP_Msk 0x00000004UL /*!< Schedule stop */ #define MILSTD_BCACT_SETT_Msk 0x00000008UL /*!< Set external trigger */ #define MILSTD_BCACT_CLRT_Msk 0x00000010UL /*!< Clear external trigger */ #define MILSTD_BCACT_ASSRT_Msk 0x00000100UL /*!< Asynchronous list start */ #define MILSTD_BCACT_ASSTP_Msk 0x00000200UL /*!< Asynchronous list stop */ #define MILSTD_BCACT_BCKEY_Msk 0xFFFF0000UL /*!< BC safety code */ /* Bit field enums: */ typedef enum { MILSTD_BCACT_BCKEY_Code = 0x1552UL, /*!< BC safety code */ } MILSTD_BCACT_BCKEY_Enum; /*-- BCLNP: BC transfer list next pointer --------------------------------------------------------------------*/ typedef struct { uint32_t SCTLP :32; /*!< Schedule transfer list pointer */ } _MILSTD_BCLNP_bits; /* Bit field positions: */ #define MILSTD_BCLNP_SCTLP_Pos 0 /*!< Schedule transfer list pointer */ /* Bit field masks: */ #define MILSTD_BCLNP_SCTLP_Msk 0xFFFFFFFFUL /*!< Schedule transfer list pointer */ /*-- BCALNP: BC asynchronous list next pointer register ------------------------------------------------------*/ typedef struct { uint32_t ASLP :32; /*!< Asynchronous list pointer */ } _MILSTD_BCALNP_bits; /* Bit field positions: */ #define MILSTD_BCALNP_ASLP_Pos 0 /*!< Asynchronous list pointer */ /* Bit field masks: */ #define MILSTD_BCALNP_ASLP_Msk 0xFFFFFFFFUL /*!< Asynchronous list pointer */ /*-- BCTIM: BC timer register --------------------------------------------------------------------------------*/ typedef struct { uint32_t SCTM :24; /*!< Schedule time */ } _MILSTD_BCTIM_bits; /* Bit field positions: */ #define MILSTD_BCTIM_SCTM_Pos 0 /*!< Schedule time */ /* Bit field masks: */ #define MILSTD_BCTIM_SCTM_Msk 0x00FFFFFFUL /*!< Schedule time */ /*-- BCTIMWK: BC timer wake-up register ----------------------------------------------------------------------*/ typedef struct { uint32_t WKTM :24; /*!< Wake-up time */ uint32_t :7; /*!< RESERVED */ uint32_t WKEN :1; /*!< Wake-up timer enable */ } _MILSTD_BCTIMWK_bits; /* Bit field positions: */ #define MILSTD_BCTIMWK_WKTM_Pos 0 /*!< Wake-up time */ #define MILSTD_BCTIMWK_WKEN_Pos 31 /*!< Wake-up timer enable */ /* Bit field masks: */ #define MILSTD_BCTIMWK_WKTM_Msk 0x00FFFFFFUL /*!< Wake-up time */ #define MILSTD_BCTIMWK_WKEN_Msk 0x80000000UL /*!< Wake-up timer enable */ /*-- BCTRP: BC transfer-triggered IRQ ring position register -------------------------------------------------*/ typedef struct { uint32_t SPRP :32; /*!< BC IRQ source pointer ring position */ } _MILSTD_BCTRP_bits; /* Bit field positions: */ #define MILSTD_BCTRP_SPRP_Pos 0 /*!< BC IRQ source pointer ring position */ /* Bit field masks: */ #define MILSTD_BCTRP_SPRP_Msk 0xFFFFFFFFUL /*!< BC IRQ source pointer ring position */ /*-- BCBSW: BC per-RT bus swap register ----------------------------------------------------------------------*/ typedef struct { uint32_t BPRBS :32; /*!< BC per-RT bus swap */ } _MILSTD_BCBSW_bits; /* Bit field positions: */ #define MILSTD_BCBSW_BPRBS_Pos 0 /*!< BC per-RT bus swap */ /* Bit field masks: */ #define MILSTD_BCBSW_BPRBS_Msk 0xFFFFFFFFUL /*!< BC per-RT bus swap */ /*-- BCTSP: BC transfer list current slot pointer ------------------------------------------------------------*/ typedef struct { uint32_t TSP :32; /*!< BC transfer slot pointer */ } _MILSTD_BCTSP_bits; /* Bit field positions: */ #define MILSTD_BCTSP_TSP_Pos 0 /*!< BC transfer slot pointer */ /* Bit field masks: */ #define MILSTD_BCTSP_TSP_Msk 0xFFFFFFFFUL /*!< BC transfer slot pointer */ /*-- BCATSP: BC asynchronous list current slot pointer -------------------------------------------------------*/ typedef struct { uint32_t ATSP :32; /*!< BC asynchronous transfer slot pointer */ } _MILSTD_BCATSP_bits; /* Bit field positions: */ #define MILSTD_BCATSP_ATSP_Pos 0 /*!< BC asynchronous transfer slot pointer */ /* Bit field masks: */ #define MILSTD_BCATSP_ATSP_Msk 0xFFFFFFFFUL /*!< BC asynchronous transfer slot pointer */ /*-- RTSTAT: RT status register ------------------------------------------------------------------------------*/ typedef struct { uint32_t RUN :1; /*!< RT running */ uint32_t SHDB :1; /*!< Bus B shutdown */ uint32_t SHDA :1; /*!< Bus A shutdown */ uint32_t ACT :1; /*!< RT active */ uint32_t :27; /*!< RESERVED */ uint32_t RTSUP :1; /*!< RT supported */ } _MILSTD_RTSTAT_bits; /* Bit field positions: */ #define MILSTD_RTSTAT_RUN_Pos 0 /*!< RT running */ #define MILSTD_RTSTAT_SHDB_Pos 1 /*!< Bus B shutdown */ #define MILSTD_RTSTAT_SHDA_Pos 2 /*!< Bus A shutdown */ #define MILSTD_RTSTAT_ACT_Pos 3 /*!< RT active */ #define MILSTD_RTSTAT_RTSUP_Pos 31 /*!< RT supported */ /* Bit field masks: */ #define MILSTD_RTSTAT_RUN_Msk 0x00000001UL /*!< RT running */ #define MILSTD_RTSTAT_SHDB_Msk 0x00000002UL /*!< Bus B shutdown */ #define MILSTD_RTSTAT_SHDA_Msk 0x00000004UL /*!< Bus A shutdown */ #define MILSTD_RTSTAT_ACT_Msk 0x00000008UL /*!< RT active */ #define MILSTD_RTSTAT_RTSUP_Msk 0x80000000UL /*!< RT supported */ /*-- RTCON: RT config register -------------------------------------------------------------------------------*/ typedef struct { uint32_t RTEN :1; /*!< RT enable */ uint32_t RTADDR :5; /*!< RT address */ uint32_t RTEIS :1; /*!< external RT address set */ uint32_t :6; /*!< RESERVED */ uint32_t BRS :1; /*!< Bus reset enable */ uint32_t SYDS :1; /*!< Sync with data enable */ uint32_t SYS :1; /*!< Sync enable */ uint32_t RTKEY :16; /*!< RT safety code */ } _MILSTD_RTCON_bits; /* Bit field positions: */ #define MILSTD_RTCON_RTEN_Pos 0 /*!< RT enable */ #define MILSTD_RTCON_RTADDR_Pos 1 /*!< RT address */ #define MILSTD_RTCON_RTEIS_Pos 6 /*!< external RT address set */ #define MILSTD_RTCON_BRS_Pos 13 /*!< Bus reset enable */ #define MILSTD_RTCON_SYDS_Pos 14 /*!< Sync with data enable */ #define MILSTD_RTCON_SYS_Pos 15 /*!< Sync enable */ #define MILSTD_RTCON_RTKEY_Pos 16 /*!< RT safety code */ /* Bit field masks: */ #define MILSTD_RTCON_RTEN_Msk 0x00000001UL /*!< RT enable */ #define MILSTD_RTCON_RTADDR_Msk 0x0000003EUL /*!< RT address */ #define MILSTD_RTCON_RTEIS_Msk 0x00000040UL /*!< external RT address set */ #define MILSTD_RTCON_BRS_Msk 0x00002000UL /*!< Bus reset enable */ #define MILSTD_RTCON_SYDS_Msk 0x00004000UL /*!< Sync with data enable */ #define MILSTD_RTCON_SYS_Msk 0x00008000UL /*!< Sync enable */ #define MILSTD_RTCON_RTKEY_Msk 0xFFFF0000UL /*!< RT safety code */ /* Bit field enums: */ typedef enum { MILSTD_RTCON_RTKEY_Code = 0x1553UL, /*!< RT safety code */ } MILSTD_RTCON_RTKEY_Enum; /*-- RTBST: RT bus status register ---------------------------------------------------------------------------*/ typedef struct { uint32_t TFLG :1; /*!< Terminal flag */ uint32_t DBCA :1; /*!< Dynamic BC acceptance */ uint32_t SSF :1; /*!< Subsystem flag */ uint32_t BUSY :1; /*!< Busy bit */ uint32_t SREQ :1; /*!< Service request */ uint32_t :3; /*!< RESERVED */ uint32_t TFDE :1; /*!< Set terminal flag */ } _MILSTD_RTBST_bits; /* Bit field positions: */ #define MILSTD_RTBST_TFLG_Pos 0 /*!< Terminal flag */ #define MILSTD_RTBST_DBCA_Pos 1 /*!< Dynamic BC acceptance */ #define MILSTD_RTBST_SSF_Pos 2 /*!< Subsystem flag */ #define MILSTD_RTBST_BUSY_Pos 3 /*!< Busy bit */ #define MILSTD_RTBST_SREQ_Pos 4 /*!< Service request */ #define MILSTD_RTBST_TFDE_Pos 8 /*!< Set terminal flag */ /* Bit field masks: */ #define MILSTD_RTBST_TFLG_Msk 0x00000001UL /*!< Terminal flag */ #define MILSTD_RTBST_DBCA_Msk 0x00000002UL /*!< Dynamic BC acceptance */ #define MILSTD_RTBST_SSF_Msk 0x00000004UL /*!< Subsystem flag */ #define MILSTD_RTBST_BUSY_Msk 0x00000008UL /*!< Busy bit */ #define MILSTD_RTBST_SREQ_Msk 0x00000010UL /*!< Service request */ #define MILSTD_RTBST_TFDE_Msk 0x00000100UL /*!< Set terminal flag */ /*-- RTSW: RT status words register --------------------------------------------------------------------------*/ typedef struct { uint32_t VECW :16; /*!< Vector word */ uint32_t BITW :16; /*!< BIT Word */ } _MILSTD_RTSW_bits; /* Bit field positions: */ #define MILSTD_RTSW_VECW_Pos 0 /*!< Vector word */ #define MILSTD_RTSW_BITW_Pos 16 /*!< BIT Word */ /* Bit field masks: */ #define MILSTD_RTSW_VECW_Msk 0x0000FFFFUL /*!< Vector word */ #define MILSTD_RTSW_BITW_Msk 0xFFFF0000UL /*!< BIT Word */ /*-- RTSYNC: RT sync register --------------------------------------------------------------------------------*/ typedef struct { uint32_t SYD :16; /*!< RT sync data */ uint32_t SYTM :16; /*!< RT sync time */ } _MILSTD_RTSYNC_bits; /* Bit field positions: */ #define MILSTD_RTSYNC_SYD_Pos 0 /*!< RT sync data */ #define MILSTD_RTSYNC_SYTM_Pos 16 /*!< RT sync time */ /* Bit field masks: */ #define MILSTD_RTSYNC_SYD_Msk 0x0000FFFFUL /*!< RT sync data */ #define MILSTD_RTSYNC_SYTM_Msk 0xFFFF0000UL /*!< RT sync time */ /*-- RTSADDR: RT subaddress table base address ---------------------------------------------------------------*/ typedef struct { uint32_t :9; /*!< RESERVED */ uint32_t SATB :23; /*!< RT subaddress table base */ } _MILSTD_RTSADDR_bits; /* Bit field positions: */ #define MILSTD_RTSADDR_SATB_Pos 9 /*!< RT subaddress table base */ /* Bit field masks: */ #define MILSTD_RTSADDR_SATB_Msk 0xFFFFFE00UL /*!< RT subaddress table base */ /*-- RTMOD: RT mode control register -------------------------------------------------------------------------*/ typedef struct { uint32_t S :2; /*!< Syncronize */ uint32_t SB :2; /*!< Synchronize broadcast */ uint32_t SD :2; /*!< Synchronize with data word */ uint32_t SDB :2; /*!< Synchronize with data word broadcast */ uint32_t TS :2; /*!< Transmitter shutdown */ uint32_t TSB :2; /*!< Transmitter shutdown broadcast */ uint32_t TVW :2; /*!< Transmit vector word */ uint32_t TBW :2; /*!< Transmit BIT word */ uint32_t DBC :2; /*!< Dynamic bus control */ uint32_t IST :2; /*!< Initiate self test */ uint32_t ISTB :2; /*!< Initiate self test broadcast */ uint32_t ITF :2; /*!< Inhibit terminal flag */ uint32_t ITFB :2; /*!< Inhibit terminal flag broadcast */ uint32_t RRT :2; /*!< Reset RT */ uint32_t RRTB :2; /*!< reset RT broadcast */ } _MILSTD_RTMOD_bits; /* Bit field positions: */ #define MILSTD_RTMOD_S_Pos 0 /*!< Syncronize */ #define MILSTD_RTMOD_SB_Pos 2 /*!< Synchronize broadcast */ #define MILSTD_RTMOD_SD_Pos 4 /*!< Synchronize with data word */ #define MILSTD_RTMOD_SDB_Pos 6 /*!< Synchronize with data word broadcast */ #define MILSTD_RTMOD_TS_Pos 8 /*!< Transmitter shutdown */ #define MILSTD_RTMOD_TSB_Pos 10 /*!< Transmitter shutdown broadcast */ #define MILSTD_RTMOD_TVW_Pos 12 /*!< Transmit vector word */ #define MILSTD_RTMOD_TBW_Pos 14 /*!< Transmit BIT word */ #define MILSTD_RTMOD_DBC_Pos 16 /*!< Dynamic bus control */ #define MILSTD_RTMOD_IST_Pos 18 /*!< Initiate self test */ #define MILSTD_RTMOD_ISTB_Pos 20 /*!< Initiate self test broadcast */ #define MILSTD_RTMOD_ITF_Pos 22 /*!< Inhibit terminal flag */ #define MILSTD_RTMOD_ITFB_Pos 24 /*!< Inhibit terminal flag broadcast */ #define MILSTD_RTMOD_RRT_Pos 26 /*!< Reset RT */ #define MILSTD_RTMOD_RRTB_Pos 28 /*!< reset RT broadcast */ /* Bit field masks: */ #define MILSTD_RTMOD_S_Msk 0x00000003UL /*!< Syncronize */ #define MILSTD_RTMOD_SB_Msk 0x0000000CUL /*!< Synchronize broadcast */ #define MILSTD_RTMOD_SD_Msk 0x00000030UL /*!< Synchronize with data word */ #define MILSTD_RTMOD_SDB_Msk 0x000000C0UL /*!< Synchronize with data word broadcast */ #define MILSTD_RTMOD_TS_Msk 0x00000300UL /*!< Transmitter shutdown */ #define MILSTD_RTMOD_TSB_Msk 0x00000C00UL /*!< Transmitter shutdown broadcast */ #define MILSTD_RTMOD_TVW_Msk 0x00003000UL /*!< Transmit vector word */ #define MILSTD_RTMOD_TBW_Msk 0x0000C000UL /*!< Transmit BIT word */ #define MILSTD_RTMOD_DBC_Msk 0x00030000UL /*!< Dynamic bus control */ #define MILSTD_RTMOD_IST_Msk 0x000C0000UL /*!< Initiate self test */ #define MILSTD_RTMOD_ISTB_Msk 0x00300000UL /*!< Initiate self test broadcast */ #define MILSTD_RTMOD_ITF_Msk 0x00C00000UL /*!< Inhibit terminal flag */ #define MILSTD_RTMOD_ITFB_Msk 0x03000000UL /*!< Inhibit terminal flag broadcast */ #define MILSTD_RTMOD_RRT_Msk 0x0C000000UL /*!< Reset RT */ #define MILSTD_RTMOD_RRTB_Msk 0x30000000UL /*!< reset RT broadcast */ /*-- RTTIM: RT time tag control register ---------------------------------------------------------------------*/ typedef struct { uint32_t TVAL :16; /*!< Time tag value */ uint32_t TRES :16; /*!< Time tag resolution */ } _MILSTD_RTTIM_bits; /* Bit field positions: */ #define MILSTD_RTTIM_TVAL_Pos 0 /*!< Time tag value */ #define MILSTD_RTTIM_TRES_Pos 16 /*!< Time tag resolution */ /* Bit field masks: */ #define MILSTD_RTTIM_TVAL_Msk 0x0000FFFFUL /*!< Time tag value */ #define MILSTD_RTTIM_TRES_Msk 0xFFFF0000UL /*!< Time tag resolution */ /*-- RTELMSK: RT event log mask register ---------------------------------------------------------------------*/ typedef struct { uint32_t :2; /*!< RESERVED */ uint32_t ELSM :19; /*!< Event log size mask */ } _MILSTD_RTELMSK_bits; /* Bit field positions: */ #define MILSTD_RTELMSK_ELSM_Pos 2 /*!< Event log size mask */ /* Bit field masks: */ #define MILSTD_RTELMSK_ELSM_Msk 0x001FFFFCUL /*!< Event log size mask */ /*-- RTELP: RT event log position pointer --------------------------------------------------------------------*/ typedef struct { uint32_t ELWP :32; /*!< Event log write pointer */ } _MILSTD_RTELP_bits; /* Bit field positions: */ #define MILSTD_RTELP_ELWP_Pos 0 /*!< Event log write pointer */ /* Bit field masks: */ #define MILSTD_RTELP_ELWP_Msk 0xFFFFFFFFUL /*!< Event log write pointer */ /*-- RTELIP: RT event log interrupt position register --------------------------------------------------------*/ typedef struct { uint32_t ELIP :32; /*!< Event log irq pointer */ } _MILSTD_RTELIP_bits; /* Bit field positions: */ #define MILSTD_RTELIP_ELIP_Pos 0 /*!< Event log irq pointer */ /* Bit field masks: */ #define MILSTD_RTELIP_ELIP_Msk 0xFFFFFFFFUL /*!< Event log irq pointer */ /*-- BMSTAT: BM status register ------------------------------------------------------------------------------*/ typedef struct { uint32_t :30; /*!< RESERVED */ uint32_t KEYEN :1; /*!< Key enabled */ uint32_t BMSUP :1; /*!< BM supported */ } _MILSTD_BMSTAT_bits; /* Bit field positions: */ #define MILSTD_BMSTAT_KEYEN_Pos 30 /*!< Key enabled */ #define MILSTD_BMSTAT_BMSUP_Pos 31 /*!< BM supported */ /* Bit field masks: */ #define MILSTD_BMSTAT_KEYEN_Msk 0x40000000UL /*!< Key enabled */ #define MILSTD_BMSTAT_BMSUP_Msk 0x80000000UL /*!< BM supported */ /*-- BMCON: BM control register ------------------------------------------------------------------------------*/ typedef struct { uint32_t BMEN :1; /*!< BM enable */ uint32_t MANL :1; /*!< Manchester parity error log */ uint32_t UDWL :1; /*!< Unexpected data word log */ uint32_t IMCL :1; /*!< Invalid mode code log */ uint32_t EXST :1; /*!< External sync start */ uint32_t WRSTP :1; /*!< Wrap stop */ uint32_t :10; /*!< RESERVED */ uint32_t BMKEY :16; /*!< Safety key */ } _MILSTD_BMCON_bits; /* Bit field positions: */ #define MILSTD_BMCON_BMEN_Pos 0 /*!< BM enable */ #define MILSTD_BMCON_MANL_Pos 1 /*!< Manchester parity error log */ #define MILSTD_BMCON_UDWL_Pos 2 /*!< Unexpected data word log */ #define MILSTD_BMCON_IMCL_Pos 3 /*!< Invalid mode code log */ #define MILSTD_BMCON_EXST_Pos 4 /*!< External sync start */ #define MILSTD_BMCON_WRSTP_Pos 5 /*!< Wrap stop */ #define MILSTD_BMCON_BMKEY_Pos 16 /*!< Safety key */ /* Bit field masks: */ #define MILSTD_BMCON_BMEN_Msk 0x00000001UL /*!< BM enable */ #define MILSTD_BMCON_MANL_Msk 0x00000002UL /*!< Manchester parity error log */ #define MILSTD_BMCON_UDWL_Msk 0x00000004UL /*!< Unexpected data word log */ #define MILSTD_BMCON_IMCL_Msk 0x00000008UL /*!< Invalid mode code log */ #define MILSTD_BMCON_EXST_Msk 0x00000010UL /*!< External sync start */ #define MILSTD_BMCON_WRSTP_Msk 0x00000020UL /*!< Wrap stop */ #define MILSTD_BMCON_BMKEY_Msk 0xFFFF0000UL /*!< Safety key */ /* Bit field enums: */ typedef enum { MILSTD_BMCON_BMKEY_Code = 0x1554UL, /*!< BM safety code */ } MILSTD_BMCON_BMKEY_Enum; /*-- BMADF: BM RT address filter register --------------------------------------------------------------------*/ typedef struct { uint32_t AFM :32; /*!< Address filter mask */ } _MILSTD_BMADF_bits; /* Bit field positions: */ #define MILSTD_BMADF_AFM_Pos 0 /*!< Address filter mask */ /* Bit field masks: */ #define MILSTD_BMADF_AFM_Msk 0xFFFFFFFFUL /*!< Address filter mask */ /*-- BMSADF: BM RT subaddress filter register ----------------------------------------------------------------*/ typedef struct { uint32_t SAFM :32; /*!< Subaddress filter mask */ } _MILSTD_BMSADF_bits; /* Bit field positions: */ #define MILSTD_BMSADF_SAFM_Pos 0 /*!< Subaddress filter mask */ /* Bit field masks: */ #define MILSTD_BMSADF_SAFM_Msk 0xFFFFFFFFUL /*!< Subaddress filter mask */ /*-- BMMODF: BM RT mode code filter register -----------------------------------------------------------------*/ typedef struct { uint32_t S :1; /*!< Syncronize */ uint32_t SB :1; /*!< Syncronize broadcast */ uint32_t SD :1; /*!< Syncronize with data word */ uint32_t SDB :1; /*!< Syncronize with data word broadcast */ uint32_t TS :1; /*!< Transmitter shutdown */ uint32_t TSB :1; /*!< Transmitter shutdown broadcast */ uint32_t TVW :1; /*!< Transmit vector word */ uint32_t TBW :1; /*!< Transmit BIT word */ uint32_t DBC :1; /*!< Dynamic bus control */ uint32_t IST :1; /*!< Initiate self test */ uint32_t ISTB :1; /*!< Initiate self test broadcast */ uint32_t ITF :1; /*!< Inhibit terminal flag */ uint32_t ITFB :1; /*!< Inhibit termital flag broadcast */ uint32_t RRT :1; /*!< Reset RT */ uint32_t RRTB :1; /*!< Reset RT broadcast */ uint32_t TSW :1; /*!< Transmit status word */ uint32_t TLC :1; /*!< Transmit last command */ uint32_t STS :1; /*!< Selected transmitter shutdown */ uint32_t STSB :1; /*!< Selected transmitter shutdown broadcast */ } _MILSTD_BMMODF_bits; /* Bit field positions: */ #define MILSTD_BMMODF_S_Pos 0 /*!< Syncronize */ #define MILSTD_BMMODF_SB_Pos 1 /*!< Syncronize broadcast */ #define MILSTD_BMMODF_SD_Pos 2 /*!< Syncronize with data word */ #define MILSTD_BMMODF_SDB_Pos 3 /*!< Syncronize with data word broadcast */ #define MILSTD_BMMODF_TS_Pos 4 /*!< Transmitter shutdown */ #define MILSTD_BMMODF_TSB_Pos 5 /*!< Transmitter shutdown broadcast */ #define MILSTD_BMMODF_TVW_Pos 6 /*!< Transmit vector word */ #define MILSTD_BMMODF_TBW_Pos 7 /*!< Transmit BIT word */ #define MILSTD_BMMODF_DBC_Pos 8 /*!< Dynamic bus control */ #define MILSTD_BMMODF_IST_Pos 9 /*!< Initiate self test */ #define MILSTD_BMMODF_ISTB_Pos 10 /*!< Initiate self test broadcast */ #define MILSTD_BMMODF_ITF_Pos 11 /*!< Inhibit terminal flag */ #define MILSTD_BMMODF_ITFB_Pos 12 /*!< Inhibit termital flag broadcast */ #define MILSTD_BMMODF_RRT_Pos 13 /*!< Reset RT */ #define MILSTD_BMMODF_RRTB_Pos 14 /*!< Reset RT broadcast */ #define MILSTD_BMMODF_TSW_Pos 15 /*!< Transmit status word */ #define MILSTD_BMMODF_TLC_Pos 16 /*!< Transmit last command */ #define MILSTD_BMMODF_STS_Pos 17 /*!< Selected transmitter shutdown */ #define MILSTD_BMMODF_STSB_Pos 18 /*!< Selected transmitter shutdown broadcast */ /* Bit field masks: */ #define MILSTD_BMMODF_S_Msk 0x00000001UL /*!< Syncronize */ #define MILSTD_BMMODF_SB_Msk 0x00000002UL /*!< Syncronize broadcast */ #define MILSTD_BMMODF_SD_Msk 0x00000004UL /*!< Syncronize with data word */ #define MILSTD_BMMODF_SDB_Msk 0x00000008UL /*!< Syncronize with data word broadcast */ #define MILSTD_BMMODF_TS_Msk 0x00000010UL /*!< Transmitter shutdown */ #define MILSTD_BMMODF_TSB_Msk 0x00000020UL /*!< Transmitter shutdown broadcast */ #define MILSTD_BMMODF_TVW_Msk 0x00000040UL /*!< Transmit vector word */ #define MILSTD_BMMODF_TBW_Msk 0x00000080UL /*!< Transmit BIT word */ #define MILSTD_BMMODF_DBC_Msk 0x00000100UL /*!< Dynamic bus control */ #define MILSTD_BMMODF_IST_Msk 0x00000200UL /*!< Initiate self test */ #define MILSTD_BMMODF_ISTB_Msk 0x00000400UL /*!< Initiate self test broadcast */ #define MILSTD_BMMODF_ITF_Msk 0x00000800UL /*!< Inhibit terminal flag */ #define MILSTD_BMMODF_ITFB_Msk 0x00001000UL /*!< Inhibit termital flag broadcast */ #define MILSTD_BMMODF_RRT_Msk 0x00002000UL /*!< Reset RT */ #define MILSTD_BMMODF_RRTB_Msk 0x00004000UL /*!< Reset RT broadcast */ #define MILSTD_BMMODF_TSW_Msk 0x00008000UL /*!< Transmit status word */ #define MILSTD_BMMODF_TLC_Msk 0x00010000UL /*!< Transmit last command */ #define MILSTD_BMMODF_STS_Msk 0x00020000UL /*!< Selected transmitter shutdown */ #define MILSTD_BMMODF_STSB_Msk 0x00040000UL /*!< Selected transmitter shutdown broadcast */ /*-- BMLBS: BM log buffer start ------------------------------------------------------------------------------*/ typedef struct { uint32_t BMBS :32; /*!< BM log buffer start */ } _MILSTD_BMLBS_bits; /* Bit field positions: */ #define MILSTD_BMLBS_BMBS_Pos 0 /*!< BM log buffer start */ /* Bit field masks: */ #define MILSTD_BMLBS_BMBS_Msk 0xFFFFFFFFUL /*!< BM log buffer start */ /*-- BMLBE: BM log buffer end --------------------------------------------------------------------------------*/ typedef struct { uint32_t BMBE :22; /*!< BM log buffer end */ } _MILSTD_BMLBE_bits; /* Bit field positions: */ #define MILSTD_BMLBE_BMBE_Pos 0 /*!< BM log buffer end */ /* Bit field masks: */ #define MILSTD_BMLBE_BMBE_Msk 0x003FFFFFUL /*!< BM log buffer end */ /*-- BMLBP: BM log buffer position ---------------------------------------------------------------------------*/ typedef struct { uint32_t BMBP :22; /*!< BM log buffer position */ } _MILSTD_BMLBP_bits; /* Bit field positions: */ #define MILSTD_BMLBP_BMBP_Pos 0 /*!< BM log buffer position */ /* Bit field masks: */ #define MILSTD_BMLBP_BMBP_Msk 0x003FFFFFUL /*!< BM log buffer position */ /*-- BMTIM: BM time tag control register ---------------------------------------------------------------------*/ typedef struct { uint32_t BMTVAL :24; /*!< Time tag value */ uint32_t BMTRES :8; /*!< Time tag resolution */ } _MILSTD_BMTIM_bits; /* Bit field positions: */ #define MILSTD_BMTIM_BMTVAL_Pos 0 /*!< Time tag value */ #define MILSTD_BMTIM_BMTRES_Pos 24 /*!< Time tag resolution */ /* Bit field masks: */ #define MILSTD_BMTIM_BMTVAL_Msk 0x00FFFFFFUL /*!< Time tag value */ #define MILSTD_BMTIM_BMTRES_Msk 0xFF000000UL /*!< Time tag resolution */ typedef struct { union { /*!< BSI interrupt register */ __IO uint32_t IR; /*!< IR : type used for word access */ __IO _MILSTD_IR_bits IR_bit; /*!< IR_bit: structure used for bit access */ }; union { /*!< BSI interrupt enable register */ __IO uint32_t IENR; /*!< IENR : type used for word access */ __IO _MILSTD_IENR_bits IENR_bit; /*!< IENR_bit: structure used for bit access */ }; __IO uint32_t Reserved0[2]; union { /*!< BSI hardware configuration register */ __I uint32_t HCON; /*!< HCON : type used for word access */ __I _MILSTD_HCON_bits HCON_bit; /*!< HCON_bit: structure used for bit access */ }; __IO uint32_t Reserved1[11]; union { /*!< BC status and config register */ __IO uint32_t BCSTCON; /*!< BCSTCON : type used for word access */ __IO _MILSTD_BCSTCON_bits BCSTCON_bit; /*!< BCSTCON_bit: structure used for bit access */ }; union { /*!< BC action register */ __O uint32_t BCACT; /*!< BCACT : type used for word access */ __O _MILSTD_BCACT_bits BCACT_bit; /*!< BCACT_bit: structure used for bit access */ }; union { /*!< BC transfer list next pointer */ __IO uint32_t BCLNP; /*!< BCLNP : type used for word access */ __IO _MILSTD_BCLNP_bits BCLNP_bit; /*!< BCLNP_bit: structure used for bit access */ }; union { /*!< BC asynchronous list next pointer register */ __IO uint32_t BCALNP; /*!< BCALNP : type used for word access */ __IO _MILSTD_BCALNP_bits BCALNP_bit; /*!< BCALNP_bit: structure used for bit access */ }; union { /*!< BC timer register */ __I uint32_t BCTIM; /*!< BCTIM : type used for word access */ __I _MILSTD_BCTIM_bits BCTIM_bit; /*!< BCTIM_bit: structure used for bit access */ }; union { /*!< BC timer wake-up register */ __IO uint32_t BCTIMWK; /*!< BCTIMWK : type used for word access */ __IO _MILSTD_BCTIMWK_bits BCTIMWK_bit; /*!< BCTIMWK_bit: structure used for bit access */ }; union { /*!< BC transfer-triggered IRQ ring position register */ __IO uint32_t BCTRP; /*!< BCTRP : type used for word access */ __IO _MILSTD_BCTRP_bits BCTRP_bit; /*!< BCTRP_bit: structure used for bit access */ }; union { /*!< BC per-RT bus swap register */ __IO uint32_t BCBSW; /*!< BCBSW : type used for word access */ __IO _MILSTD_BCBSW_bits BCBSW_bit; /*!< BCBSW_bit: structure used for bit access */ }; __IO uint32_t Reserved2[2]; union { /*!< BC transfer list current slot pointer */ __I uint32_t BCTSP; /*!< BCTSP : type used for word access */ __I _MILSTD_BCTSP_bits BCTSP_bit; /*!< BCTSP_bit: structure used for bit access */ }; union { /*!< BC asynchronous list current slot pointer */ __I uint32_t BCATSP; /*!< BCATSP : type used for word access */ __I _MILSTD_BCATSP_bits BCATSP_bit; /*!< BCATSP_bit: structure used for bit access */ }; __IO uint32_t Reserved3[4]; union { /*!< RT status register */ __I uint32_t RTSTAT; /*!< RTSTAT : type used for word access */ __I _MILSTD_RTSTAT_bits RTSTAT_bit; /*!< RTSTAT_bit: structure used for bit access */ }; union { /*!< RT config register */ __IO uint32_t RTCON; /*!< RTCON : type used for word access */ __IO _MILSTD_RTCON_bits RTCON_bit; /*!< RTCON_bit: structure used for bit access */ }; union { /*!< RT bus status register */ __IO uint32_t RTBST; /*!< RTBST : type used for word access */ __IO _MILSTD_RTBST_bits RTBST_bit; /*!< RTBST_bit: structure used for bit access */ }; union { /*!< RT status words register */ __IO uint32_t RTSW; /*!< RTSW : type used for word access */ __IO _MILSTD_RTSW_bits RTSW_bit; /*!< RTSW_bit: structure used for bit access */ }; union { /*!< RT sync register */ __I uint32_t RTSYNC; /*!< RTSYNC : type used for word access */ __I _MILSTD_RTSYNC_bits RTSYNC_bit; /*!< RTSYNC_bit: structure used for bit access */ }; union { /*!< RT subaddress table base address */ __IO uint32_t RTSADDR; /*!< RTSADDR : type used for word access */ __IO _MILSTD_RTSADDR_bits RTSADDR_bit; /*!< RTSADDR_bit: structure used for bit access */ }; union { /*!< RT mode control register */ __IO uint32_t RTMOD; /*!< RTMOD : type used for word access */ __IO _MILSTD_RTMOD_bits RTMOD_bit; /*!< RTMOD_bit: structure used for bit access */ }; __IO uint32_t Reserved4[2]; union { /*!< RT time tag control register */ __IO uint32_t RTTIM; /*!< RTTIM : type used for word access */ __IO _MILSTD_RTTIM_bits RTTIM_bit; /*!< RTTIM_bit: structure used for bit access */ }; __IO uint32_t Reserved5; union { /*!< RT event log mask register */ __IO uint32_t RTELMSK; /*!< RTELMSK : type used for word access */ __IO _MILSTD_RTELMSK_bits RTELMSK_bit; /*!< RTELMSK_bit: structure used for bit access */ }; union { /*!< RT event log position pointer */ __IO uint32_t RTELP; /*!< RTELP : type used for word access */ __IO _MILSTD_RTELP_bits RTELP_bit; /*!< RTELP_bit: structure used for bit access */ }; union { /*!< RT event log interrupt position register */ __I uint32_t RTELIP; /*!< RTELIP : type used for word access */ __I _MILSTD_RTELIP_bits RTELIP_bit; /*!< RTELIP_bit: structure used for bit access */ }; __IO uint32_t Reserved6[2]; union { /*!< BM status register */ __I uint32_t BMSTAT; /*!< BMSTAT : type used for word access */ __I _MILSTD_BMSTAT_bits BMSTAT_bit; /*!< BMSTAT_bit: structure used for bit access */ }; union { /*!< BM control register */ __IO uint32_t BMCON; /*!< BMCON : type used for word access */ __IO _MILSTD_BMCON_bits BMCON_bit; /*!< BMCON_bit: structure used for bit access */ }; union { /*!< BM RT address filter register */ __IO uint32_t BMADF; /*!< BMADF : type used for word access */ __IO _MILSTD_BMADF_bits BMADF_bit; /*!< BMADF_bit: structure used for bit access */ }; union { /*!< BM RT subaddress filter register */ __IO uint32_t BMSADF; /*!< BMSADF : type used for word access */ __IO _MILSTD_BMSADF_bits BMSADF_bit; /*!< BMSADF_bit: structure used for bit access */ }; union { /*!< BM RT mode code filter register */ __IO uint32_t BMMODF; /*!< BMMODF : type used for word access */ __IO _MILSTD_BMMODF_bits BMMODF_bit; /*!< BMMODF_bit: structure used for bit access */ }; union { /*!< BM log buffer start */ __IO uint32_t BMLBS; /*!< BMLBS : type used for word access */ __IO _MILSTD_BMLBS_bits BMLBS_bit; /*!< BMLBS_bit: structure used for bit access */ }; union { /*!< BM log buffer end */ __IO uint32_t BMLBE; /*!< BMLBE : type used for word access */ __IO _MILSTD_BMLBE_bits BMLBE_bit; /*!< BMLBE_bit: structure used for bit access */ }; union { /*!< BM log buffer position */ __IO uint32_t BMLBP; /*!< BMLBP : type used for word access */ __IO _MILSTD_BMLBP_bits BMLBP_bit; /*!< BMLBP_bit: structure used for bit access */ }; union { /*!< BM time tag control register */ __IO uint32_t BMTIM; /*!< BMTIM : type used for word access */ __IO _MILSTD_BMTIM_bits BMTIM_bit; /*!< BMTIM_bit: structure used for bit access */ }; } MILSTD_TypeDef; /******************************************************************************/ /* SPWRTMR registers */ /******************************************************************************/ /*-- CFG: SpaceWire Tick Control Register --------------------------------------------------------------------*/ typedef struct { uint32_t T0EN :1; /*!< Enable timer 0 count */ uint32_t T1EN :1; /*!< Enable timer 1 count */ } _SPWRTMR_CFG_bits; /* Bit field positions: */ #define SPWRTMR_CFG_T0EN_Pos 0 /*!< Enable timer 0 count */ #define SPWRTMR_CFG_T1EN_Pos 1 /*!< Enable timer 1 count */ /* Bit field masks: */ #define SPWRTMR_CFG_T0EN_Msk 0x00000001UL /*!< Enable timer 0 count */ #define SPWRTMR_CFG_T1EN_Msk 0x00000002UL /*!< Enable timer 1 count */ /*-- REL0: SpaceWire Timer 0 Reload value register -----------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Timer 0 Reload value */ } _SPWRTMR_REL0_bits; /* Bit field positions: */ #define SPWRTMR_REL0_VAL_Pos 0 /*!< Timer 0 Reload value */ /* Bit field masks: */ #define SPWRTMR_REL0_VAL_Msk 0xFFFFFFFFUL /*!< Timer 0 Reload value */ /*-- REL1: SpaceWire Timer 1 Reload value register -----------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Timer 1 Reload value */ } _SPWRTMR_REL1_bits; /* Bit field positions: */ #define SPWRTMR_REL1_VAL_Pos 0 /*!< Timer 1 Reload value */ /* Bit field masks: */ #define SPWRTMR_REL1_VAL_Msk 0xFFFFFFFFUL /*!< Timer 1 Reload value */ typedef struct { union { /*!< SpaceWire Tick Control Register */ __IO uint32_t CFG; /*!< CFG : type used for word access */ __IO _SPWRTMR_CFG_bits CFG_bit; /*!< CFG_bit: structure used for bit access */ }; union { /*!< SpaceWire Timer 0 Reload value register */ __IO uint32_t REL0; /*!< REL0 : type used for word access */ __IO _SPWRTMR_REL0_bits REL0_bit; /*!< REL0_bit: structure used for bit access */ }; union { /*!< SpaceWire Timer 1 Reload value register */ __IO uint32_t REL1; /*!< REL1 : type used for word access */ __IO _SPWRTMR_REL1_bits REL1_bit; /*!< REL1_bit: structure used for bit access */ }; } SPWRTMR_TypeDef; /******************************************************************************/ /* SPWR registers */ /******************************************************************************/ /*-- CTRL: Control Register ----------------------------------------------------------------------------------*/ typedef struct { uint32_t LD :1; /*!< Link Disable */ uint32_t LS :1; /*!< Link Start */ uint32_t AS :1; /*!< Link Autostart */ uint32_t IE :1; /*!< Interrupt Enable */ uint32_t TI :1; /*!< Tick In */ uint32_t PM :1; /*!< Promiscious Mode */ uint32_t RS :1; /*!< Reset */ uint32_t :1; /*!< RESERVED */ uint32_t TQ :1; /*!< Tick-out IRQ */ uint32_t LI :1; /*!< Link Error IRQ */ uint32_t TT :1; /*!< Time TX enable */ uint32_t TR :1; /*!< Time RX enable */ uint32_t TF :1; /*!< Time_coded control flag filter */ uint32_t TL :1; /*!< Transmitter enable lock control */ } _SPWR_CTRL_bits; /* Bit field positions: */ #define SPWR_CTRL_LD_Pos 0 /*!< Link Disable */ #define SPWR_CTRL_LS_Pos 1 /*!< Link Start */ #define SPWR_CTRL_AS_Pos 2 /*!< Link Autostart */ #define SPWR_CTRL_IE_Pos 3 /*!< Interrupt Enable */ #define SPWR_CTRL_TI_Pos 4 /*!< Tick In */ #define SPWR_CTRL_PM_Pos 5 /*!< Promiscious Mode */ #define SPWR_CTRL_RS_Pos 6 /*!< Reset */ #define SPWR_CTRL_TQ_Pos 8 /*!< Tick-out IRQ */ #define SPWR_CTRL_LI_Pos 9 /*!< Link Error IRQ */ #define SPWR_CTRL_TT_Pos 10 /*!< Time TX enable */ #define SPWR_CTRL_TR_Pos 11 /*!< Time RX enable */ #define SPWR_CTRL_TF_Pos 12 /*!< Time_coded control flag filter */ #define SPWR_CTRL_TL_Pos 13 /*!< Transmitter enable lock control */ /* Bit field masks: */ #define SPWR_CTRL_LD_Msk 0x00000001UL /*!< Link Disable */ #define SPWR_CTRL_LS_Msk 0x00000002UL /*!< Link Start */ #define SPWR_CTRL_AS_Msk 0x00000004UL /*!< Link Autostart */ #define SPWR_CTRL_IE_Msk 0x00000008UL /*!< Interrupt Enable */ #define SPWR_CTRL_TI_Msk 0x00000010UL /*!< Tick In */ #define SPWR_CTRL_PM_Msk 0x00000020UL /*!< Promiscious Mode */ #define SPWR_CTRL_RS_Msk 0x00000040UL /*!< Reset */ #define SPWR_CTRL_TQ_Msk 0x00000100UL /*!< Tick-out IRQ */ #define SPWR_CTRL_LI_Msk 0x00000200UL /*!< Link Error IRQ */ #define SPWR_CTRL_TT_Msk 0x00000400UL /*!< Time TX enable */ #define SPWR_CTRL_TR_Msk 0x00000800UL /*!< Time RX enable */ #define SPWR_CTRL_TF_Msk 0x00001000UL /*!< Time_coded control flag filter */ #define SPWR_CTRL_TL_Msk 0x00002000UL /*!< Transmitter enable lock control */ /*-- STAT: Status Register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t TO :1; /*!< New Timecount value was received */ uint32_t CE :1; /*!< Credit Error */ uint32_t ER :1; /*!< Escape Error */ uint32_t DE :1; /*!< Disconnect Error */ uint32_t PE :1; /*!< Parity Error */ uint32_t :2; /*!< RESERVED */ uint32_t IA :1; /*!< Invalid Address */ uint32_t EE :1; /*!< Early EOP/EEP received */ uint32_t :12; /*!< RESERVED */ uint32_t LS :3; /*!< Link State */ } _SPWR_STAT_bits; /* Bit field positions: */ #define SPWR_STAT_TO_Pos 0 /*!< New Timecount value was received */ #define SPWR_STAT_CE_Pos 1 /*!< Credit Error */ #define SPWR_STAT_ER_Pos 2 /*!< Escape Error */ #define SPWR_STAT_DE_Pos 3 /*!< Disconnect Error */ #define SPWR_STAT_PE_Pos 4 /*!< Parity Error */ #define SPWR_STAT_IA_Pos 7 /*!< Invalid Address */ #define SPWR_STAT_EE_Pos 8 /*!< Early EOP/EEP received */ #define SPWR_STAT_LS_Pos 21 /*!< Link State */ /* Bit field masks: */ #define SPWR_STAT_TO_Msk 0x00000001UL /*!< New Timecount value was received */ #define SPWR_STAT_CE_Msk 0x00000002UL /*!< Credit Error */ #define SPWR_STAT_ER_Msk 0x00000004UL /*!< Escape Error */ #define SPWR_STAT_DE_Msk 0x00000008UL /*!< Disconnect Error */ #define SPWR_STAT_PE_Msk 0x00000010UL /*!< Parity Error */ #define SPWR_STAT_IA_Msk 0x00000080UL /*!< Invalid Address */ #define SPWR_STAT_EE_Msk 0x00000100UL /*!< Early EOP/EEP received */ #define SPWR_STAT_LS_Msk 0x00E00000UL /*!< Link State */ /* Bit field enums: */ typedef enum { SPWR_STAT_LS_ErrorReset = 0x0UL, /*!< error reset state */ SPWR_STAT_LS_ErrorWait = 0x1UL, /*!< error wait state */ SPWR_STAT_LS_Ready = 0x2UL, /*!< ready state */ SPWR_STAT_LS_Started = 0x3UL, /*!< started state */ SPWR_STAT_LS_Connecting = 0x4UL, /*!< connecting state */ SPWR_STAT_LS_Run = 0x5UL, /*!< run state */ } SPWR_STAT_LS_Enum; /*-- DEFADDR: Default Address Register -----------------------------------------------------------------------*/ typedef struct { uint32_t DA :8; /*!< Default Address */ uint32_t DM :8; /*!< Default address mask */ } _SPWR_DEFADDR_bits; /* Bit field positions: */ #define SPWR_DEFADDR_DA_Pos 0 /*!< Default Address */ #define SPWR_DEFADDR_DM_Pos 8 /*!< Default address mask */ /* Bit field masks: */ #define SPWR_DEFADDR_DA_Msk 0x000000FFUL /*!< Default Address */ #define SPWR_DEFADDR_DM_Msk 0x0000FF00UL /*!< Default address mask */ /*-- CLKDIV: Clock Divisor Register --------------------------------------------------------------------------*/ typedef struct { uint32_t CKDRUN :8; /*!< Clock Divisor In Run State */ uint32_t CKDSTRT :8; /*!< Clock Divisor in startup */ } _SPWR_CLKDIV_bits; /* Bit field positions: */ #define SPWR_CLKDIV_CKDRUN_Pos 0 /*!< Clock Divisor In Run State */ #define SPWR_CLKDIV_CKDSTRT_Pos 8 /*!< Clock Divisor in startup */ /* Bit field masks: */ #define SPWR_CLKDIV_CKDRUN_Msk 0x000000FFUL /*!< Clock Divisor In Run State */ #define SPWR_CLKDIV_CKDSTRT_Msk 0x0000FF00UL /*!< Clock Divisor in startup */ /*-- TIMECODE: Time Code Register ----------------------------------------------------------------------------*/ typedef struct { uint32_t TCNT :6; /*!< Time Counter Value */ uint32_t TCTRL :2; /*!< Time Control Flags */ } _SPWR_TIMECODE_bits; /* Bit field positions: */ #define SPWR_TIMECODE_TCNT_Pos 0 /*!< Time Counter Value */ #define SPWR_TIMECODE_TCTRL_Pos 6 /*!< Time Control Flags */ /* Bit field masks: */ #define SPWR_TIMECODE_TCNT_Msk 0x0000003FUL /*!< Time Counter Value */ #define SPWR_TIMECODE_TCTRL_Msk 0x000000C0UL /*!< Time Control Flags */ /*-- DMACSR: DMA Control/Status Register ---------------------------------------------------------------------*/ typedef struct { uint32_t TE :1; /*!< Transmitter Enable */ uint32_t RE :1; /*!< Receiver Rnable */ uint32_t TI :1; /*!< Transmit Interrupt */ uint32_t RI :1; /*!< Receive Interrupt */ uint32_t AI :1; /*!< AHB Error Interrupt */ uint32_t PS :1; /*!< Packet Sent */ uint32_t PR :1; /*!< Packet Received */ uint32_t TA :1; /*!< TX AHB Error */ uint32_t RA :1; /*!< RX AHB Error */ uint32_t AT :1; /*!< Abort Tx */ uint32_t RX :1; /*!< RX Active */ uint32_t RD :1; /*!< RX descriptors Available */ uint32_t NS :1; /*!< No Spills */ uint32_t EN :1; /*!< Enable Address */ uint32_t SA :1; /*!< Strip Address */ uint32_t SP :1; /*!< Strip PID */ uint32_t LE :1; /*!< Link Error Disable transmitter */ uint32_t TL :1; /*!< Transmiter Enable Lock */ uint32_t TP :1; /*!< Transmit packet IRQ */ uint32_t RP :1; /*!< Receive packet IRQ */ uint32_t :2; /*!< RESERVED */ uint32_t TR :1; /*!< Truncated */ uint32_t EP :1; /*!< EEP Termination */ } _SPWR_DMACSR_bits; /* Bit field positions: */ #define SPWR_DMACSR_TE_Pos 0 /*!< Transmitter Enable */ #define SPWR_DMACSR_RE_Pos 1 /*!< Receiver Rnable */ #define SPWR_DMACSR_TI_Pos 2 /*!< Transmit Interrupt */ #define SPWR_DMACSR_RI_Pos 3 /*!< Receive Interrupt */ #define SPWR_DMACSR_AI_Pos 4 /*!< AHB Error Interrupt */ #define SPWR_DMACSR_PS_Pos 5 /*!< Packet Sent */ #define SPWR_DMACSR_PR_Pos 6 /*!< Packet Received */ #define SPWR_DMACSR_TA_Pos 7 /*!< TX AHB Error */ #define SPWR_DMACSR_RA_Pos 8 /*!< RX AHB Error */ #define SPWR_DMACSR_AT_Pos 9 /*!< Abort Tx */ #define SPWR_DMACSR_RX_Pos 10 /*!< RX Active */ #define SPWR_DMACSR_RD_Pos 11 /*!< RX descriptors Available */ #define SPWR_DMACSR_NS_Pos 12 /*!< No Spills */ #define SPWR_DMACSR_EN_Pos 13 /*!< Enable Address */ #define SPWR_DMACSR_SA_Pos 14 /*!< Strip Address */ #define SPWR_DMACSR_SP_Pos 15 /*!< Strip PID */ #define SPWR_DMACSR_LE_Pos 16 /*!< Link Error Disable transmitter */ #define SPWR_DMACSR_TL_Pos 17 /*!< Transmiter Enable Lock */ #define SPWR_DMACSR_TP_Pos 18 /*!< Transmit packet IRQ */ #define SPWR_DMACSR_RP_Pos 19 /*!< Receive packet IRQ */ #define SPWR_DMACSR_TR_Pos 22 /*!< Truncated */ #define SPWR_DMACSR_EP_Pos 23 /*!< EEP Termination */ /* Bit field masks: */ #define SPWR_DMACSR_TE_Msk 0x00000001UL /*!< Transmitter Enable */ #define SPWR_DMACSR_RE_Msk 0x00000002UL /*!< Receiver Rnable */ #define SPWR_DMACSR_TI_Msk 0x00000004UL /*!< Transmit Interrupt */ #define SPWR_DMACSR_RI_Msk 0x00000008UL /*!< Receive Interrupt */ #define SPWR_DMACSR_AI_Msk 0x00000010UL /*!< AHB Error Interrupt */ #define SPWR_DMACSR_PS_Msk 0x00000020UL /*!< Packet Sent */ #define SPWR_DMACSR_PR_Msk 0x00000040UL /*!< Packet Received */ #define SPWR_DMACSR_TA_Msk 0x00000080UL /*!< TX AHB Error */ #define SPWR_DMACSR_RA_Msk 0x00000100UL /*!< RX AHB Error */ #define SPWR_DMACSR_AT_Msk 0x00000200UL /*!< Abort Tx */ #define SPWR_DMACSR_RX_Msk 0x00000400UL /*!< RX Active */ #define SPWR_DMACSR_RD_Msk 0x00000800UL /*!< RX descriptors Available */ #define SPWR_DMACSR_NS_Msk 0x00001000UL /*!< No Spills */ #define SPWR_DMACSR_EN_Msk 0x00002000UL /*!< Enable Address */ #define SPWR_DMACSR_SA_Msk 0x00004000UL /*!< Strip Address */ #define SPWR_DMACSR_SP_Msk 0x00008000UL /*!< Strip PID */ #define SPWR_DMACSR_LE_Msk 0x00010000UL /*!< Link Error Disable transmitter */ #define SPWR_DMACSR_TL_Msk 0x00020000UL /*!< Transmiter Enable Lock */ #define SPWR_DMACSR_TP_Msk 0x00040000UL /*!< Transmit packet IRQ */ #define SPWR_DMACSR_RP_Msk 0x00080000UL /*!< Receive packet IRQ */ #define SPWR_DMACSR_TR_Msk 0x00400000UL /*!< Truncated */ #define SPWR_DMACSR_EP_Msk 0x00800000UL /*!< EEP Termination */ /*-- DMARXLEN: DMA RX Maximum Length Register ----------------------------------------------------------------*/ typedef struct { uint32_t RXMAXLEN :25; /*!< RX maximum length packet value */ } _SPWR_DMARXLEN_bits; /* Bit field positions: */ #define SPWR_DMARXLEN_RXMAXLEN_Pos 0 /*!< RX maximum length packet value */ /* Bit field masks: */ #define SPWR_DMARXLEN_RXMAXLEN_Msk 0x01FFFFFFUL /*!< RX maximum length packet value */ /*-- DMATDTADDR: DMA Transmit Descriptor Table Address Register ----------------------------------------------*/ typedef struct { uint32_t :4; /*!< RESERVED */ uint32_t SEL :6; /*!< Descriptor Selector */ uint32_t BADDR :22; /*!< Descriptor Table Base Address */ } _SPWR_DMATDTADDR_bits; /* Bit field positions: */ #define SPWR_DMATDTADDR_SEL_Pos 4 /*!< Descriptor Selector */ #define SPWR_DMATDTADDR_BADDR_Pos 10 /*!< Descriptor Table Base Address */ /* Bit field masks: */ #define SPWR_DMATDTADDR_SEL_Msk 0x000003F0UL /*!< Descriptor Selector */ #define SPWR_DMATDTADDR_BADDR_Msk 0xFFFFFC00UL /*!< Descriptor Table Base Address */ /*-- DMARDTADDR: DMA Receive Descriptor Table Address Register -----------------------------------------------*/ typedef struct { uint32_t :3; /*!< RESERVED */ uint32_t SEL :7; /*!< Descriptor Selector */ uint32_t BADDR :22; /*!< Descriptor Table Base Address */ } _SPWR_DMARDTADDR_bits; /* Bit field positions: */ #define SPWR_DMARDTADDR_SEL_Pos 3 /*!< Descriptor Selector */ #define SPWR_DMARDTADDR_BADDR_Pos 10 /*!< Descriptor Table Base Address */ /* Bit field masks: */ #define SPWR_DMARDTADDR_SEL_Msk 0x000003F8UL /*!< Descriptor Selector */ #define SPWR_DMARDTADDR_BADDR_Msk 0xFFFFFC00UL /*!< Descriptor Table Base Address */ /*-- DMAADDR: -----------------------------------------------------------------------------------------------*/ typedef struct { uint32_t ADDR :8; /*!< Address Value For Node Identification */ uint32_t MASK :8; /*!< Mask value for node Identification */ } _SPWR_DMAADDR_bits; /* Bit field positions: */ #define SPWR_DMAADDR_ADDR_Pos 0 /*!< Address Value For Node Identification */ #define SPWR_DMAADDR_MASK_Pos 8 /*!< Mask value for node Identification */ /* Bit field masks: */ #define SPWR_DMAADDR_ADDR_Msk 0x000000FFUL /*!< Address Value For Node Identification */ #define SPWR_DMAADDR_MASK_Msk 0x0000FF00UL /*!< Mask value for node Identification */ typedef struct { union { /*!< Control Register */ __IO uint32_t CTRL; /*!< CTRL : type used for word access */ __IO _SPWR_CTRL_bits CTRL_bit; /*!< CTRL_bit: structure used for bit access */ }; union { /*!< Status Register */ __IO uint32_t STAT; /*!< STAT : type used for word access */ __IO _SPWR_STAT_bits STAT_bit; /*!< STAT_bit: structure used for bit access */ }; union { /*!< Default Address Register */ __IO uint32_t DEFADDR; /*!< DEFADDR : type used for word access */ __IO _SPWR_DEFADDR_bits DEFADDR_bit; /*!< DEFADDR_bit: structure used for bit access */ }; union { /*!< Clock Divisor Register */ __IO uint32_t CLKDIV; /*!< CLKDIV : type used for word access */ __IO _SPWR_CLKDIV_bits CLKDIV_bit; /*!< CLKDIV_bit: structure used for bit access */ }; __IO uint32_t Reserved0; union { /*!< Time Code Register */ __IO uint32_t TIMECODE; /*!< TIMECODE : type used for word access */ __IO _SPWR_TIMECODE_bits TIMECODE_bit; /*!< TIMECODE_bit: structure used for bit access */ }; __IO uint32_t Reserved1[2]; union { /*!< DMA Control/Status Register */ __IO uint32_t DMACSR; /*!< DMACSR : type used for word access */ __IO _SPWR_DMACSR_bits DMACSR_bit; /*!< DMACSR_bit: structure used for bit access */ }; union { /*!< DMA RX Maximum Length Register */ __IO uint32_t DMARXLEN; /*!< DMARXLEN : type used for word access */ __IO _SPWR_DMARXLEN_bits DMARXLEN_bit; /*!< DMARXLEN_bit: structure used for bit access */ }; union { /*!< DMA Transmit Descriptor Table Address Register */ __IO uint32_t DMATDTADDR; /*!< DMATDTADDR : type used for word access */ __IO _SPWR_DMATDTADDR_bits DMATDTADDR_bit; /*!< DMATDTADDR_bit: structure used for bit access */ }; union { /*!< DMA Receive Descriptor Table Address Register */ __IO uint32_t DMARDTADDR; /*!< DMARDTADDR : type used for word access */ __IO _SPWR_DMARDTADDR_bits DMARDTADDR_bit; /*!< DMARDTADDR_bit: structure used for bit access */ }; union { /*!< */ __IO uint32_t DMAADDR; /*!< DMAADDR : type used for word access */ __IO _SPWR_DMAADDR_bits DMAADDR_bit; /*!< DMAADDR_bit: structure used for bit access */ }; } SPWR_TypeDef; /******************************************************************************/ /* RTC registers */ /******************************************************************************/ /*-- POS: Parts of seconds register --------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :10; /*!< Parts of seconds */ } _RTC_POS_bits; /* Bit field positions: */ #define RTC_POS_VAL_Pos 0 /*!< Parts of seconds */ /* Bit field masks: */ #define RTC_POS_VAL_Msk 0x000003FFUL /*!< Parts of seconds */ /*-- SEC: Second register ------------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :7; /*!< Seconds in BCD format */ } _RTC_SEC_bits; /* Bit field positions: */ #define RTC_SEC_VAL_Pos 0 /*!< Seconds in BCD format */ /* Bit field masks: */ #define RTC_SEC_VAL_Msk 0x0000007FUL /*!< Seconds in BCD format */ /*-- MIN: Minute register ------------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :7; /*!< Minutes in BCD format */ } _RTC_MIN_bits; /* Bit field positions: */ #define RTC_MIN_VAL_Pos 0 /*!< Minutes in BCD format */ /* Bit field masks: */ #define RTC_MIN_VAL_Msk 0x0000007FUL /*!< Minutes in BCD format */ /*-- HOUR: Hour register -------------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :6; /*!< Hours in BCD format */ } _RTC_HOUR_bits; /* Bit field positions: */ #define RTC_HOUR_VAL_Pos 0 /*!< Hours in BCD format */ /* Bit field masks: */ #define RTC_HOUR_VAL_Msk 0x0000003FUL /*!< Hours in BCD format */ /*-- DOW: Day of week register -------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :3; /*!< Day of week in BCD format */ } _RTC_DOW_bits; /* Bit field positions: */ #define RTC_DOW_VAL_Pos 0 /*!< Day of week in BCD format */ /* Bit field masks: */ #define RTC_DOW_VAL_Msk 0x00000007UL /*!< Day of week in BCD format */ /*-- DAY: Day register ---------------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :6; /*!< Day in BCD format */ } _RTC_DAY_bits; /* Bit field positions: */ #define RTC_DAY_VAL_Pos 0 /*!< Day in BCD format */ /* Bit field masks: */ #define RTC_DAY_VAL_Msk 0x0000003FUL /*!< Day in BCD format */ /*-- MONTH: Month register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :5; /*!< Month in BCD format */ } _RTC_MONTH_bits; /* Bit field positions: */ #define RTC_MONTH_VAL_Pos 0 /*!< Month in BCD format */ /* Bit field masks: */ #define RTC_MONTH_VAL_Msk 0x0000001FUL /*!< Month in BCD format */ /*-- YEAR: Year register -------------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :8; /*!< Year in BCD format */ } _RTC_YEAR_bits; /* Bit field positions: */ #define RTC_YEAR_VAL_Pos 0 /*!< Year in BCD format */ /* Bit field masks: */ #define RTC_YEAR_VAL_Msk 0x000000FFUL /*!< Year in BCD format */ /*-- SHDW: Register Update shadow registers RTC --------------------------------------------------------------*/ typedef struct { uint32_t :7; /*!< RESERVED */ uint32_t UPDTEN :1; /*!< Enable update shadow registers RTC */ } _RTC_SHDW_bits; /* Bit field positions: */ #define RTC_SHDW_UPDTEN_Pos 7 /*!< Enable update shadow registers RTC */ /* Bit field masks: */ #define RTC_SHDW_UPDTEN_Msk 0x00000080UL /*!< Enable update shadow registers RTC */ /*-- TIME: General register Time -----------------------------------------------------------------------------*/ typedef struct { uint32_t POS :10; /*!< Parts of seconds */ uint32_t SEC :7; /*!< Seconds */ uint32_t MIN :7; /*!< Minutes */ uint32_t HOUR :6; /*!< Hours */ } _RTC_TIME_bits; /* Bit field positions: */ #define RTC_TIME_POS_Pos 0 /*!< Parts of seconds */ #define RTC_TIME_SEC_Pos 10 /*!< Seconds */ #define RTC_TIME_MIN_Pos 17 /*!< Minutes */ #define RTC_TIME_HOUR_Pos 24 /*!< Hours */ /* Bit field masks: */ #define RTC_TIME_POS_Msk 0x000003FFUL /*!< Parts of seconds */ #define RTC_TIME_SEC_Msk 0x0001FC00UL /*!< Seconds */ #define RTC_TIME_MIN_Msk 0x00FE0000UL /*!< Minutes */ #define RTC_TIME_HOUR_Msk 0x3F000000UL /*!< Hours */ typedef struct { union { /*!< Parts of seconds register */ __IO uint32_t POS; /*!< POS : type used for word access */ __IO _RTC_POS_bits POS_bit; /*!< POS_bit: structure used for bit access */ }; union { /*!< Second register */ __IO uint32_t SEC; /*!< SEC : type used for word access */ __IO _RTC_SEC_bits SEC_bit; /*!< SEC_bit: structure used for bit access */ }; union { /*!< Minute register */ __IO uint32_t MIN; /*!< MIN : type used for word access */ __IO _RTC_MIN_bits MIN_bit; /*!< MIN_bit: structure used for bit access */ }; __IO uint32_t Reserved0; union { /*!< Hour register */ __IO uint32_t HOUR; /*!< HOUR : type used for word access */ __IO _RTC_HOUR_bits HOUR_bit; /*!< HOUR_bit: structure used for bit access */ }; __IO uint32_t Reserved1; union { /*!< Day of week register */ __IO uint32_t DOW; /*!< DOW : type used for word access */ __IO _RTC_DOW_bits DOW_bit; /*!< DOW_bit: structure used for bit access */ }; __IO uint32_t Reserved2; union { /*!< Day register */ __IO uint32_t DAY; /*!< DAY : type used for word access */ __IO _RTC_DAY_bits DAY_bit; /*!< DAY_bit: structure used for bit access */ }; union { /*!< Month register */ __IO uint32_t MONTH; /*!< MONTH : type used for word access */ __IO _RTC_MONTH_bits MONTH_bit; /*!< MONTH_bit: structure used for bit access */ }; union { /*!< Year register */ __IO uint32_t YEAR; /*!< YEAR : type used for word access */ __IO _RTC_YEAR_bits YEAR_bit; /*!< YEAR_bit: structure used for bit access */ }; union { /*!< Register Update shadow registers RTC */ __O uint32_t SHDW; /*!< SHDW : type used for word access */ __O _RTC_SHDW_bits SHDW_bit; /*!< SHDW_bit: structure used for bit access */ }; union { /*!< General register Time */ __I uint32_t TIME; /*!< TIME : type used for word access */ __I _RTC_TIME_bits TIME_bit; /*!< TIME_bit: structure used for bit access */ }; } RTC_TypeDef; /******************************************************************************/ /* LAU registers */ /******************************************************************************/ /*-- INTCTL: Interrupt control register ----------------------------------------------------------------------*/ typedef struct { uint32_t POL0 :1; /*!< Interrupt polarity select for LM0 */ uint32_t POL1 :1; /*!< Interrupt polarity select for LM1 */ uint32_t POL2 :1; /*!< Interrupt polarity select for LM2 */ uint32_t POL3 :1; /*!< Interrupt polarity select for LM3 */ uint32_t POL4 :1; /*!< Interrupt polarity select for LM4 */ uint32_t POL5 :1; /*!< Interrupt polarity select for LM5 */ uint32_t POL6 :1; /*!< Interrupt polarity select for LM6 */ uint32_t POL7 :1; /*!< Interrupt polarity select for LM7 */ uint32_t TYPE0 :1; /*!< Interrupt type select for LM0 */ uint32_t TYPE1 :1; /*!< Interrupt type select for LM1 */ uint32_t TYPE2 :1; /*!< Interrupt type select for LM2 */ uint32_t TYPE3 :1; /*!< Interrupt type select for LM3 */ uint32_t TYPE4 :1; /*!< Interrupt type select for LM4 */ uint32_t TYPE5 :1; /*!< Interrupt type select for LM5 */ uint32_t TYPE6 :1; /*!< Interrupt type select for LM6 */ uint32_t TYPE7 :1; /*!< Interrupt type select for LM7 */ } _LAU_INTCTL_bits; /* Bit field positions: */ #define LAU_INTCTL_POL0_Pos 0 /*!< Interrupt polarity select for LM0 */ #define LAU_INTCTL_POL1_Pos 1 /*!< Interrupt polarity select for LM1 */ #define LAU_INTCTL_POL2_Pos 2 /*!< Interrupt polarity select for LM2 */ #define LAU_INTCTL_POL3_Pos 3 /*!< Interrupt polarity select for LM3 */ #define LAU_INTCTL_POL4_Pos 4 /*!< Interrupt polarity select for LM4 */ #define LAU_INTCTL_POL5_Pos 5 /*!< Interrupt polarity select for LM5 */ #define LAU_INTCTL_POL6_Pos 6 /*!< Interrupt polarity select for LM6 */ #define LAU_INTCTL_POL7_Pos 7 /*!< Interrupt polarity select for LM7 */ #define LAU_INTCTL_TYPE0_Pos 8 /*!< Interrupt type select for LM0 */ #define LAU_INTCTL_TYPE1_Pos 9 /*!< Interrupt type select for LM1 */ #define LAU_INTCTL_TYPE2_Pos 10 /*!< Interrupt type select for LM2 */ #define LAU_INTCTL_TYPE3_Pos 11 /*!< Interrupt type select for LM3 */ #define LAU_INTCTL_TYPE4_Pos 12 /*!< Interrupt type select for LM4 */ #define LAU_INTCTL_TYPE5_Pos 13 /*!< Interrupt type select for LM5 */ #define LAU_INTCTL_TYPE6_Pos 14 /*!< Interrupt type select for LM6 */ #define LAU_INTCTL_TYPE7_Pos 15 /*!< Interrupt type select for LM7 */ /* Bit field masks: */ #define LAU_INTCTL_POL0_Msk 0x00000001UL /*!< Interrupt polarity select for LM0 */ #define LAU_INTCTL_POL1_Msk 0x00000002UL /*!< Interrupt polarity select for LM1 */ #define LAU_INTCTL_POL2_Msk 0x00000004UL /*!< Interrupt polarity select for LM2 */ #define LAU_INTCTL_POL3_Msk 0x00000008UL /*!< Interrupt polarity select for LM3 */ #define LAU_INTCTL_POL4_Msk 0x00000010UL /*!< Interrupt polarity select for LM4 */ #define LAU_INTCTL_POL5_Msk 0x00000020UL /*!< Interrupt polarity select for LM5 */ #define LAU_INTCTL_POL6_Msk 0x00000040UL /*!< Interrupt polarity select for LM6 */ #define LAU_INTCTL_POL7_Msk 0x00000080UL /*!< Interrupt polarity select for LM7 */ #define LAU_INTCTL_TYPE0_Msk 0x00000100UL /*!< Interrupt type select for LM0 */ #define LAU_INTCTL_TYPE1_Msk 0x00000200UL /*!< Interrupt type select for LM1 */ #define LAU_INTCTL_TYPE2_Msk 0x00000400UL /*!< Interrupt type select for LM2 */ #define LAU_INTCTL_TYPE3_Msk 0x00000800UL /*!< Interrupt type select for LM3 */ #define LAU_INTCTL_TYPE4_Msk 0x00001000UL /*!< Interrupt type select for LM4 */ #define LAU_INTCTL_TYPE5_Msk 0x00002000UL /*!< Interrupt type select for LM5 */ #define LAU_INTCTL_TYPE6_Msk 0x00004000UL /*!< Interrupt type select for LM6 */ #define LAU_INTCTL_TYPE7_Msk 0x00008000UL /*!< Interrupt type select for LM7 */ /*-- IMSC: Interrupt Mask Set/Clear Register -----------------------------------------------------------------*/ typedef struct { uint32_t IMLM0 :1; /*!< LM0 interrupt mask */ uint32_t IMLM1 :1; /*!< LM1 interrupt mask */ uint32_t IMLM2 :1; /*!< LM2 interrupt mask */ uint32_t IMLM3 :1; /*!< LM3 interrupt mask */ uint32_t IMLM4 :1; /*!< LM4 interrupt mask */ uint32_t IMLM5 :1; /*!< LM5 interrupt mask */ uint32_t IMLM6 :1; /*!< LM6 interrupt mask */ uint32_t IMLM7 :1; /*!< LM7 interrupt mask */ } _LAU_IMSC_bits; /* Bit field positions: */ #define LAU_IMSC_IMLM0_Pos 0 /*!< LM0 interrupt mask */ #define LAU_IMSC_IMLM1_Pos 1 /*!< LM1 interrupt mask */ #define LAU_IMSC_IMLM2_Pos 2 /*!< LM2 interrupt mask */ #define LAU_IMSC_IMLM3_Pos 3 /*!< LM3 interrupt mask */ #define LAU_IMSC_IMLM4_Pos 4 /*!< LM4 interrupt mask */ #define LAU_IMSC_IMLM5_Pos 5 /*!< LM5 interrupt mask */ #define LAU_IMSC_IMLM6_Pos 6 /*!< LM6 interrupt mask */ #define LAU_IMSC_IMLM7_Pos 7 /*!< LM7 interrupt mask */ /* Bit field masks: */ #define LAU_IMSC_IMLM0_Msk 0x00000001UL /*!< LM0 interrupt mask */ #define LAU_IMSC_IMLM1_Msk 0x00000002UL /*!< LM1 interrupt mask */ #define LAU_IMSC_IMLM2_Msk 0x00000004UL /*!< LM2 interrupt mask */ #define LAU_IMSC_IMLM3_Msk 0x00000008UL /*!< LM3 interrupt mask */ #define LAU_IMSC_IMLM4_Msk 0x00000010UL /*!< LM4 interrupt mask */ #define LAU_IMSC_IMLM5_Msk 0x00000020UL /*!< LM5 interrupt mask */ #define LAU_IMSC_IMLM6_Msk 0x00000040UL /*!< LM6 interrupt mask */ #define LAU_IMSC_IMLM7_Msk 0x00000080UL /*!< LM7 interrupt mask */ /*-- RIS: Raw Interrupt Status Register ----------------------------------------------------------------------*/ typedef struct { uint32_t RLM0 :1; /*!< LM0 interrupt status */ uint32_t RLM1 :1; /*!< LM1 interrupt status */ uint32_t RLM2 :1; /*!< LM2 interrupt status */ uint32_t RLM3 :1; /*!< LM3 interrupt status */ uint32_t RLM4 :1; /*!< LM4 interrupt status */ uint32_t RLM5 :1; /*!< LM5 interrupt status */ uint32_t RLM6 :1; /*!< LM6 interrupt status */ uint32_t RLM7 :1; /*!< LM7 interrupt status */ } _LAU_RIS_bits; /* Bit field positions: */ #define LAU_RIS_RLM0_Pos 0 /*!< LM0 interrupt status */ #define LAU_RIS_RLM1_Pos 1 /*!< LM1 interrupt status */ #define LAU_RIS_RLM2_Pos 2 /*!< LM2 interrupt status */ #define LAU_RIS_RLM3_Pos 3 /*!< LM3 interrupt status */ #define LAU_RIS_RLM4_Pos 4 /*!< LM4 interrupt status */ #define LAU_RIS_RLM5_Pos 5 /*!< LM5 interrupt status */ #define LAU_RIS_RLM6_Pos 6 /*!< LM6 interrupt status */ #define LAU_RIS_RLM7_Pos 7 /*!< LM7 interrupt status */ /* Bit field masks: */ #define LAU_RIS_RLM0_Msk 0x00000001UL /*!< LM0 interrupt status */ #define LAU_RIS_RLM1_Msk 0x00000002UL /*!< LM1 interrupt status */ #define LAU_RIS_RLM2_Msk 0x00000004UL /*!< LM2 interrupt status */ #define LAU_RIS_RLM3_Msk 0x00000008UL /*!< LM3 interrupt status */ #define LAU_RIS_RLM4_Msk 0x00000010UL /*!< LM4 interrupt status */ #define LAU_RIS_RLM5_Msk 0x00000020UL /*!< LM5 interrupt status */ #define LAU_RIS_RLM6_Msk 0x00000040UL /*!< LM6 interrupt status */ #define LAU_RIS_RLM7_Msk 0x00000080UL /*!< LM7 interrupt status */ /*-- MIS: Masked Interrupt Status Register -------------------------------------------------------------------*/ typedef struct { uint32_t MLM0 :1; /*!< LM0 masked interrupt status */ uint32_t MLM1 :1; /*!< LM1 masked interrupt status */ uint32_t MLM2 :1; /*!< LM2 masked interrupt status */ uint32_t MLM3 :1; /*!< LM3 masked interrupt status */ uint32_t MLM4 :1; /*!< LM4 masked interrupt status */ uint32_t MLM5 :1; /*!< LM5 masked interrupt status */ uint32_t MLM6 :1; /*!< LM6 masked interrupt status */ uint32_t MLM7 :1; /*!< LM7 masked interrupt status */ } _LAU_MIS_bits; /* Bit field positions: */ #define LAU_MIS_MLM0_Pos 0 /*!< LM0 masked interrupt status */ #define LAU_MIS_MLM1_Pos 1 /*!< LM1 masked interrupt status */ #define LAU_MIS_MLM2_Pos 2 /*!< LM2 masked interrupt status */ #define LAU_MIS_MLM3_Pos 3 /*!< LM3 masked interrupt status */ #define LAU_MIS_MLM4_Pos 4 /*!< LM4 masked interrupt status */ #define LAU_MIS_MLM5_Pos 5 /*!< LM5 masked interrupt status */ #define LAU_MIS_MLM6_Pos 6 /*!< LM6 masked interrupt status */ #define LAU_MIS_MLM7_Pos 7 /*!< LM7 masked interrupt status */ /* Bit field masks: */ #define LAU_MIS_MLM0_Msk 0x00000001UL /*!< LM0 masked interrupt status */ #define LAU_MIS_MLM1_Msk 0x00000002UL /*!< LM1 masked interrupt status */ #define LAU_MIS_MLM2_Msk 0x00000004UL /*!< LM2 masked interrupt status */ #define LAU_MIS_MLM3_Msk 0x00000008UL /*!< LM3 masked interrupt status */ #define LAU_MIS_MLM4_Msk 0x00000010UL /*!< LM4 masked interrupt status */ #define LAU_MIS_MLM5_Msk 0x00000020UL /*!< LM5 masked interrupt status */ #define LAU_MIS_MLM6_Msk 0x00000040UL /*!< LM6 masked interrupt status */ #define LAU_MIS_MLM7_Msk 0x00000080UL /*!< LM7 masked interrupt status */ /*-- ICR: Interrupt Clear Register ---------------------------------------------------------------------------*/ typedef struct { uint32_t ICLM0 :1; /*!< LM0 interrupt clear */ uint32_t ICLM1 :1; /*!< LM1 interrupt clear */ uint32_t ICLM2 :1; /*!< LM2 interrupt clear */ uint32_t ICLM3 :1; /*!< LM3 interrupt clear */ uint32_t ICLM4 :1; /*!< LM4 interrupt clear */ uint32_t ICLM5 :1; /*!< LM5 interrupt clear */ uint32_t ICLM6 :1; /*!< LM6 interrupt clear */ uint32_t ICLM7 :1; /*!< LM7 interrupt clear */ } _LAU_ICR_bits; /* Bit field positions: */ #define LAU_ICR_ICLM0_Pos 0 /*!< LM0 interrupt clear */ #define LAU_ICR_ICLM1_Pos 1 /*!< LM1 interrupt clear */ #define LAU_ICR_ICLM2_Pos 2 /*!< LM2 interrupt clear */ #define LAU_ICR_ICLM3_Pos 3 /*!< LM3 interrupt clear */ #define LAU_ICR_ICLM4_Pos 4 /*!< LM4 interrupt clear */ #define LAU_ICR_ICLM5_Pos 5 /*!< LM5 interrupt clear */ #define LAU_ICR_ICLM6_Pos 6 /*!< LM6 interrupt clear */ #define LAU_ICR_ICLM7_Pos 7 /*!< LM7 interrupt clear */ /* Bit field masks: */ #define LAU_ICR_ICLM0_Msk 0x00000001UL /*!< LM0 interrupt clear */ #define LAU_ICR_ICLM1_Msk 0x00000002UL /*!< LM1 interrupt clear */ #define LAU_ICR_ICLM2_Msk 0x00000004UL /*!< LM2 interrupt clear */ #define LAU_ICR_ICLM3_Msk 0x00000008UL /*!< LM3 interrupt clear */ #define LAU_ICR_ICLM4_Msk 0x00000010UL /*!< LM4 interrupt clear */ #define LAU_ICR_ICLM5_Msk 0x00000020UL /*!< LM5 interrupt clear */ #define LAU_ICR_ICLM6_Msk 0x00000040UL /*!< LM6 interrupt clear */ #define LAU_ICR_ICLM7_Msk 0x00000080UL /*!< LM7 interrupt clear */ /*-- LM: CLKCTL: Clock Control Register -----------------------------------------------------------------------*/ typedef struct { uint32_t CLKMUX :3; /*!< Clock select */ uint32_t CLKEN :1; /*!< Clock enable */ uint32_t DIV :10; /*!< Clock divider */ uint32_t :2; /*!< RESERVED */ uint32_t DIVEN :1; /*!< Clock divider enable */ } _LAU_LM_CLKCTL_bits; /* Bit field positions: */ #define LAU_LM_CLKCTL_CLKMUX_Pos 0 /*!< Clock select */ #define LAU_LM_CLKCTL_CLKEN_Pos 3 /*!< Clock enable */ #define LAU_LM_CLKCTL_DIV_Pos 4 /*!< Clock divider */ #define LAU_LM_CLKCTL_DIVEN_Pos 16 /*!< Clock divider enable */ /* Bit field masks: */ #define LAU_LM_CLKCTL_CLKMUX_Msk 0x00000007UL /*!< Clock select */ #define LAU_LM_CLKCTL_CLKEN_Msk 0x00000008UL /*!< Clock enable */ #define LAU_LM_CLKCTL_DIV_Msk 0x00003FF0UL /*!< Clock divider */ #define LAU_LM_CLKCTL_DIVEN_Msk 0x00010000UL /*!< Clock divider enable */ /*-- LM: INTSEL: Interrupt Selection Register -----------------------------------------------------------------*/ typedef struct { uint32_t LUTNUM :3; /*!< LUT chanel to make interrupt */ } _LAU_LM_INTSEL_bits; /* Bit field positions: */ #define LAU_LM_INTSEL_LUTNUM_Pos 0 /*!< LUT chanel to make interrupt */ /* Bit field masks: */ #define LAU_LM_INTSEL_LUTNUM_Msk 0x00000007UL /*!< LUT chanel to make interrupt */ /*-- LM: BUSSEL: LM_BUS Signal Selection Register -------------------------------------------------------------*/ typedef struct { uint32_t LMNUM :3; /*!< LUT chanel out to LMBUS */ } _LAU_LM_BUSSEL_bits; /* Bit field positions: */ #define LAU_LM_BUSSEL_LMNUM_Pos 0 /*!< LUT chanel out to LMBUS */ /* Bit field masks: */ #define LAU_LM_BUSSEL_LMNUM_Msk 0x00000007UL /*!< LUT chanel out to LMBUS */ /*-- LM: OUTMUX: LM_OUT Selection Register --------------------------------------------------------------------*/ typedef struct { uint32_t OUT0 :3; /*!< LUT chanel connected to OUT_0 */ uint32_t :1; /*!< RESERVED */ uint32_t OUT1 :3; /*!< LUT chanel connected to OUT_1 */ uint32_t :1; /*!< RESERVED */ uint32_t OUT2 :3; /*!< LUT chanel connected to OUT_2 */ uint32_t :1; /*!< RESERVED */ uint32_t OUT3 :3; /*!< LUT chanel connected to OUT_3 */ uint32_t :1; /*!< RESERVED */ uint32_t OUT4 :3; /*!< LUT chanel connected to OUT_4 */ uint32_t :1; /*!< RESERVED */ uint32_t OUT5 :3; /*!< LUT chanel connected to OUT_5 */ uint32_t :1; /*!< RESERVED */ uint32_t OUT6 :3; /*!< LUT chanel connected to OUT_6 */ uint32_t :1; /*!< RESERVED */ uint32_t OUT7 :3; /*!< LUT chanel connected to OUT_7 */ } _LAU_LM_OUTMUX_bits; /* Bit field positions: */ #define LAU_LM_OUTMUX_OUT0_Pos 0 /*!< LUT chanel connected to OUT_0 */ #define LAU_LM_OUTMUX_OUT1_Pos 4 /*!< LUT chanel connected to OUT_1 */ #define LAU_LM_OUTMUX_OUT2_Pos 8 /*!< LUT chanel connected to OUT_2 */ #define LAU_LM_OUTMUX_OUT3_Pos 12 /*!< LUT chanel connected to OUT_3 */ #define LAU_LM_OUTMUX_OUT4_Pos 16 /*!< LUT chanel connected to OUT_4 */ #define LAU_LM_OUTMUX_OUT5_Pos 20 /*!< LUT chanel connected to OUT_5 */ #define LAU_LM_OUTMUX_OUT6_Pos 24 /*!< LUT chanel connected to OUT_6 */ #define LAU_LM_OUTMUX_OUT7_Pos 28 /*!< LUT chanel connected to OUT_7 */ /* Bit field masks: */ #define LAU_LM_OUTMUX_OUT0_Msk 0x00000007UL /*!< LUT chanel connected to OUT_0 */ #define LAU_LM_OUTMUX_OUT1_Msk 0x00000070UL /*!< LUT chanel connected to OUT_1 */ #define LAU_LM_OUTMUX_OUT2_Msk 0x00000700UL /*!< LUT chanel connected to OUT_2 */ #define LAU_LM_OUTMUX_OUT3_Msk 0x00007000UL /*!< LUT chanel connected to OUT_3 */ #define LAU_LM_OUTMUX_OUT4_Msk 0x00070000UL /*!< LUT chanel connected to OUT_4 */ #define LAU_LM_OUTMUX_OUT5_Msk 0x00700000UL /*!< LUT chanel connected to OUT_5 */ #define LAU_LM_OUTMUX_OUT6_Msk 0x07000000UL /*!< LUT chanel connected to OUT_6 */ #define LAU_LM_OUTMUX_OUT7_Msk 0x70000000UL /*!< LUT chanel connected to OUT_7 */ /*-- LM: OEMUX: LM_OE Selection Register ----------------------------------------------------------------------*/ typedef struct { uint32_t OE0 :3; /*!< LUT chanel connected to OE_0 */ uint32_t :1; /*!< RESERVED */ uint32_t OE1 :3; /*!< LUT chanel connected to OE_1 */ uint32_t :1; /*!< RESERVED */ uint32_t OE2 :3; /*!< LUT chanel connected to OE_2 */ uint32_t :1; /*!< RESERVED */ uint32_t OE3 :3; /*!< LUT chanel connected to OE_3 */ uint32_t :1; /*!< RESERVED */ uint32_t OE4 :3; /*!< LUT chanel connected to OE_4 */ uint32_t :1; /*!< RESERVED */ uint32_t OE5 :3; /*!< LUT chanel connected to OE_5 */ uint32_t :1; /*!< RESERVED */ uint32_t OE6 :3; /*!< LUT chanel connected to OE_6 */ uint32_t :1; /*!< RESERVED */ uint32_t OE7 :3; /*!< LUT chanel connected to OE_7 */ } _LAU_LM_OEMUX_bits; /* Bit field positions: */ #define LAU_LM_OEMUX_OE0_Pos 0 /*!< LUT chanel connected to OE_0 */ #define LAU_LM_OEMUX_OE1_Pos 4 /*!< LUT chanel connected to OE_1 */ #define LAU_LM_OEMUX_OE2_Pos 8 /*!< LUT chanel connected to OE_2 */ #define LAU_LM_OEMUX_OE3_Pos 12 /*!< LUT chanel connected to OE_3 */ #define LAU_LM_OEMUX_OE4_Pos 16 /*!< LUT chanel connected to OE_4 */ #define LAU_LM_OEMUX_OE5_Pos 20 /*!< LUT chanel connected to OE_5 */ #define LAU_LM_OEMUX_OE6_Pos 24 /*!< LUT chanel connected to OE_6 */ #define LAU_LM_OEMUX_OE7_Pos 28 /*!< LUT chanel connected to OE_7 */ /* Bit field masks: */ #define LAU_LM_OEMUX_OE0_Msk 0x00000007UL /*!< LUT chanel connected to OE_0 */ #define LAU_LM_OEMUX_OE1_Msk 0x00000070UL /*!< LUT chanel connected to OE_1 */ #define LAU_LM_OEMUX_OE2_Msk 0x00000700UL /*!< LUT chanel connected to OE_2 */ #define LAU_LM_OEMUX_OE3_Msk 0x00007000UL /*!< LUT chanel connected to OE_3 */ #define LAU_LM_OEMUX_OE4_Msk 0x00070000UL /*!< LUT chanel connected to OE_4 */ #define LAU_LM_OEMUX_OE5_Msk 0x00700000UL /*!< LUT chanel connected to OE_5 */ #define LAU_LM_OEMUX_OE6_Msk 0x07000000UL /*!< LUT chanel connected to OE_6 */ #define LAU_LM_OEMUX_OE7_Msk 0x70000000UL /*!< LUT chanel connected to OE_7 */ /*-- LM: OECTL: LM_OE Control Register ------------------------------------------------------------------------*/ typedef struct { uint32_t OE0 :2; /*!< Type of OE0 */ uint32_t OE1 :2; /*!< Type of OE1 */ uint32_t OE2 :2; /*!< Type of OE2 */ uint32_t OE3 :2; /*!< Type of OE3 */ uint32_t OE4 :2; /*!< Type of OE4 */ uint32_t OE5 :2; /*!< Type of OE5 */ uint32_t OE6 :2; /*!< Type of OE6 */ uint32_t OE7 :2; /*!< Type of OE7 */ } _LAU_LM_OECTL_bits; /* Bit field positions: */ #define LAU_LM_OECTL_OE0_Pos 0 /*!< Type of OE0 */ #define LAU_LM_OECTL_OE1_Pos 2 /*!< Type of OE1 */ #define LAU_LM_OECTL_OE2_Pos 4 /*!< Type of OE2 */ #define LAU_LM_OECTL_OE3_Pos 6 /*!< Type of OE3 */ #define LAU_LM_OECTL_OE4_Pos 8 /*!< Type of OE4 */ #define LAU_LM_OECTL_OE5_Pos 10 /*!< Type of OE5 */ #define LAU_LM_OECTL_OE6_Pos 12 /*!< Type of OE6 */ #define LAU_LM_OECTL_OE7_Pos 14 /*!< Type of OE7 */ /* Bit field masks: */ #define LAU_LM_OECTL_OE0_Msk 0x00000003UL /*!< Type of OE0 */ #define LAU_LM_OECTL_OE1_Msk 0x0000000CUL /*!< Type of OE1 */ #define LAU_LM_OECTL_OE2_Msk 0x00000030UL /*!< Type of OE2 */ #define LAU_LM_OECTL_OE3_Msk 0x000000C0UL /*!< Type of OE3 */ #define LAU_LM_OECTL_OE4_Msk 0x00000300UL /*!< Type of OE4 */ #define LAU_LM_OECTL_OE5_Msk 0x00000C00UL /*!< Type of OE5 */ #define LAU_LM_OECTL_OE6_Msk 0x00003000UL /*!< Type of OE6 */ #define LAU_LM_OECTL_OE7_Msk 0x0000C000UL /*!< Type of OE7 */ /*-- LM: LUTMUX0: LUT0 Input Multiplexor Register -------------------------------------------------------------*/ typedef struct { uint32_t SEL0 :5; /*!< Input select for Gate0 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL1 :5; /*!< Input select for Gate1 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL2 :5; /*!< Input select for Gate2 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL3 :5; /*!< Input select for Gate3 */ } _LAU_LM_LUTMUX0_bits; /* Bit field positions: */ #define LAU_LM_LUTMUX0_SEL0_Pos 0 /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX0_SEL1_Pos 8 /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX0_SEL2_Pos 16 /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX0_SEL3_Pos 24 /*!< Input select for Gate3 */ /* Bit field masks: */ #define LAU_LM_LUTMUX0_SEL0_Msk 0x0000001FUL /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX0_SEL1_Msk 0x00001F00UL /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX0_SEL2_Msk 0x001F0000UL /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX0_SEL3_Msk 0x1F000000UL /*!< Input select for Gate3 */ /*-- LM: LUTGATE0: LUT0 Gate Config Register ------------------------------------------------------------------*/ typedef struct { uint32_t GP0 :4; /*!< Gate 0 positive signal enable */ uint32_t GN0 :4; /*!< Gate 0 negative signal enable */ uint32_t GP1 :4; /*!< Gate 1 positive signal enable */ uint32_t GN1 :4; /*!< Gate 1 negative signal enable */ uint32_t GP2 :4; /*!< Gate 2 positive signal enable */ uint32_t GN2 :4; /*!< Gate 2 negative signal enable */ uint32_t GP3 :4; /*!< Gate 3 positive signal enable */ uint32_t GN3 :4; /*!< Gate 3 negative signal enable */ } _LAU_LM_LUTGATE0_bits; /* Bit field positions: */ #define LAU_LM_LUTGATE0_GP0_Pos 0 /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE0_GN0_Pos 4 /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE0_GP1_Pos 8 /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE0_GN1_Pos 12 /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE0_GP2_Pos 16 /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE0_GN2_Pos 20 /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE0_GP3_Pos 24 /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE0_GN3_Pos 28 /*!< Gate 3 negative signal enable */ /* Bit field masks: */ #define LAU_LM_LUTGATE0_GP0_Msk 0x0000000FUL /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE0_GN0_Msk 0x000000F0UL /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE0_GP1_Msk 0x00000F00UL /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE0_GN1_Msk 0x0000F000UL /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE0_GP2_Msk 0x000F0000UL /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE0_GN2_Msk 0x00F00000UL /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE0_GP3_Msk 0x0F000000UL /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE0_GN3_Msk 0xF0000000UL /*!< Gate 3 negative signal enable */ /*-- LM: LUTPLF0: LUT0 PLF Config Register --------------------------------------------------------------------*/ typedef struct { uint32_t EN :1; /*!< Enable LUT */ uint32_t MODE :3; /*!< Logical function select */ uint32_t INPOL0 :1; /*!< Input signal inverce */ uint32_t INPOL1 :1; /*!< Input signal inverce */ uint32_t INPOL2 :1; /*!< Input signal inverce */ uint32_t INPOL3 :1; /*!< Input signal inverce */ uint32_t LT :16; /*!< Logic Table bit 0 */ uint32_t OUTPOL :1; /*!< Output signal inverce */ } _LAU_LM_LUTPLF0_bits; /* Bit field positions: */ #define LAU_LM_LUTPLF0_EN_Pos 0 /*!< Enable LUT */ #define LAU_LM_LUTPLF0_MODE_Pos 1 /*!< Logical function select */ #define LAU_LM_LUTPLF0_INPOL0_Pos 4 /*!< Input signal inverce */ #define LAU_LM_LUTPLF0_INPOL1_Pos 5 /*!< Input signal inverce */ #define LAU_LM_LUTPLF0_INPOL2_Pos 6 /*!< Input signal inverce */ #define LAU_LM_LUTPLF0_INPOL3_Pos 7 /*!< Input signal inverce */ #define LAU_LM_LUTPLF0_LT_Pos 8 /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF0_OUTPOL_Pos 24 /*!< Output signal inverce */ /* Bit field masks: */ #define LAU_LM_LUTPLF0_EN_Msk 0x00000001UL /*!< Enable LUT */ #define LAU_LM_LUTPLF0_MODE_Msk 0x0000000EUL /*!< Logical function select */ #define LAU_LM_LUTPLF0_INPOL0_Msk 0x00000010UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF0_INPOL1_Msk 0x00000020UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF0_INPOL2_Msk 0x00000040UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF0_INPOL3_Msk 0x00000080UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF0_LT_Msk 0x00FFFF00UL /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF0_OUTPOL_Msk 0x01000000UL /*!< Output signal inverce */ /*-- LM: LUTMUX1: LUT1 Input Multiplexor Register -------------------------------------------------------------*/ typedef struct { uint32_t SEL0 :5; /*!< Input select for Gate0 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL1 :5; /*!< Input select for Gate1 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL2 :5; /*!< Input select for Gate2 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL3 :5; /*!< Input select for Gate3 */ } _LAU_LM_LUTMUX1_bits; /* Bit field positions: */ #define LAU_LM_LUTMUX1_SEL0_Pos 0 /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX1_SEL1_Pos 8 /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX1_SEL2_Pos 16 /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX1_SEL3_Pos 24 /*!< Input select for Gate3 */ /* Bit field masks: */ #define LAU_LM_LUTMUX1_SEL0_Msk 0x0000001FUL /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX1_SEL1_Msk 0x00001F00UL /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX1_SEL2_Msk 0x001F0000UL /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX1_SEL3_Msk 0x1F000000UL /*!< Input select for Gate3 */ /*-- LM: LUTGATE1: LUT1 Gate Config Register ------------------------------------------------------------------*/ typedef struct { uint32_t GP0 :4; /*!< Gate 0 positive signal enable */ uint32_t GN0 :4; /*!< Gate 0 negative signal enable */ uint32_t GP1 :4; /*!< Gate 1 positive signal enable */ uint32_t GN1 :4; /*!< Gate 1 negative signal enable */ uint32_t GP2 :4; /*!< Gate 2 positive signal enable */ uint32_t GN2 :4; /*!< Gate 2 negative signal enable */ uint32_t GP3 :4; /*!< Gate 3 positive signal enable */ uint32_t GN3 :4; /*!< Gate 3 negative signal enable */ } _LAU_LM_LUTGATE1_bits; /* Bit field positions: */ #define LAU_LM_LUTGATE1_GP0_Pos 0 /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE1_GN0_Pos 4 /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE1_GP1_Pos 8 /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE1_GN1_Pos 12 /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE1_GP2_Pos 16 /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE1_GN2_Pos 20 /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE1_GP3_Pos 24 /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE1_GN3_Pos 28 /*!< Gate 3 negative signal enable */ /* Bit field masks: */ #define LAU_LM_LUTGATE1_GP0_Msk 0x0000000FUL /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE1_GN0_Msk 0x000000F0UL /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE1_GP1_Msk 0x00000F00UL /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE1_GN1_Msk 0x0000F000UL /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE1_GP2_Msk 0x000F0000UL /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE1_GN2_Msk 0x00F00000UL /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE1_GP3_Msk 0x0F000000UL /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE1_GN3_Msk 0xF0000000UL /*!< Gate 3 negative signal enable */ /*-- LM: LUTPLF1: LUT1 PLF Config Register --------------------------------------------------------------------*/ typedef struct { uint32_t EN :1; /*!< Enable LUT */ uint32_t MODE :3; /*!< Logical function select */ uint32_t INPOL0 :1; /*!< Input signal inverce */ uint32_t INPOL1 :1; /*!< Input signal inverce */ uint32_t INPOL2 :1; /*!< Input signal inverce */ uint32_t INPOL3 :1; /*!< Input signal inverce */ uint32_t LT :16; /*!< Logic Table bit 0 */ uint32_t OUTPOL :1; /*!< Output signal inverce */ } _LAU_LM_LUTPLF1_bits; /* Bit field positions: */ #define LAU_LM_LUTPLF1_EN_Pos 0 /*!< Enable LUT */ #define LAU_LM_LUTPLF1_MODE_Pos 1 /*!< Logical function select */ #define LAU_LM_LUTPLF1_INPOL0_Pos 4 /*!< Input signal inverce */ #define LAU_LM_LUTPLF1_INPOL1_Pos 5 /*!< Input signal inverce */ #define LAU_LM_LUTPLF1_INPOL2_Pos 6 /*!< Input signal inverce */ #define LAU_LM_LUTPLF1_INPOL3_Pos 7 /*!< Input signal inverce */ #define LAU_LM_LUTPLF1_LT_Pos 8 /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF1_OUTPOL_Pos 24 /*!< Output signal inverce */ /* Bit field masks: */ #define LAU_LM_LUTPLF1_EN_Msk 0x00000001UL /*!< Enable LUT */ #define LAU_LM_LUTPLF1_MODE_Msk 0x0000000EUL /*!< Logical function select */ #define LAU_LM_LUTPLF1_INPOL0_Msk 0x00000010UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF1_INPOL1_Msk 0x00000020UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF1_INPOL2_Msk 0x00000040UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF1_INPOL3_Msk 0x00000080UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF1_LT_Msk 0x00FFFF00UL /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF1_OUTPOL_Msk 0x01000000UL /*!< Output signal inverce */ /*-- LM: LUTMUX2: LUT2 Input Multiplexor Register -------------------------------------------------------------*/ typedef struct { uint32_t SEL0 :5; /*!< Input select for Gate0 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL1 :5; /*!< Input select for Gate1 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL2 :5; /*!< Input select for Gate2 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL3 :5; /*!< Input select for Gate3 */ } _LAU_LM_LUTMUX2_bits; /* Bit field positions: */ #define LAU_LM_LUTMUX2_SEL0_Pos 0 /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX2_SEL1_Pos 8 /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX2_SEL2_Pos 16 /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX2_SEL3_Pos 24 /*!< Input select for Gate3 */ /* Bit field masks: */ #define LAU_LM_LUTMUX2_SEL0_Msk 0x0000001FUL /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX2_SEL1_Msk 0x00001F00UL /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX2_SEL2_Msk 0x001F0000UL /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX2_SEL3_Msk 0x1F000000UL /*!< Input select for Gate3 */ /*-- LM: LUTGATE2: LUT2 Gate Config Register ------------------------------------------------------------------*/ typedef struct { uint32_t GP0 :4; /*!< Gate 0 positive signal enable */ uint32_t GN0 :4; /*!< Gate 0 negative signal enable */ uint32_t GP1 :4; /*!< Gate 1 positive signal enable */ uint32_t GN1 :4; /*!< Gate 1 negative signal enable */ uint32_t GP2 :4; /*!< Gate 2 positive signal enable */ uint32_t GN2 :4; /*!< Gate 2 negative signal enable */ uint32_t GP3 :4; /*!< Gate 3 positive signal enable */ uint32_t GN3 :4; /*!< Gate 3 negative signal enable */ } _LAU_LM_LUTGATE2_bits; /* Bit field positions: */ #define LAU_LM_LUTGATE2_GP0_Pos 0 /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE2_GN0_Pos 4 /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE2_GP1_Pos 8 /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE2_GN1_Pos 12 /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE2_GP2_Pos 16 /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE2_GN2_Pos 20 /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE2_GP3_Pos 24 /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE2_GN3_Pos 28 /*!< Gate 3 negative signal enable */ /* Bit field masks: */ #define LAU_LM_LUTGATE2_GP0_Msk 0x0000000FUL /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE2_GN0_Msk 0x000000F0UL /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE2_GP1_Msk 0x00000F00UL /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE2_GN1_Msk 0x0000F000UL /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE2_GP2_Msk 0x000F0000UL /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE2_GN2_Msk 0x00F00000UL /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE2_GP3_Msk 0x0F000000UL /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE2_GN3_Msk 0xF0000000UL /*!< Gate 3 negative signal enable */ /*-- LM: LUTPLF2: LUT2 PLF Config Register --------------------------------------------------------------------*/ typedef struct { uint32_t EN :1; /*!< Enable LUT */ uint32_t MODE :3; /*!< Logical function select */ uint32_t INPOL0 :1; /*!< Input signal inverce */ uint32_t INPOL1 :1; /*!< Input signal inverce */ uint32_t INPOL2 :1; /*!< Input signal inverce */ uint32_t INPOL3 :1; /*!< Input signal inverce */ uint32_t LT :16; /*!< Logic Table bit 0 */ uint32_t OUTPOL :1; /*!< Output signal inverce */ } _LAU_LM_LUTPLF2_bits; /* Bit field positions: */ #define LAU_LM_LUTPLF2_EN_Pos 0 /*!< Enable LUT */ #define LAU_LM_LUTPLF2_MODE_Pos 1 /*!< Logical function select */ #define LAU_LM_LUTPLF2_INPOL0_Pos 4 /*!< Input signal inverce */ #define LAU_LM_LUTPLF2_INPOL1_Pos 5 /*!< Input signal inverce */ #define LAU_LM_LUTPLF2_INPOL2_Pos 6 /*!< Input signal inverce */ #define LAU_LM_LUTPLF2_INPOL3_Pos 7 /*!< Input signal inverce */ #define LAU_LM_LUTPLF2_LT_Pos 8 /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF2_OUTPOL_Pos 24 /*!< Output signal inverce */ /* Bit field masks: */ #define LAU_LM_LUTPLF2_EN_Msk 0x00000001UL /*!< Enable LUT */ #define LAU_LM_LUTPLF2_MODE_Msk 0x0000000EUL /*!< Logical function select */ #define LAU_LM_LUTPLF2_INPOL0_Msk 0x00000010UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF2_INPOL1_Msk 0x00000020UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF2_INPOL2_Msk 0x00000040UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF2_INPOL3_Msk 0x00000080UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF2_LT_Msk 0x00FFFF00UL /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF2_OUTPOL_Msk 0x01000000UL /*!< Output signal inverce */ /*-- LM: LUTMUX3: LUT3 Input Multiplexor Register -------------------------------------------------------------*/ typedef struct { uint32_t SEL0 :5; /*!< Input select for Gate0 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL1 :5; /*!< Input select for Gate1 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL2 :5; /*!< Input select for Gate2 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL3 :5; /*!< Input select for Gate3 */ } _LAU_LM_LUTMUX3_bits; /* Bit field positions: */ #define LAU_LM_LUTMUX3_SEL0_Pos 0 /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX3_SEL1_Pos 8 /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX3_SEL2_Pos 16 /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX3_SEL3_Pos 24 /*!< Input select for Gate3 */ /* Bit field masks: */ #define LAU_LM_LUTMUX3_SEL0_Msk 0x0000001FUL /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX3_SEL1_Msk 0x00001F00UL /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX3_SEL2_Msk 0x001F0000UL /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX3_SEL3_Msk 0x1F000000UL /*!< Input select for Gate3 */ /*-- LM: LUTGATE3: LUT3 Gate Config Register ------------------------------------------------------------------*/ typedef struct { uint32_t GP0 :4; /*!< Gate 0 positive signal enable */ uint32_t GN0 :4; /*!< Gate 0 negative signal enable */ uint32_t GP1 :4; /*!< Gate 1 positive signal enable */ uint32_t GN1 :4; /*!< Gate 1 negative signal enable */ uint32_t GP2 :4; /*!< Gate 2 positive signal enable */ uint32_t GN2 :4; /*!< Gate 2 negative signal enable */ uint32_t GP3 :4; /*!< Gate 3 positive signal enable */ uint32_t GN3 :4; /*!< Gate 3 negative signal enable */ } _LAU_LM_LUTGATE3_bits; /* Bit field positions: */ #define LAU_LM_LUTGATE3_GP0_Pos 0 /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE3_GN0_Pos 4 /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE3_GP1_Pos 8 /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE3_GN1_Pos 12 /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE3_GP2_Pos 16 /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE3_GN2_Pos 20 /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE3_GP3_Pos 24 /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE3_GN3_Pos 28 /*!< Gate 3 negative signal enable */ /* Bit field masks: */ #define LAU_LM_LUTGATE3_GP0_Msk 0x0000000FUL /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE3_GN0_Msk 0x000000F0UL /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE3_GP1_Msk 0x00000F00UL /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE3_GN1_Msk 0x0000F000UL /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE3_GP2_Msk 0x000F0000UL /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE3_GN2_Msk 0x00F00000UL /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE3_GP3_Msk 0x0F000000UL /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE3_GN3_Msk 0xF0000000UL /*!< Gate 3 negative signal enable */ /*-- LM: LUTPLF3: LUT3 PLF Config Register --------------------------------------------------------------------*/ typedef struct { uint32_t EN :1; /*!< Enable LUT */ uint32_t MODE :3; /*!< Logical function select */ uint32_t INPOL0 :1; /*!< Input signal inverce */ uint32_t INPOL1 :1; /*!< Input signal inverce */ uint32_t INPOL2 :1; /*!< Input signal inverce */ uint32_t INPOL3 :1; /*!< Input signal inverce */ uint32_t LT :16; /*!< Logic Table bit 0 */ uint32_t OUTPOL :1; /*!< Output signal inverce */ } _LAU_LM_LUTPLF3_bits; /* Bit field positions: */ #define LAU_LM_LUTPLF3_EN_Pos 0 /*!< Enable LUT */ #define LAU_LM_LUTPLF3_MODE_Pos 1 /*!< Logical function select */ #define LAU_LM_LUTPLF3_INPOL0_Pos 4 /*!< Input signal inverce */ #define LAU_LM_LUTPLF3_INPOL1_Pos 5 /*!< Input signal inverce */ #define LAU_LM_LUTPLF3_INPOL2_Pos 6 /*!< Input signal inverce */ #define LAU_LM_LUTPLF3_INPOL3_Pos 7 /*!< Input signal inverce */ #define LAU_LM_LUTPLF3_LT_Pos 8 /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF3_OUTPOL_Pos 24 /*!< Output signal inverce */ /* Bit field masks: */ #define LAU_LM_LUTPLF3_EN_Msk 0x00000001UL /*!< Enable LUT */ #define LAU_LM_LUTPLF3_MODE_Msk 0x0000000EUL /*!< Logical function select */ #define LAU_LM_LUTPLF3_INPOL0_Msk 0x00000010UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF3_INPOL1_Msk 0x00000020UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF3_INPOL2_Msk 0x00000040UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF3_INPOL3_Msk 0x00000080UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF3_LT_Msk 0x00FFFF00UL /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF3_OUTPOL_Msk 0x01000000UL /*!< Output signal inverce */ /*-- LM: LUTMUX4: LUT4 Input Multiplexor Register -------------------------------------------------------------*/ typedef struct { uint32_t SEL0 :5; /*!< Input select for Gate0 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL1 :5; /*!< Input select for Gate1 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL2 :5; /*!< Input select for Gate2 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL3 :5; /*!< Input select for Gate3 */ } _LAU_LM_LUTMUX4_bits; /* Bit field positions: */ #define LAU_LM_LUTMUX4_SEL0_Pos 0 /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX4_SEL1_Pos 8 /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX4_SEL2_Pos 16 /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX4_SEL3_Pos 24 /*!< Input select for Gate3 */ /* Bit field masks: */ #define LAU_LM_LUTMUX4_SEL0_Msk 0x0000001FUL /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX4_SEL1_Msk 0x00001F00UL /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX4_SEL2_Msk 0x001F0000UL /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX4_SEL3_Msk 0x1F000000UL /*!< Input select for Gate3 */ /*-- LM: LUTGATE4: LUT4 Gate Config Register ------------------------------------------------------------------*/ typedef struct { uint32_t GP0 :4; /*!< Gate 0 positive signal enable */ uint32_t GN0 :4; /*!< Gate 0 negative signal enable */ uint32_t GP1 :4; /*!< Gate 1 positive signal enable */ uint32_t GN1 :4; /*!< Gate 1 negative signal enable */ uint32_t GP2 :4; /*!< Gate 2 positive signal enable */ uint32_t GN2 :4; /*!< Gate 2 negative signal enable */ uint32_t GP3 :4; /*!< Gate 3 positive signal enable */ uint32_t GN3 :4; /*!< Gate 3 negative signal enable */ } _LAU_LM_LUTGATE4_bits; /* Bit field positions: */ #define LAU_LM_LUTGATE4_GP0_Pos 0 /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE4_GN0_Pos 4 /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE4_GP1_Pos 8 /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE4_GN1_Pos 12 /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE4_GP2_Pos 16 /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE4_GN2_Pos 20 /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE4_GP3_Pos 24 /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE4_GN3_Pos 28 /*!< Gate 3 negative signal enable */ /* Bit field masks: */ #define LAU_LM_LUTGATE4_GP0_Msk 0x0000000FUL /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE4_GN0_Msk 0x000000F0UL /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE4_GP1_Msk 0x00000F00UL /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE4_GN1_Msk 0x0000F000UL /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE4_GP2_Msk 0x000F0000UL /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE4_GN2_Msk 0x00F00000UL /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE4_GP3_Msk 0x0F000000UL /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE4_GN3_Msk 0xF0000000UL /*!< Gate 3 negative signal enable */ /*-- LM: LUTPLF4: LUT4 PLF Config Register --------------------------------------------------------------------*/ typedef struct { uint32_t EN :1; /*!< Enable LUT */ uint32_t MODE :3; /*!< Logical function select */ uint32_t INPOL0 :1; /*!< Input signal inverce */ uint32_t INPOL1 :1; /*!< Input signal inverce */ uint32_t INPOL2 :1; /*!< Input signal inverce */ uint32_t INPOL3 :1; /*!< Input signal inverce */ uint32_t LT :16; /*!< Logic Table bit 0 */ uint32_t OUTPOL :1; /*!< Output signal inverce */ } _LAU_LM_LUTPLF4_bits; /* Bit field positions: */ #define LAU_LM_LUTPLF4_EN_Pos 0 /*!< Enable LUT */ #define LAU_LM_LUTPLF4_MODE_Pos 1 /*!< Logical function select */ #define LAU_LM_LUTPLF4_INPOL0_Pos 4 /*!< Input signal inverce */ #define LAU_LM_LUTPLF4_INPOL1_Pos 5 /*!< Input signal inverce */ #define LAU_LM_LUTPLF4_INPOL2_Pos 6 /*!< Input signal inverce */ #define LAU_LM_LUTPLF4_INPOL3_Pos 7 /*!< Input signal inverce */ #define LAU_LM_LUTPLF4_LT_Pos 8 /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF4_OUTPOL_Pos 24 /*!< Output signal inverce */ /* Bit field masks: */ #define LAU_LM_LUTPLF4_EN_Msk 0x00000001UL /*!< Enable LUT */ #define LAU_LM_LUTPLF4_MODE_Msk 0x0000000EUL /*!< Logical function select */ #define LAU_LM_LUTPLF4_INPOL0_Msk 0x00000010UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF4_INPOL1_Msk 0x00000020UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF4_INPOL2_Msk 0x00000040UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF4_INPOL3_Msk 0x00000080UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF4_LT_Msk 0x00FFFF00UL /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF4_OUTPOL_Msk 0x01000000UL /*!< Output signal inverce */ /*-- LM: LUTMUX5: LUT5 Input Multiplexor Register -------------------------------------------------------------*/ typedef struct { uint32_t SEL0 :5; /*!< Input select for Gate0 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL1 :5; /*!< Input select for Gate1 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL2 :5; /*!< Input select for Gate2 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL3 :5; /*!< Input select for Gate3 */ } _LAU_LM_LUTMUX5_bits; /* Bit field positions: */ #define LAU_LM_LUTMUX5_SEL0_Pos 0 /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX5_SEL1_Pos 8 /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX5_SEL2_Pos 16 /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX5_SEL3_Pos 24 /*!< Input select for Gate3 */ /* Bit field masks: */ #define LAU_LM_LUTMUX5_SEL0_Msk 0x0000001FUL /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX5_SEL1_Msk 0x00001F00UL /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX5_SEL2_Msk 0x001F0000UL /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX5_SEL3_Msk 0x1F000000UL /*!< Input select for Gate3 */ /*-- LM: LUTGATE5: LUT5 Gate Config Register ------------------------------------------------------------------*/ typedef struct { uint32_t GP0 :4; /*!< Gate 0 positive signal enable */ uint32_t GN0 :4; /*!< Gate 0 negative signal enable */ uint32_t GP1 :4; /*!< Gate 1 positive signal enable */ uint32_t GN1 :4; /*!< Gate 1 negative signal enable */ uint32_t GP2 :4; /*!< Gate 2 positive signal enable */ uint32_t GN2 :4; /*!< Gate 2 negative signal enable */ uint32_t GP3 :4; /*!< Gate 3 positive signal enable */ uint32_t GN3 :4; /*!< Gate 3 negative signal enable */ } _LAU_LM_LUTGATE5_bits; /* Bit field positions: */ #define LAU_LM_LUTGATE5_GP0_Pos 0 /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE5_GN0_Pos 4 /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE5_GP1_Pos 8 /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE5_GN1_Pos 12 /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE5_GP2_Pos 16 /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE5_GN2_Pos 20 /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE5_GP3_Pos 24 /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE5_GN3_Pos 28 /*!< Gate 3 negative signal enable */ /* Bit field masks: */ #define LAU_LM_LUTGATE5_GP0_Msk 0x0000000FUL /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE5_GN0_Msk 0x000000F0UL /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE5_GP1_Msk 0x00000F00UL /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE5_GN1_Msk 0x0000F000UL /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE5_GP2_Msk 0x000F0000UL /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE5_GN2_Msk 0x00F00000UL /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE5_GP3_Msk 0x0F000000UL /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE5_GN3_Msk 0xF0000000UL /*!< Gate 3 negative signal enable */ /*-- LM: LUTPLF5: LUT5 PLF Config Register --------------------------------------------------------------------*/ typedef struct { uint32_t EN :1; /*!< Enable LUT */ uint32_t MODE :3; /*!< Logical function select */ uint32_t INPOL0 :1; /*!< Input signal inverce */ uint32_t INPOL1 :1; /*!< Input signal inverce */ uint32_t INPOL2 :1; /*!< Input signal inverce */ uint32_t INPOL3 :1; /*!< Input signal inverce */ uint32_t LT :16; /*!< Logic Table bit 0 */ uint32_t OUTPOL :1; /*!< Output signal inverce */ } _LAU_LM_LUTPLF5_bits; /* Bit field positions: */ #define LAU_LM_LUTPLF5_EN_Pos 0 /*!< Enable LUT */ #define LAU_LM_LUTPLF5_MODE_Pos 1 /*!< Logical function select */ #define LAU_LM_LUTPLF5_INPOL0_Pos 4 /*!< Input signal inverce */ #define LAU_LM_LUTPLF5_INPOL1_Pos 5 /*!< Input signal inverce */ #define LAU_LM_LUTPLF5_INPOL2_Pos 6 /*!< Input signal inverce */ #define LAU_LM_LUTPLF5_INPOL3_Pos 7 /*!< Input signal inverce */ #define LAU_LM_LUTPLF5_LT_Pos 8 /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF5_OUTPOL_Pos 24 /*!< Output signal inverce */ /* Bit field masks: */ #define LAU_LM_LUTPLF5_EN_Msk 0x00000001UL /*!< Enable LUT */ #define LAU_LM_LUTPLF5_MODE_Msk 0x0000000EUL /*!< Logical function select */ #define LAU_LM_LUTPLF5_INPOL0_Msk 0x00000010UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF5_INPOL1_Msk 0x00000020UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF5_INPOL2_Msk 0x00000040UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF5_INPOL3_Msk 0x00000080UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF5_LT_Msk 0x00FFFF00UL /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF5_OUTPOL_Msk 0x01000000UL /*!< Output signal inverce */ /*-- LM: LUTMUX6: LUT6 Input Multiplexor Register -------------------------------------------------------------*/ typedef struct { uint32_t SEL0 :5; /*!< Input select for Gate0 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL1 :5; /*!< Input select for Gate1 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL2 :5; /*!< Input select for Gate2 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL3 :5; /*!< Input select for Gate3 */ } _LAU_LM_LUTMUX6_bits; /* Bit field positions: */ #define LAU_LM_LUTMUX6_SEL0_Pos 0 /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX6_SEL1_Pos 8 /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX6_SEL2_Pos 16 /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX6_SEL3_Pos 24 /*!< Input select for Gate3 */ /* Bit field masks: */ #define LAU_LM_LUTMUX6_SEL0_Msk 0x0000001FUL /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX6_SEL1_Msk 0x00001F00UL /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX6_SEL2_Msk 0x001F0000UL /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX6_SEL3_Msk 0x1F000000UL /*!< Input select for Gate3 */ /*-- LM: LUTGATE6: LUT6 Gate Config Register ------------------------------------------------------------------*/ typedef struct { uint32_t GP0 :4; /*!< Gate 0 positive signal enable */ uint32_t GN0 :4; /*!< Gate 0 negative signal enable */ uint32_t GP1 :4; /*!< Gate 1 positive signal enable */ uint32_t GN1 :4; /*!< Gate 1 negative signal enable */ uint32_t GP2 :4; /*!< Gate 2 positive signal enable */ uint32_t GN2 :4; /*!< Gate 2 negative signal enable */ uint32_t GP3 :4; /*!< Gate 3 positive signal enable */ uint32_t GN3 :4; /*!< Gate 3 negative signal enable */ } _LAU_LM_LUTGATE6_bits; /* Bit field positions: */ #define LAU_LM_LUTGATE6_GP0_Pos 0 /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE6_GN0_Pos 4 /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE6_GP1_Pos 8 /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE6_GN1_Pos 12 /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE6_GP2_Pos 16 /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE6_GN2_Pos 20 /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE6_GP3_Pos 24 /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE6_GN3_Pos 28 /*!< Gate 3 negative signal enable */ /* Bit field masks: */ #define LAU_LM_LUTGATE6_GP0_Msk 0x0000000FUL /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE6_GN0_Msk 0x000000F0UL /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE6_GP1_Msk 0x00000F00UL /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE6_GN1_Msk 0x0000F000UL /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE6_GP2_Msk 0x000F0000UL /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE6_GN2_Msk 0x00F00000UL /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE6_GP3_Msk 0x0F000000UL /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE6_GN3_Msk 0xF0000000UL /*!< Gate 3 negative signal enable */ /*-- LM: LUTPLF6: LUT6 PLF Config Register --------------------------------------------------------------------*/ typedef struct { uint32_t EN :1; /*!< Enable LUT */ uint32_t MODE :3; /*!< Logical function select */ uint32_t INPOL0 :1; /*!< Input signal inverce */ uint32_t INPOL1 :1; /*!< Input signal inverce */ uint32_t INPOL2 :1; /*!< Input signal inverce */ uint32_t INPOL3 :1; /*!< Input signal inverce */ uint32_t LT :16; /*!< Logic Table bit 0 */ uint32_t OUTPOL :1; /*!< Output signal inverce */ } _LAU_LM_LUTPLF6_bits; /* Bit field positions: */ #define LAU_LM_LUTPLF6_EN_Pos 0 /*!< Enable LUT */ #define LAU_LM_LUTPLF6_MODE_Pos 1 /*!< Logical function select */ #define LAU_LM_LUTPLF6_INPOL0_Pos 4 /*!< Input signal inverce */ #define LAU_LM_LUTPLF6_INPOL1_Pos 5 /*!< Input signal inverce */ #define LAU_LM_LUTPLF6_INPOL2_Pos 6 /*!< Input signal inverce */ #define LAU_LM_LUTPLF6_INPOL3_Pos 7 /*!< Input signal inverce */ #define LAU_LM_LUTPLF6_LT_Pos 8 /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF6_OUTPOL_Pos 24 /*!< Output signal inverce */ /* Bit field masks: */ #define LAU_LM_LUTPLF6_EN_Msk 0x00000001UL /*!< Enable LUT */ #define LAU_LM_LUTPLF6_MODE_Msk 0x0000000EUL /*!< Logical function select */ #define LAU_LM_LUTPLF6_INPOL0_Msk 0x00000010UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF6_INPOL1_Msk 0x00000020UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF6_INPOL2_Msk 0x00000040UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF6_INPOL3_Msk 0x00000080UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF6_LT_Msk 0x00FFFF00UL /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF6_OUTPOL_Msk 0x01000000UL /*!< Output signal inverce */ /*-- LM: LUTMUX7: LUT7 Input Multiplexor Register -------------------------------------------------------------*/ typedef struct { uint32_t SEL0 :5; /*!< Input select for Gate0 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL1 :5; /*!< Input select for Gate1 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL2 :5; /*!< Input select for Gate2 */ uint32_t :3; /*!< RESERVED */ uint32_t SEL3 :5; /*!< Input select for Gate3 */ } _LAU_LM_LUTMUX7_bits; /* Bit field positions: */ #define LAU_LM_LUTMUX7_SEL0_Pos 0 /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX7_SEL1_Pos 8 /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX7_SEL2_Pos 16 /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX7_SEL3_Pos 24 /*!< Input select for Gate3 */ /* Bit field masks: */ #define LAU_LM_LUTMUX7_SEL0_Msk 0x0000001FUL /*!< Input select for Gate0 */ #define LAU_LM_LUTMUX7_SEL1_Msk 0x00001F00UL /*!< Input select for Gate1 */ #define LAU_LM_LUTMUX7_SEL2_Msk 0x001F0000UL /*!< Input select for Gate2 */ #define LAU_LM_LUTMUX7_SEL3_Msk 0x1F000000UL /*!< Input select for Gate3 */ /*-- LM: LUTGATE7: LUT7 Gate Config Register ------------------------------------------------------------------*/ typedef struct { uint32_t GP0 :4; /*!< Gate 0 positive signal enable */ uint32_t GN0 :4; /*!< Gate 0 negative signal enable */ uint32_t GP1 :4; /*!< Gate 1 positive signal enable */ uint32_t GN1 :4; /*!< Gate 1 negative signal enable */ uint32_t GP2 :4; /*!< Gate 2 positive signal enable */ uint32_t GN2 :4; /*!< Gate 2 negative signal enable */ uint32_t GP3 :4; /*!< Gate 3 positive signal enable */ uint32_t GN3 :4; /*!< Gate 3 negative signal enable */ } _LAU_LM_LUTGATE7_bits; /* Bit field positions: */ #define LAU_LM_LUTGATE7_GP0_Pos 0 /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE7_GN0_Pos 4 /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE7_GP1_Pos 8 /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE7_GN1_Pos 12 /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE7_GP2_Pos 16 /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE7_GN2_Pos 20 /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE7_GP3_Pos 24 /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE7_GN3_Pos 28 /*!< Gate 3 negative signal enable */ /* Bit field masks: */ #define LAU_LM_LUTGATE7_GP0_Msk 0x0000000FUL /*!< Gate 0 positive signal enable */ #define LAU_LM_LUTGATE7_GN0_Msk 0x000000F0UL /*!< Gate 0 negative signal enable */ #define LAU_LM_LUTGATE7_GP1_Msk 0x00000F00UL /*!< Gate 1 positive signal enable */ #define LAU_LM_LUTGATE7_GN1_Msk 0x0000F000UL /*!< Gate 1 negative signal enable */ #define LAU_LM_LUTGATE7_GP2_Msk 0x000F0000UL /*!< Gate 2 positive signal enable */ #define LAU_LM_LUTGATE7_GN2_Msk 0x00F00000UL /*!< Gate 2 negative signal enable */ #define LAU_LM_LUTGATE7_GP3_Msk 0x0F000000UL /*!< Gate 3 positive signal enable */ #define LAU_LM_LUTGATE7_GN3_Msk 0xF0000000UL /*!< Gate 3 negative signal enable */ /*-- LM: LUTPLF7: LUT7 PLF Config Register --------------------------------------------------------------------*/ typedef struct { uint32_t EN :1; /*!< Enable LUT */ uint32_t MODE :3; /*!< Logical function select */ uint32_t INPOL0 :1; /*!< Input signal inverce */ uint32_t INPOL1 :1; /*!< Input signal inverce */ uint32_t INPOL2 :1; /*!< Input signal inverce */ uint32_t INPOL3 :1; /*!< Input signal inverce */ uint32_t LT :16; /*!< Logic Table bit 0 */ uint32_t OUTPOL :1; /*!< Output signal inverce */ } _LAU_LM_LUTPLF7_bits; /* Bit field positions: */ #define LAU_LM_LUTPLF7_EN_Pos 0 /*!< Enable LUT */ #define LAU_LM_LUTPLF7_MODE_Pos 1 /*!< Logical function select */ #define LAU_LM_LUTPLF7_INPOL0_Pos 4 /*!< Input signal inverce */ #define LAU_LM_LUTPLF7_INPOL1_Pos 5 /*!< Input signal inverce */ #define LAU_LM_LUTPLF7_INPOL2_Pos 6 /*!< Input signal inverce */ #define LAU_LM_LUTPLF7_INPOL3_Pos 7 /*!< Input signal inverce */ #define LAU_LM_LUTPLF7_LT_Pos 8 /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF7_OUTPOL_Pos 24 /*!< Output signal inverce */ /* Bit field masks: */ #define LAU_LM_LUTPLF7_EN_Msk 0x00000001UL /*!< Enable LUT */ #define LAU_LM_LUTPLF7_MODE_Msk 0x0000000EUL /*!< Logical function select */ #define LAU_LM_LUTPLF7_INPOL0_Msk 0x00000010UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF7_INPOL1_Msk 0x00000020UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF7_INPOL2_Msk 0x00000040UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF7_INPOL3_Msk 0x00000080UL /*!< Input signal inverce */ #define LAU_LM_LUTPLF7_LT_Msk 0x00FFFF00UL /*!< Logic Table bit 0 */ #define LAU_LM_LUTPLF7_OUTPOL_Msk 0x01000000UL /*!< Output signal inverce */ //Cluster LM: typedef struct { union { /*!< Clock Control Register */ __IO uint32_t CLKCTL; /*!< CLKCTL : type used for word access */ __IO _LAU_LM_CLKCTL_bits CLKCTL_bit; /*!< CLKCTL_bit: structure used for bit access */ }; union { /*!< Interrupt Selection Register */ __IO uint32_t INTSEL; /*!< INTSEL : type used for word access */ __IO _LAU_LM_INTSEL_bits INTSEL_bit; /*!< INTSEL_bit: structure used for bit access */ }; union { /*!< LM_BUS Signal Selection Register */ __IO uint32_t BUSSEL; /*!< BUSSEL : type used for word access */ __IO _LAU_LM_BUSSEL_bits BUSSEL_bit; /*!< BUSSEL_bit: structure used for bit access */ }; union { /*!< LM_OUT Selection Register */ __IO uint32_t OUTMUX; /*!< OUTMUX : type used for word access */ __IO _LAU_LM_OUTMUX_bits OUTMUX_bit; /*!< OUTMUX_bit: structure used for bit access */ }; union { /*!< LM_OE Selection Register */ __IO uint32_t OEMUX; /*!< OEMUX : type used for word access */ __IO _LAU_LM_OEMUX_bits OEMUX_bit; /*!< OEMUX_bit: structure used for bit access */ }; union { /*!< LM_OE Control Register */ __IO uint32_t OECTL; /*!< OECTL : type used for word access */ __IO _LAU_LM_OECTL_bits OECTL_bit; /*!< OECTL_bit: structure used for bit access */ }; union { /*!< LUT0 Input Multiplexor Register */ __IO uint32_t LUTMUX0; /*!< LUTMUX0 : type used for word access */ __IO _LAU_LM_LUTMUX0_bits LUTMUX0_bit; /*!< LUTMUX0_bit: structure used for bit access */ }; union { /*!< LUT0 Gate Config Register */ __IO uint32_t LUTGATE0; /*!< LUTGATE0 : type used for word access */ __IO _LAU_LM_LUTGATE0_bits LUTGATE0_bit; /*!< LUTGATE0_bit: structure used for bit access */ }; union { /*!< LUT0 PLF Config Register */ __IO uint32_t LUTPLF0; /*!< LUTPLF0 : type used for word access */ __IO _LAU_LM_LUTPLF0_bits LUTPLF0_bit; /*!< LUTPLF0_bit: structure used for bit access */ }; union { /*!< LUT1 Input Multiplexor Register */ __IO uint32_t LUTMUX1; /*!< LUTMUX1 : type used for word access */ __IO _LAU_LM_LUTMUX1_bits LUTMUX1_bit; /*!< LUTMUX1_bit: structure used for bit access */ }; union { /*!< LUT1 Gate Config Register */ __IO uint32_t LUTGATE1; /*!< LUTGATE1 : type used for word access */ __IO _LAU_LM_LUTGATE1_bits LUTGATE1_bit; /*!< LUTGATE1_bit: structure used for bit access */ }; union { /*!< LUT1 PLF Config Register */ __IO uint32_t LUTPLF1; /*!< LUTPLF1 : type used for word access */ __IO _LAU_LM_LUTPLF1_bits LUTPLF1_bit; /*!< LUTPLF1_bit: structure used for bit access */ }; union { /*!< LUT2 Input Multiplexor Register */ __IO uint32_t LUTMUX2; /*!< LUTMUX2 : type used for word access */ __IO _LAU_LM_LUTMUX2_bits LUTMUX2_bit; /*!< LUTMUX2_bit: structure used for bit access */ }; union { /*!< LUT2 Gate Config Register */ __IO uint32_t LUTGATE2; /*!< LUTGATE2 : type used for word access */ __IO _LAU_LM_LUTGATE2_bits LUTGATE2_bit; /*!< LUTGATE2_bit: structure used for bit access */ }; union { /*!< LUT2 PLF Config Register */ __IO uint32_t LUTPLF2; /*!< LUTPLF2 : type used for word access */ __IO _LAU_LM_LUTPLF2_bits LUTPLF2_bit; /*!< LUTPLF2_bit: structure used for bit access */ }; union { /*!< LUT3 Input Multiplexor Register */ __IO uint32_t LUTMUX3; /*!< LUTMUX3 : type used for word access */ __IO _LAU_LM_LUTMUX3_bits LUTMUX3_bit; /*!< LUTMUX3_bit: structure used for bit access */ }; union { /*!< LUT3 Gate Config Register */ __IO uint32_t LUTGATE3; /*!< LUTGATE3 : type used for word access */ __IO _LAU_LM_LUTGATE3_bits LUTGATE3_bit; /*!< LUTGATE3_bit: structure used for bit access */ }; union { /*!< LUT3 PLF Config Register */ __IO uint32_t LUTPLF3; /*!< LUTPLF3 : type used for word access */ __IO _LAU_LM_LUTPLF3_bits LUTPLF3_bit; /*!< LUTPLF3_bit: structure used for bit access */ }; union { /*!< LUT4 Input Multiplexor Register */ __IO uint32_t LUTMUX4; /*!< LUTMUX4 : type used for word access */ __IO _LAU_LM_LUTMUX4_bits LUTMUX4_bit; /*!< LUTMUX4_bit: structure used for bit access */ }; union { /*!< LUT4 Gate Config Register */ __IO uint32_t LUTGATE4; /*!< LUTGATE4 : type used for word access */ __IO _LAU_LM_LUTGATE4_bits LUTGATE4_bit; /*!< LUTGATE4_bit: structure used for bit access */ }; union { /*!< LUT4 PLF Config Register */ __IO uint32_t LUTPLF4; /*!< LUTPLF4 : type used for word access */ __IO _LAU_LM_LUTPLF4_bits LUTPLF4_bit; /*!< LUTPLF4_bit: structure used for bit access */ }; union { /*!< LUT5 Input Multiplexor Register */ __IO uint32_t LUTMUX5; /*!< LUTMUX5 : type used for word access */ __IO _LAU_LM_LUTMUX5_bits LUTMUX5_bit; /*!< LUTMUX5_bit: structure used for bit access */ }; union { /*!< LUT5 Gate Config Register */ __IO uint32_t LUTGATE5; /*!< LUTGATE5 : type used for word access */ __IO _LAU_LM_LUTGATE5_bits LUTGATE5_bit; /*!< LUTGATE5_bit: structure used for bit access */ }; union { /*!< LUT5 PLF Config Register */ __IO uint32_t LUTPLF5; /*!< LUTPLF5 : type used for word access */ __IO _LAU_LM_LUTPLF5_bits LUTPLF5_bit; /*!< LUTPLF5_bit: structure used for bit access */ }; union { /*!< LUT6 Input Multiplexor Register */ __IO uint32_t LUTMUX6; /*!< LUTMUX6 : type used for word access */ __IO _LAU_LM_LUTMUX6_bits LUTMUX6_bit; /*!< LUTMUX6_bit: structure used for bit access */ }; union { /*!< LUT6 Gate Config Register */ __IO uint32_t LUTGATE6; /*!< LUTGATE6 : type used for word access */ __IO _LAU_LM_LUTGATE6_bits LUTGATE6_bit; /*!< LUTGATE6_bit: structure used for bit access */ }; union { /*!< LUT6 PLF Config Register */ __IO uint32_t LUTPLF6; /*!< LUTPLF6 : type used for word access */ __IO _LAU_LM_LUTPLF6_bits LUTPLF6_bit; /*!< LUTPLF6_bit: structure used for bit access */ }; union { /*!< LUT7 Input Multiplexor Register */ __IO uint32_t LUTMUX7; /*!< LUTMUX7 : type used for word access */ __IO _LAU_LM_LUTMUX7_bits LUTMUX7_bit; /*!< LUTMUX7_bit: structure used for bit access */ }; union { /*!< LUT7 Gate Config Register */ __IO uint32_t LUTGATE7; /*!< LUTGATE7 : type used for word access */ __IO _LAU_LM_LUTGATE7_bits LUTGATE7_bit; /*!< LUTGATE7_bit: structure used for bit access */ }; union { /*!< LUT7 PLF Config Register */ __IO uint32_t LUTPLF7; /*!< LUTPLF7 : type used for word access */ __IO _LAU_LM_LUTPLF7_bits LUTPLF7_bit; /*!< LUTPLF7_bit: structure used for bit access */ }; } _LAU_LM_TypeDef; typedef struct { union { /*!< Interrupt control register */ __IO uint32_t INTCTL; /*!< INTCTL : type used for word access */ __IO _LAU_INTCTL_bits INTCTL_bit; /*!< INTCTL_bit: structure used for bit access */ }; union { /*!< Interrupt Mask Set/Clear Register */ __IO uint32_t IMSC; /*!< IMSC : type used for word access */ __IO _LAU_IMSC_bits IMSC_bit; /*!< IMSC_bit: structure used for bit access */ }; union { /*!< Raw Interrupt Status Register */ __I uint32_t RIS; /*!< RIS : type used for word access */ __I _LAU_RIS_bits RIS_bit; /*!< RIS_bit: structure used for bit access */ }; union { /*!< Masked Interrupt Status Register */ __I uint32_t MIS; /*!< MIS : type used for word access */ __I _LAU_MIS_bits MIS_bit; /*!< MIS_bit: structure used for bit access */ }; union { /*!< Interrupt Clear Register */ __O uint32_t ICR; /*!< ICR : type used for word access */ __O _LAU_ICR_bits ICR_bit; /*!< ICR_bit: structure used for bit access */ }; __IO uint32_t Reserved0[3]; _LAU_LM_TypeDef LM[8]; } LAU_TypeDef; /******************************************************************************/ /* SDFM registers */ /******************************************************************************/ /*-- IFLG: Interrupt Flag Register ---------------------------------------------------------------------------*/ typedef struct { uint32_t IFL0 :1; /*!< Comparator filter 0 output is equal to or below the low level threshold */ uint32_t IFL1 :1; /*!< Comparator filter 1 output is equal to or below the low level threshold */ uint32_t IFL2 :1; /*!< Comparator filter 2 output is equal to or below the low level threshold */ uint32_t IFL3 :1; /*!< Comparator filter 3 output is equal to or below the low level threshold */ uint32_t IFH0 :1; /*!< Comparator filter 0 output is equal to or above the high level threshold */ uint32_t IFH1 :1; /*!< Comparator filter 1 output is equal to or above the high level threshold */ uint32_t IFH2 :1; /*!< Comparator filter 2 output is equal to or above the high level threshold */ uint32_t IFH3 :1; /*!< Comparator filter 3 output is equal to or above the high level threshold */ uint32_t IFHZ0 :1; /*!< Comparator filter 0 output is equal to or above the zero level threshold */ uint32_t IFHZ1 :1; /*!< Comparator filter 1 output is equal to or above the zero level threshold */ uint32_t IFHZ2 :1; /*!< Comparator filter 2 output is equal to or above the zero level threshold */ uint32_t IFHZ3 :1; /*!< Comparator filter 3 output is equal to or above the zero level threshold */ uint32_t MF0 :1; /*!< Modulator failure filter 0 */ uint32_t MF1 :1; /*!< Modulator failure filter 1 */ uint32_t MF2 :1; /*!< Modulator failure filter 2 */ uint32_t MF3 :1; /*!< Modulator failure filter 3 */ uint32_t AF0 :1; /*!< New data available from filter 0 */ uint32_t AF1 :1; /*!< New data available from filter 1 */ uint32_t AF2 :1; /*!< New data available from filter 2 */ uint32_t AF3 :1; /*!< New data available from filter 3 */ uint32_t OV0 :1; /*!< Overflow FIFO0 error flag */ uint32_t OV1 :1; /*!< Overflow FIFO1 error flag */ uint32_t OV2 :1; /*!< Overflow FIFO2 error flag */ uint32_t OV3 :1; /*!< Overflow FIFO3 error flag */ uint32_t FDR0 :1; /*!< FIFO0 data ready flag */ uint32_t FDR1 :1; /*!< FIFO1 data ready flag */ uint32_t FDR2 :1; /*!< FIFO2 data ready flag */ uint32_t FDR3 :1; /*!< FIFO3 data ready flag */ uint32_t :3; /*!< RESERVED */ uint32_t MIF :1; /*!< OR'ed flags OVx, MFx, IFHx, IFLx */ } _SDFM_IFLG_bits; /* Bit field positions: */ #define SDFM_IFLG_IFL0_Pos 0 /*!< Comparator filter 0 output is equal to or below the low level threshold */ #define SDFM_IFLG_IFL1_Pos 1 /*!< Comparator filter 1 output is equal to or below the low level threshold */ #define SDFM_IFLG_IFL2_Pos 2 /*!< Comparator filter 2 output is equal to or below the low level threshold */ #define SDFM_IFLG_IFL3_Pos 3 /*!< Comparator filter 3 output is equal to or below the low level threshold */ #define SDFM_IFLG_IFH0_Pos 4 /*!< Comparator filter 0 output is equal to or above the high level threshold */ #define SDFM_IFLG_IFH1_Pos 5 /*!< Comparator filter 1 output is equal to or above the high level threshold */ #define SDFM_IFLG_IFH2_Pos 6 /*!< Comparator filter 2 output is equal to or above the high level threshold */ #define SDFM_IFLG_IFH3_Pos 7 /*!< Comparator filter 3 output is equal to or above the high level threshold */ #define SDFM_IFLG_IFHZ0_Pos 8 /*!< Comparator filter 0 output is equal to or above the zero level threshold */ #define SDFM_IFLG_IFHZ1_Pos 9 /*!< Comparator filter 1 output is equal to or above the zero level threshold */ #define SDFM_IFLG_IFHZ2_Pos 10 /*!< Comparator filter 2 output is equal to or above the zero level threshold */ #define SDFM_IFLG_IFHZ3_Pos 11 /*!< Comparator filter 3 output is equal to or above the zero level threshold */ #define SDFM_IFLG_MF0_Pos 12 /*!< Modulator failure filter 0 */ #define SDFM_IFLG_MF1_Pos 13 /*!< Modulator failure filter 1 */ #define SDFM_IFLG_MF2_Pos 14 /*!< Modulator failure filter 2 */ #define SDFM_IFLG_MF3_Pos 15 /*!< Modulator failure filter 3 */ #define SDFM_IFLG_AF0_Pos 16 /*!< New data available from filter 0 */ #define SDFM_IFLG_AF1_Pos 17 /*!< New data available from filter 1 */ #define SDFM_IFLG_AF2_Pos 18 /*!< New data available from filter 2 */ #define SDFM_IFLG_AF3_Pos 19 /*!< New data available from filter 3 */ #define SDFM_IFLG_OV0_Pos 20 /*!< Overflow FIFO0 error flag */ #define SDFM_IFLG_OV1_Pos 21 /*!< Overflow FIFO1 error flag */ #define SDFM_IFLG_OV2_Pos 22 /*!< Overflow FIFO2 error flag */ #define SDFM_IFLG_OV3_Pos 23 /*!< Overflow FIFO3 error flag */ #define SDFM_IFLG_FDR0_Pos 24 /*!< FIFO0 data ready flag */ #define SDFM_IFLG_FDR1_Pos 25 /*!< FIFO1 data ready flag */ #define SDFM_IFLG_FDR2_Pos 26 /*!< FIFO2 data ready flag */ #define SDFM_IFLG_FDR3_Pos 27 /*!< FIFO3 data ready flag */ #define SDFM_IFLG_MIF_Pos 31 /*!< OR'ed flags OVx, MFx, IFHx, IFLx */ /* Bit field masks: */ #define SDFM_IFLG_IFL0_Msk 0x00000001UL /*!< Comparator filter 0 output is equal to or below the low level threshold */ #define SDFM_IFLG_IFL1_Msk 0x00000002UL /*!< Comparator filter 1 output is equal to or below the low level threshold */ #define SDFM_IFLG_IFL2_Msk 0x00000004UL /*!< Comparator filter 2 output is equal to or below the low level threshold */ #define SDFM_IFLG_IFL3_Msk 0x00000008UL /*!< Comparator filter 3 output is equal to or below the low level threshold */ #define SDFM_IFLG_IFH0_Msk 0x00000010UL /*!< Comparator filter 0 output is equal to or above the high level threshold */ #define SDFM_IFLG_IFH1_Msk 0x00000020UL /*!< Comparator filter 1 output is equal to or above the high level threshold */ #define SDFM_IFLG_IFH2_Msk 0x00000040UL /*!< Comparator filter 2 output is equal to or above the high level threshold */ #define SDFM_IFLG_IFH3_Msk 0x00000080UL /*!< Comparator filter 3 output is equal to or above the high level threshold */ #define SDFM_IFLG_IFHZ0_Msk 0x00000100UL /*!< Comparator filter 0 output is equal to or above the zero level threshold */ #define SDFM_IFLG_IFHZ1_Msk 0x00000200UL /*!< Comparator filter 1 output is equal to or above the zero level threshold */ #define SDFM_IFLG_IFHZ2_Msk 0x00000400UL /*!< Comparator filter 2 output is equal to or above the zero level threshold */ #define SDFM_IFLG_IFHZ3_Msk 0x00000800UL /*!< Comparator filter 3 output is equal to or above the zero level threshold */ #define SDFM_IFLG_MF0_Msk 0x00001000UL /*!< Modulator failure filter 0 */ #define SDFM_IFLG_MF1_Msk 0x00002000UL /*!< Modulator failure filter 1 */ #define SDFM_IFLG_MF2_Msk 0x00004000UL /*!< Modulator failure filter 2 */ #define SDFM_IFLG_MF3_Msk 0x00008000UL /*!< Modulator failure filter 3 */ #define SDFM_IFLG_AF0_Msk 0x00010000UL /*!< New data available from filter 0 */ #define SDFM_IFLG_AF1_Msk 0x00020000UL /*!< New data available from filter 1 */ #define SDFM_IFLG_AF2_Msk 0x00040000UL /*!< New data available from filter 2 */ #define SDFM_IFLG_AF3_Msk 0x00080000UL /*!< New data available from filter 3 */ #define SDFM_IFLG_OV0_Msk 0x00100000UL /*!< Overflow FIFO0 error flag */ #define SDFM_IFLG_OV1_Msk 0x00200000UL /*!< Overflow FIFO1 error flag */ #define SDFM_IFLG_OV2_Msk 0x00400000UL /*!< Overflow FIFO2 error flag */ #define SDFM_IFLG_OV3_Msk 0x00800000UL /*!< Overflow FIFO3 error flag */ #define SDFM_IFLG_FDR0_Msk 0x01000000UL /*!< FIFO0 data ready flag */ #define SDFM_IFLG_FDR1_Msk 0x02000000UL /*!< FIFO1 data ready flag */ #define SDFM_IFLG_FDR2_Msk 0x04000000UL /*!< FIFO2 data ready flag */ #define SDFM_IFLG_FDR3_Msk 0x08000000UL /*!< FIFO3 data ready flag */ #define SDFM_IFLG_MIF_Msk 0x80000000UL /*!< OR'ed flags OVx, MFx, IFHx, IFLx */ /*-- IFLGCLR: Clear Interrupt flag register ------------------------------------------------------------------*/ typedef struct { uint32_t IFL0 :1; /*!< Comparator filter 0 output is equal to or below the low level threshold clear bit */ uint32_t IFL1 :1; /*!< Comparator filter 1 output is equal to or below the low level threshold clear bit */ uint32_t IFL2 :1; /*!< Comparator filter 2 output is equal to or below the low level threshold clear bit */ uint32_t IFL3 :1; /*!< Comparator filter 3 output is equal to or below the low level threshold clear bit */ uint32_t IFH0 :1; /*!< Comparator filter 0 output is equal to or above the high level threshold clear bit */ uint32_t IFH1 :1; /*!< Comparator filter 1 output is equal to or above the high level threshold clear bit */ uint32_t IFH2 :1; /*!< Comparator filter 2 output is equal to or above the high level threshold clear bit */ uint32_t IFH3 :1; /*!< Comparator filter 3 output is equal to or above the high level threshold clear bit */ uint32_t IFHZ0 :1; /*!< Comparator filter 0 output is equal to or above the zero level threshold clear bit */ uint32_t IFHZ1 :1; /*!< Comparator filter 1 output is equal to or above the zero level threshold clear bit */ uint32_t IFHZ2 :1; /*!< Comparator filter 2 output is equal to or above the zero level threshold clear bit */ uint32_t IFHZ3 :1; /*!< Comparator filter 3 output is equal to or above the zero level threshold clear bit */ uint32_t MF0 :1; /*!< Modulator failure filter 0 clear bit */ uint32_t MF1 :1; /*!< Modulator failure filter 1 clear bit */ uint32_t MF2 :1; /*!< Modulator failure filter 2 clear bit */ uint32_t MF3 :1; /*!< Modulator failure filter 3 clear bit */ uint32_t AF0 :1; /*!< New data available from filter 0 clear bit */ uint32_t AF1 :1; /*!< New data available from filter 1 clear bit */ uint32_t AF2 :1; /*!< New data available from filter 2 clear bit */ uint32_t AF3 :1; /*!< New data available from filter 3 clear bit */ uint32_t OV0 :1; /*!< Overflow FIFO0 error flag clear bit */ uint32_t OV1 :1; /*!< Overflow FIFO1 error flag clear bit */ uint32_t OV2 :1; /*!< Overflow FIFO2 error flag clear bit */ uint32_t OV3 :1; /*!< Overflow FIFO3 error flag clear bit */ uint32_t FDR0 :1; /*!< FIFO0 data ready flag clear */ uint32_t FDR1 :1; /*!< FIFO1 data ready flag clear */ uint32_t FDR2 :1; /*!< FIFO2 data ready flag clear */ uint32_t FDR3 :1; /*!< FIFO3 data ready flag clear */ uint32_t :3; /*!< RESERVED */ uint32_t MIF :1; /*!< MIF flag clear bit */ } _SDFM_IFLGCLR_bits; /* Bit field positions: */ #define SDFM_IFLGCLR_IFL0_Pos 0 /*!< Comparator filter 0 output is equal to or below the low level threshold clear bit */ #define SDFM_IFLGCLR_IFL1_Pos 1 /*!< Comparator filter 1 output is equal to or below the low level threshold clear bit */ #define SDFM_IFLGCLR_IFL2_Pos 2 /*!< Comparator filter 2 output is equal to or below the low level threshold clear bit */ #define SDFM_IFLGCLR_IFL3_Pos 3 /*!< Comparator filter 3 output is equal to or below the low level threshold clear bit */ #define SDFM_IFLGCLR_IFH0_Pos 4 /*!< Comparator filter 0 output is equal to or above the high level threshold clear bit */ #define SDFM_IFLGCLR_IFH1_Pos 5 /*!< Comparator filter 1 output is equal to or above the high level threshold clear bit */ #define SDFM_IFLGCLR_IFH2_Pos 6 /*!< Comparator filter 2 output is equal to or above the high level threshold clear bit */ #define SDFM_IFLGCLR_IFH3_Pos 7 /*!< Comparator filter 3 output is equal to or above the high level threshold clear bit */ #define SDFM_IFLGCLR_IFHZ0_Pos 8 /*!< Comparator filter 0 output is equal to or above the zero level threshold clear bit */ #define SDFM_IFLGCLR_IFHZ1_Pos 9 /*!< Comparator filter 1 output is equal to or above the zero level threshold clear bit */ #define SDFM_IFLGCLR_IFHZ2_Pos 10 /*!< Comparator filter 2 output is equal to or above the zero level threshold clear bit */ #define SDFM_IFLGCLR_IFHZ3_Pos 11 /*!< Comparator filter 3 output is equal to or above the zero level threshold clear bit */ #define SDFM_IFLGCLR_MF0_Pos 12 /*!< Modulator failure filter 0 clear bit */ #define SDFM_IFLGCLR_MF1_Pos 13 /*!< Modulator failure filter 1 clear bit */ #define SDFM_IFLGCLR_MF2_Pos 14 /*!< Modulator failure filter 2 clear bit */ #define SDFM_IFLGCLR_MF3_Pos 15 /*!< Modulator failure filter 3 clear bit */ #define SDFM_IFLGCLR_AF0_Pos 16 /*!< New data available from filter 0 clear bit */ #define SDFM_IFLGCLR_AF1_Pos 17 /*!< New data available from filter 1 clear bit */ #define SDFM_IFLGCLR_AF2_Pos 18 /*!< New data available from filter 2 clear bit */ #define SDFM_IFLGCLR_AF3_Pos 19 /*!< New data available from filter 3 clear bit */ #define SDFM_IFLGCLR_OV0_Pos 20 /*!< Overflow FIFO0 error flag clear bit */ #define SDFM_IFLGCLR_OV1_Pos 21 /*!< Overflow FIFO1 error flag clear bit */ #define SDFM_IFLGCLR_OV2_Pos 22 /*!< Overflow FIFO2 error flag clear bit */ #define SDFM_IFLGCLR_OV3_Pos 23 /*!< Overflow FIFO3 error flag clear bit */ #define SDFM_IFLGCLR_FDR0_Pos 24 /*!< FIFO0 data ready flag clear */ #define SDFM_IFLGCLR_FDR1_Pos 25 /*!< FIFO1 data ready flag clear */ #define SDFM_IFLGCLR_FDR2_Pos 26 /*!< FIFO2 data ready flag clear */ #define SDFM_IFLGCLR_FDR3_Pos 27 /*!< FIFO3 data ready flag clear */ #define SDFM_IFLGCLR_MIF_Pos 31 /*!< MIF flag clear bit */ /* Bit field masks: */ #define SDFM_IFLGCLR_IFL0_Msk 0x00000001UL /*!< Comparator filter 0 output is equal to or below the low level threshold clear bit */ #define SDFM_IFLGCLR_IFL1_Msk 0x00000002UL /*!< Comparator filter 1 output is equal to or below the low level threshold clear bit */ #define SDFM_IFLGCLR_IFL2_Msk 0x00000004UL /*!< Comparator filter 2 output is equal to or below the low level threshold clear bit */ #define SDFM_IFLGCLR_IFL3_Msk 0x00000008UL /*!< Comparator filter 3 output is equal to or below the low level threshold clear bit */ #define SDFM_IFLGCLR_IFH0_Msk 0x00000010UL /*!< Comparator filter 0 output is equal to or above the high level threshold clear bit */ #define SDFM_IFLGCLR_IFH1_Msk 0x00000020UL /*!< Comparator filter 1 output is equal to or above the high level threshold clear bit */ #define SDFM_IFLGCLR_IFH2_Msk 0x00000040UL /*!< Comparator filter 2 output is equal to or above the high level threshold clear bit */ #define SDFM_IFLGCLR_IFH3_Msk 0x00000080UL /*!< Comparator filter 3 output is equal to or above the high level threshold clear bit */ #define SDFM_IFLGCLR_IFHZ0_Msk 0x00000100UL /*!< Comparator filter 0 output is equal to or above the zero level threshold clear bit */ #define SDFM_IFLGCLR_IFHZ1_Msk 0x00000200UL /*!< Comparator filter 1 output is equal to or above the zero level threshold clear bit */ #define SDFM_IFLGCLR_IFHZ2_Msk 0x00000400UL /*!< Comparator filter 2 output is equal to or above the zero level threshold clear bit */ #define SDFM_IFLGCLR_IFHZ3_Msk 0x00000800UL /*!< Comparator filter 3 output is equal to or above the zero level threshold clear bit */ #define SDFM_IFLGCLR_MF0_Msk 0x00001000UL /*!< Modulator failure filter 0 clear bit */ #define SDFM_IFLGCLR_MF1_Msk 0x00002000UL /*!< Modulator failure filter 1 clear bit */ #define SDFM_IFLGCLR_MF2_Msk 0x00004000UL /*!< Modulator failure filter 2 clear bit */ #define SDFM_IFLGCLR_MF3_Msk 0x00008000UL /*!< Modulator failure filter 3 clear bit */ #define SDFM_IFLGCLR_AF0_Msk 0x00010000UL /*!< New data available from filter 0 clear bit */ #define SDFM_IFLGCLR_AF1_Msk 0x00020000UL /*!< New data available from filter 1 clear bit */ #define SDFM_IFLGCLR_AF2_Msk 0x00040000UL /*!< New data available from filter 2 clear bit */ #define SDFM_IFLGCLR_AF3_Msk 0x00080000UL /*!< New data available from filter 3 clear bit */ #define SDFM_IFLGCLR_OV0_Msk 0x00100000UL /*!< Overflow FIFO0 error flag clear bit */ #define SDFM_IFLGCLR_OV1_Msk 0x00200000UL /*!< Overflow FIFO1 error flag clear bit */ #define SDFM_IFLGCLR_OV2_Msk 0x00400000UL /*!< Overflow FIFO2 error flag clear bit */ #define SDFM_IFLGCLR_OV3_Msk 0x00800000UL /*!< Overflow FIFO3 error flag clear bit */ #define SDFM_IFLGCLR_FDR0_Msk 0x01000000UL /*!< FIFO0 data ready flag clear */ #define SDFM_IFLGCLR_FDR1_Msk 0x02000000UL /*!< FIFO1 data ready flag clear */ #define SDFM_IFLGCLR_FDR2_Msk 0x04000000UL /*!< FIFO2 data ready flag clear */ #define SDFM_IFLGCLR_FDR3_Msk 0x08000000UL /*!< FIFO3 data ready flag clear */ #define SDFM_IFLGCLR_MIF_Msk 0x80000000UL /*!< MIF flag clear bit */ /*-- CFLG: Comparator Flag Register --------------------------------------------------------------------------*/ typedef struct { uint32_t CFL0 :1; /*!< */ uint32_t CFL1 :1; /*!< */ uint32_t CFL2 :1; /*!< */ uint32_t CFL3 :1; /*!< */ uint32_t CFH0 :1; /*!< */ uint32_t CFH1 :1; /*!< */ uint32_t CFH2 :1; /*!< */ uint32_t CFH3 :1; /*!< */ uint32_t CFHZ0 :1; /*!< */ uint32_t CFHZ1 :1; /*!< */ uint32_t CFHZ2 :1; /*!< */ uint32_t CFHZ3 :1; /*!< */ } _SDFM_CFLG_bits; /* Bit field positions: */ #define SDFM_CFLG_CFL0_Pos 0 /*!< */ #define SDFM_CFLG_CFL1_Pos 1 /*!< */ #define SDFM_CFLG_CFL2_Pos 2 /*!< */ #define SDFM_CFLG_CFL3_Pos 3 /*!< */ #define SDFM_CFLG_CFH0_Pos 4 /*!< */ #define SDFM_CFLG_CFH1_Pos 5 /*!< */ #define SDFM_CFLG_CFH2_Pos 6 /*!< */ #define SDFM_CFLG_CFH3_Pos 7 /*!< */ #define SDFM_CFLG_CFHZ0_Pos 8 /*!< */ #define SDFM_CFLG_CFHZ1_Pos 9 /*!< */ #define SDFM_CFLG_CFHZ2_Pos 10 /*!< */ #define SDFM_CFLG_CFHZ3_Pos 11 /*!< */ /* Bit field masks: */ #define SDFM_CFLG_CFL0_Msk 0x00000001UL /*!< */ #define SDFM_CFLG_CFL1_Msk 0x00000002UL /*!< */ #define SDFM_CFLG_CFL2_Msk 0x00000004UL /*!< */ #define SDFM_CFLG_CFL3_Msk 0x00000008UL /*!< */ #define SDFM_CFLG_CFH0_Msk 0x00000010UL /*!< */ #define SDFM_CFLG_CFH1_Msk 0x00000020UL /*!< */ #define SDFM_CFLG_CFH2_Msk 0x00000040UL /*!< */ #define SDFM_CFLG_CFH3_Msk 0x00000080UL /*!< */ #define SDFM_CFLG_CFHZ0_Msk 0x00000100UL /*!< */ #define SDFM_CFLG_CFHZ1_Msk 0x00000200UL /*!< */ #define SDFM_CFLG_CFHZ2_Msk 0x00000400UL /*!< */ #define SDFM_CFLG_CFHZ3_Msk 0x00000800UL /*!< */ /*-- CFLGCLR: Comparator Flag Clear Register -----------------------------------------------------------------*/ typedef struct { uint32_t CFL0 :1; /*!< */ uint32_t CFL1 :1; /*!< */ uint32_t CFL2 :1; /*!< */ uint32_t CFL3 :1; /*!< */ uint32_t CFH0 :1; /*!< */ uint32_t CFH1 :1; /*!< */ uint32_t CFH2 :1; /*!< */ uint32_t CFH3 :1; /*!< */ uint32_t CFHZ0 :1; /*!< */ uint32_t CFHZ1 :1; /*!< */ uint32_t CFHZ2 :1; /*!< */ uint32_t CFHZ3 :1; /*!< */ } _SDFM_CFLGCLR_bits; /* Bit field positions: */ #define SDFM_CFLGCLR_CFL0_Pos 0 /*!< */ #define SDFM_CFLGCLR_CFL1_Pos 1 /*!< */ #define SDFM_CFLGCLR_CFL2_Pos 2 /*!< */ #define SDFM_CFLGCLR_CFL3_Pos 3 /*!< */ #define SDFM_CFLGCLR_CFH0_Pos 4 /*!< */ #define SDFM_CFLGCLR_CFH1_Pos 5 /*!< */ #define SDFM_CFLGCLR_CFH2_Pos 6 /*!< */ #define SDFM_CFLGCLR_CFH3_Pos 7 /*!< */ #define SDFM_CFLGCLR_CFHZ0_Pos 8 /*!< */ #define SDFM_CFLGCLR_CFHZ1_Pos 9 /*!< */ #define SDFM_CFLGCLR_CFHZ2_Pos 10 /*!< */ #define SDFM_CFLGCLR_CFHZ3_Pos 11 /*!< */ /* Bit field masks: */ #define SDFM_CFLGCLR_CFL0_Msk 0x00000001UL /*!< */ #define SDFM_CFLGCLR_CFL1_Msk 0x00000002UL /*!< */ #define SDFM_CFLGCLR_CFL2_Msk 0x00000004UL /*!< */ #define SDFM_CFLGCLR_CFL3_Msk 0x00000008UL /*!< */ #define SDFM_CFLGCLR_CFH0_Msk 0x00000010UL /*!< */ #define SDFM_CFLGCLR_CFH1_Msk 0x00000020UL /*!< */ #define SDFM_CFLGCLR_CFH2_Msk 0x00000040UL /*!< */ #define SDFM_CFLGCLR_CFH3_Msk 0x00000080UL /*!< */ #define SDFM_CFLGCLR_CFHZ0_Msk 0x00000100UL /*!< */ #define SDFM_CFLGCLR_CFHZ1_Msk 0x00000200UL /*!< */ #define SDFM_CFLGCLR_CFHZ2_Msk 0x00000400UL /*!< */ #define SDFM_CFLGCLR_CFHZ3_Msk 0x00000800UL /*!< */ /*-- CTL: Control Register -----------------------------------------------------------------------------------*/ typedef struct { uint32_t MIE :1; /*!< Master interrupt enable */ } _SDFM_CTL_bits; /* Bit field positions: */ #define SDFM_CTL_MIE_Pos 0 /*!< Master interrupt enable */ /* Bit field masks: */ #define SDFM_CTL_MIE_Msk 0x00000001UL /*!< Master interrupt enable */ /*-- MFILEN: Master Filter Enable Register -------------------------------------------------------------------*/ typedef struct { uint32_t MFE :1; /*!< Master filter enable */ } _SDFM_MFILEN_bits; /* Bit field positions: */ #define SDFM_MFILEN_MFE_Pos 0 /*!< Master filter enable */ /* Bit field masks: */ #define SDFM_MFILEN_MFE_Msk 0x00000001UL /*!< Master filter enable */ /*-- SD: CTLPARM: Filter Control Register ---------------------------------------------------------------------*/ typedef struct { uint32_t MOD :2; /*!< Sigma Delta modulator IO mode */ uint32_t :2; /*!< RESERVED */ uint32_t MFIE :1; /*!< Modulator failure interrupt enable */ uint32_t :11; /*!< RESERVED */ uint32_t CORM3 :8; /*!< Clock out ratio for mode 3 */ } _SDFM_SD_CTLPARM_bits; /* Bit field positions: */ #define SDFM_SD_CTLPARM_MOD_Pos 0 /*!< Sigma Delta modulator IO mode */ #define SDFM_SD_CTLPARM_MFIE_Pos 4 /*!< Modulator failure interrupt enable */ #define SDFM_SD_CTLPARM_CORM3_Pos 16 /*!< Clock out ratio for mode 3 */ /* Bit field masks: */ #define SDFM_SD_CTLPARM_MOD_Msk 0x00000003UL /*!< Sigma Delta modulator IO mode */ #define SDFM_SD_CTLPARM_MFIE_Msk 0x00000010UL /*!< Modulator failure interrupt enable */ #define SDFM_SD_CTLPARM_CORM3_Msk 0x00FF0000UL /*!< Clock out ratio for mode 3 */ /* Bit field enums: */ typedef enum { SDFM_SD_CTLPARM_MOD_Mode0SDR = 0x0UL, /*!< single data rate */ SDFM_SD_CTLPARM_MOD_Mode1DDR = 0x1UL, /*!< double data rate */ SDFM_SD_CTLPARM_MOD_Mode2Manchester = 0x2UL, /*!< manchester coding */ SDFM_SD_CTLPARM_MOD_Mode3HDR = 0x3UL, /*!< half data rate */ } SDFM_SD_CTLPARM_MOD_Enum; /*-- SD: DFPARM: Data Filter Parameter Register ---------------------------------------------------------------*/ typedef struct { uint32_t DOSR :12; /*!< Oversampling ratio */ uint32_t FEN :1; /*!< Filter enable */ uint32_t AEN :1; /*!< Acknowledge enable */ uint32_t :2; /*!< RESERVED */ uint32_t SST :3; /*!< Data Filter structure */ uint32_t :5; /*!< RESERVED */ uint32_t ENSYN :1; /*!< Enable syncronization for filter */ } _SDFM_SD_DFPARM_bits; /* Bit field positions: */ #define SDFM_SD_DFPARM_DOSR_Pos 0 /*!< Oversampling ratio */ #define SDFM_SD_DFPARM_FEN_Pos 12 /*!< Filter enable */ #define SDFM_SD_DFPARM_AEN_Pos 13 /*!< Acknowledge enable */ #define SDFM_SD_DFPARM_SST_Pos 16 /*!< Data Filter structure */ #define SDFM_SD_DFPARM_ENSYN_Pos 24 /*!< Enable syncronization for filter */ /* Bit field masks: */ #define SDFM_SD_DFPARM_DOSR_Msk 0x00000FFFUL /*!< Oversampling ratio */ #define SDFM_SD_DFPARM_FEN_Msk 0x00001000UL /*!< Filter enable */ #define SDFM_SD_DFPARM_AEN_Msk 0x00002000UL /*!< Acknowledge enable */ #define SDFM_SD_DFPARM_SST_Msk 0x00070000UL /*!< Data Filter structure */ #define SDFM_SD_DFPARM_ENSYN_Msk 0x01000000UL /*!< Enable syncronization for filter */ /* Bit field enums: */ typedef enum { SDFM_SD_DFPARM_SST_FastSinc = 0x0UL, /*!< fastsinc */ SDFM_SD_DFPARM_SST_Sinc1 = 0x1UL, /*!< sinc 1-st order */ SDFM_SD_DFPARM_SST_Sinc2 = 0x2UL, /*!< sinc 2-nd order */ SDFM_SD_DFPARM_SST_Sinc3 = 0x3UL, /*!< sinc 3-rd order */ SDFM_SD_DFPARM_SST_Sinc4 = 0x4UL, /*!< sinc 4-th order */ SDFM_SD_DFPARM_SST_Sinc5 = 0x5UL, /*!< sinc 5-th order */ } SDFM_SD_DFPARM_SST_Enum; /*-- SD: DPARM: Shift Data Control Register -------------------------------------------------------------------*/ typedef struct { uint32_t SH :5; /*!< Shift control */ } _SDFM_SD_DPARM_bits; /* Bit field positions: */ #define SDFM_SD_DPARM_SH_Pos 0 /*!< Shift control */ /* Bit field masks: */ #define SDFM_SD_DPARM_SH_Msk 0x0000001FUL /*!< Shift control */ /*-- SD: CMPH: High Level Comparator Register -----------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Unsigned high-level threshold comparator */ } _SDFM_SD_CMPH_bits; /* Bit field positions: */ #define SDFM_SD_CMPH_VAL_Pos 0 /*!< Unsigned high-level threshold comparator */ /* Bit field masks: */ #define SDFM_SD_CMPH_VAL_Msk 0xFFFFFFFFUL /*!< Unsigned high-level threshold comparator */ /*-- SD: CMPHZ: Zero Level Comparator Register ----------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Unsigned zero-level threshold comparator */ } _SDFM_SD_CMPHZ_bits; /* Bit field positions: */ #define SDFM_SD_CMPHZ_VAL_Pos 0 /*!< Unsigned zero-level threshold comparator */ /* Bit field masks: */ #define SDFM_SD_CMPHZ_VAL_Msk 0xFFFFFFFFUL /*!< Unsigned zero-level threshold comparator */ /*-- SD: CMPL: Low Level Comparator Register ------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Unsigned low-level threshold comparator */ } _SDFM_SD_CMPL_bits; /* Bit field positions: */ #define SDFM_SD_CMPL_VAL_Pos 0 /*!< Unsigned low-level threshold comparator */ /* Bit field masks: */ #define SDFM_SD_CMPL_VAL_Msk 0xFFFFFFFFUL /*!< Unsigned low-level threshold comparator */ /*-- SD: CPARM: Comparator Parameter register -----------------------------------------------------------------*/ typedef struct { uint32_t COSR :12; /*!< Oversampling ratio for comparator */ uint32_t IEH :1; /*!< High-level interrupt enable */ uint32_t IEL :1; /*!< Low-level interrupt enable */ uint32_t IEHZ :1; /*!< Zero-level interrupt enable */ uint32_t :1; /*!< RESERVED */ uint32_t CS :3; /*!< Comparator filter structure */ uint32_t CEN :1; /*!< Comparator enable */ uint32_t HWLCLR :1; /*!< Enable hardware clear low threshold comparator exceed event */ uint32_t HWHCLR :1; /*!< Enable hardware clear high threshold comparator exceed event */ uint32_t HWHZCLR :1; /*!< Enable hardware clear zero threshold comparator exceed event */ } _SDFM_SD_CPARM_bits; /* Bit field positions: */ #define SDFM_SD_CPARM_COSR_Pos 0 /*!< Oversampling ratio for comparator */ #define SDFM_SD_CPARM_IEH_Pos 12 /*!< High-level interrupt enable */ #define SDFM_SD_CPARM_IEL_Pos 13 /*!< Low-level interrupt enable */ #define SDFM_SD_CPARM_IEHZ_Pos 14 /*!< Zero-level interrupt enable */ #define SDFM_SD_CPARM_CS_Pos 16 /*!< Comparator filter structure */ #define SDFM_SD_CPARM_CEN_Pos 19 /*!< Comparator enable */ #define SDFM_SD_CPARM_HWLCLR_Pos 20 /*!< Enable hardware clear low threshold comparator exceed event */ #define SDFM_SD_CPARM_HWHCLR_Pos 21 /*!< Enable hardware clear high threshold comparator exceed event */ #define SDFM_SD_CPARM_HWHZCLR_Pos 22 /*!< Enable hardware clear zero threshold comparator exceed event */ /* Bit field masks: */ #define SDFM_SD_CPARM_COSR_Msk 0x00000FFFUL /*!< Oversampling ratio for comparator */ #define SDFM_SD_CPARM_IEH_Msk 0x00001000UL /*!< High-level interrupt enable */ #define SDFM_SD_CPARM_IEL_Msk 0x00002000UL /*!< Low-level interrupt enable */ #define SDFM_SD_CPARM_IEHZ_Msk 0x00004000UL /*!< Zero-level interrupt enable */ #define SDFM_SD_CPARM_CS_Msk 0x00070000UL /*!< Comparator filter structure */ #define SDFM_SD_CPARM_CEN_Msk 0x00080000UL /*!< Comparator enable */ #define SDFM_SD_CPARM_HWLCLR_Msk 0x00100000UL /*!< Enable hardware clear low threshold comparator exceed event */ #define SDFM_SD_CPARM_HWHCLR_Msk 0x00200000UL /*!< Enable hardware clear high threshold comparator exceed event */ #define SDFM_SD_CPARM_HWHZCLR_Msk 0x00400000UL /*!< Enable hardware clear zero threshold comparator exceed event */ /*-- SD: DATA: Data Register ----------------------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Signed data value */ } _SDFM_SD_DATA_bits; /* Bit field positions: */ #define SDFM_SD_DATA_VAL_Pos 0 /*!< Signed data value */ /* Bit field masks: */ #define SDFM_SD_DATA_VAL_Msk 0xFFFFFFFFUL /*!< Signed data value */ /*-- SD: CDATA: Comparator Data Register ----------------------------------------------------------------------*/ typedef struct { uint32_t VAL :32; /*!< Comparator Data Value */ } _SDFM_SD_CDATA_bits; /* Bit field positions: */ #define SDFM_SD_CDATA_VAL_Pos 0 /*!< Comparator Data Value */ /* Bit field masks: */ #define SDFM_SD_CDATA_VAL_Msk 0xFFFFFFFFUL /*!< Comparator Data Value */ /*-- SD: FFCTL: FIFO Configuration Register -------------------------------------------------------------------*/ typedef struct { uint32_t IL :4; /*!< Interrupt level FIFO */ uint32_t :4; /*!< RESERVED */ uint32_t STAT :4; /*!< Status FIFO level */ uint32_t :4; /*!< RESERVED */ uint32_t EN :1; /*!< Enable FIFO */ uint32_t IEN :1; /*!< Interrupt FIFO enable */ uint32_t DRISEL :1; /*!< Data Ready Int source */ uint32_t OVFIEN :1; /*!< Overflow interrupt enable */ } _SDFM_SD_FFCTL_bits; /* Bit field positions: */ #define SDFM_SD_FFCTL_IL_Pos 0 /*!< Interrupt level FIFO */ #define SDFM_SD_FFCTL_STAT_Pos 8 /*!< Status FIFO level */ #define SDFM_SD_FFCTL_EN_Pos 16 /*!< Enable FIFO */ #define SDFM_SD_FFCTL_IEN_Pos 17 /*!< Interrupt FIFO enable */ #define SDFM_SD_FFCTL_DRISEL_Pos 18 /*!< Data Ready Int source */ #define SDFM_SD_FFCTL_OVFIEN_Pos 19 /*!< Overflow interrupt enable */ /* Bit field masks: */ #define SDFM_SD_FFCTL_IL_Msk 0x0000000FUL /*!< Interrupt level FIFO */ #define SDFM_SD_FFCTL_STAT_Msk 0x00000F00UL /*!< Status FIFO level */ #define SDFM_SD_FFCTL_EN_Msk 0x00010000UL /*!< Enable FIFO */ #define SDFM_SD_FFCTL_IEN_Msk 0x00020000UL /*!< Interrupt FIFO enable */ #define SDFM_SD_FFCTL_DRISEL_Msk 0x00040000UL /*!< Data Ready Int source */ #define SDFM_SD_FFCTL_OVFIEN_Msk 0x00080000UL /*!< Overflow interrupt enable */ /* Bit field enums: */ typedef enum { SDFM_SD_FFCTL_DRISEL_AckData = 0x0UL, /*!< acknowledge new data arrived */ SDFM_SD_FFCTL_DRISEL_FIFOData = 0x1UL, /*!< FIFO data level */ } SDFM_SD_FFCTL_DRISEL_Enum; /*-- SD: SYNC: Sync Control Register --------------------------------------------------------------------------*/ typedef struct { uint32_t SRC :3; /*!< Source syncronization selector for filter */ uint32_t :1; /*!< RESERVED */ uint32_t WTSEN :1; /*!< wait for sync enable */ uint32_t WTSCLREN :1; /*!< WTSFLG cleared on FIFO data ready interrupt enable */ uint32_t FFSCLREN :1; /*!< Clear FIFO on event enable */ uint32_t WTSFLG :1; /*!< Event flag */ uint32_t WTSFLGCLR :1; /*!< Clear WTSFLG manually writing 1 */ } _SDFM_SD_SYNC_bits; /* Bit field positions: */ #define SDFM_SD_SYNC_SRC_Pos 0 /*!< Source syncronization selector for filter */ #define SDFM_SD_SYNC_WTSEN_Pos 4 /*!< wait for sync enable */ #define SDFM_SD_SYNC_WTSCLREN_Pos 5 /*!< WTSFLG cleared on FIFO data ready interrupt enable */ #define SDFM_SD_SYNC_FFSCLREN_Pos 6 /*!< Clear FIFO on event enable */ #define SDFM_SD_SYNC_WTSFLG_Pos 7 /*!< Event flag */ #define SDFM_SD_SYNC_WTSFLGCLR_Pos 8 /*!< Clear WTSFLG manually writing 1 */ /* Bit field masks: */ #define SDFM_SD_SYNC_SRC_Msk 0x00000007UL /*!< Source syncronization selector for filter */ #define SDFM_SD_SYNC_WTSEN_Msk 0x00000010UL /*!< wait for sync enable */ #define SDFM_SD_SYNC_WTSCLREN_Msk 0x00000020UL /*!< WTSFLG cleared on FIFO data ready interrupt enable */ #define SDFM_SD_SYNC_FFSCLREN_Msk 0x00000040UL /*!< Clear FIFO on event enable */ #define SDFM_SD_SYNC_WTSFLG_Msk 0x00000080UL /*!< Event flag */ #define SDFM_SD_SYNC_WTSFLGCLR_Msk 0x00000100UL /*!< Clear WTSFLG manually writing 1 */ /* Bit field enums: */ typedef enum { SDFM_SD_SYNC_SRC_PWM012A = 0x0UL, /*!< PWM0,1,2 A channel request */ SDFM_SD_SYNC_SRC_PWM012B = 0x1UL, /*!< PWM0,1,2 B channel request */ SDFM_SD_SYNC_SRC_PWM345A = 0x2UL, /*!< PWM3,4,5 A channel request */ SDFM_SD_SYNC_SRC_PWM345B = 0x3UL, /*!< PWM3,4,5 B channel request */ SDFM_SD_SYNC_SRC_PWM6789A = 0x4UL, /*!< PWM6,7,8,9 A channel request */ SDFM_SD_SYNC_SRC_PWM6789B = 0x5UL, /*!< PWM6,7,8,9 B channel request */ SDFM_SD_SYNC_SRC_TMR0 = 0x6UL, /*!< Timer 0 request */ SDFM_SD_SYNC_SRC_TMR1 = 0x7UL, /*!< Timer 1 request */ } SDFM_SD_SYNC_SRC_Enum; /*-- SD: DMACTL: DMA Control Register -------------------------------------------------------------------------*/ typedef struct { uint32_t LVL :4; /*!< Level FIFO data for DMA */ uint32_t :27; /*!< RESERVED */ uint32_t EN :1; /*!< Enable DMA */ } _SDFM_SD_DMACTL_bits; /* Bit field positions: */ #define SDFM_SD_DMACTL_LVL_Pos 0 /*!< Level FIFO data for DMA */ #define SDFM_SD_DMACTL_EN_Pos 31 /*!< Enable DMA */ /* Bit field masks: */ #define SDFM_SD_DMACTL_LVL_Msk 0x0000000FUL /*!< Level FIFO data for DMA */ #define SDFM_SD_DMACTL_EN_Msk 0x80000000UL /*!< Enable DMA */ //Cluster SD: typedef struct { union { /*!< Filter Control Register */ __IO uint32_t CTLPARM; /*!< CTLPARM : type used for word access */ __IO _SDFM_SD_CTLPARM_bits CTLPARM_bit; /*!< CTLPARM_bit: structure used for bit access */ }; union { /*!< Data Filter Parameter Register */ __IO uint32_t DFPARM; /*!< DFPARM : type used for word access */ __IO _SDFM_SD_DFPARM_bits DFPARM_bit; /*!< DFPARM_bit: structure used for bit access */ }; union { /*!< Shift Data Control Register */ __IO uint32_t DPARM; /*!< DPARM : type used for word access */ __IO _SDFM_SD_DPARM_bits DPARM_bit; /*!< DPARM_bit: structure used for bit access */ }; union { /*!< High Level Comparator Register */ __IO uint32_t CMPH; /*!< CMPH : type used for word access */ __IO _SDFM_SD_CMPH_bits CMPH_bit; /*!< CMPH_bit: structure used for bit access */ }; union { /*!< Zero Level Comparator Register */ __IO uint32_t CMPHZ; /*!< CMPHZ : type used for word access */ __IO _SDFM_SD_CMPHZ_bits CMPHZ_bit; /*!< CMPHZ_bit: structure used for bit access */ }; union { /*!< Low Level Comparator Register */ __IO uint32_t CMPL; /*!< CMPL : type used for word access */ __IO _SDFM_SD_CMPL_bits CMPL_bit; /*!< CMPL_bit: structure used for bit access */ }; union { /*!< Comparator Parameter register */ __IO uint32_t CPARM; /*!< CPARM : type used for word access */ __IO _SDFM_SD_CPARM_bits CPARM_bit; /*!< CPARM_bit: structure used for bit access */ }; union { /*!< Data Register */ __I uint32_t DATA; /*!< DATA : type used for word access */ __I _SDFM_SD_DATA_bits DATA_bit; /*!< DATA_bit: structure used for bit access */ }; union { /*!< Comparator Data Register */ __I uint32_t CDATA; /*!< CDATA : type used for word access */ __I _SDFM_SD_CDATA_bits CDATA_bit; /*!< CDATA_bit: structure used for bit access */ }; union { /*!< FIFO Configuration Register */ __IO uint32_t FFCTL; /*!< FFCTL : type used for word access */ __IO _SDFM_SD_FFCTL_bits FFCTL_bit; /*!< FFCTL_bit: structure used for bit access */ }; union { /*!< Sync Control Register */ __IO uint32_t SYNC; /*!< SYNC : type used for word access */ __IO _SDFM_SD_SYNC_bits SYNC_bit; /*!< SYNC_bit: structure used for bit access */ }; union { /*!< DMA Control Register */ __IO uint32_t DMACTL; /*!< DMACTL : type used for word access */ __IO _SDFM_SD_DMACTL_bits DMACTL_bit; /*!< DMACTL_bit: structure used for bit access */ }; } _SDFM_SD_TypeDef; typedef struct { union { /*!< Interrupt Flag Register */ __I uint32_t IFLG; /*!< IFLG : type used for word access */ __I _SDFM_IFLG_bits IFLG_bit; /*!< IFLG_bit: structure used for bit access */ }; union { /*!< Clear Interrupt flag register */ __O uint32_t IFLGCLR; /*!< IFLGCLR : type used for word access */ __O _SDFM_IFLGCLR_bits IFLGCLR_bit; /*!< IFLGCLR_bit: structure used for bit access */ }; union { /*!< Comparator Flag Register */ __I uint32_t CFLG; /*!< CFLG : type used for word access */ __I _SDFM_CFLG_bits CFLG_bit; /*!< CFLG_bit: structure used for bit access */ }; union { /*!< Comparator Flag Clear Register */ __O uint32_t CFLGCLR; /*!< CFLGCLR : type used for word access */ __O _SDFM_CFLGCLR_bits CFLGCLR_bit; /*!< CFLGCLR_bit: structure used for bit access */ }; union { /*!< Control Register */ __IO uint32_t CTL; /*!< CTL : type used for word access */ __IO _SDFM_CTL_bits CTL_bit; /*!< CTL_bit: structure used for bit access */ }; union { /*!< Master Filter Enable Register */ __IO uint32_t MFILEN; /*!< MFILEN : type used for word access */ __IO _SDFM_MFILEN_bits MFILEN_bit; /*!< MFILEN_bit: structure used for bit access */ }; _SDFM_SD_TypeDef SD[4]; } SDFM_TypeDef; /* -------------------- End of section using anonymous unions ------------------- */ #if defined(__CC_ARM) #pragma pop #elif defined(__ICCARM__) /* leave anonymous unions enabled */ #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__TMS470__) /* anonymous unions are enabled by default */ #elif defined(__TASKING__) #pragma warning restore #elif defined (__CMCPPARM__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /******************************************************************************/ /* Peripheral memory map */ /******************************************************************************/ #define GPIOA_BASE (0x40010000UL) #define GPIOB_BASE (0x40011000UL) #define GPIOC_BASE (0x40012000UL) #define GPIOD_BASE (0x40013000UL) #define GPIOE_BASE (0x40014000UL) #define GPIOF_BASE (0x40015000UL) #define GPIOG_BASE (0x40016000UL) #define GPIOH_BASE (0x40017000UL) #define GPIOJ_BASE (0x40018000UL) #define GPIOK_BASE (0x40019000UL) #define GPIOL_BASE (0x4001A000UL) #define GPIOM_BASE (0x4001B000UL) #define CAN_BASE (0x40020000UL) #define CANMSG_BASE (0x40021000UL) #define ETH_BASE (0x40030000UL) #define TMU_BASE (0x40040000UL) #define MFLASH_BASE (0x40060000UL) #define BFLASH_BASE (0x40061000UL) #define EXTMEM_BASE (0x40062000UL) #define SPWR0_BASE (0x40070000UL) #define SPWR1_BASE (0x40071000UL) #define MILSTD0_BASE (0x40072000UL) #define MILSTD1_BASE (0x40073000UL) #define SPWRTMR_BASE (0x40074000UL) #define SDFM_BASE (0x40075000UL) #define SIU_BASE (0x40080000UL) #define RCU_BASE (0x40081000UL) #define PMU_BASE (0x40082000UL) #define WDT_BASE (0x40083000UL) #define DMA_BASE (0x40084000UL) #define UART0_BASE (0x40085000UL) #define UART1_BASE (0x40086000UL) #define UART2_BASE (0x40087000UL) #define UART3_BASE (0x40088000UL) #define TUART0_BASE (0x40089000UL) #define TUART1_BASE (0x4008A000UL) #define I2C0_BASE (0x4008B000UL) #define I2C1_BASE (0x4008C000UL) #define SPI0_BASE (0x4008D000UL) #define SPI1_BASE (0x4008E000UL) #define SPI2_BASE (0x4008F000UL) #define SPI3_BASE (0x40090000UL) #define TMR0_BASE (0x40091000UL) #define TMR1_BASE (0x40092000UL) #define TMR2_BASE (0x40093000UL) #define TMR3_BASE (0x40094000UL) #define ETMR0_BASE (0x40095000UL) #define ETMR1_BASE (0x40096000UL) #define ETMR2_BASE (0x40097000UL) #define ETMR3_BASE (0x40098000UL) #define RTC_BASE (0x40099000UL) #define ECAP0_BASE (0x4009A000UL) #define ECAP1_BASE (0x4009B000UL) #define ECAP2_BASE (0x4009C000UL) #define ECAP3_BASE (0x4009D000UL) #define ECAP4_BASE (0x4009E000UL) #define ECAP5_BASE (0x4009F000UL) #define PWM0_BASE (0x400A0000UL) #define PWM1_BASE (0x400A1000UL) #define PWM2_BASE (0x400A2000UL) #define PWM3_BASE (0x400A3000UL) #define PWM4_BASE (0x400A4000UL) #define PWM5_BASE (0x400A5000UL) #define PWM6_BASE (0x400A6000UL) #define PWM7_BASE (0x400A7000UL) #define PWM8_BASE (0x400A8000UL) #define PWM9_BASE (0x400A9000UL) #define QEP0_BASE (0x400AA000UL) #define QEP1_BASE (0x400AB000UL) #define QEP2_BASE (0x400AC000UL) #define QEP3_BASE (0x400AD000UL) #define LAU_BASE (0x400AE000UL) #define OWI0_BASE (0x400AF000UL) #define OWI1_BASE (0x400B0000UL) #define ADC_BASE (0x400B1000UL) /******************************************************************************/ /* Peripheral declaration */ /******************************************************************************/ #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) #define GPIOL ((GPIO_TypeDef *) GPIOL_BASE) #define GPIOM ((GPIO_TypeDef *) GPIOM_BASE) #define CAN ((CAN_TypeDef *) CAN_BASE) #define CANMSG ((CANMSG_TypeDef *) CANMSG_BASE) #define ETH ((ETH_TypeDef *) ETH_BASE) #define TMU ((TMU_TypeDef *) TMU_BASE) #define MFLASH ((MFLASH_TypeDef *) MFLASH_BASE) #define BFLASH ((BFLASH_TypeDef *) BFLASH_BASE) #define EXTMEM ((EXTMEM_TypeDef *) EXTMEM_BASE) #define SPWR0 ((SPWR_TypeDef *) SPWR0_BASE) #define SPWR1 ((SPWR_TypeDef *) SPWR1_BASE) #define MILSTD0 ((MILSTD_TypeDef *) MILSTD0_BASE) #define MILSTD1 ((MILSTD_TypeDef *) MILSTD1_BASE) #define SPWRTMR ((SPWRTMR_TypeDef *) SPWRTMR_BASE) #define SDFM ((SDFM_TypeDef *) SDFM_BASE) #define SIU ((SIU_TypeDef *) SIU_BASE) #define RCU ((RCU_TypeDef *) RCU_BASE) #define PMU ((PMU_TypeDef *) PMU_BASE) #define WDT ((WDT_TypeDef *) WDT_BASE) #define DMA ((DMA_TypeDef *) DMA_BASE) #define UART0 ((UART_TypeDef *) UART0_BASE) #define UART1 ((UART_TypeDef *) UART1_BASE) #define UART2 ((UART_TypeDef *) UART2_BASE) #define UART3 ((UART_TypeDef *) UART3_BASE) #define TUART0 ((TUART_TypeDef *) TUART0_BASE) #define TUART1 ((TUART_TypeDef *) TUART1_BASE) #define I2C0 ((I2C_TypeDef *) I2C0_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define SPI0 ((SPI_TypeDef *) SPI0_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define SPI3 ((SPI_TypeDef *) SPI3_BASE) #define TMR0 ((TMR_TypeDef *) TMR0_BASE) #define TMR1 ((TMR_TypeDef *) TMR1_BASE) #define TMR2 ((TMR_TypeDef *) TMR2_BASE) #define TMR3 ((TMR_TypeDef *) TMR3_BASE) #define ETMR0 ((ETMR_TypeDef *) ETMR0_BASE) #define ETMR1 ((ETMR_TypeDef *) ETMR1_BASE) #define ETMR2 ((ETMR_TypeDef *) ETMR2_BASE) #define ETMR3 ((ETMR_TypeDef *) ETMR3_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define ECAP0 ((ECAP_TypeDef *) ECAP0_BASE) #define ECAP1 ((ECAP_TypeDef *) ECAP1_BASE) #define ECAP2 ((ECAP_TypeDef *) ECAP2_BASE) #define ECAP3 ((ECAP_TypeDef *) ECAP3_BASE) #define ECAP4 ((ECAP_TypeDef *) ECAP4_BASE) #define ECAP5 ((ECAP_TypeDef *) ECAP5_BASE) #define PWM0 ((PWM_TypeDef *) PWM0_BASE) #define PWM1 ((PWM_TypeDef *) PWM1_BASE) #define PWM2 ((PWM_TypeDef *) PWM2_BASE) #define PWM3 ((PWM_TypeDef *) PWM3_BASE) #define PWM4 ((PWM_TypeDef *) PWM4_BASE) #define PWM5 ((PWM_TypeDef *) PWM5_BASE) #define PWM6 ((PWM_TypeDef *) PWM6_BASE) #define PWM7 ((PWM_TypeDef *) PWM7_BASE) #define PWM8 ((PWM_TypeDef *) PWM8_BASE) #define PWM9 ((PWM_TypeDef *) PWM9_BASE) #define QEP0 ((QEP_TypeDef *) QEP0_BASE) #define QEP1 ((QEP_TypeDef *) QEP1_BASE) #define QEP2 ((QEP_TypeDef *) QEP2_BASE) #define QEP3 ((QEP_TypeDef *) QEP3_BASE) #define LAU ((LAU_TypeDef *) LAU_BASE) #define OWI0 ((OWI_TypeDef *) OWI0_BASE) #define OWI1 ((OWI_TypeDef *) OWI1_BASE) #define ADC ((ADC_TypeDef *) ADC_BASE) /******************************************************************************/ /* Peripheral capabilities */ /******************************************************************************/ #define GPIO_PRESENT #define GPIO_TOTAL 12 typedef enum { GPIOA_Num, GPIOB_Num, GPIOC_Num, GPIOD_Num, GPIOE_Num, GPIOF_Num, GPIOG_Num, GPIOH_Num, GPIOJ_Num, GPIOK_Num, GPIOL_Num, GPIOM_Num } GPIO_Num_TypeDef; #define CAN_PRESENT #define CAN_TOTAL 1 typedef enum { CAN_Num } CAN_Num_TypeDef; #define CANMSG_PRESENT #define CANMSG_TOTAL 1 typedef enum { CANMSG_Num } CANMSG_Num_TypeDef; #define ETH_PRESENT #define ETH_TOTAL 1 typedef enum { ETH_Num } ETH_Num_TypeDef; #define TMU_PRESENT #define TMU_TOTAL 1 typedef enum { TMU_Num } TMU_Num_TypeDef; #define MFLASH_PRESENT #define MFLASH_TOTAL 1 typedef enum { MFLASH_Num } MFLASH_Num_TypeDef; #define BFLASH_PRESENT #define BFLASH_TOTAL 1 typedef enum { BFLASH_Num } BFLASH_Num_TypeDef; #define EXTMEM_PRESENT #define EXTMEM_TOTAL 1 typedef enum { EXTMEM_Num } EXTMEM_Num_TypeDef; #define SPWR_PRESENT #define SPWR_TOTAL 2 typedef enum { SPWR0_Num, SPWR1_Num } SPWR_Num_TypeDef; #define MILSTD_PRESENT #define MILSTD_TOTAL 2 typedef enum { MILSTD0_Num, MILSTD1_Num } MILSTD_Num_TypeDef; #define SPWRTMR_PRESENT #define SPWRTMR_TOTAL 1 typedef enum { SPWRTMR_Num } SPWRTMR_Num_TypeDef; #define SDFM_PRESENT #define SDFM_TOTAL 1 typedef enum { SDFM_Num } SDFM_Num_TypeDef; #define SIU_PRESENT #define SIU_TOTAL 1 typedef enum { SIU_Num } SIU_Num_TypeDef; #define RCU_PRESENT #define RCU_TOTAL 1 typedef enum { RCU_Num } RCU_Num_TypeDef; #define PMU_PRESENT #define PMU_TOTAL 1 typedef enum { PMU_Num } PMU_Num_TypeDef; #define WDT_PRESENT #define WDT_TOTAL 1 typedef enum { WDT_Num } WDT_Num_TypeDef; #define DMA_PRESENT #define DMA_TOTAL 1 typedef enum { DMA_Num } DMA_Num_TypeDef; #define UART_PRESENT #define UART_TOTAL 4 typedef enum { UART0_Num, UART1_Num, UART2_Num, UART3_Num } UART_Num_TypeDef; #define TUART_PRESENT #define TUART_TOTAL 2 typedef enum { TUART0_Num, TUART1_Num } TUART_Num_TypeDef; #define I2C_PRESENT #define I2C_TOTAL 2 typedef enum { I2C0_Num, I2C1_Num } I2C_Num_TypeDef; #define SPI_PRESENT #define SPI_TOTAL 4 typedef enum { SPI0_Num, SPI1_Num, SPI2_Num, SPI3_Num } SPI_Num_TypeDef; #define TMR_PRESENT #define TMR_TOTAL 4 typedef enum { TMR0_Num, TMR1_Num, TMR2_Num, TMR3_Num } TMR_Num_TypeDef; #define ETMR_PRESENT #define ETMR_TOTAL 4 typedef enum { ETMR0_Num, ETMR1_Num, ETMR2_Num, ETMR3_Num } ETMR_Num_TypeDef; #define RTC_PRESENT #define RTC_TOTAL 1 typedef enum { RTC_Num } RTC_Num_TypeDef; #define ECAP_PRESENT #define ECAP_TOTAL 6 typedef enum { ECAP0_Num, ECAP1_Num, ECAP2_Num, ECAP3_Num, ECAP4_Num, ECAP5_Num } ECAP_Num_TypeDef; #define PWM_PRESENT #define PWM_TOTAL 10 typedef enum { PWM0_Num, PWM1_Num, PWM2_Num, PWM3_Num, PWM4_Num, PWM5_Num, PWM6_Num, PWM7_Num, PWM8_Num, PWM9_Num } PWM_Num_TypeDef; #define QEP_PRESENT #define QEP_TOTAL 4 typedef enum { QEP0_Num, QEP1_Num, QEP2_Num, QEP3_Num } QEP_Num_TypeDef; #define LAU_PRESENT #define LAU_TOTAL 1 typedef enum { LAU_Num } LAU_Num_TypeDef; #define OWI_PRESENT #define OWI_TOTAL 2 typedef enum { OWI0_Num, OWI1_Num } OWI_Num_TypeDef; #define ADC_PRESENT #define ADC_TOTAL 1 typedef enum { ADC_Num } ADC_Num_TypeDef; /******************************************************************************/ /* Peripheral assertions */ /******************************************************************************/ #define IS_GPIO_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ ((PERIPH) == GPIOB) || \ ((PERIPH) == GPIOC) || \ ((PERIPH) == GPIOD) || \ ((PERIPH) == GPIOE) || \ ((PERIPH) == GPIOF) || \ ((PERIPH) == GPIOG) || \ ((PERIPH) == GPIOH) || \ ((PERIPH) == GPIOJ) || \ ((PERIPH) == GPIOK) || \ ((PERIPH) == GPIOL) || \ ((PERIPH) == GPIOM)) #define IS_CAN_PERIPH(PERIPH) (((PERIPH) == CAN)) #define IS_CANMSG_PERIPH(PERIPH) (((PERIPH) == CANMSG)) #define IS_ETH_PERIPH(PERIPH) (((PERIPH) == ETH)) #define IS_TMU_PERIPH(PERIPH) (((PERIPH) == TMU)) #define IS_MFLASH_PERIPH(PERIPH) (((PERIPH) == MFLASH)) #define IS_BFLASH_PERIPH(PERIPH) (((PERIPH) == BFLASH)) #define IS_EXTMEM_PERIPH(PERIPH) (((PERIPH) == EXTMEM)) #define IS_SPWR_PERIPH(PERIPH) (((PERIPH) == SPWR0) || \ ((PERIPH) == SPWR1)) #define IS_MILSTD_PERIPH(PERIPH) (((PERIPH) == MILSTD0) || \ ((PERIPH) == MILSTD1)) #define IS_SPWRTMR_PERIPH(PERIPH) (((PERIPH) == SPWRTMR)) #define IS_SDFM_PERIPH(PERIPH) (((PERIPH) == SDFM)) #define IS_SIU_PERIPH(PERIPH) (((PERIPH) == SIU)) #define IS_RCU_PERIPH(PERIPH) (((PERIPH) == RCU)) #define IS_PMU_PERIPH(PERIPH) (((PERIPH) == PMU)) #define IS_WDT_PERIPH(PERIPH) (((PERIPH) == WDT)) #define IS_DMA_PERIPH(PERIPH) (((PERIPH) == DMA)) #define IS_UART_PERIPH(PERIPH) (((PERIPH) == UART0) || \ ((PERIPH) == UART1) || \ ((PERIPH) == UART2) || \ ((PERIPH) == UART3)) #define IS_TUART_PERIPH(PERIPH) (((PERIPH) == TUART0) || \ ((PERIPH) == TUART1)) #define IS_I2C_PERIPH(PERIPH) (((PERIPH) == I2C0) || \ ((PERIPH) == I2C1)) #define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI0) || \ ((PERIPH) == SPI1) || \ ((PERIPH) == SPI2) || \ ((PERIPH) == SPI3)) #define IS_TMR_PERIPH(PERIPH) (((PERIPH) == TMR0) || \ ((PERIPH) == TMR1) || \ ((PERIPH) == TMR2) || \ ((PERIPH) == TMR3)) #define IS_ETMR_PERIPH(PERIPH) (((PERIPH) == ETMR0) || \ ((PERIPH) == ETMR1) || \ ((PERIPH) == ETMR2) || \ ((PERIPH) == ETMR3)) #define IS_RTC_PERIPH(PERIPH) (((PERIPH) == RTC)) #define IS_ECAP_PERIPH(PERIPH) (((PERIPH) == ECAP0) || \ ((PERIPH) == ECAP1) || \ ((PERIPH) == ECAP2) || \ ((PERIPH) == ECAP3) || \ ((PERIPH) == ECAP4) || \ ((PERIPH) == ECAP5)) #define IS_PWM_PERIPH(PERIPH) (((PERIPH) == PWM0) || \ ((PERIPH) == PWM1) || \ ((PERIPH) == PWM2) || \ ((PERIPH) == PWM3) || \ ((PERIPH) == PWM4) || \ ((PERIPH) == PWM5) || \ ((PERIPH) == PWM6) || \ ((PERIPH) == PWM7) || \ ((PERIPH) == PWM8) || \ ((PERIPH) == PWM9)) #define IS_QEP_PERIPH(PERIPH) (((PERIPH) == QEP0) || \ ((PERIPH) == QEP1) || \ ((PERIPH) == QEP2) || \ ((PERIPH) == QEP3)) #define IS_LAU_PERIPH(PERIPH) (((PERIPH) == LAU)) #define IS_OWI_PERIPH(PERIPH) (((PERIPH) == OWI0) || \ ((PERIPH) == OWI1)) #define IS_ADC_PERIPH(PERIPH) (((PERIPH) == ADC)) #ifdef __cplusplus } #endif #endif /* __K1921VK028_H */ /************************** (C) COPYRIGHT 2019 NIIET *************************** * * END OF FILE K1921VK028.h */