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инициализация spi перенесена на cube (работает)

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убрана кастомная библиотека periph_general
This commit is contained in:
Razvalyaev
2025-06-27 15:28:58 +03:00
parent 981dbf9bfa
commit a9a2466359
1587 changed files with 403396 additions and 250770 deletions
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7
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c
View File

@@ -50,11 +50,11 @@
* @{
*/
/**
* @brief STM32F4xx HAL Driver version number V1.8.1
* @brief STM32F4xx HAL Driver version number V1.8.4
*/
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */
#define __STM32F4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
@@ -368,7 +368,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
/**
* @brief Return tick frequency.
* @retval tick period in Hz
* @retval Tick frequency.
* Value of @ref HAL_TickFreqTypeDef.
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{

854
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c
View File

@@ -2,7 +2,7 @@
******************************************************************************
* @file stm32f4xx_hal_adc.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Converter (ADC) peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
@@ -23,21 +23,21 @@
==============================================================================
##### ADC Peripheral features #####
==============================================================================
[..]
[..]
(#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
(#) Interrupt generation at the end of conversion, end of injected conversion,
(#) Interrupt generation at the end of conversion, end of injected conversion,
and in case of analog watchdog or overrun events
(#) Single and continuous conversion modes.
(#) Scan mode for automatic conversion of channel 0 to channel x.
(#) Data alignment with in-built data coherency.
(#) Channel-wise programmable sampling time.
(#) External trigger option with configurable polarity for both regular and
(#) External trigger option with configurable polarity for both regular and
injected conversion.
(#) Dual/Triple mode (on devices with 2 ADCs or more).
(#) Configurable DMA data storage in Dual/Triple ADC mode.
(#) Configurable DMA data storage in Dual/Triple ADC mode.
(#) Configurable delay between conversions in Dual/Triple interleaved mode.
(#) ADC conversion type (refer to the datasheets).
(#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
(#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
slower speed.
(#) ADC input range: VREF(minus) = VIN = VREF(plus).
(#) DMA request generation during regular channel conversion.
@@ -50,8 +50,8 @@
(##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
(##) ADC pins configuration
(+++) Enable the clock for the ADC GPIOs using the following function:
__HAL_RCC_GPIOx_CLK_ENABLE()
(+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
__HAL_RCC_GPIOx_CLK_ENABLE()
(+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
(##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
(+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
@@ -65,7 +65,7 @@
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA Streams. The output stream should have higher
priority than the input stream.
*** Configuration of ADC, groups regular/injected, channels parameters ***
==============================================================================
[..]
@@ -73,64 +73,64 @@
and regular group parameters (conversion trigger, sequencer, ...)
using function HAL_ADC_Init().
(#) Configure the channels for regular group parameters (channel number,
(#) Configure the channels for regular group parameters (channel number,
channel rank into sequencer, ..., into regular group)
using function HAL_ADC_ConfigChannel().
(#) Optionally, configure the injected group parameters (conversion trigger,
(#) Optionally, configure the injected group parameters (conversion trigger,
sequencer, ..., of injected group)
and the channels for injected group parameters (channel number,
and the channels for injected group parameters (channel number,
channel rank into sequencer, ..., into injected group)
using function HAL_ADCEx_InjectedConfigChannel().
(#) Optionally, configure the analog watchdog parameters (channels
monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
(#) Optionally, for devices with several ADC instances: configure the
(#) Optionally, for devices with several ADC instances: configure the
multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
*** Execution of ADC conversions ***
==============================================================================
[..]
[..]
(#) ADC driver can be used among three modes: polling, interruption,
transfer by DMA.
transfer by DMA.
*** Polling mode IO operation ***
=================================
[..]
(+) Start the ADC peripheral using HAL_ADC_Start()
[..]
(+) Start the ADC peripheral using HAL_ADC_Start()
(+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
user can specify the value of timeout according to his end application
user can specify the value of timeout according to his end application
(+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
(+) Stop the ADC peripheral using HAL_ADC_Stop()
*** Interrupt mode IO operation ***
===================================
[..]
(+) Start the ADC peripheral using HAL_ADC_Start_IT()
(+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
(+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
(+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADC_ErrorCallback
(+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
*** DMA mode IO operation ***
*** Interrupt mode IO operation ***
===================================
[..]
(+) Start the ADC peripheral using HAL_ADC_Start_IT()
(+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
(+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
(+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADC_ErrorCallback
(+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
*** DMA mode IO operation ***
==============================
[..]
(+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
of data to be transferred at each end of conversion
(+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
(+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
[..]
(+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
of data to be transferred at each end of conversion
(+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
(+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADC_ErrorCallback
(+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
*** ADC HAL driver macros list ***
=============================================
=============================================
[..]
Below the list of most used macros in ADC HAL driver.
(+) __HAL_ADC_ENABLE : Enable the ADC peripheral
(+) __HAL_ADC_DISABLE : Disable the ADC peripheral
(+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
@@ -138,10 +138,10 @@
(+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
(+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
(+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
(+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
[..]
(@) You can refer to the ADC HAL driver header file for more useful macros
(+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
[..]
(@) You can refer to the ADC HAL driver header file for more useful macros
*** Deinitialization of ADC ***
==============================================================================
@@ -167,7 +167,7 @@
(#) Optionally, in case of usage of DMA:
(++) Deinitialize the DMA using function HAL_DMA_DeInit().
(++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
(++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
*** Callback registration ***
==============================================================================
[..]
@@ -242,7 +242,7 @@
are set to the corresponding weak functions.
@endverbatim
*/
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
@@ -254,10 +254,10 @@
/** @defgroup ADC ADC
* @brief ADC driver modules
* @{
*/
*/
#ifdef HAL_ADC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -266,7 +266,7 @@
* @{
*/
/* Private function prototypes -----------------------------------------------*/
static void ADC_Init(ADC_HandleTypeDef* hadc);
static void ADC_Init(ADC_HandleTypeDef *hadc);
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
static void ADC_DMAError(DMA_HandleTypeDef *hdma);
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
@@ -278,46 +278,46 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
* @{
*/
/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the ADC.
(+) De-initialize the ADC.
(+) Initialize and configure the ADC.
(+) De-initialize the ADC.
@endverbatim
* @{
*/
/**
* @brief Initializes the ADCx peripheral according to the specified parameters
* @brief Initializes the ADCx peripheral according to the specified parameters
* in the ADC_InitStruct and initializes the ADC MSP.
*
* @note This function is used to configure the global features of the ADC (
*
* @note This function is used to configure the global features of the ADC (
* ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
* the rest of the configuration parameters are specific to the regular
* channels group (scan mode activation, continuous mode activation,
* External trigger source and edge, DMA continuous request after the
* External trigger source and edge, DMA continuous request after the
* last transfer and End of conversion selection).
*
*
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check ADC handle */
if(hadc == NULL)
if (hadc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
@@ -330,13 +330,13 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
}
if(hadc->State == HAL_ADC_STATE_RESET)
if (hadc->State == HAL_ADC_STATE_RESET)
{
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/* Init the ADC Callback settings */
@@ -359,12 +359,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
}
/* Configuration of ADC parameters if previous preliminary actions are */
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
{
@@ -372,13 +372,13 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Set ADC parameters */
ADC_Init(hadc);
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_BUSY_INTERNAL,
@@ -388,7 +388,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
tmp_hal_status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hadc);
@@ -397,58 +397,58 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
}
/**
* @brief Deinitializes the ADCx peripheral registers to their default reset values.
* @brief Deinitializes the ADCx peripheral registers to their default reset values.
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check ADC handle */
if(hadc == NULL)
if (hadc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
/* Configuration of ADC parameters if previous preliminary actions are */
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
if (hadc->MspDeInitCallback == NULL)
{
hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
}
if (hadc->MspDeInitCallback == NULL)
{
hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware: RCC clock, NVIC */
hadc->MspDeInitCallback(hadc);
/* DeInit the low level hardware: RCC clock, NVIC */
hadc->MspDeInitCallback(hadc);
#else
/* DeInit the low level hardware: RCC clock, NVIC */
HAL_ADC_MspDeInit(hadc);
/* DeInit the low level hardware: RCC clock, NVIC */
HAL_ADC_MspDeInit(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
/* Set ADC state */
hadc->State = HAL_ADC_STATE_RESET;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return tmp_hal_status;
}
@@ -656,31 +656,31 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca
/**
* @brief Initializes the ADC MSP.
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* the configuration information for the specified ADC.
* @retval None
*/
__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_MspInit could be implemented in the user file
*/
*/
}
/**
* @brief DeInitializes the ADC MSP.
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* the configuration information for the specified ADC.
* @retval None
*/
__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_MspDeInit could be implemented in the user file
*/
*/
}
/**
@@ -688,12 +688,12 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
*/
/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @brief IO operation functions
*
@verbatim
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
===============================================================================
[..] This section provides functions allowing to:
(+) Start conversion of regular channel.
(+) Stop conversion of regular channel.
@@ -701,8 +701,8 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
(+) Stop conversion of regular channel and disable interrupt.
(+) Start conversion of regular channel and enable DMA transfer.
(+) Stop conversion of regular channel and disable DMA transfer.
(+) Handle ADC interrupt request.
(+) Handle ADC interrupt request.
@endverbatim
* @{
*/
@@ -713,37 +713,37 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
/* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
while(counter != 0U)
while (counter != 0U)
{
counter--;
}
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
@@ -751,25 +751,25 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
HAL_ADC_STATE_REG_BUSY);
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
}
else
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
@@ -784,17 +784,17 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
#if defined(ADC2) && defined(ADC3)
if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
|| ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
|| ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
{
#endif /* ADC2 || ADC3 */
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
@@ -806,10 +806,10 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
else
{
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
}
@@ -821,45 +821,45 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
/* Return function status */
return HAL_OK;
}
/**
* @brief Disables ADC and stop conversion of regular channels.
*
* @note Caution: This function will stop also injected channels.
*
* @note Caution: This function will stop also injected channels.
*
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
*
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
/* Check if ADC is effectively disabled */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
@@ -868,21 +868,21 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
* @brief Poll for regular conversion complete
* @note ADC conversion flags EOS (end of sequence) and EOC (end of
* conversion) are cleared by this function.
* @note This function cannot be used in a particular setup: ADC configured
* @note This function cannot be used in a particular setup: ADC configured
* in DMA mode and polling for end of each conversion (ADC init
* parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
* In this case, DMA resets the flag EOC and polling cannot be
* performed on each conversion. Nevertheless, polling can still
* performed on each conversion. Nevertheless, polling can still
* be performed on the complete sequence.
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param Timeout Timeout value in millisecond.
* @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
{
uint32_t tickstart = 0U;
/* Verification that ADC configuration is compliant with polling for */
/* each conversion: */
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
@@ -890,69 +890,69 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and polling for end of each conversion. */
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA))
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_ERROR;
}
/* Get tick */
/* Get tick */
tickstart = HAL_GetTick();
/* Check End of conversion flag */
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
while (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
{
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
if (Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* New check to avoid false timeout detection in case of preemption */
if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
if (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
/* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_TIMEOUT;
}
}
}
}
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F4, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE) &&
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE) &&
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)))
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
/* Return ADC state */
return HAL_OK;
}
@@ -965,13 +965,13 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
* This parameter can be one of the following values:
* @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
* @arg ADC_OVR_EVENT: ADC Overrun event.
* @param Timeout Timeout value in millisecond.
* @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
{
uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_EVENT_TYPE(EventType));
@@ -980,34 +980,34 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
tickstart = HAL_GetTick();
/* Check selected event flag */
while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
while (!(__HAL_ADC_GET_FLAG(hadc, EventType)))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
if (Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* New check to avoid false timeout detection in case of preemption */
if(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
if (!(__HAL_ADC_GET_FLAG(hadc, EventType)))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
/* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_TIMEOUT;
}
}
}
}
/* Analog watchdog (level out of window) event */
if(EventType == ADC_AWD_EVENT)
if (EventType == ADC_AWD_EVENT)
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
}
@@ -1018,11 +1018,11 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
/* Set ADC error code to overrun */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
/* Clear ADC overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
}
/* Return ADC state */
return HAL_OK;
}
@@ -1034,37 +1034,37 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
* the configuration information for the specified ADC.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
/* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
while(counter != 0U)
while (counter != 0U)
{
counter--;
}
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
@@ -1072,19 +1072,19 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
HAL_ADC_STATE_REG_BUSY);
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
}
else
{
@@ -1105,20 +1105,20 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
/* Enable end of conversion interrupt for regular group */
__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
#if defined(ADC2) && defined(ADC3)
if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
|| ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
|| ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
{
#endif /* ADC2 || ADC3 */
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
@@ -1130,10 +1130,10 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
else
{
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
}
@@ -1145,36 +1145,36 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
/* Return function status */
return HAL_OK;
}
/**
* @brief Disables the interrupt and stop ADC conversion of regular channels.
*
* @note Caution: This function will stop also injected channels.
*
* @note Caution: This function will stop also injected channels.
*
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
/* Check if ADC is effectively disabled */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Disable ADC end of conversion interrupt for regular group */
/* Disable ADC end of conversion interrupt for regular group */
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
/* Set ADC state */
@@ -1182,24 +1182,24 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Handles ADC interrupt request
* @brief Handles ADC interrupt request
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
{
uint32_t tmp1 = 0U, tmp2 = 0U;
uint32_t tmp_sr = hadc->Instance->SR;
uint32_t tmp_cr1 = hadc->Instance->CR1;
@@ -1207,60 +1207,60 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
tmp1 = tmp_sr & ADC_FLAG_EOC;
tmp2 = tmp_cr1 & ADC_IT_EOC;
/* Check End of conversion flag for regular channels */
if(tmp1 && tmp2)
if (tmp1 && tmp2)
{
/* Update state machine on conversion status if not in error state */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
}
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F4, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE) &&
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE) &&
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)))
{
/* Disable ADC end of single conversion interrupt on group regular */
/* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_ADC_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
/* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
}
tmp1 = tmp_sr & ADC_FLAG_JEOC;
tmp2 = tmp_cr1 & ADC_IT_JEOC;
/* Check End of conversion flag for injected channels */
if(tmp1 && tmp2)
if (tmp1 && tmp2)
{
/* Update state machine on conversion status if not in error state */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
@@ -1273,132 +1273,132 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* by external trigger, scan sequence on going or by automatic injected */
/* conversion from group regular (same conditions as group regular */
/* interruption disabling above). */
if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
(HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
(HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE) ) ) )
if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
(HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
(HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE))))
{
/* Disable ADC end of single conversion interrupt on group injected */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
{
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
/* Conversion complete callback */
/* Conversion complete callback */
/* Conversion complete callback */
/* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->InjectedConvCpltCallback(hadc);
hadc->InjectedConvCpltCallback(hadc);
#else
HAL_ADCEx_InjectedConvCpltCallback(hadc);
HAL_ADCEx_InjectedConvCpltCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear injected group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
}
tmp1 = tmp_sr & ADC_FLAG_AWD;
tmp2 = tmp_cr1 & ADC_IT_AWD;
/* Check Analog watchdog flag */
if(tmp1 && tmp2)
if (tmp1 && tmp2)
{
if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
/* Level out of window callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindowCallback(hadc);
#else
HAL_ADC_LevelOutOfWindowCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear the ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
}
}
tmp1 = tmp_sr & ADC_FLAG_OVR;
tmp2 = tmp_cr1 & ADC_IT_OVR;
/* Check Overrun flag */
if(tmp1 && tmp2)
if (tmp1 && tmp2)
{
/* Note: On STM32F4, ADC overrun can be set through other parameters */
/* refer to description of parameter "EOCSelection" for more */
/* details. */
/* Set ADC error code to overrun */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
/* Clear ADC overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
/* Error callback */
/* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc);
HAL_ADC_ErrorCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear the Overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
}
}
/**
* @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
* @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param pData The destination Buffer address.
* @param Length The length of data to be transferred from ADC peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
/* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
while(counter != 0U)
while (counter != 0U)
{
counter--;
}
}
/* Check ADC DMA Mode */
/* - disable the DMA Mode if it is already enabled */
if((hadc->Instance->CR2 & ADC_CR2_DMA) == ADC_CR2_DMA)
if ((hadc->Instance->CR2 & ADC_CR2_DMA) == ADC_CR2_DMA)
{
CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
@@ -1406,19 +1406,19 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
HAL_ADC_STATE_REG_BUSY);
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
}
else
{
@@ -1429,7 +1429,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
__HAL_UNLOCK(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
@@ -1441,37 +1441,37 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
/* start (in case of SW start): */
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Enable ADC DMA mode */
hadc->Instance->CR2 |= ADC_CR2_DMA;
/* Start the DMA channel */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
#if defined(ADC2) && defined(ADC3)
if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
|| ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
|| ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
{
#endif /* ADC2 || ADC3 */
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
@@ -1483,10 +1483,10 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
else
{
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
}
@@ -1498,43 +1498,43 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
/* Return function status */
return HAL_OK;
return tmp_hal_status;
}
/**
* @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
* @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
/* Check if ADC is effectively disabled */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Disable the selected ADC DMA mode */
hadc->Instance->CR2 &= ~ADC_CR2_DMA;
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
/* DMA transfer is on going) */
if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
{
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
/* Check if DMA channel effectively disabled */
if (tmp_hal_status != HAL_OK)
{
@@ -1542,19 +1542,19 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
}
}
/* Disable ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return tmp_hal_status;
}
@@ -1565,19 +1565,19 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
* the configuration information for the specified ADC.
* @retval Converted value
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
{
/* Return the selected ADC converted value */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
{
/* Return the selected ADC converted value */
return hadc->Instance->DR;
}
/**
* @brief Regular conversion complete callback in non blocking mode
* @brief Regular conversion complete callback in non blocking mode
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
@@ -1587,12 +1587,12 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
}
/**
* @brief Regular conversion half DMA transfer callback in non blocking mode
* @brief Regular conversion half DMA transfer callback in non blocking mode
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
@@ -1602,12 +1602,12 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
}
/**
* @brief Analog watchdog callback in non blocking mode
* @brief Analog watchdog callback in non blocking mode
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
@@ -1618,7 +1618,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
/**
* @brief Error ADC callback.
* @note In case of error due to overrun when using ADC with DMA transfer
* @note In case of error due to overrun when using ADC with DMA transfer
* (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
* - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
* - If needed, restart a new ADC conversion using function
@@ -1640,51 +1640,51 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
/**
* @}
*/
/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
===============================================================================
[..] This section provides functions allowing to:
(+) Configure regular channels.
(+) Configure regular channels.
(+) Configure injected channels.
(+) Configure multimode.
(+) Configure the analog watch dog.
@endverbatim
* @{
*/
/**
* @brief Configures for the selected ADC regular channel its corresponding
* rank in the sequencer and its sample time.
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param sConfig ADC configuration structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
/**
* @brief Configures for the selected ADC regular channel its corresponding
* rank in the sequencer and its sample time.
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param sConfig ADC configuration structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if (sConfig->Channel > ADC_CHANNEL_9)
{
/* Clear the old sample time */
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
}
@@ -1692,17 +1692,17 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
{
/* Clear the old sample time */
hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
/* Set the new sample time */
hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
}
/* For Rank 1 to 6 */
if (sConfig->Rank < 7U)
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
}
@@ -1711,7 +1711,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
}
@@ -1720,20 +1720,20 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
}
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
{
/* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
/* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
{
tmpADC_Common->CCR &= ~ADC_CCR_TSVREFE;
@@ -1741,8 +1741,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
/* Enable the VBAT channel*/
tmpADC_Common->CCR |= ADC_CCR_VBATE;
}
/* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or
/* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or
Channel_17 is selected for VREFINT enable TSVREFE */
if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
{
@@ -1753,22 +1753,22 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
}
/* Enable the Temperature sensor and VREFINT channel*/
tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
while(counter != 0U)
while (counter != 0U)
{
counter--;
}
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
@@ -1785,31 +1785,31 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
* effective timing of the new programmed threshold values.
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure
* @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure
* that contains the configuration information of ADC analog watchdog.
* @retval HAL status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
{
#ifdef USE_FULL_ASSERT
#ifdef USE_FULL_ASSERT
uint32_t tmp = 0U;
#endif /* USE_FULL_ASSERT */
#endif /* USE_FULL_ASSERT */
/* Check the parameters */
assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
#ifdef USE_FULL_ASSERT
#ifdef USE_FULL_ASSERT
tmp = ADC_GET_RESOLUTION(hadc);
assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
#endif /* USE_FULL_ASSERT */
/* Process locked */
__HAL_LOCK(hadc);
if(AnalogWDGConfig->ITMode == ENABLE)
if (AnalogWDGConfig->ITMode == ENABLE)
{
/* Enable the ADC Analog watchdog interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
@@ -1819,28 +1819,28 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
/* Disable the ADC Analog watchdog interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
}
/* Clear AWDEN, JAWDEN and AWDSGL bits */
hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
/* Set the analog watchdog enable mode */
hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
/* Set the high threshold */
hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
/* Set the low threshold */
hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
/* Clear the Analog watchdog channel select bits */
hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
/* Set the Analog watchdog channel */
hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
@@ -1850,28 +1850,28 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
*/
/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
* @brief ADC Peripheral State functions
* @brief ADC Peripheral State functions
*
@verbatim
@verbatim
===============================================================================
##### Peripheral State and errors functions #####
===============================================================================
===============================================================================
[..]
This subsection provides functions allowing to
(+) Check the ADC state
(+) Check the ADC Error
@endverbatim
* @{
*/
/**
* @brief return the ADC state
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL state
*/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
{
/* Return ADC state */
return hadc->State;
@@ -1897,49 +1897,49 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
*/
/**
* @brief Initializes the ADCx peripheral according to the specified parameters
* in the ADC_InitStruct without initializing the ADC MSP.
* @brief Initializes the ADCx peripheral according to the specified parameters
* in the ADC_InitStruct without initializing the ADC MSP.
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* the configuration information for the specified ADC.
* @retval None
*/
static void ADC_Init(ADC_HandleTypeDef* hadc)
static void ADC_Init(ADC_HandleTypeDef *hadc)
{
ADC_Common_TypeDef *tmpADC_Common;
/* Set ADC parameters */
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Set the ADC clock prescaler */
tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE);
tmpADC_Common->CCR |= hadc->Init.ClockPrescaler;
/* Set ADC scan mode */
hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
/* Set ADC resolution */
hadc->Instance->CR1 &= ~(ADC_CR1_RES);
hadc->Instance->CR1 |= hadc->Init.Resolution;
/* Set ADC data alignment */
hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
hadc->Instance->CR2 |= hadc->Init.DataAlign;
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
/* Select external trigger polarity */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
@@ -1950,18 +1950,18 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
}
/* Enable or disable ADC continuous conversion mode */
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
if(hadc->Init.DiscontinuousConvMode != DISABLE)
if (hadc->Init.DiscontinuousConvMode != DISABLE)
{
assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
/* Enable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
/* Set the number of channels to be converted in discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
@@ -1971,63 +1971,63 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
/* Disable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
}
/* Set ADC number of conversion */
hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
/* Enable or disable ADC DMA continuous request */
hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
/* Enable or disable ADC end of conversion selection */
hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
}
/**
* @brief DMA transfer complete callback.
* @brief DMA transfer complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Update state machine on conversion status if not in error state */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
{
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F4, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE) &&
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE) &&
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)))
{
/* Disable ADC end of single conversion interrupt on group regular */
/* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_ADC_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
/* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
@@ -2046,8 +2046,8 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
HAL_ADC_ErrorCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
else
{
else
{
/* Call DMA error callback */
hadc->DMA_Handle->XferErrorCallback(hdma);
}
@@ -2055,15 +2055,15 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
}
/**
* @brief DMA half transfer complete callback.
* @brief DMA half transfer complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Half conversion callback */
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Half conversion callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvHalfCpltCallback(hadc);
#else
@@ -2072,18 +2072,18 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
}
/**
* @brief DMA error callback
* @brief DMA error callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_DMAError(DMA_HandleTypeDef *hdma)
static void ADC_DMAError(DMA_HandleTypeDef *hdma)
{
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hadc->State= HAL_ADC_STATE_ERROR_DMA;
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hadc->State = HAL_ADC_STATE_ERROR_DMA;
/* Set ADC error code to DMA error */
hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
/* Error callback */
/* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
@@ -2102,9 +2102,9 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma)
#endif /* HAL_ADC_MODULE_ENABLED */
/**
* @}
*/
*/
/**
* @}
*/
*/

443
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c
View File

@@ -64,8 +64,8 @@
(+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
(+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
(+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
(+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
(+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
(+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
@@ -92,12 +92,12 @@
/** @defgroup ADCEx ADCEx
* @brief ADC Extended driver modules
* @{
*/
*/
#ifdef HAL_ADC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @addtogroup ADCEx_Private_Functions
@@ -106,7 +106,7 @@
/* Private function prototypes -----------------------------------------------*/
static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
/**
* @}
*/
@@ -116,13 +116,13 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
* @{
*/
/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
*
@verbatim
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
===============================================================================
[..] This section provides functions allowing to:
(+) Start conversion of injected channel.
(+) Stop conversion of injected channel.
@@ -132,7 +132,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
(+) Get result of multimode conversion.
(+) Configure injected channels.
(+) Configure multimode.
@endverbatim
* @{
*/
@@ -143,35 +143,35 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
{
__IO uint32_t counter = 0U;
uint32_t tmp1 = 0U, tmp2 = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Process locked */
__HAL_LOCK(hadc);
/* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
while(counter != 0U)
while (counter != 0U)
{
counter--;
}
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Set ADC state */
/* - Clear state bitfield related to injected group conversion results */
@@ -179,7 +179,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
HAL_ADC_STATE_INJ_BUSY);
/* Check if a regular conversion is ongoing */
/* Note: On this device, there is no ADC error code fields related to */
/* conversions on group injected only. In case of conversion on */
@@ -189,12 +189,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Clear injected group conversion flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
@@ -205,11 +205,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if(tmp1 && tmp2)
if (tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
@@ -219,7 +219,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if((hadc->Instance == ADC1) && tmp1 && tmp2)
if ((hadc->Instance == ADC1) && tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
@@ -234,7 +234,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
/* Return function status */
return HAL_OK;
}
@@ -246,35 +246,35 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
*
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
{
__IO uint32_t counter = 0U;
uint32_t tmp1 = 0U, tmp2 = 0U;
ADC_Common_TypeDef *tmpADC_Common;
/* Process locked */
__HAL_LOCK(hadc);
/* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
while(counter != 0U)
while (counter != 0U)
{
counter--;
}
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Set ADC state */
/* - Clear state bitfield related to injected group conversion results */
@@ -282,7 +282,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
HAL_ADC_STATE_INJ_BUSY);
/* Check if a regular conversion is ongoing */
/* Note: On this device, there is no ADC error code fields related to */
/* conversions on group injected only. In case of conversion on */
@@ -292,16 +292,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Clear injected group conversion flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
/* Enable end of conversion interrupt for injected channels */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
@@ -309,13 +309,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if(tmp1 && tmp2)
if (tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
@@ -325,7 +325,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if((hadc->Instance == ADC1) && tmp1 && tmp2)
if ((hadc->Instance == ADC1) && tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
@@ -340,7 +340,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
/* Return function status */
return HAL_OK;
}
@@ -348,7 +348,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
/**
* @brief Stop conversion of injected channels. Disable ADC peripheral if
* no regular conversion is on going.
* @note If ADC must be disabled and if conversion is on going on
* @note If ADC must be disabled and if conversion is on going on
* regular group, function HAL_ADC_Stop must be used to stop both
* injected and regular groups, and disable the ADC.
* @note If injected group mode auto-injection is enabled,
@@ -357,31 +357,31 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
* @param hadc ADC handle
* @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
/* Stop potential conversion and disable ADC peripheral */
/* Conditioned to: */
/* - No conversion on the other group (regular group) is intended to */
/* continue (injected and regular groups stop conversion and ADC disable */
/* are common) */
/* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
{
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
/* Check if ADC is effectively disabled */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
@@ -393,13 +393,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
tmp_hal_status = HAL_ERROR;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return tmp_hal_status;
}
@@ -408,28 +408,28 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
* @brief Poll for injected conversion complete
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param Timeout Timeout value in millisecond.
* @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
{
uint32_t tickstart = 0U;
/* Get tick */
/* Get tick */
tickstart = HAL_GetTick();
/* Check End of conversion flag */
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
while (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
if (Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* New check to avoid false timeout detection in case of preemption */
if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
if (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
{
hadc->State= HAL_ADC_STATE_TIMEOUT;
hadc->State = HAL_ADC_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_TIMEOUT;
@@ -437,44 +437,44 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
}
}
}
/* Clear injected group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
/* Determine whether any further conversion upcoming on group injected */
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F4, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
(HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
(HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE) ) ) )
if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
(HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
(HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE))))
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
{
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
/* Return ADC state */
return HAL_OK;
}
}
/**
* @brief Stop conversion of injected channels, disable interruption of
* @brief Stop conversion of injected channels, disable interruption of
* end-of-conversion. Disable ADC peripheral if no regular conversion
* is on going.
* @note If ADC must be disabled and if conversion is on going on
* @note If ADC must be disabled and if conversion is on going on
* regular group, function HAL_ADC_Stop must be used to stop both
* injected and regular groups, and disable the ADC.
* @note If injected group mode auto-injection is enabled,
@@ -482,35 +482,35 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
* @param hadc ADC handle
* @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
/* Stop potential conversion and disable ADC peripheral */
/* Conditioned to: */
/* - No conversion on the other group (regular group) is intended to */
/* continue (injected and regular groups stop conversion and ADC disable */
/* are common) */
/* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
/* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
{
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
/* Check if ADC is effectively disabled */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Disable ADC end of conversion interrupt for injected channels */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
@@ -521,13 +521,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
tmp_hal_status = HAL_ERROR;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return tmp_hal_status;
}
@@ -544,32 +544,32 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
* @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
* @retval None
*/
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
{
__IO uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
/* Clear injected group conversion flag to have similar behaviour as */
/* regular group: reading data register also clears end of conversion flag. */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
/* Return the selected ADC converted value */
switch(InjectedRank)
{
/* Return the selected ADC converted value */
switch (InjectedRank)
{
case ADC_INJECTED_RANK_4:
{
tmp = hadc->Instance->JDR4;
}
}
break;
case ADC_INJECTED_RANK_3:
{
case ADC_INJECTED_RANK_3:
{
tmp = hadc->Instance->JDR3;
}
}
break;
case ADC_INJECTED_RANK_2:
{
case ADC_INJECTED_RANK_2:
{
tmp = hadc->Instance->JDR2;
}
break;
@@ -579,53 +579,53 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
}
break;
default:
break;
break;
}
return tmp;
}
/**
* @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
*
* @note Caution: This function must be used only with the ADC master.
*
* @note Caution: This function must be used only with the ADC master.
*
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
* @param Length The length of data to be transferred from ADC peripheral to memory.
* @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
* @param Length The length of data to be transferred from ADC peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
{
__IO uint32_t counter = 0U;
ADC_Common_TypeDef *tmpADC_Common;
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
/* Process locked */
__HAL_LOCK(hadc);
/* Check if ADC peripheral is disabled in order to enable it and wait during
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
while(counter != 0U)
while (counter != 0U)
{
counter--;
}
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
@@ -633,43 +633,43 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
HAL_ADC_STATE_REG_BUSY);
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
}
else
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
/* start (in case of SW start): */
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
@@ -692,12 +692,12 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
/* Disable the selected ADC EOC rising on each regular channel conversion */
tmpADC_Common->CCR &= ~ADC_CCR_DDS;
}
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
@@ -711,28 +711,28 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
/* Return function status */
return HAL_OK;
return tmp_hal_status;
}
/**
* @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral
* @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
@@ -743,42 +743,45 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Check if ADC is effectively disabled */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Disable the selected ADC DMA mode for multimode */
tmpADC_Common->CCR &= ~ADC_CCR_DDS;
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
/* DMA transfer is on going) */
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
/* Disable ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return tmp_hal_status;
}
/**
* @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results
* @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results
* data in the selected multi mode.
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval The converted data value.
*/
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
{
ADC_Common_TypeDef *tmpADC_Common;
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
@@ -789,12 +792,12 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
}
/**
* @brief Injected conversion complete callback in non blocking mode
* @brief Injected conversion complete callback in non blocking mode
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
@@ -808,15 +811,15 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
* rank in the sequencer and its sample time.
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param sConfigInjected ADC configuration structure for injected channel.
* @param sConfigInjected ADC configuration structure for injected channel.
* @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
{
#ifdef USE_FULL_ASSERT
#ifdef USE_FULL_ASSERT
uint32_t tmp = 0U;
#endif /* USE_FULL_ASSERT */
ADC_Common_TypeDef *tmpADC_Common;
@@ -835,20 +838,20 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
#endif /* USE_FULL_ASSERT */
if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
}
/* Process locked */
__HAL_LOCK(hadc);
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
{
/* Clear the old sample time */
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
}
@@ -856,34 +859,34 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
{
/* Clear the old sample time */
hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
/* Set the new sample time */
hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
}
/*---------------------------- ADCx JSQR Configuration -----------------*/
hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
/* Rank configuration */
/* Clear the old SQx bits for the selected rank */
hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion);
/* Set the SQx bits for the selected rank */
hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion);
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
/* software start. */
if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
/* Select external trigger polarity */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
@@ -892,9 +895,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
{
/* Reset the external trigger */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
}
if (sConfigInjected->AutoInjectedConv != DISABLE)
{
/* Enable the selected ADC automatic injected group conversion */
@@ -905,7 +908,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Disable the selected ADC automatic injected group conversion */
hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);
}
if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)
{
/* Enable the selected ADC injected discontinuous mode */
@@ -916,8 +919,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Disable the selected ADC injected discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);
}
switch(sConfigInjected->InjectedRank)
switch (sConfigInjected->InjectedRank)
{
case 1U:
/* Set injected channel 1 offset */
@@ -944,7 +947,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* if ADC1 Channel_18 is selected enable VBAT Channel */
if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
@@ -952,30 +955,30 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Enable the VBAT channel*/
tmpADC_Common->CCR |= ADC_CCR_VBATE;
}
/* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
{
/* Enable the TSVREFE channel*/
tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Configures the ADC multi-mode
* @brief Configures the ADC multi-mode
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param multimode pointer to an ADC_MultiModeTypeDef structure that contains
* the configuration information for the specified ADC.
* @param multimode pointer to an ADC_MultiModeTypeDef structure that contains
* the configuration information for multimode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
{
ADC_Common_TypeDef *tmpADC_Common;
@@ -984,7 +987,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
assert_param(IS_ADC_MODE(multimode->Mode));
assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
/* Process locked */
__HAL_LOCK(hadc);
@@ -996,18 +999,18 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
/* Set ADC mode */
tmpADC_Common->CCR &= ~(ADC_CCR_MULTI);
tmpADC_Common->CCR |= multimode->Mode;
/* Set the ADC DMA access mode */
tmpADC_Common->CCR &= ~(ADC_CCR_DMA);
tmpADC_Common->CCR |= multimode->DMAAccessMode;
/* Set delay between two sampling phases */
tmpADC_Common->CCR &= ~(ADC_CCR_DELAY);
tmpADC_Common->CCR |= multimode->TwoSamplingDelay;
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
@@ -1017,48 +1020,48 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
*/
/**
* @brief DMA transfer complete callback.
* @brief DMA transfer complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
{
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Update state machine on conversion status if not in error state */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
{
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F4, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE) &&
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE) &&
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)))
{
/* Disable ADC end of single conversion interrupt on group regular */
/* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_ADC_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
/* Conversion complete callback */
HAL_ADC_ConvCpltCallback(hadc);
}
@@ -1070,31 +1073,31 @@ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
}
/**
* @brief DMA half transfer complete callback.
* @brief DMA half transfer complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Conversion complete callback */
HAL_ADC_ConvHalfCpltCallback(hadc);
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Conversion complete callback */
HAL_ADC_ConvHalfCpltCallback(hadc);
}
/**
* @brief DMA error callback
* @brief DMA error callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)
static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)
{
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hadc->State= HAL_ADC_STATE_ERROR_DMA;
/* Set ADC error code to DMA error */
hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
HAL_ADC_ErrorCallback(hadc);
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hadc->State = HAL_ADC_STATE_ERROR_DMA;
/* Set ADC error code to DMA error */
hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
HAL_ADC_ErrorCallback(hadc);
}
/**
@@ -1104,9 +1107,9 @@ static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)
#endif /* HAL_ADC_MODULE_ENABLED */
/**
* @}
*/
*/
/**
* @}
*/
*/

96
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c
View File

@@ -33,7 +33,7 @@
(++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
(++) Configure CAN pins
(+++) Enable the clock for the CAN GPIOs
(+++) Configure CAN pins as alternate function open-drain
(+++) Configure CAN pins as alternate function
(++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
(+++) Configure the CAN interrupt priority using
HAL_NVIC_SetPriority()
@@ -226,8 +226,8 @@
#ifdef HAL_CAN_MODULE_ENABLED
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
#error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once"
#endif
#error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once"
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -235,6 +235,7 @@
* @{
*/
#define CAN_TIMEOUT_VALUE 10U
#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U
/**
* @}
*/
@@ -248,8 +249,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -328,7 +329,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
@@ -482,7 +483,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Reset the CAN peripheral */
SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
@@ -555,7 +556,8 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan))
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID,
void (* pCallback)(CAN_HandleTypeDef *_hcan))
{
HAL_StatusTypeDef status = HAL_OK;
@@ -813,8 +815,8 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca
*/
/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
* @brief Configuration functions.
*
* @brief Configuration functions.
*
@verbatim
==============================================================================
##### Configuration functions #####
@@ -835,10 +837,10 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca
* contains the filter configuration information.
* @retval None
*/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig)
{
uint32_t filternbrbitpos;
CAN_TypeDef *can_ip = hcan->Instance;
CAN_TypeDef *can_ip;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
@@ -859,6 +861,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe
if (hcan->Instance == CAN3)
{
/* CAN3 is single instance with 14 dedicated filters banks */
can_ip = hcan->Instance;
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
@@ -883,10 +886,11 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe
assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
#else
/* CAN1 is single instance with 14 dedicated filters banks */
can_ip = hcan->Instance;
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
#endif
#endif /* CAN3 */
/* Initialisation mode for the filter */
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
@@ -905,7 +909,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe
CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
#endif
#endif /* CAN3 */
/* Convert filter number into bit position */
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
@@ -997,8 +1001,8 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe
*/
/** @defgroup CAN_Exported_Functions_Group3 Control functions
* @brief Control functions
*
* @brief Control functions
*
@verbatim
==============================================================================
##### Control functions #####
@@ -1170,7 +1174,6 @@ HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
{
__IO uint32_t count = 0;
uint32_t timeout = 1000000U;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
@@ -1186,15 +1189,14 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
count++;
/* Check if timeout is reached */
if (count > timeout)
if (count > CAN_WAKEUP_TIMEOUT_COUNTER)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
return HAL_ERROR;
}
}
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
} while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
/* Return function status */
return HAL_OK;
@@ -1216,7 +1218,7 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
* - 0 : Sleep mode is not active.
* - 1 : Sleep mode is active.
*/
uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan)
{
uint32_t status = 0U;
HAL_CAN_StateTypeDef state = hcan->State;
@@ -1247,7 +1249,8 @@ uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
* This parameter can be a value of @arg CAN_Tx_Mailboxes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
const uint8_t aData[], uint32_t *pTxMailbox)
{
uint32_t transmitmailbox;
HAL_CAN_StateTypeDef state = hcan->State;
@@ -1278,15 +1281,6 @@ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderType
/* Select an empty transmit mailbox */
transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
/* Check transmit mailbox value */
if (transmitmailbox > 2U)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
return HAL_ERROR;
}
/* Store the Tx mailbox */
*pTxMailbox = (uint32_t)1 << transmitmailbox;
@@ -1404,7 +1398,7 @@ HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMai
* the configuration information for the specified CAN.
* @retval Number of free Tx Mailboxes.
*/
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan)
{
uint32_t freelevel = 0U;
HAL_CAN_StateTypeDef state = hcan->State;
@@ -1447,7 +1441,7 @@ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
* - 1 : Pending transmission request on at least one of the selected
* Tx Mailbox.
*/
uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
{
uint32_t status = 0U;
HAL_CAN_StateTypeDef state = hcan->State;
@@ -1479,7 +1473,7 @@ uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxe
* This parameter can be one value of @arg CAN_Tx_Mailboxes.
* @retval Timestamp of message sent from Tx Mailbox.
*/
uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
{
uint32_t timestamp = 0U;
uint32_t transmitmailbox;
@@ -1513,7 +1507,8 @@ uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
* @param aData array where the payload of the Rx frame will be stored.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
HAL_CAN_StateTypeDef state = hcan->State;
@@ -1554,10 +1549,19 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
}
else
{
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U)
{
/* Truncate DLC to 8 if received field is over range */
pHeader->DLC = 8U;
}
else
{
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
}
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
@@ -1603,7 +1607,7 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
* This parameter can be a value of @arg CAN_receive_FIFO_number.
* @retval Number of messages available in Rx FIFO.
*/
uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo)
{
uint32_t filllevel = 0U;
HAL_CAN_StateTypeDef state = hcan->State;
@@ -1633,8 +1637,8 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
*/
/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
* @brief Interrupts management
*
* @brief Interrupts management
*
@verbatim
==============================================================================
##### Interrupts management #####
@@ -2099,8 +2103,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group5 Callback functions
* @brief CAN Callback functions
*
* @brief CAN Callback functions
*
@verbatim
==============================================================================
##### Callback functions #####
@@ -2349,8 +2353,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
* @brief CAN Peripheral State functions
*
* @brief CAN Peripheral State functions
*
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
@@ -2371,7 +2375,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
* the configuration information for the specified CAN.
* @retval HAL state
*/
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan)
{
HAL_CAN_StateTypeDef state = hcan->State;
@@ -2406,7 +2410,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
* the configuration information for the specified CAN.
* @retval CAN Error Code
*/
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan)
{
/* Return CAN error code */
return hcan->ErrorCode;

57
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c
View File

@@ -233,7 +233,8 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
/* Write to CEC Control Register */
hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \
hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen | \
hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | \
hcec->Init.BroadcastMsgNoErrorBitGen | \
hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \
hcec->Init.ListenMode;
@@ -412,10 +413,10 @@ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
* @param hcec CEC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
* @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
* @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
* @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
* @arg HAL_CEC_ERROR_CB_ID Error callback ID
* @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
* @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
@@ -501,10 +502,10 @@ HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_Call
* @param hcec uart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
* @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
* @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
* @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
* @arg HAL_CEC_ERROR_CB_ID Error callback ID
* @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
* @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
@@ -694,7 +695,7 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
uint8_t *pData, uint32_t Size)
const uint8_t *pData, uint32_t Size)
{
/* if the peripheral isn't already busy and if there is no previous transmission
already pending due to arbitration lost */
@@ -749,7 +750,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator
* @param hcec CEC handle
* @retval Frame size
*/
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec)
{
return hcec->RxXferSize;
}
@@ -775,13 +776,13 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
{
/* save interrupts register for further error or interrupts handling purposes */
uint32_t reg;
reg = hcec->Instance->ISR;
uint32_t itflag;
itflag = hcec->Instance->ISR;
/* ----------------------------Arbitration Lost Management----------------------------------*/
/* CEC TX arbitration error interrupt occurred --------------------------------------*/
if ((reg & CEC_FLAG_ARBLST) != 0U)
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST))
{
hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
@@ -789,7 +790,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
/* ----------------------------Rx Management----------------------------------*/
/* CEC RX byte received interrupt ---------------------------------------------------*/
if ((reg & CEC_FLAG_RXBR) != 0U)
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR))
{
/* reception is starting */
hcec->RxState = HAL_CEC_STATE_BUSY_RX;
@@ -801,7 +802,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
}
/* CEC RX end received interrupt ---------------------------------------------------*/
if ((reg & CEC_FLAG_RXEND) != 0U)
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND))
{
/* clear IT */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
@@ -820,7 +821,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
/* ----------------------------Tx Management----------------------------------*/
/* CEC TX byte request interrupt ------------------------------------------------*/
if ((reg & CEC_FLAG_TXBR) != 0U)
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR))
{
--hcec->TxXferCount;
if (hcec->TxXferCount == 0U)
@@ -829,14 +830,14 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* In all cases transmit the byte */
hcec->Instance->TXDR = *hcec->pTxBuffPtr;
hcec->Instance->TXDR = (uint8_t) * hcec->pTxBuffPtr;
hcec->pTxBuffPtr++;
/* clear Tx-Byte request flag */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
}
/* CEC TX end interrupt ------------------------------------------------*/
if ((reg & CEC_FLAG_TXEND) != 0U)
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND))
{
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
@@ -854,21 +855,21 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
}
/* ----------------------------Rx/Tx Error Management----------------------------------*/
if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | CEC_ISR_TXERR |
CEC_ISR_TXACKE)) != 0U)
if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR |
CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)
{
hcec->ErrorCode = reg;
hcec->ErrorCode = itflag;
__HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE);
if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
{
hcec->Init.RxBuffer -= hcec->RxXferSize;
hcec->RxXferSize = 0U;
hcec->RxState = HAL_CEC_STATE_READY;
}
else if (((reg & CEC_ISR_ARBLST) == 0U) && ((reg & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
{
/* Set the CEC state ready to be able to start again the process */
hcec->gState = HAL_CEC_STATE_READY;
@@ -957,9 +958,10 @@ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
* the configuration information for the specified CEC module.
* @retval HAL state
*/
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec)
{
uint32_t temp1, temp2;
uint32_t temp1;
uint32_t temp2;
temp1 = hcec->gState;
temp2 = hcec->RxState;
@@ -972,7 +974,7 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
* the configuration information for the specified CEC.
* @retval CEC Error Code
*/
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec)
{
return hcec->ErrorCode;
}
@@ -993,4 +995,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
/**
* @}
*/

94
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c
View File

@@ -289,9 +289,41 @@ void HAL_MPU_Enable(uint32_t MPU_Control)
__ISB();
}
/**
* @brief Enables the MPU Region.
* @retval None
*/
void HAL_MPU_EnableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Enable the Region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Disables the MPU Region.
* @retval None
*/
void HAL_MPU_DisableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
@@ -300,41 +332,45 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
if ((MPU_Init->Enable) != RESET)
{
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
else
{
MPU->RBAR = 0x00U;
MPU->RASR = 0x00U;
}
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
/* Apply configuration */
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
#endif /* __MPU_PRESENT */
/**
* @brief Clear pending events.
* @retval None
*/
void HAL_CORTEX_ClearEvent(void)
{
__SEV();
__WFE();
}
/**
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)

4
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c
View File

@@ -147,7 +147,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
__HAL_CRC_DR_RESET(hcrc);
/* Reset IDR register content */
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
__HAL_CRC_SET_IDR(hcrc, 0);
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
@@ -303,7 +303,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
* @param hcrc CRC handle
* @retval HAL state
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
{
/* Return CRC handle state */
return hcrc->State;

187
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c
View File

@@ -30,7 +30,8 @@
The CRYP HAL driver can be used in CRYP or TinyAES IP as follows:
(#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
(##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES IP
(##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or
__HAL_RCC_AES_CLK_ENABLE for TinyAES IP
(##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
(+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
@@ -71,7 +72,7 @@
the CRYP peripheral is configured and processes the buffer in input.
At second call, no need to Initialize the CRYP, user have to get current configuration via
HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
new parametres, finally user can start encryption/decryption.
new parameters, finally user can start encryption/decryption.
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
@@ -277,7 +278,8 @@
* @{
*/
#define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is
299 clock cycles.*/
#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
#define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
@@ -1011,7 +1013,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Statrt DES/TDES encryption process */
/* Start DES/TDES encryption process */
status = CRYP_TDES_Process(hcryp, Timeout);
break;
@@ -1022,7 +1024,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u
/* AES encryption */
status = CRYP_AES_Encrypt(hcryp, Timeout);
break;
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
case CRYP_AES_GCM:
/* AES GCM encryption */
@@ -1035,7 +1037,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u
/* AES CCM encryption */
status = CRYP_AESCCM_Process(hcryp, Timeout);
break;
#endif /* GCM CCM defined*/
#endif /* GCM CCM defined*/
default:
hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
/* Change the CRYP peripheral state */
@@ -1197,7 +1199,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u
/* AES decryption */
status = CRYP_AES_Decrypt(hcryp, Timeout);
break;
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
case CRYP_AES_GCM:
/* AES GCM decryption */
@@ -1209,7 +1211,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u
/* AES CCM decryption */
status = CRYP_AESCCM_Process(hcryp, Timeout);
break;
#endif /* GCM CCM defined*/
#endif /* GCM CCM defined*/
default:
hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
/* Change the CRYP peripheral state */
@@ -1369,7 +1371,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
status = CRYP_AES_Encrypt_IT(hcryp);
break;
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
case CRYP_AES_GCM:
status = CRYP_AESGCM_Process_IT(hcryp) ;
@@ -1379,7 +1381,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
status = CRYP_AESCCM_Process_IT(hcryp);
break;
#endif /* GCM CCM defined*/
#endif /* GCM CCM defined*/
default:
hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
/* Change the CRYP peripheral state */
@@ -1534,7 +1536,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
/* AES decryption */
status = CRYP_AES_Decrypt_IT(hcryp);
break;
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
case CRYP_AES_GCM:
/* AES GCM decryption */
@@ -1546,7 +1548,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
/* AES CCMdecryption */
status = CRYP_AESCCM_Process_IT(hcryp);
break;
#endif /* GCM CCM defined*/
#endif /* GCM CCM defined*/
default:
hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
/* Change the CRYP peripheral state */
@@ -1736,7 +1738,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
(uint32_t)(hcryp->pCrypOutBuffPtr));
break;
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
case CRYP_AES_GCM:
/* AES GCM encryption */
status = CRYP_AESGCM_Process_DMA(hcryp) ;
@@ -1746,7 +1748,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
/* AES CCM encryption */
status = CRYP_AESCCM_Process_DMA(hcryp);
break;
#endif /* GCM CCM defined*/
#endif /* GCM CCM defined*/
default:
hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
/* Change the CRYP peripheral state */
@@ -1806,7 +1808,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Start DMA process transfer for AES */
CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr),
(hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
break;
case CRYP_AES_GCM_GMAC:
@@ -1932,7 +1935,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
/* AES decryption */
status = CRYP_AES_Decrypt_DMA(hcryp);
break;
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
case CRYP_AES_GCM:
/* AES GCM decryption */
status = CRYP_AESGCM_Process_DMA(hcryp) ;
@@ -1942,7 +1945,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
/* AES CCM decryption */
status = CRYP_AESCCM_Process_DMA(hcryp);
break;
#endif /* GCM CCM defined*/
#endif /* GCM CCM defined*/
default:
hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
/* Change the CRYP peripheral state */
@@ -2051,7 +2054,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
{
CRYP_AES_IT(hcryp); /*AES*/
}
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM))
{
/* if header phase */
@@ -2064,7 +2067,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
}
}
#endif /* GCM CCM defined*/
#endif /* GCM CCM defined*/
else
{
/* Nothing to do */
@@ -2268,7 +2271,8 @@ static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t T
if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
{
/* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
/* Read the output block from the Output FIFO and put them in temporary Buffer
then get CrypOutBuff from temporary buffer */
for (i = 0U; i < 2U; i++)
{
temp[i] = hcryp->Instance->DOUT;
@@ -2337,7 +2341,8 @@ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
{
if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)
{
/* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
/* Read the output block from the Output FIFO and put them in temporary Buffer
then get CrypOutBuff from temporary buffer */
for (i = 0U; i < 2U; i++)
{
temp[i] = hcryp->Instance->DOUT;
@@ -2533,15 +2538,17 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
/* Increment the pointer before writing the input block in the IN FIFO to make sure that
when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value
and it is ready for the next operation. */
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
#else /* CRYP */
@@ -2867,15 +2874,17 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
/* Increment the pointer before writing the input block in the IN FIFO to make sure that
when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value
and it is ready for the next operation. */
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
#else /* CRYP */
@@ -3113,17 +3122,17 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
#if defined (CRYP)
hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
if ((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
{
/* Disable CRYP (not allowed in GCM)*/
__HAL_CRYP_DISABLE(hcryp);
}
#else /*NO GCM CCM */
#else /*NO GCM CCM */
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
#endif /* GCM CCM defined*/
#endif /* GCM CCM defined*/
#else /* AES */
CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
@@ -3315,7 +3324,7 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
#if defined (CRYP)
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
#endif
#endif /* CRYP */
#if defined (CRYP)
@@ -3361,7 +3370,8 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
{
/* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
/* Read the output block from the Output FIFO and put them in temporary buffer
then get CrypOutBuff from temporary buffer */
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUT;
@@ -3411,7 +3421,8 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
/* Read the output block from the output FIFO and put them in temporary buffer
then get CrypOutBuff from temporary buffer*/
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUTR;
@@ -3441,7 +3452,7 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
#if defined (CRYP)
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
#endif
#endif /* CRYP */
if (hcryp->State == HAL_CRYP_STATE_BUSY)
{
@@ -3480,7 +3491,8 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
/* Read the output block from the output FIFO and put them in temporary buffer
then get CrypOutBuff from temporary buffer */
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUT;
@@ -3516,10 +3528,10 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
#else /*AES*/
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
/* Read the output block from the output FIFO and put them in temporary buffer
then get CrypOutBuff from temporary buffer*/
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUTR;
@@ -4288,13 +4300,15 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
if (hcryp->Size != 0U)
{
/* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
/* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will
be incorrectly generated for GCM Encryption:
Workaround is implemented in polling mode, so if last block of
payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */
/* Set the input and output addresses and start DMA transfer */
if ((hcryp->Size % 16U) == 0U)
{
CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U),
(uint32_t)(hcryp->pCrypOutBuffPtr));
}
else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
{
@@ -4523,7 +4537,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
else
{
/*Write Header block in the IN FIFO without last block */
for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U)));
loopcounter += 4U)
{
/* Write the input block in the data input register */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
@@ -4736,8 +4751,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
if ((hcryp->Size % 16U) != 0U)
{
/* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of
128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
/* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption
only when ciphertext blocks size is multiple of 128 bits. If lthe size of
the last block of payload is inferior to 128 bits, when CCM decryption
is selected, then the TAG message will be wrong.*/
CRYP_Workaround(hcryp, Timeout);
}
@@ -4919,7 +4935,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
uint32_t loopcounter;
uint32_t npblb;
uint32_t lastwordsize;
#endif
#endif /* AES */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
@@ -5115,7 +5131,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
else
{
/*Write Header block in the IN FIFO without last block */
for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U)));
loopcounter += 4U)
{
/* Write the input block in the data input register */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
@@ -5192,7 +5209,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
if ((hcryp->Size % 16U) == 0U)
{
CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U),
(uint32_t)(hcryp->pCrypOutBuffPtr));
}
else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
{
@@ -5320,7 +5338,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
}
/**
* @brief Sets the payload phase in iterrupt mode
* @brief Sets the payload phase in interrupt mode
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval state
@@ -5378,7 +5396,8 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
}
if (hcryp->CrypOutCount < (hcryp->Size / 4U))
{
/* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
/* Read the output block from the Output FIFO and put them in temporary buffer
then get CrypOutBuff from temporary buffer */
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUT;
@@ -5417,7 +5436,8 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
}
else if ((hcryp->Size % 16U) != 0U)
{
/* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption
/* Size should be %4 in word and %16 in byte otherwise TAG will
be incorrectly generated for GCM Encryption & CCM Decryption
Workaround is implemented in polling mode, so if last block of
payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
@@ -5497,7 +5517,8 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
}
#else /* AES */
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
/* Read the output block from the output FIFO and put them in temporary buffer
then get CrypOutBuff from temporary buffer*/
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUTR;
@@ -5545,22 +5566,23 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call Input transfer complete callback */
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
}
else /* Last block of payload < 128bit*/
{
/* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode, so if last block of
payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */
generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode,
so if last block of payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly
generated for GCM Encryption & CCM Decryption. */
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
@@ -5607,7 +5629,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
uint32_t tmp;
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
}; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
@@ -5710,7 +5733,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
{
/* Enter last bytes, padded with zeroes */
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
tmp &= mask[(((hcryp->Init.DataType) >> 5) * 2U) + (size_in_bytes % 4U)];
hcryp->Instance->DIN = tmp;
loopcounter++;
/* Pad the data with zeros to have a complete block */
@@ -5911,7 +5934,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
uint32_t tmp;
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
}; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
@@ -5922,7 +5946,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
{
headersize_in_bytes = hcryp->Init.HeaderSize;
}
if (headersize_in_bytes != 0U)
{
@@ -6023,7 +6047,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
{
/* Enter last bytes, padded with zeroes */
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
tmp &= mask[(((hcryp->Init.DataType) >> 5) * 2U) + (headersize_in_bytes % 4U)];
hcryp->Instance->DIN = tmp;
loopcounter++;
/* Pad the data with zeros to have a complete block */
@@ -6164,7 +6188,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
/* Last block optionally pad the data with zeros*/
for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes /4U) % 4U)); loopcounter++)
for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
@@ -6247,15 +6271,16 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t loopcounter;
uint32_t headersize_in_bytes;
#if defined(AES)
uint32_t lastwordsize;
uint32_t npblb;
#endif
uint32_t headersize_in_bytes;
#endif /* AES */
uint32_t tmp;
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
}; /* 8-bit data type */
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
{
@@ -6324,15 +6349,15 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
{
/* Enter last bytes, padded with zeros */
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
tmp &= mask[(((hcryp->Init.DataType) >> 5) * 2U) + (headersize_in_bytes % 4U)];
hcryp->Instance->DIN = tmp;
loopcounter++;
hcryp->CrypHeaderCount++;
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DIN = 0x0U;
loopcounter++;
while (loopcounter < 4U)
{
hcryp->Instance->DIN = 0x0U;
loopcounter++;
hcryp->CrypHeaderCount++;
}
}
@@ -6463,10 +6488,10 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
loopcounter++;
hcryp->CrypHeaderCount++;
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0x0U;
loopcounter++;
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0x0U;
loopcounter++;
hcryp->CrypHeaderCount++;
}
}
@@ -7109,8 +7134,6 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T
* @}
*/
/**
* @}
*/

1
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c
View File

@@ -93,7 +93,6 @@
/* Private function prototypes -----------------------------------------------*/
/* Exported functions---------------------------------------------------------*/
/** @addtogroup CRYPEx_Exported_Functions
* @{

135
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c
View File

@@ -99,9 +99,9 @@
A DMA request can be generated when an external trigger (but not a software trigger)
occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
DMA1 requests are mapped as following:
(#) DAC channel1 mapped on DMA1 Stream5 channel7 which must be
(#) DAC channel1 mapped on DMA1 Stream5 channel7 which must be
already configured
(#) DAC channel2 mapped on DMA1 Stream6 channel7 which must be
(#) DAC channel2 mapped on DMA1 Stream6 channel7 which must be
already configured
[..]
@@ -168,7 +168,7 @@
and a pointer to the user callback function.
Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
weak (overridden) function. It allows to reset following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
@@ -183,9 +183,9 @@
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
reset to the legacy weak (overridden) functions in the HAL_DAC_Init
and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -200,7 +200,7 @@
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
and weak (overridden) callbacks are used.
*** DAC HAL driver macros list ***
=============================================
@@ -270,7 +270,7 @@
*/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
{
/* Check DAC handle */
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
@@ -331,7 +331,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
*/
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
{
/* Check DAC handle */
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
@@ -434,6 +434,12 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
*/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -489,6 +495,12 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -519,11 +531,21 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
uint32_t Alignment)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpreg = 0U;
#if defined(DAC_CHANNEL2_SUPPORT)
HAL_StatusTypeDef status;
#else
HAL_StatusTypeDef status = HAL_ERROR;
#endif /* DAC_CHANNEL2_SUPPORT */
uint32_t tmpreg;
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -560,12 +582,10 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
/* Get DHR12L1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
break;
case DAC_ALIGN_8B_R:
default: /* case DAC_ALIGN_8B_R */
/* Get DHR8R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
break;
default:
break;
}
}
#if defined(DAC_CHANNEL2_SUPPORT)
@@ -594,17 +614,13 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
/* Get DHR12L2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
break;
case DAC_ALIGN_8B_R:
default: /* case DAC_ALIGN_8B_R */
/* Get DHR8R2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
break;
default:
break;
}
}
#endif /* DAC_CHANNEL2_SUPPORT */
/* Enable the DMA Stream */
if (Channel == DAC_CHANNEL_1)
{
/* Enable the DAC DMA underrun interrupt */
@@ -653,6 +669,12 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
*/
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -701,10 +723,13 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
{
if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
uint32_t itsource = hdac->Instance->CR;
uint32_t itflag = hdac->Instance->SR;
if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1)
{
/* Check underrun flag of DAC channel 1 */
if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1)
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
@@ -716,7 +741,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
/* Disable the selected DAC channel1 DMA request */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
__HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1);
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@@ -728,10 +753,10 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
}
#if defined(DAC_CHANNEL2_SUPPORT)
if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2)
{
/* Check underrun flag of DAC channel 2 */
if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2)
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
@@ -743,7 +768,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
/* Disable the selected DAC channel2 DMA request */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
__HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2);
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@@ -776,6 +801,12 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, ui
{
__IO uint32_t tmp = 0UL;
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
@@ -893,10 +924,13 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval The selected DAC channel data output value.
*/
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel)
{
uint32_t result = 0;
/* Check the DAC peripheral handle */
assert_param(hdac != NULL);
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -925,11 +959,19 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpreg1;
uint32_t tmpreg2;
/* Check the DAC peripheral handle and channel configuration struct */
if ((hdac == NULL) || (sConfig == NULL))
{
return HAL_ERROR;
}
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
@@ -944,7 +986,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
/* Get the DAC CR value */
tmpreg1 = hdac->Instance->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << (Channel & 0x10UL));
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1))
<< (Channel & 0x10UL));
/* Configure for the selected DAC channel: buffer output, trigger */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
@@ -963,7 +1006,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
return status;
}
/**
@@ -992,7 +1035,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
* the configuration information for the specified DAC.
* @retval HAL state
*/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac)
{
/* Return DAC handle state */
return hdac->State;
@@ -1005,7 +1048,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
* the configuration information for the specified DAC.
* @retval DAC Error Code
*/
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac)
{
return hdac->ErrorCode;
}
@@ -1028,7 +1071,9 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DAC Callback
* To be used instead of the weak (surcharged) predefined callback
* To be used instead of the weak (overridden) predefined callback
* @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register
* callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
* @param hdac DAC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1052,6 +1097,12 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
if (pCallback == NULL)
{
/* Update the error code */
@@ -1059,9 +1110,6 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdac);
if (hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackID)
@@ -1132,14 +1180,14 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdac);
return status;
}
/**
* @brief Unregister a User DAC Callback
* DAC Callback is redirected to the weak (surcharged) predefined callback
* DAC Callback is redirected to the weak (overridden) predefined callback
* @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register
* callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1160,8 +1208,11 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdac);
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
if (hdac->State == HAL_DAC_STATE_READY)
{
@@ -1247,8 +1298,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdac);
return status;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
@@ -1334,8 +1383,6 @@ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
#endif /* DAC */
#endif /* HAL_DAC_MODULE_ENABLED */
/**
* @}
*/

43
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c
View File

@@ -23,15 +23,6 @@
##### How to use this driver #####
==============================================================================
[..]
*** Dual mode IO operation ***
==============================
[..]
(+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
Channel 1 and Channel 2.
*** Signal generation operation ***
===================================
[..]
@@ -61,6 +52,7 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -100,6 +92,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
{
uint32_t tmp_swtrig = 0UL;
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdac);
@@ -141,6 +139,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
*/
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
{
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
@@ -180,6 +184,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
*/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
{
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
@@ -230,6 +240,12 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32
*/
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
{
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
@@ -275,6 +291,12 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Align
uint32_t data;
uint32_t tmp;
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_ALIGN(Alignment));
assert_param(IS_DAC_DATA(Data1));
@@ -391,7 +413,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
* the configuration information for the specified DAC.
* @retval The selected DAC channel data output value.
*/
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac)
{
uint32_t tmp = 0UL;
@@ -492,4 +514,3 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
/**
* @}
*/

18
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c
View File

@@ -346,6 +346,8 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
*/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
{
HAL_StatusTypeDef status;
/* Initialize the second memory address */
uint32_t SecondMemAddress = 0U;
@@ -381,7 +383,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
if(Length <= 0xFFFFU)
{
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
status = HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
}
else /* DCMI_DOUBLE_BUFFER Mode */
{
@@ -408,7 +410,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
SecondMemAddress = (uint32_t)(pData + (4U*hdcmi->XferSize));
/* Start DMA multi buffer transfer */
HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
status = HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
}
/* Enable Capture */
@@ -418,7 +420,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
__HAL_UNLOCK(hdcmi);
/* Return function status */
return HAL_OK;
return status;
}
/**
@@ -572,7 +574,10 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
/* Abort the DMA Transfer */
HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK)
{
DCMI_DMAError(hdcmi->DMA_Handle);
}
}
/* Overflow interrupt management ********************************************/
if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
@@ -590,7 +595,10 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
/* Abort the DMA Transfer */
HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK)
{
DCMI_DMAError(hdcmi->DMA_Handle);
}
}
/* Line Interrupt management ************************************************/
if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)

544
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c
View File

@@ -2,7 +2,7 @@
******************************************************************************
* @file stm32f4xx_hal_dfsdm.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
* @brief This file provides firmware functions to manage the following
* functionalities of the Digital Filter for Sigma-Delta Modulators
* (DFSDM) peripherals:
* + Initialization and configuration of channels and filters
@@ -26,7 +26,7 @@
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -43,7 +43,7 @@
(++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(#) Configure the output clock, input, serial interface, analog watchdog,
offset and data right bit shift parameters for this channel using the
offset and data right bit shift parameters for this channel using the
HAL_DFSDM_ChannelInit() function.
*** Channel clock absence detector ***
@@ -57,36 +57,36 @@
clock absence is detected.
(#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
HAL_DFSDM_ChannelCkabStop_IT().
(#) Please note that the same mode (polling or interrupt) has to be used
(#) Please note that the same mode (polling or interrupt) has to be used
for all channels because the channels are sharing the same interrupt.
(#) Please note also that in interrupt mode, if clock absence detector is
stopped for one channel, interrupt will be disabled for all channels.
*** Channel short circuit detector ***
======================================
[..]
[..]
(#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
or HAL_DFSDM_ChannelScdStart_IT().
(#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
circuit.
(#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
(#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
short circuit is detected.
(#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
or HAL_DFSDM_ChannelScdStop_IT().
(#) Please note that the same mode (polling or interrupt) has to be used
(#) Please note that the same mode (polling or interrupt) has to be used
for all channels because the channels are sharing the same interrupt.
(#) Please note also that in interrupt mode, if short circuit detector is
stopped for one channel, interrupt will be disabled for all channels.
*** Channel analog watchdog value ***
=====================================
[..]
[..]
(#) Get analog watchdog filter value of a channel using
HAL_DFSDM_ChannelGetAwdValue().
*** Channel offset value ***
=====================================
[..]
[..]
(#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().
*** Filter initialization ***
@@ -105,21 +105,21 @@
*** Filter regular channel conversion ***
=========================================
[..]
[..]
(#) Select regular channel and enable/disable continuous mode using
HAL_DFSDM_FilterConfigRegChannel().
(#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
HAL_DFSDM_FilterRegularMsbStart_DMA().
(#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
(#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
the end of regular conversion.
(#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
at the end of regular conversion.
(#) Get value of regular conversion and corresponding channel using
(#) Get value of regular conversion and corresponding channel using
HAL_DFSDM_FilterGetRegularValue().
(#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
(#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
half transfer and at the transfer complete. Please note that
half transfer and at the transfer complete. Please note that
HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
circular mode.
(#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
@@ -132,15 +132,15 @@
(#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
HAL_DFSDM_FilterInjectedMsbStart_DMA().
(#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
(#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
the end of injected conversion.
(#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
at the end of injected conversion.
(#) Get value of injected conversion and corresponding channel using
(#) Get value of injected conversion and corresponding channel using
HAL_DFSDM_FilterGetInjectedValue().
(#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
(#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
half transfer and at the transfer complete. Please note that
half transfer and at the transfer complete. Please note that
HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
circular mode.
(#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
@@ -201,7 +201,7 @@
and a pointer to the user callback function.
[..]
For specific DFSDM filter analog watchdog callback use dedicated register callback:
For specific DFSDM filter analog watchdog callback use dedicated register callback:
HAL_DFSDM_Filter_RegisterAwdCallback().
[..]
@@ -237,11 +237,11 @@
HAL_DFSDM_Filter_UnRegisterAwdCallback().
[..]
By default, after the call of init function and if the state is RESET
all callbacks are reset to the corresponding legacy weak functions:
By default, after the call of init function and if the state is RESET
all callbacks are reset to the corresponding legacy weak functions:
examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak functions in the init and de-init only when these
reset to the legacy weak functions in the init and de-init only when these
callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the init and de-init keep and use
the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -251,13 +251,13 @@
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the init/de-init.
In that case first register the MspInit/MspDeInit user callbacks using
In that case first register the MspInit/MspDeInit user callbacks using
HAL_DFSDM_Channel_RegisterCallback() or
HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
[..]
When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
not defined, the callback registering feature is not available
and weak callbacks are used.
@endverbatim
@@ -275,7 +275,7 @@
/** @defgroup DFSDM DFSDM
* @brief DFSDM HAL driver module
* @{
*/
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -296,7 +296,7 @@
/**
* @}
*/
/** @addtogroup DFSDM_Private_Macros
/** @addtogroup DFSDM_Private_Macros
* @{
*/
@@ -324,7 +324,7 @@ DFSDM_Channel_HandleTypeDef* a_dfsdm2ChannelHandle[DFSDM2_CHANNEL_NUMBER] = {NUL
* @{
*/
static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);
static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance);
static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance);
static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
@@ -345,7 +345,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma);
*/
/** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
* @brief Channel initialization and de-initialization functions
* @brief Channel initialization and de-initialization functions
*
@verbatim
==============================================================================
@@ -371,7 +371,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
DFSDM_Channel_HandleTypeDef **channelHandleTable;
DFSDM_Channel_TypeDef* channel0Instance;
#endif /* defined(DFSDM2_Channel0) */
/* Check DFSDM Channel handle */
if(hdfsdm_channel == NULL)
{
@@ -390,7 +390,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
#if defined(DFSDM2_Channel0)
/* Get channel counter, channel handle table and channel 0 instance */
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
@@ -405,13 +405,13 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
channelHandleTable = a_dfsdm2ChannelHandle;
channel0Instance = DFSDM2_Channel0;
}
/* Check that channel has not been already initialized */
if(channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
{
return HAL_ERROR;
}
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/* Reset callback pointers to the weak predefined callbacks */
hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
@@ -427,10 +427,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
/* Call MSP init function */
HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
#endif
/* Update the channel counter */
(*channelCounterPtr)++;
/* Configure output serial clock and enable global DFSDM interface only for first channel */
if(*channelCounterPtr == 1U)
{
@@ -438,59 +438,59 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
/* Set the output serial clock source */
channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
channel0Instance->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
/* Reset clock divider */
channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
{
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
/* Set the output clock divider */
channel0Instance->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
channel0Instance->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
DFSDM_CHCFGR1_CKOUTDIV_Pos);
}
/* enable the DFSDM global interface */
channel0Instance->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
}
/* Set channel input parameters */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
DFSDM_CHCFGR1_CHINSEL);
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
hdfsdm_channel->Init.Input.DataPacking |
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
hdfsdm_channel->Init.Input.DataPacking |
hdfsdm_channel->Init.Input.Pins);
/* Set serial interface parameters */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
hdfsdm_channel->Init.SerialInterface.SpiClock);
/* Set analog watchdog parameters */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
/* Set channel offset and right bit shift */
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
(hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
/* Enable DFSDM channel */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
/* Set DFSDM Channel to ready state */
hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
/* Store channel handle in DFSDM channel handle table */
channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
#else
/* Check that channel has not been already initialized */
if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
{
return HAL_ERROR;
}
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/* Reset callback pointers to the weak predefined callbacks */
hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
@@ -506,10 +506,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
/* Call MSP init function */
HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
#endif
/* Update the channel counter */
v_dfsdm1ChannelCounter++;
/* Configure output serial clock and enable global DFSDM interface only for first channel */
if(v_dfsdm1ChannelCounter == 1U)
{
@@ -517,53 +517,53 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
/* Set the output serial clock source */
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
/* Reset clock divider */
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
{
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
/* Set the output clock divider */
DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
DFSDM_CHCFGR1_CKOUTDIV_Pos);
}
/* enable the DFSDM global interface */
DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
}
/* Set channel input parameters */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
DFSDM_CHCFGR1_CHINSEL);
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
hdfsdm_channel->Init.Input.DataPacking |
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
hdfsdm_channel->Init.Input.DataPacking |
hdfsdm_channel->Init.Input.Pins);
/* Set serial interface parameters */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
hdfsdm_channel->Init.SerialInterface.SpiClock);
/* Set analog watchdog parameters */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
/* Set channel offset and right bit shift */
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
(hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
/* Enable DFSDM channel */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
/* Set DFSDM Channel to ready state */
hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
/* Store channel handle in DFSDM channel handle table */
a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
#endif /* DFSDM2_Channel0 */
return HAL_OK;
}
@@ -573,13 +573,13 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
{
#if defined(DFSDM2_Channel0)
__IO uint32_t* channelCounterPtr;
DFSDM_Channel_HandleTypeDef **channelHandleTable;
DFSDM_Channel_TypeDef* channel0Instance;
#endif /* defined(DFSDM2_Channel0) */
/* Check DFSDM Channel handle */
if(hdfsdm_channel == NULL)
{
@@ -588,7 +588,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
#if defined(DFSDM2_Channel0)
/* Get channel counter, channel handle table and channel 0 instance */
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
@@ -603,7 +603,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch
channelHandleTable = a_dfsdm2ChannelHandle;
channel0Instance = DFSDM2_Channel0;
}
/* Check that channel has not been already deinitialized */
if(channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
{
@@ -612,10 +612,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch
/* Disable the DFSDM channel */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
/* Update the channel counter */
(*channelCounterPtr)--;
/* Disable global DFSDM at deinit of last channel */
if(*channelCounterPtr == 0U)
{
@@ -647,10 +647,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch
/* Disable the DFSDM channel */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
/* Update the channel counter */
v_dfsdm1ChannelCounter--;
/* Disable global DFSDM at deinit of last channel */
if(v_dfsdm1ChannelCounter == 0U)
{
@@ -868,7 +868,7 @@ HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeD
* @note Same mode has to be used for all channels.
* @note If clock is not available on this channel during 5 seconds,
* clock absence detection will not be activated and function
* will return HAL_TIMEOUT error.
* will return HAL_TIMEOUT error.
* @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
@@ -884,7 +884,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -902,7 +902,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm
else
{
filter0Instance = DFSDM2_Filter0;
}
}
/* Get channel number from channel instance */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
@@ -942,7 +942,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm
break;
}
}
#endif /* DFSDM2_Channel0 */
#endif /* DFSDM2_Channel0 */
if(status == HAL_OK)
{
@@ -960,7 +960,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm
* @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
uint32_t Timeout)
{
uint32_t tickstart;
@@ -968,7 +968,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs
#if defined(DFSDM2_Channel0)
DFSDM_Filter_TypeDef* filter0Instance;
#endif /* defined(DFSDM2_Channel0) */
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
@@ -981,7 +981,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs
else
{
#if defined(DFSDM2_Channel0)
/* Get channel counter, channel handle table and channel 0 instance */
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
{
@@ -994,7 +994,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs
/* Get channel number from channel instance */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
/* Get timeout */
tickstart = HAL_GetTick();
@@ -1011,13 +1011,13 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs
}
}
}
/* Clear clock absence detection flag */
filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
#else
filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
#else
/* Get channel number from channel instance */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
/* Get timeout */
tickstart = HAL_GetTick();
@@ -1034,10 +1034,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs
}
}
}
/* Clear clock absence detection flag */
DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
#endif /* defined(DFSDM2_Channel0) */
#endif /* defined(DFSDM2_Channel0) */
/* Return function status */
return HAL_OK;
}
@@ -1058,7 +1058,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -1077,7 +1077,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_
else
{
filter0Instance = DFSDM2_Filter0;
}
}
/* Stop clock absence detection */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
@@ -1089,16 +1089,16 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_
#else
/* Stop clock absence detection */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
/* Clear clock absence flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
#endif /* DFSDM2_Channel0 */
#endif /* DFSDM2_Channel0 */
}
/* Return function status */
return status;
}
/**
* @brief This function allows to start clock absence detection in interrupt mode.
* @note Same mode has to be used for all channels.
@@ -1119,7 +1119,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -1168,7 +1168,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf
/* Start clock absence detection */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
}
#else
#else
/* Get channel number from channel instance */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
@@ -1198,14 +1198,14 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
}
#endif /* defined(DFSDM2_Channel0) */
#endif /* defined(DFSDM2_Channel0) */
}
/* Return function status */
return status;
}
/**
* @brief Clock absence detection callback.
* @brief Clock absence detection callback.
* @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
@@ -1234,7 +1234,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -1253,7 +1253,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs
else
{
filter0Instance = DFSDM2_Filter0;
}
}
/* Stop clock absence detection */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
@@ -1263,12 +1263,12 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs
filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Disable clock absence detection interrupt */
filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
#else
/* Stop clock absence detection */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
/* Clear clock absence flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
@@ -1302,7 +1302,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -1315,7 +1315,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
Threshold);
/* Start short circuit detection */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
}
@@ -1329,7 +1329,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_
* @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
uint32_t Timeout)
{
uint32_t tickstart;
@@ -1337,7 +1337,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd
#if defined(DFSDM2_Channel0)
DFSDM_Filter_TypeDef* filter0Instance;
#endif /* defined(DFSDM2_Channel0) */
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
@@ -1379,7 +1379,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd
}
}
}
/* Clear short circuit detection flag */
filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
@@ -1403,7 +1403,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd
/* Clear short circuit detection flag */
DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
#endif /* DFSDM2_Channel0 */
#endif /* DFSDM2_Channel0 */
/* Return function status */
return HAL_OK;
@@ -1421,11 +1421,11 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c
uint32_t channel;
#if defined(DFSDM2_Channel0)
DFSDM_Filter_TypeDef* filter0Instance;
#endif /* defined(DFSDM2_Channel0) */
#endif /* defined(DFSDM2_Channel0) */
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -1439,7 +1439,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c
/* Clear short circuit detection flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
#if defined(DFSDM2_Channel0)
/* Get channel counter, channel handle table and channel 0 instance */
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
@@ -1477,13 +1477,13 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs
HAL_StatusTypeDef status = HAL_OK;
#if defined(DFSDM2_Channel0)
DFSDM_Filter_TypeDef* filter0Instance;
#endif /* defined(DFSDM2_Channel0) */
#endif /* defined(DFSDM2_Channel0) */
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -1513,7 +1513,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
Threshold);
/* Start short circuit detection */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
}
@@ -1522,7 +1522,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs
}
/**
* @brief Short circuit detection callback.
* @brief Short circuit detection callback.
* @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
@@ -1551,7 +1551,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -1562,7 +1562,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd
{
/* Stop short circuit detection */
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
/* Clear short circuit detection flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
#if defined(DFSDM2_Channel0)
@@ -1596,7 +1596,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd
* @param hdfsdm_channel DFSDM channel handle.
* @retval Channel analog watchdog value.
*/
int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
}
@@ -1616,7 +1616,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf
/* Check parameters */
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
/* Check DFSDM channel state */
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
@@ -1655,7 +1655,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf
* @param hdfsdm_channel DFSDM channel handle.
* @retval DFSDM channel state.
*/
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
/* Return DFSDM channel handle state */
return hdfsdm_channel->State;
@@ -1666,7 +1666,7 @@ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTyp
*/
/** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
* @brief Filter initialization and de-initialization functions
* @brief Filter initialization and de-initialization functions
*
@verbatim
==============================================================================
@@ -1706,27 +1706,27 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
/* Check parameters compatibility */
if((hdfsdm_filter->Instance == DFSDM1_Filter0) &&
((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
if((hdfsdm_filter->Instance == DFSDM1_Filter0) &&
((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
{
return HAL_ERROR;
}
#if defined (DFSDM2_Channel0)
if((hdfsdm_filter->Instance == DFSDM2_Filter0) &&
((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
#if defined (DFSDM2_Channel0)
if((hdfsdm_filter->Instance == DFSDM2_Filter0) &&
((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
{
return HAL_ERROR;
}
}
#endif /* DFSDM2_Channel0 */
/* Initialize DFSDM filter variables with default values */
hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF;
hdfsdm_filter->InjectedChannelsNbr = 1U;
hdfsdm_filter->InjConvRemaining = 1U;
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/* Reset callback pointers to the weak predefined callbacks */
hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;
@@ -1793,7 +1793,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
}
/* Set filter parameters */
hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
@@ -1805,13 +1805,13 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger;
hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
/* Enable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
/* Set DFSDM filter to ready state */
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
return HAL_OK;
}
@@ -1830,10 +1830,10 @@ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filt
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
/* Disable the DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
/* Call MSP deinit function */
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
if(hdfsdm_filter->MspDeInitCallback == NULL)
@@ -2147,14 +2147,14 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *h
uint32_t ContinuousMode)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
/* Check DFSDM filter state */
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
(hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
{
/* Configure channel and continuous mode for regular conversion */
@@ -2170,7 +2170,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *h
}
/* Store continuous mode information */
hdfsdm_filter->RegularContMode = ContinuousMode;
}
}
else
{
status = HAL_ERROR;
@@ -2195,9 +2195,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *h
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
/* Check DFSDM filter state */
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
(hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
{
/* Configure channel for injected conversion */
@@ -2252,7 +2252,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *h
/**
* @brief This function allows to start regular conversion in polling mode.
* @note This function should be called only when DFSDM filter instance is
* @note This function should be called only when DFSDM filter instance is
* in idle state or if injected conversion is ongoing.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
@@ -2304,7 +2304,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe
else
{
/* Get timeout */
tickstart = HAL_GetTick();
tickstart = HAL_GetTick();
/* Wait end of regular conversion */
while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
@@ -2376,7 +2376,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm
/**
* @brief This function allows to start regular conversion in interrupt mode.
* @note This function should be called only when DFSDM filter instance is
* @note This function should be called only when DFSDM filter instance is
* in idle state or if injected conversion is ongoing.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
@@ -2394,7 +2394,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hd
{
/* Enable interrupts for regular conversions */
hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
/* Start regular conversion */
DFSDM_RegConvStart(hdfsdm_filter);
}
@@ -2430,7 +2430,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf
{
/* Disable interrupts for regular conversions */
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
/* Stop regular conversion */
DFSDM_RegConvStop(hdfsdm_filter);
}
@@ -2440,7 +2440,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf
/**
* @brief This function allows to start regular conversion in DMA mode.
* @note This function should be called only when DFSDM filter instance is
* @note This function should be called only when DFSDM filter instance is
* in idle state or if injected conversion is ongoing.
* Please note that data on buffer will contain signed regular conversion
* value on 24 most significant bits and corresponding channel on 3 least
@@ -2492,7 +2492,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *h
hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
DFSDM_DMARegularHalfConvCplt : NULL;
/* Start DMA in interrupt mode */
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
(uint32_t) pData, Length) != HAL_OK)
@@ -2518,7 +2518,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *h
/**
* @brief This function allows to start regular conversion in DMA mode and to get
* only the 16 most significant bits of conversion.
* @note This function should be called only when DFSDM filter instance is
* @note This function should be called only when DFSDM filter instance is
* in idle state or if injected conversion is ongoing.
* Please note that data on buffer will contain signed 16 most significant
* bits of regular conversion.
@@ -2569,7 +2569,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef
hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
DFSDM_DMARegularHalfConvCplt : NULL;
/* Start DMA in interrupt mode */
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \
(uint32_t) pData, Length) != HAL_OK)
@@ -2637,19 +2637,19 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd
* @param Channel Corresponding channel of regular conversion.
* @retval Regular conversion value
*/
int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t *Channel)
{
uint32_t reg = 0U;
int32_t value = 0;
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(Channel != NULL);
/* Get value of data register for regular channel */
reg = hdfsdm_filter->Instance->FLTRDATAR;
/* Extract channel and regular conversion value */
*Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos);
@@ -2660,7 +2660,7 @@ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filte
/**
* @brief This function allows to start injected conversion in polling mode.
* @note This function should be called only when DFSDM filter instance is
* @note This function should be called only when DFSDM filter instance is
* in idle state or if regular conversion is ongoing.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
@@ -2712,7 +2712,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe
else
{
/* Get timeout */
tickstart = HAL_GetTick();
tickstart = HAL_GetTick();
/* Wait end of injected conversions */
while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
@@ -2752,7 +2752,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
}
/* end of injected sequence, reset the value */
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
hdfsdm_filter->InjectedChannelsNbr : 1U;
@@ -2794,7 +2794,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd
/**
* @brief This function allows to start injected conversion in interrupt mode.
* @note This function should be called only when DFSDM filter instance is
* @note This function should be called only when DFSDM filter instance is
* in idle state or if regular conversion is ongoing.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
@@ -2812,7 +2812,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *h
{
/* Enable interrupts for injected conversions */
hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
/* Start injected conversion */
DFSDM_InjConvStart(hdfsdm_filter);
}
@@ -2848,7 +2848,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd
{
/* Disable interrupts for injected conversions */
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
/* Stop injected conversion */
DFSDM_InjConvStop(hdfsdm_filter);
}
@@ -2858,7 +2858,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd
/**
* @brief This function allows to start injected conversion in DMA mode.
* @note This function should be called only when DFSDM filter instance is
* @note This function should be called only when DFSDM filter instance is
* in idle state or if regular conversion is ongoing.
* Please note that data on buffer will contain signed injected conversion
* value on 24 most significant bits and corresponding channel on 3 least
@@ -2908,7 +2908,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *
hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
DFSDM_DMAInjectedHalfConvCplt : NULL;
/* Start DMA in interrupt mode */
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
(uint32_t) pData, Length) != HAL_OK)
@@ -2934,7 +2934,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *
/**
* @brief This function allows to start injected conversion in DMA mode and to get
* only the 16 most significant bits of conversion.
* @note This function should be called only when DFSDM filter instance is
* @note This function should be called only when DFSDM filter instance is
* in idle state or if regular conversion is ongoing.
* Please note that data on buffer will contain signed 16 most significant
* bits of injected conversion.
@@ -2983,7 +2983,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDe
hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
DFSDM_DMAInjectedHalfConvCplt : NULL;
/* Start DMA in interrupt mode */
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \
(uint32_t) pData, Length) != HAL_OK)
@@ -3051,19 +3051,19 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h
* @param Channel Corresponding channel of injected conversion.
* @retval Injected conversion value
*/
int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t *Channel)
{
uint32_t reg = 0U;
int32_t value = 0;
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(Channel != NULL);
/* Get value of data register for injected channel */
reg = hdfsdm_filter->Instance->FLTJDATAR;
/* Extract channel and injected conversion value */
*Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos);
@@ -3079,7 +3079,7 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
DFSDM_Filter_AwdParamTypeDef *awdParam)
const DFSDM_Filter_AwdParamTypeDef *awdParam)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -3091,7 +3091,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfs
assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
@@ -3133,7 +3133,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
@@ -3148,7 +3148,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_
/* Clear all analog watchdog flags */
hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
/* Reset thresholds and break signals */
hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
@@ -3175,7 +3175,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
@@ -3187,7 +3187,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi
{
/* Set channels for extreme detector */
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos);
hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos);
}
/* Return function status */
return status;
@@ -3206,7 +3206,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
@@ -3221,7 +3221,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil
/* Clear extreme detector values */
reg1 = hdfsdm_filter->Instance->FLTEXMAX;
reg2 = hdfsdm_filter->Instance->FLTEXMIN;
reg2 = hdfsdm_filter->Instance->FLTEXMIN;
UNUSED(reg1); /* To avoid GCC warning */
UNUSED(reg2); /* To avoid GCC warning */
}
@@ -3236,19 +3236,19 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil
* @retval Extreme detector maximum value
* This value is between Min_Data = -8388608 and Max_Data = 8388607.
*/
int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t *Channel)
{
uint32_t reg = 0U;
int32_t value = 0;
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(Channel != NULL);
/* Get value of extreme detector maximum register */
reg = hdfsdm_filter->Instance->FLTEXMAX;
/* Extract channel and extreme detector maximum value */
*Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos);
@@ -3264,19 +3264,19 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
* @retval Extreme detector minimum value
* This value is between Min_Data = -8388608 and Max_Data = 8388607.
*/
int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t *Channel)
{
uint32_t reg = 0U;
int32_t value = 0;
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(Channel != NULL);
/* Get value of extreme detector minimum register */
reg = hdfsdm_filter->Instance->FLTEXMIN;
/* Extract channel and extreme detector minimum value */
*Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos);
@@ -3291,17 +3291,17 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
* @retval Conversion time value
* @note To get time in second, this value has to be divided by DFSDM clock frequency.
*/
uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
uint32_t reg = 0U;
uint32_t value = 0U;
/* Check parameters */
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
/* Get value of conversion timer register */
reg = hdfsdm_filter->Instance->FLTCNVTIMR;
/* Extract conversion time value */
value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos);
@@ -3410,7 +3410,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
uint32_t reg = 0U;
uint32_t threshold = 0U;
uint32_t channel = 0U;
/* Get channel and threshold */
reg = hdfsdm_filter->Instance->FLTAWSR;
threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
@@ -3442,7 +3442,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
uint32_t reg = 0U;
uint32_t channel = 0U;
reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
while(channel < DFSDM1_CHANNEL_NUMBER)
@@ -3468,7 +3468,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
reg = reg >> 1U;
}
}
#if defined (DFSDM2_Channel0)
#if defined (DFSDM2_Channel0)
/* Check if clock absence occurs */
else if((hdfsdm_filter->Instance == DFSDM2_Filter0) && \
((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \
@@ -3476,7 +3476,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
uint32_t reg = 0U;
uint32_t channel = 0U;
reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
while(channel < DFSDM2_CHANNEL_NUMBER)
@@ -3502,7 +3502,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
reg = reg >> 1U;
}
}
#endif /* DFSDM2_Channel0 */
#endif /* DFSDM2_Channel0 */
/* Check if short circuit detection occurs */
else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \
@@ -3510,7 +3510,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
uint32_t reg = 0U;
uint32_t channel = 0U;
/* Get channel */
reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
while((reg & 1U) == 0U)
@@ -3518,7 +3518,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
channel++;
reg = reg >> 1U;
}
/* Clear short circuit detection flag */
hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
@@ -3529,7 +3529,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
#endif
}
#if defined (DFSDM2_Channel0)
#if defined (DFSDM2_Channel0)
/* Check if short circuit detection occurs */
else if((hdfsdm_filter->Instance == DFSDM2_Filter0) && \
((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \
@@ -3537,7 +3537,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
uint32_t reg = 0U;
uint32_t channel = 0U;
/* Get channel */
reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
while((reg & 1U) == 0U)
@@ -3545,7 +3545,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
channel++;
reg = reg >> 1U;
}
/* Clear short circuit detection flag */
hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
@@ -3556,11 +3556,11 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
HAL_DFSDM_ChannelScdCallback(a_dfsdm2ChannelHandle[channel]);
#endif
}
#endif /* DFSDM2_Channel0 */
#endif /* DFSDM2_Channel0 */
}
/**
* @brief Regular conversion complete callback.
* @brief Regular conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
* using HAL_DFSDM_FilterGetRegularValue.
* @param hdfsdm_filter DFSDM filter handle.
@@ -3576,7 +3576,7 @@ __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs
}
/**
* @brief Half regular conversion complete callback.
* @brief Half regular conversion complete callback.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
@@ -3590,7 +3590,7 @@ __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *
}
/**
* @brief Injected conversion complete callback.
* @brief Injected conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
* using HAL_DFSDM_FilterGetInjectedValue.
* @param hdfsdm_filter DFSDM filter handle.
@@ -3606,7 +3606,7 @@ __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs
}
/**
* @brief Half injected conversion complete callback.
* @brief Half injected conversion complete callback.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
@@ -3620,7 +3620,7 @@ __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *
}
/**
* @brief Filter analog watchdog callback.
* @brief Filter analog watchdog callback.
* @param hdfsdm_filter DFSDM filter handle.
* @param Channel Corresponding channel.
* @param Threshold Low or high threshold has been reached.
@@ -3633,14 +3633,14 @@ __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filte
UNUSED(hdfsdm_filter);
UNUSED(Channel);
UNUSED(Threshold);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.
*/
}
/**
* @brief Error callback.
* @brief Error callback.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
@@ -3676,7 +3676,7 @@ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_fil
* @param hdfsdm_filter DFSDM filter handle.
* @retval DFSDM filter state.
*/
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
/* Return DFSDM filter handle state */
return hdfsdm_filter->State;
@@ -3687,7 +3687,7 @@ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDe
* @param hdfsdm_filter DFSDM filter handle.
* @retval DFSDM filter error code.
*/
uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
return hdfsdm_filter->ErrorCode;
}
@@ -3711,13 +3711,13 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
/**
* @brief Select the DFSDM2 as clock source for the bitstream clock.
* @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
* before HAL_DFSDM_BitstreamClock_Start()
* @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
* before HAL_DFSDM_BitstreamClock_Start()
*/
void HAL_DFSDM_BitstreamClock_Start(void)
{
uint32_t tmp = 0;
uint32_t tmp = 0;
tmp = SYSCFG->MCHDLYCR;
tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL));
@@ -3726,14 +3726,14 @@ void HAL_DFSDM_BitstreamClock_Start(void)
/**
* @brief Stop the DFSDM2 as clock source for the bitstream clock.
* @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
* before HAL_DFSDM_BitstreamClock_Stop()
* @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
* before HAL_DFSDM_BitstreamClock_Stop()
* @retval None
*/
void HAL_DFSDM_BitstreamClock_Stop(void)
{
uint32_t tmp = 0U;
uint32_t tmp = 0U;
tmp = SYSCFG->MCHDLYCR;
tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL));
@@ -3744,16 +3744,16 @@ void HAL_DFSDM_BitstreamClock_Stop(void)
* @brief Disable Delay Clock for DFSDM1/2.
* @param MCHDLY HAL_MCHDLY_CLOCK_DFSDM2.
* HAL_MCHDLY_CLOCK_DFSDM1.
* @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
* before HAL_DFSDM_DisableDelayClock()
* @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
* before HAL_DFSDM_DisableDelayClock()
* @retval None
*/
void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY)
{
uint32_t tmp = 0U;
uint32_t tmp = 0U;
assert_param(IS_DFSDM_DELAY_CLOCK(MCHDLY));
tmp = SYSCFG->MCHDLYCR;
if(MCHDLY == HAL_MCHDLY_CLOCK_DFSDM2)
{
@@ -3771,13 +3771,13 @@ void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY)
* @brief Enable Delay Clock for DFSDM1/2.
* @param MCHDLY HAL_MCHDLY_CLOCK_DFSDM2.
* HAL_MCHDLY_CLOCK_DFSDM1.
* @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
* before HAL_DFSDM_EnableDelayClock()
* @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
* before HAL_DFSDM_EnableDelayClock()
* @retval None
*/
void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY)
{
uint32_t tmp = 0U;
uint32_t tmp = 0U;
assert_param(IS_DFSDM_DELAY_CLOCK(MCHDLY));
@@ -3797,17 +3797,17 @@ void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY)
*/
void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source)
{
uint32_t tmp = 0U;
uint32_t tmp = 0U;
assert_param(IS_DFSDM_CLOCKIN_SELECTION(source));
tmp = SYSCFG->MCHDLYCR;
if((source == HAL_DFSDM2_CKIN_PAD) || (source == HAL_DFSDM2_CKIN_DM))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CFG);
if(source == HAL_DFSDM2_CKIN_PAD)
if(source == HAL_DFSDM2_CKIN_PAD)
{
source = 0x000000U;
}
@@ -3823,23 +3823,23 @@ void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source)
/**
* @brief Select the source for CKOut signals for DFSDM1/2.
* @param source: DFSDM2_CKOUT_DFSDM2.
* DFSDM2_CKOUT_M27.
* DFSDM2_CKOUT_M27.
* DFSDM1_CKOUT_DFSDM1.
* DFSDM1_CKOUT_M27.
* @retval None
*/
void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source)
{
uint32_t tmp = 0U;
uint32_t tmp = 0U;
assert_param(IS_DFSDM_CLOCKOUT_SELECTION(source));
tmp = SYSCFG->MCHDLYCR;
if((source == HAL_DFSDM2_CKOUT_DFSDM2) || (source == HAL_DFSDM2_CKOUT_M27))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CKOSEL);
if(source == HAL_DFSDM2_CKOUT_DFSDM2)
{
source = 0x000U;
@@ -3856,19 +3856,19 @@ void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source)
/**
* @brief Select the source for DataIn0 signals for DFSDM1/2.
* @param source DATAIN0_DFSDM2_PAD.
* DATAIN0_DFSDM2_DATAIN1.
* DATAIN0_DFSDM2_DATAIN1.
* DATAIN0_DFSDM1_PAD.
* DATAIN0_DFSDM1_DATAIN1.
* DATAIN0_DFSDM1_DATAIN1.
* @retval None
*/
void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source)
{
uint32_t tmp = 0U;
uint32_t tmp = 0U;
assert_param(IS_DFSDM_DATAIN0_SRC_SELECTION(source));
tmp = SYSCFG->MCHDLYCR;
if((source == HAL_DATAIN0_DFSDM2_PAD)|| (source == HAL_DATAIN0_DFSDM2_DATAIN1))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D0SEL);
@@ -3887,26 +3887,26 @@ void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source)
/**
* @brief Select the source for DataIn2 signals for DFSDM1/2.
* @param source DATAIN2_DFSDM2_PAD.
* DATAIN2_DFSDM2_DATAIN3.
* DATAIN2_DFSDM2_DATAIN3.
* DATAIN2_DFSDM1_PAD.
* DATAIN2_DFSDM1_DATAIN3.
* @retval None
*/
void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source)
{
uint32_t tmp = 0U;
uint32_t tmp = 0U;
assert_param(IS_DFSDM_DATAIN2_SRC_SELECTION(source));
tmp = SYSCFG->MCHDLYCR;
if((source == HAL_DATAIN2_DFSDM2_PAD)|| (source == HAL_DATAIN2_DFSDM2_DATAIN3))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D2SEL);
if (source == HAL_DATAIN2_DFSDM2_PAD)
{
source = 0x0000U;
}
}
}
else
{
@@ -3923,7 +3923,7 @@ void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source)
*/
void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source)
{
uint32_t tmp = 0U;
uint32_t tmp = 0U;
assert_param(IS_DFSDM_DATAIN4_SRC_SELECTION(source));
@@ -3941,20 +3941,20 @@ void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source)
*/
void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source)
{
uint32_t tmp = 0U;
uint32_t tmp = 0U;
assert_param(IS_DFSDM_DATAIN6_SRC_SELECTION(source));
tmp = SYSCFG->MCHDLYCR;
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D6SEL);
SYSCFG->MCHDLYCR = (source|tmp);
}
/**
* @brief Configure the distribution of the bitstream clock gated from TIM4_OC
* for DFSDM1 or TIM3_OC for DFSDM2
* @brief Configure the distribution of the bitstream clock gated from TIM4_OC
* for DFSDM1 or TIM3_OC for DFSDM2
* @param source DFSDM1_CLKIN0_TIM4OC2
* DFSDM1_CLKIN2_TIM4OC2
* DFSDM1_CLKIN1_TIM4OC1
@@ -3971,7 +3971,7 @@ void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source)
*/
void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source)
{
uint32_t tmp = 0U;
uint32_t tmp = 0U;
assert_param(IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(source));
@@ -3992,7 +3992,7 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source)
else if ((source == HAL_DFSDM2_CLKIN1_TIM3OC3) || (source == HAL_DFSDM2_CLKIN5_TIM3OC3))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK15SEL);
}else if ((source == HAL_DFSDM2_CLKIN2_TIM3OC2) || (source == HAL_DFSDM2_CLKIN6_TIM3OC2))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK26SEL);
@@ -4001,36 +4001,36 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source)
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK37SEL);
}
if((source == HAL_DFSDM1_CLKIN0_TIM4OC2) ||(source == HAL_DFSDM1_CLKIN1_TIM4OC1)||
(source == HAL_DFSDM2_CLKIN0_TIM3OC4) ||(source == HAL_DFSDM2_CLKIN1_TIM3OC3)||
(source == HAL_DFSDM2_CLKIN2_TIM3OC2) ||(source == HAL_DFSDM2_CLKIN3_TIM3OC1))
{
source = 0x0000U;
}
SYSCFG->MCHDLYCR = (source|tmp);
}
/**
* @brief Configure multi channel delay block: Use DFSDM2 audio clock source as input
* @brief Configure multi channel delay block: Use DFSDM2 audio clock source as input
* clock for DFSDM1 and DFSDM2 filters to Synchronize DFSDMx filters.
* Set the path of the DFSDM2 clock output (dfsdm2_ckout) to the
* DFSDM1/2 CkInx and data inputs channels by configuring following MCHDLY muxes
* or demuxes: M1, M2, M3, M4, M5, M6, M7, M8, DM1, DM2, DM3, DM4, DM5, DM6,
* M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20 based on the
* contains of the DFSDM_MultiChannelConfigTypeDef structure
* contains of the DFSDM_MultiChannelConfigTypeDef structure
* @param mchdlystruct Structure of multi channel configuration
* @retval None
* @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
* @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
* before HAL_DFSDM_ConfigMultiChannelDelay()
* @note The HAL_DFSDM_ConfigMultiChannelDelay() function clears the SYSCFG-MCHDLYCR
* register before setting the new configuration.
* register before setting the new configuration.
*/
void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct)
{
uint32_t mchdlyreg = 0U;
{
uint32_t mchdlyreg = 0U;
assert_param(IS_DFSDM_DFSDM1_CLKOUT(mchdlystruct->DFSDM1ClockOut));
assert_param(IS_DFSDM_DFSDM2_CLKOUT(mchdlystruct->DFSDM2ClockOut));
assert_param(IS_DFSDM_DFSDM1_CLKIN(mchdlystruct->DFSDM1ClockIn));
@@ -4039,7 +4039,7 @@ void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlyst
assert_param(IS_DFSDM_DFSDM2_BIT_CLK(mchdlystruct->DFSDM2BitClkDistribution));
assert_param(IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(mchdlystruct->DFSDM1DataDistribution));
assert_param(IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(mchdlystruct->DFSDM2DataDistribution));
mchdlyreg = (SYSCFG->MCHDLYCR & 0x80103U);
SYSCFG->MCHDLYCR = (mchdlyreg |(mchdlystruct->DFSDM1ClockOut)|(mchdlystruct->DFSDM2ClockOut)|
@@ -4063,11 +4063,11 @@ void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlyst
*/
/**
* @brief DMA half transfer complete callback for regular conversion.
* @brief DMA half transfer complete callback for regular conversion.
* @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
{
/* Get DFSDM filter handle */
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -4081,11 +4081,11 @@ static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
}
/**
* @brief DMA transfer complete callback for regular conversion.
* @brief DMA transfer complete callback for regular conversion.
* @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
{
/* Get DFSDM filter handle */
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -4099,11 +4099,11 @@ static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
}
/**
* @brief DMA half transfer complete callback for injected conversion.
* @brief DMA half transfer complete callback for injected conversion.
* @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
{
/* Get DFSDM filter handle */
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -4117,11 +4117,11 @@ static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
}
/**
* @brief DMA transfer complete callback for injected conversion.
* @brief DMA transfer complete callback for injected conversion.
* @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
{
/* Get DFSDM filter handle */
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -4135,11 +4135,11 @@ static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
}
/**
* @brief DMA error callback.
* @brief DMA error callback.
* @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
{
/* Get DFSDM filter handle */
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -4164,7 +4164,7 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
{
uint32_t nbChannels = 0U;
uint32_t tmp;
/* Get the number of channels from bitfield */
tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);
while(tmp != 0U)
@@ -4183,10 +4183,10 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
* @param Instance DFSDM channel instance.
* @retval Channel number.
*/
static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance)
{
uint32_t channel;
/* Get channel from instance */
#if defined(DFSDM2_Channel0)
if((Instance == DFSDM1_Channel0) || (Instance == DFSDM2_Channel0))
@@ -4261,13 +4261,13 @@ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
{
/* Disable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
/* Set RSYNC bit in DFSDM_FLTCR1 register */
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
/* Enable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
/* If injected conversion was in progress, restart it */
if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
{
@@ -4303,7 +4303,7 @@ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
/* Enable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
/* If injected conversion was in progress, restart it */
if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
{
@@ -4315,7 +4315,7 @@ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
hdfsdm_filter->InjectedChannelsNbr : 1U;
}
/* Update DFSDM filter state */
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
@@ -4338,7 +4338,7 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
{
/* Disable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
{
/* Set JSYNC bit in DFSDM_FLTCR1 register */
@@ -4349,7 +4349,7 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
/* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
}
/* Enable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
@@ -4392,7 +4392,7 @@ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
}
/* Enable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
/* If regular conversion was in progress, restart it */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))

35
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c
View File

@@ -118,7 +118,7 @@
and a pointer to the user callback function.
(#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
weak (overridden) function.
@ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -130,16 +130,16 @@
(+) MspDeInitCallback : DMA2D MspDeInit.
(#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
all callbacks are reset to the corresponding legacy weak (overridden) functions:
examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
reset to the legacy weak (overridden) functions in the @ref HAL_DMA2D_Init
and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
as weak (surcharged) functions. They must be defined by the user to be resorted to.
as weak (overridden) functions. They must be defined by the user to be resorted to.
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
@@ -151,7 +151,7 @@
When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
and weak (overridden) callbacks are used.
[..]
(@) You can refer to the DMA2D HAL driver header file for more useful macros
@@ -314,7 +314,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
/* Before aborting any DMA2D transfer or CLUT loading, check
first whether or not DMA2D clock is enabled */
if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
if (__HAL_RCC_DMA2D_IS_CLK_ENABLED() == 1U)
{
/* Abort DMA2D transfer if any */
if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
@@ -422,7 +422,7 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DMA2D Callback
* To be used instead of the weak (surcharged) predefined callback
* To be used instead of the weak (overridden) predefined callback
* @param hdma2d DMA2D handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -521,7 +521,7 @@ HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DM
/**
* @brief Unregister a DMA2D Callback
* DMA2D Callback is redirected to the weak (surcharged) predefined callback
* DMA2D Callback is redirected to the weak (overridden) predefined callback
* @param hdma2d DMA2D handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -562,11 +562,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_
break;
case HAL_DMA2D_MSPINIT_CB_ID :
hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */
break;
case HAL_DMA2D_MSPDEINIT_CB_ID :
hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */
break;
default :
@@ -582,11 +582,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_
switch (CallbackID)
{
case HAL_DMA2D_MSPINIT_CB_ID :
hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */
break;
case HAL_DMA2D_MSPDEINIT_CB_ID :
hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */
break;
default :
@@ -971,7 +971,8 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
@@ -1025,7 +1026,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLU
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
uint32_t LayerIdx)
{
/* Check the parameters */
@@ -1728,7 +1729,7 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
DMA2D_LayerCfgTypeDef *pLayerCfg;
const DMA2D_LayerCfgTypeDef *pLayerCfg;
uint32_t regMask;
uint32_t regValue;
@@ -2007,7 +2008,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t
* the configuration information for the DMA2D.
* @retval HAL state
*/
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d)
{
return hdma2d->State;
}
@@ -2018,7 +2019,7 @@ HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
* the configuration information for DMA2D.
* @retval DMA2D Error Code
*/
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d)
{
return hdma2d->ErrorCode;
}

442
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c
View File

@@ -130,7 +130,7 @@
all callbacks are set to the corresponding weak functions:
examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback().
Exception done for MspInit and MspDeInit functions that are respectively
reset to the legacy weak (surcharged) functions in the HAL_DSI_Init()
reset to the legacy weak (overridden) functions in the HAL_DSI_Init()
and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -395,24 +395,53 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
}
}
__HAL_DSI_ENABLE(hdsi);
/************************ Set the DSI clock parameters ************************/
/* Set the TX escape clock division factor */
hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
/*************************** Set the PHY parameters ***************************/
/* D-PHY clock and digital enable*/
hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
hdsi->Instance->PCTLR |= DSI_PCTLR_DEN;
hdsi->Instance->PCTLR |= DSI_PCTLR_CKE;
/* Clock lane configuration */
hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
/* Configure the number of active data lanes */
hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
/************************ Set the DSI clock parameters ************************/
/* Get tick */
tickstart = HAL_GetTick();
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | DSI_PSR_PSSC))
{
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
/* Set the TX escape clock division factor */
hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
return HAL_TIMEOUT;
}
}
}
else
{
while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | \
DSI_PSR_PSS1 | DSI_PSR_PSSC))
{
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
}
/* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
/* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
@@ -431,6 +460,12 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
hdsi->Instance->IER[1U] = 0U;
hdsi->ErrorMsk = 0U;
__HAL_DSI_DISABLE(hdsi);
/* Clock lane configuration */
hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
/* Initialize the error code */
hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
@@ -1628,14 +1663,14 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
uint32_t Mode,
uint32_t NbParams,
uint32_t Param1,
uint8_t *ParametersTable)
const uint8_t *ParametersTable)
{
uint32_t uicounter;
uint32_t nbBytes;
uint32_t count;
uint32_t tickstart;
uint32_t fifoword;
uint8_t *pparams = ParametersTable;
const uint8_t *pparams = ParametersTable;
/* Process locked */
__HAL_LOCK(hdsi);
@@ -1835,6 +1870,95 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
/* Process locked */
__HAL_LOCK(hdsi);
/* Verify the initial status of the DSI Host */
/* Verify that the clock lane and the digital section of the D-PHY are enabled */
if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN))
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Verify that the D-PHY PLL and the reference bias are enabled */
if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
else
{
/* Nothing to do */
}
/* Verify that there are no ULPS exit or request on data lanes */
if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL)) != 0U)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Verify that there are no Transmission trigger */
if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Requires min of 400us delay before reading the PLLLS flag */
/* 1ms delay is inserted that is the minimum HAL delay granularity */
HAL_Delay(1);
/* Verify that D-PHY PLL is locked */
tickstart = HAL_GetTick();
while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U))
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
/* Verify that all active lanes are in Stop state */
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* ULPS Request on Data Lanes */
hdsi->Instance->PUCR |= DSI_PUCR_URDL;
@@ -1898,6 +2022,58 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
/* Process locked */
__HAL_LOCK(hdsi);
/* Verify that all active lanes are in ULPM */
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Turn on the DSI PLL */
__HAL_DSI_PLL_ENABLE(hdsi);
/* Requires min of 400us delay before reading the PLLLS flag */
/* 1ms delay is inserted that is the minimum HAL delay granularity */
HAL_Delay(1);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for the lock of the PLL */
while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
/* Exit ULPS on Data Lanes */
hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
@@ -1947,6 +2123,61 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
/* De-assert the ULPM requests and the ULPM exit bits */
hdsi->Instance->PUCR = 0U;
/* Verify that D-PHY PLL is enabled */
if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Verify that all active lanes are in Stop state */
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Verify that D-PHY PLL is locked */
/* Requires min of 400us delay before reading the PLLLS flag */
/* 1ms delay is inserted that is the minimum HAL delay granularity */
HAL_Delay(1);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for the lock of the PLL */
while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -1967,6 +2198,96 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
/* Process locked */
__HAL_LOCK(hdsi);
/* Verify the initial status of the DSI Host */
/* Verify that the clock lane and the digital section of the D-PHY are enabled */
if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN))
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Verify that the D-PHY PLL and the reference bias are enabled */
if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
else
{
/* Nothing to do */
}
/* Verify that there are no ULPS exit or request on both data and clock lanes */
if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL | DSI_PUCR_UECL | DSI_PUCR_URCL)) != 0U)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Verify that there are no Transmission trigger */
if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Requires min of 400us delay before reading the PLLLS flag */
/* 1ms delay is inserted that is the minimum HAL delay granularity */
HAL_Delay(1);
/* Verify that D-PHY PLL is locked */
tickstart = HAL_GetTick();
while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U))
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
/* Verify that all active lanes are in Stop state */
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0))
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \
DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1))
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Clock lane configuration: no more HS request */
hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
@@ -1979,7 +2300,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until all active lanes exit ULPM */
/* Wait until all active lanes enter ULPM */
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U)
@@ -2039,9 +2360,44 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
/* Process locked */
__HAL_LOCK(hdsi);
/* Verify that all active lanes are in ULPM */
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | \
DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_UAN1 | \
DSI_PSR_PSS1 | DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Turn on the DSI PLL */
__HAL_DSI_PLL_ENABLE(hdsi);
/* Requires min of 400us delay before reading the PLLLS flag */
/* 1ms delay is inserted that is the minimum HAL delay granularity */
HAL_Delay(1);
/* Get tick */
tickstart = HAL_GetTick();
@@ -2114,6 +2470,62 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
/* Restore clock lane configuration to HS */
hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
/* Verify that D-PHY PLL is enabled */
if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Verify that all active lanes are in Stop state */
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0))
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \
DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1))
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Verify that D-PHY PLL is locked */
/* Requires min of 400us delay before reading the PLLLS flag */
/* 1ms delay is inserted that is the minimum HAL delay granularity */
HAL_Delay(1);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for the lock of the PLL */
while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -2722,7 +3134,7 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun
* the configuration information for the DSI.
* @retval HAL state
*/
HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi)
{
return hdsi->State;
}
@@ -2733,7 +3145,7 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
* the configuration information for the DSI.
* @retval DSI Error Code
*/
uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi)
{
/* Get the error code */
return hdsi->ErrorCode;

482
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c
View File

@@ -83,6 +83,7 @@
(##) HAL_ETH_PTP_GetTime(): Get Seconds and Nanoseconds for the Ethernet PTP registers
(##) HAL_ETH_PTP_SetTime(): Set Seconds and Nanoseconds for the Ethernet PTP registers
(##) HAL_ETH_PTP_AddTimeOffset(): Add Seconds and Nanoseconds offset for the Ethernet PTP registers
(##) HAL_ETH_PTP_AddendUpdate(): Update the Addend register
(##) HAL_ETH_PTP_InsertTxTimestamp(): Insert Timestamp in transmission
(##) HAL_ETH_PTP_GetTxTimestamp(): Get transmission timestamp
(##) HAL_ETH_PTP_GetRxTimestamp(): Get reception timestamp
@@ -202,7 +203,7 @@
#define ETH_MACRFCR_MASK 0x00000003U
#define ETH_MTLTQOMR_MASK 0x00000072U
#define ETH_MTLRQOMR_MASK 0x0000007BU
#define ETH_DMAMR_MASK 0x00007802U
#define ETH_DMASBMR_MASK 0x0000D001U
#define ETH_DMACCR_MASK 0x00013FFFU
@@ -234,7 +235,7 @@
#define ETH_REG_WRITE_DELAY 0x00000001U
/* ETHERNET MACCR register Mask */
#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
#define ETH_MACCR_CLEAR_MASK 0xFD20810FU
/* ETHERNET MACFCR register Mask */
#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
@@ -276,12 +277,13 @@
/** @defgroup ETH_Private_Functions ETH Private Functions
* @{
*/
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf);
static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf);
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode);
static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
uint32_t ItMode);
static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth);
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
@@ -289,6 +291,11 @@ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
#ifdef HAL_ETH_USE_PTP
static HAL_StatusTypeDef HAL_ETH_PTP_AddendUpdate(ETH_HandleTypeDef *heth, int32_t timeoffset);
#endif /* HAL_ETH_USE_PTP */
/**
* @}
*/
@@ -406,6 +413,17 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
/*--------------------- ETHERNET MAC Address Configuration ------------------*/
ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
/* Disable MMC Interrupts */
SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM);
/* Disable Rx MMC Interrupts */
SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | \
ETH_MMCRIMR_RFCEM);
/* Disable Tx MMC Interrupts */
SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | \
ETH_MMCTIMR_TGFSCM);
heth->ErrorCode = HAL_ETH_ERROR_NONE;
heth->gState = HAL_ETH_STATE_READY;
@@ -501,7 +519,6 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call
{
/* Update the error code */
heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
@@ -579,7 +596,7 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call
/**
* @brief Unregister an ETH Callback
* ETH callabck is redirected to the weak predefined callback
* ETH callback is redirected to the weak predefined callback
* @param heth eth handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -702,7 +719,7 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
{
heth->gState = HAL_ETH_STATE_BUSY;
/* Set nombre of descriptors to build */
/* Set number of descriptors to build */
heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
/* Build all descriptors */
@@ -761,23 +778,29 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
/* save IT mode to ETH Handle */
heth->RxDescList.ItMode = 1U;
/* Disable MMC Interrupts */
SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM);
/* Disable Rx MMC Interrupts */
SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | \
ETH_MMCRIMR_RFCEM);
/* Disable Tx MMC Interrupts */
SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | \
ETH_MMCTIMR_TGFSCM);
/* Set nombre of descriptors to build */
/* Set number of descriptors to build */
heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
/* Build all descriptors */
ETH_UpdateDescriptor(heth);
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACCR = tmpreg1;
/* Enable the DMA transmission */
SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST);
/* Enable the DMA reception */
SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR);
/* Flush Transmit FIFO */
ETH_FlushTransmitFIFO(heth);
/* Enable the MAC transmission */
SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
@@ -790,21 +813,6 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
/* Enable the MAC reception */
SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACCR = tmpreg1;
/* Flush Transmit FIFO */
ETH_FlushTransmitFIFO(heth);
/* Enable the DMA transmission */
SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST);
/* Enable the DMA reception */
SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR);
/* Enable ETH DMA interrupts:
- Tx complete interrupt
- Rx complete interrupt
@@ -836,6 +844,7 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
{
/* Set the ETH peripheral state to BUSY */
heth->gState = HAL_ETH_STATE_BUSY;
/* Disable the DMA transmission */
CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST);
@@ -903,6 +912,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
/* Disable the MAC reception */
CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACCR;
@@ -949,7 +959,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
* @param Timeout: timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout)
{
uint32_t tickstart;
ETH_DMADescTypeDef *dmatxdesc;
@@ -1024,7 +1034,7 @@ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *
* @param pTxConfig: Hold the configuration of packet to be transmitted
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig)
{
if (pTxConfig == NULL)
{
@@ -1085,7 +1095,6 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
uint32_t bufflength;
uint8_t rxdataready = 0U;
if (pAppBuff == NULL)
{
heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
@@ -1108,9 +1117,9 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_LS) != (uint32_t)RESET)
{
/* Get timestamp high */
heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC6;
heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC7;
/* Get timestamp low */
heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC7;
heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC6;
}
if ((READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_FS) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL))
{
@@ -1121,13 +1130,12 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
heth->RxDescList.RxDataLength = 0;
}
/* Get the Frame Length of the received packet */
bufflength = ((dmarxdesc->DESC0 & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT);
/* Check if last descriptor */
bufflength = heth->Init.RxBuffLen;
if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_LS) != (uint32_t)RESET)
{
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
bufflength = ((dmarxdesc->DESC0 & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
/* Save Last descriptor index */
heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC0;
@@ -1194,6 +1202,7 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
{
uint32_t descidx;
uint32_t tailidx;
uint32_t desccount;
ETH_DMADescTypeDef *dmarxdesc;
uint8_t *buff = NULL;
@@ -1231,19 +1240,13 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
{
if (heth->RxDescList.ItMode == 0U)
{
WRITE_REG(dmarxdesc->DESC1, ETH_DMARXDESC_DIC | ETH_RX_BUF_SIZE | ETH_DMARXDESC_RCH);
WRITE_REG(dmarxdesc->DESC1, heth->Init.RxBuffLen | ETH_DMARXDESC_DIC | ETH_DMARXDESC_RCH);
}
else
{
WRITE_REG(dmarxdesc->DESC1, ETH_RX_BUF_SIZE | ETH_DMARXDESC_RCH);
WRITE_REG(dmarxdesc->DESC1, heth->Init.RxBuffLen | ETH_DMARXDESC_RCH);
}
/* Before transferring the ownership to DMA, make sure that the RX descriptors bits writing
is fully performed.
The __DMB() instruction is added to avoid any potential compiler optimization that
may lead to abnormal behavior. */
__DMB();
SET_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN);
/* Increment current rx descriptor index */
@@ -1256,8 +1259,14 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
if (heth->RxDescList.RxBuildDescCnt != desccount)
{
/* Set the tail pointer index */
tailidx = (ETH_RX_DESC_CNT + descidx - 1U) % ETH_RX_DESC_CNT;
/* DMB instruction to avoid race condition */
__DMB();
/* Set the Tail pointer address */
WRITE_REG(heth->Instance->DMARPDR, 0);
WRITE_REG(heth->Instance->DMARPDR, ((uint32_t)(heth->Init.RxDesc + (tailidx))));
heth->RxDescList.RxBuildDescIdx = descidx;
heth->RxDescList.RxBuildDescCnt = desccount;
@@ -1317,7 +1326,7 @@ __weak void HAL_ETH_RxAllocateCallback(uint8_t **buff)
/**
* @brief Rx Link callback.
* @param pStart: pointer to packet start
* @param pStart: pointer to packet end
* @param pEnd: pointer to packet end
* @param buff: pointer to received data
* @param Length: received data length
* @retval None
@@ -1376,7 +1385,7 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth)
* @param pErrorCode: pointer to uint32_t to hold the error code
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode)
HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode)
{
/* Get error bits. */
*pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXDESC_ERRORS_MASK);
@@ -1459,7 +1468,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
if (dmatxdesclist->PacketAddress[idx] == NULL)
{
/* No packet in use, skip to next. */
idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U);
INCR_TX_DESC_INDEX(idx, 1U);
pktInUse = 0U;
}
@@ -1469,17 +1478,28 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
if ((heth->Init.TxDesc[idx].DESC0 & ETH_DMATXDESC_OWN) == 0U)
{
#ifdef HAL_ETH_USE_PTP
/* Get timestamp low */
timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC6;
/* Get timestamp high */
timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC7;
if ((heth->Init.TxDesc[idx].DESC0 & ETH_DMATXDESC_LS)
&& (heth->Init.TxDesc[idx].DESC0 & ETH_DMATXDESC_TTSS))
{
/* Get timestamp low */
timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC6;
/* Get timestamp high */
timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC7;
}
else
{
timestamp->TimeStampHigh = timestamp->TimeStampLow = UINT32_MAX;
}
#endif /* HAL_ETH_USE_PTP */
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/*Call registered callbacks*/
#ifdef HAL_ETH_USE_PTP
/* Handle Ptp */
heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX)
{
heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
}
#endif /* HAL_ETH_USE_PTP */
/* Release the packet. */
heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]);
@@ -1487,7 +1507,10 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
/* Call callbacks */
#ifdef HAL_ETH_USE_PTP
/* Handle Ptp */
HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX)
{
HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
}
#endif /* HAL_ETH_USE_PTP */
/* Release the packet. */
HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]);
@@ -1497,7 +1520,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
dmatxdesclist->PacketAddress[idx] = NULL;
/* Update the transmit relesae index and number of buffers in use. */
idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U);
INCR_TX_DESC_INDEX(idx, 1U);
dmatxdesclist->BuffersInUse = numOfBuf;
dmatxdesclist->releaseIndex = idx;
}
@@ -1530,6 +1553,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT
return HAL_ERROR;
}
/* Mask the Timestamp Trigger interrupt */
CLEAR_BIT(heth->Instance->MACIMR, ETH_MACIMR_TSTIM);
tmpTSCR = ptpconfig->Timestamp |
((uint32_t)ptpconfig->TimestampUpdate << ETH_PTPTSCR_TSFCU_Pos) |
((uint32_t)ptpconfig->TimestampAll << ETH_PTPTSCR_TSSARFE_Pos) |
@@ -1555,7 +1581,10 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT
if (ptpconfig->TimestampAddendUpdate == ENABLE)
{
SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSARU);
while ((heth->Instance->PTPTSCR & ETH_PTPTSCR_TSARU) != 0) {}
while ((heth->Instance->PTPTSCR & ETH_PTPTSCR_TSARU) != 0)
{
}
}
/* Enable Update mode */
@@ -1564,17 +1593,19 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT
SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSFCU);
}
/* Initialize Time */
time.Seconds = 0;
time.NanoSeconds = 0;
/* Set PTP Configuration done */
heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED;
/* Set Seconds */
time.Seconds = heth->Instance->PTPTSHR;
/* Set NanoSeconds */
time.NanoSeconds = heth->Instance->PTPTSLR;
HAL_ETH_PTP_SetTime(heth, &time);
/* Ptp Init */
SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSTI);
/* Set PTP Configuration done */
heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURATED;
/* Return function status */
return HAL_OK;
}
@@ -1627,13 +1658,13 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT
* @brief Set Seconds and Nanoseconds for the Ethernet PTP registers.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param heth: pointer to a ETH_TimeTypeDef structure that contains
* @param time: pointer to a ETH_TimeTypeDef structure that contains
* time to set
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
{
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
{
/* Set Seconds */
heth->Instance->PTPTSHUR = time->Seconds;
@@ -1641,6 +1672,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *
/* Set NanoSeconds */
heth->Instance->PTPTSLUR = time->NanoSeconds;
/* the system time is updated */
SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSTU);
/* Return function status */
return HAL_OK;
}
@@ -1655,17 +1689,16 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *
* @brief Get Seconds and Nanoseconds for the Ethernet PTP registers.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param heth: pointer to a ETH_TimeTypeDef structure that contains
* @param time: pointer to a ETH_TimeTypeDef structure that contains
* time to get
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
{
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
{
/* Get Seconds */
time->Seconds = heth->Instance->PTPTSHR;
/* Get NanoSeconds */
time->NanoSeconds = heth->Instance->PTPTSLR;
@@ -1683,14 +1716,15 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *
* @brief Update time for the Ethernet PTP registers.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param timeupdate: pointer to a ETH_TIMEUPDATETypeDef structure that contains
* @param timeoffset: pointer to a ETH_PtpUpdateTypeDef structure that contains
* the time update information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
ETH_TimeTypeDef *timeoffset)
{
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
int32_t addendtime ;
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
{
if (ptpoffsettype == HAL_ETH_PTP_NEGATIVE_UPDATE)
{
@@ -1706,6 +1740,11 @@ HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpda
{
heth->Instance->PTPTSLUR = ETH_PTPTSHR_VALUE - timeoffset->NanoSeconds + 1U;
}
/* adjust negative addend register */
addendtime = - timeoffset->NanoSeconds;
HAL_ETH_PTP_AddendUpdate(heth, addendtime);
}
else
{
@@ -1713,8 +1752,15 @@ HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpda
heth->Instance->PTPTSHUR = timeoffset->Seconds;
/* Set nanoSeconds update */
heth->Instance->PTPTSLUR = timeoffset->NanoSeconds;
/* adjust positive addend register */
addendtime = timeoffset->NanoSeconds;
HAL_ETH_PTP_AddendUpdate(heth, addendtime);
}
SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSTU);
/* Return function status */
return HAL_OK;
}
@@ -1725,11 +1771,44 @@ HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpda
}
}
/**
* @brief Update the Addend register
* @param heth: Pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param timeoffset: The value of the time offset to be added to
* the addend register in Nanoseconds
* @retval HAL status
*/
static HAL_StatusTypeDef HAL_ETH_PTP_AddendUpdate(ETH_HandleTypeDef *heth, int32_t timeoffset)
{
uint32_t tmpreg;
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
{
/* update the addend register */
tmpreg = READ_REG(heth->Instance->PTPTSAR);
tmpreg += timeoffset ;
WRITE_REG(heth->Instance->PTPTSAR, tmpreg);
SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSARU);
while ((heth->Instance->PTPTSCR & ETH_PTPTSCR_TSARU) != 0)
{
}
/* Return function status */
return HAL_OK;
}
else
{
/* Return function status */
return HAL_ERROR;
}
}
/**
* @brief Insert Timestamp in transmission.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param txtimestampconf: Enable or Disable timestamp in transmission
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth)
@@ -1738,7 +1817,7 @@ HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth)
uint32_t descidx = dmatxdesclist->CurTxDesc;
ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
{
/* Enable Time Stamp transmission */
SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_TTSE);
@@ -1767,7 +1846,7 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeSt
uint32_t idx = dmatxdesclist->releaseIndex;
ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx];
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
{
/* Get timestamp low */
timestamp->TimeStampLow = dmatxdesc->DESC0;
@@ -1794,7 +1873,7 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeSt
*/
HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp)
{
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
{
/* Get timestamp low */
timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow;
@@ -1848,6 +1927,8 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth)
/**
* @brief Tx Ptp callback.
* @param buff: pointer to application buffer
* @param timestamp: pointer to ETH_TimeStampTypeDef structure that contains
* transmission timestamp
* @retval None
*/
__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp)
@@ -1868,86 +1949,79 @@ __weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestam
*/
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
{
uint32_t mac_flag = READ_REG(heth->Instance->MACSR);
uint32_t dma_flag = READ_REG(heth->Instance->DMASR);
uint32_t dma_itsource = READ_REG(heth->Instance->DMAIER);
uint32_t exti_flag = READ_REG(EXTI->PR);
/* Packet received */
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_RS))
if (((dma_flag & ETH_DMASR_RS) != 0U) && ((dma_itsource & ETH_DMAIER_RIE) != 0U))
{
if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMAIER_RIE))
{
/* Clear the Eth DMA Rx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMASR_RS | ETH_DMASR_NIS);
/* Clear the Eth DMA Rx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMASR_RS | ETH_DMASR_NIS);
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/*Call registered Receive complete callback*/
heth->RxCpltCallback(heth);
/*Call registered Receive complete callback*/
heth->RxCpltCallback(heth);
#else
/* Receive complete callback */
HAL_ETH_RxCpltCallback(heth);
/* Receive complete callback */
HAL_ETH_RxCpltCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
}
/* Packet transmitted */
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_TS))
if (((dma_flag & ETH_DMASR_TS) != 0U) && ((dma_itsource & ETH_DMAIER_TIE) != 0U))
{
if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMAIER_TIE))
{
/* Clear the Eth DMA Tx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMASR_TS | ETH_DMASR_NIS);
/* Clear the Eth DMA Tx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMASR_TS | ETH_DMASR_NIS);
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/*Call registered Transmit complete callback*/
heth->TxCpltCallback(heth);
/*Call registered Transmit complete callback*/
heth->TxCpltCallback(heth);
#else
/* Transfer complete callback */
HAL_ETH_TxCpltCallback(heth);
/* Transfer complete callback */
HAL_ETH_TxCpltCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
}
/* ETH DMA Error */
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_AIS))
if (((dma_flag & ETH_DMASR_AIS) != 0U) && ((dma_itsource & ETH_DMAIER_AISE) != 0U))
{
if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMAIER_AISE))
heth->ErrorCode |= HAL_ETH_ERROR_DMA;
/* if fatal bus error occurred */
if ((dma_flag & ETH_DMASR_FBES) != 0U)
{
heth->ErrorCode |= HAL_ETH_ERROR_DMA;
/* Get DMA error code */
heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_FBES | ETH_DMASR_TPS | ETH_DMASR_RPS));
/* if fatal bus error occurred */
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_FBES))
{
/* Get DMA error code */
heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_FBES | ETH_DMASR_TPS | ETH_DMASR_RPS));
/* Disable all interrupts */
__HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMAIER_NISE | ETH_DMAIER_AISE);
/* Set HAL state to ERROR */
heth->gState = HAL_ETH_STATE_ERROR;
}
else
{
/* Get DMA error status */
heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_ETS | ETH_DMASR_RWTS |
ETH_DMASR_RBUS | ETH_DMASR_AIS));
/* Clear the interrupt summary flag */
__HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMASR_ETS | ETH_DMASR_RWTS |
ETH_DMASR_RBUS | ETH_DMASR_AIS));
}
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/* Call registered Error callback*/
heth->ErrorCallback(heth);
#else
/* Ethernet DMA Error callback */
HAL_ETH_ErrorCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Disable all interrupts */
__HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMAIER_NISE | ETH_DMAIER_AISE);
/* Set HAL state to ERROR */
heth->gState = HAL_ETH_STATE_ERROR;
}
else
{
/* Get DMA error status */
heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_ETS | ETH_DMASR_RWTS |
ETH_DMASR_RBUS | ETH_DMASR_AIS));
/* Clear the interrupt summary flag */
__HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMASR_ETS | ETH_DMASR_RWTS |
ETH_DMASR_RBUS | ETH_DMASR_AIS));
}
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/* Call registered Error callback*/
heth->ErrorCallback(heth);
#else
/* Ethernet DMA Error callback */
HAL_ETH_ErrorCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
/* ETH PMT IT */
if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
if ((mac_flag & ETH_MAC_PMT_IT) != 0U)
{
/* Get MAC Wake-up source and clear the status register pending bit */
heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPMTCSR, (ETH_MACPMTCSR_WFR | ETH_MACPMTCSR_MPR));
@@ -1965,7 +2039,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
/* check ETH WAKEUP exti flag */
if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
if ((exti_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
{
/* Clear ETH WAKEUP Exti pending bit */
__HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
@@ -2106,7 +2180,6 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA
return HAL_OK;
}
/**
* @brief Writes to a PHY register.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
@@ -2116,7 +2189,7 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA
* @param RegValue: the value to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
uint32_t RegValue)
{
uint32_t tmpreg1;
@@ -2184,7 +2257,7 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHY
* the configuration of the MAC.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
{
if (macconf == NULL)
{
@@ -2206,7 +2279,7 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp
macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_APCS) >> 7) > 0U) ? ENABLE : DISABLE;
macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IFG);
macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPCO) >> 10U) > 0U) ? ENABLE : DISABLE;
macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CSTF) >> 25U) > 0U) ? ENABLE : DISABLE;
macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_TFCE) >> 1) > 0U) ? ENABLE : DISABLE;
macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_ZQPD) >> 7) == 0U) ? ENABLE : DISABLE;
@@ -2227,7 +2300,7 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp
* the configuration of the ETH DMA.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
{
if (dmaconf == NULL)
{
@@ -2235,7 +2308,7 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp
}
dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMABMR,
(ETH_DMAARBITRATION_RXPRIORTX | ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1));
(ETH_DMAARBITRATION_RXPRIORTX | ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1));
dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_AAB) >> 25U) > 0U) ? ENABLE : DISABLE;
dmaconf->BurstMode = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_FB | ETH_DMABMR_MB);
dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_RDP);
@@ -2254,6 +2327,7 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp
ETH_DMAOMR_FUGF) >> 6) > 0U) ? ENABLE : DISABLE;
dmaconf->ReceiveThresholdControl = READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_RTC);
dmaconf->SecondFrameOperate = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_OSF) >> 2) > 0U) ? ENABLE : DISABLE;
return HAL_OK;
}
@@ -2331,29 +2405,29 @@ void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
hclk = HAL_RCC_GetHCLKFreq();
/* Set CR bits depending on hclk value */
if ((hclk >= 20000000U) && (hclk < 35000000U))
if (hclk < 35000000U)
{
/* CSR Clock Range between 20-35 MHz */
/* CSR Clock Range between 0-35 MHz */
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
}
else if ((hclk >= 35000000U) && (hclk < 60000000U))
else if (hclk < 60000000U)
{
/* CSR Clock Range between 35-60 MHz */
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
}
else if ((hclk >= 60000000U) && (hclk < 100000000U))
else if (hclk < 100000000U)
{
/* CSR Clock Range between 60-100 MHz */
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
}
else if ((hclk >= 100000000U) && (hclk < 150000000U))
else if (hclk < 150000000U)
{
/* CSR Clock Range between 100-150 MHz */
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
}
else /* ((hclk >= 150000000)&&(hclk <= 183000000))*/
else /* (hclk >= 150000000) */
{
/* CSR Clock Range between 150-183 MHz */
/* CSR Clock >= 150 MHz */
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
}
@@ -2369,7 +2443,7 @@ void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
* the configuration of the ETH MAC filters.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig)
{
uint32_t filterconfig;
uint32_t tmpreg1;
@@ -2384,7 +2458,7 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil
((uint32_t)pFilterConfig->HashMulticast << 2) |
((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
((uint32_t)pFilterConfig->PassAllMulticast << 4) |
((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) |
((uint32_t)((pFilterConfig->BroadcastFilter == ENABLE) ? 1U : 0U) << 5) |
((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
@@ -2410,7 +2484,7 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil
* the configuration of the ETH MAC filters.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
{
if (pFilterConfig == NULL)
{
@@ -2423,7 +2497,7 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil
pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACFFR,
ETH_MACFFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE;
pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_PAM) >> 4) > 0U) ? ENABLE : DISABLE;
pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_BFD) >> 5) == 0U) ? ENABLE : DISABLE;
pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_BFD) >> 5) > 0U) ? ENABLE : DISABLE;
pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_PCF);
pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACFFR,
ETH_MACFFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE;
@@ -2447,7 +2521,8 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil
* @param pMACAddr: Pointer to MAC address buffer data (6 bytes)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
const uint8_t *pMACAddr)
{
uint32_t macaddrlr;
uint32_t macaddrhr;
@@ -2546,7 +2621,7 @@ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBit
* that contains the Power Down configuration
* @retval None.
*/
void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, const ETH_PowerDownConfigTypeDef *pPowerDownConfig)
{
uint32_t powerdownconfig;
@@ -2650,7 +2725,7 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi
* the configuration information for ETHERNET module
* @retval HAL state
*/
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth)
{
return heth->gState;
}
@@ -2661,7 +2736,7 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
* the configuration information for ETHERNET module
* @retval ETH Error Code
*/
uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth)
uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth)
{
return heth->ErrorCode;
}
@@ -2672,7 +2747,7 @@ uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth)
* the configuration information for ETHERNET module
* @retval ETH DMA Error Code
*/
uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth)
{
return heth->DMAErrorCode;
}
@@ -2683,7 +2758,7 @@ uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
* the configuration information for ETHERNET module
* @retval ETH MAC Error Code
*/
uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth)
uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth)
{
return heth->MACErrorCode;
}
@@ -2694,11 +2769,21 @@ uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth)
* the configuration information for ETHERNET module
* @retval ETH MAC WakeUp event source
*/
uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth)
uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth)
{
return heth->MACWakeUpEvent;
}
/**
* @brief Returns the ETH Tx Buffers in use number
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval ETH Tx Buffers in use number
*/
uint32_t HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth)
{
return heth->TxDescList.BuffersInUse;
}
/**
* @}
*/
@@ -2731,17 +2816,18 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
(heth->Instance)->DMAOMR = tmpreg;
}
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf)
{
uint32_t tmpreg1;
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg1 = (heth->Instance)->MACCR;
/* Clear WD, PCE, PS, TE and RE bits */
/* Clear CSTF, WD, PCE, PS, TE and RE bits */
tmpreg1 &= ETH_MACCR_CLEAR_MASK;
tmpreg1 |= (uint32_t)(((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) |
tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) |
((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) |
((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) |
(uint32_t)macconf->InterPacketGapVal |
((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) |
@@ -2788,7 +2874,7 @@ static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *mac
(heth->Instance)->MACFCR = tmpreg1;
}
static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf)
{
uint32_t tmpreg1;
@@ -2854,6 +2940,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
macDefaultConf.ReceiveOwn = ENABLE;
macDefaultConf.LoopbackMode = DISABLE;
macDefaultConf.CRCStripTypePacket = ENABLE;
macDefaultConf.ChecksumOffload = ENABLE;
macDefaultConf.RetryTransmission = DISABLE;
macDefaultConf.AutomaticPadCRCStrip = DISABLE;
@@ -2892,7 +2979,6 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
/* DMA default configuration */
ETH_SetDMAConfig(heth, &dmaDefaultConf);
}
/**
* @brief Configures the selected MAC address.
* @param heth pointer to a ETH_HandleTypeDef structure that contains
@@ -2941,10 +3027,10 @@ static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
{
dmatxdesc = heth->Init.TxDesc + i;
WRITE_REG(dmatxdesc->DESC0, 0x0);
WRITE_REG(dmatxdesc->DESC1, 0x0);
WRITE_REG(dmatxdesc->DESC2, 0x0);
WRITE_REG(dmatxdesc->DESC3, 0x0);
WRITE_REG(dmatxdesc->DESC0, 0x0U);
WRITE_REG(dmatxdesc->DESC1, 0x0U);
WRITE_REG(dmatxdesc->DESC2, 0x0U);
WRITE_REG(dmatxdesc->DESC3, 0x0U);
WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
@@ -2986,22 +3072,21 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
{
dmarxdesc = heth->Init.RxDesc + i;
WRITE_REG(dmarxdesc->DESC0, 0x0);
WRITE_REG(dmarxdesc->DESC1, 0x0);
WRITE_REG(dmarxdesc->DESC2, 0x0);
WRITE_REG(dmarxdesc->DESC3, 0x0);
WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
WRITE_REG(dmarxdesc->DESC0, 0x0U);
WRITE_REG(dmarxdesc->DESC1, 0x0U);
WRITE_REG(dmarxdesc->DESC2, 0x0U);
WRITE_REG(dmarxdesc->DESC3, 0x0U);
WRITE_REG(dmarxdesc->BackupAddr0, 0x0U);
WRITE_REG(dmarxdesc->BackupAddr1, 0x0U);
/* Set Own bit of the Rx descriptor Status */
dmarxdesc->DESC0 = ETH_DMARXDESC_OWN;
/* Set Buffer1 size and Second Address Chained bit */
dmarxdesc->DESC1 = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
dmarxdesc->DESC1 = heth->Init.RxBuffLen | ETH_DMARXDESC_RCH;
/* Enable Ethernet DMA Rx Descriptor interrupt */
dmarxdesc->DESC1 &= ~ETH_DMARXDESC_DIC;
/* Set Rx descritors addresses */
WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
@@ -3015,11 +3100,11 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
}
}
WRITE_REG(heth->RxDescList.RxDescIdx, 0);
WRITE_REG(heth->RxDescList.RxDescCnt, 0);
WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0);
WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0);
WRITE_REG(heth->RxDescList.ItMode, 0);
WRITE_REG(heth->RxDescList.RxDescIdx, 0U);
WRITE_REG(heth->RxDescList.RxDescCnt, 0U);
WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U);
WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U);
WRITE_REG(heth->RxDescList.ItMode, 0U);
/* Set Receive Descriptor List Address */
WRITE_REG(heth->Instance->DMARDLAR, (uint32_t) heth->Init.RxDesc);
@@ -3031,10 +3116,11 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param pTxConfig: Tx packet configuration
* @param ItMode: Enable or disable Tx EOT interrept
* @param ItMode: Enable or disable Tx EOT interrupt
* @retval Status
*/
static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
uint32_t ItMode)
{
ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
uint32_t descidx = dmatxdesclist->CurTxDesc;
@@ -3045,6 +3131,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer;
uint32_t bd_count = 0;
uint32_t primask_bit;
/* Current Tx Descriptor Owned by DMA: cannot be used by the application */
if ((READ_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN) == ETH_DMATXDESC_OWN)
@@ -3082,11 +3169,6 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
/* Mark it as First Descriptor */
SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_FS);
/* Ensure rest of descriptor is written to RAM before the OWN bit */
__DMB();
/* set OWN bit of FIRST descriptor */
SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN);
/* only if the packet is split into more than one descriptors > 1 */
while (txbuffer->next != NULL)
{
@@ -3107,9 +3189,6 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
/* Get current descriptor address */
dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
/* Clear the FD bit of new Descriptor */
CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_FS);
/* Current Tx Descriptor Owned by DMA: cannot be used by the application */
if ((READ_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN) == ETH_DMATXDESC_OWN)
|| (dmatxdesclist->PacketAddress[descidx] != NULL))
@@ -3134,6 +3213,9 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
return HAL_ETH_ERROR_BUSY;
}
/* Clear the FD bit of new Descriptor */
CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_FS);
descnbr += 1U;
/* Get the next Tx buffer in the list */
@@ -3166,19 +3248,26 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
/* Mark it as LAST descriptor */
SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_LS);
/* Get address of first descriptor */
dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
/* Ensure rest of descriptor is written to RAM before the OWN bit */
__DMB();
/* set OWN bit of FIRST descriptor */
SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN);
/* Save the current packet address to expose it to the application */
dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress;
dmatxdesclist->CurTxDesc = descidx;
/* disable the interrupt */
__disable_irq();
/* Enter critical section */
primask_bit = __get_PRIMASK();
__set_PRIMASK(1);
dmatxdesclist->BuffersInUse += bd_count + 1U;
/* Enable interrupts back */
__enable_irq();
/* Exit critical section: restore previous priority mask */
__set_PRIMASK(primask_bit);
/* Return function status */
return HAL_ETH_ERROR_NONE;
@@ -3217,4 +3306,3 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
/**
* @}
*/

14
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c
View File

@@ -64,7 +64,7 @@
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
@@ -75,7 +75,7 @@
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@@ -300,8 +300,8 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = (SYSCFG->EXTICR[linepos >> 2u] << 16u );
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 28u);
regval = SYSCFG->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
}
}
@@ -469,6 +469,9 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
uint32_t linepos;
uint32_t maskline;
/* Prevent unused argument(s) compilation warning */
UNUSED(Edge);
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
@@ -496,6 +499,9 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
uint32_t maskline;
/* Prevent unused argument(s) compilation warning */
UNUSED(Edge);
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));

340
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c
View File

@@ -3,23 +3,23 @@
* @file stm32f4xx_hal_flash.c
* @author MCD Application Team
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
* + Program operations functions
* + Memory Control functions
* + Memory Control functions
* + Peripheral Errors functions
*
*
@verbatim
==============================================================================
##### FLASH peripheral features #####
==============================================================================
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
to the Flash memory. It implements the erase and program Flash memory operations
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
to the Flash memory. It implements the erase and program Flash memory operations
and the read and write protection mechanisms.
[..] The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
prefetch and cache lines.
[..] The FLASH main features are:
(+) Flash memory read operations
@@ -28,28 +28,28 @@
(+) Prefetch on I-Code
(+) 64 cache lines of 128 bits on I-Code
(+) 8 cache lines of 128 bits on D-Code
##### How to use this driver #####
==============================================================================
[..]
This driver provides functions and macros to configure and program the FLASH
[..]
This driver provides functions and macros to configure and program the FLASH
memory of all STM32F4xx devices.
(#) FLASH Memory IO Programming functions:
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
(#) FLASH Memory IO Programming functions:
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
HAL_FLASH_Lock() functions
(++) Program functions: byte, half word, word and double word
(++) There Two modes of programming :
(+++) Polling mode using HAL_FLASH_Program() function
(+++) Interrupt mode using HAL_FLASH_Program_IT() function
(#) Interrupts and flags management functions :
(#) Interrupts and flags management functions :
(++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
(++) Wait for last FLASH operation according to its status
(++) Get error flag status by calling HAL_SetErrorCode()
(++) Get error flag status by calling HAL_SetErrorCode()
[..]
[..]
In addition to these functions, this driver includes a set of macros allowing
to handle the following operations:
(+) Set the latency
@@ -58,7 +58,7 @@
(+) Reset the Instruction cache and the Data cache
(+) Enable/Disable the FLASH interrupts
(+) Monitor the FLASH flags status
@endverbatim
******************************************************************************
* @attention
@@ -70,7 +70,7 @@
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
@@ -94,7 +94,7 @@
#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
/**
* @}
*/
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @addtogroup FLASH_Private_Variables
@@ -126,16 +126,16 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
* @{
*/
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
* @brief Programming operation functions
*
@verbatim
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
* @brief Programming operation functions
*
@verbatim
===============================================================================
##### Programming operation functions #####
===============================================================================
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the FLASH
This subsection provides a set of functions allowing to manage the FLASH
program operations.
@endverbatim
@@ -148,35 +148,35 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed
*
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
HAL_StatusTypeDef status = HAL_ERROR;
HAL_StatusTypeDef status;
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
if (status == HAL_OK)
{
if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
if (TypeProgram == FLASH_TYPEPROGRAM_BYTE)
{
/*Program byte (8-bit) at a specified address.*/
FLASH_Program_Byte(Address, (uint8_t) Data);
}
else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
else if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
/*Program halfword (16-bit) at a specified address.*/
FLASH_Program_HalfWord(Address, (uint16_t) Data);
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
else if (TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
/*Program word (32-bit) at a specified address.*/
FLASH_Program_Word(Address, (uint32_t) Data);
@@ -186,17 +186,17 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
/*Program double word (64-bit) at a specified address.*/
FLASH_Program_DoubleWord(Address, Data);
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG Bit */
FLASH->CR &= (~FLASH_CR_PG);
FLASH->CR &= (~FLASH_CR_PG);
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
return status;
}
@@ -206,39 +206,36 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed
*
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Enable End of FLASH Operation interrupt */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
/* Enable Error source interrupt */
__HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
pFlash.Address = Address;
if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
if (TypeProgram == FLASH_TYPEPROGRAM_BYTE)
{
/*Program byte (8-bit) at a specified address.*/
FLASH_Program_Byte(Address, (uint8_t) Data);
FLASH_Program_Byte(Address, (uint8_t) Data);
}
else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
else if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
/*Program halfword (16-bit) at a specified address.*/
FLASH_Program_HalfWord(Address, (uint16_t) Data);
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
else if (TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
/*Program word (32-bit) at a specified address.*/
FLASH_Program_Word(Address, (uint32_t) Data);
@@ -259,23 +256,23 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
void HAL_FLASH_IRQHandler(void)
{
uint32_t addresstmp = 0U;
/* Check FLASH operation error flags */
#if defined(FLASH_SR_RDERR)
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
#if defined(FLASH_SR_RDERR)
if (__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
#else
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
if (__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
#endif /* FLASH_SR_RDERR */
{
if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
if (pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
{
/*return the faulty sector*/
addresstmp = pFlash.Sector;
pFlash.Sector = 0xFFFFFFFFU;
}
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
{
/*return the faulty bank*/
addresstmp = pFlash.Bank;
@@ -285,35 +282,35 @@ void HAL_FLASH_IRQHandler(void)
/*return the faulty address*/
addresstmp = pFlash.Address;
}
/*Save the Error code*/
FLASH_SetErrorCode();
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(addresstmp);
/*Stop the procedure ongoing*/
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
/* Check FLASH End of Operation flag */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
if (pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
{
/*Nb of sector to erased can be decreased*/
pFlash.NbSectorsToErase--;
/* Check if there are still sectors to erase*/
if(pFlash.NbSectorsToErase != 0U)
if (pFlash.NbSectorsToErase != 0U)
{
addresstmp = pFlash.Sector;
/*Indicate user which sector has been erased*/
HAL_FLASH_EndOfOperationCallback(addresstmp);
/*Increment sector number*/
pFlash.Sector++;
addresstmp = pFlash.Sector;
@@ -325,21 +322,21 @@ void HAL_FLASH_IRQHandler(void)
/*Reset Sector and stop Erase sectors procedure*/
pFlash.Sector = addresstmp = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches() ;
FLASH_FlushCaches();
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(addresstmp);
}
}
else
else
{
if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
{
/* MassErase ended. Return the selected bank */
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches() ;
FLASH_FlushCaches();
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
@@ -353,20 +350,17 @@ void HAL_FLASH_IRQHandler(void)
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
}
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
{
/* Operation is completed, disable the PG, SER, SNB and MER Bits */
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT));
/* Disable End of FLASH Operation interrupt */
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
/* Disable Error source interrupt */
__HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
}
@@ -374,7 +368,7 @@ void HAL_FLASH_IRQHandler(void)
* @brief FLASH end of operation interrupt callback
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* Mass Erase: Bank number which has been requested to erase
* Sectors Erase: Sector which has been erased
* Sectors Erase: Sector which has been erased
* (if 0xFFFFFFFFU, it means that all the selected sectors have been erased)
* Program: Address which was selected for data program
* @retval None
@@ -385,7 +379,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
UNUSED(ReturnValue);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
*/
*/
}
/**
@@ -402,22 +396,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
UNUSED(ReturnValue);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
*/
*/
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
* @brief management functions
*
@verbatim
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
* @brief management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
===============================================================================
[..]
This subsection provides a set of functions allowing to control the FLASH
This subsection provides a set of functions allowing to control the FLASH
memory operations.
@endverbatim
@@ -432,14 +426,14 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
HAL_StatusTypeDef status = HAL_OK;
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
/* Verify Flash is unlocked */
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
{
status = HAL_ERROR;
}
@@ -456,8 +450,8 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
/* Set the LOCK Bit to lock the FLASH Registers access */
FLASH->CR |= FLASH_CR_LOCK;
return HAL_OK;
return HAL_OK;
}
/**
@@ -466,7 +460,7 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void)
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
{
if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
if ((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
{
/* Authorizes the Option Byte register programming */
FLASH->OPTKEYR = FLASH_OPT_KEY1;
@@ -475,21 +469,21 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
else
{
return HAL_ERROR;
}
return HAL_OK;
}
return HAL_OK;
}
/**
* @brief Lock the FLASH Option Control Registers access.
* @retval HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
{
/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
return HAL_OK;
return HAL_OK;
}
/**
@@ -502,20 +496,20 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
/* Wait for last operation to be completed */
return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
return (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral Errors functions
*
@verbatim
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral Errors functions
*
@verbatim
===============================================================================
##### Peripheral Errors functions #####
===============================================================================
===============================================================================
[..]
This subsection permits to get in run-time Errors of the FLASH peripheral.
@@ -527,20 +521,20 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
* @brief Get the specific FLASH error flag.
* @retval FLASH_ErrorCode: The returned value can be a combination of:
* @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
* @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
* @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
* @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
* @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
* @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
* @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
* @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
* @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
*/
uint32_t HAL_FLASH_GetError(void)
{
return pFlash.ErrorCode;
}
{
return pFlash.ErrorCode;
}
/**
* @}
*/
*/
/**
* @brief Wait for a FLASH operation to complete.
@@ -548,27 +542,27 @@ uint32_t HAL_FLASH_GetError(void)
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
{
uint32_t tickstart = 0U;
/* Clear Error Code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
/* Get tick */
tickstart = HAL_GetTick();
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
{
if(Timeout != HAL_MAX_DELAY)
while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
{
if (Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
return HAL_TIMEOUT;
}
}
}
}
/* Check FLASH End of Operation flag */
@@ -577,12 +571,12 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
#if defined(FLASH_SR_RDERR)
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
#if defined(FLASH_SR_RDERR)
if (__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
#else
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
if (__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
#endif /* FLASH_SR_RDERR */
{
/*Save the error code*/
@@ -592,17 +586,17 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
/* If there is no error flag set */
return HAL_OK;
}
}
/**
* @brief Program a double word (64-bit) at a specified address.
* @note This function must be used when the device voltage range is from
* 2.7V to 3.6V and Vpp in the range 7V to 9V.
*
* @note If an erase and a program operations are requested simultaneously,
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
*
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed.
* @retval None
@@ -611,21 +605,21 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
{
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
FLASH->CR |= FLASH_CR_PG;
/* Program first word */
*(__IO uint32_t*)Address = (uint32_t)Data;
*(__IO uint32_t *)Address = (uint32_t)Data;
/* Barrier to ensure programming is performed in 2 steps, in right order
(independently of compiler optimization behavior) */
__ISB();
/* Program second word */
*(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
*(__IO uint32_t *)(Address + 4) = (uint32_t)(Data >> 32);
}
@@ -634,9 +628,9 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
* @note This function must be used when the device voltage range is from
* 2.7V to 3.6V.
*
* @note If an erase and a program operations are requested simultaneously,
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
*
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed.
* @retval None
@@ -645,13 +639,13 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
{
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= FLASH_PSIZE_WORD;
FLASH->CR |= FLASH_CR_PG;
*(__IO uint32_t*)Address = Data;
*(__IO uint32_t *)Address = Data;
}
/**
@@ -659,9 +653,9 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
* @note This function must be used when the device voltage range is from
* 2.1V to 3.6V.
*
* @note If an erase and a program operations are requested simultaneously,
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
*
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed.
* @retval None
@@ -670,13 +664,13 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
{
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= FLASH_PSIZE_HALF_WORD;
FLASH->CR |= FLASH_CR_PG;
*(__IO uint16_t*)Address = Data;
*(__IO uint16_t *)Address = Data;
}
/**
@@ -684,9 +678,9 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
* @note This function must be used when the device voltage range is from
* 1.8V to 3.6V.
*
* @note If an erase and a program operations are requested simultaneously,
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
*
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed.
* @retval None
@@ -695,13 +689,13 @@ static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
{
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= FLASH_PSIZE_BYTE;
FLASH->CR |= FLASH_CR_PG;
*(__IO uint8_t*)Address = Data;
*(__IO uint8_t *)Address = Data;
}
/**
@@ -709,51 +703,51 @@ static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
* @retval None
*/
static void FLASH_SetErrorCode(void)
{
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
{
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
/* Clear FLASH write protection error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR);
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
/* Clear FLASH write protection error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
/* Clear FLASH Programming alignment error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR);
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
/* Clear FLASH Programming alignment error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
/* Clear FLASH Programming parallelism error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
/* Clear FLASH Programming sequence error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR);
}
#if defined(FLASH_SR_RDERR)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
#if defined(FLASH_SR_RDERR)
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
/* Clear FLASH Proprietary readout protection error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR);
}
#endif /* FLASH_SR_RDERR */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
#endif /* FLASH_SR_RDERR */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
/* Clear FLASH Operation error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR);
}

15
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c
View File

@@ -133,8 +133,8 @@ extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
*/
/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
* @brief Extended IO operation functions
*
* @brief Extended IO operation functions
*
@verbatim
===============================================================================
##### Extended programming operation functions #####
@@ -159,7 +159,7 @@ extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
{
HAL_StatusTypeDef status = HAL_ERROR;
HAL_StatusTypeDef status;
uint32_t index = 0U;
/* Process Locked */
@@ -232,9 +232,6 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Check the parameters */
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
@@ -459,7 +456,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
*/
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
{
uint8_t optiontmp = 0xFF;
uint8_t optiontmp;
/* Mask SPRMOD bit */
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
@@ -484,7 +481,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
*/
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
{
uint8_t optiontmp = 0xFF;
uint8_t optiontmp;
/* Mask SPRMOD bit */
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
@@ -1193,7 +1190,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
*/
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
{
uint8_t optiontmp = 0xFF;
uint8_t optiontmp;
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */

54
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c
View File

@@ -3,7 +3,7 @@
* @file stm32f4xx_hal_flash_ramfunc.c
* @author MCD Application Team
* @brief FLASH RAMFUNC module driver.
* This file provides a FLASH firmware functions which should be
* This file provides a FLASH firmware functions which should be
* executed from internal SRAM
* + Stop/Start the flash interface while System Run
* + Enable/Disable the flash sleep while System Run
@@ -14,11 +14,11 @@
[..]
*** ARM Compiler ***
--------------------
[..] RAM functions are defined using the toolchain options.
[..] RAM functions are defined using the toolchain options.
Functions that are be executed in RAM should reside in a separate
source module. Using the 'Options for File' dialog you can simply change
the 'Code / Const' area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the
Available memory areas are declared in the 'Target' tab of the
Options for Target' dialog.
*** ICCARM Compiler ***
@@ -29,8 +29,8 @@
--------------------
[..] RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
@endverbatim
@endverbatim
******************************************************************************
* @attention
*
@@ -41,7 +41,7 @@
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
@@ -68,44 +68,44 @@
* @{
*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM
* @brief Peripheral Extended features functions
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM
* @brief Peripheral Extended features functions
*
@verbatim
@verbatim
===============================================================================
##### ramfunc functions #####
===============================================================================
===============================================================================
[..]
This subsection provides a set of functions that should be executed from RAM
This subsection provides a set of functions that should be executed from RAM
transfers.
@endverbatim
* @{
*/
/**
* @brief Stop the flash interface while System Run
* @note This mode is only available for STM32F41xxx/STM32F446xx devices.
* @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @note This mode is only available for STM32F41xxx/STM32F446xx devices.
* @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void)
{
/* Enable Power ctrl clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* Stop the flash interface while System Run */
/* Stop the flash interface while System Run */
SET_BIT(PWR->CR, PWR_CR_FISSR);
return HAL_OK;
}
/**
* @brief Start the flash interface while System Run
* @note This mode is only available for STM32F411xx/STM32F446xx devices.
* @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @note This mode is only available for STM32F411xx/STM32F446xx devices.
* @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void)
@@ -120,9 +120,9 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void)
/**
* @brief Enable the flash sleep while System Run
* @note This mode is only available for STM32F41xxx/STM32F446xx devices.
* @note This mode could n't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @note This mode is only available for STM32F41xxx/STM32F446xx devices.
* @note This mode could n't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void)
@@ -137,9 +137,9 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void)
/**
* @brief Disable the flash sleep while System Run
* @note This mode is only available for STM32F41xxx/STM32F446xx devices.
* @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @note This mode is only available for STM32F41xxx/STM32F446xx devices.
* @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void)
@@ -148,7 +148,7 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void)
__HAL_RCC_PWR_CLK_ENABLE();
/* Disable the flash sleep while System Run */
CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
return HAL_OK;
}

1545
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c
View File

@@ -357,28 +357,28 @@
/* Private define for @ref PreviousState usage */
#define FMPI2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_FMPI2C_STATE_BUSY_TX | \
(uint32_t)HAL_FMPI2C_STATE_BUSY_RX) & \
(uint32_t)(~((uint32_t)HAL_FMPI2C_STATE_READY))))
(uint32_t)HAL_FMPI2C_STATE_BUSY_RX) & \
(uint32_t)(~((uint32_t)HAL_FMPI2C_STATE_READY))))
/*!< Mask State define, keep only RX and TX bits */
#define FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE))
/*!< Default Value */
#define FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \
(uint32_t)HAL_FMPI2C_MODE_MASTER))
(uint32_t)HAL_FMPI2C_MODE_MASTER))
/*!< Master Busy TX, combinaison of State LSB and Mode enum */
#define FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \
(uint32_t)HAL_FMPI2C_MODE_MASTER))
(uint32_t)HAL_FMPI2C_MODE_MASTER))
/*!< Master Busy RX, combinaison of State LSB and Mode enum */
#define FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \
(uint32_t)HAL_FMPI2C_MODE_SLAVE))
(uint32_t)HAL_FMPI2C_MODE_SLAVE))
/*!< Slave Busy TX, combinaison of State LSB and Mode enum */
#define FMPI2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \
(uint32_t)HAL_FMPI2C_MODE_SLAVE))
(uint32_t)HAL_FMPI2C_MODE_SLAVE))
/*!< Slave Busy RX, combinaison of State LSB and Mode enum */
#define FMPI2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \
(uint32_t)HAL_FMPI2C_MODE_MEM))
(uint32_t)HAL_FMPI2C_MODE_MEM))
/*!< Memory Busy TX, combinaison of State LSB and Mode enum */
#define FMPI2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \
(uint32_t)HAL_FMPI2C_MODE_MEM))
(uint32_t)HAL_FMPI2C_MODE_MEM))
/*!< Memory Busy RX, combinaison of State LSB and Mode enum */
@@ -401,7 +401,16 @@
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup FMPI2C_Private_Macro
* @{
*/
/* Macro to get remaining data to transfer on DMA side */
#define FMPI2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -416,6 +425,7 @@ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma);
static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma);
/* Private functions to handle IT transfer */
static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
static void FMPI2C_ITMasterSeqCplt(FMPI2C_HandleTypeDef *hfmpi2c);
@@ -427,33 +437,37 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode);
/* Private functions to handle IT transfer */
static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress,
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart);
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart);
static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress,
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart);
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart);
/* Private functions for FMPI2C transfer IRQ handler */
static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef FMPI2C_Mem_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags,
uint32_t ITSources);
uint32_t ITSources);
static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef FMPI2C_Mem_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags,
uint32_t ITSources);
uint32_t ITSources);
/* Private functions to handle flags during polling transfer */
static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart);
uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout,
uint32_t Tickstart);
uint32_t Tickstart);
static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout,
uint32_t Tickstart);
uint32_t Tickstart);
static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout,
uint32_t Tickstart);
uint32_t Tickstart);
static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout,
uint32_t Tickstart);
uint32_t Tickstart);
/* Private functions to centralize the enable/disable of Interrupts */
static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
@@ -467,7 +481,7 @@ static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c);
/* Private function to handle start, restart or stop a transfer */
static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
uint32_t Request);
uint32_t Request);
/* Private function to Convert Specific options */
static void FMPI2C_ConvertOtherXferOptions(FMPI2C_HandleTypeDef *hfmpi2c);
@@ -595,7 +609,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c)
/* Configure FMPI2Cx: Addressing Master mode */
if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
{
hfmpi2c->Instance->CR2 = (FMPI2C_CR2_ADD10);
SET_BIT(hfmpi2c->Instance->CR2, FMPI2C_CR2_ADD10);
}
else
{
/* Clear the FMPI2C ADD10 bit */
CLEAR_BIT(hfmpi2c->Instance->CR2, FMPI2C_CR2_ADD10);
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hfmpi2c->Instance->CR2 |= (FMPI2C_CR2_AUTOEND | FMPI2C_CR2_NACK);
@@ -606,7 +625,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c)
/* Configure FMPI2Cx: Dual mode and Own Address2 */
hfmpi2c->Instance->OAR2 = (hfmpi2c->Init.DualAddressMode | hfmpi2c->Init.OwnAddress2 | \
(hfmpi2c->Init.OwnAddress2Masks << 8));
(hfmpi2c->Init.OwnAddress2Masks << 8));
/*---------------------------- FMPI2Cx CR1 Configuration ----------------------*/
/* Configure FMPI2Cx: Generalcall and NoStretch mode */
@@ -705,6 +724,8 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c)
/**
* @brief Register a User FMPI2C Callback
* To be used instead of the weak predefined callback
* @note The HAL_FMPI2C_RegisterCallback() may be called before HAL_FMPI2C_Init() in HAL_FMPI2C_STATE_RESET
* to register callbacks for HAL_FMPI2C_MSPINIT_CB_ID and HAL_FMPI2C_MSPDEINIT_CB_ID.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
* @param CallbackID ID of the callback to be registered
@@ -724,7 +745,7 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID,
pFMPI2C_CallbackTypeDef pCallback)
pFMPI2C_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -735,8 +756,6 @@ HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hfmpi2c);
if (HAL_FMPI2C_STATE_READY == hfmpi2c->State)
{
@@ -825,14 +844,14 @@ HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hfmpi2c);
return status;
}
/**
* @brief Unregister an FMPI2C Callback
* FMPI2C callback is redirected to the weak predefined callback
* @note The HAL_FMPI2C_UnRegisterCallback() may be called before HAL_FMPI2C_Init() in HAL_FMPI2C_STATE_RESET
* to un-register callbacks for HAL_FMPI2C_MSPINIT_CB_ID and HAL_FMPI2C_MSPDEINIT_CB_ID.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
* @param CallbackID ID of the callback to be unregistered
@@ -855,9 +874,6 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, H
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hfmpi2c);
if (HAL_FMPI2C_STATE_READY == hfmpi2c->State)
{
switch (CallbackID)
@@ -945,8 +961,6 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, H
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hfmpi2c);
return status;
}
@@ -969,8 +983,6 @@ HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c,
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hfmpi2c);
if (HAL_FMPI2C_STATE_READY == hfmpi2c->State)
{
@@ -985,8 +997,6 @@ HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c,
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hfmpi2c);
return status;
}
@@ -1001,9 +1011,6 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hfmpi2c);
if (HAL_FMPI2C_STATE_READY == hfmpi2c->State)
{
hfmpi2c->AddrCallback = HAL_FMPI2C_AddrCallback; /* Legacy weak AddrCallback */
@@ -1017,8 +1024,6 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hfmpi2c);
return status;
}
@@ -1113,9 +1118,10 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout)
uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t xfermode;
if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
@@ -1139,19 +1145,40 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint
hfmpi2c->XferCount = Size;
hfmpi2c->XferISR = NULL;
/* Send Slave Address */
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE,
FMPI2C_GENERATE_START_WRITE);
xfermode = FMPI2C_RELOAD_MODE;
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE,
FMPI2C_GENERATE_START_WRITE);
xfermode = FMPI2C_AUTOEND_MODE;
}
if (hfmpi2c->XferSize > 0U)
{
/* Preload TX register */
/* Write data to TXDR */
hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
/* Increment Buffer pointer */
hfmpi2c->pBuffPtr++;
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
/* Send Slave Address */
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)(hfmpi2c->XferSize + 1U), xfermode,
FMPI2C_GENERATE_START_WRITE);
}
else
{
/* Send Slave Address */
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode,
FMPI2C_GENERATE_START_WRITE);
}
while (hfmpi2c->XferCount > 0U)
@@ -1182,13 +1209,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE,
FMPI2C_NO_STARTSTOP);
FMPI2C_NO_STARTSTOP);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE,
FMPI2C_NO_STARTSTOP);
FMPI2C_NO_STARTSTOP);
}
}
}
@@ -1232,7 +1259,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout)
uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
@@ -1262,15 +1289,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
hfmpi2c->XferSize = 1U;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE,
FMPI2C_GENERATE_START_READ);
FMPI2C_GENERATE_START_READ);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE,
FMPI2C_GENERATE_START_READ);
FMPI2C_GENERATE_START_READ);
}
while (hfmpi2c->XferCount > 0U)
@@ -1302,13 +1329,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE,
FMPI2C_NO_STARTSTOP);
FMPI2C_NO_STARTSTOP);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE,
FMPI2C_NO_STARTSTOP);
FMPI2C_NO_STARTSTOP);
}
}
}
@@ -1350,9 +1377,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout)
uint32_t Timeout)
{
uint32_t tickstart;
uint16_t tmpXferCount;
HAL_StatusTypeDef error;
if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
@@ -1387,6 +1416,19 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
return HAL_ERROR;
}
/* Preload TX data if no stretch enable */
if (hfmpi2c->Init.NoStretchMode == FMPI2C_NOSTRETCH_ENABLE)
{
/* Preload TX register */
/* Write data to TXDR */
hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
/* Increment Buffer pointer */
hfmpi2c->pBuffPtr++;
hfmpi2c->XferCount--;
}
/* Clear ADDR flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
@@ -1432,26 +1474,48 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
hfmpi2c->XferCount--;
}
/* Wait until STOP flag is set */
if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
/* Wait until AF flag is set */
error = FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_AF, RESET, Timeout, tickstart);
if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
if (error != HAL_OK)
{
/* Check that FMPI2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0 */
tmpXferCount = hfmpi2c->XferCount;
if ((hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) && (tmpXferCount == 0U))
{
/* Normal use case for Transmitter mode */
/* A NACK is generated to confirm the end of transfer */
/* Reset ErrorCode to NONE */
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
}
else
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
return HAL_ERROR;
}
}
else
{
/* Flush TX register */
FMPI2C_Flush_TXDR(hfmpi2c);
/* Clear STOP flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
/* Clear AF flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
/* Wait until STOP flag is set */
if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
return HAL_ERROR;
}
/* Clear STOP flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
}
/* Wait until BUSY flag is reset */
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
@@ -1488,7 +1552,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout)
uint32_t Timeout)
{
uint32_t tickstart;
@@ -1512,6 +1576,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
/* Prepare transfer parameters */
hfmpi2c->pBuffPtr = pData;
hfmpi2c->XferCount = Size;
hfmpi2c->XferSize = hfmpi2c->XferCount;
hfmpi2c->XferISR = NULL;
/* Enable Address Acknowledge */
@@ -1554,6 +1619,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
hfmpi2c->pBuffPtr++;
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
}
return HAL_ERROR;
@@ -1566,6 +1632,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
hfmpi2c->pBuffPtr++;
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
}
/* Wait until STOP flag is set */
@@ -1615,7 +1682,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size)
uint16_t Size)
{
uint32_t xfermode;
@@ -1652,7 +1719,26 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u
/* Send Slave Address */
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE);
if (hfmpi2c->XferSize > 0U)
{
/* Preload TX register */
/* Write data to TXDR */
hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
/* Increment Buffer pointer */
hfmpi2c->pBuffPtr++;
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)(hfmpi2c->XferSize + 1U), xfermode,
FMPI2C_GENERATE_START_WRITE);
}
else
{
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode,
FMPI2C_GENERATE_START_WRITE);
}
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -1686,7 +1772,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size)
uint16_t Size)
{
uint32_t xfermode;
@@ -1712,7 +1798,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
hfmpi2c->XferSize = 1U;
xfermode = FMPI2C_RELOAD_MODE;
}
else
@@ -1775,6 +1861,20 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
/* Preload TX data if no stretch enable */
if (hfmpi2c->Init.NoStretchMode == FMPI2C_NOSTRETCH_ENABLE)
{
/* Preload TX register */
/* Write data to TXDR */
hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
/* Increment Buffer pointer */
hfmpi2c->pBuffPtr++;
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
}
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -1857,10 +1957,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uin
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size)
uint16_t Size)
{
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
uint32_t sizetoxfer = 0U;
if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
@@ -1893,6 +1994,20 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c,
xfermode = FMPI2C_AUTOEND_MODE;
}
if (hfmpi2c->XferSize > 0U)
{
/* Preload TX register */
/* Write data to TXDR */
hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
/* Increment Buffer pointer */
hfmpi2c->pBuffPtr++;
sizetoxfer = hfmpi2c->XferSize;
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
}
if (hfmpi2c->XferSize > 0U)
{
if (hfmpi2c->hdmatx != NULL)
@@ -1908,8 +2023,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c,
hfmpi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA stream */
dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR,
hfmpi2c->XferSize);
dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr,
(uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
}
else
{
@@ -1930,7 +2045,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c,
{
/* Send Slave Address */
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE);
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)(hfmpi2c->XferSize + 1U),
xfermode, FMPI2C_GENERATE_START_WRITE);
/* Update XferCount value */
hfmpi2c->XferCount -= hfmpi2c->XferSize;
@@ -1969,8 +2085,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c,
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE,
FMPI2C_GENERATE_START_WRITE);
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, FMPI2C_AUTOEND_MODE,
FMPI2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -2004,7 +2120,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c,
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size)
uint16_t Size)
{
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
@@ -2031,7 +2147,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
hfmpi2c->XferSize = 1U;
xfermode = FMPI2C_RELOAD_MODE;
}
else
@@ -2117,7 +2233,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
/* Send Slave Address */
/* Set NBYTES to read and generate START condition */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE,
FMPI2C_GENERATE_START_READ);
FMPI2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -2125,11 +2241,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
/* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI |
FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
}
return HAL_OK;
@@ -2173,38 +2289,87 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Slave_ISR_DMA;
if (hfmpi2c->hdmatx != NULL)
/* Preload TX data if no stretch enable */
if (hfmpi2c->Init.NoStretchMode == FMPI2C_NOSTRETCH_ENABLE)
{
/* Set the FMPI2C DMA transfer complete callback */
hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMASlaveTransmitCplt;
/* Preload TX register */
/* Write data to TXDR */
hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
/* Set the DMA error callback */
hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
/* Increment Buffer pointer */
hfmpi2c->pBuffPtr++;
/* Set the unused DMA callbacks to NULL */
hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
hfmpi2c->hdmatx->XferAbortCallback = NULL;
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
}
/* Enable the DMA stream */
dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR,
hfmpi2c->XferSize);
if (hfmpi2c->XferCount != 0U)
{
if (hfmpi2c->hdmatx != NULL)
{
/* Set the FMPI2C DMA transfer complete callback */
hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMASlaveTransmitCplt;
/* Set the DMA error callback */
hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
/* Set the unused DMA callbacks to NULL */
hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
hfmpi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA stream */
dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx,
(uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR,
hfmpi2c->XferSize);
}
else
{
/* Update FMPI2C state */
hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Update FMPI2C error code */
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
{
/* Enable Address Acknowledge */
hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
process unlock */
/* Enable ERR, STOP, NACK, ADDR interrupts */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
/* Enable DMA Request */
hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
}
else
{
/* Update FMPI2C state */
hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Update FMPI2C error code */
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_ERROR;
}
}
else
{
/* Update FMPI2C state */
hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Update FMPI2C error code */
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
{
/* Enable Address Acknowledge */
hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
@@ -2213,27 +2378,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
__HAL_UNLOCK(hfmpi2c);
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
process unlock */
to avoid the risk of FMPI2C interrupt handle execution before current
process unlock */
/* Enable ERR, STOP, NACK, ADDR interrupts */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
/* Enable DMA Request */
hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
}
else
{
/* Update FMPI2C state */
hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Update FMPI2C error code */
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_ERROR;
}
return HAL_OK;
@@ -2347,6 +2495,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui
return HAL_BUSY;
}
}
/**
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
@@ -2361,7 +2510,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
@@ -2445,13 +2594,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE,
FMPI2C_NO_STARTSTOP);
FMPI2C_NO_STARTSTOP);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE,
FMPI2C_NO_STARTSTOP);
FMPI2C_NO_STARTSTOP);
}
}
@@ -2498,7 +2647,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
@@ -2545,15 +2694,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
hfmpi2c->XferSize = 1U;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE,
FMPI2C_GENERATE_START_READ);
FMPI2C_GENERATE_START_READ);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE,
FMPI2C_GENERATE_START_READ);
FMPI2C_GENERATE_START_READ);
}
do
@@ -2583,15 +2732,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
hfmpi2c->XferSize = 1U;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t) hfmpi2c->XferSize, FMPI2C_RELOAD_MODE,
FMPI2C_NO_STARTSTOP);
FMPI2C_NO_STARTSTOP);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE,
FMPI2C_NO_STARTSTOP);
FMPI2C_NO_STARTSTOP);
}
}
} while (hfmpi2c->XferCount > 0U);
@@ -2635,11 +2784,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
/* Check the parameters */
assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
@@ -2659,41 +2805,38 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
/* Process Locked */
__HAL_LOCK(hfmpi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
/* Prepare transfer parameters */
hfmpi2c->XferSize = 0U;
hfmpi2c->pBuffPtr = pData;
hfmpi2c->XferCount = Size;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
hfmpi2c->XferISR = FMPI2C_Mem_ISR_IT;
hfmpi2c->Devaddress = DevAddress;
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
/* If Memory address size is 8Bit */
if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
/* Prefetch Memory Address */
hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
/* Reset Memaddress content */
hfmpi2c->Memaddress = 0xFFFFFFFFU;
}
/* If Memory address size is 16Bit */
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
xfermode = FMPI2C_AUTOEND_MODE;
}
/* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress);
/* Prepare Memaddress buffer for LSB part */
hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress);
}
/* Send Slave Address and Memory Address */
if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart)
!= HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_ERROR;
}
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -2729,11 +2872,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
/* Check the parameters */
assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
@@ -2753,9 +2893,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t
/* Process Locked */
__HAL_LOCK(hfmpi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
@@ -2764,29 +2901,29 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t
hfmpi2c->pBuffPtr = pData;
hfmpi2c->XferCount = Size;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
hfmpi2c->XferISR = FMPI2C_Mem_ISR_IT;
hfmpi2c->Devaddress = DevAddress;
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
/* If Memory address size is 8Bit */
if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
/* Prefetch Memory Address */
hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
/* Reset Memaddress content */
hfmpi2c->Memaddress = 0xFFFFFFFFU;
}
/* If Memory address size is 16Bit */
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
xfermode = FMPI2C_AUTOEND_MODE;
}
/* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress);
/* Prepare Memaddress buffer for LSB part */
hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress);
}
/* Send Slave Address and Memory Address */
if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_ERROR;
}
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -2795,11 +2932,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t
to avoid the risk of FMPI2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI |
FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
return HAL_OK;
}
@@ -2808,6 +2945,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t
return HAL_BUSY;
}
}
/**
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
@@ -2821,10 +2959,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -2846,9 +2982,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16
/* Process Locked */
__HAL_LOCK(hfmpi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
@@ -2857,28 +2990,36 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16
hfmpi2c->pBuffPtr = pData;
hfmpi2c->XferCount = Size;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA;
hfmpi2c->XferISR = FMPI2C_Mem_ISR_DMA;
hfmpi2c->Devaddress = DevAddress;
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
xfermode = FMPI2C_AUTOEND_MODE;
}
/* Send Slave Address and Memory Address */
if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart)
!= HAL_OK)
/* If Memory address size is 8Bit */
if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
{
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_ERROR;
}
/* Prefetch Memory Address */
hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
/* Reset Memaddress content */
hfmpi2c->Memaddress = 0xFFFFFFFFU;
}
/* If Memory address size is 16Bit */
else
{
/* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress);
/* Prepare Memaddress buffer for LSB part */
hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress);
}
if (hfmpi2c->hdmatx != NULL)
{
@@ -2913,12 +3054,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16
if (dmaxferstatus == HAL_OK)
{
/* Send Slave Address */
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
/* Update XferCount value */
hfmpi2c->XferCount -= hfmpi2c->XferSize;
/* Send Slave Address and Memory Address */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -2926,11 +3063,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
process unlock */
/* Enable ERR and NACK interrupts */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
/* Enable DMA Request */
hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI |
FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
}
else
{
@@ -2968,10 +3105,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -2993,9 +3128,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
/* Process Locked */
__HAL_LOCK(hfmpi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
@@ -3004,25 +3136,35 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
hfmpi2c->pBuffPtr = pData;
hfmpi2c->XferCount = Size;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA;
hfmpi2c->XferISR = FMPI2C_Mem_ISR_DMA;
hfmpi2c->Devaddress = DevAddress;
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
xfermode = FMPI2C_AUTOEND_MODE;
}
/* Send Slave Address and Memory Address */
if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
/* If Memory address size is 8Bit */
if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
{
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_ERROR;
/* Prefetch Memory Address */
hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
/* Reset Memaddress content */
hfmpi2c->Memaddress = 0xFFFFFFFFU;
}
/* If Memory address size is 16Bit */
else
{
/* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress);
/* Prepare Memaddress buffer for LSB part */
hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress);
}
if (hfmpi2c->hdmarx != NULL)
@@ -3058,11 +3200,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
if (dmaxferstatus == HAL_OK)
{
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
/* Update XferCount value */
hfmpi2c->XferCount -= hfmpi2c->XferSize;
/* Send Slave Address and Memory Address */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -3070,11 +3209,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
process unlock */
/* Enable ERR and NACK interrupts */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
/* Enable DMA Request */
hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI |
FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
}
else
{
@@ -3111,7 +3250,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout)
uint32_t Timeout)
{
uint32_t tickstart;
@@ -3203,22 +3342,6 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
}
/* Check if the maximum allowed number of trials has been reached */
if (FMPI2C_Trials == Trials)
{
/* Generate Stop */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
/* Wait until STOPF flag is reset */
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
}
/* Increment Trials */
FMPI2C_Trials++;
} while (FMPI2C_Trials < Trials);
@@ -3253,10 +3376,11 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions)
uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = FMPI2C_GENERATE_START_WRITE;
uint32_t sizetoxfer = 0U;
/* Check the parameters */
assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3288,6 +3412,21 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2
xfermode = hfmpi2c->XferOptions;
}
if ((hfmpi2c->XferSize > 0U) && ((XferOptions == FMPI2C_FIRST_FRAME) || \
(XferOptions == FMPI2C_FIRST_AND_LAST_FRAME)))
{
/* Preload TX register */
/* Write data to TXDR */
hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
/* Increment Buffer pointer */
hfmpi2c->pBuffPtr++;
sizetoxfer = hfmpi2c->XferSize;
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
}
/* If transfer direction not change and there is no request to start another frame,
do not generate Restart Condition */
/* Mean Previous state is same as current state */
@@ -3309,7 +3448,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2
}
/* Send Slave Address and set NBYTES to write */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest);
if ((XferOptions == FMPI2C_FIRST_FRAME) || (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME))
{
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
}
else
{
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest);
}
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -3317,6 +3463,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI |
FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
return HAL_OK;
@@ -3340,11 +3490,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions)
uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = FMPI2C_GENERATE_START_WRITE;
HAL_StatusTypeDef dmaxferstatus;
uint32_t sizetoxfer = 0U;
/* Check the parameters */
assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3376,6 +3527,21 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi
xfermode = hfmpi2c->XferOptions;
}
if ((hfmpi2c->XferSize > 0U) && ((XferOptions == FMPI2C_FIRST_FRAME) || \
(XferOptions == FMPI2C_FIRST_AND_LAST_FRAME)))
{
/* Preload TX register */
/* Write data to TXDR */
hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
/* Increment Buffer pointer */
hfmpi2c->pBuffPtr++;
sizetoxfer = hfmpi2c->XferSize;
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
}
/* If transfer direction not change and there is no request to start another frame,
do not generate Restart Condition */
/* Mean Previous state is same as current state */
@@ -3411,8 +3577,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi
hfmpi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA stream */
dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR,
hfmpi2c->XferSize);
dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr,
(uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
}
else
{
@@ -3432,7 +3598,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi
if (dmaxferstatus == HAL_OK)
{
/* Send Slave Address and set NBYTES to write */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest);
if ((XferOptions == FMPI2C_FIRST_FRAME) || (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME))
{
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
}
else
{
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest);
}
/* Update XferCount value */
hfmpi2c->XferCount -= hfmpi2c->XferSize;
@@ -3471,8 +3644,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE,
FMPI2C_GENERATE_START_WRITE);
if ((XferOptions == FMPI2C_FIRST_FRAME) || (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME))
{
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
}
else
{
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest);
}
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -3508,7 +3687,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions)
uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = FMPI2C_GENERATE_START_READ;
@@ -3595,7 +3774,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions)
uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = FMPI2C_GENERATE_START_READ;
@@ -3727,7 +3906,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2
/* Send Slave Address */
/* Set NBYTES to read and generate START condition */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE,
FMPI2C_GENERATE_START_READ);
FMPI2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -3735,11 +3914,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
/* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI |
FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
}
return HAL_OK;
@@ -3761,8 +3940,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
uint32_t XferOptions)
{
/* Declaration of tmp to prevent undefined behavior of volatile usage */
FlagStatus tmp;
/* Check the parameters */
assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3822,7 +4004,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c
hfmpi2c->XferOptions = XferOptions;
hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -3857,8 +4040,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
uint32_t XferOptions)
{
/* Declaration of tmp to prevent undefined behavior of volatile usage */
FlagStatus tmp;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -3893,7 +4078,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2
hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
/* Set the FMPI2C DMA Abort callback :
will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
hfmpi2c->hdmarx->XferAbortCallback = FMPI2C_DMAAbort;
/* Abort DMA RX */
@@ -3915,7 +4100,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2
if (hfmpi2c->hdmatx != NULL)
{
/* Set the FMPI2C DMA Abort callback :
will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
hfmpi2c->hdmatx->XferAbortCallback = FMPI2C_DMAAbort;
/* Abort DMA TX */
@@ -4000,7 +4185,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2
return HAL_ERROR;
}
if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4010,15 +4196,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
/* Enable DMA Request */
hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
process unlock */
/* Enable ERR, STOP, NACK, ADDR interrupts */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
/* Enable DMA Request */
hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
return HAL_OK;
}
else
@@ -4038,8 +4224,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
uint32_t XferOptions)
{
/* Declaration of tmp to prevent undefined behavior of volatile usage */
FlagStatus tmp;
/* Check the parameters */
assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -4099,7 +4288,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c,
hfmpi2c->XferOptions = XferOptions;
hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT)
tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4134,8 +4324,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c,
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
uint32_t XferOptions)
{
/* Declaration of tmp to prevent undefined behavior of volatile usage */
FlagStatus tmp;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -4277,7 +4469,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c
return HAL_ERROR;
}
if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT)
tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4287,15 +4480,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
/* Enable DMA Request */
hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
process unlock */
/* REnable ADDR interrupt */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_LISTEN_IT);
/* Enable DMA Request */
hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
return HAL_OK;
}
else
@@ -4429,7 +4622,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint
* the configuration information for the specified FMPI2C.
* @retval None
*/
void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Get current IT Flags and IT sources value */
uint32_t itflags = READ_REG(hfmpi2c->Instance->ISR);
@@ -4682,7 +4875,7 @@ __weak void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
* the configuration information for the specified FMPI2C.
* @retval HAL state
*/
HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c)
HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(const FMPI2C_HandleTypeDef *hfmpi2c)
{
/* Return FMPI2C handle state */
return hfmpi2c->State;
@@ -4694,7 +4887,7 @@ HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c)
* the configuration information for FMPI2C module
* @retval HAL mode
*/
HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c)
HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(const FMPI2C_HandleTypeDef *hfmpi2c)
{
return hfmpi2c->Mode;
}
@@ -4705,7 +4898,7 @@ HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c)
* the configuration information for the specified FMPI2C.
* @retval FMPI2C Error Code
*/
uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c)
uint32_t HAL_FMPI2C_GetError(const FMPI2C_HandleTypeDef *hfmpi2c)
{
return hfmpi2c->ErrorCode;
}
@@ -4731,7 +4924,7 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c)
* @retval HAL status
*/
static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags,
uint32_t ITSources)
uint32_t ITSources)
{
uint16_t devaddress;
uint32_t tmpITFlags = ITFlags;
@@ -4768,17 +4961,22 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
}
else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET))
else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TC) == RESET) && \
((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)))
{
/* Write data to TXDR */
hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
if (hfmpi2c->XferCount != 0U)
{
/* Write data to TXDR */
hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
/* Increment Buffer pointer */
hfmpi2c->pBuffPtr++;
/* Increment Buffer pointer */
hfmpi2c->pBuffPtr++;
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
}
}
else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TCR) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET))
@@ -4789,7 +4987,15 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
/* Errata workaround 170323 */
if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
{
hfmpi2c->XferSize = 1U;
}
else
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
}
FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
}
else
@@ -4798,12 +5004,12 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm
if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
{
FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize,
hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP);
hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP);
}
else
{
FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize,
FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
}
}
}
@@ -4868,6 +5074,165 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm
return HAL_OK;
}
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
* @param ITFlags Interrupt flags to handle.
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef FMPI2C_Mem_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags,
uint32_t ITSources)
{
uint32_t direction = FMPI2C_GENERATE_START_WRITE;
uint32_t tmpITFlags = ITFlags;
/* Process Locked */
__HAL_LOCK(hfmpi2c);
if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
/* Set corresponding Error Code */
/* No need to generate STOP, it is automatically done */
/* Error callback will be send during stop flag treatment */
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
/* Flush TX register */
FMPI2C_Flush_TXDR(hfmpi2c);
}
else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_RXI) != RESET))
{
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~FMPI2C_FLAG_RXNE;
/* Read data from RXDR */
*hfmpi2c->pBuffPtr = (uint8_t)hfmpi2c->Instance->RXDR;
/* Increment Buffer pointer */
hfmpi2c->pBuffPtr++;
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
}
else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET))
{
if (hfmpi2c->Memaddress == 0xFFFFFFFFU)
{
/* Write data to TXDR */
hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
/* Increment Buffer pointer */
hfmpi2c->pBuffPtr++;
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
}
else
{
/* Write LSB part of Memory Address */
hfmpi2c->Instance->TXDR = hfmpi2c->Memaddress;
/* Reset Memaddress content */
hfmpi2c->Memaddress = 0xFFFFFFFFU;
}
}
else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TCR) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET))
{
if ((hfmpi2c->XferCount != 0U) && (hfmpi2c->XferSize == 0U))
{
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
/* Errata workaround 170323 */
if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
{
hfmpi2c->XferSize = 1U;
}
else
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
}
FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize,
FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize,
FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
}
}
else
{
/* Wrong size Status regarding TCR flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE);
}
}
else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TC) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET))
{
/* Disable Interrupt related to address step */
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
{
direction = FMPI2C_GENERATE_START_READ;
}
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
/* Errata workaround 170323 */
if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
{
hfmpi2c->XferSize = 1U;
}
else
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
}
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize,
FMPI2C_RELOAD_MODE, direction);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
/* Set NBYTES to write and generate RESTART */
FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize,
FMPI2C_AUTOEND_MODE, direction);
}
}
else
{
/* Nothing to do */
}
if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET))
{
/* Call FMPI2C Master complete process */
FMPI2C_ITMasterCplt(hfmpi2c, tmpITFlags);
}
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_OK;
}
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
@@ -4877,7 +5242,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm
* @retval HAL status
*/
static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags,
uint32_t ITSources)
uint32_t ITSources)
{
uint32_t tmpoptions = hfmpi2c->XferOptions;
uint32_t tmpITFlags = ITFlags;
@@ -4892,9 +5257,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp
/* Call FMPI2C Slave complete process */
FMPI2C_ITSlaveCplt(hfmpi2c, tmpITFlags);
}
if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET))
else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET))
{
/* Check that FMPI2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -5018,7 +5382,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp
* @retval HAL status
*/
static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags,
uint32_t ITSources)
uint32_t ITSources)
{
uint16_t devaddress;
uint32_t xfermode;
@@ -5057,7 +5421,15 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf
/* Prepare the new XferSize to transfer */
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
/* Errata workaround 170323 */
if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
{
hfmpi2c->XferSize = 1U;
}
else
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
}
xfermode = FMPI2C_RELOAD_MODE;
}
else
@@ -5149,6 +5521,170 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf
return HAL_OK;
}
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
* @param ITFlags Interrupt flags to handle.
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef FMPI2C_Mem_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags,
uint32_t ITSources)
{
uint32_t direction = FMPI2C_GENERATE_START_WRITE;
/* Process Locked */
__HAL_LOCK(hfmpi2c);
if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
/* Set corresponding Error Code */
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
/* No need to generate STOP, it is automatically done */
/* But enable STOP interrupt, to treat it */
/* Error callback will be send during stop flag treatment */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT);
/* Flush TX register */
FMPI2C_Flush_TXDR(hfmpi2c);
}
else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TXIS) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET))
{
/* Write LSB part of Memory Address */
hfmpi2c->Instance->TXDR = hfmpi2c->Memaddress;
/* Reset Memaddress content */
hfmpi2c->Memaddress = 0xFFFFFFFFU;
}
else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TCR) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET))
{
/* Disable Interrupt related to address step */
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
/* Enable only Error interrupt */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
if (hfmpi2c->XferCount != 0U)
{
/* Prepare the new XferSize to transfer */
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
/* Errata workaround 170323 */
if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
{
hfmpi2c->XferSize = 1U;
}
else
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
}
FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize,
FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize,
FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
}
/* Update XferCount value */
hfmpi2c->XferCount -= hfmpi2c->XferSize;
/* Enable DMA Request */
if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
{
hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
}
else
{
hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
}
}
else
{
/* Wrong size Status regarding TCR flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE);
}
}
else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TC) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET))
{
/* Disable Interrupt related to address step */
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
/* Enable only Error and NACK interrupt for data transfer */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
{
direction = FMPI2C_GENERATE_START_READ;
}
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
/* Errata workaround 170323 */
if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
{
hfmpi2c->XferSize = 1U;
}
else
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
}
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize,
FMPI2C_RELOAD_MODE, direction);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
/* Set NBYTES to write and generate RESTART */
FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize,
FMPI2C_AUTOEND_MODE, direction);
}
/* Update XferCount value */
hfmpi2c->XferCount -= hfmpi2c->XferSize;
/* Enable DMA Request */
if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
{
hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
}
else
{
hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
}
}
else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET))
{
/* Call FMPI2C Master complete process */
FMPI2C_ITMasterCplt(hfmpi2c, ITFlags);
}
else
{
/* Nothing to do */
}
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_OK;
}
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
@@ -5158,7 +5694,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf
* @retval HAL status
*/
static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags,
uint32_t ITSources)
uint32_t ITSources)
{
uint32_t tmpoptions = hfmpi2c->XferOptions;
uint32_t treatdmanack = 0U;
@@ -5174,9 +5710,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm
/* Call FMPI2C Slave complete process */
FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags);
}
if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET))
else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET))
{
/* Check that FMPI2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -5190,7 +5725,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm
{
if (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_CR1_RXDMAEN) != RESET)
{
if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U)
if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx) == 0U)
{
treatdmanack = 1U;
}
@@ -5202,7 +5737,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm
{
if (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_CR1_TXDMAEN) != RESET)
{
if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx) == 0U)
if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmatx) == 0U)
{
treatdmanack = 1U;
}
@@ -5303,8 +5838,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm
* @retval HAL status
*/
static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress,
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart)
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart)
{
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
@@ -5358,8 +5893,8 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c
* @retval HAL status
*/
static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress,
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart)
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart)
{
FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE);
@@ -5775,6 +6310,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
{
uint32_t tmpcr1value = READ_REG(hfmpi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
uint32_t tmpoptions = hfmpi2c->XferOptions;
HAL_FMPI2C_StateTypeDef tmpstate = hfmpi2c->State;
/* Clear STOP Flag */
@@ -5791,6 +6327,11 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT);
hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_RX;
}
else if (tmpstate == HAL_FMPI2C_STATE_LISTEN)
{
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT);
hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
}
else
{
/* Do nothing */
@@ -5813,7 +6354,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
if (hfmpi2c->hdmatx != NULL)
{
hfmpi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx);
hfmpi2c->XferCount = (uint16_t)FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmatx);
}
}
else if (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_CR1_RXDMAEN) != RESET)
@@ -5823,7 +6364,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
if (hfmpi2c->hdmarx != NULL)
{
hfmpi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx);
hfmpi2c->XferCount = (uint16_t)FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx);
}
}
else
@@ -5857,6 +6398,57 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
}
if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \
(FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_IT_NACKI) != RESET))
{
/* Check that FMPI2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0*/
/* So clear Flag NACKF only */
if (hfmpi2c->XferCount == 0U)
{
if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME))
/* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for
Warning[Pa134]: left and right operands are identical */
{
/* Call FMPI2C Listen complete process */
FMPI2C_ITListenCplt(hfmpi2c, tmpITFlags);
}
else if ((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != FMPI2C_NO_OPTION_FRAME))
{
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
/* Flush TX register */
FMPI2C_Flush_TXDR(hfmpi2c);
/* Last Byte is Transmitted */
/* Call FMPI2C Slave Sequential complete process */
FMPI2C_ITSlaveSeqCplt(hfmpi2c);
}
else
{
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
}
}
else
{
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
/* Set ErrorCode corresponding to a Non-Acknowledge */
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
if ((tmpoptions == FMPI2C_FIRST_FRAME) || (tmpoptions == FMPI2C_NEXT_FRAME))
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
}
}
}
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
hfmpi2c->XferISR = NULL;
@@ -5984,6 +6576,7 @@ static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
{
HAL_FMPI2C_StateTypeDef tmpstate = hfmpi2c->State;
uint32_t tmppreviousstate;
/* Reset handle parameters */
@@ -6011,20 +6604,38 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
/* Disable all interrupts */
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT);
/* Flush TX register */
FMPI2C_Flush_TXDR(hfmpi2c);
/* If state is an abort treatment on going, don't change state */
/* This change will be do later */
if (hfmpi2c->State != HAL_FMPI2C_STATE_ABORT)
{
/* Set HAL_FMPI2C_STATE_READY */
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
/* Check if a STOPF is detected */
if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
{
if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)
{
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
}
/* Clear STOP Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
}
}
hfmpi2c->XferISR = NULL;
}
/* Abort DMA TX transfer if any */
tmppreviousstate = hfmpi2c->PreviousState;
if ((hfmpi2c->hdmatx != NULL) && ((tmppreviousstate == FMPI2C_STATE_MASTER_BUSY_TX) || \
(tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_TX)))
(tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_TX)))
{
if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN)
{
@@ -6054,7 +6665,7 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
}
/* Abort DMA RX transfer if any */
else if ((hfmpi2c->hdmarx != NULL) && ((tmppreviousstate == FMPI2C_STATE_MASTER_BUSY_RX) || \
(tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_RX)))
(tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_RX)))
{
if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN)
{
@@ -6197,6 +6808,7 @@ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
}
}
/**
* @brief DMA FMPI2C slave transmit process complete callback.
* @param hdma DMA handle
@@ -6225,6 +6837,7 @@ static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
}
}
/**
* @brief DMA FMPI2C master receive process complete callback.
* @param hdma DMA handle
@@ -6253,7 +6866,15 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
/* Set the XferSize to transfer */
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
/* Errata workaround 170323 */
if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
{
hfmpi2c->XferSize = 1U;
}
else
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
}
}
else
{
@@ -6275,6 +6896,7 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
}
}
/**
* @brief DMA FMPI2C slave receive process complete callback.
* @param hdma DMA handle
@@ -6286,7 +6908,7 @@ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tmpoptions = hfmpi2c->XferOptions;
if ((__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U) && \
if ((FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx) == 0U) && \
(tmpoptions != FMPI2C_NO_OPTION_FRAME))
{
/* Disable DMA Request */
@@ -6303,6 +6925,7 @@ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
}
}
/**
* @brief DMA FMPI2C communication error callback.
* @param hdma DMA handle
@@ -6316,7 +6939,7 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma)
if (hfmpi2c->hdmatx != NULL)
{
if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx) == 0U)
if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmatx) == 0U)
{
treatdmaerror = 1U;
}
@@ -6324,7 +6947,7 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma)
if (hfmpi2c->hdmarx != NULL)
{
if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U)
if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx) == 0U)
{
treatdmaerror = 1U;
}
@@ -6341,6 +6964,7 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma)
}
}
/**
* @brief DMA FMPI2C communication abort callback
* (To be called at end of DMA Abort procedure).
@@ -6365,6 +6989,7 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma)
FMPI2C_TreatErrorCallback(hfmpi2c);
}
/**
* @brief This function handles FMPI2C Communication Timeout. It waits
* until a flag is no longer in the specified status.
@@ -6377,22 +7002,31 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma)
* @retval HAL status
*/
static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart)
uint32_t Timeout, uint32_t Tickstart)
{
while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == Status)
{
/* Check if an error is detected */
if (FMPI2C_IsErrorOccurred(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == Status))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_ERROR;
}
}
}
}
@@ -6408,7 +7042,7 @@ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfm
* @retval HAL status
*/
static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout,
uint32_t Tickstart)
uint32_t Tickstart)
{
while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET)
{
@@ -6422,6 +7056,47 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_ERROR;
}
}
}
}
return HAL_OK;
}
/**
* @brief This function handles FMPI2C Communication Timeout for specific usage of STOP flag.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout,
uint32_t Tickstart)
{
while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
{
/* Check if an error is detected */
if (FMPI2C_IsErrorOccurred(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
@@ -6437,41 +7112,6 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef
return HAL_OK;
}
/**
* @brief This function handles FMPI2C Communication Timeout for specific usage of STOP flag.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout,
uint32_t Tickstart)
{
while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
{
/* Check if an error is detected */
if (FMPI2C_IsErrorOccurred(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_ERROR;
}
}
return HAL_OK;
}
/**
* @brief This function handles FMPI2C Communication Timeout for specific usage of RXNE flag.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
@@ -6481,18 +7121,20 @@ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef
* @retval HAL status
*/
static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout,
uint32_t Tickstart)
uint32_t Tickstart)
{
while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET)
HAL_StatusTypeDef status = HAL_OK;
while ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
{
/* Check if an error is detected */
if (FMPI2C_IsErrorOccurred(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
status = HAL_ERROR;
}
/* Check if a STOPF is detected */
if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) && (status == HAL_OK))
{
/* Check if an RXNE is pending */
/* Store Last receive data if any */
@@ -6500,40 +7142,51 @@ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef
{
/* Return HAL_OK */
/* The Reading of data from RXDR will be done in caller function */
return HAL_OK;
status = HAL_OK;
}
else
/* Check a no-acknowledge have been detected */
if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)
{
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_AF;
/* Clear STOP Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
FMPI2C_RESET_CR2(hfmpi2c);
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_ERROR;
status = HAL_ERROR;
}
else
{
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
}
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
return HAL_ERROR;
status = HAL_ERROR;
}
}
}
return HAL_OK;
return status;
}
/**
@@ -6549,15 +7202,14 @@ static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, u
HAL_StatusTypeDef status = HAL_OK;
uint32_t itflag = hfmpi2c->Instance->ISR;
uint32_t error_code = 0;
uint32_t tickstart = Tickstart;
uint32_t tmp1;
HAL_FMPI2C_ModeTypeDef tmp2;
if (HAL_IS_BIT_SET(itflag, FMPI2C_FLAG_AF))
{
/* In case of Soft End condition, generate the STOP condition */
if (FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)
{
/* Generate Stop */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
}
/* Clear NACKF Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
/* Wait until STOP Flag is set or timeout occurred */
/* AutoEnd should be initiate after AF */
@@ -6566,11 +7218,35 @@ static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, u
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
error_code |= HAL_FMPI2C_ERROR_TIMEOUT;
tmp1 = (uint32_t)(hfmpi2c->Instance->CR2 & FMPI2C_CR2_STOP);
tmp2 = hfmpi2c->Mode;
status = HAL_ERROR;
/* In case of FMPI2C still busy, try to regenerate a STOP manually */
if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) != RESET) && \
(tmp1 != FMPI2C_CR2_STOP) && \
(tmp2 != HAL_FMPI2C_MODE_SLAVE))
{
/* Generate Stop */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
/* Update Tick with new reference */
tickstart = HAL_GetTick();
}
while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > FMPI2C_TIMEOUT_STOPF)
{
error_code |= HAL_FMPI2C_ERROR_TIMEOUT;
status = HAL_ERROR;
break;
}
}
}
}
}
@@ -6582,9 +7258,6 @@ static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, u
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
}
/* Clear NACKF Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
error_code |= HAL_FMPI2C_ERROR_AF;
status = HAL_ERROR;
@@ -6666,7 +7339,7 @@ static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, u
* @retval None
*/
static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
uint32_t Request)
uint32_t Request)
{
/* Check the parameters */
assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
@@ -6675,14 +7348,14 @@ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAdd
/* Declaration of tmp to prevent undefined behavior of volatile usage */
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | \
(((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | \
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
(((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | \
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
/* update CR2 register */
MODIFY_REG(hfmpi2c->Instance->CR2, \
((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | \
(FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | \
FMPI2C_CR2_START | FMPI2C_CR2_STOP)), tmp);
FMPI2C_CR2_START | FMPI2C_CR2_STOP)), tmp);
}
/**
@@ -6696,8 +7369,9 @@ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptR
{
uint32_t tmpisr = 0U;
if ((hfmpi2c->XferISR == FMPI2C_Master_ISR_DMA) || \
(hfmpi2c->XferISR == FMPI2C_Slave_ISR_DMA))
if ((hfmpi2c->XferISR != FMPI2C_Master_ISR_DMA) && \
(hfmpi2c->XferISR != FMPI2C_Slave_ISR_DMA) && \
(hfmpi2c->XferISR != FMPI2C_Mem_ISR_DMA))
{
if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
{
@@ -6705,6 +7379,51 @@ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptR
tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
}
if ((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT)
{
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI;
}
if ((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT)
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI;
}
if (InterruptRequest == FMPI2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI;
}
if (InterruptRequest == FMPI2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= FMPI2C_IT_STOPI;
}
}
else
{
if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
{
/* Enable ERR, STOP, NACK and ADDR interrupts */
tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
}
if ((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT)
{
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI;
}
if ((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT)
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI;
}
if (InterruptRequest == FMPI2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
@@ -6723,32 +7442,6 @@ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptR
tmpisr |= FMPI2C_IT_TCI;
}
}
else
{
if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
{
/* Enable ERR, STOP, NACK, and ADDR interrupts */
tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
}
if ((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT)
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI;
}
if ((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT)
{
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI;
}
if (InterruptRequest == FMPI2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= FMPI2C_IT_STOPI;
}
}
/* Enable interrupts only at the end */
/* to avoid the risk of FMPI2C interrupt handle execution before */

211
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c
View File

@@ -209,20 +209,28 @@
/** @addtogroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions
* @{
*/
/* Private functions to handle flags during polling transfer */
static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag,
FlagStatus Status, uint32_t Timeout);
FlagStatus Status, uint32_t Timeout);
static void FMPSMBUS_Enable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest);
static void FMPSMBUS_Disable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest);
/* Private functions for FMPSMBUS transfer IRQ handler */
static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags);
static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags);
static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus);
static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus);
/* Private functions to centralize the enable/disable of Interrupts */
static void FMPSMBUS_Enable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest);
static void FMPSMBUS_Disable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest);
/* Private function to flush TXDR register */
static void FMPSMBUS_Flush_TXDR(FMPSMBUS_HandleTypeDef *hfmpsmbus);
/* Private function to handle start, restart or stop a transfer */
static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size,
uint32_t Mode, uint32_t Request);
uint32_t Mode, uint32_t Request);
/* Private function to Convert Specific options */
static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus);
/**
* @}
*/
@@ -371,13 +379,13 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus)
/*---------------------------- FMPSMBUSx OAR2 Configuration -----------------------*/
/* Configure FMPSMBUSx: Dual mode and Own Address2 */
hfmpsmbus->Instance->OAR2 = (hfmpsmbus->Init.DualAddressMode | hfmpsmbus->Init.OwnAddress2 | \
(hfmpsmbus->Init.OwnAddress2Masks << 8U));
(hfmpsmbus->Init.OwnAddress2Masks << 8U));
/*---------------------------- FMPSMBUSx CR1 Configuration ------------------------*/
/* Configure FMPSMBUSx: Generalcall and NoStretch mode */
hfmpsmbus->Instance->CR1 = (hfmpsmbus->Init.GeneralCallMode | hfmpsmbus->Init.NoStretchMode | \
hfmpsmbus->Init.PacketErrorCheckMode | hfmpsmbus->Init.PeripheralMode | \
hfmpsmbus->Init.AnalogFilter);
hfmpsmbus->Init.PacketErrorCheckMode | hfmpsmbus->Init.PeripheralMode | \
hfmpsmbus->Init.AnalogFilter);
/* Enable Slave Byte Control only in case of Packet Error Check is enabled
and FMPSMBUS Peripheral is set in Slave mode */
@@ -577,6 +585,9 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps
/**
* @brief Register a User FMPSMBUS Callback
* To be used instead of the weak predefined callback
* @note The HAL_FMPSMBUS_RegisterCallback() may be called before HAL_FMPSMBUS_Init() in
* HAL_FMPSMBUS_STATE_RESET to register callbacks for HAL_FMPSMBUS_MSPINIT_CB_ID and
* HAL_FMPSMBUS_MSPDEINIT_CB_ID.
* @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
* the configuration information for the specified FMPSMBUS.
* @param CallbackID ID of the callback to be registered
@@ -593,8 +604,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus,
HAL_FMPSMBUS_CallbackIDTypeDef CallbackID,
pFMPSMBUS_CallbackTypeDef pCallback)
HAL_FMPSMBUS_CallbackIDTypeDef CallbackID,
pFMPSMBUS_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -606,9 +617,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbu
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hfmpsmbus);
if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State)
{
switch (CallbackID)
@@ -684,14 +692,15 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbu
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hfmpsmbus);
return status;
}
/**
* @brief Unregister an FMPSMBUS Callback
* FMPSMBUS callback is redirected to the weak predefined callback
* @note The HAL_FMPSMBUS_UnRegisterCallback() may be called before HAL_FMPSMBUS_Init() in
* HAL_FMPSMBUS_STATE_RESET to un-register callbacks for HAL_FMPSMBUS_MSPINIT_CB_ID and
* HAL_FMPSMBUS_MSPDEINIT_CB_ID
* @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
* the configuration information for the specified FMPSMBUS.
* @param CallbackID ID of the callback to be unregistered
@@ -708,13 +717,10 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbu
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus,
HAL_FMPSMBUS_CallbackIDTypeDef CallbackID)
HAL_FMPSMBUS_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hfmpsmbus);
if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State)
{
switch (CallbackID)
@@ -790,8 +796,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsm
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hfmpsmbus);
return status;
}
@@ -804,7 +808,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsm
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus,
pFMPSMBUS_AddrCallbackTypeDef pCallback)
pFMPSMBUS_AddrCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -815,8 +819,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmp
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hfmpsmbus);
if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State)
{
@@ -831,8 +833,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmp
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hfmpsmbus);
return status;
}
@@ -847,9 +847,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hfmpsmbus);
if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State)
{
hfmpsmbus->AddrCallback = HAL_FMPSMBUS_AddrCallback; /* Legacy weak AddrCallback */
@@ -863,8 +860,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hfmpsmbus);
return status;
}
@@ -929,9 +924,10 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress,
uint8_t *pData, uint16_t Size, uint32_t XferOptions)
uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
uint32_t tmp;
uint32_t sizetoxfer;
/* Check the parameters */
assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -964,13 +960,37 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm
hfmpsmbus->XferSize = Size;
}
sizetoxfer = hfmpsmbus->XferSize;
if ((sizetoxfer > 0U) && ((XferOptions == FMPSMBUS_FIRST_FRAME) ||
(XferOptions == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) ||
(XferOptions == FMPSMBUS_FIRST_FRAME_WITH_PEC) ||
(XferOptions == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)))
{
if (hfmpsmbus->pBuffPtr != NULL)
{
/* Preload TX register */
/* Write data to TXDR */
hfmpsmbus->Instance->TXDR = *hfmpsmbus->pBuffPtr;
/* Increment Buffer pointer */
hfmpsmbus->pBuffPtr++;
hfmpsmbus->XferCount--;
hfmpsmbus->XferSize--;
}
else
{
return HAL_ERROR;
}
}
/* Send Slave Address */
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE))
if ((sizetoxfer < hfmpsmbus->XferCount) && (sizetoxfer == MAX_NBYTE_SIZE))
{
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize,
FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE),
FMPSMBUS_GENERATE_START_WRITE);
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)sizetoxfer,
FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE),
FMPSMBUS_GENERATE_START_WRITE);
}
else
{
@@ -983,8 +1003,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm
if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) && \
(IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
{
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions,
FMPSMBUS_NO_STARTSTOP);
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)sizetoxfer, hfmpsmbus->XferOptions,
FMPSMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
@@ -993,17 +1013,24 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm
FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus);
/* Handle Transfer */
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize,
hfmpsmbus->XferOptions,
FMPSMBUS_GENERATE_START_WRITE);
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)sizetoxfer,
hfmpsmbus->XferOptions,
FMPSMBUS_GENERATE_START_WRITE);
}
/* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL)
{
hfmpsmbus->XferSize--;
hfmpsmbus->XferCount--;
if (hfmpsmbus->XferSize > 0U)
{
hfmpsmbus->XferSize--;
hfmpsmbus->XferCount--;
}
else
{
return HAL_ERROR;
}
}
}
@@ -1035,7 +1062,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions)
uint16_t Size, uint32_t XferOptions)
{
uint32_t tmp;
@@ -1076,8 +1103,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb
if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE))
{
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize,
FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE),
FMPSMBUS_GENERATE_START_READ);
FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE),
FMPSMBUS_GENERATE_START_READ);
}
else
{
@@ -1091,7 +1118,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb
(IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
{
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions,
FMPSMBUS_NO_STARTSTOP);
FMPSMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
@@ -1101,8 +1128,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb
/* Handle Transfer */
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize,
hfmpsmbus->XferOptions,
FMPSMBUS_GENERATE_START_READ);
hfmpsmbus->XferOptions,
FMPSMBUS_GENERATE_START_READ);
}
}
@@ -1197,7 +1224,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -1246,14 +1273,14 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmb
if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE))
{
FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize,
FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE),
FMPSMBUS_NO_STARTSTOP);
FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE),
FMPSMBUS_NO_STARTSTOP);
}
else
{
/* Set NBYTE to transmit */
FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions,
FMPSMBUS_NO_STARTSTOP);
FMPSMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
@@ -1295,7 +1322,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmb
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -1340,7 +1367,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbu
if (((FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) && (hfmpsmbus->XferSize == 2U)) || (hfmpsmbus->XferSize == 1U))
{
FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions,
FMPSMBUS_NO_STARTSTOP);
FMPSMBUS_NO_STARTSTOP);
}
else
{
@@ -1455,7 +1482,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout)
uint32_t Timeout)
{
uint32_t tickstart;
@@ -1604,7 +1631,7 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus)
/* FMPSMBUS in mode Transmitter ---------------------------------------------------*/
if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI |
FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) &&
FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) &&
((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TXIS) != RESET) ||
(FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) ||
(FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) ||
@@ -1629,7 +1656,7 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus)
/* FMPSMBUS in mode Receiver ----------------------------------------------------*/
if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI |
FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) &&
FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) &&
((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_RXNE) != RESET) ||
(FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) ||
(FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) ||
@@ -1750,7 +1777,7 @@ __weak void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus)
* @retval None
*/
__weak void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection,
uint16_t AddrMatchCode)
uint16_t AddrMatchCode)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfmpsmbus);
@@ -1819,7 +1846,7 @@ __weak void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus)
* the configuration information for the specified FMPSMBUS.
* @retval HAL state
*/
uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus)
uint32_t HAL_FMPSMBUS_GetState(const FMPSMBUS_HandleTypeDef *hfmpsmbus)
{
/* Return FMPSMBUS handle state */
return hfmpsmbus->State;
@@ -1831,7 +1858,7 @@ uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus)
* the configuration information for the specified FMPSMBUS.
* @retval FMPSMBUS Error Code
*/
uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus)
uint32_t HAL_FMPSMBUS_GetError(const FMPSMBUS_HandleTypeDef *hfmpsmbus)
{
return hfmpsmbus->ErrorCode;
}
@@ -1872,6 +1899,9 @@ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus,
/* No need to generate STOP, it is automatically done */
hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ACKF;
/* Flush TX register */
FMPSMBUS_Flush_TXDR(hfmpsmbus);
/* Process Unlocked */
__HAL_UNLOCK(hfmpsmbus);
@@ -1997,15 +2027,15 @@ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus,
if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE)
{
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, MAX_NBYTE_SIZE,
(FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)),
FMPSMBUS_NO_STARTSTOP);
(FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)),
FMPSMBUS_NO_STARTSTOP);
hfmpsmbus->XferSize = MAX_NBYTE_SIZE;
}
else
{
hfmpsmbus->XferSize = hfmpsmbus->XferCount;
FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions,
FMPSMBUS_NO_STARTSTOP);
FMPSMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL)
@@ -2162,6 +2192,9 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u
/* Clear NACK Flag */
__HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF);
/* Flush TX register */
FMPSMBUS_Flush_TXDR(hfmpsmbus);
/* Process Unlocked */
__HAL_UNLOCK(hfmpsmbus);
}
@@ -2183,6 +2216,9 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u
/* Set ErrorCode corresponding to a Non-Acknowledge */
hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ACKF;
/* Flush TX register */
FMPSMBUS_Flush_TXDR(hfmpsmbus);
/* Process Unlocked */
__HAL_UNLOCK(hfmpsmbus);
@@ -2258,8 +2294,8 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u
{
/* Set Reload for next Bytes */
FMPSMBUS_TransferConfig(hfmpsmbus, 0, 1,
FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE),
FMPSMBUS_NO_STARTSTOP);
FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE),
FMPSMBUS_NO_STARTSTOP);
/* Ack last Byte Read */
hfmpsmbus->Instance->CR2 &= ~FMPI2C_CR2_NACK;
@@ -2272,15 +2308,15 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u
if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE)
{
FMPSMBUS_TransferConfig(hfmpsmbus, 0, MAX_NBYTE_SIZE,
(FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)),
FMPSMBUS_NO_STARTSTOP);
(FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)),
FMPSMBUS_NO_STARTSTOP);
hfmpsmbus->XferSize = MAX_NBYTE_SIZE;
}
else
{
hfmpsmbus->XferSize = hfmpsmbus->XferCount;
FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions,
FMPSMBUS_NO_STARTSTOP);
FMPSMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL)
@@ -2584,7 +2620,13 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus)
__HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_PECERR);
}
/* Store current volatile hfmpsmbus->State, misra rule */
if (hfmpsmbus->ErrorCode != HAL_FMPSMBUS_ERROR_NONE)
{
/* Flush TX register */
FMPSMBUS_Flush_TXDR(hfmpsmbus);
}
/* Store current volatile hfmpsmbus->ErrorCode, misra rule */
tmperror = hfmpsmbus->ErrorCode;
/* Call the Error Callback in case of Error detected */
@@ -2625,7 +2667,7 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus)
* @retval HAL status
*/
static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag,
FlagStatus Status, uint32_t Timeout)
FlagStatus Status, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
@@ -2654,6 +2696,27 @@ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef
return HAL_OK;
}
/**
* @brief FMPSMBUS Tx data register flush process.
* @param hfmpsmbus FMPSMBUS handle.
* @retval None
*/
static void FMPSMBUS_Flush_TXDR(FMPSMBUS_HandleTypeDef *hfmpsmbus)
{
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
if (__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_TXIS) != RESET)
{
hfmpsmbus->Instance->TXDR = 0x00U;
}
/* Flush TX register if not empty */
if (__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_TXE) == RESET)
{
__HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_TXE);
}
}
/**
* @brief Handle FMPSMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
* @param hfmpsmbus FMPSMBUS handle.
@@ -2675,7 +2738,7 @@ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef
* @retval None
*/
static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size,
uint32_t Mode, uint32_t Request)
uint32_t Mode, uint32_t Request)
{
/* Check the parameters */
assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance));

186
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c
View File

@@ -123,7 +123,7 @@
(#) HAL in interruption mode (interruptions driven)
(##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes.
This is why, for driver implementation simplicity’s sake, user is requested to enter a message the
This is why, for driver implementation simplicity s sake, user is requested to enter a message the
length of which is a multiple of 4 bytes.
(##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR
@@ -272,10 +272,10 @@
*/
static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
static void HASH_DMAError(DMA_HandleTypeDef *hdma);
static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size);
static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status,
uint32_t Timeout);
static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout);
@@ -766,7 +766,8 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
@@ -792,7 +793,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
@@ -807,7 +808,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
@@ -824,7 +825,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pI
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
@@ -850,7 +852,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
@@ -865,7 +867,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBu
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
@@ -913,7 +915,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
@@ -937,7 +939,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
@@ -951,7 +953,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
@@ -967,7 +969,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
@@ -992,7 +994,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
@@ -1006,7 +1008,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pI
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
@@ -1079,7 +1081,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
@@ -1109,7 +1111,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
@@ -1166,7 +1168,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutB
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
@@ -1185,7 +1188,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
@@ -1227,7 +1231,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
@@ -1245,7 +1249,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
@@ -1256,7 +1260,6 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
*/
/** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
* @brief HMAC processing functions using DMA modes.
*
@@ -1299,7 +1302,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
@@ -1324,7 +1327,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
@@ -1371,7 +1374,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
* @param hhash HASH handle.
* @retval HAL HASH state
*/
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash)
{
return hhash->State;
}
@@ -1384,7 +1387,7 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
* @param hhash HASH handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash)
{
return hhash->Status;
}
@@ -1402,7 +1405,7 @@ HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
* must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
* @retval None
*/
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
void HAL_HASH_ContextSaving(const HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer)
{
uint32_t mem_ptr = (uint32_t)pMemBuffer;
uint32_t csr_ptr = (uint32_t)HASH->CSR;
@@ -1448,7 +1451,7 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
* beforehand).
* @retval None
*/
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer)
{
uint32_t mem_ptr = (uint32_t)pMemBuffer;
uint32_t csr_ptr = (uint32_t)HASH->CSR;
@@ -1627,7 +1630,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
* @param hhash pointer to a HASH_HandleTypeDef structure.
* @retval HASH Error Code
*/
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash)
{
/* Return HASH Error Code */
return hhash->ErrorCode;
@@ -1657,7 +1660,7 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
uint32_t inputaddr;
uint32_t buffersize;
HAL_StatusTypeDef status = HAL_OK;
HAL_StatusTypeDef status;
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
@@ -1830,12 +1833,13 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma)
* suspension time is stored in the handle for resumption later on.
* @retval HAL status
*/
static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
uint32_t buffercounter;
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
uint32_t tmp;
for (buffercounter = 0U; buffercounter < Size; buffercounter += 4U)
for (buffercounter = 0U; buffercounter < (Size / 4U); buffercounter++)
{
/* Write input data 4 bytes at a time */
HASH->DIN = *(uint32_t *)inputaddr;
@@ -1843,8 +1847,16 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
/* If the suspension flag has been raised and if the processing is not about
to end, suspend processing */
if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter + 4U) < Size))
if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (((buffercounter * 4U) + 4U) < Size))
{
/* wait for flag BUSY not set before Wait for DINIS = 1*/
if ((buffercounter * 4U) >= 64U)
{
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
return HAL_TIMEOUT;
}
}
/* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
in the input buffer */
if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
@@ -1859,14 +1871,14 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
/* Save current reading and writing locations of Input and Output buffers */
hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
hhash->HashInCount = Size - (buffercounter + 4U);
hhash->HashInCount = Size - ((buffercounter * 4U) + 4U);
}
else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Save current reading and writing locations of Input and Output buffers */
hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
hhash->HashKeyCount = Size - (buffercounter + 4U);
hhash->HashKeyCount = Size - ((buffercounter * 4U) + 4U);
}
else
{
@@ -1885,6 +1897,51 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
} /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */
/* At this point, all the data have been entered to the Peripheral: exit */
if ((Size % 4U) != 0U)
{
if (hhash->Init.DataType == HASH_DATATYPE_16B)
{
/* Write remaining input data */
if ((Size % 4U) <= 2U)
{
HASH->DIN = (uint32_t) * (uint16_t *)inputaddr;
}
if ((Size % 4U) == 3U)
{
HASH->DIN = *(uint32_t *)inputaddr;
}
}
else if ((hhash->Init.DataType == HASH_DATATYPE_8B)
|| (hhash->Init.DataType == HASH_DATATYPE_1B)) /* byte swap or bit swap or */
{
/* Write remaining input data */
if ((Size % 4U) == 1U)
{
HASH->DIN = (uint32_t) * (uint8_t *)inputaddr;
}
if ((Size % 4U) == 2U)
{
HASH->DIN = (uint32_t) * (uint16_t *)inputaddr;
}
if ((Size % 4U) == 3U)
{
tmp = *(uint8_t *)inputaddr;
tmp |= (uint32_t) * (uint8_t *)(inputaddr + 1U) << 8U;
tmp |= (uint32_t) * (uint8_t *)(inputaddr + 2U) << 16U;
HASH->DIN = tmp;
}
}
else
{
HASH->DIN = *(uint32_t *)inputaddr;
}
}
return HAL_OK;
}
@@ -1894,7 +1951,7 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
* @param Size message digest size in bytes.
* @retval None
*/
static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size)
{
uint32_t msgdigest = (uint32_t)pMsgDigest;
@@ -1963,7 +2020,6 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
}
/**
* @brief Handle HASH processing Timeout.
* @param hhash HASH handle.
@@ -2449,10 +2505,11 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Timeout, uint32_t Algorithm)
{
uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
HAL_HASH_StateTypeDef State_tmp = hhash->State;
@@ -2484,7 +2541,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint
/* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
input parameters of HASH_WriteData() */
pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */
Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
/* Set the phase */
@@ -2500,7 +2557,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint
/* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
to the API input parameters but to those saved beforehand by HASH_WriteData()
when the processing was suspended */
pInBuffer_tmp = hhash->pHashInBuffPtr;
pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr;
Size_tmp = hhash->HashInCount;
}
/* ... or multi-buffer HASH processing end */
@@ -2508,7 +2565,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint
{
/* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
input parameters of HASH_WriteData() */
pInBuffer_tmp = pInBuffer;
pInBuffer_tmp = (const uint8_t *)pInBuffer;
Size_tmp = Size;
/* Configure the number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(Size);
@@ -2586,9 +2643,10 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint32_t Algorithm)
{
uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
HAL_HASH_StateTypeDef State_tmp = hhash->State;
@@ -2620,7 +2678,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
/* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
to the API input parameters but to those saved beforehand by HASH_WriteData()
when the processing was suspended */
pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */
pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */
Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */
}
@@ -2631,7 +2689,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
/* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
input parameters of HASH_WriteData() */
pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */
Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
/* Check if initialization phase has already be performed */
@@ -2689,7 +2747,8 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint32_t Algorithm)
{
HAL_HASH_StateTypeDef State_tmp = hhash->State;
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
@@ -2799,7 +2858,6 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
}
/**
* @brief Initialize the HASH peripheral, next process pInBuffer then
* read the computed digest in interruption mode.
@@ -2811,7 +2869,8 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Algorithm)
{
HAL_HASH_StateTypeDef State_tmp = hhash->State;
@@ -2860,6 +2919,19 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
}
else if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) && (SizeVar < 4U))
{
if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
/* It remains data to enter and the Peripheral is ready to trigger DINIE,carry on as usual.
Update HashInCount and pHashInBuffPtr accordingly. */
hhash->HashInCount = SizeVar;
hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
/* Update the configuration of the number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(SizeVar);
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
}
}
else
{
initialization_skipped = 1; /* info user later on in case of multi-buffer */
@@ -2969,7 +3041,8 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint32_t Algorithm)
{
uint32_t inputaddr;
uint32_t inputSize;
@@ -3146,7 +3219,8 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, ui
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Timeout, uint32_t Algorithm)
{
HAL_HASH_StateTypeDef State_tmp = hhash->State;
@@ -3210,7 +3284,6 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint
}
/**
* @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
* read the computed digest in interruption mode.
@@ -3224,7 +3297,8 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Algorithm)
{
HAL_HASH_StateTypeDef State_tmp = hhash->State;
@@ -3319,7 +3393,6 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u
}
/**
* @brief Initialize the HASH peripheral in HMAC mode then initiate the required
* DMA transfers to feed the key and the input buffer to the Peripheral.
@@ -3335,7 +3408,8 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint32_t Algorithm)
{
uint32_t inputaddr;
uint32_t inputSize;
@@ -3475,7 +3549,7 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
/* Enable the DMA In DMA stream */
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
(((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) \
: (inputSize / 4U)));
: (inputSize / 4U)));
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);

79
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash_ex.c
View File

@@ -86,8 +86,6 @@
#include "stm32f4xx_hal.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -148,7 +146,7 @@
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
@@ -174,7 +172,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
@@ -189,7 +187,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
@@ -206,7 +204,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
@@ -232,7 +230,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
@@ -247,7 +245,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
@@ -290,7 +288,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
@@ -314,7 +312,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
@@ -328,7 +326,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
@@ -344,7 +343,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
@@ -368,7 +367,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
@@ -382,7 +381,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
@@ -422,8 +422,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
*/
/**
* @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
* to feed the input buffer to the Peripheral.
@@ -434,7 +432,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
@@ -464,7 +462,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *p
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
@@ -507,7 +505,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p
*/
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
* read the computed digest.
@@ -521,7 +518,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
@@ -540,7 +537,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
@@ -570,7 +567,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
*/
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
* read the computed digest in interrupt mode.
@@ -583,7 +579,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
@@ -601,15 +597,13 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
@@ -639,7 +633,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
*/
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
* DMA transfers to feed the key and the input buffer to the Peripheral.
@@ -659,7 +652,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
@@ -683,7 +676,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
@@ -759,7 +752,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = SET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
@@ -780,7 +773,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
if (hhash->DigestCalculationDisable != SET)
{
@@ -806,7 +799,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = RESET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
@@ -829,7 +822,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = SET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
@@ -850,7 +843,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
if (hhash->DigestCalculationDisable != SET)
{
@@ -876,7 +869,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = RESET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
@@ -898,7 +891,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
uint32_t Size)
{
hhash->DigestCalculationDisable = SET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
@@ -919,7 +913,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
if (hhash->DigestCalculationDisable != SET)
{
@@ -945,7 +939,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
uint32_t Size)
{
hhash->DigestCalculationDisable = RESET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
@@ -967,7 +962,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
uint32_t Size)
{
hhash->DigestCalculationDisable = SET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
@@ -988,7 +984,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
if (hhash->DigestCalculationDisable != SET)
{
@@ -1014,7 +1010,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
uint32_t Size)
{
hhash->DigestCalculationDisable = RESET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);

795
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c
View File

@@ -109,7 +109,9 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx;
#if defined (USB_OTG_FS)
const USB_OTG_GlobalTypeDef *USBx;
#endif /* defined (USB_OTG_FS) */
/* Check the HCD handle allocation */
if (hhcd == NULL)
@@ -120,7 +122,9 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
#if defined (USB_OTG_FS)
USBx = hhcd->Instance;
#endif /* defined (USB_OTG_FS) */
if (hhcd->State == HAL_HCD_STATE_RESET)
{
@@ -150,23 +154,37 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
hhcd->State = HAL_HCD_STATE_BUSY;
#if defined (USB_OTG_FS)
/* Disable DMA mode for FS instance */
if ((USBx->CID & (0x1U << 8)) == 0U)
if (USBx == USB_OTG_FS)
{
hhcd->Init.dma_enable = 0U;
}
#endif /* defined (USB_OTG_FS) */
/* Disable the Interrupts */
__HAL_HCD_DISABLE(hhcd);
/* Init the Core (common init.) */
(void)USB_CoreInit(hhcd->Instance, hhcd->Init);
if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK)
{
hhcd->State = HAL_HCD_STATE_ERROR;
return HAL_ERROR;
}
/* Force Host Mode*/
(void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
/* Force Host Mode */
if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK)
{
hhcd->State = HAL_HCD_STATE_ERROR;
return HAL_ERROR;
}
/* Init Host */
(void)USB_HostInit(hhcd->Instance, hhcd->Init);
if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK)
{
hhcd->State = HAL_HCD_STATE_ERROR;
return HAL_ERROR;
}
hhcd->State = HAL_HCD_STATE_READY;
@@ -197,24 +215,22 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
* This parameter can be a value from 0 to32K
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
uint8_t epnum,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps)
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum,
uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
{
HAL_StatusTypeDef status;
uint32_t HostCoreSpeed;
uint32_t HCcharMps = mps;
__HAL_LOCK(hhcd);
hhcd->hc[ch_num].do_ping = 0U;
hhcd->hc[ch_num].dev_addr = dev_address;
hhcd->hc[ch_num].max_packet = mps;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].ep_type = ep_type;
hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
(void)HAL_HCD_HC_ClearHubInfo(hhcd, ch_num);
if ((epnum & 0x80U) == 0x80U)
{
hhcd->hc[ch_num].ep_is_in = 1U;
@@ -224,15 +240,27 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
hhcd->hc[ch_num].ep_is_in = 0U;
}
hhcd->hc[ch_num].speed = speed;
HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance);
if (ep_type == EP_TYPE_ISOC)
{
/* FS device plugged to HS HUB */
if ((speed == HCD_DEVICE_SPEED_FULL) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED))
{
if (HCcharMps > ISO_SPLT_MPS)
{
/* ISO Max Packet Size for Split mode */
HCcharMps = ISO_SPLT_MPS;
}
}
}
hhcd->hc[ch_num].speed = speed;
hhcd->hc[ch_num].max_packet = (uint16_t)HCcharMps;
status = USB_HC_Init(hhcd->Instance, ch_num, epnum,
dev_address, speed, ep_type, (uint16_t)HCcharMps);
status = USB_HC_Init(hhcd->Instance,
ch_num,
epnum,
dev_address,
speed,
ep_type,
mps);
__HAL_UNLOCK(hhcd);
return status;
@@ -250,7 +278,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
HAL_StatusTypeDef status = HAL_OK;
__HAL_LOCK(hhcd);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
(void)USB_HC_Halt(hhcd->Instance, ch_num);
__HAL_UNLOCK(hhcd);
return status;
@@ -389,24 +417,41 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
switch (ep_type)
{
case EP_TYPE_CTRL:
if ((token == 1U) && (direction == 0U)) /*send data */
if (token == 1U) /* send data */
{
if (length == 0U)
if (direction == 0U)
{
/* For Status OUT stage, Length==0, Status Out PID = 1 */
hhcd->hc[ch_num].toggle_out = 1U;
}
if (length == 0U)
{
/* For Status OUT stage, Length == 0U, Status Out PID = 1 */
hhcd->hc[ch_num].toggle_out = 1U;
}
/* Set the Data Toggle bit as per the Flag */
if (hhcd->hc[ch_num].toggle_out == 0U)
{
/* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
/* Set the Data Toggle bit as per the Flag */
if (hhcd->hc[ch_num].toggle_out == 0U)
{
/* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{
/* Put the PID 1 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
else
{
/* Put the PID 1 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
if (hhcd->hc[ch_num].do_ssplit == 1U)
{
if (hhcd->hc[ch_num].toggle_in == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
}
}
break;
@@ -541,8 +586,11 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
(void)USB_FlushTxFifo(USBx, 0x10U);
(void)USB_FlushRxFifo(USBx);
/* Restore FS Clock */
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
{
/* Restore FS Clock */
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
}
/* Handle Host Port Disconnect Interrupt */
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
@@ -571,16 +619,6 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
}
/* Handle Rx Queue Level Interrupts */
if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
HCD_RXQLVL_IRQHandler(hhcd);
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
/* Handle Host channel Interrupt */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
{
@@ -601,6 +639,16 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
}
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
}
/* Handle Rx Queue Level Interrupts */
if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
HCD_RXQLVL_IRQHandler(hhcd);
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
}
}
@@ -1084,7 +1132,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
* @param hhcd HCD handle
* @retval HAL state
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd)
{
return hhcd->State;
}
@@ -1103,7 +1151,7 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
* URB_ERROR/
* URB_STALL
*/
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
{
return hhcd->hc[chnum].urb_state;
}
@@ -1116,7 +1164,7 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu
* This parameter can be a value from 1 to 15
* @retval last transfer size in byte
*/
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
{
return hhcd->hc[chnum].xfer_count;
}
@@ -1138,7 +1186,7 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
* HC_BBLERR/
* HC_DATATGLERR
*/
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
{
return hhcd->hc[chnum].state;
}
@@ -1163,6 +1211,54 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
return (USB_GetHostSpeed(hhcd->Instance));
}
/**
* @brief Set host channel Hub information.
* @param hhcd HCD handle
* @param ch_num Channel number.
* This parameter can be a value from 1 to 15
* @param addr Hub address
* @param PortNbr Hub port number
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
uint8_t addr, uint8_t PortNbr)
{
uint32_t HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance);
/* LS/FS device plugged to HS HUB */
if ((hhcd->hc[ch_num].speed != HCD_DEVICE_SPEED_HIGH) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED))
{
hhcd->hc[ch_num].do_ssplit = 1U;
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) && (hhcd->hc[ch_num].ep_is_in != 0U))
{
hhcd->hc[ch_num].toggle_in = 1U;
}
}
hhcd->hc[ch_num].hub_addr = addr;
hhcd->hc[ch_num].hub_port_nbr = PortNbr;
return HAL_OK;
}
/**
* @brief Clear host channel hub information.
* @param hhcd HCD handle
* @param ch_num Channel number.
* This parameter can be a value from 1 to 15
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
{
hhcd->hc[ch_num].do_ssplit = 0U;
hhcd->hc[ch_num].do_csplit = 0U;
hhcd->hc[ch_num].hub_addr = 0U;
hhcd->hc[ch_num].hub_port_nbr = 0U;
return HAL_OK;
}
/**
* @}
*/
@@ -1183,84 +1279,86 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
*/
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t ch_num = (uint32_t)chnum;
uint32_t tmpreg;
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR))
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
hhcd->hc[ch_num].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
hhcd->hc[chnum].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR)
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR))
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR);
hhcd->hc[ch_num].state = HC_BBLERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR);
hhcd->hc[chnum].state = HC_BBLERR;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL))
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
hhcd->hc[chnum].state = HC_STALL;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR))
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
hhcd->hc[ch_num].state = HC_STALL;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
hhcd->hc[chnum].state = HC_DATATGLERR;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR))
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
hhcd->hc[ch_num].state = HC_DATATGLERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
hhcd->hc[ch_num].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
hhcd->hc[chnum].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else
{
/* ... */
}
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
{
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
(void)USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC))
{
/* Clear any pending ACK IT */
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
if (hhcd->hc[chnum].do_csplit == 1U)
{
hhcd->hc[chnum].do_csplit = 0U;
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
}
if (hhcd->Init.dma_enable != 0U)
{
hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].XferSize - \
(USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
}
hhcd->hc[ch_num].state = HC_XFRC;
hhcd->hc[ch_num].ErrCnt = 0U;
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
hhcd->hc[chnum].state = HC_XFRC;
hhcd->hc[chnum].ErrCnt = 0U;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
(void)USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
}
else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC))
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_ISOC))
{
USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
hhcd->hc[ch_num].urb_state = URB_DONE;
USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
hhcd->hc[chnum].urb_state = URB_DONE;
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
@@ -1270,96 +1368,220 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
if (hhcd->Init.dma_enable == 1U)
{
if (((hhcd->hc[ch_num].XferSize / hhcd->hc[ch_num].max_packet) & 1U) != 0U)
if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U)
{
hhcd->hc[ch_num].toggle_in ^= 1U;
hhcd->hc[chnum].toggle_in ^= 1U;
}
}
else
{
hhcd->hc[ch_num].toggle_in ^= 1U;
hhcd->hc[chnum].toggle_in ^= 1U;
}
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
{
if (hhcd->hc[ch_num].state == HC_XFRC)
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
if (hhcd->hc[chnum].do_ssplit == 1U)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
hhcd->hc[chnum].do_csplit = 1U;
hhcd->hc[chnum].state = HC_ACK;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if (hhcd->hc[ch_num].state == HC_STALL)
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
if (hhcd->hc[chnum].state == HC_XFRC)
{
hhcd->hc[ch_num].urb_state = URB_STALL;
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].urb_state = URB_DONE;
}
else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
(hhcd->hc[ch_num].state == HC_DATATGLERR))
else if (hhcd->hc[chnum].state == HC_STALL)
{
hhcd->hc[ch_num].ErrCnt++;
if (hhcd->hc[ch_num].ErrCnt > 2U)
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].urb_state = URB_STALL;
}
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
(hhcd->hc[chnum].state == HC_DATATGLERR))
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].ErrCnt++;
if (hhcd->hc[chnum].ErrCnt > 2U)
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].urb_state = URB_ERROR;
hhcd->hc[chnum].ErrCnt = 0U;
if (hhcd->hc[chnum].do_ssplit == 1U)
{
hhcd->hc[chnum].do_csplit = 0U;
hhcd->hc[chnum].ep_ss_schedule = 0U;
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
}
hhcd->hc[chnum].urb_state = URB_ERROR;
}
else
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
hhcd->hc[chnum].urb_state = URB_NOTREADY;
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
/* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg;
}
}
}
else if (hhcd->hc[chnum].state == HC_NYET)
{
hhcd->hc[chnum].state = HC_HALTED;
if (hhcd->hc[chnum].do_csplit == 1U)
{
if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
{
hhcd->hc[chnum].NyetErrCnt++;
if (hhcd->hc[chnum].NyetErrCnt > 2U)
{
hhcd->hc[chnum].NyetErrCnt = 0U;
hhcd->hc[chnum].do_csplit = 0U;
if (hhcd->hc[chnum].ErrCnt < 3U)
{
hhcd->hc[chnum].ep_ss_schedule = 1U;
}
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
hhcd->hc[chnum].urb_state = URB_ERROR;
}
else
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
}
}
else
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
}
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
/* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg;
}
}
}
else if (hhcd->hc[chnum].state == HC_ACK)
{
hhcd->hc[chnum].state = HC_HALTED;
if (hhcd->hc[chnum].do_csplit == 1U)
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
/* Set Complete split and re-activate the channel */
USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET;
USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK;
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
/* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg;
}
}
}
else if (hhcd->hc[chnum].state == HC_NAK)
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].urb_state = URB_NOTREADY;
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
/* re-activate the channel */
tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
USBx_HC(chnum)->HCCHAR = tmpreg;
}
}
else if (hhcd->hc[ch_num].state == HC_NAK)
else if (hhcd->hc[chnum].state == HC_BBLERR)
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
/* re-activate the channel */
tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
}
else if (hhcd->hc[ch_num].state == HC_BBLERR)
{
hhcd->hc[ch_num].ErrCnt++;
hhcd->hc[ch_num].urb_state = URB_ERROR;
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].ErrCnt++;
hhcd->hc[chnum].urb_state = URB_ERROR;
}
else
{
/* ... */
if (hhcd->hc[chnum].state == HC_HALTED)
{
return;
}
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
{
if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
{
hhcd->hc[ch_num].ErrCnt = 0U;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
{
hhcd->hc[ch_num].ErrCnt = 0U;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
hhcd->hc[chnum].state = HC_NYET;
if (hhcd->Init.dma_enable == 0U)
if (hhcd->hc[chnum].do_ssplit == 0U)
{
hhcd->hc[chnum].ErrCnt = 0U;
}
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK))
{
if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
{
hhcd->hc[chnum].ErrCnt = 0U;
hhcd->hc[chnum].state = HC_NAK;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
hhcd->hc[chnum].ErrCnt = 0U;
if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U))
{
hhcd->hc[ch_num].state = HC_NAK;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
hhcd->hc[chnum].state = HC_NAK;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
}
else
{
/* ... */
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
if (hhcd->hc[chnum].do_csplit == 1U)
{
hhcd->hc[chnum].do_csplit = 0U;
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
__HAL_HCD_UNMASK_ACK_HC_INT(chnum);
}
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
}
else
{
@@ -1376,184 +1598,237 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
*/
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t ch_num = (uint32_t)chnum;
uint32_t tmpreg;
uint32_t num_packets;
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR))
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
hhcd->hc[ch_num].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
hhcd->hc[chnum].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
if (hhcd->hc[ch_num].do_ping == 1U)
if (hhcd->hc[chnum].do_ping == 1U)
{
hhcd->hc[ch_num].do_ping = 0U;
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
hhcd->hc[chnum].do_ping = 0U;
hhcd->hc[chnum].urb_state = URB_NOTREADY;
hhcd->hc[chnum].state = HC_ACK;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U))
{
if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC)
{
hhcd->hc[chnum].do_csplit = 1U;
}
hhcd->hc[chnum].state = HC_ACK;
(void)USB_HC_Halt(hhcd->Instance, chnum);
/* reset error_count */
hhcd->hc[chnum].ErrCnt = 0U;
}
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC))
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[chnum].ErrCnt = 0U;
/* transaction completed with NYET state, update do ping state */
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
{
hhcd->hc[ch_num].do_ping = 1U;
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
hhcd->hc[chnum].do_ping = 1U;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
hhcd->hc[ch_num].state = HC_XFRC;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
{
hhcd->hc[ch_num].state = HC_NYET;
hhcd->hc[ch_num].do_ping = 1U;
hhcd->hc[ch_num].ErrCnt = 0U;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
hhcd->hc[ch_num].state = HC_STALL;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].state = HC_NAK;
if (hhcd->hc[ch_num].do_ping == 0U)
if (hhcd->hc[chnum].do_csplit != 0U)
{
if (hhcd->hc[ch_num].speed == HCD_DEVICE_SPEED_HIGH)
hhcd->hc[chnum].do_csplit = 0U;
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
}
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
hhcd->hc[chnum].state = HC_XFRC;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
{
hhcd->hc[chnum].state = HC_NYET;
if (hhcd->hc[chnum].do_ssplit == 0U)
{
hhcd->hc[chnum].do_ping = 1U;
}
hhcd->hc[chnum].ErrCnt = 0U;
(void)USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
hhcd->hc[chnum].state = HC_STALL;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK))
{
hhcd->hc[chnum].ErrCnt = 0U;
hhcd->hc[chnum].state = HC_NAK;
if (hhcd->hc[chnum].do_ping == 0U)
{
if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH)
{
hhcd->hc[ch_num].do_ping = 1U;
hhcd->hc[chnum].do_ping = 1U;
}
}
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
(void)USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR))
{
if (hhcd->Init.dma_enable == 0U)
{
hhcd->hc[ch_num].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
hhcd->hc[chnum].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else
{
hhcd->hc[ch_num].ErrCnt++;
if (hhcd->hc[ch_num].ErrCnt > 2U)
hhcd->hc[chnum].ErrCnt++;
if (hhcd->hc[chnum].ErrCnt > 2U)
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].urb_state = URB_ERROR;
hhcd->hc[chnum].ErrCnt = 0U;
hhcd->hc[chnum].urb_state = URB_ERROR;
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
hhcd->hc[chnum].urb_state = URB_NOTREADY;
/* Re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg;
}
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR))
{
hhcd->hc[ch_num].state = HC_DATATGLERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
hhcd->hc[chnum].state = HC_DATATGLERR;
(void)USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
{
if (hhcd->hc[ch_num].state == HC_XFRC)
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
if (hhcd->hc[chnum].state == HC_XFRC)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].urb_state = URB_DONE;
if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_INTR))
{
if (hhcd->Init.dma_enable == 0U)
{
hhcd->hc[ch_num].toggle_out ^= 1U;
hhcd->hc[chnum].toggle_out ^= 1U;
}
if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[ch_num].xfer_len > 0U))
if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U))
{
num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet;
num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet;
if ((num_packets & 1U) != 0U)
{
hhcd->hc[ch_num].toggle_out ^= 1U;
hhcd->hc[chnum].toggle_out ^= 1U;
}
}
}
}
else if (hhcd->hc[ch_num].state == HC_NAK)
else if (hhcd->hc[chnum].state == HC_ACK)
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
}
else if (hhcd->hc[ch_num].state == HC_NYET)
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
}
else if (hhcd->hc[ch_num].state == HC_STALL)
{
hhcd->hc[ch_num].urb_state = URB_STALL;
}
else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
(hhcd->hc[ch_num].state == HC_DATATGLERR))
{
hhcd->hc[ch_num].ErrCnt++;
if (hhcd->hc[ch_num].ErrCnt > 2U)
hhcd->hc[chnum].state = HC_HALTED;
if (hhcd->hc[chnum].do_csplit == 1U)
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].urb_state = URB_ERROR;
hhcd->hc[chnum].urb_state = URB_NOTREADY;
}
}
else if (hhcd->hc[chnum].state == HC_NAK)
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].urb_state = URB_NOTREADY;
if (hhcd->hc[chnum].do_csplit == 1U)
{
hhcd->hc[chnum].do_csplit = 0U;
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
}
}
else if (hhcd->hc[chnum].state == HC_NYET)
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].urb_state = URB_NOTREADY;
}
else if (hhcd->hc[chnum].state == HC_STALL)
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].urb_state = URB_STALL;
}
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
(hhcd->hc[chnum].state == HC_DATATGLERR))
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].ErrCnt++;
if (hhcd->hc[chnum].ErrCnt > 2U)
{
hhcd->hc[chnum].ErrCnt = 0U;
hhcd->hc[chnum].urb_state = URB_ERROR;
}
else
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
hhcd->hc[chnum].urb_state = URB_NOTREADY;
/* re-activate the channel */
tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
USBx_HC(chnum)->HCCHAR = tmpreg;
}
}
else
{
/* ... */
return;
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
/* ... */
return;
}
}
@@ -1564,17 +1839,17 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
*/
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t pktsts;
uint32_t pktcnt;
uint32_t GrxstspReg;
uint32_t xferSizePktCnt;
uint32_t tmpreg;
uint32_t ch_num;
uint32_t chnum;
GrxstspReg = hhcd->Instance->GRXSTSP;
ch_num = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17;
pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4;
@@ -1582,33 +1857,33 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
{
case GRXSTS_PKTSTS_IN:
/* Read the data into the host buffer. */
if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0))
if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0))
{
if ((hhcd->hc[ch_num].xfer_count + pktcnt) <= hhcd->hc[ch_num].xfer_len)
if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len)
{
(void)USB_ReadPacket(hhcd->Instance,
hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
hhcd->hc[chnum].xfer_buff, (uint16_t)pktcnt);
/* manage multiple Xfer */
hhcd->hc[ch_num].xfer_buff += pktcnt;
hhcd->hc[ch_num].xfer_count += pktcnt;
hhcd->hc[chnum].xfer_buff += pktcnt;
hhcd->hc[chnum].xfer_count += pktcnt;
/* get transfer size packet count */
xferSizePktCnt = (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
if ((hhcd->hc[ch_num].max_packet == pktcnt) && (xferSizePktCnt > 0U))
if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U))
{
/* re-activate the channel when more packets are expected */
tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
hhcd->hc[ch_num].toggle_in ^= 1U;
USBx_HC(chnum)->HCCHAR = tmpreg;
hhcd->hc[chnum].toggle_in ^= 1U;
}
}
else
{
hhcd->hc[ch_num].urb_state = URB_ERROR;
hhcd->hc[chnum].urb_state = URB_ERROR;
}
}
break;
@@ -1630,7 +1905,7 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
*/
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0;
__IO uint32_t hprt0_dup;
@@ -1663,7 +1938,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
{
if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
{
if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
{
@@ -1678,7 +1953,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
{
if (hhcd->Init.speed == HCD_SPEED_FULL)
{
USBx_HOST->HFIR = 60000U;
USBx_HOST->HFIR = HFIR_60_MHZ;
}
}
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)

257
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c
View File

@@ -89,7 +89,7 @@
add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2C_ErrorCallback()
(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
@@ -139,7 +139,7 @@
or using HAL_I2C_Master_Seq_Receive_DMA()
(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
(++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
@@ -193,7 +193,7 @@
add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2C_ErrorCallback()
(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
@@ -313,7 +313,7 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup I2C_Private_Define
/** @defgroup I2C_Private_Define I2C Private Define
* @{
*/
#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
@@ -334,6 +334,14 @@
*/
/* Private macro -------------------------------------------------------------*/
/** @addtogroup I2C_Private_Macros
* @{
*/
/* Macro to get remaining data to transfer on DMA side */
#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -383,6 +391,9 @@ static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c);
/* Private function to Convert Specific options */
static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
/* Private function to flush DR register */
static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
@@ -940,6 +951,20 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @brief I2C data register flush process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c)
{
/* Write a dummy data in DR to clear TXE flag */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) != RESET)
{
hi2c->Instance->DR = 0x00U;
}
}
/**
* @}
*/
@@ -1357,6 +1382,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
{
if (hi2c->XferSize == 3U)
{
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
@@ -1662,10 +1694,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_BUSY;
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
@@ -1742,10 +1771,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_BUSY;
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
@@ -1952,10 +1978,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_BUSY;
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
@@ -2110,10 +2133,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_BUSY;
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
@@ -2811,6 +2831,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
{
if (hi2c->XferSize == 3U)
{
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
@@ -2871,10 +2896,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_BUSY;
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
@@ -2959,10 +2981,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_BUSY;
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
@@ -3057,10 +3076,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_BUSY;
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
@@ -3241,10 +3257,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_BUSY;
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
@@ -3577,10 +3590,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_BUSY;
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
@@ -3676,10 +3686,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_BUSY;
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
@@ -3859,10 +3866,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_BUSY;
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
@@ -3984,10 +3988,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_BUSY;
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
@@ -4712,7 +4713,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
}
/**
* @brief Abort a master I2C IT or DMA process communication with Interrupt.
* @brief Abort a master or memory I2C IT or DMA process communication with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
@@ -4728,7 +4729,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
UNUSED(DevAddress);
/* Abort Master transfer during Receive or Transmit process */
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER))
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && ((CurrentMode == HAL_I2C_MODE_MASTER) ||
(CurrentMode == HAL_I2C_MODE_MEM)))
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -5504,7 +5506,8 @@ static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c)
}
else
{
/* Do nothing */
/* Clear TXE and BTF flags */
I2C_Flush_DR(hi2c);
}
}
@@ -5519,7 +5522,9 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
uint32_t tmp;
uint32_t CurrentXferOptions;
CurrentXferOptions = hi2c->XferOptions;
tmp = hi2c->XferCount;
if (tmp > 3U)
{
@@ -5575,7 +5580,14 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
{
hi2c->PreviousState = I2C_STATE_NONE;
}
else
{
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
}
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterRxCpltCallback(hi2c);
@@ -5678,15 +5690,11 @@ static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
/* Enable Acknowledge */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
}
else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
else
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
else
{
/* Do nothing */
}
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
@@ -5723,7 +5731,14 @@ static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
{
hi2c->PreviousState = I2C_STATE_NONE;
}
else
{
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
}
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterRxCpltCallback(hi2c);
#else
@@ -6170,7 +6185,7 @@ static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
{
if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx));
hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx));
if (hi2c->XferCount != 0U)
{
@@ -6198,7 +6213,7 @@ static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
}
else
{
hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx));
hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx));
if (hi2c->XferCount != 0U)
{
@@ -6367,6 +6382,9 @@ static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Clear TXE flag */
I2C_Flush_DR(hi2c);
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->SlaveTxCpltCallback(hi2c);
#else
@@ -7028,7 +7046,14 @@ static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
{
hi2c->PreviousState = I2C_STATE_NONE;
}
else
{
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
}
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterRxCpltCallback(hi2c);
@@ -7203,15 +7228,18 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_ERROR;
}
}
}
}
@@ -7255,15 +7283,18 @@ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeD
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET))
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_ERROR;
}
}
}
}
@@ -7293,15 +7324,18 @@ static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET))
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_ERROR;
}
}
}
}
@@ -7331,15 +7365,18 @@ static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_ERROR;
}
}
}
}
@@ -7367,15 +7404,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_ERROR;
}
}
}
return HAL_OK;
@@ -7441,15 +7481,18 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_ERROR;
}
}
}
return HAL_OK;

82
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c
View File

@@ -848,15 +848,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2s);
if (hi2s->State != HAL_I2S_STATE_READY)
{
__HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2s);
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -967,15 +966,14 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2s);
if (hi2s->State != HAL_I2S_STATE_READY)
{
__HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2s);
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1065,15 +1063,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2s);
if (hi2s->State != HAL_I2S_STATE_READY)
{
__HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2s);
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1092,6 +1089,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
hi2s->TxXferCount = Size;
}
__HAL_UNLOCK(hi2s);
/* Enable TXE and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
@@ -1102,7 +1101,6 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
__HAL_I2S_ENABLE(hi2s);
}
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
@@ -1131,15 +1129,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2s);
if (hi2s->State != HAL_I2S_STATE_READY)
{
__HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2s);
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1158,6 +1155,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
hi2s->RxXferCount = Size;
}
__HAL_UNLOCK(hi2s);
/* Enable RXNE and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
@@ -1168,7 +1167,6 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
__HAL_I2S_ENABLE(hi2s);
}
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
@@ -1195,15 +1193,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2s);
if (hi2s->State != HAL_I2S_STATE_READY)
{
__HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2s);
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1245,12 +1242,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
/* Check if the I2S is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
__HAL_UNLOCK(hi2s);
/* Check if the I2S Tx request is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
@@ -1259,7 +1251,13 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
__HAL_UNLOCK(hi2s);
/* Check if the I2S is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
return HAL_OK;
}
@@ -1286,15 +1284,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2s);
if (hi2s->State != HAL_I2S_STATE_READY)
{
__HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2s);
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1342,12 +1339,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
/* Check if the I2S is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
__HAL_UNLOCK(hi2s);
/* Check if the I2S Rx request is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
@@ -1356,7 +1348,13 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
__HAL_UNLOCK(hi2s);
/* Check if the I2S is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
return HAL_OK;
}
@@ -1769,7 +1767,7 @@ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
* the configuration information for I2S module
* @retval HAL state
*/
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s)
{
return hi2s->State;
}
@@ -1780,7 +1778,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
* the configuration information for I2S module
* @retval I2S Error Code
*/
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s)
{
return hi2s->ErrorCode;
}

103
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c
View File

@@ -210,17 +210,15 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s,
uint32_t Timeout)
{
uint32_t tmp1 = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
if (hi2s->State != HAL_I2S_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
return HAL_ERROR;
}
/* Process Locked */
@@ -281,8 +279,11 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s,
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
errorcode = HAL_ERROR;
goto error;
hi2s->State = HAL_I2S_STATE_READY;
/* Process UnLock */
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
/* Write Data on DR register */
hi2s->Instance->DR = (*pTxData++);
@@ -305,8 +306,11 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s,
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
errorcode = HAL_ERROR;
goto error;
hi2s->State = HAL_I2S_STATE_READY;
/* Process UnLock */
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
/* Read Data from DR register */
(*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
@@ -354,8 +358,11 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s,
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
errorcode = HAL_ERROR;
goto error;
hi2s->State = HAL_I2S_STATE_READY;
/* Process UnLock */
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
/* Write Data on DR register */
I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
@@ -378,8 +385,11 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s,
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
errorcode = HAL_ERROR;
goto error;
hi2s->State = HAL_I2S_STATE_READY;
/* Process UnLock */
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
/* Read Data from DR register */
(*pRxData++) = hi2s->Instance->DR;
@@ -398,15 +408,17 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s,
}
}
if (hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
{
errorcode = HAL_ERROR;
}
error :
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
return errorcode;
if (hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
{
return HAL_ERROR;
}
else
{
return HAL_OK;
}
}
/**
@@ -430,12 +442,10 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s,
uint16_t Size)
{
uint32_t tmp1 = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
if (hi2s->State != HAL_I2S_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
@@ -510,15 +520,14 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s,
}
}
__HAL_UNLOCK(hi2s);
/* Enable I2Sext peripheral */
__HAL_I2SEXT_ENABLE(hi2s);
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
error :
__HAL_UNLOCK(hi2s);
return errorcode;
return HAL_OK;
}
/**
@@ -543,12 +552,11 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s,
{
uint32_t *tmp = NULL;
uint32_t tmp1 = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
HAL_StatusTypeDef status;
if (hi2s->State != HAL_I2S_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
@@ -609,27 +617,17 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s,
{
/* Enable the Rx DMA Stream */
tmp = (uint32_t *)&pRxData;
HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t *)tmp, hi2s->RxXferSize);
status = HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t *)tmp, hi2s->RxXferSize);
/* Enable Rx DMA Request */
SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
/* Enable the Tx DMA Stream */
tmp = (uint32_t *)&pTxData;
HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
status = HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
/* Enable Tx DMA Request */
SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
/* Check if the I2S is already enabled */
if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2Sext(receiver) before enabling I2Sx peripheral */
__HAL_I2SEXT_ENABLE(hi2s);
/* Enable I2S peripheral after the I2Sext */
__HAL_I2S_ENABLE(hi2s);
}
}
else
{
@@ -642,31 +640,30 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s,
}
/* Enable the Tx DMA Stream */
tmp = (uint32_t *)&pTxData;
HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
status = HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
/* Enable Tx DMA Request */
SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
/* Enable the Rx DMA Stream */
tmp = (uint32_t *)&pRxData;
HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t *)tmp, hi2s->RxXferSize);
status = HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t *)tmp, hi2s->RxXferSize);
/* Enable Rx DMA Request */
SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
/* Check if the I2S is already enabled */
if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
__HAL_I2SEXT_ENABLE(hi2s);
/* Enable I2S peripheral before the I2Sext */
__HAL_I2S_ENABLE(hi2s);
}
}
error :
__HAL_UNLOCK(hi2s);
return errorcode;
/* Check if the I2S is already enabled */
if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
__HAL_I2SEXT_ENABLE(hi2s);
/* Enable I2S peripheral before the I2Sext */
__HAL_I2S_ENABLE(hi2s);
}
return status;
}
/**

99
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c
View File

@@ -439,6 +439,8 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
/**
* @brief Register a User IRDA Callback
* To be used instead of the weak predefined callback
* @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
* to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -466,8 +468,6 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hirda);
if (hirda->gState == HAL_IRDA_STATE_READY)
{
@@ -552,15 +552,14 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hirda);
return status;
}
/**
* @brief Unregister an IRDA callback
* IRDA callback is redirected to the weak predefined callback
* @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
* to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -580,9 +579,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hirda);
if (HAL_IRDA_STATE_READY == hirda->gState)
{
switch (CallbackID)
@@ -666,9 +662,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hirda);
return status;
}
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
@@ -1080,19 +1073,33 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t
/* Enable the IRDA transmit DMA stream */
tmp = (const uint32_t *)&pData;
HAL_DMA_Start_IT(hirda->hdmatx, *(const uint32_t *)tmp, (uint32_t)&hirda->Instance->DR, Size);
if (HAL_DMA_Start_IT(hirda->hdmatx, *(const uint32_t *)tmp, (uint32_t)&hirda->Instance->DR, Size) == HAL_OK)
{
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
else
{
/* Set error code to DMA */
hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
return HAL_OK;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Restore hirda->gState to ready */
hirda->gState = HAL_IRDA_STATE_READY;
return HAL_ERROR;
}
}
else
{
@@ -1147,28 +1154,42 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
/* Enable the DMA stream */
tmp = (uint32_t *)&pData;
HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t *)tmp, Size);
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
__HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Process Unlocked */
__HAL_UNLOCK(hirda);
if (hirda->Init.Parity != IRDA_PARITY_NONE)
if (HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t *)tmp, Size) == HAL_OK)
{
/* Enable the IRDA Parity Error Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
__HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Process Unlocked */
__HAL_UNLOCK(hirda);
if (hirda->Init.Parity != IRDA_PARITY_NONE)
{
/* Enable the IRDA Parity Error Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
}
/* Enable the IRDA Error Interrupt: (Frame error, Noise error, Overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the USART CR3 register */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
return HAL_OK;
}
else
{
/* Set error code to DMA */
hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
/* Enable the IRDA Error Interrupt: (Frame error, Noise error, Overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the USART CR3 register */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Restore hirda->RxState to ready */
hirda->RxState = HAL_IRDA_STATE_READY;
return HAL_OK;
return HAL_ERROR;
}
}
else
{
@@ -2030,7 +2051,7 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
* the configuration information for the specified IRDA.
* @retval HAL state
*/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda)
{
uint32_t temp1 = 0x00U, temp2 = 0x00U;
temp1 = hirda->gState;
@@ -2045,7 +2066,7 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
* the configuration information for the specified IRDA.
* @retval IRDA Error Code
*/
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda)
{
return hirda->ErrorCode;
}

3
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c
View File

@@ -120,7 +120,8 @@
The timeout value is multiplied by 1000 to be converted in milliseconds.
LSI startup time is also considered here by adding LSI_STARTUP_TIME
converted in milliseconds. */
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \
((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_RVU | IWDG_SR_PVU)
/**
* @}

24
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c
View File

@@ -185,7 +185,7 @@
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag);
/* Exported functions --------------------------------------------------------*/
@@ -1753,7 +1753,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
* @param hlptim LPTIM handle
* @retval Counter value.
*/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@@ -1766,7 +1766,7 @@ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
* @param hlptim LPTIM handle
* @retval Autoreload value.
*/
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@@ -1779,7 +1779,7 @@ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
* @param hlptim LPTIM handle
* @retval Compare value.
*/
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@@ -2077,9 +2077,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim,
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hlptim);
if (hlptim->State == HAL_LPTIM_STATE_READY)
{
switch (CallbackID)
@@ -2150,9 +2147,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim,
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hlptim);
return status;
}
@@ -2178,9 +2172,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hlptim);
if (hlptim->State == HAL_LPTIM_STATE_READY)
{
switch (CallbackID)
@@ -2262,9 +2253,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hlptim);
return status;
}
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
@@ -2292,7 +2280,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti
* @param hlptim LPTIM handle
* @retval HAL state
*/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim)
{
/* Return LPTIM handle state */
return hlptim->State;
@@ -2339,7 +2327,7 @@ static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
* @param flag The lptim flag
* @retval HAL status
*/
static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag)
{
HAL_StatusTypeDef result = HAL_OK;
uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);

36
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c
View File

@@ -178,7 +178,13 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup LTDC_Private_Define LTDC Private Define
* @{
*/
#define LTDC_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -273,24 +279,20 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
/* Set Synchronization size */
hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
tmp = (hltdc->Init.HorizontalSync << 16U);
hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
WRITE_REG(hltdc->Instance->SSCR, (tmp | hltdc->Init.VerticalSync));
/* Set Accumulated Back porch */
hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
tmp = (hltdc->Init.AccumulatedHBP << 16U);
hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
WRITE_REG(hltdc->Instance->BPCR, (tmp | hltdc->Init.AccumulatedVBP));
/* Set Accumulated Active Width */
hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
tmp = (hltdc->Init.AccumulatedActiveW << 16U);
hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
WRITE_REG(hltdc->Instance->AWCR, (tmp | hltdc->Init.AccumulatedActiveH));
/* Set Total Width */
hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
tmp = (hltdc->Init.TotalWidth << 16U);
hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
WRITE_REG(hltdc->Instance->TWCR, (tmp | hltdc->Init.TotalHeigh));
/* Set the background color value */
tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
@@ -549,7 +551,7 @@ HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTD
break;
case HAL_LTDC_MSPINIT_CB_ID :
hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */
hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */
break;
case HAL_LTDC_MSPDEINIT_CB_ID :
@@ -910,11 +912,12 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize,
uint32_t LayerIdx)
{
uint32_t tmp;
uint32_t counter;
uint32_t *pcolorlut = pCLUT;
const uint32_t *pcolorlut = pCLUT;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
@@ -2086,7 +2089,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3
* the configuration information for the LTDC.
* @retval HAL state
*/
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc)
{
return hltdc->State;
}
@@ -2097,7 +2100,7 @@ HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
* the configuration information for the LTDC.
* @retval LTDC Error Code
*/
uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc)
{
return hltdc->ErrorCode;
}
@@ -2148,9 +2151,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
tmp2 = (pLayerCfg->Alpha0 << 24U);
LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED |
LTDC_LxDCCR_DCALPHA);
LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->DCCR, (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2));
/* Specifies the constant alpha value */
LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
@@ -2161,8 +2162,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
/* Configure the color frame buffer start address */
LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CFBAR, pLayerCfg->FBStartAdress);
if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
{

21
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c
View File

@@ -74,16 +74,18 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc
/* The following polarity is inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
#if !defined(POLARITIES_INVERSION_UPDATED)
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \
DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
#else
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29;
#endif /* POLARITIES_INVERSION_UPDATED */
/* Retrieve vertical timing parameters from DSI */
hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U;
@@ -115,17 +117,18 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD
LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
#if !defined(POLARITIES_INVERSION_UPDATED)
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \
DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
#else
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29;
#endif /* POLARITIES_INVERSION_UPDATED */
return HAL_OK;
}

32
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c
View File

@@ -1676,24 +1676,30 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
else if((context & MMC_CONTEXT_DMA) != 0U)
{
/* Abort the MMC DMA Streams */
if(hmmc->hdmatx != NULL)
if(((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
/* Set the DMA Tx abort callback */
hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort;
/* Abort DMA in IT mode */
if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK)
if(hmmc->hdmatx != NULL)
{
MMC_DMATxAbort(hmmc->hdmatx);
/* Set the DMA Tx abort callback */
hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort;
/* Abort DMA in IT mode */
if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK)
{
MMC_DMATxAbort(hmmc->hdmatx);
}
}
}
else if(hmmc->hdmarx != NULL)
else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
/* Set the DMA Rx abort callback */
hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort;
/* Abort DMA in IT mode */
if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK)
if(hmmc->hdmarx != NULL)
{
MMC_DMARxAbort(hmmc->hdmarx);
/* Set the DMA Rx abort callback */
hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort;
/* Abort DMA in IT mode */
if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK)
{
MMC_DMARxAbort(hmmc->hdmarx);
}
}
}
else
@@ -2377,7 +2383,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}

114
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c
View File

@@ -77,15 +77,15 @@
and a pointer to the user callback function.
Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : NAND MspInit.
(+) MspDeInitCallback : NAND MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_NAND_Init
reset to the legacy weak (overridden) functions in the HAL_NAND_Init
and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -100,7 +100,7 @@
When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -199,7 +199,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
__FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
#else
__FMC_NAND_ENABLE(hnand->Instance);
#endif
#endif /* (FMC_Bank2_3) || (FSMC_Bank2_3) */
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
@@ -428,7 +428,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN
}
#else
deviceaddress = NAND_DEVICE;
#endif
#endif /* FMC_Bank2_3 */
/* Send Read ID command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
@@ -441,7 +441,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN
if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
#else /* FMC_PCR2_PWID is defined */
if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
#endif
#endif /* FSMC_PCR2_PWID */
{
data = *(__IO uint32_t *)deviceaddress;
@@ -512,7 +512,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
}
#else
deviceaddress = NAND_DEVICE;
#endif
#endif /* FMC_Bank2_3 */
/* Send NAND reset command */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
@@ -539,7 +539,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
* @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig)
{
hnand->Config.PageSize = pDeviceConfig->PageSize;
hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
@@ -561,8 +561,8 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToRead)
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
@@ -597,7 +597,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT
}
#else
deviceaddress = NAND_DEVICE;
#endif
#endif /* FMC_Bank2_3 */
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
@@ -693,7 +693,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
*buff = *(uint8_t *)deviceaddress;
*buff = *(__IO uint8_t *)deviceaddress;
buff++;
}
@@ -730,8 +730,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToRead)
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
@@ -766,7 +766,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address
}
#else
deviceaddress = NAND_DEVICE;
#endif
#endif /* FMC_Bank2_3 */
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
@@ -860,9 +860,9 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address
/* Calculate PageSize */
#if defined(FSMC_PCR2_PWID)
if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
#else
if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
#endif /* FSMC_PCR2_PWID */
{
hnand->Config.PageSize = hnand->Config.PageSize / 2U;
@@ -876,7 +876,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
*buff = *(uint16_t *)deviceaddress;
*buff = *(__IO uint16_t *)deviceaddress;
buff++;
}
@@ -913,8 +913,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToWrite)
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint8_t *pBuffer, uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
@@ -922,7 +922,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address
uint32_t numpageswritten = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToWrite;
uint8_t *buff = pBuffer;
const uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -949,7 +949,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address
}
#else
deviceaddress = NAND_DEVICE;
#endif
#endif /* FMC_Bank2_3 */
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
@@ -1077,8 +1077,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToWrite)
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint16_t *pBuffer, uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
@@ -1086,7 +1086,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres
uint32_t numpageswritten = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToWrite;
uint16_t *buff = pBuffer;
const uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1113,7 +1113,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres
}
#else
deviceaddress = NAND_DEVICE;
#endif
#endif /* FMC_Bank2_3 */
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
@@ -1181,9 +1181,9 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres
/* Calculate PageSize */
#if defined(FSMC_PCR2_PWID)
if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
#else
if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
#endif /* FSMC_PCR2_PWID */
{
hnand->Config.PageSize = hnand->Config.PageSize / 2U;
@@ -1256,8 +1256,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumSpareAreaToRead)
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
@@ -1293,7 +1293,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add
}
#else
deviceaddress = NAND_DEVICE;
#endif
#endif /* FMC_Bank2_3 */
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
@@ -1395,7 +1395,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
*buff = *(uint8_t *)deviceaddress;
*buff = *(__IO uint8_t *)deviceaddress;
buff++;
}
@@ -1432,7 +1432,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
@@ -1469,7 +1469,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad
}
#else
deviceaddress = NAND_DEVICE;
#endif
#endif /* FMC_Bank2_3 */
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
@@ -1571,7 +1571,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
*buff = *(uint16_t *)deviceaddress;
*buff = *(__IO uint16_t *)deviceaddress;
buff++;
}
@@ -1608,8 +1608,8 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
@@ -1618,7 +1618,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaTowrite;
uint8_t *buff = pBuffer;
const uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1645,7 +1645,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad
}
#else
deviceaddress = NAND_DEVICE;
#endif
#endif /* FMC_Bank2_3 */
/* Page address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
@@ -1782,8 +1782,8 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
@@ -1792,7 +1792,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaTowrite;
uint16_t *buff = pBuffer;
const uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1819,7 +1819,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A
}
#else
deviceaddress = NAND_DEVICE;
#endif
#endif /* FMC_Bank2_3 */
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
@@ -1954,7 +1954,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A
* @param pAddress pointer to NAND address structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress)
{
uint32_t deviceaddress;
@@ -1983,7 +1983,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy
}
#else
deviceaddress = NAND_DEVICE;
#endif
#endif /* FMC_Bank2_3 */
/* Send Erase block command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
@@ -2021,7 +2021,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
*/
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
uint32_t status = NAND_VALID_ADDRESS;
@@ -2052,7 +2052,7 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User NAND Callback
* To be used instead of the weak (surcharged) predefined callback
* To be used to override the weak predefined callback
* @param hnand : NAND handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -2072,9 +2072,6 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hnand);
if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
@@ -2116,14 +2113,12 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hnand);
return status;
}
/**
* @brief Unregister a User NAND Callback
* NAND Callback is redirected to the weak (surcharged) predefined callback
* NAND Callback is redirected to the weak predefined callback
* @param hnand : NAND handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -2136,9 +2131,6 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hnand);
if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
@@ -2180,8 +2172,6 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hnand);
return status;
}
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
@@ -2332,7 +2322,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
* the configuration information for NAND module.
* @retval HAL state
*/
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand)
{
return hnand->State;
}
@@ -2343,7 +2333,7 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
* the configuration information for NAND module.
* @retval NAND status
*/
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand)
{
uint32_t data;
uint32_t deviceaddress;
@@ -2361,7 +2351,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
}
#else
deviceaddress = NAND_DEVICE;
#endif
#endif /* FMC_Bank2_3 */
/* Send Read status operation command */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;

208
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c
View File

@@ -74,15 +74,15 @@
and a pointer to the user callback function.
Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : NOR MspInit.
(+) MspDeInitCallback : NOR MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_NOR_Init
reset to the legacy weak (overridden) functions in the HAL_NOR_Init
and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -97,7 +97,7 @@
When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -106,7 +106,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
#if defined(FMC_Bank1) || defined(FSMC_Bank1)
#if defined(FMC_Bank1) || defined(FSMC_Bank1)
/** @addtogroup STM32F4xx_HAL_Driver
* @{
@@ -127,6 +127,11 @@
*/
/* Constants to define address to set to write a command */
#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA
#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA
#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555
#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA
#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
@@ -264,7 +269,8 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
(void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
/* Initialize NOR extended mode timing Interface */
(void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
(void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming,
hnor->Init.NSBank, hnor->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
@@ -310,7 +316,16 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
else
{
/* Get the value of the command set */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
NOR_CMD_DATA_CFI);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
}
hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
status = HAL_NOR_ReturnToReadMode(hnor);
@@ -472,9 +487,22 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
/* Send read ID command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_AUTO_SELECT);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_AUTO_SELECT);
}
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@@ -641,9 +669,22 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
/* Send read data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_READ_RESET);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_READ_RESET);
}
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@@ -722,9 +763,21 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
/* Send program data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_PROGRAM);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
}
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@@ -814,9 +867,22 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
/* Send read data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_READ_RESET);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_READ_RESET);
}
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@@ -909,10 +975,20 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
/* Issue unlock command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
/* Issue unlock command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
}
else
{
/* Issue unlock command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
}
/* Write Buffer Load Command */
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
@@ -1012,14 +1088,26 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
/* Send block erase command sequence */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
}
NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
@@ -1097,15 +1185,28 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
/* Send NOR chip erase command sequence */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH),
NOR_CMD_DATA_CHIP_ERASE);
}
}
else
{
@@ -1176,8 +1277,15 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
}
/* Send read CFI query command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
NOR_CMD_DATA_CFI);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
}
/* read the NOR CFI information */
pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
@@ -1201,7 +1309,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User NOR Callback
* To be used instead of the weak (surcharged) predefined callback
* To be used to override the weak predefined callback
* @param hnor : NOR handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1221,9 +1329,6 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hnor);
state = hnor->State;
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
@@ -1247,14 +1352,12 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hnor);
return status;
}
/**
* @brief Unregister a User NOR Callback
* NOR Callback is redirected to the weak (surcharged) predefined callback
* NOR Callback is redirected to the weak predefined callback
* @param hnor : NOR handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1267,9 +1370,6 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Ca
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
/* Process locked */
__HAL_LOCK(hnor);
state = hnor->State;
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
@@ -1293,8 +1393,6 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Ca
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hnor);
return status;
}
#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
@@ -1411,7 +1509,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
* the configuration information for NOR module.
* @retval NOR controller state
*/
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor)
{
return hnor->State;
}

49
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c
View File

@@ -163,7 +163,8 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming,
FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
{
/* Check the PCCARD controller state */
if (hpccard == NULL)
@@ -187,7 +188,7 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti
#else
/* Initialize the low level hardware (MSP) */
HAL_PCCARD_MspInit(hpccard);
#endif
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
}
/* Initialize the PCCARD state */
@@ -234,7 +235,7 @@ HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
#else
/* De-Initialize the low level hardware (MSP) */
HAL_PCCARD_MspDeInit(hpccard);
#endif
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Configure the PCCARD registers with their reset values */
FMC_PCCARD_DeInit(hpccard->Instance);
@@ -307,8 +308,9 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
*/
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
uint8_t status = 0;
uint32_t timeout = 0U;
uint32_t index = 0U;
uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -319,6 +321,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp
return HAL_BUSY;
}
/* Initialize timeout value */
timeout = PCCARD_TIMEOUT_READ_ID;
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
@@ -371,8 +376,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
uint8_t status = 0;
uint32_t timeout = 0U;
uint32_t index = 0U;
uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -383,6 +389,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
return HAL_BUSY;
}
/* Initialize timeout value */
timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
@@ -448,8 +457,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
uint8_t status = 0;
uint32_t timeout = 0U;
uint32_t index = 0U;
uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -460,6 +470,9 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
return HAL_BUSY;
}
/* Initialize timeout value */
timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
@@ -522,7 +535,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR;
uint8_t status = 0;
uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -624,7 +637,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
#endif
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Rising edge pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE);
@@ -638,7 +651,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
#endif
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Level pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_LEVEL);
@@ -652,7 +665,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
#endif
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Falling edge pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE);
@@ -666,7 +679,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
#endif
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt FIFO empty pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT);
@@ -823,7 +836,7 @@ HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, H
__HAL_UNLOCK(hpccard);
return status;
}
#endif
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
@@ -866,7 +879,8 @@ HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
*/
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
{
uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0U;
uint32_t timeout = PCCARD_TIMEOUT_STATUS;
uint32_t status_pccard = 0U;
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
@@ -902,7 +916,8 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
*/
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
{
uint8_t data = 0U, status_pccard = PCCARD_BUSY;
uint8_t data = 0U;
uint8_t status_pccard = PCCARD_BUSY;
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)

107
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c
View File

@@ -122,7 +122,9 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx;
#if defined (USB_OTG_FS)
const USB_OTG_GlobalTypeDef *USBx;
#endif /* defined (USB_OTG_FS) */
uint8_t i;
/* Check the PCD handle allocation */
@@ -134,7 +136,9 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
#if defined (USB_OTG_FS)
USBx = hpcd->Instance;
#endif /* defined (USB_OTG_FS) */
if (hpcd->State == HAL_PCD_STATE_RESET)
{
@@ -171,11 +175,13 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->State = HAL_PCD_STATE_BUSY;
#if defined (USB_OTG_FS)
/* Disable DMA mode for FS instance */
if ((USBx->CID & (0x1U << 8)) == 0U)
if (USBx == USB_OTG_FS)
{
hpcd->Init.dma_enable = 0U;
}
#endif /* defined (USB_OTG_FS) */
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
@@ -187,8 +193,12 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
return HAL_ERROR;
}
/* Force Device Mode*/
(void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
/* Force Device Mode */
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
{
hpcd->State = HAL_PCD_STATE_ERROR;
return HAL_ERROR;
}
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
@@ -224,13 +234,17 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->USB_Address = 0U;
hpcd->State = HAL_PCD_STATE_READY;
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|| defined(STM32F423xx)
/* Activate LPM */
if (hpcd->Init.lpm_enable == 1U)
{
(void)HAL_PCDEx_ActivateLPM(hpcd);
}
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
defined(STM32F423xx) */
(void)USB_DevDisconnect(hpcd->Instance);
return HAL_OK;
@@ -318,7 +332,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
* @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
* @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
* @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
* @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
* @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
* @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
@@ -432,7 +446,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
* @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
* @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
* @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
* @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
* @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
* @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
@@ -1004,8 +1018,8 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
__HAL_LOCK(hpcd);
if ((hpcd->Init.battery_charging_enable == 1U) &&
(hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
(hpcd->Init.battery_charging_enable == 1U))
{
/* Enable USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
@@ -1033,8 +1047,8 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
if ((hpcd->Init.battery_charging_enable == 1U) &&
(hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
(hpcd->Init.battery_charging_enable == 1U))
{
/* Disable USB Transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
@@ -1306,7 +1320,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
}
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|| defined(STM32F423xx)
/* Handle LPM Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
{
@@ -1332,7 +1348,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
defined(STM32F423xx) */
/* Handle Reset Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
{
@@ -1458,7 +1476,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U)))
(((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U)))
{
hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
@@ -1513,16 +1531,17 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
*/
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd)
{
#if defined (USB_OTG_FS)
USB_OTG_GlobalTypeDef *USBx;
USBx = hpcd->Instance;
if ((USBx->CID & (0x1U << 8)) == 0U)
if (USBx == USB_OTG_FS)
{
/* Clear EXTI pending Bit */
__HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG();
}
else
#endif /* defined (USB_OTG_FS) */
{
/* Clear EXTI pending Bit */
__HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG();
@@ -1733,8 +1752,8 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
__HAL_LOCK(hpcd);
if ((hpcd->Init.battery_charging_enable == 1U) &&
(hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
(hpcd->Init.battery_charging_enable == 1U))
{
/* Enable USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
@@ -1757,8 +1776,8 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
__HAL_LOCK(hpcd);
(void)USB_DevDisconnect(hpcd->Instance);
if ((hpcd->Init.battery_charging_enable == 1U) &&
(hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
(hpcd->Init.battery_charging_enable == 1U))
{
/* Disable USB Transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
@@ -1795,7 +1814,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type)
{
HAL_StatusTypeDef ret = HAL_OK;
HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
@@ -1810,7 +1829,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
}
ep->num = ep_addr & EP_ADDR_MSK;
ep->maxpacket = ep_mps;
ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
ep->type = ep_type;
if (ep->is_in != 0U)
@@ -1818,6 +1837,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
/* Assign a Tx FIFO */
ep->tx_fifo_num = ep->num;
}
/* Set initial data PID. */
if (ep_type == EP_TYPE_BULK)
{
@@ -1851,7 +1871,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 0U;
}
ep->num = ep_addr & EP_ADDR_MSK;
ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
@@ -1886,14 +1906,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
ep->dma_addr = (uint32_t)pBuf;
}
if ((ep_addr & EP_ADDR_MSK) == 0U)
{
(void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
}
else
{
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
}
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
return HAL_OK;
}
@@ -1904,7 +1917,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
* @param ep_addr endpoint address
* @retval Data Size
*/
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
{
return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
}
@@ -1934,14 +1947,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
ep->dma_addr = (uint32_t)pBuf;
}
if ((ep_addr & EP_ADDR_MSK) == 0U)
{
(void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
}
else
{
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
}
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
return HAL_OK;
}
@@ -2119,20 +2125,21 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
* @param hpcd PCD handle
* @retval HAL state
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd)
{
return hpcd->State;
}
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/**
* @brief Set the USB Device high speed test mode.
* @param hpcd PCD handle
* @param testmode USB Device high speed test mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode)
HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
switch (testmode)
@@ -2142,6 +2149,7 @@ HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode)
case TEST_SE0_NAK:
case TEST_PACKET:
case TEST_FORCE_EN:
USBx_DEVICE->DCTL &= ~(0x7U << 4);
USBx_DEVICE->DCTL |= (uint32_t)testmode << 4;
break;
@@ -2151,6 +2159,7 @@ HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode)
return HAL_OK;
}
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
*/
@@ -2233,9 +2242,9 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
USB_OTG_EPTypeDef *ep;
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if (hpcd->Init.dma_enable == 1U)
@@ -2344,9 +2353,9 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint
*/
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
@@ -2371,13 +2380,11 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint
}
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
*/
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
*/

22
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c
View File

@@ -115,7 +115,9 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
return HAL_OK;
}
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|| defined(STM32F423xx)
/**
* @brief Activate LPM feature.
* @param hpcd PCD handle
@@ -148,8 +150,11 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
return HAL_OK;
}
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
defined(STM32F423xx) */
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) \
|| defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
* @brief Handle BatteryCharging Process.
* @param hpcd PCD handle
@@ -178,9 +183,9 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
/* Primary detection: checks if connected to Standard Downstream Port
(without charging capability) */
USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
USBx->GCCFG &= ~USB_OTG_GCCFG_DCDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
@@ -196,9 +201,9 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
{
/* start secondary detection to check connection to Charging Downstream
Port or Dedicated Charging Port */
USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
HAL_Delay(50U);
if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
@@ -285,7 +290,8 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
return HAL_OK;
}
#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||
defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**

51
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c
View File

@@ -179,10 +179,12 @@ void HAL_PWR_DisableBkUpAccess(void)
==================
[..]
(+) Entry:
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry)
functions with
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
(++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE instruction and
no clear of pending event before.
-@@- The Regulator parameter is not used for the STM32F4 family
and is kept as parameter just to maintain compatibility with the
@@ -204,10 +206,17 @@ void HAL_PWR_DisableBkUpAccess(void)
the HAL_PWREx_DisableFlashPowerDown() function.
(+) Entry:
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry)
function with:
(++) Main regulator ON.
(++) Low Power regulator ON.
(++) Regulator:
(+++) Main regulator ON.
(+++) Low Power regulator ON.
(++) STOPEntry:
(+++) PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
(+++) PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and
clear of pending events before.
(+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and
no clear of pending event before.
(+) Exit:
Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
@@ -372,12 +381,18 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
* just to maintain compatibility with the lower power families.
* @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
* @arg PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction
* @arg PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and
* clear of pending events before.
* @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR : Enter SLEEP mode with WFE instruction and
* no clear of pending event before.
* @retval None
*/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(Regulator);
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
@@ -393,9 +408,14 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
}
else
{
if(SLEEPEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)
{
/* Clear all pending event */
__SEV();
__WFE();
}
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
}
@@ -415,8 +435,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
* @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
* @arg PWR_STOPENTRY_WFI : Enter Stop mode with WFI instruction
* @arg PWR_STOPENTRY_WFE : Enter Stop mode with WFE instruction and
* clear of pending events before.
* @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and
* no clear of pending event before.
* @retval None
*/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
@@ -439,9 +462,13 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
}
else
{
if(STOPEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR)
{
/* Clear all pending event */
__SEV();
__WFE();
}
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */

98
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c
View File

@@ -162,7 +162,7 @@
and a pointer to the user callback function.
Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
weak (overridden) function. It allows to reset following callbacks:
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
(+) FifoThresholdCallback : callback when the fifo threshold is reached.
@@ -178,9 +178,9 @@
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init
reset to the legacy weak (overridden) functions in the HAL_QSPI_Init
and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -195,7 +195,7 @@
When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
and weak (overridden) callbacks are used.
*** Workarounds linked to Silicon Limitation ***
====================================================
@@ -573,7 +573,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* Clear Busy bit */
HAL_QSPI_Abort_IT(hqspi);
(void)HAL_QSPI_Abort_IT(hqspi);
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@@ -616,7 +616,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* Workaround - Extra data written in the FIFO at the end of a read transfer */
HAL_QSPI_Abort_IT(hqspi);
(void)HAL_QSPI_Abort_IT(hqspi);
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@@ -1379,20 +1379,24 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
/* Update direction mode bit */
MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
/* Enable the QSPI transmit DMA Channel */
if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK)
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
}
else
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
status = HAL_ERROR;
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
hqspi->State = HAL_QSPI_STATE_READY;
@@ -1552,20 +1556,23 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
/* Start the transfer by re-writing the address in AR register */
WRITE_REG(hqspi->Instance->AR, addr_reg);
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
/* Enable the DMA Channel */
if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK)
{
/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
/* Process unlocked */
__HAL_UNLOCK(hqspi);
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
}
else
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
status = HAL_ERROR;
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
hqspi->State = HAL_QSPI_STATE_READY;
@@ -1580,26 +1587,29 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
/* Update direction mode bit */
MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
/* Configure QSPI: CCR register with functional as indirect read */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
/* Start the transfer by re-writing the address in AR register */
WRITE_REG(hqspi->Instance->AR, addr_reg);
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
/* Enable the DMA Channel */
if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize)== HAL_OK)
{
/* Configure QSPI: CCR register with functional as indirect read */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
/* Start the transfer by re-writing the address in AR register */
WRITE_REG(hqspi->Instance->AR, addr_reg);
/* Process unlocked */
__HAL_UNLOCK(hqspi);
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
}
else
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
status = HAL_ERROR;
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
hqspi->State = HAL_QSPI_STATE_READY;
@@ -1851,7 +1861,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT
assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
{
assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
}
assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
@@ -1891,9 +1901,9 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT
if (status == HAL_OK)
{
/* Configure QSPI: CR register with timeout counter enable */
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
{
assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
@@ -2075,7 +2085,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User QSPI Callback
* To be used instead of the weak (surcharged) predefined callback
* To be used to override the weak predefined callback
* @param hqspi QSPI handle
* @param CallbackId ID of the callback to be registered
* This parameter can be one of the following values:
@@ -2189,7 +2199,7 @@ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI
/**
* @brief Unregister a User QSPI Callback
* QSPI Callback is redirected to the weak (surcharged) predefined callback
* QSPI Callback is redirected to the weak predefined callback
* @param hqspi QSPI handle
* @param CallbackId ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -2321,7 +2331,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS
* @param hqspi QSPI handle
* @retval HAL state
*/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi)
{
/* Return QSPI handle state */
return hqspi->State;
@@ -2332,7 +2342,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
* @param hqspi QSPI handle
* @retval QSPI Error Code
*/
uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi)
{
return hqspi->ErrorCode;
}
@@ -2512,7 +2522,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t
* @param hqspi QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi)
{
return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
}
@@ -2799,6 +2809,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
cmd->AlternateBytesSize | cmd->AlternateByteMode |
cmd->AddressMode | cmd->InstructionMode |
cmd->Instruction | FunctionalMode));
/* Clear AR register */
CLEAR_REG(hqspi->Instance->AR);
}
}
else
@@ -2826,6 +2839,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
cmd->AlternateByteMode | cmd->AddressMode |
cmd->InstructionMode | cmd->Instruction | FunctionalMode));
/* Clear AR register */
CLEAR_REG(hqspi->Instance->AR);
}
}
}
@@ -2860,6 +2876,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
cmd->AlternateBytesSize | cmd->AlternateByteMode |
cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
/* Clear AR register */
CLEAR_REG(hqspi->Instance->AR);
}
}
else
@@ -2889,6 +2908,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
cmd->AlternateByteMode | cmd->AddressMode |
cmd->InstructionMode | FunctionalMode));
/* Clear AR register */
CLEAR_REG(hqspi->Instance->AR);
}
}
}

196
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c
View File

@@ -110,8 +110,8 @@
*/
/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -216,12 +216,12 @@ __weak HAL_StatusTypeDef HAL_RCC_DeInit(void)
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
{
uint32_t tickstart, pll_config;
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
if (RCC_OscInitStruct == NULL)
{
return HAL_ERROR;
}
@@ -229,15 +229,15 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
{
return HAL_ERROR;
}
@@ -248,15 +248,15 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
{
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -268,9 +268,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
tickstart = HAL_GetTick();
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -279,18 +279,18 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
{
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
{
return HAL_ERROR;
}
@@ -304,7 +304,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
@@ -313,9 +313,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -333,9 +333,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -344,13 +344,13 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
@@ -359,9 +359,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
tickstart = HAL_GetTick();
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -376,9 +376,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
tickstart = HAL_GetTick();
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -386,7 +386,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
FlagStatus pwrclkchanged = RESET;
@@ -395,13 +395,13 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
{
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
@@ -409,9 +409,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -421,15 +421,15 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -441,9 +441,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -451,7 +451,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
if (pwrclkchanged == SET)
{
__HAL_RCC_PWR_CLK_DISABLE();
}
@@ -462,9 +462,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
{
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
@@ -479,10 +479,10 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -501,9 +501,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -517,10 +517,10 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -530,7 +530,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
{
return HAL_ERROR;
}
@@ -553,7 +553,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
#endif
#endif /* RCC_PLLCFGR_PLLR */
{
return HAL_ERROR;
}
@@ -588,12 +588,12 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
if (RCC_ClkInitStruct == NULL)
{
return HAL_ERROR;
}
@@ -607,30 +607,30 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
if (FLatency > __HAL_FLASH_GET_LATENCY())
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
if (__HAL_FLASH_GET_LATENCY() != FLatency)
{
return HAL_ERROR;
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
}
@@ -640,25 +640,25 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
return HAL_ERROR;
}
}
/* PLL is selected as System Clock Source */
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
return HAL_ERROR;
}
@@ -667,7 +667,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
return HAL_ERROR;
}
@@ -688,38 +688,38 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
if (FLatency < __HAL_FLASH_GET_LATENCY())
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
if (__HAL_FLASH_GET_LATENCY() != FLatency)
{
return HAL_ERROR;
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick (uwTickPrio);
HAL_InitTick(uwTickPrio);
return HAL_OK;
}
@@ -729,8 +729,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
*/
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
* @brief RCC clocks control functions
*
* @brief RCC clocks control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -779,7 +779,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
assert_param(IS_RCC_MCO(RCC_MCOx));
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
/* RCC_MCO1 */
if(RCC_MCOx == RCC_MCO1)
if (RCC_MCOx == RCC_MCO1)
{
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
@@ -797,7 +797,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
/* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
/* This RCC MCO1 enable feature is available only on STM32F410xx devices */
/* This RCC MCO1 enable feature is available only on STM32F410xx devices */
#if defined(RCC_CFGR_MCO1EN)
__HAL_RCC_MCO1_ENABLE();
#endif /* RCC_CFGR_MCO1EN */
@@ -821,7 +821,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
/* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
/* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
/* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
#if defined(RCC_CFGR_MCO2EN)
__HAL_RCC_MCO2_ENABLE();
#endif /* RCC_CFGR_MCO2EN */
@@ -884,7 +884,9 @@ void HAL_RCC_DisableCSS(void)
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
uint32_t pllm = 0U;
uint32_t pllvco = 0U;
uint32_t pllp = 0U;
uint32_t sysclockfreq = 0U;
/* Get SYSCLK source -------------------------------------------------------*/
@@ -893,7 +895,7 @@ __weak uint32_t HAL_RCC_GetSysClockFreq(void)
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
break;
break;
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
@@ -905,19 +907,19 @@ __weak uint32_t HAL_RCC_GetSysClockFreq(void)
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U);
sysclockfreq = pllvco/pllp;
sysclockfreq = pllvco / pllp;
break;
}
default:
@@ -952,7 +954,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
}
/**
@@ -964,7 +966,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
}
/**
@@ -980,11 +982,11 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
/* Get the HSE configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
{
RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
}
else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
{
RCC_OscInitStruct->HSEState = RCC_HSE_ON;
}
@@ -994,7 +996,7 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Get the HSI configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
{
RCC_OscInitStruct->HSIState = RCC_HSI_ON;
}
@@ -1003,14 +1005,14 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
/* Get the LSE configuration -----------------------------------------------*/
if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
{
RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
}
else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
{
RCC_OscInitStruct->LSEState = RCC_LSE_ON;
}
@@ -1020,7 +1022,7 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Get the LSI configuration -----------------------------------------------*/
if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
{
RCC_OscInitStruct->LSIState = RCC_LSI_ON;
}
@@ -1030,7 +1032,7 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Get the PLL configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
{
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
}
@@ -1082,7 +1084,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF
void HAL_RCC_NMI_IRQHandler(void)
{
/* Check RCC CSSF flag */
if(__HAL_RCC_GET_IT(RCC_IT_CSS))
if (__HAL_RCC_GET_IT(RCC_IT_CSS))
{
/* RCC Clock Security System interrupt user callback */
HAL_RCC_CSSCallback();

997
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c
View File

@@ -50,8 +50,8 @@
*/
/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
* @brief Extended Peripheral Control functions
*
* @brief Extended Peripheral Control functions
*
@verbatim
===============================================================================
##### Extended Peripheral Control functions #####
@@ -100,7 +100,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*------------------------ I2S APB1 configuration --------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
{
/* Check the parameters */
assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
@@ -108,7 +108,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure I2S Clock source */
__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
{
plli2sused = 1U;
}
@@ -116,7 +116,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*---------------------------- I2S APB2 configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
{
/* Check the parameters */
assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
@@ -124,7 +124,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure I2S Clock source */
__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
{
plli2sused = 1U;
}
@@ -132,7 +132,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*--------------------------- SAI1 configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
@@ -140,12 +140,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure SAI1 Clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
{
plli2sused = 1U;
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
{
pllsaiused = 1U;
}
@@ -153,7 +153,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*-------------------------- SAI2 configuration ----------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
@@ -162,12 +162,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
{
plli2sused = 1U;
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
{
pllsaiused = 1U;
}
@@ -175,7 +175,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*----------------------------- RTC configuration --------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
@@ -189,16 +189,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
while((PWR->CR & PWR_CR_DBP) == RESET)
while ((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
@@ -209,15 +209,15 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
RCC->BDCR = tmpreg1;
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
{
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -229,7 +229,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*---------------------------- TIM configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
{
/* Configure Timer Prescaler */
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
@@ -237,7 +237,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*---------------------------- FMPI2C1 Configuration -----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
{
/* Check the parameters */
assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
@@ -248,7 +248,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*------------------------------ CEC Configuration -------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
{
/* Check the parameters */
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
@@ -259,7 +259,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*----------------------------- CLK48 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
{
/* Check the parameters */
assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
@@ -268,7 +268,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
/* Enable the PLLSAI when it's used as clock source for CLK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
{
pllsaiused = 1U;
}
@@ -276,7 +276,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*----------------------------- SDIO Configuration -------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
{
/* Check the parameters */
assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
@@ -287,7 +287,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*------------------------------ SPDIFRX Configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
{
/* Check the parameters */
assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
@@ -295,7 +295,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure the SPDIFRX clock source */
__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
/* Enable the PLLI2S when it's used as clock source for SPDIFRX */
if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
{
plli2sused = 1U;
}
@@ -305,16 +305,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*---------------------------- PLLI2S Configuration ------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
I2S on APB2 or SPDIFRX */
if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
{
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -326,8 +326,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1)
&& (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
@@ -338,12 +339,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq,
PeriphClkInit->PLLI2S.PLLI2SR);
}
/*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
{
/* Check for PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
@@ -357,14 +360,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp,
PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
}
/*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
&& (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
@@ -374,11 +379,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP,
plli2sq, plli2sr);
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
/*----------------- In Case of PLLI2S is just selected -----------------*/
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
{
/* Check for Parameters */
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
@@ -387,7 +393,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP,
PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
}
/* Enable the PLLI2S */
@@ -395,9 +402,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -408,16 +415,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*----------------------------- PLLSAI Configuration -----------------------*/
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
if(pllsaiused == 1U)
if (pllsaiused == 1U)
{
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -429,8 +436,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
{
/* check for PLLSAIQ Parameter */
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
@@ -442,7 +450,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip,
PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
@@ -450,7 +459,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/
/* In Case of PLLI2S is selected as source clock for CLK48 */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
&& (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
{
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
@@ -459,7 +469,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U);
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP,
pllsaiq, 0U);
}
/* Enable PLLSAI Clock */
@@ -467,9 +478,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -491,11 +502,11 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
uint32_t tempreg;
/* Set all possible values for the extended clock type parameter------------*/
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMPI2C1 |\
RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO |\
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 | \
RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC | \
RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMPI2C1 | \
RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO | \
RCC_PERIPHCLK_SPDIFRX;
/* Get the PLLI2S Clock configuration --------------------------------------*/
@@ -580,18 +591,18 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
uint32_t vcooutput = 0U;
switch (PeriphClk)
{
case RCC_PERIPHCLK_SAI1:
case RCC_PERIPHCLK_SAI2:
case RCC_PERIPHCLK_SAI1:
case RCC_PERIPHCLK_SAI2:
{
saiclocksource = RCC->DCKCFGR;
saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC);
switch (saiclocksource)
{
case 0U: /* PLLSAI is the clock source for SAI*/
case 0U: /* PLLSAI is the clock source for SAI*/
{
/* Configure the PLLSAI division factor */
/* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
{
/* In Case the PLL Source is HSI (Internal Clock) */
vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
@@ -604,19 +615,19 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1);
frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U)) / (tmpreg1);
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
frequency = frequency/(tmpreg1);
frequency = frequency / (tmpreg1);
break;
}
case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
{
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
{
/* In Case the PLL Source is HSI (Internal Clock) */
vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
@@ -630,19 +641,19 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1);
frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U)) / (tmpreg1);
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
frequency = frequency/(tmpreg1);
frequency = frequency / (tmpreg1);
break;
}
case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
{
/* Configure the PLLI2S division factor */
/* PLL_VCO Input = PLL_SOURCE/PLLM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
{
/* In Case the PLL Source is HSI (Internal Clock) */
vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
@@ -656,17 +667,17 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* PLL_VCO Output = PLL_VCO Input * PLLN */
/* SAI_CLK_x = PLL_VCO Output/PLLR */
tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1);
frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U)) / (tmpreg1);
break;
}
case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
{
frequency = EXTERNAL_CLOCK_VALUE;
break;
}
case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
{
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
{
/* In Case the PLL Source is HSI (Internal Clock) */
frequency = (uint32_t)(HSI_VALUE);
@@ -678,111 +689,32 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
break;
}
default :
default :
{
break;
}
}
break;
}
case RCC_PERIPHCLK_I2S_APB1:
case RCC_PERIPHCLK_I2S_APB1:
{
/* Get the current I2S source */
srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
switch (srcclk)
{
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SAPB1CLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
break;
}
/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
case RCC_I2SAPB1CLKSOURCE_PLLI2S:
{
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
}
else
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
}
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
break;
}
/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
case RCC_I2SAPB1CLKSOURCE_PLLR:
{
/* Configure the PLL division factor R */
/* PLL_VCO Input = PLL_SOURCE/PLLM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
else
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
/* PLL_VCO Output = PLL_VCO Input * PLLN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
/* I2S_CLK = PLL_VCO Output/PLLR */
frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
break;
}
/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
case RCC_I2SAPB1CLKSOURCE_PLLSRC:
{
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
frequency = HSE_VALUE;
}
else
{
frequency = HSI_VALUE;
}
break;
}
/* Clock not enabled for I2S*/
default:
{
frequency = 0U;
break;
}
}
break;
}
case RCC_PERIPHCLK_I2S_APB2:
{
/* Get the current I2S source */
srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
switch (srcclk)
{
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SAPB2CLKSOURCE_EXT:
case RCC_I2SAPB1CLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
break;
}
/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
case RCC_I2SAPB2CLKSOURCE_PLLI2S:
case RCC_I2SAPB1CLKSOURCE_PLLI2S:
{
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
@@ -796,15 +728,15 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
break;
}
/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
case RCC_I2SAPB2CLKSOURCE_PLLR:
case RCC_I2SAPB1CLKSOURCE_PLLR:
{
/* Configure the PLL division factor R */
/* PLL_VCO Input = PLL_SOURCE/PLLM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
@@ -818,13 +750,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* PLL_VCO Output = PLL_VCO Input * PLLN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
/* I2S_CLK = PLL_VCO Output/PLLR */
frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
break;
}
/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
case RCC_I2SAPB2CLKSOURCE_PLLSRC:
case RCC_I2SAPB1CLKSOURCE_PLLSRC:
{
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
frequency = HSE_VALUE;
}
@@ -835,7 +767,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
break;
}
/* Clock not enabled for I2S*/
default:
default:
{
frequency = 0U;
break;
@@ -843,6 +775,89 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
break;
}
case RCC_PERIPHCLK_I2S_APB2:
{
/* Get the current I2S source */
srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
switch (srcclk)
{
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SAPB2CLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
break;
}
/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
case RCC_I2SAPB2CLKSOURCE_PLLI2S:
{
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
}
else
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
}
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
break;
}
/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
case RCC_I2SAPB2CLKSOURCE_PLLR:
{
/* Configure the PLL division factor R */
/* PLL_VCO Input = PLL_SOURCE/PLLM */
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
else
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
/* PLL_VCO Output = PLL_VCO Input * PLLN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
/* I2S_CLK = PLL_VCO Output/PLLR */
frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
break;
}
/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
case RCC_I2SAPB2CLKSOURCE_PLLSRC:
{
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
frequency = HSE_VALUE;
}
else
{
frequency = HSI_VALUE;
}
break;
}
/* Clock not enabled for I2S*/
default:
{
frequency = 0U;
break;
}
}
break;
}
default:
{
break;
}
}
return frequency;
}
@@ -875,7 +890,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*--------------------------- CLK48 Configuration --------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
{
/* Check the parameters */
assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
@@ -886,7 +901,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*------------------------------ SDIO Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
{
/* Check the parameters */
assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
@@ -900,9 +915,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*------------------- Common configuration SAI/I2S -------------------------*/
/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
factor is common parameters for both peripherals */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
@@ -912,9 +927,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -924,20 +939,20 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*---------------------- I2S configuration -------------------------------*/
/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
only for I2S configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
}
/*---------------------------- SAI configuration -------------------------*/
/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
be added only for SAI configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
{
/* Check the PLLI2S division factors */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
@@ -949,20 +964,21 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
{
/* Check for Parameters */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Configure the PLLI2S multiplication and division factors */
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ,
PeriphClkInit->PLLI2S.PLLI2SR);
}
/* Enable the PLLI2S */
@@ -970,9 +986,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -985,10 +1001,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*----------------------- Common configuration SAI/LTDC --------------------*/
/* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division
factor is common parameters for these peripherals */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) &&
(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)))
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) &&
(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)))
{
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
@@ -998,9 +1014,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -1010,7 +1026,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*---------------------------- SAI configuration -------------------------*/
/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
be added only for SAI configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
{
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
@@ -1028,7 +1044,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
/*---------------------------- LTDC configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
{
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
@@ -1047,8 +1063,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*---------------------------- CLK48 configuration ------------------------*/
/* Configure the PLLSAI when it is used as clock source for CLK48 */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) &&
(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) &&
(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
{
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
@@ -1067,9 +1083,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -1080,7 +1096,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*---------------------------- RTC configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
@@ -1094,16 +1110,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
while((PWR->CR & PWR_CR_DBP) == RESET)
while ((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
@@ -1114,15 +1130,15 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
RCC->BDCR = tmpreg1;
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
{
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -1134,7 +1150,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*---------------------------- TIM configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
{
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
}
@@ -1153,9 +1169,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
uint32_t tempreg;
/* Set all possible values for the extended clock type parameter------------*/
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI |\
RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC |\
RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | \
RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | \
RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC | \
RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO;
/* Get the PLLI2S Clock configuration --------------------------------------*/
@@ -1174,7 +1190,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
/* Get the CLK48 clock configuration -------------------------------------*/
/* Get the CLK48 clock configuration -------------------------------------*/
PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
/* Get the SDIO clock configuration ----------------------------------------*/
@@ -1209,25 +1225,25 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
uint32_t vcooutput = 0U;
switch (PeriphClk)
{
case RCC_PERIPHCLK_I2S:
case RCC_PERIPHCLK_I2S:
{
/* Get the current I2S source */
srcclk = __HAL_RCC_GET_I2S_SOURCE();
switch (srcclk)
{
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SCLKSOURCE_EXT:
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SCLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
break;
}
/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
case RCC_I2SCLKSOURCE_PLLI2S:
/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
case RCC_I2SCLKSOURCE_PLLI2S:
{
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
@@ -1241,11 +1257,11 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
break;
}
/* Clock not enabled for I2S*/
default:
default:
{
frequency = 0U;
break;
@@ -1253,6 +1269,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
break;
}
default:
{
break;
}
}
return frequency;
}
@@ -1286,7 +1306,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*----------------------------------- I2S APB1 configuration ---------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
{
/* Check the parameters */
assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
@@ -1294,7 +1314,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure I2S Clock source */
__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
{
plli2sused = 1U;
}
@@ -1302,7 +1322,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*----------------------------------- I2S APB2 configuration ---------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
{
/* Check the parameters */
assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
@@ -1310,7 +1330,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure I2S Clock source */
__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
{
plli2sused = 1U;
}
@@ -1319,7 +1339,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
#if defined(STM32F413xx) || defined(STM32F423xx)
/*----------------------- SAI1 Block A configuration -----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA))
{
/* Check the parameters */
assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection));
@@ -1327,12 +1347,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure SAI1 Clock source */
__HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection);
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)
if (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)
{
plli2sused = 1U;
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR)
if (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR)
{
/* Check for PLL/DIVR parameters */
assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
@@ -1344,7 +1364,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*---------------------- SAI1 Block B configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB))
{
/* Check the parameters */
assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection));
@@ -1352,12 +1372,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure SAI1 Clock source */
__HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection);
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)
if (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)
{
plli2sused = 1U;
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR)
if (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR)
{
/* Check for PLL/DIVR parameters */
assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
@@ -1370,7 +1390,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
#endif /* STM32F413xx || STM32F423xx */
/*------------------------------------ RTC configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
@@ -1384,16 +1404,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
while((PWR->CR & PWR_CR_DBP) == RESET)
while ((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
@@ -1404,15 +1424,15 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
RCC->BDCR = tmpreg1;
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
{
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -1424,7 +1444,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*------------------------------------ TIM configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
{
/* Configure Timer Prescaler */
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
@@ -1432,7 +1452,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*------------------------------------- FMPI2C1 Configuration --------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
{
/* Check the parameters */
assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
@@ -1443,7 +1463,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*------------------------------------- CLK48 Configuration ----------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
{
/* Check the parameters */
assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
@@ -1452,7 +1472,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
/* Enable the PLLI2S when it's used as clock source for CLK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)
if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)
{
plli2sused = 1U;
}
@@ -1460,7 +1480,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*------------------------------------- SDIO Configuration -----------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
{
/* Check the parameters */
assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
@@ -1473,16 +1493,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*-------------------------------------- PLLI2S Configuration --------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or
I2S on APB2*/
if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
{
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -1497,10 +1517,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
__HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection);
/*------- In Case of PLLI2S is selected as source clock for I2S ----------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)))
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1)
&& (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
@@ -1509,13 +1530,15 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ,
PeriphClkInit->PLLI2S.PLLI2SR);
}
#if defined(STM32F413xx) || defined(STM32F423xx)
/*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)))
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA)
&& (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)))
{
/* Check for PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
@@ -1528,7 +1551,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq,
PeriphClkInit->PLLI2S.PLLI2SR);
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */
__HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR);
@@ -1536,7 +1560,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
#endif /* STM32F413xx || STM32F423xx */
/*----------------- In Case of PLLI2S is just selected ------------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
{
/* Check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
@@ -1545,7 +1569,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ,
PeriphClkInit->PLLI2S.PLLI2SR);
}
/* Enable the PLLI2S */
@@ -1553,9 +1578,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -1565,7 +1590,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*-------------------- DFSDM1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
@@ -1576,7 +1601,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*-------------------- DFSDM1 Audio clock source configuration -------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
@@ -1588,7 +1613,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
#if defined(STM32F413xx) || defined(STM32F423xx)
/*-------------------- DFSDM2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
@@ -1599,7 +1624,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*-------------------- DFSDM2 Audio clock source configuration -------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2_AUDIO) == RCC_PERIPHCLK_DFSDM2_AUDIO)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2_AUDIO) == RCC_PERIPHCLK_DFSDM2_AUDIO)
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM2AUDIOCLKSOURCE(PeriphClkInit->Dfsdm2AudioClockSelection));
@@ -1610,7 +1635,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*---------------------------- LPTIM1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
@@ -1637,18 +1662,18 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
/* Set all possible values for the extended clock type parameter------------*/
#if defined(STM32F413xx) || defined(STM32F423xx)
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_CLK48 |\
RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 |\
RCC_PERIPHCLK_DFSDM1_AUDIO | RCC_PERIPHCLK_DFSDM2 |\
RCC_PERIPHCLK_DFSDM2_AUDIO | RCC_PERIPHCLK_LPTIM1 |\
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 | \
RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC | \
RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_CLK48 | \
RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 | \
RCC_PERIPHCLK_DFSDM1_AUDIO | RCC_PERIPHCLK_DFSDM2 | \
RCC_PERIPHCLK_DFSDM2_AUDIO | RCC_PERIPHCLK_LPTIM1 | \
RCC_PERIPHCLK_SAIA | RCC_PERIPHCLK_SAIB;
#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_CLK48 |\
RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 |\
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 | \
RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC | \
RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_CLK48 | \
RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 | \
RCC_PERIPHCLK_DFSDM1_AUDIO;
#endif /* STM32F413xx || STM32F423xx */
@@ -1738,23 +1763,23 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
uint32_t vcooutput = 0U;
switch (PeriphClk)
{
case RCC_PERIPHCLK_I2S_APB1:
case RCC_PERIPHCLK_I2S_APB1:
{
/* Get the current I2S source */
srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
switch (srcclk)
{
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SAPB1CLKSOURCE_EXT:
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SAPB1CLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
break;
}
/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
case RCC_I2SAPB1CLKSOURCE_PLLI2S:
/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
case RCC_I2SAPB1CLKSOURCE_PLLI2S:
{
if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
if ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
@@ -1763,7 +1788,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
@@ -1777,15 +1802,15 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
break;
}
/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
case RCC_I2SAPB1CLKSOURCE_PLLR:
/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
case RCC_I2SAPB1CLKSOURCE_PLLR:
{
/* Configure the PLL division factor R */
/* PLL_VCO Input = PLL_SOURCE/PLLM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
@@ -1799,13 +1824,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* PLL_VCO Output = PLL_VCO Input * PLLN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
/* I2S_CLK = PLL_VCO Output/PLLR */
frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
break;
}
/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
case RCC_I2SAPB1CLKSOURCE_PLLSRC:
/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
case RCC_I2SAPB1CLKSOURCE_PLLSRC:
{
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
frequency = HSE_VALUE;
}
@@ -1816,7 +1841,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
break;
}
/* Clock not enabled for I2S*/
default:
default:
{
frequency = 0U;
break;
@@ -1824,23 +1849,23 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
break;
}
case RCC_PERIPHCLK_I2S_APB2:
case RCC_PERIPHCLK_I2S_APB2:
{
/* Get the current I2S source */
srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
switch (srcclk)
{
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SAPB2CLKSOURCE_EXT:
case RCC_I2SAPB2CLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
break;
}
/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
case RCC_I2SAPB2CLKSOURCE_PLLI2S:
case RCC_I2SAPB2CLKSOURCE_PLLI2S:
{
if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
if ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
@@ -1849,7 +1874,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
@@ -1863,15 +1888,15 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
break;
}
/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
case RCC_I2SAPB2CLKSOURCE_PLLR:
case RCC_I2SAPB2CLKSOURCE_PLLR:
{
/* Configure the PLL division factor R */
/* PLL_VCO Input = PLL_SOURCE/PLLM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
@@ -1885,13 +1910,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* PLL_VCO Output = PLL_VCO Input * PLLN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
/* I2S_CLK = PLL_VCO Output/PLLR */
frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
break;
}
/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
case RCC_I2SAPB2CLKSOURCE_PLLSRC:
case RCC_I2SAPB2CLKSOURCE_PLLSRC:
{
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
frequency = HSE_VALUE;
}
@@ -1901,8 +1926,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
break;
}
/* Clock not enabled for I2S*/
default:
/* Clock not enabled for I2S*/
default:
{
frequency = 0U;
break;
@@ -1910,6 +1935,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
break;
}
default:
{
break;
}
}
return frequency;
}
@@ -1937,7 +1966,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*---------------------------- RTC configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
@@ -1951,16 +1980,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
while((PWR->CR & PWR_CR_DBP) == RESET)
while ((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
@@ -1971,15 +2000,15 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
RCC->BDCR = tmpreg1;
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
{
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -1991,14 +2020,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*---------------------------- TIM configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
{
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
}
/*--------------------------------------------------------------------------*/
/*---------------------------- FMPI2C1 Configuration -----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
{
/* Check the parameters */
assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
@@ -2009,7 +2038,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*---------------------------- LPTIM1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
@@ -2019,7 +2048,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
/*---------------------------- I2S Configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
{
/* Check the parameters */
assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));
@@ -2083,25 +2112,25 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
uint32_t vcooutput = 0U;
switch (PeriphClk)
{
case RCC_PERIPHCLK_I2S:
case RCC_PERIPHCLK_I2S:
{
/* Get the current I2S source */
srcclk = __HAL_RCC_GET_I2S_SOURCE();
switch (srcclk)
{
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SAPBCLKSOURCE_EXT:
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SAPBCLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
break;
}
/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
case RCC_I2SAPBCLKSOURCE_PLLR:
/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
case RCC_I2SAPBCLKSOURCE_PLLR:
{
/* Configure the PLL division factor R */
/* PLL_VCO Input = PLL_SOURCE/PLLM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
@@ -2115,13 +2144,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* PLL_VCO Output = PLL_VCO Input * PLLN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
/* I2S_CLK = PLL_VCO Output/PLLR */
frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
break;
}
/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
case RCC_I2SAPBCLKSOURCE_PLLSRC:
/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
case RCC_I2SAPBCLKSOURCE_PLLSRC:
{
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
frequency = HSE_VALUE;
}
@@ -2132,7 +2161,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
break;
}
/* Clock not enabled for I2S*/
default:
default:
{
frequency = 0U;
break;
@@ -2140,6 +2169,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
break;
}
default:
{
break;
}
}
return frequency;
}
@@ -2172,9 +2205,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*----------------------- Common configuration SAI/I2S ---------------------*/
/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
factor is common parameters for both peripherals */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
@@ -2184,9 +2217,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -2196,20 +2229,20 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*---------------------------- I2S configuration -------------------------*/
/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
only for I2S configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
}
/*---------------------------- SAI configuration -------------------------*/
/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
be added only for SAI configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
{
/* Check the PLLI2S division factors */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
@@ -2221,20 +2254,21 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
{
/* Check for Parameters */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Configure the PLLI2S multiplication and division factors */
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ,
PeriphClkInit->PLLI2S.PLLI2SR);
}
/* Enable the PLLI2S */
@@ -2242,9 +2276,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -2257,8 +2291,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*----------------------- Common configuration SAI/LTDC --------------------*/
/* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
factor is common parameters for both peripherals */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
{
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
@@ -2268,9 +2302,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -2280,7 +2314,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*---------------------------- SAI configuration -------------------------*/
/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
be added only for SAI configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
{
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
@@ -2290,13 +2324,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
}
/*---------------------------- LTDC configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
{
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
@@ -2306,7 +2340,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
}
@@ -2315,9 +2349,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -2327,7 +2361,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*---------------------------- RTC configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
@@ -2341,16 +2375,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
while((PWR->CR & PWR_CR_DBP) == RESET)
while ((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
@@ -2361,15 +2395,15 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
RCC->BDCR = tmpreg1;
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
{
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -2381,7 +2415,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*--------------------------------------------------------------------------*/
/*---------------------------- TIM configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
{
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
}
@@ -2447,25 +2481,25 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
uint32_t vcooutput = 0U;
switch (PeriphClk)
{
case RCC_PERIPHCLK_I2S:
case RCC_PERIPHCLK_I2S:
{
/* Get the current I2S source */
srcclk = __HAL_RCC_GET_I2S_SOURCE();
switch (srcclk)
{
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SCLKSOURCE_EXT:
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SCLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
break;
}
/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
case RCC_I2SCLKSOURCE_PLLI2S:
/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
case RCC_I2SCLKSOURCE_PLLI2S:
{
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
@@ -2479,11 +2513,11 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
break;
}
/* Clock not enabled for I2S*/
default:
default:
{
frequency = 0U;
break;
@@ -2491,6 +2525,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
break;
}
default:
{
break;
}
}
return frequency;
}
@@ -2519,8 +2557,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*---------------------------- I2S configuration ---------------------------*/
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
@@ -2533,9 +2571,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -2546,12 +2584,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
__HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN,
PeriphClkInit->PLLI2S.PLLI2SR);
#else
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
#endif /* STM32F411xE */
/* Enable the PLLI2S */
@@ -2559,9 +2598,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -2570,7 +2609,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
/*---------------------------- RTC configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
@@ -2584,16 +2623,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Get tick */
tickstart = HAL_GetTick();
while((PWR->CR & PWR_CR_DBP) == RESET)
while ((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
@@ -2604,15 +2643,15 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
RCC->BDCR = tmpreg1;
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
{
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -2623,7 +2662,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
/*---------------------------- TIM configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
{
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
}
@@ -2687,26 +2726,26 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
uint32_t vcooutput = 0U;
switch (PeriphClk)
{
case RCC_PERIPHCLK_I2S:
case RCC_PERIPHCLK_I2S:
{
/* Get the current I2S source */
srcclk = __HAL_RCC_GET_I2S_SOURCE();
switch (srcclk)
{
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SCLKSOURCE_EXT:
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SCLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
break;
}
/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
case RCC_I2SCLKSOURCE_PLLI2S:
/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
case RCC_I2SCLKSOURCE_PLLI2S:
{
#if defined(STM32F411xE)
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
@@ -2719,7 +2758,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
#else
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
@@ -2733,11 +2772,11 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
break;
}
/* Clock not enabled for I2S*/
default:
default:
{
frequency = 0U;
break;
@@ -2745,6 +2784,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
break;
}
default:
{
break;
}
}
return frequency;
}
@@ -2767,7 +2810,7 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
{
/* Check the parameters */
assert_param(IS_RCC_LSE_MODE(Mode));
if(Mode == RCC_LSE_HIGHDRIVE_MODE)
if (Mode == RCC_LSE_HIGHDRIVE_MODE)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
}
@@ -2780,14 +2823,14 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
* @brief Extended Clock management functions
*
@verbatim
* @brief Extended Clock management functions
*
@verbatim
===============================================================================
##### Extended clock management functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the
This subsection provides a set of functions allowing to control the
activation or deactivation of PLLI2S, PLLSAI.
@endverbatim
* @{
@@ -2822,9 +2865,9 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
/* Wait till PLLI2S is disabled */
tickstart = HAL_GetTick();
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -2867,16 +2910,16 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
/* Wait till PLLI2S is ready */
tickstart = HAL_GetTick();
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
}
}
return HAL_OK;
return HAL_OK;
}
/**
@@ -2892,9 +2935,9 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
/* Wait till PLLI2S is disabled */
tickstart = HAL_GetTick();
while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -2935,9 +2978,9 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit)
/* Wait till PLLSAI is disabled */
tickstart = HAL_GetTick();
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -2971,16 +3014,16 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit)
/* Wait till PLLSAI is ready */
tickstart = HAL_GetTick();
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
}
}
return HAL_OK;
return HAL_OK;
}
/**
@@ -2996,9 +3039,9 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)
/* Wait till PLLSAI is disabled */
tickstart = HAL_GetTick();
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
@@ -3062,7 +3105,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
break;
break;
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
@@ -3074,19 +3117,19 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U);
sysclockfreq = pllvco/pllp;
sysclockfreq = pllvco / pllp;
break;
}
case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
@@ -3094,19 +3137,19 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
sysclockfreq = pllvco/pllr;
sysclockfreq = pllvco / pllr;
break;
}
default:
@@ -3282,7 +3325,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
#endif /* RCC_CIR_PLLSAIRDYIE */
/* Clear all interrupt flags */
SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);
SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC |
RCC_CIR_CSSC);
#if defined(RCC_CIR_PLLI2SRDYC)
SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
@@ -3302,7 +3346,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
SystemCoreClock = HSI_VALUE;
/* Adapt Systick interrupt period */
if(HAL_InitTick(uwTickPrio) != HAL_OK)
if (HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
}
@@ -3330,12 +3374,13 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
* is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
{
uint32_t tickstart, pll_config;
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
if (RCC_OscInitStruct == NULL)
{
return HAL_ERROR;
}
@@ -3343,21 +3388,23 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
#if defined(STM32F446xx)
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|| \
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
#else
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|| \
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
#endif /* STM32F446xx */
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
{
return HAL_ERROR;
}
@@ -3368,15 +3415,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -3388,9 +3435,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -3399,7 +3446,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
{
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
@@ -3407,16 +3454,18 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
#if defined(STM32F446xx)
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
|| \
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
#else
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
|| \
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
#endif /* STM32F446xx */
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
{
return HAL_ERROR;
}
@@ -3430,7 +3479,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
@@ -3439,9 +3488,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -3459,9 +3508,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -3470,13 +3519,13 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
@@ -3485,9 +3534,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -3502,9 +3551,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -3512,7 +3561,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
FlagStatus pwrclkchanged = RESET;
@@ -3521,13 +3570,13 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
{
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
@@ -3535,9 +3584,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -3547,15 +3596,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -3567,9 +3616,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -3577,7 +3626,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
if (pwrclkchanged == SET)
{
__HAL_RCC_PWR_CLK_DISABLE();
}
@@ -3588,9 +3637,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
{
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
@@ -3607,9 +3656,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -3629,9 +3678,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -3646,9 +3695,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -3658,7 +3707,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
{
return HAL_ERROR;
}
@@ -3681,7 +3730,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
#endif
#endif /* RCC_PLLCFGR_PLLR */
{
return HAL_ERROR;
}
@@ -3706,11 +3755,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
/* Get the HSE configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
{
RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
}
else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
{
RCC_OscInitStruct->HSEState = RCC_HSE_ON;
}
@@ -3720,7 +3769,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Get the HSI configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
{
RCC_OscInitStruct->HSIState = RCC_HSI_ON;
}
@@ -3729,14 +3778,14 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
/* Get the LSE configuration -----------------------------------------------*/
if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
{
RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
}
else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
{
RCC_OscInitStruct->LSEState = RCC_LSE_ON;
}
@@ -3746,7 +3795,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Get the LSI configuration -----------------------------------------------*/
if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
{
RCC_OscInitStruct->LSIState = RCC_LSI_ON;
}
@@ -3756,7 +3805,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Get the PLL configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
{
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
}

29
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c
View File

@@ -52,7 +52,7 @@
[..]
Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
weak (overridden) function.
HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -66,10 +66,10 @@
[..]
By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
all callbacks are set to the corresponding weak (overridden) functions:
example HAL_RNG_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are respectively
reset to the legacy weak (surcharged) functions in the HAL_RNG_Init()
reset to the legacy weak (overridden) functions in the HAL_RNG_Init()
and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -86,7 +86,7 @@
[..]
When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
and weak (surcharged) callbacks are used.
and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -307,8 +307,6 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hrng);
if (HAL_RNG_STATE_READY == hrng->State)
{
@@ -362,8 +360,6 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hrng);
return status;
}
@@ -382,8 +378,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hrng);
if (HAL_RNG_STATE_READY == hrng->State)
{
@@ -437,8 +431,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hrng);
return status;
}
@@ -697,15 +689,16 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
{
uint32_t rngclockerror = 0U;
uint32_t itflag = hrng->Instance->SR;
/* RNG clock error interrupt occurred */
if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
if ((itflag & RNG_IT_CEI) == RNG_IT_CEI)
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
rngclockerror = 1U;
}
else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI)
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_SEED;
@@ -736,7 +729,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
}
/* Check RNG data ready interrupt occurred */
if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY)
{
/* Generate random number once, so disable the IT */
__HAL_RNG_DISABLE_IT(hrng);
@@ -768,7 +761,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
* the configuration information for RNG.
* @retval random value
*/
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng)
{
return (hrng->RandomNumber);
}
@@ -830,7 +823,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
* the configuration information for RNG.
* @retval HAL state
*/
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng)
{
return hrng->State;
}
@@ -840,7 +833,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
* @param hrng: pointer to a RNG_HandleTypeDef structure.
* @retval RNG Error Code
*/
uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng)
{
/* Return RNG Error Code */
return hrng->ErrorCode;

218
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c
View File

@@ -6,15 +6,15 @@
* This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral:
* + Initialization and de-initialization functions
* + RTC Calendar (Time and Date) configuration functions
* + RTC Alarms (Alarm A and Alarm B) configuration functions
* + Calendar (Time and Date) configuration functions
* + Alarms (Alarm A and Alarm B) configuration functions
* + Peripheral Control functions
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -124,6 +124,12 @@
*** Callback registration ***
=============================================
[..]
When the compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all
callbacks are set to the corresponding weak functions.
This is the recommended configuration in order to optimize memory/code
consumption footprint/performances.
[..]
The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.
@@ -134,9 +140,11 @@
(+) TimeStampEventCallback : RTC Timestamp Event callback.
(+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
(+) Tamper1EventCallback : RTC Tamper 1 Event callback.
(+) Tamper2EventCallback : RTC Tamper 2 Event callback.
(+) Tamper2EventCallback : RTC Tamper 2 Event callback. (*)
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
(*) value not applicable to all devices.
[..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
@@ -151,31 +159,29 @@
(+) TimeStampEventCallback : RTC Timestamp Event callback.
(+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
(+) Tamper1EventCallback : RTC Tamper 1 Event callback.
(+) Tamper2EventCallback : RTC Tamper 2 Event callback.
(+) Tamper2EventCallback : RTC Tamper 2 Event callback. (*)
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
(*) value not applicable to all devices.
[..]
By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
all callbacks are set to the corresponding weak functions:
examples AlarmAEventCallback(), WakeUpTimerEventCallback().
examples AlarmAEventCallback(), TimeStampEventCallback().
Exception done for MspInit() and MspDeInit() callbacks that are reset to the
legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only
when these callbacks are null (not registered beforehand).
legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these
callbacks are null (not registered beforehand).
If not, MspInit() or MspDeInit() are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
keep and use the user MspInit()/MspDeInit() callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
Exception done MspInit()/MspDeInit() that can be registered/unregistered
Exception done for MspInit() and MspDeInit() that can be registered/unregistered
in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state.
Thus registered (user) MspInit()/MspDeInit() callbacks can be used during the
Init/DeInit.
In that case first register the MspInit()/MspDeInit() user callbacks
using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
or HAL_RTC_Init() functions.
[..]
When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all
callbacks are set to the corresponding weak functions.
In that case first register the MspInit()/MspDeInit() user callbacks using
HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() or HAL_RTC_Init()
functions.
@endverbatim
******************************************************************************
@@ -248,7 +254,7 @@
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
HAL_StatusTypeDef status = HAL_ERROR;
HAL_StatusTypeDef status;
/* Check RTC handler validity */
if (hrtc == NULL)
@@ -306,38 +312,50 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Enter Initialization mode */
status = RTC_EnterInitMode(hrtc);
if (status == HAL_OK)
/* Check whether the calendar needs to be initialized */
if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
{
/* Clear RTC_CR FMT, OSEL and POL Bits */
hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
/* Set RTC_CR register */
hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Configure the RTC PRER */
hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
/* Enter Initialization mode */
status = RTC_EnterInitMode(hrtc);
/* Exit Initialization mode */
status = RTC_ExitInitMode(hrtc);
if (status == HAL_OK)
{
/* Clear RTC_CR FMT, OSEL and POL Bits */
hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
/* Set RTC_CR register */
hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
/* Configure the RTC PRER */
hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
/* Exit Initialization mode */
status = RTC_ExitInitMode(hrtc);
}
if (status == HAL_OK)
{
hrtc->Instance->TAFCR &= (uint32_t)~RTC_OUTPUT_TYPE_PUSHPULL;
hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
else
{
/* The calendar is already initialized */
status = HAL_OK;
}
if (status == HAL_OK)
{
hrtc->Instance->TAFCR &= (uint32_t)~RTC_OUTPUT_TYPE_PUSHPULL;
hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
hrtc->State = HAL_RTC_STATE_READY;
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
return status;
}
@@ -350,7 +368,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
*/
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
{
HAL_StatusTypeDef status = HAL_ERROR;
HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
@@ -369,10 +387,10 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
/* Reset RTC registers */
hrtc->Instance->TR = 0x00000000U;
hrtc->Instance->DR = (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0);
hrtc->Instance->CR &= 0x00000000U;
hrtc->Instance->CR = 0x00000000U;
hrtc->Instance->WUTR = RTC_WUTR_WUT;
hrtc->Instance->PRER = (uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU);
hrtc->Instance->CALIBR = 0x00000000U;
hrtc->Instance->CALIBR = 0x00000000U;
hrtc->Instance->ALRMAR = 0x00000000U;
hrtc->Instance->ALRMBR = 0x00000000U;
hrtc->Instance->CALR = 0x00000000U;
@@ -426,11 +444,12 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
* @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
* @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID
* @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID
* @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
* @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
* @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
* @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
* @note HAL_RTC_TAMPER2_EVENT_CB_ID is not applicable to all devices.
* @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Event Callback ID
* @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Event Callback ID (*)
* @arg @ref HAL_RTC_MSPINIT_CB_ID MSP Init callback ID
* @arg @ref HAL_RTC_MSPDEINIT_CB_ID MSP DeInit callback ID
*
* (*) value not applicable to all devices.
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
@@ -522,7 +541,7 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call
/**
* @brief Unregisters an RTC Callback
* RTC callabck is redirected to the weak predefined callback
* RTC callback is redirected to the weak predefined callback
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param CallbackID ID of the callback to be unregistered
@@ -531,11 +550,12 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call
* @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
* @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID
* @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID
* @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
* @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
* @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
* @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
* @note HAL_RTC_TAMPER2_EVENT_CB_ID is not applicable to all devices.
* @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Event Callback ID
* @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Event Callback ID (*)
* @arg @ref HAL_RTC_MSPINIT_CB_ID MSP Init callback ID
* @arg @ref HAL_RTC_MSPDEINIT_CB_ID MSP DeInit callback ID
*
* (*) value not applicable to all devices.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
@@ -1038,7 +1058,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
@@ -1071,7 +1091,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
((uint32_t) sAlarm->AlarmTime.Seconds) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
((uint32_t) sAlarm->AlarmDateWeekDaySel) | \
((uint32_t) sAlarm->AlarmMask));
@@ -1084,16 +1104,15 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Configure the Alarm register */
if (sAlarm->Alarm == RTC_ALARM_A)
{
/* Disable the Alarm A */
/* Disable Alarm A */
__HAL_RTC_ALARMA_DISABLE(hrtc);
/* In case interrupt mode is used, the interrupt source must be disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
/* Clear the Alarm flag */
/* Clear Alarm A flag */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
/* Get tick */
@@ -1116,21 +1135,22 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
}
}
/* Configure Alarm A register */
hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
/* Configure the Alarm A Subseconds register */
/* Configure Alarm A Subseconds register */
hrtc->Instance->ALRMASSR = subsecondtmpreg;
/* Configure the Alarm state: Enable Alarm */
/* Enable Alarm A */
__HAL_RTC_ALARMA_ENABLE(hrtc);
}
else
{
/* Disable the Alarm B */
/* Disable Alarm B */
__HAL_RTC_ALARMB_DISABLE(hrtc);
/* In case interrupt mode is used, the interrupt source must be disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
/* Clear the Alarm flag */
/* Clear Alarm B flag */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
/* Get tick */
@@ -1153,10 +1173,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
}
}
/* Configure Alarm B register */
hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
/* Configure the Alarm B Subseconds register */
/* Configure Alarm B Subseconds register */
hrtc->Instance->ALRMBSSR = subsecondtmpreg;
/* Configure the Alarm state: Enable Alarm */
/* Enable Alarm B */
__HAL_RTC_ALARMB_ENABLE(hrtc);
}
@@ -1235,7 +1256,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
@@ -1268,7 +1289,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
((uint32_t) sAlarm->AlarmTime.Seconds) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
((uint32_t) sAlarm->AlarmDateWeekDaySel) | \
((uint32_t) sAlarm->AlarmMask));
@@ -1281,19 +1302,19 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Configure the Alarm register */
if (sAlarm->Alarm == RTC_ALARM_A)
{
/* Disable the Alarm A */
/* Disable Alarm A */
__HAL_RTC_ALARMA_DISABLE(hrtc);
/* Clear the Alarm flag */
/* Clear Alarm A flag */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
/* Wait till RTC ALRAWF flag is set and if timeout is reached exit */
do
{
if (count-- == 0U)
count = count - 1U;
if (count == 0U)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1307,20 +1328,21 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
}
} while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U);
/* Configure Alarm A register */
hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
/* Configure the Alarm A Subseconds register */
/* Configure Alarm A Subseconds register */
hrtc->Instance->ALRMASSR = subsecondtmpreg;
/* Configure the Alarm state: Enable Alarm */
/* Enable Alarm A */
__HAL_RTC_ALARMA_ENABLE(hrtc);
/* Configure the Alarm interrupt */
/* Enable Alarm A interrupt */
__HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA);
}
else
{
/* Disable the Alarm B */
/* Disable Alarm B */
__HAL_RTC_ALARMB_DISABLE(hrtc);
/* Clear the Alarm flag */
/* Clear Alarm B flag */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
/* Reload the counter */
@@ -1329,7 +1351,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
/* Wait till RTC ALRBWF flag is set and if timeout is reached exit */
do
{
if (count-- == 0U)
count = count - 1U;
if (count == 0U)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1343,16 +1366,17 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
}
} while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U);
/* Configure Alarm B register */
hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
/* Configure the Alarm B Subseconds register */
/* Configure Alarm B Subseconds register */
hrtc->Instance->ALRMBSSR = subsecondtmpreg;
/* Configure the Alarm state: Enable Alarm */
/* Enable Alarm B */
__HAL_RTC_ALARMB_ENABLE(hrtc);
/* Configure the Alarm interrupt */
/* Enable Alarm B interrupt */
__HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
}
/* RTC Alarm Interrupt Configuration: EXTI configuration */
/* Enable and configure the EXTI line associated to the RTC Alarm interrupt */
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
@@ -1404,7 +1428,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC ALRxWF flag is set and if timeout is reached exit */
/* Wait till RTC ALRAWF flag is set and if timeout is reached exit */
while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
@@ -1432,7 +1456,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC ALRxWF flag is set and if timeout is reached exit */
/* Wait till RTC ALRBWF flag is set and if timeout is reached exit */
while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
@@ -1529,21 +1553,24 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
*/
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
{
/* Clear the EXTI flag associated to the RTC Alarm interrupt */
__HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
/* Get the Alarm A interrupt source enable status */
if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U)
{
/* Get the pending status of the Alarm A Interrupt */
if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U)
{
/* Clear the Alarm A interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
/* Alarm A callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->AlarmAEventCallback(hrtc);
#else
HAL_RTC_AlarmAEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Alarm A interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
}
}
@@ -1553,21 +1580,18 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
/* Get the pending status of the Alarm B Interrupt */
if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U)
{
/* Clear the Alarm B interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
/* Alarm B callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->AlarmBEventCallback(hrtc);
#else
HAL_RTCEx_AlarmBEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Alarm B interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
}
}
/* Clear the EXTI's line Flag for RTC Alarm */
__HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
@@ -1663,8 +1687,8 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart = 0U;
/* Clear RSF flag */
hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
/* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */
hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK));
/* Get tick */
tickstart = HAL_GetTick();
@@ -1859,7 +1883,7 @@ HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
*/
uint8_t RTC_ByteToBcd2(uint8_t number)
{
uint8_t bcdhigh = 0U;
uint32_t bcdhigh = 0U;
while (number >= 10U)
{
@@ -1877,9 +1901,9 @@ uint8_t RTC_ByteToBcd2(uint8_t number)
*/
uint8_t RTC_Bcd2ToByte(uint8_t number)
{
uint8_t tmp = 0U;
tmp = ((uint8_t)(number & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
return (tmp + (number & (uint8_t)0x0F));
uint32_t tens = 0U;
tens = (((uint32_t)number & 0xF0U) >> 4U) * 10U;
return (uint8_t)(tens + ((uint32_t)number & 0x0FU));
}
/**

76
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c
View File

@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -59,7 +59,7 @@
*** Tamper configuration ***
============================
[..]
(+) To Enable the RTC Tamper and configure the Tamper filter count, trigger
(+) To enable the RTC Tamper and configure the Tamper filter count, trigger
Edge or Level according to the Tamper filter value (if equal to 0 Edge
else Level), sampling frequency, precharge or discharge and Pull-UP use
the HAL_RTCEx_SetTamper() function.
@@ -99,8 +99,8 @@
0 to 62.
(+) In order to measure the clock deviation, a 512 Hz clock is output for
calibration.
(+) The RTC Coarse Digital Calibration value and sign can be calibrated using
the HAL_RTCEx_SetCoarseCalib() function.
(+) To configure the RTC Coarse Digital Calibration value and sign use the
HAL_RTCEx_SetCoarseCalib() function.
*** Smooth Digital Calibration configuration ***
================================================
@@ -114,9 +114,9 @@
This cycle is maintained by a 20-bit counter clocked by RTCCLK.
(+) The smooth calibration register (RTC_CALR) specifies the number of RTCCLK
clock cycles to be masked during the 32-second cycle.
(+) The RTC Smooth Digital Calibration value and the corresponding calibration
cycle period (32s, 16s, or 8s) can be calibrated using the
HAL_RTCEx_SetSmoothCalib() function.
(+) To configure the RTC Smooth Digital Calibration value and the corresponding
calibration cycle period (32s,16s and 8s) use the HAL_RTCEx_SetSmoothCalib()
function.
@endverbatim
******************************************************************************
@@ -299,7 +299,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t RT
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* RTC Timestamp Interrupt Configuration: EXTI configuration */
/* Enable and configure the EXTI line associated to the RTC Timestamp and Tamper interrupts */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
@@ -330,7 +330,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
/* In case interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
/* Get the RTC_CR register and clear the bits to be configured */
@@ -553,7 +553,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
/* Copy desired configuration into configuration register */
hrtc->Instance->TAFCR = tmpreg;
/* RTC Tamper Interrupt Configuration: EXTI configuration */
/* Enable and configure the EXTI line associated to the RTC Timestamp and Tamper interrupts */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
@@ -573,8 +573,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
* @param Tamper Selected tamper pin.
* This parameter can be any combination of the following values:
* @arg RTC_TAMPER_1: Tamper 1
* @arg RTC_TAMPER_2: Tamper 2
* @note RTC_TAMPER_2 is not applicable to all devices.
* @arg RTC_TAMPER_2: Tamper 2 (*)
*
* (*) value not applicable to all devices.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
@@ -605,6 +606,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
{
/* Clear the EXTI flag associated to the RTC Timestamp and Tamper interrupts */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
/* Get the Timestamp interrupt source enable status */
if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U)
{
@@ -618,7 +622,8 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
HAL_RTCEx_TimeStampEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Timestamp interrupt pending bit */
/* Clear the Timestamp interrupt pending bit after returning from callback
as RTC_TSTR and RTC_TSDR registers are cleared when TSF bit is reset */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
}
}
@@ -629,15 +634,15 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
/* Get the pending status of the Tamper 1 Interrupt */
if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U)
{
/* Clear the Tamper interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
/* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->Tamper1EventCallback(hrtc);
#else
HAL_RTCEx_Tamper1EventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Tamper interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
}
}
@@ -648,22 +653,19 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
/* Get the pending status of the Tamper 2 Interrupt */
if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U)
{
/* Clear the Tamper interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
/* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->Tamper2EventCallback(hrtc);
#else
HAL_RTCEx_Tamper2EventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Tamper interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
}
}
#endif /* RTC_TAMPER2_SUPPORT */
/* Clear the EXTI's Flag for RTC Timestamp and Tamper */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
@@ -979,7 +981,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
/* Wait till RTC WUTWF flag is reset and if timeout is reached exit */
do
{
if (count-- == 0U)
count = count - 1U;
if (count == 0U)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1006,7 +1009,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
/* Wait till RTC WUTWF flag is set and if timeout is reached exit */
do
{
if (count-- == 0U)
count = count - 1U;
if (count == 0U)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1029,7 +1033,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
/* Configure the Wakeup Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
/* RTC wakeup timer Interrupt Configuration: EXTI configuration */
/* Enable and configure the EXTI line associated to the RTC Wakeup Timer interrupt */
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
@@ -1071,7 +1075,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
/* Disable the Wakeup Timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
/* In case interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT);
/* Get tick */
@@ -1130,23 +1134,23 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
{
/* Clear the EXTI flag associated to the RTC Wakeup Timer interrupt */
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
/* Get the pending status of the Wakeup timer Interrupt */
if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U)
{
/* Clear the Wakeup timer interrupt pending bit */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
/* Wakeup timer callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->WakeUpTimerEventCallback(hrtc);
#else
HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Wakeup timer interrupt pending bit */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
}
/* Clear the EXTI's line Flag for RTC WakeUpTimer */
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
@@ -1249,7 +1253,7 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
tmp = (uint32_t) & (hrtc->Instance->BKP0R);
tmp = (uint32_t) &(hrtc->Instance->BKP0R);
tmp += (BackupRegister * 4U);
/* Write the specified register */
@@ -1272,7 +1276,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
tmp = (uint32_t) & (hrtc->Instance->BKP0R);
tmp = (uint32_t) &(hrtc->Instance->BKP0R);
tmp += (BackupRegister * 4U);
/* Read the specified register */
@@ -1742,7 +1746,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc)
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Set the BYPSHAD bit */
hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
hrtc->Instance->CR |= (uint32_t)RTC_CR_BYPSHAD;
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1775,7 +1779,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc)
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Reset the BYPSHAD bit */
hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;
hrtc->Instance->CR &= (uint32_t)~RTC_CR_BYPSHAD;
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);

106
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c
View File

@@ -172,7 +172,7 @@
[..]
Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
weak function.
HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
[..]
@@ -187,10 +187,10 @@
[..]
By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
all callbacks are reset to the corresponding legacy weak functions:
examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
reset to the legacy weak functions in the HAL_SAI_Init
and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -207,7 +207,7 @@
[..]
When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
and weak callbacks are used.
@endverbatim
*/
@@ -260,7 +260,7 @@ typedef enum
* @{
*/
static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);
static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, uint32_t mode);
static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
@@ -1243,6 +1243,9 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
/* Process Locked */
__HAL_LOCK(hsai);
/* Disable SAI peripheral */
SAI_Disable(hsai);
/* Disable the SAI DMA request */
hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
@@ -1274,9 +1277,6 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
}
}
/* Disable SAI peripheral */
SAI_Disable(hsai);
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
@@ -1302,6 +1302,9 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
/* Process Locked */
__HAL_LOCK(hsai);
/* Disable SAI peripheral */
SAI_Disable(hsai);
/* Check SAI DMA is enabled or not */
if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
{
@@ -1341,9 +1344,6 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
hsai->Instance->IMR = 0U;
hsai->Instance->CLRFR = 0xFFFFFFFFU;
/* Disable SAI peripheral */
SAI_Disable(hsai);
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
@@ -1663,7 +1663,18 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
/* Abort DMA in IT mode */
HAL_DMA_Abort_IT(hsai->hdmatx);
if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
{
/* Update SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
/* Call SAI error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
hsai->ErrorCallback(hsai);
#else
HAL_SAI_ErrorCallback(hsai);
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
else if (hsai->hdmarx != NULL)
{
@@ -1671,7 +1682,18 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
/* Abort DMA in IT mode */
HAL_DMA_Abort_IT(hsai->hdmarx);
if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
{
/* Update SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
/* Call SAI error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
hsai->ErrorCallback(hsai);
#else
HAL_SAI_ErrorCallback(hsai);
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
}
else
@@ -1706,7 +1728,18 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
/* Abort DMA in IT mode */
HAL_DMA_Abort_IT(hsai->hdmatx);
if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
{
/* Update SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
/* Call SAI error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
hsai->ErrorCallback(hsai);
#else
HAL_SAI_ErrorCallback(hsai);
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
else if (hsai->hdmarx != NULL)
{
@@ -1714,7 +1747,18 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
/* Abort DMA in IT mode */
HAL_DMA_Abort_IT(hsai->hdmarx);
if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
{
/* Update SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
/* Call SAI error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
hsai->ErrorCallback(hsai);
#else
HAL_SAI_ErrorCallback(hsai);
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
}
else
@@ -1749,7 +1793,18 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
/* Abort DMA in IT mode */
HAL_DMA_Abort_IT(hsai->hdmatx);
if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
{
/* Update SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
/* Call SAI error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
hsai->ErrorCallback(hsai);
#else
HAL_SAI_ErrorCallback(hsai);
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
else if (hsai->hdmarx != NULL)
{
@@ -1757,7 +1812,18 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
/* Abort DMA in IT mode */
HAL_DMA_Abort_IT(hsai->hdmarx);
if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
{
/* Update SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
/* Call SAI error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
hsai->ErrorCallback(hsai);
#else
HAL_SAI_ErrorCallback(hsai);
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
}
else
@@ -1909,7 +1975,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
* the configuration information for SAI module.
* @retval HAL state
*/
HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai)
{
return hsai->State;
}
@@ -1920,7 +1986,7 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
* the configuration information for the specified SAI Block.
* @retval SAI Error Code
*/
uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai)
{
return hsai->ErrorCode;
}
@@ -2138,7 +2204,7 @@ static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
* @param mode SAI_MODE_DMA or SAI_MODE_IT
* @retval the list of the IT flag to enable
*/
static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, uint32_t mode)
{
uint32_t tmpIT = SAI_IT_OVRUDR;

4
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c
View File

@@ -95,7 +95,7 @@
* the configuration information for SAI module.
* @retval SAI Clock Input
*/
void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
void SAI_BlockSynchroConfig(const SAI_HandleTypeDef *hsai)
{
uint32_t tmpregisterGCR;
@@ -158,7 +158,7 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
* the configuration information for SAI module.
* @retval SAI Clock Input
*/
uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai)
uint32_t SAI_GetInputClock(const SAI_HandleTypeDef *hsai)
{
/* This variable used to store the SAI_CK_x (value in Hz) */
uint32_t saiclocksource = 0U;

29
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c
View File

@@ -403,7 +403,6 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
{
uint32_t errorstate;
HAL_StatusTypeDef status;
SD_InitTypeDef Init;
/* Default SDIO peripheral configuration for SD card initialization */
@@ -415,11 +414,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
Init.ClockDiv = SDIO_INIT_CLK_DIV;
/* Initialize SDIO peripheral interface with default configuration */
status = SDIO_Init(hsd->Instance, Init);
if(status != HAL_OK)
{
return HAL_ERROR;
}
SDIO_Init(hsd->Instance, Init);
/* Disable SDIO Clock */
__HAL_SD_DISABLE(hsd);
@@ -696,7 +691,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
}
/* Get error state */
#if defined(SDIO_STA_STBITERR)
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
#else /* SDIO_STA_STBITERR not defined */
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
#endif /* SDIO_STA_STBITERR */
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
@@ -911,7 +910,11 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
}
/* Get error state */
#if defined(SDIO_STA_STBITERR)
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
#else /* SDIO_STA_STBITERR not defined */
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
#endif /* SDIO_STA_STBITERR */
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
@@ -2921,13 +2924,17 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
}
}
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
#if defined(SDIO_STA_STBITERR)
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
#else /* SDIO_STA_STBITERR not defined */
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
#endif /* SDIO_STA_STBITERR */
{
return HAL_SD_ERROR_DATA_TIMEOUT;
}
@@ -2949,7 +2956,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
*pData = SDIO_ReadFIFO(hsd->Instance);
pData++;
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
@@ -3141,13 +3148,17 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
break;
}
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
#if defined(SDIO_STA_STBITERR)
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
#else /* SDIO_STA_STBITERR not defined */
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
#endif /* SDIO_STA_STBITERR */
{
__HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);

41
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c
View File

@@ -82,15 +82,15 @@
and a pointer to the user callback function.
Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : SDRAM MspInit.
(+) MspDeInitCallback : SDRAM MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init
reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init
and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -105,7 +105,7 @@
When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -132,9 +132,15 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
* @{
*/
static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma);
static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
static void SDRAM_DMAError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
@@ -785,7 +791,7 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User SDRAM Callback
* To be used instead of the weak (surcharged) predefined callback
* To be used to override the weak predefined callback
* @param hsdram : SDRAM handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -806,9 +812,6 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SD
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hsdram);
state = hsdram->State;
if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
{
@@ -851,14 +854,12 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SD
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hsdram);
return status;
}
/**
* @brief Unregister a User SDRAM Callback
* SDRAM Callback is redirected to the weak (surcharged) predefined callback
* SDRAM Callback is redirected to the weak predefined callback
* @param hsdram : SDRAM handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -874,9 +875,6 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_
HAL_StatusTypeDef status = HAL_OK;
HAL_SDRAM_StateTypeDef state;
/* Process locked */
__HAL_LOCK(hsdram);
state = hsdram->State;
if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
{
@@ -925,14 +923,12 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hsdram);
return status;
}
/**
* @brief Register a User SDRAM Callback for DMA transfers
* To be used instead of the weak (surcharged) predefined callback
* To be used to override the weak predefined callback
* @param hsdram : SDRAM handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1216,7 +1212,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
* the configuration information for SDRAM module.
* @retval HAL state
*/
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram)
{
return hsdram->State;
}
@@ -1229,6 +1225,9 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
* @}
*/
/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
* @{
*/
/**
* @brief DMA SDRAM process complete callback.
* @param hdma : DMA handle
@@ -1236,6 +1235,7 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
*/
static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
@@ -1258,6 +1258,7 @@ static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma)
*/
static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
@@ -1280,6 +1281,7 @@ static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
*/
static void SDRAM_DMAError(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
@@ -1295,6 +1297,9 @@ static void SDRAM_DMAError(DMA_HandleTypeDef *hdma)
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
}
/**
* @}
*/
/**
* @}
*/

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