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инициализация spi перенесена на cube (работает)

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убрана кастомная библиотека periph_general
This commit is contained in:
Razvalyaev
2025-06-27 15:28:58 +03:00
parent 981dbf9bfa
commit a9a2466359
1587 changed files with 403396 additions and 250770 deletions
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542
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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@@ -37,16 +37,12 @@ extern "C" {
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
#if defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
#if defined(STM32U5)
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
#endif /* STM32U5 */
#endif /* STM32U5 || STM32H7 || STM32MP1 */
#endif /* STM32H7 || STM32MP1 */
/**
* @}
*/
@@ -113,6 +109,9 @@ extern "C" {
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
#endif /* STM32U5 */
#if defined(STM32H5)
#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
#endif /* STM32H5 */
/**
* @}
*/
@@ -140,7 +139,8 @@ extern "C" {
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#if defined(STM32L0)
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
input 1 for COMP1, LPTIM input 2 for COMP2 */
#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
@@ -214,6 +214,11 @@ extern "C" {
#endif
#endif
#if defined(STM32U5)
#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
#endif
/**
* @}
*/
@@ -234,10 +239,12 @@ extern "C" {
/** @defgroup CRC_Aliases CRC API aliases
* @{
*/
#if defined(STM32C0)
#if defined(STM32H5) || defined(STM32C0)
#else
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
inter STM32 series compatibility */
#endif
/**
* @}
@@ -280,7 +287,13 @@ extern "C" {
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#if defined(STM32H5)
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@@ -345,7 +358,8 @@ extern "C" {
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
@@ -458,7 +472,9 @@ extern "C" {
#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
#define PAGESIZE FLASH_PAGE_SIZE
#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
@@ -522,6 +538,10 @@ extern "C" {
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
#endif /* STM32H7 */
#if defined(STM32H7RS)
#define FLASH_OPTKEY1 FLASH_OPT_KEY1
#define FLASH_OPTKEY2 FLASH_OPT_KEY2
#endif /* STM32H7RS */
#if defined(STM32U5)
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
@@ -530,7 +550,20 @@ extern "C" {
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */
#if defined(STM32U0)
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_USER_nBOOT1 OB_USER_NBOOT1
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
#endif /* STM32U0 */
/**
* @}
@@ -574,6 +607,115 @@ extern "C" {
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
#if defined(STM32U5)
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster
#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection
#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection
#endif /* STM32U5 */
#if defined(STM32H5)
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
#define SYSCFG_ETH_MII SBS_ETH_MII
#define SYSCFG_ETH_RMII SBS_ETH_RMII
#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SYSCFG_SAU SBS_SAU
#define SYSCFG_MPU_SEC SBS_MPU_SEC
#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
#else
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
#endif /* __ARM_FEATURE_CMSE */
#define SYSCFG_CLK SBS_CLK
#define SYSCFG_CLASSB SBS_CLASSB
#define SYSCFG_FPU SBS_FPU
#define SYSCFG_ALL SBS_ALL
#define SYSCFG_SEC SBS_SEC
#define SYSCFG_NSEC SBS_NSEC
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
#define HAL_SYSCFG_Lock HAL_SBS_Lock
#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
#endif /* __ARM_FEATURE_CMSE */
#endif /* STM32H5 */
/**
* @}
*/
@@ -641,14 +783,16 @@ extern "C" {
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
@@ -670,13 +814,28 @@ extern "C" {
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
#if defined(STM32U5)
#if defined(STM32U5) || defined(STM32H5)
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
#endif /* STM32U5 */
#endif /* STM32U5 || STM32H5 */
#if defined(STM32U5)
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
#endif /* STM32U5 */
#if defined(STM32WBA)
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
#endif /* STM32WBA */
/**
* @}
*/
@@ -686,7 +845,25 @@ extern "C" {
*/
#if defined(STM32U5)
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
#endif /* STM32U5 */
#if defined(STM32H5)
#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
#endif /* STM32H5 */
#if defined(STM32H5) || defined(STM32U5)
#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
#endif /* STM32H5 || STM32U5 */
/**
* @}
*/
@@ -713,6 +890,10 @@ extern "C" {
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
#define HRTIMInterruptResquests HRTIMInterruptRequests
#endif /* STM32F3 || STM32G4 || STM32H7 */
#if defined(STM32G4)
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
@@ -850,8 +1031,8 @@ extern "C" {
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
#endif /* STM32F3 */
/**
* @}
*/
@@ -867,7 +1048,8 @@ extern "C" {
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@@ -1005,7 +1187,7 @@ extern "C" {
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@@ -1101,22 +1283,42 @@ extern "C" {
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
#if defined(STM32F7)
#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
#endif /* STM32H5 || STM32H7RS || STM32N6 */
#if defined(STM32WBA)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
#endif /* STM32WBA */
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
#if defined(STM32F7) || defined(STM32WB)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
#endif /* STM32F7 */
#endif /* STM32F7 || STM32WB */
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
#endif /* STM32H7 */
#if defined(STM32F7) || defined(STM32H7)
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
#endif /* STM32F7 || STM32H7 */
#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
/**
* @}
@@ -1396,30 +1598,40 @@ extern "C" {
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
(or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
@@ -1427,6 +1639,8 @@ extern "C" {
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
/**
* @}
*/
@@ -1590,7 +1804,8 @@ extern "C" {
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@@ -1599,8 +1814,10 @@ extern "C" {
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
@@ -1634,16 +1851,21 @@ extern "C" {
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
@@ -1768,6 +1990,17 @@ extern "C" {
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
@@ -1776,6 +2009,8 @@ extern "C" {
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
@@ -1786,6 +2021,7 @@ extern "C" {
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
#endif
@@ -1794,6 +2030,20 @@ extern "C" {
* @}
*/
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
* @{
*/
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
/**
* @}
*/
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
*/
@@ -1819,7 +2069,8 @@ extern "C" {
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
@@ -2076,7 +2327,8 @@ extern "C" {
#define COMP_STOP __HAL_COMP_DISABLE
#define COMP_LOCK __HAL_COMP_LOCK
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
@@ -2101,8 +2353,8 @@ extern "C" {
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F302xE) || defined(STM32F302xC)
#endif
#if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -2135,8 +2387,8 @@ extern "C" {
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#endif
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@@ -2193,8 +2445,8 @@ extern "C" {
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F373xC) ||defined(STM32F378xx)
#endif
#if defined(STM32F373xC) ||defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@@ -2211,7 +2463,7 @@ extern "C" {
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
# endif
#endif
#else
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@@ -2248,8 +2500,10 @@ extern "C" {
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
done into HAL_COMP_Init() */
/**
* @}
*/
@@ -2408,7 +2662,9 @@ extern "C" {
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@@ -2417,8 +2673,12 @@ extern "C" {
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
} while(0)
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
} while(0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
@@ -2454,8 +2714,8 @@ extern "C" {
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@@ -2505,6 +2765,12 @@ extern "C" {
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
#if defined(STM32C0)
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
#endif /* STM32C0 */
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@@ -2959,6 +3225,11 @@ extern "C" {
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
#endif
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
@@ -3423,7 +3694,13 @@ extern "C" {
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
#if defined(STM32U0)
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
#endif
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
defined(STM32U0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3525,8 +3802,10 @@ extern "C" {
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
#if !defined(STM32U0)
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
#endif
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@@ -3568,6 +3847,92 @@ extern "C" {
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
#endif /* STM32U5 */
#if defined(STM32H5)
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
#endif /* STM32H5 */
/**
* @}
*/
@@ -3584,9 +3949,10 @@ extern "C" {
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \
defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
defined (STM32C0)
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
defined (STM32WBA) || defined (STM32H5) || \
defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3621,6 +3987,13 @@ extern "C" {
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
defined (STM32H7) || \
defined (STM32L0) || defined (STM32L1) || \
defined (STM32WB)
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
#endif
#define IS_ALARM IS_RTC_ALARM
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
#define IS_TAMPER IS_RTC_TAMPER
@@ -3639,6 +4012,11 @@ extern "C" {
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
#if defined (STM32H5)
#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
#endif /* STM32H5 */
/**
* @}
*/
@@ -3868,6 +4246,33 @@ extern "C" {
#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
#if defined(STM32U5)
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD
#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK
#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC
#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM
#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM
#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK
#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ
#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT
#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0
#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1
#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM
#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM
#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT
#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM
#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM
#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID
#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0
#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
#endif
/**
* @}
*/
@@ -3897,6 +4302,9 @@ extern "C" {
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
/**
* @}
*/

168
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h
View File

@@ -21,7 +21,7 @@
#define __STM32F4xx_ADC_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -36,15 +36,15 @@
/** @addtogroup ADC
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Types ADC Exported Types
* @{
*/
/**
* @brief Structure definition of ADC and regular group initialization
/**
* @brief Structure definition of ADC and regular group initialization
* @note Parameters of this structure are shared within 2 scopes:
* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
@@ -58,7 +58,7 @@
*/
typedef struct
{
uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
all the ADCs.
This parameter can be a value of @ref ADC_ClockPrescaler */
uint32_t Resolution; /*!< Configures the ADC resolution.
@@ -101,20 +101,20 @@ typedef struct
If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
This parameter can be set to ENABLE or DISABLE. */
}ADC_InitTypeDef;
or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
This parameter can be set to ENABLE or DISABLE. */
} ADC_InitTypeDef;
/**
* @brief Structure definition of ADC channel for regular group
/**
* @brief Structure definition of ADC channel for regular group
* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
* ADC can be either disabled or enabled without conversion on going on regular group.
*/
typedef struct
*/
typedef struct
{
uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_channels */
@@ -130,31 +130,31 @@ typedef struct
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
}ADC_ChannelConfTypeDef;
} ADC_ChannelConfTypeDef;
/**
* @brief ADC Configuration multi-mode structure definition
*/
/**
* @brief ADC Configuration multi-mode structure definition
*/
typedef struct
{
uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
This parameter can be a value of @ref ADC_analog_watchdog_selection */
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
This parameter must be a 12-bit value. */
This parameter must be a 12-bit value. */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
This parameter must be a 12-bit value. */
uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
This parameter has an effect only if watchdog mode is configured on single channel
This parameter can be a value of @ref ADC_channels */
uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
This parameter has an effect only if watchdog mode is configured on single channel
This parameter can be a value of @ref ADC_channels */
FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured
is interrupt mode or in polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
}ADC_AnalogWDGConfTypeDef;
} ADC_AnalogWDGConfTypeDef;
/**
/**
* @brief HAL ADC state machine: ADC states definition (bitfields)
*/
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */
@@ -186,9 +186,9 @@ typedef struct
#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
/**
/**
* @brief ADC handle Structure definition
*/
*/
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
typedef struct __ADC_HandleTypeDef
#else
@@ -217,7 +217,7 @@ typedef struct
void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}ADC_HandleTypeDef;
} ADC_HandleTypeDef;
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/**
@@ -268,18 +268,18 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
* @{
*/
*/
#define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U
#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
/**
* @}
*/
*/
/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
* @{
*/
*/
#define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U
#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
@@ -298,29 +298,29 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
/**
* @}
*/
*/
/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
*/
#define ADC_RESOLUTION_12B 0x00000000U
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
/**
* @}
*/
*/
/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
* @{
*/
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
/**
* @}
*/
*/
/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
* @{
@@ -346,20 +346,20 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U)
/**
* @}
*/
*/
/** @defgroup ADC_Data_align ADC Data Align
* @{
*/
*/
#define ADC_DATAALIGN_RIGHT 0x00000000U
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
/**
* @}
*/
*/
/** @defgroup ADC_channels ADC Common Channels
* @{
*/
*/
#define ADC_CHANNEL_0 0x00000000U
#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
@@ -384,11 +384,11 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
/**
* @}
*/
*/
/** @defgroup ADC_sampling_times ADC Sampling Times
* @{
*/
*/
#define ADC_SAMPLETIME_3CYCLES 0x00000000U
#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
@@ -399,21 +399,21 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
/**
* @}
*/
*/
/** @defgroup ADC_EOCSelection ADC EOC Selection
/** @defgroup ADC_EOCSelection ADC EOC Selection
* @{
*/
*/
#define ADC_EOC_SEQ_CONV 0x00000000U
#define ADC_EOC_SINGLE_CONV 0x00000001U
#define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */
/**
* @}
*/
*/
/** @defgroup ADC_Event_type ADC Event Type
* @{
*/
*/
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
/**
@@ -422,7 +422,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
* @{
*/
*/
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
@@ -432,22 +432,22 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_ANALOGWATCHDOG_NONE 0x00000000U
/**
* @}
*/
*/
/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
* @{
*/
*/
#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
/**
* @}
*/
*/
/** @defgroup ADC_flags_definition ADC Flags Definition
* @{
*/
*/
#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
@@ -456,11 +456,11 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
/**
* @}
*/
*/
/** @defgroup ADC_channels_type ADC Channels Type
* @{
*/
*/
#define ADC_ALL_CHANNELS 0x00000001U
#define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */
#define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */
@@ -470,7 +470,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/**
* @}
*/
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Macros ADC Exported Macros
@@ -562,10 +562,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @{
*/
/* Initialization/de-initialization functions ***********************************/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
@@ -580,25 +580,25 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca
* @{
*/
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
/**
* @}
@@ -608,8 +608,8 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
* @{
*/
/* Peripheral Control functions *************************************************/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
/**
* @}
*/
@@ -618,7 +618,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
* @{
*/
/* Peripheral State functions ***************************************************/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @}
@@ -697,7 +697,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
@@ -781,7 +781,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @brief Set ADC Regular channel sequence length.
* @param _NbrOfConversion_ Regular channel sequence length.
* @param _NbrOfConversion_ Regular channel sequence length.
* @retval None
*/
#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
@@ -789,7 +789,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @brief Set the ADC's sample time for channel numbers between 10 and 18.
* @param _SAMPLETIME_ Sample time parameter.
* @param _CHANNELNB_ Channel number.
* @param _CHANNELNB_ Channel number.
* @retval None
*/
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
@@ -797,7 +797,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @brief Set the ADC's sample time for channel numbers between 0 and 9.
* @param _SAMPLETIME_ Sample time parameter.
* @param _CHANNELNB_ Channel number.
* @param _CHANNELNB_ Channel number.
* @retval None
*/
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
@@ -805,7 +805,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @brief Set the selected regular channel rank for rank between 1 and 6.
* @param _CHANNELNB_ Channel number.
* @param _RANKNB_ Rank number.
* @param _RANKNB_ Rank number.
* @retval None
*/
#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
@@ -813,7 +813,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @brief Set the selected regular channel rank for rank between 7 and 12.
* @param _CHANNELNB_ Channel number.
* @param _RANKNB_ Rank number.
* @param _RANKNB_ Rank number.
* @retval None
*/
#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
@@ -821,7 +821,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @brief Set the selected regular channel rank for rank between 13 and 16.
* @param _CHANNELNB_ Channel number.
* @param _RANKNB_ Rank number.
* @param _RANKNB_ Rank number.
* @retval None
*/
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
@@ -883,7 +883,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @}
*/
*/
/**
* @}

94
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h
View File

@@ -21,7 +21,7 @@
#define __STM32F4xx_ADC_EX_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -33,14 +33,14 @@
/** @addtogroup ADCEx
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Types ADC Exported Types
* @{
*/
/**
/**
* @brief ADC Configuration injected Channel structure definition
* @note Parameters of this structure are shared within 2 scopes:
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
@@ -52,7 +52,7 @@
* - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
* - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
*/
typedef struct
typedef struct
{
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
This parameter can be a value of @ref ADC_channels
@@ -76,17 +76,17 @@ typedef struct
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE.
Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
This parameter can be set to ENABLE or DISABLE.
This parameter can be set to ENABLE or DISABLE.
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
@@ -104,22 +104,22 @@ typedef struct
uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
}ADC_InjectionConfTypeDef;
} ADC_InjectionConfTypeDef;
/**
* @brief ADC Configuration multi-mode structure definition
*/
/**
* @brief ADC Configuration multi-mode structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
This parameter can be a value of @ref ADCEx_Common_mode */
uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
}ADC_MultiModeTypeDef;
} ADC_MultiModeTypeDef;
/**
* @}
@@ -132,7 +132,7 @@ typedef struct
/** @defgroup ADCEx_Common_mode ADC Common Mode
* @{
*/
*/
#define ADC_MODE_INDEPENDENT 0x00000000U
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
@@ -148,33 +148,33 @@ typedef struct
#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
/**
* @}
*/
*/
/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
* @{
*/
*/
#define ADC_DMAACCESSMODE_DISABLED 0x00000000U /*!< DMA mode disabled */
#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
/**
* @}
*/
*/
/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
* @{
*/
*/
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE 0x00000000U
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
/**
* @}
*/
*/
/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
* @{
*/
*/
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 0x00000000U
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)
@@ -194,11 +194,11 @@ typedef struct
#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1U)
/**
* @}
*/
*/
/** @defgroup ADCEx_injected_rank ADC Injected Rank
* @{
*/
*/
#define ADC_INJECTED_RANK_1 0x00000001U
#define ADC_INJECTED_RANK_2 0x00000002U
#define ADC_INJECTED_RANK_3 0x00000003U
@@ -219,18 +219,18 @@ typedef struct
STM32F412Vx || STM32F412Rx || STM32F412Cx */
#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
*/
/**
* @}
*/
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Macros ADC Exported Macros
@@ -242,9 +242,9 @@ typedef struct
* @note Use case of this macro:
* On devices STM32F42x and STM32F43x, ADC internal channels
* Vbat and VrefInt share the same internal path, only
* one of them can be enabled.This macro is to be used when ADC
* channels Vbat and VrefInt are selected, and must be called
* before starting conversion of ADC channel VrefInt in order
* one of them can be enabled.This macro is to be used when ADC
* channels Vbat and VrefInt are selected, and must be called
* before starting conversion of ADC channel VrefInt in order
* to disable ADC channel Vbat.
* @retval None
*/
@@ -252,7 +252,7 @@ typedef struct
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/**
* @}
*/
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADCEx_Exported_Functions
@@ -264,24 +264,24 @@ typedef struct
*/
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
/* Peripheral Control functions *************************************************/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected);
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
/**
* @}
*/
*/
/**
* @}
@@ -308,7 +308,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE ||
STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || \
defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || \
defined(STM32F469xx) || defined(STM32F479xx)
@@ -360,7 +360,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
/**
* @brief Set the selected injected Channel rank.
* @param _CHANNELNB_ Channel number.
* @param _RANKNB_ Rank number.
* @param _RANKNB_ Rank number.
* @param _JSQR_JL_ Sequence length.
* @retval None
*/
@@ -392,7 +392,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
/**
* @}
*/
*/
/**
* @}

53
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h
View File

@@ -102,21 +102,25 @@ typedef struct
{
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
This parameter must be a number between
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
This parameter must be a number between
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
This parameter must be a number between
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
This parameter must be a number between
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
@@ -205,7 +209,11 @@ typedef struct
/**
* @brief CAN handle Structure definition
*/
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
typedef struct __CAN_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
{
CAN_TypeDef *Instance; /*!< Register base address */
@@ -294,11 +302,11 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to
#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
@@ -329,7 +337,8 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to
#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with
silent mode */
/**
* @}
*/
@@ -644,7 +653,8 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID,
void (* pCallback)(CAN_HandleTypeDef *_hcan));
HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
@@ -658,7 +668,7 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig);
/**
* @}
@@ -674,14 +684,16 @@ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
const uint8_t aData[], uint32_t *pTxMailbox);
HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan);
uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo);
/**
* @}
@@ -729,8 +741,8 @@ void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan);
uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
/**
@@ -806,7 +818,8 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | \
CAN_TX_MAILBOX2))
#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
#define IS_CAN_DLC(DLC) ((DLC) <= 8U)

136
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h
View File

@@ -48,61 +48,70 @@ extern "C" {
typedef struct
{
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
It can be one of @ref CEC_Signal_Free_Time
It can be one of CEC_Signal_Free_Time
and belongs to the set {0,...,7} where
0x0 is the default configuration
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
or CEC_EXTENDED_TOLERANCE */
it can be a value of CEC_Tolerance :
it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */
uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising
Error stops the reception.
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
CEC_RX_STOP_ON_BRE: reception is stopped. */
uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an
Error-Bit is generated on the
CEC line upon Bit Rising Error detection.
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an
Error-Bit is generated on the
CEC line upon Long Bit Period Error detection.
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an
Error-Bit generation on the CEC line
upon an error detected on a broadcast message.
It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
It supersedes BREGEN and LBPEGEN bits for a broadcast message error
handling. It can take two values:
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
a) BRE detection: error-bit generation on the CEC line if
BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
b) LBPE detection: error-bit generation on the CEC line
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
no error-bit generation in case neither a) nor b) are satisfied. Additionally,
there is no error-bit generation in case of Short Bit Period Error detection in
a broadcast message while LSTN bit is set. */
no error-bit generation in case neither a) nor b) are satisfied.
Additionally, there is no error-bit generation in case of Short Bit
Period Error detection in a broadcast message while LSTN bit is set. */
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts.
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end
of message transmission/reception. */
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode.
It can take two values:
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
own address (OAR). Messages addressed to different destination are ignored.
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed
to its own address (OAR). Messages addressed to different destination
are ignored.
Broadcast messages are always received.
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
address (OAR) with positive acknowledge. Messages addressed to different destination
are received, but without interfering with the CEC bus: no acknowledge sent. */
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its
own address (OAR) with positive acknowledge. Messages addressed to
different destination are received, but without interfering with the
CEC bus: no acknowledge sent. */
uint16_t OwnAddress; /*!< Own addresses configuration
This parameter can be a value of @ref CEC_OWN_ADDRESS */
uint16_t OwnAddress; /*!< Own addresses configuration
This parameter can be a value of CEC_OWN_ADDRESS */
uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */
@@ -111,7 +120,8 @@ typedef struct
/**
* @brief HAL CEC State definition
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState
(see CEC_State_Definition).
* - gState contains CEC state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -159,37 +169,37 @@ typedef struct __CEC_HandleTypeDef
typedef struct
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
{
CEC_TypeDef *Instance; /*!< CEC registers base address */
CEC_TypeDef *Instance; /*!< CEC registers base address */
CEC_InitTypeDef Init; /*!< CEC communication parameters */
CEC_InitTypeDef Init; /*!< CEC communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
HAL_LockTypeDef Lock; /*!< Locking object */
HAL_LockTypeDef Lock; /*!< Locking object */
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
This parameter can be a value of HAL_CEC_StateTypeDef */
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
This parameter can be a value of HAL_CEC_StateTypeDef */
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
in case error is reported */
in case error is reported */
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback)(struct __CEC_HandleTypeDef
*hcec); /*!< CEC Tx Transfer completed callback */
*hcec); /*!< CEC Tx Transfer completed callback */
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
} CEC_HandleTypeDef;
@@ -202,7 +212,7 @@ typedef enum
{
HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
} HAL_CEC_CallbackIDTypeDef;
@@ -212,7 +222,8 @@ typedef enum
*/
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed
callback function */
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
@@ -358,16 +369,16 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
* @{
*/
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
@@ -421,8 +432,8 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
* @{
*/
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
/**
* @}
*/
@@ -430,7 +441,7 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
* @{
*/
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
/**
* @}
*/
@@ -438,7 +449,7 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
* @{
*/
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
/**
* @}
*/
@@ -622,7 +633,8 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
* @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
* @retval none
*/
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \
(__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
/**
* @}
@@ -660,8 +672,8 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
uint8_t *pData, uint32_t Size);
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
const uint8_t *pData, uint32_t Size);
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec);
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
@@ -675,8 +687,8 @@ void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
* @{
*/
/* Peripheral State functions ************************************************/
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec);
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec);
/**
* @}
*/
@@ -731,8 +743,9 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \
(((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
@@ -789,4 +802,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
#endif
#endif /* STM32F4xxHAL_CEC_H */

5
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h
View File

@@ -45,6 +45,7 @@
#define HAL_DMA_MODULE_ENABLED
#define HAL_DMA2D_MODULE_ENABLED
#define HAL_ETH_MODULE_ENABLED
/* #define HAL_ETH_LEGACY_MODULE_ENABLED */
#define HAL_FLASH_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
@@ -332,6 +333,10 @@
#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
#include "stm32f4xx_hal_eth_legacy.h"
#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */

3
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h
View File

@@ -284,8 +284,11 @@ void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1U)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
void HAL_CORTEX_ClearEvent(void);
/**
* @}
*/

2
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h
View File

@@ -157,7 +157,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
/**
* @}
*/

12
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h
View File

@@ -51,7 +51,8 @@ typedef struct
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref CRYP_Data_Type */
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
128 or 256 bit key length in TinyAES This parameter can be a value of
@ref CRYP_Key_Size */
uint32_t *pKey; /*!< The key used for encryption/decryption */
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
counter in CTR mode */
@@ -224,7 +225,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
/**
* @}
*/
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
* @{
*/
@@ -402,8 +403,11 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
*/
#define CRYP_FLAG_MASK 0x0000001FU
#if defined(CRYP)
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)? \
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) \
& CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK))\
== ((__FLAG__) & CRYP_FLAG_MASK)))
#else /* AES*/
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
#endif /* End AES or CRYP */

32
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h
View File

@@ -78,19 +78,19 @@ typedef struct
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
#if defined(DAC_CHANNEL2_SUPPORT)
void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
#endif /* DAC_CHANNEL2_SUPPORT */
void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac);
void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
} DAC_HandleTypeDef;
@@ -404,7 +404,7 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
@@ -430,8 +430,9 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA
* @{
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
/**
* @}
*/
@@ -440,8 +441,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
/**
* @}
@@ -477,4 +478,3 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
#endif /* STM32F4xx_HAL_DAC_H */

9
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h
View File

@@ -81,6 +81,7 @@ extern "C" {
* @}
*/
/**
* @}
*/
@@ -147,19 +148,18 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
#if defined(DAC_CHANNEL2_SUPPORT)
#endif
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
#endif /* DAC_CHANNEL2_SUPPORT */
#if defined(DAC_CHANNEL2_SUPPORT)
#endif
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
#endif /* DAC_CHANNEL2_SUPPORT */
/**
* @}
@@ -202,4 +202,3 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
#endif
#endif /* STM32F4xx_HAL_DAC_EX_H */

2
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
View File

@@ -54,7 +54,9 @@ typedef enum
/* Exported macro ------------------------------------------------------------*/
#if !defined(UNUSED)
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#endif /* UNUSED */
#define HAL_MAX_DELAY 0xFFFFFFFFU

246
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h
View File

@@ -34,16 +34,16 @@
/** @addtogroup DFSDM
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
* @{
*/
/**
* @brief HAL DFSDM Channel states definition
*/
/**
* @brief HAL DFSDM Channel states definition
*/
typedef enum
{
HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
@@ -51,9 +51,9 @@ typedef enum
HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */
}HAL_DFSDM_Channel_StateTypeDef;
/**
* @brief DFSDM channel output clock structure definition
*/
/**
* @brief DFSDM channel output clock structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< Output clock enable/disable */
@@ -63,9 +63,9 @@ typedef struct
This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
}DFSDM_Channel_OutputClockTypeDef;
/**
* @brief DFSDM channel input structure definition
*/
/**
* @brief DFSDM channel input structure definition
*/
typedef struct
{
uint32_t Multiplexer; /*!< Input is external serial inputs or internal register.
@@ -76,9 +76,9 @@ typedef struct
This parameter can be a value of @ref DFSDM_Channel_InputPins */
}DFSDM_Channel_InputTypeDef;
/**
* @brief DFSDM channel serial interface structure definition
*/
/**
* @brief DFSDM channel serial interface structure definition
*/
typedef struct
{
uint32_t Type; /*!< SPI or Manchester modes.
@@ -87,9 +87,9 @@ typedef struct
This parameter can be a value of @ref DFSDM_Channel_SpiClock */
}DFSDM_Channel_SerialInterfaceTypeDef;
/**
* @brief DFSDM channel analog watchdog structure definition
*/
/**
* @brief DFSDM channel analog watchdog structure definition
*/
typedef struct
{
uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
@@ -98,9 +98,9 @@ typedef struct
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
}DFSDM_Channel_AwdTypeDef;
/**
* @brief DFSDM channel init structure definition
*/
/**
* @brief DFSDM channel init structure definition
*/
typedef struct
{
DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */
@@ -113,14 +113,14 @@ typedef struct
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
}DFSDM_Channel_InitTypeDef;
/**
* @brief DFSDM channel handle structure definition
*/
/**
* @brief DFSDM channel handle structure definition
*/
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
typedef struct __DFSDM_Channel_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
{
DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
@@ -150,9 +150,9 @@ typedef enum
*/
typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
#endif
/**
* @brief HAL DFSDM Filter states definition
*/
/**
* @brief HAL DFSDM Filter states definition
*/
typedef enum
{
HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */
@@ -163,9 +163,9 @@ typedef enum
HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */
}HAL_DFSDM_Filter_StateTypeDef;
/**
* @brief DFSDM filter regular conversion parameters structure definition
*/
/**
* @brief DFSDM filter regular conversion parameters structure definition
*/
typedef struct
{
uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
@@ -174,9 +174,9 @@ typedef struct
FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */
}DFSDM_Filter_RegularParamTypeDef;
/**
* @brief DFSDM filter injected conversion parameters structure definition
*/
/**
* @brief DFSDM filter injected conversion parameters structure definition
*/
typedef struct
{
uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
@@ -189,9 +189,9 @@ typedef struct
This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
}DFSDM_Filter_InjectedParamTypeDef;
/**
* @brief DFSDM filter parameters structure definition
*/
/**
* @brief DFSDM filter parameters structure definition
*/
typedef struct
{
uint32_t SincOrder; /*!< Sinc filter order.
@@ -202,9 +202,9 @@ typedef struct
This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
}DFSDM_Filter_FilterParamTypeDef;
/**
* @brief DFSDM filter init structure definition
*/
/**
* @brief DFSDM filter init structure definition
*/
typedef struct
{
DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */
@@ -212,9 +212,9 @@ typedef struct
DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */
}DFSDM_Filter_InitTypeDef;
/**
* @brief DFSDM filter handle structure definition
*/
/**
* @brief DFSDM filter handle structure definition
*/
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
typedef struct __DFSDM_Filter_HandleTypeDef
#else
@@ -233,7 +233,7 @@ typedef struct
uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
uint32_t InjConvRemaining; /*!< Injected conversions remaining */
HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
uint32_t ErrorCode; /*!< DFSDM filter error code */
uint32_t ErrorCode; /*!< DFSDM filter error code */
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */
@@ -247,9 +247,9 @@ typedef struct
#endif
}DFSDM_Filter_HandleTypeDef;
/**
* @brief DFSDM filter analog watchdog parameters structure definition
*/
/**
* @brief DFSDM filter analog watchdog parameters structure definition
*/
typedef struct
{
uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
@@ -290,11 +290,11 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
/**
* @}
*/
#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
/**
* @brief Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices
*/
*/
#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
/**
* @brief Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices
*/
typedef struct
{
uint32_t DFSDM1ClockIn; /*!< Source selection for DFSDM1_Ckin.
@@ -306,15 +306,15 @@ typedef struct
uint32_t DFSDM2ClockOut; /*!< Source selection for DFSDM2_Ckout.
This parameter can be a value of @ref DFSDM_2_CLOCKOUT_SELECTION*/
uint32_t DFSDM1BitClkDistribution; /*!< Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1 or TIM4 OC2.
This parameter can be a value of @ref DFSDM_1_BIT_STREAM_DISTRIBUTION
@note The DFSDM2 audio gated by TIM4 OC2 can be injected on CKIN0 or CKIN2
This parameter can be a value of @ref DFSDM_1_BIT_STREAM_DISTRIBUTION
@note The DFSDM2 audio gated by TIM4 OC2 can be injected on CKIN0 or CKIN2
@note The DFSDM2 audio gated by TIM4 OC1 can be injected on CKIN1 or CKIN3 */
uint32_t DFSDM2BitClkDistribution; /*!< Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 or TIM3 OC2 or TIM3 OC3 or TIM3 OC4.
This parameter can be a value of @ref DFSDM_2_BIT_STREAM_DISTRIBUTION
@note The DFSDM2 audio gated by TIM3 OC4 can be injected on CKIN0 or CKIN4
@note The DFSDM2 audio gated by TIM3 OC3 can be injected on CKIN1 or CKIN5
@note The DFSDM2 audio gated by TIM3 OC2 can be injected on CKIN2 or CKIN6
@note The DFSDM2 audio gated by TIM3 OC1 can be injected on CKIN3 or CKIN7 */
This parameter can be a value of @ref DFSDM_2_BIT_STREAM_DISTRIBUTION
@note The DFSDM2 audio gated by TIM3 OC4 can be injected on CKIN0 or CKIN4
@note The DFSDM2 audio gated by TIM3 OC3 can be injected on CKIN1 or CKIN5
@note The DFSDM2 audio gated by TIM3 OC2 can be injected on CKIN2 or CKIN6
@note The DFSDM2 audio gated by TIM3 OC1 can be injected on CKIN3 or CKIN7 */
uint32_t DFSDM1DataDistribution; /*!< Source selection for DatIn0 and DatIn2 of DFSDM1.
This parameter can be a value of @ref DFSDM_1_DATA_DISTRIBUTION */
uint32_t DFSDM2DataDistribution; /*!< Source selection for DatIn0, DatIn2, DatIn4 and DatIn6 of DFSDM2.
@@ -323,8 +323,8 @@ typedef struct
#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
/**
* @}
*/
*/
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@@ -415,7 +415,7 @@ typedef struct
/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
* @{
*/
#if defined(STM32F413xx) || defined(STM32F423xx)
#if defined(STM32F413xx) || defined(STM32F423xx)
/* Trigger for stm32f413xx and STM32f423xx devices */
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For All DFSDM1/2 filters */
#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For All DFSDM1/2 filters */
@@ -442,7 +442,7 @@ typedef struct
/**
* @}
*/
/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
* @{
*/
@@ -477,7 +477,7 @@ typedef struct
/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
* @{
*/
*/
#define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */
#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */
#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */
@@ -510,7 +510,7 @@ typedef struct
- in 16-bit MSB the channel number is set
e.g. for channel 3 definition:
- the channel mask is 0x00000008 (bit 3 is set)
- the channel number 3 is 0x00030000
- the channel number 3 is 0x00030000
--> Consequently, channel 3 definition is 0x00000008 | 0x00030000 = 0x00030008 */
#define DFSDM_CHANNEL_0 0x00000001U
#define DFSDM_CHANNEL_1 0x00010002U
@@ -545,25 +545,25 @@ typedef struct
#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
/** @defgroup DFSDM_1_CLOCKOUT_SELECTION DFSDM1 ClockOut Selection
* @{
*/
*/
#define DFSDM1_CKOUT_DFSDM2_CKOUT 0x00000080U
#define DFSDM1_CKOUT_DFSDM1 0x00000000U
/**
* @}
*/
*/
/** @defgroup DFSDM_2_CLOCKOUT_SELECTION DFSDM2 ClockOut Selection
* @{
*/
*/
#define DFSDM2_CKOUT_DFSDM2_CKOUT 0x00040000U
#define DFSDM2_CKOUT_DFSDM2 0x00000000U
#define DFSDM2_CKOUT_DFSDM2 0x00000000U
/**
* @}
*/
*/
/** @defgroup DFSDM_1_CLOCKIN_SELECTION DFSDM1 ClockIn Selection
* @{
*/
*/
#define DFSDM1_CKIN_DFSDM2_CKOUT 0x00000040U
#define DFSDM1_CKIN_PAD 0x00000000U
/**
@@ -572,16 +572,16 @@ typedef struct
/** @defgroup DFSDM_2_CLOCKIN_SELECTION DFSDM2 ClockIn Selection
* @{
*/
*/
#define DFSDM2_CKIN_DFSDM2_CKOUT 0x00020000U
#define DFSDM2_CKIN_PAD 0x00000000U
/**
* @}
*/
/** @defgroup DFSDM_1_BIT_STREAM_DISTRIBUTION DFSDM1 Bit Stream Distribution
/** @defgroup DFSDM_1_BIT_STREAM_DISTRIBUTION DFSDM1 Bit Stream Distribution
* @{
*/
*/
#define DFSDM1_T4_OC2_BITSTREAM_CKIN0 0x00000000U /* TIM4_OC2 to CLKIN0 */
#define DFSDM1_T4_OC2_BITSTREAM_CKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL /* TIM4_OC2 to CLKIN2 */
#define DFSDM1_T4_OC1_BITSTREAM_CKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL /* TIM4_OC1 to CLKIN3 */
@@ -589,14 +589,14 @@ typedef struct
/**
* @}
*/
/** @defgroup DFSDM_2_BIT_STREAM_DISTRIBUTION DFSDM12 Bit Stream Distribution
/** @defgroup DFSDM_2_BIT_STREAM_DISTRIBUTION DFSDM12 Bit Stream Distribution
* @{
*/
#define DFSDM2_T3_OC4_BITSTREAM_CKIN0 0x00000000U /* TIM3_OC4 to CKIN0 */
#define DFSDM2_T3_OC4_BITSTREAM_CKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */
#define DFSDM2_T3_OC3_BITSTREAM_CKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */
#define DFSDM2_T3_OC3_BITSTREAM_CKIN1 0x00000000U /* TIM3_OC3 to CKIN1 */
#define DFSDM2_T3_OC4_BITSTREAM_CKIN0 0x00000000U /* TIM3_OC4 to CKIN0 */
#define DFSDM2_T3_OC4_BITSTREAM_CKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */
#define DFSDM2_T3_OC3_BITSTREAM_CKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */
#define DFSDM2_T3_OC3_BITSTREAM_CKIN1 0x00000000U /* TIM3_OC3 to CKIN1 */
#define DFSDM2_T3_OC2_BITSTREAM_CKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL /* TIM3_OC2to CKIN6 */
#define DFSDM2_T3_OC2_BITSTREAM_CKIN2 0x00000000U /* TIM3_OC2 to CKIN2 */
#define DFSDM2_T3_OC1_BITSTREAM_CKIN3 0x00000000U /* TIM3_OC1 to CKIN3 */
@@ -605,9 +605,9 @@ typedef struct
* @}
*/
/** @defgroup DFSDM_1_DATA_DISTRIBUTION DFSDM1 Data Distribution
/** @defgroup DFSDM_1_DATA_DISTRIBUTION DFSDM1 Data Distribution
* @{
*/
*/
#define DFSDM1_DATIN0_TO_DATIN0_PAD 0x00000000U
#define DFSDM1_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM1D0SEL
#define DFSDM1_DATIN2_TO_DATIN2_PAD 0x00000000U
@@ -615,8 +615,8 @@ typedef struct
/**
* @}
*/
/** @defgroup DFSDM_2_DATA_DISTRIBUTION DFSDM2 Data Distribution
/** @defgroup DFSDM_2_DATA_DISTRIBUTION DFSDM2 Data Distribution
* @{
*/
#define DFSDM2_DATIN0_TO_DATIN0_PAD 0x00000000U
@@ -624,13 +624,13 @@ typedef struct
#define DFSDM2_DATIN2_TO_DATIN2_PAD 0x00000000U
#define DFSDM2_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM2D2SEL
#define DFSDM2_DATIN4_TO_DATIN4_PAD 0x00000000U
#define DFSDM2_DATIN4_TO_DATIN5_PAD SYSCFG_MCHDLYCR_DFSDM2D4SEL
#define DFSDM2_DATIN6_TO_DATIN6_PAD 0x00000000U
#define DFSDM2_DATIN6_TO_DATIN7_PAD SYSCFG_MCHDLYCR_DFSDM2D6SEL
#define DFSDM2_DATIN4_TO_DATIN5_PAD SYSCFG_MCHDLYCR_DFSDM2D4SEL
#define DFSDM2_DATIN6_TO_DATIN6_PAD 0x00000000U
#define DFSDM2_DATIN6_TO_DATIN7_PAD SYSCFG_MCHDLYCR_DFSDM2D6SEL
/**
* @}
*/
/** @defgroup HAL_MCHDLY_CLOCK HAL MCHDLY Clock enable
* @{
*/
@@ -650,7 +650,7 @@ typedef struct
/**
* @}
*/
/** @defgroup DFSDM_CLOCKOUT_SOURCE DFSDM Clock Source Selection
* @{
*/
@@ -682,8 +682,8 @@ typedef struct
#define HAL_DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL
/**
* @}
*/
*/
/** @defgroup DFSDM_DATAIN4_SOURCE DFSDM Source Selection For DATAIN4
* @{
*/
@@ -691,8 +691,8 @@ typedef struct
#define HAL_DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL
/**
* @}
*/
*/
/** @defgroup DFSDM_DATAIN6_SOURCE DFSDM Source Selection For DATAIN6
* @{
*/
@@ -700,7 +700,7 @@ typedef struct
#define HAL_DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL
/**
* @}
*/
*/
/** @defgroup DFSDM1_CLKIN_SOURCE DFSDM1 Source Selection For CLKIN
* @{
@@ -711,8 +711,8 @@ typedef struct
#define HAL_DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
/**
* @}
*/
*/
/** @defgroup DFSDM2_CLKIN_SOURCE DFSDM2 Source Selection For CLKIN
* @{
*/
@@ -726,12 +726,12 @@ typedef struct
#define HAL_DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
/**
* @}
*/
*/
#endif /* SYSCFG_MCHDLYCR_BSCKSEL*/
/**
* @}
*/
*/
/* End of exported constants -------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
@@ -811,11 +811,11 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
@@ -827,7 +827,7 @@ void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
* @{
*/
/* Channel state function *****************************************************/
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
/**
* @}
*/
@@ -887,16 +887,16 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
DFSDM_Filter_AwdParamTypeDef* awdParam);
const DFSDM_Filter_AwdParamTypeDef* awdParam);
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
@@ -917,8 +917,8 @@ void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
* @{
*/
/* Filter state functions *****************************************************/
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
/**
* @}
*/
@@ -994,7 +994,7 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source);
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
#define IS_DFSDM_DELAY_CLOCK(CLOCK) (((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM2) || \
((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1))
((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1))
#else
#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
@@ -1045,18 +1045,18 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source);
((INSTANCE) == DFSDM1_Channel2) || \
((INSTANCE) == DFSDM1_Channel3))
#define IS_DFSDM1_FILTER_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
((INSTANCE) == DFSDM1_Filter1))
((INSTANCE) == DFSDM1_Filter1))
#endif /* DFSDM2_Channel0 */
#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
#define IS_DFSDM_CLOCKIN_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKIN_PAD) || \
((SELECTION) == HAL_DFSDM2_CKIN_DM) || \
((SELECTION) == HAL_DFSDM1_CKIN_PAD) || \
((SELECTION) == HAL_DFSDM1_CKIN_DM))
((SELECTION) == HAL_DFSDM1_CKIN_DM))
#define IS_DFSDM_CLOCKOUT_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKOUT_DFSDM2) || \
((SELECTION) == HAL_DFSDM2_CKOUT_M27) || \
((SELECTION) == HAL_DFSDM1_CKOUT_DFSDM1) || \
((SELECTION) == HAL_DFSDM1_CKOUT_M27))
((SELECTION) == HAL_DFSDM1_CKOUT_M27))
#define IS_DFSDM_DATAIN0_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN0_DFSDM2_PAD) || \
((SELECTION) == HAL_DATAIN0_DFSDM2_DATAIN1) || \
((SELECTION) == HAL_DATAIN0_DFSDM1_PAD) || \
@@ -1084,16 +1084,16 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source);
#define IS_DFSDM_DFSDM1_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM1_CKOUT_DFSDM2_CKOUT) || \
((CLKOUT) == DFSDM1_CKOUT_DFSDM1))
#define IS_DFSDM_DFSDM2_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM2_CKOUT_DFSDM2_CKOUT) || \
((CLKOUT) == DFSDM2_CKOUT_DFSDM2))
((CLKOUT) == DFSDM2_CKOUT_DFSDM2))
#define IS_DFSDM_DFSDM1_CLKIN(CLKIN) (((CLKIN) == DFSDM1_CKIN_DFSDM2_CKOUT) || \
((CLKIN) == DFSDM1_CKIN_PAD))
((CLKIN) == DFSDM1_CKIN_PAD))
#define IS_DFSDM_DFSDM2_CLKIN(CLKIN) (((CLKIN) == DFSDM2_CKIN_DFSDM2_CKOUT) || \
((CLKIN) == DFSDM2_CKIN_PAD))
#define IS_DFSDM_DFSDM1_BIT_CLK(CLK) (((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN0) || \
((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN2) || \
((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN3) || \
((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN1) || \
((CLK) <= 0x30U))
((CLK) <= 0x30U))
#define IS_DFSDM_DFSDM2_BIT_CLK(CLK) (((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN0) || \
((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN4) || \
@@ -1103,14 +1103,14 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source);
((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN2) || \
((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN3) || \
((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN7)|| \
((CLK) <= 0x1E000U))
((CLK) <= 0x1E000U))
#define IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN0_PAD )|| \
((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN1_PAD) || \
((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN2_PAD) || \
((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN3_PAD)|| \
((DISTRIBUTION) <= 0xCU))
((DISTRIBUTION) <= 0xCU))
#define IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN0_PAD)|| \
((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN1_PAD)|| \
((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN2_PAD)|| \
@@ -1119,16 +1119,16 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source);
((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN5_PAD)|| \
((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN6_PAD)|| \
((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN7_PAD)|| \
((DISTRIBUTION) <= 0x1D00U))
((DISTRIBUTION) <= 0x1D00U))
#endif /* (SYSCFG_MCHDLYCR_BSCKSEL) */
/**
* @}
*/
*/
/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
*/
/**
* @}

8
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h
View File

@@ -448,9 +448,9 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
@@ -487,8 +487,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t
*/
/* Peripheral State functions ***************************************************/
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d);
uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d);
/**
* @}

18
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h
View File

@@ -976,7 +976,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
/* Delay after an DSI warpper enabling */ \
/* Delay after an DSI wrapper enabling */ \
tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
UNUSED(tmpreg); \
} while(0U)
@@ -989,7 +989,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
__IO uint32_t tmpreg = 0x00U; \
CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
/* Delay after an DSI warpper disabling*/ \
/* Delay after an DSI wrapper disabling*/ \
tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
UNUSED(tmpreg); \
} while(0U)
@@ -1184,7 +1184,7 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
uint32_t Mode,
uint32_t NbParams,
uint32_t Param1,
uint8_t *ParametersTable);
const uint8_t *ParametersTable);
HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
uint32_t ChannelNbr,
uint8_t *Array,
@@ -1222,8 +1222,8 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun
* @brief Peripheral State and Errors functions
* @{
*/
uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi);
HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi);
/**
* @}
@@ -1271,10 +1271,10 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
|| ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\
|| ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\
|| ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\
|| ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
#define IS_DSI_VSYNC_POLARITY(Vsync) (((Vsync) == DSI_VSYNC_ACTIVE_HIGH)\
|| ((Vsync) == DSI_VSYNC_ACTIVE_LOW))
#define IS_DSI_HSYNC_POLARITY(Hsync) (((Hsync) == DSI_HSYNC_ACTIVE_HIGH)\
|| ((Hsync) == DSI_HSYNC_ACTIVE_LOW))
#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
((VideoModeType) == DSI_VID_MODE_BURST))

301
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h
View File

@@ -24,7 +24,6 @@
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -99,7 +98,7 @@ typedef struct
uint32_t *PacketAddress[ETH_TX_DESC_CNT]; /*<! Ethernet packet addresses array */
uint32_t *CurrentPacketAddress; /*<! Current transmit NX_PACKET addresses */
uint32_t *CurrentPacketAddress; /*<! Current transmit packet addresses */
uint32_t BuffersInUse; /*<! Buffers in Use */
@@ -153,7 +152,7 @@ typedef struct
void *pData; /*!< Specifies Application packet pointer to save */
} ETH_TxPacketConfig;
} ETH_TxPacketConfigTypeDef;
/**
*
*/
@@ -171,6 +170,7 @@ typedef struct
*
*/
#ifdef HAL_ETH_USE_PTP
/**
* @brief ETH Timeupdate structure definition
*/
@@ -182,6 +182,7 @@ typedef struct
/**
*
*/
#endif /* HAL_ETH_USE_PTP */
/**
* @brief DMA Receive Descriptors Wrapper structure definition
@@ -347,7 +348,6 @@ typedef struct
uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers.
This parameter can be a value of @ref ETH_Burst_Mode */
FunctionalState DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames */
FunctionalState ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode */
@@ -407,6 +407,7 @@ typedef enum
*
*/
#ifdef HAL_ETH_USE_PTP
/**
* @brief HAL ETH PTP Update type enum definition
*/
@@ -418,13 +419,13 @@ typedef enum
/**
*
*/
#endif /* HAL_ETH_USE_PTP */
/**
* @brief ETH Init Structure definition
*/
typedef struct
{
uint8_t
*MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
@@ -443,6 +444,7 @@ typedef struct
*
*/
#ifdef HAL_ETH_USE_PTP
/**
* @brief ETH PTP Init Structure definition
*/
@@ -470,6 +472,7 @@ typedef struct
/**
*
*/
#endif /* HAL_ETH_USE_PTP */
/**
* @brief HAL State structures definition
@@ -538,7 +541,7 @@ typedef struct
__IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management
and also related to Tx operations. This parameter can
be a value of @ref HAL_ETH_StateTypeDef */
be a value of @ref ETH_State_Codes */
__IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine
This parameter can be a value of @ref ETH_Error_Code.*/
@@ -595,14 +598,12 @@ typedef enum
{
HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */
HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */
HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
HAL_ETH_ERROR_CB_ID = 0x04U, /*!< ETH Error Callback ID */
HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */
HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */
} HAL_ETH_CallbackIDTypeDef;
/**
@@ -753,7 +754,6 @@ TDES7 | Transmit Time Stamp High [31:0]
* @}
*/
/** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
* @{
*/
@@ -913,15 +913,6 @@ TDES7 | Transmit Time Stamp High [31:0]
* @}
*/
/** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control
* @{
*/
#define ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE
#define ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT
#define ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE
/**
* @}
*/
/** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
* @{
@@ -944,28 +935,6 @@ TDES7 | Transmit Time Stamp High [31:0]
* @}
*/
/** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control
* @{
*/
#define ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE
#define ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE
#define ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT
#define ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE
/**
* @}
*/
/** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control
* @{
*/
#define ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE
#define ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE
#define ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT
#define ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE
/**
* @}
*/
/** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
* @{
@@ -993,15 +962,11 @@ TDES7 | Transmit Time Stamp High [31:0]
/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
* @{
*/
#define ETH_DMAARBITRATION_RX ETH_DMAMR_DA
#define ETH_DMAARBITRATION_RX ETH_DMABMR_DA
#define ETH_DMAARBITRATION_RX1_TX1 0x00000000U
#define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1
#define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1
#define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1
#define ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1
#define ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1
#define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1
#define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1
#define ETH_DMAARBITRATION_RX2_TX1 ETH_DMABMR_RTPR_2_1
#define ETH_DMAARBITRATION_RX3_TX1 ETH_DMABMR_RTPR_3_1
#define ETH_DMAARBITRATION_RX4_TX1 ETH_DMABMR_RTPR_4_1
#define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
#define ETH_DMAARBITRATION_TX1_RX1 0x00000000U
#define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
@@ -1066,19 +1031,18 @@ TDES7 | Transmit Time Stamp High [31:0]
/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
* @{
*/
#define ETH_DMA_NORMAL_IT ETH_DMACIER_NIE
#define ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE
#define ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE
#define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE
#define ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE
#define ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE
#define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE
#define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE
#define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE
#define ETH_DMA_RX_IT ETH_DMACIER_RIE
#define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE
#define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE
#define ETH_DMA_TX_IT ETH_DMACIER_TIE
#define ETH_DMA_NORMAL_IT ETH_DMAIER_NISE
#define ETH_DMA_ABNORMAL_IT ETH_DMAIER_AISE
#define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMAIER_FBEIE
#define ETH_DMA_EARLY_RX_IT ETH_DMAIER_ERIE
#define ETH_DMA_EARLY_TX_IT ETH_DMAIER_ETIE
#define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMAIER_RWTIE
#define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMAIER_RPSIE
#define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMAIER_RBUIE
#define ETH_DMA_RX_IT ETH_DMAIER_RIE
#define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMAIER_TBUIE
#define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMAIER_TPSIE
#define ETH_DMA_TX_IT ETH_DMAIER_TIE
/**
* @}
*/
@@ -1086,23 +1050,19 @@ TDES7 | Transmit Time Stamp High [31:0]
/** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
* @{
*/
#define ETH_DMA_RX_NO_ERROR_FLAG 0x00000000U
#define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
#define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
#define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
#define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2
#define ETH_DMA_TX_NO_ERROR_FLAG 0x00000000U
#define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
#define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
#define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
#define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2
#define ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE
#define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE
#define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI
#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT
#define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS
#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU
#define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS
#define ETH_DMA_NO_ERROR_FLAG 0x00000000U
#define ETH_DMA_TX_DATA_TRANS_ERROR_FLAG ETH_DMASR_EBS_DataTransfTx
#define ETH_DMA_RX_DATA_TRANS_ERROR_FLAG 0x00000000U
#define ETH_DMA_READ_TRANS_ERROR_FLAG ETH_DMASR_EBS_ReadTransf
#define ETH_DMA_WRITE_TRANS_ERROR_FLAG 0x00000000U
#define ETH_DMA_DESC_ACCESS_ERROR_FLAG ETH_DMASR_EBS_DescAccess
#define ETH_DMA_DATA_BUFF_ACCESS_ERROR_FLAG 0x00000000U
#define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMASR_FBES
#define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMASR_ETS
#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMASR_RWTS
#define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMASR_RPSS
#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMASR_RBUS
#define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMASR_TPS
/**
* @}
*/
@@ -1110,15 +1070,15 @@ TDES7 | Transmit Time Stamp High [31:0]
/** @defgroup ETH_Transmit_Mode ETH Transmit Mode
* @{
*/
#define ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF
#define ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS
#define ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS
#define ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS
#define ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS
#define ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS
#define ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS
#define ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS
#define ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS
#define ETH_TRANSMITSTOREFORWARD ETH_DMAOMR_TSF
#define ETH_TRANSMITTHRESHOLD_16 ETH_DMAOMR_TTC_16Bytes
#define ETH_TRANSMITTHRESHOLD_24 ETH_DMAOMR_TTC_24Bytes
#define ETH_TRANSMITTHRESHOLD_32 ETH_DMAOMR_TTC_32Bytes
#define ETH_TRANSMITTHRESHOLD_40 ETH_DMAOMR_TTC_40Bytes
#define ETH_TRANSMITTHRESHOLD_64 ETH_DMAOMR_TTC_64Bytes
#define ETH_TRANSMITTHRESHOLD_128 ETH_DMAOMR_TTC_128Bytes
#define ETH_TRANSMITTHRESHOLD_192 ETH_DMAOMR_TTC_192Bytes
#define ETH_TRANSMITTHRESHOLD_256 ETH_DMAOMR_TTC_256Bytes
/**
* @}
*/
@@ -1126,11 +1086,11 @@ TDES7 | Transmit Time Stamp High [31:0]
/** @defgroup ETH_Receive_Mode ETH Receive Mode
* @{
*/
#define ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF
#define ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS
#define ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS
#define ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS
#define ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS
#define ETH_RECEIVESTOREFORWARD ETH_DMAOMR_RSF
#define ETH_RECEIVETHRESHOLD8_64 ETH_DMAOMR_RTC_64Bytes
#define ETH_RECEIVETHRESHOLD8_32 ETH_DMAOMR_RTC_32Bytes
#define ETH_RECEIVETHRESHOLD8_96 ETH_DMAOMR_RTC_96Bytes
#define ETH_RECEIVETHRESHOLD8_128 ETH_DMAOMR_RTC_128Bytes
/**
* @}
*/
@@ -1138,52 +1098,14 @@ TDES7 | Transmit Time Stamp High [31:0]
/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
* @{
*/
#define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4
#define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28
#define ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36
#define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144
#define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256
#define ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512
#define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACFCR_PLT_Minus4
#define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACFCR_PLT_Minus28
#define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACFCR_PLT_Minus144
#define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACFCR_PLT_Minus256
/**
* @}
*/
/** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
* @{
*/
#define ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB
#define ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB
#define ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB
#define ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB
#define ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB
#define ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB
#define ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB
#define ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB
#define ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB
#define ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB
#define ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB
#define ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB
#define ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB
#define ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB
#define ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB
/**
* @}
*/
/** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
* @{
*/
#define ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT
#define ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT
#define ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT
#define ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT
#define ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT
#define ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT
#define ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT
#define ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT
/**
* @}
*/
/** @defgroup ETH_Speed ETH Speed
* @{
@@ -1214,15 +1136,6 @@ TDES7 | Transmit Time Stamp High [31:0]
* @}
*/
/** @defgroup ETH_Preamble_Length ETH Preamble Length
* @{
*/
#define ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7
#define ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5
#define ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3
/**
* @}
*/
/** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
* @{
@@ -1236,16 +1149,6 @@ TDES7 | Transmit Time Stamp High [31:0]
* @}
*/
/** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
* @{
*/
#define ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL
#define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
#define ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL
#define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
/**
* @}
*/
/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
* @{
@@ -1278,33 +1181,20 @@ TDES7 | Transmit Time Stamp High [31:0]
/** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
* @{
*/
#define ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD
#define ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD
#define ETH_WAKEUP_FRAME_RECIEVED ETH_MACPMTCSR_WFR
#define ETH_MAGIC_PACKET_RECIEVED ETH_MACPMTCSR_MPR
/**
* @}
*/
/** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status
* @{
*/
#define ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT
#define ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL
#define ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL
#define ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF
#define ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR
#define ETH_NO_CARRIER ETH_MACRXTXSR_NCARR
#define ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT
/**
* @}
*/
/** @defgroup HAL_ETH_StateTypeDef ETH States
/** @defgroup ETH_State_Codes ETH States
* @{
*/
#define HAL_ETH_STATE_RESET 0x00000000U /*!< Peripheral not yet Initialized or disabled */
#define HAL_ETH_STATE_READY 0x00000010U /*!< Peripheral Communication started */
#define HAL_ETH_STATE_BUSY 0x00000023U /*!< an internal process is ongoing */
#define HAL_ETH_STATE_STARTED 0x00000023U /*!< an internal process is started */
#define HAL_ETH_STATE_BUSY 0x00000020U /*!< an internal process is ongoing */
#define HAL_ETH_STATE_STARTED 0x00000040U /*!< an internal process is started */
#define HAL_ETH_STATE_ERROR 0x000000E0U /*!< Error State */
/**
* @}
@@ -1802,11 +1692,12 @@ TDES7 | Transmit Time Stamp High [31:0]
/** @defgroup ETH_PTP_Config_Status ETH PTP Config Status
* @{
*/
#define HAL_ETH_PTP_NOT_CONFIGURATED 0x00000000U /*!< ETH PTP Configuration not done */
#define HAL_ETH_PTP_CONFIGURATED 0x00000001U /*!< ETH PTP Configuration done */
#define HAL_ETH_PTP_NOT_CONFIGURED 0x00000000U /*!< ETH PTP Configuration not done */
#define HAL_ETH_PTP_CONFIGURED 0x00000001U /*!< ETH PTP Configuration done */
/**
* @}
*/
/**
* @}
*/
@@ -1884,7 +1775,7 @@ TDES7 | Transmit Time Stamp High [31:0]
* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
* @retval The state of ETH DMA FLAG (SET or RESET).
*/
#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &\
#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &\
( __FLAG__)) == ( __FLAG__))
/**
@@ -1893,27 +1784,8 @@ TDES7 | Transmit Time Stamp High [31:0]
* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
* @retval The state of ETH DMA FLAG (SET or RESET).
*/
#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = ( __FLAG__))
/**
* @brief Enables the specified ETHERNET MAC interrupts.
* @param __HANDLE__ : ETH Handle
* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
* enabled @ref ETH_MAC_Interrupts
* @retval None
*/
#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER \
|= (__INTERRUPT__))
/**
* @brief Disables the specified ETHERNET MAC interrupts.
* @param __HANDLE__ : ETH Handle
* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
* enabled @ref ETH_MAC_Interrupts
* @retval None
*/
#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER \
&= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified ETHERNET MAC flag is set or not.
@@ -1921,8 +1793,8 @@ TDES7 | Transmit Time Stamp High [31:0]
* @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
* @retval The state of ETH MAC IT (SET or RESET).
*/
#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACSR &\
( __INTERRUPT__)) == ( __INTERRUPT__))
#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACSR &\
( __INTERRUPT__)) == ( __INTERRUPT__))
/*!< External interrupt line 19 Connected to the ETH wakeup EXTI Line */
#define ETH_WAKEUP_EXTI_LINE 0x00080000U
@@ -1951,7 +1823,6 @@ TDES7 | Transmit Time Stamp High [31:0]
*/
#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
/**
* @brief enable rising edge interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
@@ -1991,6 +1862,7 @@ TDES7 | Transmit Time Stamp High [31:0]
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->PTPTSCR |= (__FLAG__))
/**
* @}
*/
@@ -2037,7 +1909,7 @@ HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback);
HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback);
HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth);
@@ -2056,10 +1928,10 @@ HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_tx
HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth);
#endif /* HAL_ETH_USE_PTP */
HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout);
HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig);
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
uint32_t RegValue);
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
uint32_t *pRegValue);
@@ -2083,8 +1955,8 @@ void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *ti
*/
/* Peripheral Control functions **********************************************/
/* MAC & DMA Configuration APIs **********************************************/
HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
@@ -2094,13 +1966,15 @@ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t
uint32_t VLANIdentifier);
/* MAC L2 Packet Filtering APIs **********************************************/
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig);
HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);
HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
const uint8_t *pMACAddr);
/* MAC Power Down APIs *****************************************************/
void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);
void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth,
const ETH_PowerDownConfigTypeDef *pPowerDownConfig);
void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
@@ -2112,11 +1986,12 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi
* @{
*/
/* Peripheral State functions **************************************************/
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth);
uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth);
uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth);
uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth);
uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth);
uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth);
uint32_t HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth);
/**
* @}
*/
@@ -2140,5 +2015,3 @@ uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
#endif
#endif /* STM32F4xx_HAL_ETH_H */

156
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h
View File

@@ -13,14 +13,14 @@
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_FLASH_H
#define __STM32F4xx_HAL_FLASH_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -32,46 +32,46 @@
/** @addtogroup FLASH
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Types FLASH Exported Types
* @{
*/
/**
* @brief FLASH Procedure structure definition
*/
typedef enum
typedef enum
{
FLASH_PROC_NONE = 0U,
FLASH_PROC_NONE = 0U,
FLASH_PROC_SECTERASE,
FLASH_PROC_MASSERASE,
FLASH_PROC_PROGRAM
} FLASH_ProcedureTypeDef;
/**
* @brief FLASH handle Structure definition
/**
* @brief FLASH handle Structure definition
*/
typedef struct
{
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/
__IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to erase in IT context*/
__IO uint8_t VoltageForErase; /*Internal variable to provide voltage range selected by user in IT context*/
__IO uint32_t Sector; /*Internal variable to define the current sector which is erasing*/
__IO uint32_t Bank; /*Internal variable to save current bank selected during mass erase*/
__IO uint32_t Address; /*Internal variable to save address selected for program*/
HAL_LockTypeDef Lock; /* FLASH locking object */
__IO uint32_t ErrorCode; /* FLASH error code */
}FLASH_ProcessTypeDef;
} FLASH_ProcessTypeDef;
/**
* @}
@@ -80,11 +80,11 @@ typedef struct
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{
*/
*/
/** @defgroup FLASH_Error_Code FLASH Error Code
* @brief FLASH Error Code
* @brief FLASH Error Code
* @{
*/
*/
#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_FLASH_ERROR_RD 0x00000001U /*!< Read Protection error */
#define HAL_FLASH_ERROR_PGS 0x00000002U /*!< Programming Sequence error */
@@ -95,10 +95,10 @@ typedef struct
/**
* @}
*/
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
*/
#define FLASH_TYPEPROGRAM_BYTE 0x00000000U /*!< Program byte (8-bit) at a specified address */
#define FLASH_TYPEPROGRAM_HALFWORD 0x00000001U /*!< Program a half-word (16-bit) at a specified address */
#define FLASH_TYPEPROGRAM_WORD 0x00000002U /*!< Program a word (32-bit) at a specified address */
@@ -110,7 +110,7 @@ typedef struct
/** @defgroup FLASH_Flag_definition FLASH Flag definition
* @brief Flag definition
* @{
*/
*/
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
#define FLASH_FLAG_OPERR FLASH_SR_SOP /*!< FLASH operation Error flag */
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
@@ -120,20 +120,20 @@ typedef struct
#if defined(FLASH_SR_RDERR)
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read Protection error flag (PCROP) */
#endif /* FLASH_SR_RDERR */
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
/**
* @}
*/
/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
* @brief FLASH Interrupt definition
* @{
*/
*/
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
#define FLASH_IT_ERR 0x02000000U /*!< Error Interrupt source */
/**
* @}
*/
*/
/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
* @{
@@ -145,11 +145,11 @@ typedef struct
#define CR_PSIZE_MASK 0xFFFFFCFFU
/**
* @}
*/
*/
/** @defgroup FLASH_Keys FLASH Keys
* @{
*/
*/
#define RDP_KEY ((uint16_t)0x00A5)
#define FLASH_KEY1 0x45670123U
#define FLASH_KEY2 0xCDEF89ABU
@@ -157,12 +157,12 @@ typedef struct
#define FLASH_OPT_KEY2 0x4C5D6E7FU
/**
* @}
*/
*/
/**
* @}
*/
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
* @{
@@ -172,102 +172,102 @@ typedef struct
* @param __LATENCY__ FLASH Latency
* The value of this parameter depend on device used within the same series
* @retval none
*/
*/
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
/**
* @brief Get the FLASH Latency.
* @retval FLASH Latency
* The value of this parameter depend on device used within the same series
*/
*/
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
/**
* @brief Enable the FLASH prefetch buffer.
* @retval none
*/
*/
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
/**
* @brief Disable the FLASH prefetch buffer.
* @retval none
*/
*/
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
/**
* @brief Enable the FLASH instruction cache.
* @retval none
*/
*/
#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN)
/**
* @brief Disable the FLASH instruction cache.
* @retval none
*/
*/
#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN))
/**
* @brief Enable the FLASH data cache.
* @retval none
*/
*/
#define __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN)
/**
* @brief Disable the FLASH data cache.
* @retval none
*/
*/
#define __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN))
/**
* @brief Resets the FLASH instruction Cache.
* @note This function must be used only when the Instruction Cache is disabled.
* @note This function must be used only when the Instruction Cache is disabled.
* @retval None
*/
#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \
FLASH->ACR &= ~FLASH_ACR_ICRST; \
FLASH->ACR &= ~FLASH_ACR_ICRST; \
}while(0U)
/**
* @brief Resets the FLASH data Cache.
* @note This function must be used only when the data Cache is disabled.
* @note This function must be used only when the data Cache is disabled.
* @retval None
*/
#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \
FLASH->ACR &= ~FLASH_ACR_DCRST; \
FLASH->ACR &= ~FLASH_ACR_DCRST; \
}while(0U)
/**
* @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ FLASH interrupt
* @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
* @arg FLASH_IT_ERR: Error Interrupt
* @arg FLASH_IT_ERR: Error Interrupt
* @retval none
*/
*/
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
/**
* @brief Disable the specified FLASH interrupt.
* @param __INTERRUPT__ FLASH interrupt
* @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
* @arg FLASH_IT_ERR: Error Interrupt
* @arg FLASH_IT_ERR: Error Interrupt
* @retval none
*/
*/
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
/**
* @brief Get the specified FLASH flag status.
* @brief Get the specified FLASH flag status.
* @param __FLAG__ specifies the FLASH flags to check.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
* @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)
* @arg FLASH_FLAG_BSY : FLASH Busy flag
* (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices
* (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))
@@ -276,14 +276,14 @@ typedef struct
* @brief Clear the specified FLASH flags.
* @param __FLAG__ specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
* @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)
* (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices
* (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices
* @retval none
*/
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
@@ -307,7 +307,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
/* FLASH IRQ handler method */
void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */
/* Callbacks in non blocking modes */
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
/**
@@ -340,7 +340,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @}
*/
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
@@ -355,25 +355,25 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
* @{
*/
/**
* @brief ACR register byte 0 (Bits[7:0]) base address
*/
#define ACR_BYTE0_ADDRESS 0x40023C00U
/**
* @brief OPTCR register byte 0 (Bits[7:0]) base address
*/
/**
* @brief ACR register byte 0 (Bits[7:0]) base address
*/
#define ACR_BYTE0_ADDRESS 0x40023C00U
/**
* @brief OPTCR register byte 0 (Bits[7:0]) base address
*/
#define OPTCR_BYTE0_ADDRESS 0x40023C14U
/**
* @brief OPTCR register byte 1 (Bits[15:8]) base address
*/
/**
* @brief OPTCR register byte 1 (Bits[15:8]) base address
*/
#define OPTCR_BYTE1_ADDRESS 0x40023C15U
/**
* @brief OPTCR register byte 2 (Bits[23:16]) base address
*/
/**
* @brief OPTCR register byte 2 (Bits[23:16]) base address
*/
#define OPTCR_BYTE2_ADDRESS 0x40023C16U
/**
* @brief OPTCR register byte 3 (Bits[31:24]) base address
*/
/**
* @brief OPTCR register byte 3 (Bits[31:24]) base address
*/
#define OPTCR_BYTE3_ADDRESS 0x40023C17U
/**
@@ -391,7 +391,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
/**
* @}
*/
@@ -411,7 +411,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @}
*/
*/
/**
* @}

184
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h
View File

@@ -13,14 +13,14 @@
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_FLASH_EX_H
#define __STM32F4xx_HAL_FLASH_EX_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -32,7 +32,7 @@
/** @addtogroup FLASHEx
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
@@ -76,7 +76,7 @@ typedef struct
The value of this parameter depend on device used within the same series */
uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
This parameter must be a value of @ref FLASHEx_Banks */
This parameter must be a value of @ref FLASHEx_Banks */
uint32_t RDPLevel; /*!< Set the read protection level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
@@ -125,7 +125,7 @@ typedef struct
This parameter can be a value of @ref FLASHEx_Dual_Boot */
#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
}FLASH_AdvOBProgramInitTypeDef;
} FLASH_AdvOBProgramInitTypeDef;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx ||
STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
/**
@@ -140,16 +140,16 @@ typedef struct
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
* @{
*/
*/
#define FLASH_TYPEERASE_SECTORS 0x00000000U /*!< Sectors erase only */
#define FLASH_TYPEERASE_MASSERASE 0x00000001U /*!< Flash Mass erase activation */
/**
* @}
*/
/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
* @{
*/
*/
#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Device operating range: 1.8V to 2.1V */
#define FLASH_VOLTAGE_RANGE_2 0x00000001U /*!< Device operating range: 2.1V to 2.7V */
#define FLASH_VOLTAGE_RANGE_3 0x00000002U /*!< Device operating range: 2.7V to 3.6V */
@@ -157,19 +157,19 @@ typedef struct
/**
* @}
*/
/** @defgroup FLASHEx_WRP_State FLASH WRP State
* @{
*/
*/
#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */
#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Type FLASH Option Type
* @{
*/
*/
#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */
#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */
#define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */
@@ -177,7 +177,7 @@ typedef struct
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
* @{
*/
@@ -187,39 +187,39 @@ typedef struct
it s no more possible to go back to level 1 or 0 */
/**
* @}
*/
*/
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
* @{
*/
*/
#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
/**
* @}
*/
*/
/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
* @{
*/
*/
#define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
/**
* @}
*/
*/
/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
* @{
*/
*/
#define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
/**
* @}
*/
*/
/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
* @{
*/
*/
#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
@@ -235,7 +235,7 @@ typedef struct
defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
* @{
*/
*/
#define OB_PCROP_STATE_DISABLE 0x00000000U /*!< Disable PCROP */
#define OB_PCROP_STATE_ENABLE 0x00000001U /*!< Enable PCROP */
/**
@@ -247,7 +247,7 @@ typedef struct
/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type
* @{
*/
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#define OPTIONBYTE_PCROP 0x00000001U /*!< PCROP option byte configuration */
@@ -268,7 +268,7 @@ typedef struct
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
/*------------------------- STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx ----------------------*/
/*------------------------- STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx ----------------------*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
@@ -290,12 +290,12 @@ typedef struct
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/*--------------------------------------------------------------------------------------------------------------*/
/*-------------------------- STM32F40xxx/STM32F41xxx/STM32F401xx/STM32F411xx/STM32F423xx -----------------------*/
/*-------------------------- STM32F40xxx/STM32F41xxx/STM32F401xx/STM32F411xx/STM32F423xx -----------------------*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
@@ -310,8 +310,8 @@ typedef struct
/**
* @}
*/
*/
/** @defgroup FLASHEx_Banks FLASH Banks
* @{
@@ -333,8 +333,8 @@ typedef struct
STM32F413xx || STM32F423xx */
/**
* @}
*/
*/
/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
* @{
*/
@@ -353,12 +353,12 @@ typedef struct
STM32F413xx || STM32F423xx */
/**
* @}
*/
*/
/** @defgroup FLASHEx_Sectors FLASH Sectors
* @{
*/
/*-------------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx ------------------------------------*/
/*-------------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx ------------------------------------*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
@@ -388,7 +388,7 @@ typedef struct
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
/*-----------------------------------------------------------------------------------------------------*/
/*-------------------------------------- STM32F413xx/STM32F423xx --------------------------------------*/
/*-------------------------------------- STM32F413xx/STM32F423xx --------------------------------------*/
#if defined(STM32F413xx) || defined(STM32F423xx)
#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
@@ -407,11 +407,11 @@ typedef struct
#define FLASH_SECTOR_14 14U /*!< Sector Number 14 */
#define FLASH_SECTOR_15 15U /*!< Sector Number 15 */
#endif /* STM32F413xx || STM32F423xx */
/*-----------------------------------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------------------------------*/
/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */
@@ -427,7 +427,7 @@ typedef struct
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
/*-----------------------------------------------------------------------------------------------------*/
/*--------------------------------------------- STM32F401xC -------------------------------------------*/
/*--------------------------------------------- STM32F401xC -------------------------------------------*/
#if defined(STM32F401xC)
#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
@@ -438,7 +438,7 @@ typedef struct
#endif /* STM32F401xC */
/*-----------------------------------------------------------------------------------------------------*/
/*--------------------------------------------- STM32F410xx -------------------------------------------*/
/*--------------------------------------------- STM32F410xx -------------------------------------------*/
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
@@ -463,14 +463,14 @@ typedef struct
/**
* @}
*/
*/
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @{
*/
/*--------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx -------------------------*/
/*--------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx -------------------------*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
defined(STM32F469xx) || defined(STM32F479xx)
#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
@@ -499,8 +499,8 @@ typedef struct
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
/*-----------------------------------------------------------------------------------------------------*/
/*--------------------------------------- STM32F413xx/STM32F423xx -------------------------------------*/
#if defined(STM32F413xx) || defined(STM32F423xx)
/*--------------------------------------- STM32F413xx/STM32F423xx -------------------------------------*/
#if defined(STM32F413xx) || defined(STM32F423xx)
#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
@@ -516,14 +516,14 @@ typedef struct
#define OB_WRP_SECTOR_12 0x00001000U /*!< Write protection of Sector12 */
#define OB_WRP_SECTOR_13 0x00002000U /*!< Write protection of Sector13 */
#define OB_WRP_SECTOR_14 0x00004000U /*!< Write protection of Sector14 */
#define OB_WRP_SECTOR_15 0x00004000U /*!< Write protection of Sector15 */
#define OB_WRP_SECTOR_15 0x00004000U /*!< Write protection of Sector15 */
#define OB_WRP_SECTOR_All 0x00007FFFU /*!< Write protection of all Sectors */
#endif /* STM32F413xx || STM32F423xx */
/*-----------------------------------------------------------------------------------------------------*/
/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
/*-----------------------------------------------------------------------------------------------------*/
/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
@@ -551,7 +551,7 @@ typedef struct
#define OB_WRP_SECTOR_All 0x00000FFFU /*!< Write protection of all Sectors */
#endif /* STM32F401xC */
/*-----------------------------------------------------------------------------------------------------*/
/*--------------------------------------------- STM32F410xx -------------------------------------------*/
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
@@ -579,13 +579,13 @@ typedef struct
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection
* @{
*/
/*-------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx ---------------------------*/
/*-------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx ---------------------------*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
defined(STM32F469xx) || defined(STM32F479xx)
#define OB_PCROP_SECTOR_0 0x00000001U /*!< PC Read/Write protection of Sector0 */
#define OB_PCROP_SECTOR_1 0x00000002U /*!< PC Read/Write protection of Sector1 */
#define OB_PCROP_SECTOR_2 0x00000004U /*!< PC Read/Write protection of Sector2 */
@@ -613,9 +613,9 @@ typedef struct
#define OB_PCROP_SECTOR_All 0x00000FFFU /*!< PC Read/Write protection of all Sectors */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
/*-----------------------------------------------------------------------------------------------------*/
/*------------------------------------- STM32F413xx/STM32F423xx ---------------------------------------*/
#if defined(STM32F413xx) || defined(STM32F423xx)
#if defined(STM32F413xx) || defined(STM32F423xx)
#define OB_PCROP_SECTOR_0 0x00000001U /*!< PC Read/Write protection of Sector0 */
#define OB_PCROP_SECTOR_1 0x00000002U /*!< PC Read/Write protection of Sector1 */
#define OB_PCROP_SECTOR_2 0x00000004U /*!< PC Read/Write protection of Sector2 */
@@ -631,10 +631,10 @@ typedef struct
#define OB_PCROP_SECTOR_12 0x00001000U /*!< PC Read/Write protection of Sector12 */
#define OB_PCROP_SECTOR_13 0x00002000U /*!< PC Read/Write protection of Sector13 */
#define OB_PCROP_SECTOR_14 0x00004000U /*!< PC Read/Write protection of Sector14 */
#define OB_PCROP_SECTOR_15 0x00004000U /*!< PC Read/Write protection of Sector15 */
#define OB_PCROP_SECTOR_15 0x00004000U /*!< PC Read/Write protection of Sector15 */
#define OB_PCROP_SECTOR_All 0x00007FFFU /*!< PC Read/Write protection of all Sectors */
#endif /* STM32F413xx || STM32F423xx */
/*-----------------------------------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------------------------------*/
/*--------------------------------------------- STM32F401xC -------------------------------------------*/
#if defined(STM32F401xC)
@@ -661,7 +661,7 @@ typedef struct
/*-------------- STM32F401xE/STM32F411xE/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F446xx --*/
#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
#define OB_PCROP_SECTOR_0 0x00000001U /*!< PC Read/Write protection of Sector0 */
#define OB_PCROP_SECTOR_1 0x00000002U /*!< PC Read/Write protection of Sector1 */
#define OB_PCROP_SECTOR_2 0x00000004U /*!< PC Read/Write protection of Sector2 */
@@ -677,12 +677,12 @@ typedef struct
/**
* @}
*/
/** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot
* @{
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
defined(STM32F469xx) || defined(STM32F479xx)
#define OB_DUAL_BOOT_ENABLE ((uint8_t)0x10) /*!< Dual Bank Boot Enable */
#define OB_DUAL_BOOT_DISABLE ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
@@ -709,8 +709,8 @@ typedef struct
/**
* @}
*/
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
@@ -732,7 +732,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
@@ -757,7 +757,7 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
/** @defgroup FLASHEx_Private_Constants FLASH Private Constants
* @{
*/
/*--------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx---------------------*/
/*--------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx---------------------*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define FLASH_SECTOR_TOTAL 24U
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
@@ -767,18 +767,18 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
#define FLASH_SECTOR_TOTAL 16U
#endif /* STM32F413xx || STM32F423xx */
/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
#define FLASH_SECTOR_TOTAL 12U
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
/*--------------------------------------------- STM32F401xC -------------------------------------------*/
/*--------------------------------------------- STM32F401xC -------------------------------------------*/
#if defined(STM32F401xC)
#define FLASH_SECTOR_TOTAL 6U
#endif /* STM32F401xC */
/*--------------------------------------------- STM32F410xx -------------------------------------------*/
/*--------------------------------------------- STM32F410xx -------------------------------------------*/
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
#define FLASH_SECTOR_TOTAL 5U
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
@@ -788,10 +788,10 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
#define FLASH_SECTOR_TOTAL 8U
#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
/**
* @brief OPTCR1 register byte 2 (Bits[23:16]) base address
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief OPTCR1 register byte 2 (Bits[23:16]) base address
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define OPTCR1_BYTE2_ADDRESS 0x40023C1AU
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
@@ -809,15 +809,15 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
*/
#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
((VALUE) == FLASH_TYPEERASE_MASSERASE))
((VALUE) == FLASH_TYPEERASE_MASSERASE))
#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
((RANGE) == FLASH_VOLTAGE_RANGE_4))
((RANGE) == FLASH_VOLTAGE_RANGE_4))
#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
((VALUE) == OB_WRPSTATE_ENABLE))
((VALUE) == OB_WRPSTATE_ENABLE))
#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
@@ -840,7 +840,7 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
#define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \
((VALUE) == OB_PCROP_STATE_ENABLE))
((VALUE) == OB_PCROP_STATE_ENABLE))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
@@ -848,17 +848,17 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP) || \
((VALUE) == OPTIONBYTE_BOOTCONFIG))
((VALUE) == OPTIONBYTE_BOOTCONFIG))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
defined(STM32F423xx)
#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP))
#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP))
#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx ||\
STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
@@ -908,7 +908,7 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx ||\
STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
@@ -936,7 +936,7 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
#endif /* STM32F413xx || STM32F423xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
@@ -968,12 +968,12 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
(((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFF000000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#if defined(STM32F413xx) || defined(STM32F423xx)
#if defined(STM32F413xx) || defined(STM32F423xx)
#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#endif /* STM32F413xx || STM32F423xx */
@@ -990,16 +990,16 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Rx) || defined(STM32F412Cx)
#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#if defined(STM32F413xx) || defined(STM32F423xx)
#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#endif /* STM32F413xx || STM32F423xx */
#if defined(STM32F401xC)
@@ -1011,12 +1011,12 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Rx) || defined(STM32F412Cx)
#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
defined(STM32F469xx) || defined(STM32F479xx)
#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
@@ -1045,11 +1045,11 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
void FLASH_FlushCaches(void);
/**
* @}
*/
*/
/**
* @}
*/
*/
/**
* @}

14
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h
View File

@@ -13,17 +13,17 @@
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_FLASH_RAMFUNC_H
#define __STM32F4xx_FLASH_RAMFUNC_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -45,14 +45,14 @@
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
* @{
*/
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void);
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void);
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void);
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void);
/**
* @}
*/
*/
/**
* @}
@@ -60,13 +60,13 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void);
/**
* @}
*/
*/
/**
* @}
*/
#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
#ifdef __cplusplus
}
#endif

143
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h
View File

@@ -119,8 +119,6 @@ typedef enum
HAL_FMPI2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_FMPI2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_FMPI2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_FMPI2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_FMPI2C_StateTypeDef;
@@ -208,6 +206,7 @@ typedef struct __FMPI2C_HandleTypeDef
DMA_HandleTypeDef *hdmarx; /*!< FMPI2C Rx DMA handle parameters */
HAL_LockTypeDef Lock; /*!< FMPI2C locking object */
__IO HAL_FMPI2C_StateTypeDef State; /*!< FMPI2C communication state */
@@ -218,6 +217,10 @@ typedef struct __FMPI2C_HandleTypeDef
__IO uint32_t AddrEventCount; /*!< FMPI2C Address Event counter */
__IO uint32_t Devaddress; /*!< FMPI2C Target device address */
__IO uint32_t Memaddress; /*!< FMPI2C Target memory address */
#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c);
/*!< FMPI2C Master Tx Transfer completed callback */
@@ -276,7 +279,7 @@ typedef enum
typedef void (*pFMPI2C_CallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c);
/*!< pointer to an FMPI2C callback function */
typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection,
uint16_t AddrMatchCode);
uint16_t AddrMatchCode);
/*!< pointer to an FMPI2C Address Match callback function */
#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
@@ -458,10 +461,10 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint
*/
#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_FMPI2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
(__HANDLE__)->State = HAL_FMPI2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET)
#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
@@ -513,7 +516,7 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified FMPI2C flag is set or not.
* @param __HANDLE__ specifies the FMPI2C Handle.
@@ -540,7 +543,7 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint
*/
#define FMPI2C_FLAG_MASK (0x0001FFFFU)
#define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the FMPI2C Handle.
@@ -560,8 +563,8 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint
* @retval None
*/
#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? \
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
((__HANDLE__)->Instance->ICR = (__FLAG__)))
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified FMPI2C peripheral.
* @param __HANDLE__ specifies the FMPI2C Handle.
@@ -604,7 +607,7 @@ void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID,
pFMPI2C_CallbackTypeDef pCallback);
pFMPI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, pFMPI2C_AddrCallbackTypeDef pCallback);
@@ -620,64 +623,64 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout);
uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
uint32_t XferOptions);
/**
* @}
*/
@@ -706,9 +709,9 @@ void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c);
HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c);
uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(const FMPI2C_HandleTypeDef *hfmpi2c);
HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(const FMPI2C_HandleTypeDef *hfmpi2c);
uint32_t HAL_FMPI2C_GetError(const FMPI2C_HandleTypeDef *hfmpi2c);
/**
* @}
@@ -733,28 +736,28 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
*/
#define IS_FMPI2C_ADDRESSING_MODE(MODE) (((MODE) == FMPI2C_ADDRESSINGMODE_7BIT) || \
((MODE) == FMPI2C_ADDRESSINGMODE_10BIT))
((MODE) == FMPI2C_ADDRESSINGMODE_10BIT))
#define IS_FMPI2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPI2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE))
((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE))
#define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPI2C_OA2_NOMASK) || \
((MASK) == FMPI2C_OA2_MASK01) || \
((MASK) == FMPI2C_OA2_MASK02) || \
((MASK) == FMPI2C_OA2_MASK03) || \
((MASK) == FMPI2C_OA2_MASK04) || \
((MASK) == FMPI2C_OA2_MASK05) || \
((MASK) == FMPI2C_OA2_MASK06) || \
((MASK) == FMPI2C_OA2_MASK07))
((MASK) == FMPI2C_OA2_MASK01) || \
((MASK) == FMPI2C_OA2_MASK02) || \
((MASK) == FMPI2C_OA2_MASK03) || \
((MASK) == FMPI2C_OA2_MASK04) || \
((MASK) == FMPI2C_OA2_MASK05) || \
((MASK) == FMPI2C_OA2_MASK06) || \
((MASK) == FMPI2C_OA2_MASK07))
#define IS_FMPI2C_GENERAL_CALL(CALL) (((CALL) == FMPI2C_GENERALCALL_DISABLE) || \
((CALL) == FMPI2C_GENERALCALL_ENABLE))
((CALL) == FMPI2C_GENERALCALL_ENABLE))
#define IS_FMPI2C_NO_STRETCH(STRETCH) (((STRETCH) == FMPI2C_NOSTRETCH_DISABLE) || \
((STRETCH) == FMPI2C_NOSTRETCH_ENABLE))
((STRETCH) == FMPI2C_NOSTRETCH_ENABLE))
#define IS_FMPI2C_MEMADD_SIZE(SIZE) (((SIZE) == FMPI2C_MEMADD_SIZE_8BIT) || \
((SIZE) == FMPI2C_MEMADD_SIZE_16BIT))
((SIZE) == FMPI2C_MEMADD_SIZE_16BIT))
#define IS_TRANSFER_MODE(MODE) (((MODE) == FMPI2C_RELOAD_MODE) || \
((MODE) == FMPI2C_AUTOEND_MODE) || \
@@ -766,25 +769,25 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
((REQUEST) == FMPI2C_NO_STARTSTOP))
#define IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_FIRST_FRAME) || \
((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == FMPI2C_NEXT_FRAME) || \
((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == FMPI2C_LAST_FRAME) || \
((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP) || \
IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == FMPI2C_NEXT_FRAME) || \
((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == FMPI2C_LAST_FRAME) || \
((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP) || \
IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
#define IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_OTHER_FRAME) || \
((REQUEST) == FMPI2C_OTHER_AND_LAST_FRAME))
((REQUEST) == FMPI2C_OTHER_AND_LAST_FRAME))
#define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
(uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \
FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \
FMPI2C_CR2_RD_WRN)))
(uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \
FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \
FMPI2C_CR2_RD_WRN)))
#define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) \
>> 16U))
>> 16U))
#define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) \
>> 16U))
>> 16U))
#define FMPI2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
#define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1))
#define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2))
@@ -793,19 +796,19 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
(uint16_t)(0xFF00U))) >> 8U)))
(uint16_t)(0xFF00U))) >> 8U)))
#define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? \
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \
(FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \
(~FMPI2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \
(FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & \
(~FMPI2C_CR2_RD_WRN)))
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \
(FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \
(~FMPI2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \
(FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START) | \
(FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)))
#define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == \
((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET)
((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET)
#define FMPI2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}

4
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h
View File

@@ -115,12 +115,12 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
* @{
*/
#define IS_FMPI2C_ANALOG_FILTER(FILTER) (((FILTER) == FMPI2C_ANALOGFILTER_ENABLE) || \
((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))
((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))
#define IS_FMPI2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_FMPI2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SCL)) == FMPI2C_FASTMODEPLUS_SCL) || \
(((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA))
(((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA))
/**
* @}
*/

139
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h
View File

@@ -101,8 +101,6 @@ typedef struct
#define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
#define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
#define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
#define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
#define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
#define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
/**
* @}
@@ -208,7 +206,7 @@ typedef enum
typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus);
/*!< pointer to an FMPSMBUS callback function */
typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection,
uint16_t AddrMatchCode);
uint16_t AddrMatchCode);
/*!< pointer to an FMPSMBUS Address Match callback function */
#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
@@ -372,9 +370,9 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus
#define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE
#define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE
#define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | \
FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)
FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)
#define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | \
FMPSMBUS_IT_RXI)
FMPSMBUS_IT_RXI)
#define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI)
#define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI)
/**
@@ -423,10 +421,10 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus
*/
#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
(__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET)
#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
@@ -512,6 +510,7 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus
* @param __HANDLE__ specifies the FMPSMBUS Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty
* @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode)
* @arg @ref FMPSMBUS_FLAG_AF NACK received flag
* @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag
@@ -524,7 +523,9 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus
*
* @retval None
*/
#define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
#define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPSMBUS_FLAG_TXE) ? \
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified FMPSMBUS peripheral.
* @param __HANDLE__ specifies the FMPSMBUS Handle.
@@ -557,84 +558,84 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus
*/
#define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \
((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE))
((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE))
#define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \
((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT))
((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT))
#define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \
((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE))
((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE))
#define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \
((MASK) == FMPSMBUS_OA2_MASK01) || \
((MASK) == FMPSMBUS_OA2_MASK02) || \
((MASK) == FMPSMBUS_OA2_MASK03) || \
((MASK) == FMPSMBUS_OA2_MASK04) || \
((MASK) == FMPSMBUS_OA2_MASK05) || \
((MASK) == FMPSMBUS_OA2_MASK06) || \
((MASK) == FMPSMBUS_OA2_MASK07))
((MASK) == FMPSMBUS_OA2_MASK01) || \
((MASK) == FMPSMBUS_OA2_MASK02) || \
((MASK) == FMPSMBUS_OA2_MASK03) || \
((MASK) == FMPSMBUS_OA2_MASK04) || \
((MASK) == FMPSMBUS_OA2_MASK05) || \
((MASK) == FMPSMBUS_OA2_MASK06) || \
((MASK) == FMPSMBUS_OA2_MASK07))
#define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) || \
((CALL) == FMPSMBUS_GENERALCALL_ENABLE))
((CALL) == FMPSMBUS_GENERALCALL_ENABLE))
#define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) || \
((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE))
((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE))
#define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \
((PEC) == FMPSMBUS_PEC_ENABLE))
((PEC) == FMPSMBUS_PEC_ENABLE))
#define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \
((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \
((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP))
((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \
((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP))
#define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \
((MODE) == FMPSMBUS_AUTOEND_MODE) || \
((MODE) == FMPSMBUS_SOFTEND_MODE) || \
((MODE) == FMPSMBUS_SENDPEC_MODE) || \
((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | \
FMPSMBUS_RELOAD_MODE )))
((MODE) == FMPSMBUS_AUTOEND_MODE) || \
((MODE) == FMPSMBUS_SOFTEND_MODE) || \
((MODE) == FMPSMBUS_SENDPEC_MODE) || \
((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | \
FMPSMBUS_RELOAD_MODE )))
#define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \
((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \
((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \
((REQUEST) == FMPSMBUS_NO_STARTSTOP))
((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \
((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \
((REQUEST) == FMPSMBUS_NO_STARTSTOP))
#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
((REQUEST) == FMPSMBUS_FIRST_FRAME) || \
((REQUEST) == FMPSMBUS_NEXT_FRAME) || \
((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \
((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \
((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC))
((REQUEST) == FMPSMBUS_FIRST_FRAME) || \
((REQUEST) == FMPSMBUS_NEXT_FRAME) || \
((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \
((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \
((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC))
#define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \
((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \
((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \
((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
#define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
(uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \
FMPI2C_CR1_PECEN)))
(uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \
FMPI2C_CR1_PECEN)))
#define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
(uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \
FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \
FMPI2C_CR2_RD_WRN)))
(uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \
FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \
FMPI2C_CR2_RD_WRN)))
#define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? \
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \
(FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \
(~FMPI2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & \
(FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | \
(FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \
(FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \
(~FMPI2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & \
(FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | \
(FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
#define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U)
#define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U)
@@ -643,7 +644,7 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus
#define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN)
#define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \
((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
#define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
@@ -676,13 +677,13 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus,
HAL_FMPSMBUS_CallbackIDTypeDef CallbackID,
pFMPSMBUS_CallbackTypeDef pCallback);
HAL_FMPSMBUS_CallbackIDTypeDef CallbackID,
pFMPSMBUS_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus,
HAL_FMPSMBUS_CallbackIDTypeDef CallbackID);
HAL_FMPSMBUS_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus,
pFMPSMBUS_AddrCallbackTypeDef pCallback);
pFMPSMBUS_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
/**
@@ -699,7 +700,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf
*/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout);
uint32_t Timeout);
/**
* @}
*/
@@ -709,14 +710,14 @@ HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus,
*/
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress,
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress,
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress);
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
@@ -749,8 +750,8 @@ void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
*/
/* Peripheral State and Errors functions **************************************************/
uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus);
uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus);
uint32_t HAL_FMPSMBUS_GetState(const FMPSMBUS_HandleTypeDef *hfmpsmbus);
uint32_t HAL_FMPSMBUS_GetError(const FMPSMBUS_HandleTypeDef *hfmpsmbus);
/**
* @}

6
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h
View File

@@ -104,9 +104,9 @@ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
* @{
*/
#define IS_FMPSMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SCL)) == \
FMPSMBUS_FASTMODEPLUS_SCL) || \
(((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == \
FMPSMBUS_FASTMODEPLUS_SDA))
FMPSMBUS_FASTMODEPLUS_SCL) || \
(((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == \
FMPSMBUS_FASTMODEPLUS_SDA))
/**
* @}
*/

82
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h
View File

@@ -117,13 +117,13 @@ typedef struct
{
HASH_InitTypeDef Init; /*!< HASH required parameters */
uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */
uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
uint8_t const *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
uint32_t HashBuffSize; /*!< Size of buffer to be processed */
@@ -480,15 +480,17 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS
/* HASH processing using polling *********************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout);
@@ -501,15 +503,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p
*/
/* HASH processing using IT **************************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/**
@@ -521,9 +523,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
*/
/* HASH processing using DMA *************************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
/**
@@ -535,9 +537,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu
*/
/* HASH-MAC processing using polling *****************************************/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Timeout);
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Timeout);
/**
@@ -548,9 +552,9 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
* @{
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
/**
@@ -562,8 +566,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
*/
/* HASH-HMAC processing using DMA ********************************************/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
/**
* @}
@@ -575,13 +579,13 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
/* Peripheral State methods **************************************************/
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash);
void HAL_HASH_ContextSaving(const HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer);
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer);
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash);
/**
* @}
@@ -598,19 +602,27 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
*/
/* Private functions */
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Timeout, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint32_t Algorithm);
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Timeout, uint32_t Algorithm);
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer,
uint32_t Algorithm);
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint32_t Algorithm);
/**
* @}

70
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash_ex.h
View File

@@ -50,15 +50,15 @@ extern "C" {
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout);
/**
@@ -69,15 +69,17 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
uint32_t Size,
uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
uint32_t Size,
uint8_t *pOutBuffer);
/**
@@ -87,9 +89,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
/**
@@ -99,9 +101,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p
/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
* @{
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -111,9 +113,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
* @{
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
/**
@@ -124,8 +126,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
* @{
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
/**
* @}
@@ -135,20 +137,24 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @{
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
uint32_t Size);
/**
* @}
*/

26
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h
View File

@@ -159,6 +159,10 @@ typedef struct
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
& (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \
((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
@@ -167,6 +171,9 @@ typedef struct
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
#define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT)
#define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT)
#define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN)
/**
* @}
*/
@@ -248,6 +255,11 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n
uint8_t token, uint8_t *pbuff,
uint16_t length, uint8_t do_ping);
HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
uint8_t addr, uint8_t PortNbr);
HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
/* Non-Blocking mode: Interrupt */
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd);
@@ -277,16 +289,13 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd);
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
/**
* @}
@@ -307,6 +316,9 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#ifdef __cplusplus

4
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h
View File

@@ -496,8 +496,8 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
* @{
*/
/* Peripheral Control and State functions ************************************/
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s);
uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s);
/**
* @}
*/

4
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h
View File

@@ -593,8 +593,8 @@ void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
* @{
*/
/* Peripheral State functions **************************************************/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
/**
* @}
*/

12
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h
View File

@@ -399,6 +399,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @brief Write the passed parameter in the Autoreload register.
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Autoreload value
* This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF.
* @retval None
* @note The ARR register can only be modified when the LPTIM instance is enabled.
*/
@@ -689,9 +690,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
* @{
*/
/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
@@ -727,7 +728,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_
* @{
*/
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
@@ -818,9 +819,6 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\
((__AUTORELOAD__) <= 0x0000FFFFUL))
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\

23
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h
View File

@@ -338,14 +338,14 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer
/** @defgroup LTDC_Pixelformat LTDC Pixel format
* @{
*/
#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */
/**
* @}
*/
@@ -592,7 +592,8 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, u
HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize,
uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
@@ -625,8 +626,8 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3
* @{
*/
/* Peripheral State functions *************************************************/
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc);
uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc);
/**
* @}
*/

45
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h
View File

@@ -109,9 +109,8 @@ typedef struct
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
parameter is mandatory for some NAND parts after the read
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
Example: Toshiba THTH58BYG3S0HBAI6.
This parameter could be ENABLE or DISABLE
Please check the Read Mode sequnece in the NAND device datasheet */
Please check the Read Mode sequence in the NAND device datasheet */
} NAND_DeviceConfigTypeDef;
/**
@@ -131,7 +130,7 @@ typedef struct
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
@@ -199,7 +198,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig);
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
@@ -219,27 +218,27 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint8_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint16_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/* NAND callback registering/unregistering */
@@ -269,8 +268,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
* @{
*/
/* NAND State functions *******************************************************/
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
/**
* @}
*/
@@ -290,7 +289,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
#define NAND_DEVICE2 0x80000000UL
#else
#define NAND_DEVICE 0x80000000UL
#endif
#endif /* FMC_Bank2_3 */
#define NAND_WRITE_TIMEOUT 0x01000000UL
#define CMD_AREA (1UL<<16U) /* A16 = CLE high */

2
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nor.h
View File

@@ -238,7 +238,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
*/
/* NOR State functions ********************************************************/
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
/**
* @}

13
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pccard.h
View File

@@ -72,7 +72,7 @@ typedef enum
typedef struct __PCCARD_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
{
FMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
@@ -86,7 +86,7 @@ typedef struct
void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */
void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */
void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */
#endif
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
} PCCARD_HandleTypeDef;
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
@@ -104,7 +104,7 @@ typedef enum
* @brief HAL PCCARD Callback pointer definition
*/
typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
#endif
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -126,7 +126,7 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
} while(0)
#else
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
#endif
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -141,7 +141,8 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming,
FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
@@ -169,7 +170,7 @@ HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HA
pPCCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard,
HAL_PCCARD_CallbackIDTypeDef CallbackId);
#endif
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
*/

12
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h
View File

@@ -190,14 +190,14 @@ typedef struct
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
@@ -368,9 +368,11 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode);
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode);
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
/**
* @}
*/
@@ -379,7 +381,7 @@ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
/**
* @}
*/

15
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h
View File

@@ -45,21 +45,26 @@ extern "C" {
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|| defined(STM32F423xx)
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
defined(STM32F423xx) */
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) \
|| defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||
defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);

13
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h
View File

@@ -114,6 +114,8 @@ typedef struct
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
#define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR ((uint8_t)0x03)
/**
* @}
*/
@@ -123,6 +125,7 @@ typedef struct
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
#define PWR_STOPENTRY_WFE_NO_EVT_CLEAR ((uint8_t)0x03)
/**
* @}
*/
@@ -401,8 +404,14 @@ void HAL_PWR_DisableSEVOnPend(void);
((MODE) == PWR_PVD_MODE_NORMAL))
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || \
((ENTRY) == PWR_SLEEPENTRY_WFE) || \
((ENTRY) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR))
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || \
((ENTRY) == PWR_STOPENTRY_WFE) || \
((ENTRY) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR))
/**
* @}
*/

6
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h
View File

@@ -623,13 +623,13 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi,
* @{
*/
/* Peripheral Control and State functions ************************************/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (const QSPI_HandleTypeDef *hqspi);
uint32_t HAL_QSPI_GetError (const QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
/**
* @}

341
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h
View File

@@ -20,7 +20,7 @@
#define __STM32F4xx_HAL_RCC_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -67,7 +67,7 @@ typedef struct
This parameter can be a value of @ref RCC_LSI_Config */
RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
}RCC_OscInitTypeDef;
} RCC_OscInitTypeDef;
/**
* @brief RCC System, AHB and APB busses clock configuration structure definition
@@ -89,7 +89,7 @@ typedef struct
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
}RCC_ClkInitTypeDef;
} RCC_ClkInitTypeDef;
/**
* @}
@@ -382,47 +382,47 @@ typedef struct
* @{
*/
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
UNUSED(tmpreg); \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
UNUSED(tmpreg); \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
UNUSED(tmpreg); \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
UNUSED(tmpreg); \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
UNUSED(tmpreg); \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
@@ -466,53 +466,53 @@ typedef struct
* @{
*/
#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_USART2_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
@@ -560,61 +560,61 @@ typedef struct
* @{
*/
#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_USART1_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_USART6_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
UNUSED(tmpreg); \
} while(0U)
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
@@ -660,7 +660,6 @@ typedef struct
* @brief Force or release AHB1 peripheral reset.
* @{
*/
#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
@@ -683,7 +682,6 @@ typedef struct
* @brief Force or release APB1 peripheral reset.
* @{
*/
#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
@@ -708,7 +706,6 @@ typedef struct
* @brief Force or release APB2 peripheral reset.
* @{
*/
#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
@@ -842,7 +839,7 @@ typedef struct
* This parameter must be a number between 0 and 0x1F.
*/
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))
RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))
/**
* @}
*/
@@ -891,22 +888,22 @@ typedef struct
* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
*/
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
do { \
if ((__STATE__) == RCC_HSE_ON) \
{ \
SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \
else if ((__STATE__) == RCC_HSE_BYPASS) \
{ \
SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
} \
} while(0U)
do { \
if ((__STATE__) == RCC_HSE_ON) \
{ \
SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \
else if ((__STATE__) == RCC_HSE_BYPASS) \
{ \
SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
} \
} while(0U)
/**
* @}
*/
@@ -934,22 +931,22 @@ typedef struct
* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
*/
#define __HAL_RCC_LSE_CONFIG(__STATE__) \
do { \
if((__STATE__) == RCC_LSE_ON) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else if((__STATE__) == RCC_LSE_BYPASS) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
} while(0U)
do { \
if((__STATE__) == RCC_LSE_ON) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else if((__STATE__) == RCC_LSE_BYPASS) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
} while(0U)
/**
* @}
*/
@@ -986,7 +983,7 @@ typedef struct
* RTC clock source).
*/
#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
@@ -1004,7 +1001,7 @@ typedef struct
/**
* @brief Get the RTC and HSE clock divider (RTCPRE).
* @retval Returned value can be one of the following values:
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
*/
#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
@@ -1114,7 +1111,7 @@ typedef struct
* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
*/
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
/** @brief Macro to configure the MCO2 clock.
* @param __MCOCLKSOURCE__ specifies the MCO clock source.
@@ -1135,7 +1132,7 @@ typedef struct
* at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
*/
#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
/**
* @}
*/
@@ -1223,7 +1220,9 @@ typedef struct
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define RCC_FLAG_MASK ((uint8_t)0x1FU)
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U)\
== 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) &\
(1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
/**
* @}
@@ -1234,17 +1233,17 @@ typedef struct
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RCC_Exported_Functions
/** @addtogroup RCC_Exported_Functions
* @{
*/
*/
/** @addtogroup RCC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
/**
* @}
*/
@@ -1407,7 +1406,7 @@ void HAL_RCC_CSSCallback(void);
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
#define IS_RCC_PLLM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U))
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
@@ -1431,8 +1430,8 @@ void HAL_RCC_CSSCallback(void);
((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
((DIV) == RCC_MCODIV_5))
((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
((DIV) == RCC_MCODIV_5))
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
/**

4417
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h
View File

File diff suppressed because it is too large Load Diff

6
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h
View File

@@ -304,7 +304,7 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef
*hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng);
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
@@ -317,8 +317,8 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
* @{
*/
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng);
uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng);
/**
* @}
*/

11
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h
View File

@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -489,6 +489,12 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to
(__HANDLE__)->Instance->WPR = 0xFFU; \
} while(0U)
/**
* @brief Check whether the RTC Calendar is initialized.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ISR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U)
/**
* @brief Enable the RTC ALARMA peripheral.
@@ -772,6 +778,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
RTC_DR_MT | RTC_DR_MU | \
RTC_DR_DT | RTC_DR_DU | \
RTC_DR_WDU))
#define RTC_ISR_RESERVED_MASK ((uint32_t)(RTC_FLAGS_MASK | RTC_ISR_INIT))
#define RTC_INIT_MASK 0xFFFFFFFFU
#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | \
@@ -784,7 +791,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
#define RTC_TIMEOUT_VALUE 1000U
#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 connected to the RTC Alarm event */
/**
* @}
*/

32
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h
View File

@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -162,7 +162,7 @@ typedef struct
* @{
*/
#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U
#define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG
#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U
#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
/**
@@ -635,18 +635,6 @@ typedef struct
*/
#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified RTC Tamper interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
* This parameter can be:
* @arg RTC_IT_TAMP1: Tamper 1 interrupt
* @arg RTC_IT_TAMP2: Tamper 2 interrupt
* @note RTC_IT_TAMP2 is not applicable to all devices.
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
/**
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
@@ -663,8 +651,9 @@ typedef struct
* @param __FLAG__ specifies the RTC Tamper flag to be checked.
* This parameter can be:
* @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag
* @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag
* @note RTC_FLAG_TAMP2F is not applicable to all devices.
* @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag (*)
*
* (*) value not applicable to all devices.
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
@@ -675,8 +664,9 @@ typedef struct
* @param __FLAG__ specifies the RTC Tamper Flag to clear.
* This parameter can be:
* @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag
* @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag
* @note RTC_FLAG_TAMP2F is not applicable to all devices.
* @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag (*)
*
* (*) value not applicable to all devices.
* @retval None
*/
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
@@ -705,13 +695,13 @@ typedef struct
* @brief Enable event on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
* @brief Disable event on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
* @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
@@ -916,7 +906,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
* @{
*/
/* Extended RTC features functions *******************************************/
void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
/**
* @}

4
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h
View File

@@ -748,8 +748,8 @@ void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
* @{
*/
/* Peripheral State functions ************************************************/
HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai);
uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai);
/**
* @}
*/

4
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h
View File

@@ -71,8 +71,8 @@ extern "C" {
*/
/* Extended features functions ************************************************/
void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai);
uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai);
void SAI_BlockSynchroConfig(const SAI_HandleTypeDef *hsai);
uint32_t SAI_GetInputClock(const SAI_HandleTypeDef *hsai);
/**
* @}
*/

2
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h
View File

@@ -212,7 +212,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
* @{
*/
/* SDRAM State functions ********************************************************/
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram);
/**
* @}
*/

4
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h
View File

@@ -671,8 +671,8 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
* @{
*/
/* Peripheral State functions **************************************************/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsc);
uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsc);
/**
* @}
*/

36
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h
View File

@@ -150,35 +150,35 @@ typedef enum
*/
typedef struct __SMBUS_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
uint16_t XferSize; /*!< SMBUS transfer size */
uint16_t XferSize; /*!< SMBUS transfer size */
__IO uint16_t XferCount; /*!< SMBUS transfer counter */
__IO uint16_t XferCount; /*!< SMBUS transfer counter */
__IO uint32_t XferOptions; /*!< SMBUS transfer options this parameter can
be a value of @ref SMBUS_OPTIONS */
be a value of @ref SMBUS_XferOptions_definition */
__IO uint32_t PreviousState; /*!< SMBUS communication Previous state and mode
context for internal usage */
context for internal usage */
HAL_LockTypeDef Lock; /*!< SMBUS locking object */
HAL_LockTypeDef Lock; /*!< SMBUS locking object */
__IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */
__IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */
__IO HAL_SMBUS_ModeTypeDef Mode; /*!< SMBUS communication mode */
__IO HAL_SMBUS_ModeTypeDef Mode; /*!< SMBUS communication mode */
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
__IO uint32_t Devaddress; /*!< SMBUS Target device address */
__IO uint32_t Devaddress; /*!< SMBUS Target device address */
__IO uint32_t EventCount; /*!< SMBUS Event counter */
__IO uint32_t EventCount; /*!< SMBUS Event counter */
uint8_t XferPEC; /*!< SMBUS PEC data in reception mode */
uint8_t XferPEC; /*!< SMBUS PEC data in reception mode */
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */
@@ -604,6 +604,10 @@ void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_AbortCpltCallback(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/**
* @}
*/
@@ -718,10 +722,6 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif

56
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spdifrx.h
View File

@@ -56,7 +56,8 @@ typedef struct
uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input.
This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.
uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status
from channel A or B.
This parameter can be a value of @ref SPDIFRX_Channel_Selection */
uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
@@ -65,16 +66,19 @@ typedef struct
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_PT_Mask */
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not
into the received frame.
This parameter can be a value of @ref SPDIFRX_PT_Mask */
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not
into the received frame.
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_V_Mask */
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not
into the received frame.
This parameter can be a value of @ref SPDIFRX_PE_Mask */
} SPDIFRX_InitTypeDef;
@@ -89,17 +93,20 @@ typedef struct
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_PT_Mask */
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not
into the received frame.
This parameter can be a value of @ref SPDIFRX_PT_Mask */
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not
into the received frame.
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_V_Mask */
This parameter can be a value of @ref SPDIFRX_V_Mask */
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_PE_Mask */
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not
into the received frame.
This parameter can be a value of @ref SPDIFRX_PE_Mask */
} SPDIFRX_SetDataFormatTypeDef;
@@ -151,7 +158,8 @@ typedef struct
decremented when a sample is received.
NbSamplesReceived = RxBufferSize-RxBufferCount) */
DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information
DMA handle parameters */
DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */
@@ -162,9 +170,11 @@ typedef struct
__IO uint32_t ErrorCode; /* SPDIFRX Error code */
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed callback */
void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed
callback */
void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow completed callback */
void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed callback */
void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed
callback */
void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */
void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */
void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp Init callback */
@@ -172,9 +182,6 @@ typedef struct
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
} SPDIFRX_HandleTypeDef;
/**
* @}
*/
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
/**
@@ -194,9 +201,12 @@ typedef enum
/**
* @brief HAL SPDIFRX Callback pointer definition
*/
typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback function */
typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback
function */
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
* @{
@@ -260,8 +270,10 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!<
/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask
* @{
*/
#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */
#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied
into the SPDIF_DR */
#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied
into the SPDIF_DR, zeros are written instead*/
/**
* @}
*/

46
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h
View File

@@ -107,7 +107,7 @@ typedef struct __SPI_HandleTypeDef
SPI_InitTypeDef Init; /*!< SPI communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
@@ -339,11 +339,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @retval None
*/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \
do{ \
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
@@ -444,7 +445,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
__IO uint32_t tmpreg_fre = 0x00U; \
tmpreg_fre = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_fre); \
}while(0U)
} while(0U)
/** @brief Enable the SPI peripheral.
* @param __HANDLE__ specifies the SPI Handle.
@@ -488,8 +489,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
#define SPI_RESET_CRC(__HANDLE__) \
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
} while(0U)
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of SPI SR register.
@@ -505,7 +509,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @retval SET or RESET.
*/
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of SPI CR2 register.
@@ -517,7 +521,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @retval SET or RESET.
*/
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
(__INTERRUPT__)) ? SET : RESET)
(__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if SPI Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Mode.
@@ -627,7 +631,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
*/
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
((__POLYNOMIAL__) <= 0xFFFFU) && \
(((__POLYNOMIAL__)&0x1U) != 0U))
(((__POLYNOMIAL__)&0x1U) != 0U))
/** @brief Checks if DMA handle is valid.
* @param __HANDLE__ specifies a DMA Handle.
@@ -667,17 +671,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
@@ -703,8 +707,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi);
uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
/**
* @}
*/

2
CubeKeil Example/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h
View File

@@ -209,7 +209,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
*/
/* SRAM State functions ******************************************************/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram);
/**
* @}

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