инициализация spi перенесена на cube (работает)
убрана кастомная библиотека periph_general
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@@ -1,11 +1,11 @@
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/******************************************************************************
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* @file mpu_armv8.h
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* @brief CMSIS MPU API for Armv8-M MPU
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* @version V5.0.4
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* @date 10. January 2018
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* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
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* @version V5.1.3
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* @date 03. February 2021
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******************************************************************************/
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/*
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* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
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* Copyright (c) 2017-2021 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@@ -44,7 +44,7 @@
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* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
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*/
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#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
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(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
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((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
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/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
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#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
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@@ -62,7 +62,7 @@
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* \param O Outer memory attributes
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* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
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*/
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#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
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#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
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/** \brief Normal memory non-shareable */
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#define ARM_MPU_SH_NON (0U)
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@@ -77,7 +77,7 @@
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* \param RO Read-Only: Set to 1 for read-only memory.
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* \param NP Non-Privileged: Set to 1 for non-privileged memory.
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*/
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#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
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#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
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/** \brief Region Base Address Register value
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* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
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@@ -87,20 +87,35 @@
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* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
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*/
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#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
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((BASE & MPU_RBAR_BASE_Msk) | \
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((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
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(((BASE) & MPU_RBAR_BASE_Msk) | \
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(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
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((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
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((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
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(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
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/** \brief Region Limit Address Register value
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* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
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* \param IDX The attribute index to be associated with this memory region.
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*/
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#define ARM_MPU_RLAR(LIMIT, IDX) \
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((LIMIT & MPU_RLAR_LIMIT_Msk) | \
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((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
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(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
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(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
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(MPU_RLAR_EN_Msk))
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#if defined(MPU_RLAR_PXN_Pos)
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/** \brief Region Limit Address Register with PXN value
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* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
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* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
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* \param IDX The attribute index to be associated with this memory region.
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*/
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#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
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(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
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(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
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(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
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(MPU_RLAR_EN_Msk))
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#endif
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/**
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* Struct for a single MPU Region
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*/
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@@ -114,24 +129,26 @@ typedef struct {
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*/
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__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
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{
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__DSB();
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__ISB();
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__DMB();
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MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
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#ifdef SCB_SHCSR_MEMFAULTENA_Msk
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SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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#endif
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__DSB();
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__ISB();
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}
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/** Disable the MPU.
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*/
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__STATIC_INLINE void ARM_MPU_Disable(void)
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{
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__DSB();
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__ISB();
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__DMB();
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#ifdef SCB_SHCSR_MEMFAULTENA_Msk
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SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
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#endif
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MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
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__DSB();
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__ISB();
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}
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#ifdef MPU_NS
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@@ -140,24 +157,26 @@ __STATIC_INLINE void ARM_MPU_Disable(void)
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*/
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__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
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{
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__DSB();
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__ISB();
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__DMB();
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MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
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#ifdef SCB_SHCSR_MEMFAULTENA_Msk
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SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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#endif
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__DSB();
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__ISB();
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}
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/** Disable the Non-secure MPU.
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*/
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__STATIC_INLINE void ARM_MPU_Disable_NS(void)
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{
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__DSB();
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__ISB();
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__DMB();
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#ifdef SCB_SHCSR_MEMFAULTENA_Msk
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SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
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#endif
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MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
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__DSB();
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__ISB();
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}
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#endif
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@@ -262,12 +281,12 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
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}
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#endif
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/** Memcopy with strictly ordered memory access, e.g. for register targets.
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/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
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* \param dst Destination data is copied to.
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* \param src Source data is copied from.
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* \param len Amount of data words to be copied.
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*/
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__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
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__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
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{
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uint32_t i;
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for (i = 0U; i < len; ++i)
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@@ -287,7 +306,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
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const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
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if (cnt == 1U) {
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mpu->RNR = rnr;
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orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
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ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
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} else {
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uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
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uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
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@@ -295,7 +314,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
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mpu->RNR = rnrBase;
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while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
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uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
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orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
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ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
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table += c;
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cnt -= c;
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rnrOffset = 0U;
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@@ -303,7 +322,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
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mpu->RNR = rnrBase;
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}
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orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
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ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
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}
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}
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