инициализация spi перенесена на cube (работает)
убрана кастомная библиотека periph_general
This commit is contained in:
@@ -1,11 +1,11 @@
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/**************************************************************************//**
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* @file cmsis_armclang.h
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* @brief CMSIS compiler armclang (Arm Compiler 6) header file
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* @version V5.0.4
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* @date 10. January 2018
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* @version V5.4.3
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* @date 27. May 2021
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@@ -29,10 +29,6 @@
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#pragma clang system_header /* treat file as system include file */
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#ifndef __ARM_COMPAT_H
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#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
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#endif
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/* CMSIS compiler specific defines */
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#ifndef __ASM
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#define __ASM __asm
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@@ -43,9 +39,9 @@
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#ifndef __STATIC_INLINE
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#define __STATIC_INLINE static __inline
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#endif
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#ifndef __STATIC_FORCEINLINE
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#ifndef __STATIC_FORCEINLINE
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#define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
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#endif
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#endif
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#ifndef __NO_RETURN
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#define __NO_RETURN __attribute__((__noreturn__))
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#endif
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@@ -110,6 +106,620 @@
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#ifndef __RESTRICT
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#define __RESTRICT __restrict
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#endif
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#ifndef __COMPILER_BARRIER
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#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
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#endif
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/* ######################### Startup and Lowlevel Init ######################## */
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#ifndef __PROGRAM_START
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#define __PROGRAM_START __main
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#endif
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#ifndef __INITIAL_SP
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#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
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#endif
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#ifndef __STACK_LIMIT
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#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
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#endif
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#ifndef __VECTOR_TABLE
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#define __VECTOR_TABLE __Vectors
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#endif
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#ifndef __VECTOR_TABLE_ATTRIBUTE
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#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
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#endif
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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#ifndef __STACK_SEAL
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#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base
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#endif
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#ifndef __TZ_STACK_SEAL_SIZE
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#define __TZ_STACK_SEAL_SIZE 8U
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#endif
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#ifndef __TZ_STACK_SEAL_VALUE
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#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
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#endif
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__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
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*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
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}
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#endif
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/* ########################## Core Instruction Access ######################### */
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/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
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Access to dedicated instructions
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@{
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*/
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/* Define macros for porting to both thumb1 and thumb2.
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* For thumb1, use low register (r0-r7), specified by constraint "l"
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* Otherwise, use general registers, specified by constraint "r" */
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#if defined (__thumb__) && !defined (__thumb2__)
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#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
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#define __CMSIS_GCC_RW_REG(r) "+l" (r)
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#define __CMSIS_GCC_USE_REG(r) "l" (r)
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#else
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#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
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#define __CMSIS_GCC_RW_REG(r) "+r" (r)
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#define __CMSIS_GCC_USE_REG(r) "r" (r)
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#endif
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/**
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\brief No Operation
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\details No Operation does nothing. This instruction can be used for code alignment purposes.
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*/
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#define __NOP __builtin_arm_nop
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/**
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\brief Wait For Interrupt
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\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
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*/
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#define __WFI __builtin_arm_wfi
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/**
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\brief Wait For Event
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\details Wait For Event is a hint instruction that permits the processor to enter
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a low-power state until one of a number of events occurs.
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*/
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#define __WFE __builtin_arm_wfe
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/**
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\brief Send Event
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\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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*/
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#define __SEV __builtin_arm_sev
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/**
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\brief Instruction Synchronization Barrier
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\details Instruction Synchronization Barrier flushes the pipeline in the processor,
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so that all instructions following the ISB are fetched from cache or memory,
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after the instruction has been completed.
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*/
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#define __ISB() __builtin_arm_isb(0xF)
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/**
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\brief Data Synchronization Barrier
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\details Acts as a special kind of Data Memory Barrier.
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It completes when all explicit memory accesses before this instruction complete.
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*/
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#define __DSB() __builtin_arm_dsb(0xF)
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/**
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\brief Data Memory Barrier
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\details Ensures the apparent order of the explicit memory operations before
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and after the instruction, without ensuring their completion.
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*/
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#define __DMB() __builtin_arm_dmb(0xF)
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/**
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\brief Reverse byte order (32 bit)
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\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __REV(value) __builtin_bswap32(value)
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __REV16(value) __ROR(__REV(value), 16)
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __REVSH(value) (int16_t)__builtin_bswap16(value)
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/**
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\brief Rotate Right in unsigned value (32 bit)
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\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
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\param [in] op1 Value to rotate
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\param [in] op2 Number of Bits to rotate
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\return Rotated value
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*/
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__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
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{
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op2 %= 32U;
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if (op2 == 0U)
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{
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return op1;
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}
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return (op1 >> op2) | (op1 << (32U - op2));
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}
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/**
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\brief Breakpoint
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\details Causes the processor to enter Debug state.
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Debug tools can use this to investigate system state when the instruction at a particular address is reached.
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\param [in] value is ignored by the processor.
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If required, a debugger can use it to store additional information about the breakpoint.
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*/
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#define __BKPT(value) __ASM volatile ("bkpt "#value)
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/**
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\brief Reverse bit order of value
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\details Reverses the bit order of the given value.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __RBIT __builtin_arm_rbit
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/**
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\brief Count leading zeros
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\details Counts the number of leading zeros of a data value.
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\param [in] value Value to count the leading zeros
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\return number of leading zeros in value
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*/
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__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
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{
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/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
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__builtin_clz(0) is undefined behaviour, so handle this case specially.
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This guarantees ARM-compatible results if happening to compile on a non-ARM
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target, and ensures the compiler doesn't decide to activate any
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optimisations using the logic "value was passed to __builtin_clz, so it
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is non-zero".
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ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
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single CLZ instruction.
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*/
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if (value == 0U)
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{
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return 32U;
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}
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return __builtin_clz(value);
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}
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#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
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(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
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(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
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(defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
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/**
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\brief LDR Exclusive (8 bit)
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\details Executes a exclusive LDR instruction for 8 bit value.
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\param [in] ptr Pointer to data
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\return value of type uint8_t at (*ptr)
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*/
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#define __LDREXB (uint8_t)__builtin_arm_ldrex
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/**
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\brief LDR Exclusive (16 bit)
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\details Executes a exclusive LDR instruction for 16 bit values.
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\param [in] ptr Pointer to data
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\return value of type uint16_t at (*ptr)
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*/
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#define __LDREXH (uint16_t)__builtin_arm_ldrex
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/**
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\brief LDR Exclusive (32 bit)
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\details Executes a exclusive LDR instruction for 32 bit values.
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\param [in] ptr Pointer to data
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\return value of type uint32_t at (*ptr)
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*/
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#define __LDREXW (uint32_t)__builtin_arm_ldrex
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/**
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\brief STR Exclusive (8 bit)
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\details Executes a exclusive STR instruction for 8 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#define __STREXB (uint32_t)__builtin_arm_strex
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/**
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\brief STR Exclusive (16 bit)
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\details Executes a exclusive STR instruction for 16 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#define __STREXH (uint32_t)__builtin_arm_strex
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/**
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\brief STR Exclusive (32 bit)
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\details Executes a exclusive STR instruction for 32 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#define __STREXW (uint32_t)__builtin_arm_strex
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/**
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\brief Remove the exclusive lock
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\details Removes the exclusive lock which is created by LDREX.
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*/
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#define __CLREX __builtin_arm_clrex
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#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
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(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
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(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
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(defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
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#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
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(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
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(defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
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/**
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\brief Signed Saturate
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\details Saturates a signed value.
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\param [in] value Value to be saturated
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\param [in] sat Bit position to saturate to (1..32)
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\return Saturated value
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*/
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#define __SSAT __builtin_arm_ssat
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/**
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\brief Unsigned Saturate
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\details Saturates an unsigned value.
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\param [in] value Value to be saturated
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\param [in] sat Bit position to saturate to (0..31)
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\return Saturated value
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*/
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#define __USAT __builtin_arm_usat
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/**
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\brief Rotate Right with Extend (32 bit)
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\details Moves each bit of a bitstring right by one bit.
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The carry input is shifted in at the left end of the bitstring.
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\param [in] value Value to rotate
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\return Rotated value
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*/
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__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
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{
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uint32_t result;
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__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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return(result);
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}
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/**
|
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\brief LDRT Unprivileged (8 bit)
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\details Executes a Unprivileged LDRT instruction for 8 bit value.
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\param [in] ptr Pointer to data
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\return value of type uint8_t at (*ptr)
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*/
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__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
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{
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uint32_t result;
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__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
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return ((uint8_t) result); /* Add explicit type cast here */
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}
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|
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/**
|
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\brief LDRT Unprivileged (16 bit)
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\details Executes a Unprivileged LDRT instruction for 16 bit values.
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\param [in] ptr Pointer to data
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\return value of type uint16_t at (*ptr)
|
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*/
|
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__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
|
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{
|
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uint32_t result;
|
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__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
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return ((uint16_t) result); /* Add explicit type cast here */
|
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}
|
||||
|
||||
|
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/**
|
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\brief LDRT Unprivileged (32 bit)
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\details Executes a Unprivileged LDRT instruction for 32 bit values.
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\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
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__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
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{
|
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uint32_t result;
|
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|
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__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
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return(result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
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||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
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__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
|
||||
}
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Load-Acquire (8 bit)
|
||||
\details Executes a LDAB instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
|
||||
return ((uint8_t) result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Load-Acquire (16 bit)
|
||||
\details Executes a LDAH instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
|
||||
return ((uint16_t) result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Load-Acquire (32 bit)
|
||||
\details Executes a LDA instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Store-Release (8 bit)
|
||||
\details Executes a STLB instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Store-Release (16 bit)
|
||||
\details Executes a STLH instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Store-Release (32 bit)
|
||||
\details Executes a STL instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Load-Acquire Exclusive (8 bit)
|
||||
\details Executes a LDAB exclusive instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDAEXB (uint8_t)__builtin_arm_ldaex
|
||||
|
||||
|
||||
/**
|
||||
\brief Load-Acquire Exclusive (16 bit)
|
||||
\details Executes a LDAH exclusive instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDAEXH (uint16_t)__builtin_arm_ldaex
|
||||
|
||||
|
||||
/**
|
||||
\brief Load-Acquire Exclusive (32 bit)
|
||||
\details Executes a LDA exclusive instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDAEX (uint32_t)__builtin_arm_ldaex
|
||||
|
||||
|
||||
/**
|
||||
\brief Store-Release Exclusive (8 bit)
|
||||
\details Executes a STLB exclusive instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STLEXB (uint32_t)__builtin_arm_stlex
|
||||
|
||||
|
||||
/**
|
||||
\brief Store-Release Exclusive (16 bit)
|
||||
\details Executes a STLH exclusive instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STLEXH (uint32_t)__builtin_arm_stlex
|
||||
|
||||
|
||||
/**
|
||||
\brief Store-Release Exclusive (32 bit)
|
||||
\details Executes a STL exclusive instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STLEX (uint32_t)__builtin_arm_stlex
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
@@ -120,18 +730,28 @@
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); see arm_compat.h */
|
||||
#ifndef __ARM_COMPAT_H
|
||||
__STATIC_FORCEINLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i" : : : "memory");
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); see arm_compat.h */
|
||||
#ifndef __ARM_COMPAT_H
|
||||
__STATIC_FORCEINLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i" : : : "memory");
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
@@ -172,6 +792,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
|
||||
__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
|
||||
__ISB();
|
||||
}
|
||||
|
||||
|
||||
@@ -184,6 +805,7 @@ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
|
||||
__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -419,23 +1041,30 @@ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
|
||||
#endif
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
|
||||
__STATIC_FORCEINLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
|
||||
__STATIC_FORCEINLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@@ -557,26 +1186,29 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer Limit
|
||||
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||||
Stack Pointer Limit register hence zero is returned always in non-secure
|
||||
mode.
|
||||
|
||||
|
||||
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
|
||||
\return PSPLIM Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
return 0U;
|
||||
@@ -599,7 +1231,8 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||||
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
return 0U;
|
||||
#else
|
||||
@@ -616,13 +1249,14 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
|
||||
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||||
Stack Pointer Limit register hence the write is silently ignored in non-secure
|
||||
mode.
|
||||
|
||||
|
||||
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
|
||||
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)ProcStackPtrLimit;
|
||||
@@ -644,7 +1278,8 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||||
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)ProcStackPtrLimit;
|
||||
#else
|
||||
@@ -664,7 +1299,8 @@ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
return 0U;
|
||||
@@ -687,7 +1323,8 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||||
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
return 0U;
|
||||
#else
|
||||
@@ -709,7 +1346,8 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
(void)MainStackPtrLimit;
|
||||
@@ -730,7 +1368,8 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
|
||||
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
(void)MainStackPtrLimit;
|
||||
#else
|
||||
@@ -739,8 +1378,9 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
|
||||
#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
@@ -770,549 +1410,6 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Define macros for porting to both thumb1 and thumb2.
|
||||
* For thumb1, use low register (r0-r7), specified by constraint "l"
|
||||
* Otherwise, use general registers, specified by constraint "r" */
|
||||
#if defined (__thumb__) && !defined (__thumb2__)
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "l" (r)
|
||||
#else
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "r" (r)
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __builtin_arm_nop
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __builtin_arm_wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __builtin_arm_wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __builtin_arm_sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __builtin_arm_isb(0xF);
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __builtin_arm_dsb(0xF);
|
||||
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __builtin_arm_dmb(0xF);
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV(value) __builtin_bswap32(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV16(value) __ROR(__REV(value), 16)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REVSH(value) (int16_t)__builtin_bswap16(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
op2 %= 32U;
|
||||
if (op2 == 0U)
|
||||
{
|
||||
return op1;
|
||||
}
|
||||
return (op1 >> op2) | (op1 << (32U - op2));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __ASM volatile ("bkpt "#value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __RBIT __builtin_arm_rbit
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ (uint8_t)__builtin_clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXB (uint8_t)__builtin_arm_ldrex
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXH (uint16_t)__builtin_arm_ldrex
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXW (uint32_t)__builtin_arm_ldrex
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXB (uint32_t)__builtin_arm_strex
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXH (uint32_t)__builtin_arm_strex
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXW (uint32_t)__builtin_arm_strex
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __builtin_arm_clrex
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __builtin_arm_ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __builtin_arm_usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
return ((uint16_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
|
||||
}
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
/**
|
||||
\brief Load-Acquire (8 bit)
|
||||
\details Executes a LDAB instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
return ((uint8_t) result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Load-Acquire (16 bit)
|
||||
\details Executes a LDAH instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
return ((uint16_t) result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Load-Acquire (32 bit)
|
||||
\details Executes a LDA instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Store-Release (8 bit)
|
||||
\details Executes a STLB instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Store-Release (16 bit)
|
||||
\details Executes a STLH instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Store-Release (32 bit)
|
||||
\details Executes a STL instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Load-Acquire Exclusive (8 bit)
|
||||
\details Executes a LDAB exclusive instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDAEXB (uint8_t)__builtin_arm_ldaex
|
||||
|
||||
|
||||
/**
|
||||
\brief Load-Acquire Exclusive (16 bit)
|
||||
\details Executes a LDAH exclusive instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDAEXH (uint16_t)__builtin_arm_ldaex
|
||||
|
||||
|
||||
/**
|
||||
\brief Load-Acquire Exclusive (32 bit)
|
||||
\details Executes a LDA exclusive instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDAEX (uint32_t)__builtin_arm_ldaex
|
||||
|
||||
|
||||
/**
|
||||
\brief Store-Release Exclusive (8 bit)
|
||||
\details Executes a STLB exclusive instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STLEXB (uint32_t)__builtin_arm_stlex
|
||||
|
||||
|
||||
/**
|
||||
\brief Store-Release Exclusive (16 bit)
|
||||
\details Executes a STLH exclusive instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STLEXH (uint32_t)__builtin_arm_stlex
|
||||
|
||||
|
||||
/**
|
||||
\brief Store-Release Exclusive (32 bit)
|
||||
\details Executes a STL exclusive instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STLEX (uint32_t)__builtin_arm_stlex
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@@ -1321,532 +1418,65 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||
|
||||
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SSAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
int32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __USAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ /* Little endian */
|
||||
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else /* Big endian */
|
||||
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ /* Little endian */
|
||||
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else /* Big endian */
|
||||
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ /* Little endian */
|
||||
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else /* Big endian */
|
||||
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ /* Little endian */
|
||||
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else /* Big endian */
|
||||
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#if 0
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
if (ARG3 == 0) \
|
||||
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
||||
else \
|
||||
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
#endif
|
||||
#define __SADD8 __builtin_arm_sadd8
|
||||
#define __QADD8 __builtin_arm_qadd8
|
||||
#define __SHADD8 __builtin_arm_shadd8
|
||||
#define __UADD8 __builtin_arm_uadd8
|
||||
#define __UQADD8 __builtin_arm_uqadd8
|
||||
#define __UHADD8 __builtin_arm_uhadd8
|
||||
#define __SSUB8 __builtin_arm_ssub8
|
||||
#define __QSUB8 __builtin_arm_qsub8
|
||||
#define __SHSUB8 __builtin_arm_shsub8
|
||||
#define __USUB8 __builtin_arm_usub8
|
||||
#define __UQSUB8 __builtin_arm_uqsub8
|
||||
#define __UHSUB8 __builtin_arm_uhsub8
|
||||
#define __SADD16 __builtin_arm_sadd16
|
||||
#define __QADD16 __builtin_arm_qadd16
|
||||
#define __SHADD16 __builtin_arm_shadd16
|
||||
#define __UADD16 __builtin_arm_uadd16
|
||||
#define __UQADD16 __builtin_arm_uqadd16
|
||||
#define __UHADD16 __builtin_arm_uhadd16
|
||||
#define __SSUB16 __builtin_arm_ssub16
|
||||
#define __QSUB16 __builtin_arm_qsub16
|
||||
#define __SHSUB16 __builtin_arm_shsub16
|
||||
#define __USUB16 __builtin_arm_usub16
|
||||
#define __UQSUB16 __builtin_arm_uqsub16
|
||||
#define __UHSUB16 __builtin_arm_uhsub16
|
||||
#define __SASX __builtin_arm_sasx
|
||||
#define __QASX __builtin_arm_qasx
|
||||
#define __SHASX __builtin_arm_shasx
|
||||
#define __UASX __builtin_arm_uasx
|
||||
#define __UQASX __builtin_arm_uqasx
|
||||
#define __UHASX __builtin_arm_uhasx
|
||||
#define __SSAX __builtin_arm_ssax
|
||||
#define __QSAX __builtin_arm_qsax
|
||||
#define __SHSAX __builtin_arm_shsax
|
||||
#define __USAX __builtin_arm_usax
|
||||
#define __UQSAX __builtin_arm_uqsax
|
||||
#define __UHSAX __builtin_arm_uhsax
|
||||
#define __USAD8 __builtin_arm_usad8
|
||||
#define __USADA8 __builtin_arm_usada8
|
||||
#define __SSAT16 __builtin_arm_ssat16
|
||||
#define __USAT16 __builtin_arm_usat16
|
||||
#define __UXTB16 __builtin_arm_uxtb16
|
||||
#define __UXTAB16 __builtin_arm_uxtab16
|
||||
#define __SXTB16 __builtin_arm_sxtb16
|
||||
#define __SXTAB16 __builtin_arm_sxtab16
|
||||
#define __SMUAD __builtin_arm_smuad
|
||||
#define __SMUADX __builtin_arm_smuadx
|
||||
#define __SMLAD __builtin_arm_smlad
|
||||
#define __SMLADX __builtin_arm_smladx
|
||||
#define __SMLALD __builtin_arm_smlald
|
||||
#define __SMLALDX __builtin_arm_smlaldx
|
||||
#define __SMUSD __builtin_arm_smusd
|
||||
#define __SMUSDX __builtin_arm_smusdx
|
||||
#define __SMLSD __builtin_arm_smlsd
|
||||
#define __SMLSDX __builtin_arm_smlsdx
|
||||
#define __SMLSLD __builtin_arm_smlsld
|
||||
#define __SMLSLDX __builtin_arm_smlsldx
|
||||
#define __SEL __builtin_arm_sel
|
||||
#define __QADD __builtin_arm_qadd
|
||||
#define __QSUB __builtin_arm_qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
@@ -1854,6 +1484,10 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
||||
|
||||
#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
|
||||
|
||||
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
Reference in New Issue
Block a user