Templates/PY32_Support
9
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

init

Browse Source
This commit is contained in:
Razvalyaev
2025-02-28 12:32:54 +03:00
commit 3fe4b442a4
2259 changed files with 1042663 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

217
AliBoardExample/Drivers/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f002ax5.s Normal file
View File

@@ -0,0 +1,217 @@
;******************************************************************************
;* @file : startup_py32f002ax5.s
;* @brief : PY32F002Axx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) Puya Semiconductor Co.
;* All rights reserved.</center></h2>
;*
;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD 0 ; 0Reserved
DCD 0 ; 1Reserved
DCD 0 ; 2Reserved
DCD FLASH_IRQHandler ; 3FLASH
DCD RCC_IRQHandler ; 4RCC
DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15
DCD 0 ; 8Reserved
DCD 0 ; 9Reserved
DCD 0 ; 10Reserved
DCD 0 ; 11Reserved
DCD ADC_COMP_IRQHandler ; 12ADC&COMP1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare
DCD 0 ; 15Reserved
DCD 0 ; 16Reserved
DCD LPTIM1_IRQHandler ; 17LPTIM1
DCD 0 ; 18Reserved
DCD 0 ; 19Reserved
DCD 0 ; 20Reserved
DCD TIM16_IRQHandler ; 21TIM16
DCD 0 ; 22Reserved
DCD I2C1_IRQHandler ; 23I2C1
DCD 0 ; 24Reserved
DCD SPI1_IRQHandler ; 25SPI1
DCD 0 ; 26Reserved
DCD USART1_IRQHandler ; 27USART1
DCD 0 ; 28Reserved
DCD 0 ; 29Reserved
DCD 0 ; 30Reserved
DCD 0 ; 31Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT ADC_COMP_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
ADC_COMP_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
LPTIM1_IRQHandler
TIM16_IRQHandler
I2C1_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

235
AliBoardExample/Drivers/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x4.s Normal file
View File

@@ -0,0 +1,235 @@
;******************************************************************************
;* @file : startup_py32f003xx.s
;* @brief : PY32F003xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) Puya Semiconductor Co.
;* All rights reserved.</center></h2>
;*
;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; 0Window Watchdog
DCD PVD_IRQHandler ; 1PVD through EXTI Line detect
DCD RTC_IRQHandler ; 2RTC through EXTI Line
DCD FLASH_IRQHandler ; 3FLASH
DCD RCC_IRQHandler ; 4RCC
DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15
DCD 0 ; 8Reserved
DCD DMA1_Channel1_IRQHandler ; 9DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; 10DMA1 Channel 2 and Channel 3
DCD 0 ; 11Reserved
DCD ADC_COMP_IRQHandler ; 12ADC&COMP1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare
DCD 0 ; 15Reserved
DCD TIM3_IRQHandler ; 16TIM3
DCD LPTIM1_IRQHandler ; 17LPTIM1
DCD 0 ; 18Reserved
DCD TIM14_IRQHandler ; 19TIM14
DCD 0 ; 20Reserved
DCD TIM16_IRQHandler ; 21TIM16
DCD TIM17_IRQHandler ; 22TIM17
DCD I2C1_IRQHandler ; 23I2C1
DCD 0 ; 24Reserved
DCD SPI1_IRQHandler ; 25SPI1
DCD 0 ; 26Reserved
DCD USART1_IRQHandler ; 27USART1
DCD USART2_IRQHandler ; 28USART2
DCD 0 ; 29Reserved
DCD 0 ; 30Reserved
DCD 0 ; 31Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT ADC_COMP_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
ADC_COMP_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM3_IRQHandler
LPTIM1_IRQHandler
TIM14_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

235
AliBoardExample/Drivers/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x6.s Normal file
View File

@@ -0,0 +1,235 @@
;******************************************************************************
;* @file : startup_py32f003xx.s
;* @brief : PY32F003xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) Puya Semiconductor Co.
;* All rights reserved.</center></h2>
;*
;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; 0Window Watchdog
DCD PVD_IRQHandler ; 1PVD through EXTI Line detect
DCD RTC_IRQHandler ; 2RTC through EXTI Line
DCD FLASH_IRQHandler ; 3FLASH
DCD RCC_IRQHandler ; 4RCC
DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15
DCD 0 ; 8Reserved
DCD DMA1_Channel1_IRQHandler ; 9DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; 10DMA1 Channel 2 and Channel 3
DCD 0 ; 11Reserved
DCD ADC_COMP_IRQHandler ; 12ADC&COMP1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare
DCD 0 ; 15Reserved
DCD TIM3_IRQHandler ; 16TIM3
DCD LPTIM1_IRQHandler ; 17LPTIM1
DCD 0 ; 18Reserved
DCD TIM14_IRQHandler ; 19TIM14
DCD 0 ; 20Reserved
DCD TIM16_IRQHandler ; 21TIM16
DCD TIM17_IRQHandler ; 22TIM17
DCD I2C1_IRQHandler ; 23I2C1
DCD 0 ; 24Reserved
DCD SPI1_IRQHandler ; 25SPI1
DCD 0 ; 26Reserved
DCD USART1_IRQHandler ; 27USART1
DCD USART2_IRQHandler ; 28USART2
DCD 0 ; 29Reserved
DCD 0 ; 30Reserved
DCD 0 ; 31Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT ADC_COMP_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
ADC_COMP_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM3_IRQHandler
LPTIM1_IRQHandler
TIM14_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

235
AliBoardExample/Drivers/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x8.s Normal file
View File

@@ -0,0 +1,235 @@
;******************************************************************************
;* @file : startup_py32f003xx.s
;* @brief : PY32F003xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) Puya Semiconductor Co.
;* All rights reserved.</center></h2>
;*
;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; 0Window Watchdog
DCD PVD_IRQHandler ; 1PVD through EXTI Line detect
DCD RTC_IRQHandler ; 2RTC through EXTI Line
DCD FLASH_IRQHandler ; 3FLASH
DCD RCC_IRQHandler ; 4RCC
DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15
DCD 0 ; 8Reserved
DCD DMA1_Channel1_IRQHandler ; 9DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; 10DMA1 Channel 2 and Channel 3
DCD 0 ; 11Reserved
DCD ADC_COMP_IRQHandler ; 12ADC&COMP1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare
DCD 0 ; 15Reserved
DCD TIM3_IRQHandler ; 16TIM3
DCD LPTIM1_IRQHandler ; 17LPTIM1
DCD 0 ; 18Reserved
DCD TIM14_IRQHandler ; 19TIM14
DCD 0 ; 20Reserved
DCD TIM16_IRQHandler ; 21TIM16
DCD TIM17_IRQHandler ; 22TIM17
DCD I2C1_IRQHandler ; 23I2C1
DCD 0 ; 24Reserved
DCD SPI1_IRQHandler ; 25SPI1
DCD 0 ; 26Reserved
DCD USART1_IRQHandler ; 27USART1
DCD USART2_IRQHandler ; 28USART2
DCD 0 ; 29Reserved
DCD 0 ; 30Reserved
DCD 0 ; 31Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT ADC_COMP_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
ADC_COMP_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM3_IRQHandler
LPTIM1_IRQHandler
TIM14_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

239
AliBoardExample/Drivers/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x3.s Normal file
View File

@@ -0,0 +1,239 @@
;******************************************************************************
;* @file : startup_py32f030xx.s
;* @brief : PY32F030xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) Puya Semiconductor Co.
;* All rights reserved.</center></h2>
;*
;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; 0Window Watchdog
DCD PVD_IRQHandler ; 1PVD through EXTI Line detect
DCD RTC_IRQHandler ; 2RTC through EXTI Line
DCD FLASH_IRQHandler ; 3FLASH
DCD RCC_IRQHandler ; 4RCC
DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15
DCD 0 ; 8Reserved
DCD DMA1_Channel1_IRQHandler ; 9DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; 10DMA1 Channel 2 and Channel 3
DCD 0 ; 11Reserved
DCD ADC_COMP_IRQHandler ; 12ADC&COMP1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare
DCD 0 ; 15Reserved
DCD TIM3_IRQHandler ; 16TIM3
DCD LPTIM1_IRQHandler ; 17LPTIM1
DCD 0 ; 18Reserved
DCD TIM14_IRQHandler ; 19TIM14
DCD 0 ; 20Reserved
DCD TIM16_IRQHandler ; 21TIM16
DCD TIM17_IRQHandler ; 22TIM17
DCD I2C1_IRQHandler ; 23I2C1
DCD 0 ; 24Reserved
DCD SPI1_IRQHandler ; 25SPI1
DCD SPI2_IRQHandler ; 26SPI2
DCD USART1_IRQHandler ; 27USART1
DCD USART2_IRQHandler ; 28USART2
DCD 0 ; 29Reserved
DCD LED_IRQHandler ; 30LED
DCD 0 ; 31Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT ADC_COMP_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LED_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
ADC_COMP_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM3_IRQHandler
LPTIM1_IRQHandler
TIM14_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LED_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

239
AliBoardExample/Drivers/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x4.s Normal file
View File

@@ -0,0 +1,239 @@
;******************************************************************************
;* @file : startup_py32f030xx.s
;* @brief : PY32F030xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) Puya Semiconductor Co.
;* All rights reserved.</center></h2>
;*
;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; 0Window Watchdog
DCD PVD_IRQHandler ; 1PVD through EXTI Line detect
DCD RTC_IRQHandler ; 2RTC through EXTI Line
DCD FLASH_IRQHandler ; 3FLASH
DCD RCC_IRQHandler ; 4RCC
DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15
DCD 0 ; 8Reserved
DCD DMA1_Channel1_IRQHandler ; 9DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; 10DMA1 Channel 2 and Channel 3
DCD 0 ; 11Reserved
DCD ADC_COMP_IRQHandler ; 12ADC&COMP1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare
DCD 0 ; 15Reserved
DCD TIM3_IRQHandler ; 16TIM3
DCD LPTIM1_IRQHandler ; 17LPTIM1
DCD 0 ; 18Reserved
DCD TIM14_IRQHandler ; 19TIM14
DCD 0 ; 20Reserved
DCD TIM16_IRQHandler ; 21TIM16
DCD TIM17_IRQHandler ; 22TIM17
DCD I2C1_IRQHandler ; 23I2C1
DCD 0 ; 24Reserved
DCD SPI1_IRQHandler ; 25SPI1
DCD SPI2_IRQHandler ; 26SPI2
DCD USART1_IRQHandler ; 27USART1
DCD USART2_IRQHandler ; 28USART2
DCD 0 ; 29Reserved
DCD LED_IRQHandler ; 30LED
DCD 0 ; 31Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT ADC_COMP_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LED_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
ADC_COMP_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM3_IRQHandler
LPTIM1_IRQHandler
TIM14_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LED_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

239
AliBoardExample/Drivers/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x6.s Normal file
View File

@@ -0,0 +1,239 @@
;******************************************************************************
;* @file : startup_py32f030xx.s
;* @brief : PY32F030xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) Puya Semiconductor Co.
;* All rights reserved.</center></h2>
;*
;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; 0Window Watchdog
DCD PVD_IRQHandler ; 1PVD through EXTI Line detect
DCD RTC_IRQHandler ; 2RTC through EXTI Line
DCD FLASH_IRQHandler ; 3FLASH
DCD RCC_IRQHandler ; 4RCC
DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15
DCD 0 ; 8Reserved
DCD DMA1_Channel1_IRQHandler ; 9DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; 10DMA1 Channel 2 and Channel 3
DCD 0 ; 11Reserved
DCD ADC_COMP_IRQHandler ; 12ADC&COMP1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare
DCD 0 ; 15Reserved
DCD TIM3_IRQHandler ; 16TIM3
DCD LPTIM1_IRQHandler ; 17LPTIM1
DCD 0 ; 18Reserved
DCD TIM14_IRQHandler ; 19TIM14
DCD 0 ; 20Reserved
DCD TIM16_IRQHandler ; 21TIM16
DCD TIM17_IRQHandler ; 22TIM17
DCD I2C1_IRQHandler ; 23I2C1
DCD 0 ; 24Reserved
DCD SPI1_IRQHandler ; 25SPI1
DCD SPI2_IRQHandler ; 26SPI2
DCD USART1_IRQHandler ; 27USART1
DCD USART2_IRQHandler ; 28USART2
DCD 0 ; 29Reserved
DCD LED_IRQHandler ; 30LED
DCD 0 ; 31Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT ADC_COMP_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LED_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
ADC_COMP_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM3_IRQHandler
LPTIM1_IRQHandler
TIM14_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LED_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

239
AliBoardExample/Drivers/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x7.s Normal file
View File

@@ -0,0 +1,239 @@
;******************************************************************************
;* @file : startup_py32f030xx.s
;* @brief : PY32F030xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) Puya Semiconductor Co.
;* All rights reserved.</center></h2>
;*
;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; 0Window Watchdog
DCD PVD_IRQHandler ; 1PVD through EXTI Line detect
DCD RTC_IRQHandler ; 2RTC through EXTI Line
DCD FLASH_IRQHandler ; 3FLASH
DCD RCC_IRQHandler ; 4RCC
DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15
DCD 0 ; 8Reserved
DCD DMA1_Channel1_IRQHandler ; 9DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; 10DMA1 Channel 2 and Channel 3
DCD 0 ; 11Reserved
DCD ADC_COMP_IRQHandler ; 12ADC&COMP1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare
DCD 0 ; 15Reserved
DCD TIM3_IRQHandler ; 16TIM3
DCD LPTIM1_IRQHandler ; 17LPTIM1
DCD 0 ; 18Reserved
DCD TIM14_IRQHandler ; 19TIM14
DCD 0 ; 20Reserved
DCD TIM16_IRQHandler ; 21TIM16
DCD TIM17_IRQHandler ; 22TIM17
DCD I2C1_IRQHandler ; 23I2C1
DCD 0 ; 24Reserved
DCD SPI1_IRQHandler ; 25SPI1
DCD SPI2_IRQHandler ; 26SPI2
DCD USART1_IRQHandler ; 27USART1
DCD USART2_IRQHandler ; 28USART2
DCD 0 ; 29Reserved
DCD LED_IRQHandler ; 30LED
DCD 0 ; 31Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT ADC_COMP_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LED_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
ADC_COMP_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM3_IRQHandler
LPTIM1_IRQHandler
TIM14_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LED_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

239
AliBoardExample/Drivers/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x8.s Normal file
View File

@@ -0,0 +1,239 @@
;******************************************************************************
;* @file : startup_py32f030xx.s
;* @brief : PY32F030xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) Puya Semiconductor Co.
;* All rights reserved.</center></h2>
;*
;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; 0Window Watchdog
DCD PVD_IRQHandler ; 1PVD through EXTI Line detect
DCD RTC_IRQHandler ; 2RTC through EXTI Line
DCD FLASH_IRQHandler ; 3FLASH
DCD RCC_IRQHandler ; 4RCC
DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15
DCD 0 ; 8Reserved
DCD DMA1_Channel1_IRQHandler ; 9DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; 10DMA1 Channel 2 and Channel 3
DCD 0 ; 11Reserved
DCD ADC_COMP_IRQHandler ; 12ADC&COMP1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare
DCD 0 ; 15Reserved
DCD TIM3_IRQHandler ; 16TIM3
DCD LPTIM1_IRQHandler ; 17LPTIM1
DCD 0 ; 18Reserved
DCD TIM14_IRQHandler ; 19TIM14
DCD 0 ; 20Reserved
DCD TIM16_IRQHandler ; 21TIM16
DCD TIM17_IRQHandler ; 22TIM17
DCD I2C1_IRQHandler ; 23I2C1
DCD 0 ; 24Reserved
DCD SPI1_IRQHandler ; 25SPI1
DCD SPI2_IRQHandler ; 26SPI2
DCD USART1_IRQHandler ; 27USART1
DCD USART2_IRQHandler ; 28USART2
DCD 0 ; 29Reserved
DCD LED_IRQHandler ; 30LED
DCD 0 ; 31Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT ADC_COMP_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT LED_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
ADC_COMP_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM3_IRQHandler
LPTIM1_IRQHandler
TIM14_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
LED_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

212
AliBoardExample/Drivers/CMSIS/Device/PY32F0xx/Source/iar/startup_py32f002axx.s Normal file
View File

@@ -0,0 +1,212 @@
;******************************************************************************
;* @file : startup_py32f002axx.s
;* @brief : PY32F002Axx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == __iar_program_start
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) Puya Semiconductor Co.
;* All rights reserved.</center></h2>
;*
;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD 0 ; 0Reserved
DCD 0 ; 1Reserved
DCD 0 ; 2Reserved
DCD FLASH_IRQHandler ; 3FLASH
DCD RCC_IRQHandler ; 4RCC
DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15
DCD 0 ; 8Reserved
DCD 0 ; 9Reserved
DCD 0 ; 10Reserved
DCD 0 ; 11Reserved
DCD ADC_COMP_IRQHandler ; 12ADC&COMP
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare
DCD 0 ; 15Reserved
DCD 0 ; 16Reserved
DCD LPTIM1_IRQHandler ; 17LPTIM1
DCD 0 ; 18Reserved
DCD 0 ; 19Reserved
DCD 0 ; 20Reserved
DCD TIM16_IRQHandler ; 21TIM16
DCD 0 ; 22Reserved
DCD I2C1_IRQHandler ; 23I2C1
DCD 0 ; 24Reserved
DCD SPI1_IRQHandler ; 25SPI1
DCD 0 ; 26Reserved
DCD USART1_IRQHandler ; 27USART1
DCD 0 ; 28Reserved
DCD 0 ; 29Reserved
DCD 0 ; 30Reserved
DCD 0 ; 31Reserved
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_1_IRQHandler
B EXTI0_1_IRQHandler
PUBWEAK EXTI2_3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_3_IRQHandler
B EXTI2_3_IRQHandler
PUBWEAK EXTI4_15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_15_IRQHandler
B EXTI4_15_IRQHandler
PUBWEAK ADC_COMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_COMP_IRQHandler
B ADC_COMP_IRQHandler
PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_UP_TRG_COM_IRQHandler
B TIM1_BRK_UP_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
END
/*****************************END OF FILE************************************/

257
AliBoardExample/Drivers/CMSIS/Device/PY32F0xx/Source/iar/startup_py32f003xx.s Normal file
View File

@@ -0,0 +1,257 @@
;******************************************************************************
;* @file : startup_py32f003xx.s
;* @brief : PY32F003xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == __iar_program_start
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) Puya Semiconductor Co.
;* All rights reserved.</center></h2>
;*
;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; 0Window Watchdog
DCD PVD_IRQHandler ; 1PVD through EXTI Line detect
DCD RTC_IRQHandler ; 2RTC through EXTI Line
DCD FLASH_IRQHandler ; 3FLASH
DCD RCC_IRQHandler ; 4RCC
DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15
DCD 0 ; 8Reserved
DCD DMA1_Channel1_IRQHandler ; 9DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; 10DMA1 Channel 2 and Channel 3
DCD 0 ; 11Reserved
DCD ADC_COMP_IRQHandler ; 12ADC&COMP
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare
DCD 0 ; 15Reserved
DCD TIM3_IRQHandler ; 16TIM3
DCD LPTIM1_IRQHandler ; 17LPTIM1
DCD 0 ; 18Reserved
DCD TIM14_IRQHandler ; 19TIM14
DCD 0 ; 20Reserved
DCD TIM16_IRQHandler ; 21TIM16
DCD TIM17_IRQHandler ; 22TIM17
DCD I2C1_IRQHandler ; 23I2C1
DCD 0 ; 24Reserved
DCD SPI1_IRQHandler ; 25SPI1
DCD 0 ; 26Reserved
DCD USART1_IRQHandler ; 27USART1
DCD USART2_IRQHandler ; 28USART2
DCD 0 ; 29Reserved
DCD 0 ; 30Reserved
DCD 0 ; 31Reserved
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_1_IRQHandler
B EXTI0_1_IRQHandler
PUBWEAK EXTI2_3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_3_IRQHandler
B EXTI2_3_IRQHandler
PUBWEAK EXTI4_15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_15_IRQHandler
B EXTI4_15_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_3_IRQHandler
B DMA1_Channel2_3_IRQHandler
PUBWEAK ADC_COMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_COMP_IRQHandler
B ADC_COMP_IRQHandler
PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_UP_TRG_COM_IRQHandler
B TIM1_BRK_UP_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK TIM14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM14_IRQHandler
B TIM14_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
END
/*****************************END OF FILE************************************/

267
AliBoardExample/Drivers/CMSIS/Device/PY32F0xx/Source/iar/startup_py32f030xx.s Normal file
View File

@@ -0,0 +1,267 @@
;******************************************************************************
;* @file : startup_py32f030xx.s
;* @brief : PY32F030xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == __iar_program_start
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) Puya Semiconductor Co.
;* All rights reserved.</center></h2>
;*
;* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; 0Window Watchdog
DCD PVD_IRQHandler ; 1PVD through EXTI Line detect
DCD RTC_IRQHandler ; 2RTC through EXTI Line
DCD FLASH_IRQHandler ; 3FLASH
DCD RCC_IRQHandler ; 4RCC
DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15
DCD 0 ; 8Reserved
DCD DMA1_Channel1_IRQHandler ; 9DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; 10DMA1 Channel 2 and Channel 3
DCD 0 ; 11Reserved
DCD ADC_COMP_IRQHandler ; 12ADC&COMP
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare
DCD 0 ; 15Reserved
DCD TIM3_IRQHandler ; 16TIM3
DCD LPTIM1_IRQHandler ; 17LPTIM1
DCD 0 ; 18Reserved
DCD TIM14_IRQHandler ; 19TIM14
DCD 0 ; 20Reserved
DCD TIM16_IRQHandler ; 21TIM16
DCD TIM17_IRQHandler ; 22TIM17
DCD I2C1_IRQHandler ; 23I2C1
DCD 0 ; 24Reserved
DCD SPI1_IRQHandler ; 25SPI1
DCD SPI2_IRQHandler ; 26SPI2
DCD USART1_IRQHandler ; 27USART1
DCD USART2_IRQHandler ; 28USART2
DCD 0 ; 29Reserved
DCD LED_IRQHandler ; 30LED
DCD 0 ; 31Reserved
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_1_IRQHandler
B EXTI0_1_IRQHandler
PUBWEAK EXTI2_3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_3_IRQHandler
B EXTI2_3_IRQHandler
PUBWEAK EXTI4_15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_15_IRQHandler
B EXTI4_15_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_3_IRQHandler
B DMA1_Channel2_3_IRQHandler
PUBWEAK ADC_COMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_COMP_IRQHandler
B ADC_COMP_IRQHandler
PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_UP_TRG_COM_IRQHandler
B TIM1_BRK_UP_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK TIM14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM14_IRQHandler
B TIM14_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LED_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
LED_IRQHandler
B LED_IRQHandler
END
/*****************************END OF FILE************************************/

173
AliBoardExample/Drivers/CMSIS/Device/PY32F0xx/Source/system_py32f0xx.c Normal file
View File

@@ -0,0 +1,173 @@
/**
******************************************************************************
* @file system_py32f0xx.c
* @author MCU Application Team
* @Version V1.0.0
* @Date 2020-10-19
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
******************************************************************************
*/
#include "py32f0xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
#if !defined (LSI_VALUE)
#define LSI_VALUE 32768U /*!< Value of LSI in Hz*/
#endif /* LSI_VALUE */
#if !defined (LSE_VALUE)
#define LSE_VALUE 32768U /*!< Value of LSE in Hz*/
#endif /* LSE_VALUE */
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define FORBID_VECT_TAB_MIGRATION */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x100. */
/******************************************************************************/
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = HSI_VALUE;
const uint32_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint32_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
const uint32_t HSIFreqTable[8] = {4000000U, 8000000U, 16000000U, 22120000U, 24000000U, 4000000U, 4000000U, 4000000U};
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
{
uint32_t tmp;
uint32_t hsidiv;
uint32_t hsifs;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_0: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */
SystemCoreClock = LSI_VALUE;
break;
#if defined(RCC_LSE_SUPPORT)
case RCC_CFGR_SWS_2: /* LSE used as system clock */
SystemCoreClock = LSE_VALUE;
break;
#endif
#if defined(RCC_PLL_SUPPORT)
case RCC_CFGR_SWS_1: /* PLL used as system clock */
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI) /* HSI used as PLL clock source */
{
hsifs = ((READ_BIT(RCC->ICSCR, RCC_ICSCR_HSI_FS)) >> RCC_ICSCR_HSI_FS_Pos);
SystemCoreClock = 2 * (HSIFreqTable[hsifs]);
}
else /* HSE used as PLL clock source */
{
SystemCoreClock = 2 * HSE_VALUE;
}
break;
#endif
case 0x00000000U: /* HSI used as system clock */
default: /* HSI used as system clock */
hsifs = ((READ_BIT(RCC->ICSCR, RCC_ICSCR_HSI_FS)) >> RCC_ICSCR_HSI_FS_Pos);
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
SystemCoreClock = (HSIFreqTable[hsifs] / hsidiv);
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit(void)
{
/* Set the HSI clock to 8MHz by default */
RCC->ICSCR = (RCC->ICSCR & 0xFFFF0000) | (0x1 << 13) | *(uint32_t *)(0x1fff0f04);
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
#ifndef FORBID_VECT_TAB_MIGRATION
#ifndef VECT_TAB_SRAM
#if (defined (__CC_ARM)) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
extern int32_t $Super$$main(void);
uint32_t VECT_SRAM_TAB[48]__attribute__((section(".ARM.__at_0x20000000")));
/* re-define main function */
int $Sub$$main(void)
{
uint8_t i;
uint32_t *pFmcVect = (uint32_t *)(FLASH_BASE | VECT_TAB_OFFSET);
for (i = 0; i < 48; i++)
{
VECT_SRAM_TAB[i] = pFmcVect[i];
}
SCB->VTOR = SRAM_BASE;
$Super$$main();
return 0;
}
#elif defined(__ICCARM__)
extern int32_t main(void);
/* __low_level_init will auto called by IAR cstartup */
extern void __iar_data_init3(void);
uint32_t VECT_SRAM_TAB[48] @SRAM_BASE;
int __low_level_init(void)
{
uint8_t i;
uint32_t *pFmcVect = (uint32_t *)(FLASH_BASE | VECT_TAB_OFFSET);
/* call IAR table copy function. */
__iar_data_init3();
for (i = 0; i < 48; i++)
{
VECT_SRAM_TAB[i] = pFmcVect[i];
}
SCB->VTOR = SRAM_BASE;
main();
return 0;
}
#endif
#endif
#endif