285 lines
13 KiB
C
285 lines
13 KiB
C
/**
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******************************************************************************
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* @file py32f002b_ll_spi.c
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* @author MCU Application Team
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* @brief SPI LL module driver.
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******************************************************************************
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Additional table :
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DataSize = SPI_DATASIZE_8BIT:
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+----------------------------------------------------------------------------------------------+
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| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
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| Process | Tranfert mode |---------------------|----------------------|----------------------|
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| | | Master | Slave | Master | Slave | Master | Slave |
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|==============================================================================================|
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| TX | Polling | Fpclk/2 | Fpclk/32 | NA | NA | NA | NA |
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| / |----------------|----------|----------|-----------|----------|-----------|----------|
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| RX | Interrupt | Fpclk/2 | Fpclk/32 | NA | NA | NA | NA |
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| |----------------|----------|----------|-----------|----------|-----------|----------|
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|=========|================|==========|==========|===========|==========|===========|==========|
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| | Polling | NA | NA | Fpclk/4 | Fpclk/8 | Fpclk/4 | Fpclk/8 |
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| R |----------------|----------|----------|-----------|----------|-----------|----------|
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| X | Interrupt | NA | NA | Fpclk/16 | Fpclk/16 | Fpclk/16 | Fpclk/16 |
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| |----------------|----------|----------|-----------|----------|-----------|----------|
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|=========|================|==========|==========|===========|==========|===========|==========|
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| | Polling | NA | NA | NA | NA | Fpclk/2 | Fpclk/8 |
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| T |----------------|----------|----------|-----------|----------|-----------|----------|
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| X | Interrupt | NA | NA | NA | NA | Fpclk/2 | Fpclk/16 |
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| |----------------|----------|----------|-----------|----------|-----------|----------|
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+----------------------------------------------------------------------------------------------+
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DataSize = SPI_DATASIZE_16BIT:
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+----------------------------------------------------------------------------------------------+
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| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
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| Process | Tranfert mode |---------------------|----------------------|----------------------|
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| | | Master | Slave | Master | Slave | Master | Slave |
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|==============================================================================================|
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| TX | Polling | Fpclk/2 | Fpclk/16 | NA | NA | NA | NA |
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| / |----------------|----------|----------|-----------|----------|-----------|----------|
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| RX | Interrupt | Fpclk/2 | Fpclk/16 | NA | NA | NA | NA |
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| |----------------|----------|----------|-----------|----------|-----------|----------|
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|=========|================|==========|==========|===========|==========|===========|==========|
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| | Polling | NA | NA | Fpclk/2 | Fpclk/4 | Fpclk/2 | Fpclk/4 |
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| |----------------|----------|----------|-----------|----------|-----------|----------|
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| R | Interrupt | NA | NA | Fpclk/2 | Fpclk/8 | Fpclk/2 | Fpclk/8 |
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| X |----------------|----------|----------|-----------|----------|-----------|----------|
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|=========|================|==========|==========|===========|==========|===========|==========|
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| | Polling | NA | NA | NA | NA | Fpclk/2 | Fpclk/4 |
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| |----------------|----------|----------|-----------|----------|-----------|----------|
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| T | Interrupt | NA | NA | NA | NA | Fpclk/2 | Fpclk/8 |
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| X |----------------|----------|----------|-----------|----------|-----------|----------|
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+----------------------------------------------------------------------------------------------+
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@note The max SPI frequency depend on SPI data size (8bits, 16bits),
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SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT).
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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#if defined(USE_FULL_LL_DRIVER)
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/* Includes ------------------------------------------------------------------*/
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#include "py32f002b_ll_spi.h"
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#include "py32f002b_ll_bus.h"
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#include "py32f002b_ll_rcc.h"
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#ifdef USE_FULL_ASSERT
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#include "py32_assert.h"
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#else
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#define assert_param(expr) ((void)0U)
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#endif /* USE_FULL_ASSERT */
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/** @addtogroup PY32F002B_LL_Driver
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* @{
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*/
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#if defined (SPI1)
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/** @addtogroup SPI_LL
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @defgroup SPI_LL_Private_Constants SPI Private Constants
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* @{
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*/
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/* SPI registers Masks */
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#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
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SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
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SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
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SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE)
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/** @defgroup SPI_LL_Private_Macros SPI Private Macros
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* @{
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*/
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#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
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|| ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
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|| ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
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|| ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
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#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
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|| ((__VALUE__) == LL_SPI_MODE_SLAVE))
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#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
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|| ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
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#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
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|| ((__VALUE__) == LL_SPI_POLARITY_HIGH))
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#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
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|| ((__VALUE__) == LL_SPI_PHASE_2EDGE))
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#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
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|| ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
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|| ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
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#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
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|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
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|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
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|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
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|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
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|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
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|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
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|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
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#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
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|| ((__VALUE__) == LL_SPI_MSB_FIRST))
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/**
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* @}
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*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup SPI_LL_Exported_Functions
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* @{
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*/
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/** @addtogroup SPI_LL_EF_Init
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* @{
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*/
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/**
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* @brief De-initialize the SPI registers to their default reset values.
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* @param SPIx SPI Instance
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: SPI registers are de-initialized
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* - ERROR: SPI registers are not de-initialized
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*/
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ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
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{
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ErrorStatus status = ERROR;
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/* Check the parameters */
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assert_param(IS_SPI_ALL_INSTANCE(SPIx));
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if (SPIx == SPI1)
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{
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/* Force reset of SPI clock */
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LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SPI1);
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/* Release reset of SPI clock */
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LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SPI1);
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status = SUCCESS;
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}
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return status;
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}
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/**
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* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
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* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
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* SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
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* @param SPIx SPI Instance
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* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
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* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
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*/
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ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
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{
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ErrorStatus status = ERROR;
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/* Check the SPI Instance SPIx*/
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assert_param(IS_SPI_ALL_INSTANCE(SPIx));
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/* Check the SPI parameters from SPI_InitStruct*/
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assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
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assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
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assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
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assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
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assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
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assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
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assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
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assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
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if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
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{
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/*---------------------------- SPIx CR1 Configuration ------------------------
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* Configure SPIx CR1 with parameters:
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* - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
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* - Master/Slave Mode: SPI_CR1_MSTR bit
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* - ClockPolarity: SPI_CR1_CPOL bit
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* - ClockPhase: SPI_CR1_CPHA bit
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* - NSS management: SPI_CR1_SSM bit
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* - BaudRate prescaler: SPI_CR1_BR[2:0] bits
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* - BitOrder: SPI_CR1_LSBFIRST bit
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* - DataWidth: SPI_CR1_DFF bit
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*/
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MODIFY_REG(SPIx->CR1,
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SPI_CR1_CLEAR_MASK,
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SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
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SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
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(SPI_InitStruct->NSS & SPI_CR1_SSM) | SPI_InitStruct->BaudRate |
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SPI_InitStruct->BitOrder | SPI_InitStruct->DataWidth);
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/*---------------------------- SPIx CR2 Configuration ------------------------
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* Configure SPIx CR2 with parameters:
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* - NSS management: SSOE bit
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*/
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MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((SPI_InitStruct->NSS >> 16U) & SPI_CR2_SSOE));
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status = SUCCESS;
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}
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return status;
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}
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/**
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* @brief Set each @ref LL_SPI_InitTypeDef field to default value.
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* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
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* whose fields will be set to default values.
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* @retval None
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*/
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void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
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{
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/* Set SPI_InitStruct fields to default values */
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SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
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SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
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SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
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SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
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SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
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SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
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SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
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SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* defined (SPI1) */
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/**
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* @}
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*/
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#endif /* USE_FULL_LL_DRIVER */
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/************************ (C) COPYRIGHT Puya *****END OF FILE****/
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