собрал проект со всеми библиотеками
This commit is contained in:
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/**
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******************************************************************************
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* @file stm32f1xx_hal_can_ex_legacy.h
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* @author MCD Application Team
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* @brief Header file of CAN HAL Extension module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F1xx_HAL_CAN_EX_LEGACY_H
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#define __STM32F1xx_HAL_CAN_EX_LEGACY_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
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defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal_def.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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/** @defgroup CANEx CANEx
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief CAN filter configuration structure definition
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*/
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/* CAN filter banks differences over STM32F1 devices: */
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/* - STM32F1 Connectivity line: 28 filter banks shared between CAN1 and CAN2 */
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/* - Other STM32F10x devices: 14 filter banks */
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typedef struct
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{
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uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
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configuration, first one for a 16-bit configuration).
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
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uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
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configuration, second one for a 16-bit configuration).
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
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uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
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according to the mode (MSBs for a 32-bit configuration,
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first one for a 16-bit configuration).
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
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uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
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according to the mode (LSBs for a 32-bit configuration,
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second one for a 16-bit configuration).
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
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uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
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This parameter can be a value of @ref CAN_filter_FIFO */
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#if defined(STM32F105xC) || defined(STM32F107xC)
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uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
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This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
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#else
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uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
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This parameter must be a number between Min_Data = 0 and Max_Data = 13. */
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#endif /* STM32F105xC || STM32F107xC */
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uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
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This parameter can be a value of @ref CAN_filter_mode */
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uint32_t FilterScale; /*!< Specifies the filter scale.
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This parameter can be a value of @ref CAN_filter_scale */
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uint32_t FilterActivation; /*!< Enable or disable the filter.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t BankNumber; /*!< Select the start slave bank filter
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This parameter must be a number between Min_Data = 0 and Max_Data = 28. */
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}CAN_FilterConfTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/* Exported macro ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/** @defgroup CANEx_Private_Macros CAN Extended Private Macros
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* @{
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*/
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#if defined(STM32F105xC) || defined(STM32F107xC)
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#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
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#else
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#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13U)
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#endif /* STM32F105xC || STM32F107xC */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32F1xx_HAL_CAN_EX_LEGACY_H */
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@@ -0,0 +1,776 @@
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/**
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******************************************************************************
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* @file stm32f1xx_hal_can_legacy.h
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* @author MCD Application Team
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* @brief Header file of CAN HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F1xx_HAL_CAN_LEGACY_H
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#define __STM32F1xx_HAL_CAN_LEGACY_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
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defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal_def.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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/** @addtogroup CAN
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup CAN_Exported_Types CAN Exported Types
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* @{
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*/
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/**
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* @brief HAL State structures definition
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*/
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typedef enum
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{
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HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
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HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
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HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
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HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
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}HAL_CAN_StateTypeDef;
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/**
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* @brief CAN init structure definition
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*/
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typedef struct
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{
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uint32_t Prescaler; /*!< Specifies the length of a time quantum.
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This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
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uint32_t Mode; /*!< Specifies the CAN operating mode.
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This parameter can be a value of @ref CAN_operating_mode */
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uint32_t SJW; /*!< Specifies the maximum number of time quanta
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the CAN hardware is allowed to lengthen or
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shorten a bit to perform resynchronization.
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This parameter can be a value of @ref CAN_synchronisation_jump_width */
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uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
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This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
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uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
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This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
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uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
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This parameter can be set to ENABLE or DISABLE */
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}CAN_InitTypeDef;
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/**
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* @brief CAN Tx message structure definition
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*/
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typedef struct
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{
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uint32_t StdId; /*!< Specifies the standard identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
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uint32_t ExtId; /*!< Specifies the extended identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
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uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
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This parameter can be a value of @ref CAN_Identifier_Type */
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uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
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This parameter can be a value of @ref CAN_remote_transmission_request */
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uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
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This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
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uint8_t Data[8]; /*!< Contains the data to be transmitted.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
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}CanTxMsgTypeDef;
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/**
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* @brief CAN Rx message structure definition
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*/
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typedef struct
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{
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uint32_t StdId; /*!< Specifies the standard identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
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uint32_t ExtId; /*!< Specifies the extended identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
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uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
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This parameter can be a value of @ref CAN_Identifier_Type */
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uint32_t RTR; /*!< Specifies the type of frame for the received message.
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This parameter can be a value of @ref CAN_remote_transmission_request */
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uint32_t DLC; /*!< Specifies the length of the frame that will be received.
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This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
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uint8_t Data[8]; /*!< Contains the data to be received.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
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uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
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uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
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This parameter can be CAN_FIFO0 or CAN_FIFO1 */
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}CanRxMsgTypeDef;
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/**
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* @brief CAN handle Structure definition
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*/
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typedef struct
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{
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CAN_TypeDef *Instance; /*!< Register base address */
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CAN_InitTypeDef Init; /*!< CAN required parameters */
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CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
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CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
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CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
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__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
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HAL_LockTypeDef Lock; /*!< CAN locking object */
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__IO uint32_t ErrorCode; /*!< CAN Error code */
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}CAN_HandleTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup CAN_Exported_Constants CAN Exported Constants
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* @{
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*/
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/** @defgroup CAN_Error_Code CAN Error Code
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* @{
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*/
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#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
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#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
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#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
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#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
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#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
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#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
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#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
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#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
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#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
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#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
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#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
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#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
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#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
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/**
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* @}
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*/
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/** @defgroup CAN_InitStatus CAN initialization Status
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* @{
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*/
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#define CAN_INITSTATUS_FAILED 0x00000000U /*!< CAN initialization failed */
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#define CAN_INITSTATUS_SUCCESS 0x00000001U /*!< CAN initialization OK */
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/**
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* @}
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*/
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/** @defgroup CAN_operating_mode CAN Operating Mode
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* @{
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*/
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#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
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#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
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#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
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#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
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/**
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* @}
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*/
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/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
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* @{
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*/
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#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
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#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
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#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
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#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
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/**
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* @}
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*/
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/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
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* @{
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*/
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#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
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#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
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#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
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#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
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#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
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#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
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#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
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#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
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#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
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#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
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#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
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#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
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#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
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#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
|
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#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
|
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#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
|
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/**
|
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* @}
|
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*/
|
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|
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/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
|
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* @{
|
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*/
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#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
|
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#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
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#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
|
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#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
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#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
|
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#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
|
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#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
|
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#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
|
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/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode CAN Filter Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
|
||||
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale CAN Filter Scale
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
|
||||
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Identifier_Type CAN Identifier Type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_ID_STD 0x00000000U /*!< Standard Id */
|
||||
#define CAN_ID_EXT 0x00000004U /*!< Extended Id */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RTR_DATA 0x00000000U /*!< Data frame */
|
||||
#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_transmit_constants CAN Transmit Constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags CAN Flags
|
||||
* @{
|
||||
*/
|
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions. */
|
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
|
||||
CAN_GetFlagStatus() function. */
|
||||
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Request MailBox0 flag */
|
||||
#define CAN_FLAG_RQCP1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION)) /*!< Request MailBox1 flag */
|
||||
#define CAN_FLAG_RQCP2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION)) /*!< Request MailBox2 flag */
|
||||
#define CAN_FLAG_TXOK0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION)) /*!< Transmission OK MailBox0 flag */
|
||||
#define CAN_FLAG_TXOK1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION)) /*!< Transmission OK MailBox1 flag */
|
||||
#define CAN_FLAG_TXOK2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK2_BIT_POSITION)) /*!< Transmission OK MailBox2 flag */
|
||||
#define CAN_FLAG_TME0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FF0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION)) /*!< FIFO 0 Full flag */
|
||||
#define CAN_FLAG_FOV0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION)) /*!< FIFO 0 Overrun flag */
|
||||
|
||||
#define CAN_FLAG_FF1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION)) /*!< FIFO 1 Full flag */
|
||||
#define CAN_FLAG_FOV1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION)) /*!< FIFO 1 Overrun flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION)) /*!< Wake up flag */
|
||||
#define CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION)) /*!< Sleep acknowledge flag */
|
||||
#define CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION)) /*!< Sleep acknowledge flag */
|
||||
|
||||
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION)) /*!< Error warning flag */
|
||||
#define CAN_FLAG_EPV ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION)) /*!< Error passive flag */
|
||||
#define CAN_FLAG_BOF ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION)) /*!< Bus-Off flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Interrupts CAN Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
|
||||
#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
|
||||
#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
|
||||
#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
|
||||
#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
|
||||
#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
|
||||
#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
|
||||
#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
|
||||
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
|
||||
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
|
||||
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Private_Constants CAN Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* CAN intermediate shift values used for CAN flags */
|
||||
#define TSR_REGISTER_INDEX 0x5U
|
||||
#define RF0R_REGISTER_INDEX 0x2U
|
||||
#define RF1R_REGISTER_INDEX 0x4U
|
||||
#define MSR_REGISTER_INDEX 0x1U
|
||||
#define ESR_REGISTER_INDEX 0x3U
|
||||
|
||||
/* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR registers) */
|
||||
/* Transmit Flags */
|
||||
#define CAN_TSR_RQCP0_BIT_POSITION 0x00000000U
|
||||
#define CAN_TSR_RQCP1_BIT_POSITION 0x00000008U
|
||||
#define CAN_TSR_RQCP2_BIT_POSITION 0x00000010U
|
||||
#define CAN_TSR_TXOK0_BIT_POSITION 0x00000001U
|
||||
#define CAN_TSR_TXOK1_BIT_POSITION 0x00000009U
|
||||
#define CAN_TSR_TXOK2_BIT_POSITION 0x00000011U
|
||||
#define CAN_TSR_TME0_BIT_POSITION 0x0000001AU
|
||||
#define CAN_TSR_TME1_BIT_POSITION 0x0000001BU
|
||||
#define CAN_TSR_TME2_BIT_POSITION 0x0000001CU
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_RF0R_FF0_BIT_POSITION 0x00000003U
|
||||
#define CAN_RF0R_FOV0_BIT_POSITION 0x00000004U
|
||||
|
||||
#define CAN_RF1R_FF1_BIT_POSITION 0x00000003U
|
||||
#define CAN_RF1R_FOV1_BIT_POSITION 0x00000004U
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_MSR_WKU_BIT_POSITION 0x00000003U
|
||||
#define CAN_MSR_SLAK_BIT_POSITION 0x00000001U
|
||||
#define CAN_MSR_SLAKI_BIT_POSITION 0x00000004U
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_ESR_EWG_BIT_POSITION 0x00000000U
|
||||
#define CAN_ESR_EPV_BIT_POSITION 0x00000001U
|
||||
#define CAN_ESR_BOF_BIT_POSITION 0x00000002U
|
||||
|
||||
/* Mask used by macro to get/clear CAN flags*/
|
||||
#define CAN_FLAG_MASK 0x000000FFU
|
||||
|
||||
/* Mailboxes definition */
|
||||
#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
|
||||
#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
|
||||
#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CAN_Exported_Macros CAN Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CAN handle state
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified CAN interrupts
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @param __INTERRUPT__: CAN Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
|
||||
* @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
|
||||
* @arg CAN_IT_FF0 : FIFO 0 full interrupt
|
||||
* @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
|
||||
* @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
|
||||
* @arg CAN_IT_FF1 : FIFO 1 full interrupt
|
||||
* @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
|
||||
* @arg CAN_IT_WKU : Wake-up interrupt
|
||||
* @arg CAN_IT_SLK : Sleep acknowledge interrupt
|
||||
* @arg CAN_IT_EWG : Error warning interrupt
|
||||
* @arg CAN_IT_EPV : Error passive interrupt
|
||||
* @arg CAN_IT_BOF : Bus-off interrupt
|
||||
* @arg CAN_IT_LEC : Last error code interrupt
|
||||
* @arg CAN_IT_ERR : Error Interrupt
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified CAN interrupts
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @param __INTERRUPT__: CAN Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
|
||||
* @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
|
||||
* @arg CAN_IT_FF0 : FIFO 0 full interrupt
|
||||
* @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
|
||||
* @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
|
||||
* @arg CAN_IT_FF1 : FIFO 1 full interrupt
|
||||
* @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
|
||||
* @arg CAN_IT_WKU : Wake-up interrupt
|
||||
* @arg CAN_IT_SLK : Sleep acknowledge interrupt
|
||||
* @arg CAN_IT_EWG : Error warning interrupt
|
||||
* @arg CAN_IT_EPV : Error passive interrupt
|
||||
* @arg CAN_IT_BOF : Bus-off interrupt
|
||||
* @arg CAN_IT_LEC : Last error code interrupt
|
||||
* @arg CAN_IT_ERR : Error Interrupt
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Return the number of pending received messages.
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||||
* @retval The number of pending message.
|
||||
*/
|
||||
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
||||
((uint8_t)((__HANDLE__)->Instance->RF0R & 0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
|
||||
|
||||
/** @brief Check whether the specified CAN flag is set or not.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
||||
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
||||
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
||||
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
||||
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
||||
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
||||
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKU: Wake up Flag
|
||||
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_EWG: Error Warning Flag
|
||||
* @arg CAN_FLAG_EPV: Error Passive Flag
|
||||
* @arg CAN_FLAG_BOF: Bus-Off Flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
|
||||
|
||||
/** @brief Clear the specified CAN pending flag.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
||||
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
||||
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
||||
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
||||
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
||||
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
||||
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKU: Wake up Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
|
||||
|
||||
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __INTERRUPT__: specifies the CAN interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
|
||||
* @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
|
||||
* @arg CAN_IT_FF0 : FIFO 0 full interrupt
|
||||
* @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
|
||||
* @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
|
||||
* @arg CAN_IT_FF1 : FIFO 1 full interrupt
|
||||
* @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
|
||||
* @arg CAN_IT_WKU : Wake-up interrupt
|
||||
* @arg CAN_IT_SLK : Sleep acknowledge interrupt
|
||||
* @arg CAN_IT_EWG : Error warning interrupt
|
||||
* @arg CAN_IT_EPV : Error passive interrupt
|
||||
* @arg CAN_IT_BOF : Bus-off interrupt
|
||||
* @arg CAN_IT_LEC : Last error code interrupt
|
||||
* @arg CAN_IT_ERR : Error Interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Check the transmission status of a CAN Frame.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
|
||||
* @retval The new status of transmission (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
|
||||
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
|
||||
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
|
||||
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
|
||||
|
||||
/**
|
||||
* @brief Release the specified receive FIFO.
|
||||
* @param __HANDLE__: CAN handle.
|
||||
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
||||
((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
|
||||
|
||||
/**
|
||||
* @brief Cancel a transmit request.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
|
||||
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
|
||||
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
|
||||
((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
|
||||
|
||||
/**
|
||||
* @brief Enable or disables the DBG Freeze for CAN.
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @param __NEWSTATE__: new state of the CAN peripheral.
|
||||
* This parameter can be: ENABLE (CAN reception/transmission is frozen
|
||||
* during debug. Reception FIFOs can still be accessed/controlled normally)
|
||||
* or DISABLE (CAN is working during debug).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
|
||||
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include CAN HAL Extension module */
|
||||
#include "stm32f1xx_hal_can_ex_legacy.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CAN_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group1
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
|
||||
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group2
|
||||
* @brief I/O operation functions
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
|
||||
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group3
|
||||
* @brief CAN Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
|
||||
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Macros CAN Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
|
||||
((MODE) == CAN_MODE_LOOPBACK)|| \
|
||||
((MODE) == CAN_MODE_SILENT) || \
|
||||
((MODE) == CAN_MODE_SILENT_LOOPBACK))
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
|
||||
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
|
||||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
|
||||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
|
||||
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
|
||||
((MODE) == CAN_FILTERMODE_IDLIST))
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
|
||||
((SCALE) == CAN_FILTERSCALE_32BIT))
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
|
||||
((FIFO) == CAN_FILTER_FIFO1))
|
||||
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
|
||||
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= 0x00007FFU)
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
|
||||
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
|
||||
((IDTYPE) == CAN_ID_EXT))
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
|
||||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_CAN_LEGACY_H */
|
||||
56
Drivers/STM32F1xx_HAL_Driver/Inc/stm32_assert_template.h
Normal file
56
Drivers/STM32F1xx_HAL_Driver/Inc/stm32_assert_template.h
Normal file
@@ -0,0 +1,56 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32_assert.h
|
||||
* @author MCD Application Team
|
||||
* @brief STM32 assert template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32_assert.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32_ASSERT_H
|
||||
#define __STM32_ASSERT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32_ASSERT_H */
|
||||
|
||||
|
||||
|
||||
1000
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h
Normal file
1000
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h
Normal file
File diff suppressed because it is too large
Load Diff
706
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h
Normal file
706
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h
Normal file
@@ -0,0 +1,706 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_adc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of ADC HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_ADC_EX_H
|
||||
#define __STM32F1xx_HAL_ADC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ADC Configuration injected Channel structure definition
|
||||
* @note Parameters of this structure are shared within 2 scopes:
|
||||
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
|
||||
* - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
|
||||
* AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
|
||||
* @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
|
||||
* - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
|
||||
This parameter can be a value of @ref ADC_channels
|
||||
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
|
||||
Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
|
||||
Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
|
||||
It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
|
||||
Refer to errata sheet of these devices for more details. */
|
||||
uint32_t InjectedRank; /*!< Rank in the injected group sequencer
|
||||
This parameter must be a value of @ref ADCEx_injected_rank
|
||||
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
|
||||
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles
|
||||
Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
|
||||
This parameter can be a value of @ref ADC_sampling_times
|
||||
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
|
||||
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
|
||||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
|
||||
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
|
||||
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
|
||||
Offset value must be a positive number.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
|
||||
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
|
||||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
|
||||
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
|
||||
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
|
||||
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
|
||||
To maintain JAUTO always enabled, DMA must be configured in circular mode.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
|
||||
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
|
||||
If set to external trigger source, triggering is on event rising edge.
|
||||
This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
|
||||
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
}ADC_InjectionConfTypeDef;
|
||||
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||
/**
|
||||
* @brief Structure definition of ADC multimode
|
||||
* @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
|
||||
* State of ADCs of the common group must be: disabled.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
|
||||
This parameter can be a value of @ref ADCEx_Common_mode
|
||||
Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change.
|
||||
Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2.
|
||||
Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode.
|
||||
Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters).
|
||||
The equivalences are:
|
||||
- Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
|
||||
- Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */
|
||||
|
||||
|
||||
}ADC_MultiModeTypeDef;
|
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_injected_rank ADCEx rank into injected group
|
||||
* @{
|
||||
*/
|
||||
#define ADC_INJECTED_RANK_1 0x00000001U
|
||||
#define ADC_INJECTED_RANK_2 0x00000002U
|
||||
#define ADC_INJECTED_RANK_3 0x00000003U
|
||||
#define ADC_INJECTED_RANK_4 0x00000004U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group
|
||||
* @{
|
||||
*/
|
||||
/*!< List of external triggers with generic trigger name, independently of */
|
||||
/* ADC target, sorted by trigger name: */
|
||||
|
||||
/*!< External triggers of regular group for ADC1&ADC2 only */
|
||||
#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
|
||||
#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
|
||||
#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
|
||||
#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
|
||||
#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
|
||||
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
|
||||
|
||||
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||
/*!< External triggers of regular group for ADC3 only */
|
||||
#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3
|
||||
#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1
|
||||
#define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1
|
||||
#define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3
|
||||
#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1
|
||||
#endif /* STM32F103xE || defined STM32F103xG */
|
||||
|
||||
/*!< External triggers of regular group for all ADC instances */
|
||||
#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3
|
||||
|
||||
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||
/*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
|
||||
/* XL-density devices. */
|
||||
/* To use it on ADC or ADC2, a remap of trigger must be done from */
|
||||
/* EXTI line 11 to TIM8_TRGO with macro: */
|
||||
/* __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() */
|
||||
/* __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() */
|
||||
|
||||
/* Note for internal constant value management: If TIM8_TRGO is available, */
|
||||
/* its definition is set to value for ADC1&ADC2 by default and changed to */
|
||||
/* value for ADC3 by HAL ADC driver if ADC3 is selected. */
|
||||
#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
|
||||
#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||
|
||||
#define ADC_SOFTWARE_START ADC1_2_3_SWSTART
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group
|
||||
* @{
|
||||
*/
|
||||
/*!< List of external triggers with generic trigger name, independently of */
|
||||
/* ADC target, sorted by trigger name: */
|
||||
|
||||
/*!< External triggers of injected group for ADC1&ADC2 only */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
|
||||
|
||||
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||
/*!< External triggers of injected group for ADC3 only */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_EXTERNALTRIGINJEC_T4_CC3
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_EXTERNALTRIGINJEC_T8_CC2
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ADC3_EXTERNALTRIGINJEC_T5_CC4
|
||||
#endif /* STM32F103xE || defined STM32F103xG */
|
||||
|
||||
/*!< External triggers of injected group for all ADC instances */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO
|
||||
|
||||
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||
/*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
|
||||
/* XL-density devices. */
|
||||
/* To use it on ADC1 or ADC2, a remap of trigger must be done from */
|
||||
/* EXTI line 11 to TIM8_CC4 with macro: */
|
||||
/* __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() */
|
||||
/* __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() */
|
||||
|
||||
/* Note for internal constant value management: If TIM8_CC4 is available, */
|
||||
/* its definition is set to value for ADC1&ADC2 by default and changed to */
|
||||
/* value for ADC3 by HAL ADC driver if ADC3 is selected. */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
|
||||
#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||
|
||||
#define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||
/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
|
||||
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */
|
||||
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */
|
||||
#define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
|
||||
#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
|
||||
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */
|
||||
#define ADC_DUALMODE_REGSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */
|
||||
#define ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
|
||||
#define ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 )) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
|
||||
#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
|
||||
* @{
|
||||
*/
|
||||
/* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC */
|
||||
/* instance is available on the selected device). */
|
||||
/* (used internally by HAL driver. To not use into HAL structure parameters) */
|
||||
|
||||
/* External triggers of regular group for ADC1&ADC2 (if ADCx available) */
|
||||
#define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U
|
||||
#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0))
|
||||
#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 ))
|
||||
#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 ))
|
||||
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||
/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
|
||||
/* XL-density devices. */
|
||||
#define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11
|
||||
#endif
|
||||
|
||||
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||
/* External triggers of regular group for ADC3 */
|
||||
#define ADC3_EXTERNALTRIG_T3_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
|
||||
#define ADC3_EXTERNALTRIG_T2_CC3 ADC1_2_EXTERNALTRIG_T1_CC2
|
||||
#define ADC3_EXTERNALTRIG_T8_CC1 ADC1_2_EXTERNALTRIG_T2_CC2
|
||||
#define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
|
||||
#define ADC3_EXTERNALTRIG_T5_CC1 ADC1_2_EXTERNALTRIG_T4_CC4
|
||||
#define ADC3_EXTERNALTRIG_T5_CC3 ADC1_2_EXTERNALTRIG_EXT_IT11
|
||||
#endif
|
||||
|
||||
/* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */
|
||||
#define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
|
||||
#define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
|
||||
* @{
|
||||
*/
|
||||
/* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC */
|
||||
/* instance is available on the selected device). */
|
||||
/* (used internally by HAL driver. To not use into HAL structure parameters) */
|
||||
|
||||
/* External triggers of injected group for ADC1&ADC2 (if ADCx available) */
|
||||
#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 ))
|
||||
#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 ))
|
||||
#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 ))
|
||||
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||
/* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
|
||||
/* XL-density devices. */
|
||||
#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
|
||||
#endif
|
||||
|
||||
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||
/* External triggers of injected group for ADC3 */
|
||||
#define ADC3_EXTERNALTRIGINJEC_T4_CC3 ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
|
||||
#define ADC3_EXTERNALTRIGINJEC_T8_CC2 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
|
||||
#define ADC3_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
|
||||
#define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
|
||||
#define ADC3_EXTERNALTRIGINJEC_T5_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
|
||||
#endif /* STM32F103xE || defined STM32F103xG */
|
||||
|
||||
/* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */
|
||||
#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U
|
||||
#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0))
|
||||
#define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADCEx_Private_Macro ADCEx Private Macro
|
||||
* @{
|
||||
*/
|
||||
/* Macro reserved for internal HAL driver usage, not intended to be used in */
|
||||
/* code of final user. */
|
||||
|
||||
|
||||
/**
|
||||
* @brief For devices with 3 ADCs: Defines the external trigger source
|
||||
* for regular group according to ADC into common group ADC1&ADC2 or
|
||||
* ADC3 (some triggers with same source have different value to
|
||||
* be programmed into ADC EXTSEL bits of CR2 register).
|
||||
* For devices with 2 ADCs or less: this macro makes no change.
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @param __EXT_TRIG_CONV__: External trigger selected for regular group.
|
||||
* @retval External trigger to be programmed into EXTSEL bits of CR2 register
|
||||
*/
|
||||
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||
#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
|
||||
(( (((__HANDLE__)->Instance) == ADC3) \
|
||||
)? \
|
||||
( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
|
||||
)? \
|
||||
(ADC3_EXTERNALTRIG_T8_TRGO) \
|
||||
: \
|
||||
(__EXT_TRIG_CONV__) \
|
||||
) \
|
||||
: \
|
||||
(__EXT_TRIG_CONV__) \
|
||||
)
|
||||
#else
|
||||
#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
|
||||
(__EXT_TRIG_CONV__)
|
||||
#endif /* STM32F103xE || STM32F103xG */
|
||||
|
||||
/**
|
||||
* @brief For devices with 3 ADCs: Defines the external trigger source
|
||||
* for injected group according to ADC into common group ADC1&ADC2 or
|
||||
* ADC3 (some triggers with same source have different value to
|
||||
* be programmed into ADC JEXTSEL bits of CR2 register).
|
||||
* For devices with 2 ADCs or less: this macro makes no change.
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group.
|
||||
* @retval External trigger to be programmed into JEXTSEL bits of CR2 register
|
||||
*/
|
||||
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||
#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
|
||||
(( (((__HANDLE__)->Instance) == ADC3) \
|
||||
)? \
|
||||
( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
|
||||
)? \
|
||||
(ADC3_EXTERNALTRIGINJEC_T8_CC4) \
|
||||
: \
|
||||
(__EXT_TRIG_INJECTCONV__) \
|
||||
) \
|
||||
: \
|
||||
(__EXT_TRIG_INJECTCONV__) \
|
||||
)
|
||||
#else
|
||||
#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
|
||||
(__EXT_TRIG_INJECTCONV__)
|
||||
#endif /* STM32F103xE || STM32F103xG */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
|
||||
*/
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \
|
||||
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
|
||||
)? \
|
||||
(ADC1->CR1 & ADC_CR1_DUALMOD) \
|
||||
: \
|
||||
(RESET) \
|
||||
)
|
||||
#else
|
||||
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \
|
||||
(RESET)
|
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||
|
||||
/**
|
||||
* @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
|
||||
(( (((__HANDLE__)->Instance) == ADC2) \
|
||||
)? \
|
||||
((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) \
|
||||
: \
|
||||
(!RESET) \
|
||||
)
|
||||
#else
|
||||
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
|
||||
(!RESET)
|
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||
|
||||
/**
|
||||
* @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
|
||||
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
|
||||
)? \
|
||||
(ADC1->CR1 & ADC_CR1_JAUTO) \
|
||||
: \
|
||||
(RESET) \
|
||||
)
|
||||
#else
|
||||
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
|
||||
(RESET)
|
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||
/**
|
||||
* @brief Set handle of the other ADC sharing the common multimode settings
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @param __HANDLE_OTHER_ADC__: other ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
|
||||
((__HANDLE_OTHER_ADC__)->Instance = ADC2)
|
||||
|
||||
/**
|
||||
* @brief Set handle of the ADC slave associated to the ADC master
|
||||
* On STM32F1 devices, ADC slave is always ADC2 (this can be different
|
||||
* on other STM32 devices)
|
||||
* @param __HANDLE_MASTER__: ADC master handle
|
||||
* @param __HANDLE_SLAVE__: ADC slave handle
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
|
||||
((__HANDLE_SLAVE__)->Instance = ADC2)
|
||||
|
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||
|
||||
#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
|
||||
((CHANNEL) == ADC_INJECTED_RANK_2) || \
|
||||
((CHANNEL) == ADC_INJECTED_RANK_3) || \
|
||||
((CHANNEL) == ADC_INJECTED_RANK_4))
|
||||
|
||||
#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
|
||||
((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
|
||||
|
||||
/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
|
||||
((REGTRIG) == ADC_SOFTWARE_START))
|
||||
#endif
|
||||
#if defined (STM32F101xE)
|
||||
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
|
||||
((REGTRIG) == ADC_SOFTWARE_START))
|
||||
#endif
|
||||
#if defined (STM32F101xG)
|
||||
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
|
||||
((REGTRIG) == ADC_SOFTWARE_START))
|
||||
#endif
|
||||
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
|
||||
((REGTRIG) == ADC_SOFTWARE_START))
|
||||
#endif
|
||||
|
||||
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
|
||||
#endif
|
||||
#if defined (STM32F101xE)
|
||||
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
|
||||
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
|
||||
#endif
|
||||
#if defined (STM32F101xG)
|
||||
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
|
||||
#endif
|
||||
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
|
||||
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
|
||||
#endif
|
||||
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
|
||||
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
|
||||
((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
|
||||
((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \
|
||||
((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \
|
||||
((MODE) == ADC_DUALMODE_INJECSIMULT) || \
|
||||
((MODE) == ADC_DUALMODE_REGSIMULT) || \
|
||||
((MODE) == ADC_DUALMODE_INTERLFAST) || \
|
||||
((MODE) == ADC_DUALMODE_INTERLSLOW) || \
|
||||
((MODE) == ADC_DUALMODE_ALTERTRIG) )
|
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ADCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup ADCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ADC calibration */
|
||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
||||
|
||||
/* Non-blocking mode: Interruption */
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
|
||||
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||
/* ADC multimode */
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
|
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||
|
||||
/* ADC retrieve conversion value intended to be used with polling or interruption */
|
||||
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
|
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||
|
||||
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
|
||||
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/** @addtogroup ADCEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
|
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_ADC_EX_H */
|
||||
559
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cec.h
Normal file
559
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cec.h
Normal file
@@ -0,0 +1,559 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_cec.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CEC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_CEC_H
|
||||
#define __STM32F1xx_HAL_CEC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
#if defined (CEC)
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Types CEC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CEC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TimingErrorFree; /*!< Configures the CEC Bit Timing Error Mode.
|
||||
This parameter can be a value of CEC_BitTimingErrorMode */
|
||||
|
||||
uint32_t PeriodErrorFree; /*!< Configures the CEC Bit Period Error Mode.
|
||||
This parameter can be a value of CEC_BitPeriodErrorMode */
|
||||
|
||||
uint16_t OwnAddress; /*!< Own addresses configuration
|
||||
This parameter can be a value of @ref CEC_OWN_ADDRESS */
|
||||
|
||||
uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */
|
||||
} CEC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC State definition
|
||||
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState
|
||||
(see @ref CEC_State_Definition).
|
||||
* - gState contains CEC state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7 (not used)
|
||||
* x : Should be set to 0
|
||||
* b6 Error information
|
||||
* 0 : No Error
|
||||
* 1 : Error
|
||||
* b5 CEC peripheral initialization status
|
||||
* 0 : Reset (peripheral not initialized)
|
||||
* 1 : Init done (peripheral initialized. HAL CEC Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (peripheral busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 CEC peripheral initialization status
|
||||
* 0 : Reset (peripheral not initialized)
|
||||
* 1 : Init done (peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
|
||||
} HAL_CEC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CEC handle Structure definition
|
||||
*/
|
||||
typedef struct __CEC_HandleTypeDef
|
||||
{
|
||||
CEC_TypeDef *Instance; /*!< CEC registers base address */
|
||||
|
||||
CEC_InitTypeDef Init; /*!< CEC communication parameters */
|
||||
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
|
||||
|
||||
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
|
||||
|
||||
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
|
||||
|
||||
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
|
||||
in case error is reported */
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
void (* TxCpltCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Tx Transfer completed callback */
|
||||
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
|
||||
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
|
||||
} CEC_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL CEC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
|
||||
HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
|
||||
HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
|
||||
HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
|
||||
HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
|
||||
} HAL_CEC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
|
||||
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
|
||||
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed
|
||||
callback function */
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Constants CEC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Error_Code CEC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CEC_ERROR_NONE 0x00000000U /*!< no error */
|
||||
#define HAL_CEC_ERROR_BTE CEC_ESR_BTE /*!< Bit Timing Error */
|
||||
#define HAL_CEC_ERROR_BPE CEC_ESR_BPE /*!< Bit Period Error */
|
||||
#define HAL_CEC_ERROR_RBTFE CEC_ESR_RBTFE /*!< Rx Block Transfer Finished Error */
|
||||
#define HAL_CEC_ERROR_SBE CEC_ESR_SBE /*!< Start Bit Error */
|
||||
#define HAL_CEC_ERROR_ACKE CEC_ESR_ACKE /*!< Block Acknowledge Error */
|
||||
#define HAL_CEC_ERROR_LINE CEC_ESR_LINE /*!< Line Error */
|
||||
#define HAL_CEC_ERROR_TBTFE CEC_ESR_TBTFE /*!< Tx Block Transfer Finished Error */
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback Error */
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BitTimingErrorMode Bit Timing Error Mode
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BIT_TIMING_ERROR_MODE_STANDARD 0x00000000U /*!< Bit timing error Standard Mode */
|
||||
#define CEC_BIT_TIMING_ERROR_MODE_ERRORFREE CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BitPeriodErrorMode Bit Period Error Mode
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BIT_PERIOD_ERROR_MODE_STANDARD 0x00000000U /*!< Bit period error Standard Mode */
|
||||
#define CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
|
||||
* @{
|
||||
*/
|
||||
#define CEC_INITIATOR_LSB_POS 4U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
|
||||
* @{
|
||||
*/
|
||||
#define CEC_OWN_ADDRESS_NONE CEC_OWN_ADDRESS_0 /* Reset value */
|
||||
#define CEC_OWN_ADDRESS_0 ((uint16_t)0x0000U) /* Logical Address 0 */
|
||||
#define CEC_OWN_ADDRESS_1 ((uint16_t)0x0001U) /* Logical Address 1 */
|
||||
#define CEC_OWN_ADDRESS_2 ((uint16_t)0x0002U) /* Logical Address 2 */
|
||||
#define CEC_OWN_ADDRESS_3 ((uint16_t)0x0003U) /* Logical Address 3 */
|
||||
#define CEC_OWN_ADDRESS_4 ((uint16_t)0x0004U) /* Logical Address 4 */
|
||||
#define CEC_OWN_ADDRESS_5 ((uint16_t)0x0005U) /* Logical Address 5 */
|
||||
#define CEC_OWN_ADDRESS_6 ((uint16_t)0x0006U) /* Logical Address 6 */
|
||||
#define CEC_OWN_ADDRESS_7 ((uint16_t)0x0007U) /* Logical Address 7 */
|
||||
#define CEC_OWN_ADDRESS_8 ((uint16_t)0x0008U) /* Logical Address 8 */
|
||||
#define CEC_OWN_ADDRESS_9 ((uint16_t)0x0009U) /* Logical Address 9 */
|
||||
#define CEC_OWN_ADDRESS_10 ((uint16_t)0x000AU) /* Logical Address 10 */
|
||||
#define CEC_OWN_ADDRESS_11 ((uint16_t)0x000BU) /* Logical Address 11 */
|
||||
#define CEC_OWN_ADDRESS_12 ((uint16_t)0x000CU) /* Logical Address 12 */
|
||||
#define CEC_OWN_ADDRESS_13 ((uint16_t)0x000DU) /* Logical Address 13 */
|
||||
#define CEC_OWN_ADDRESS_14 ((uint16_t)0x000EU) /* Logical Address 14 */
|
||||
#define CEC_OWN_ADDRESS_15 ((uint16_t)0x000FU) /* Logical Address 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Interrupts_Definitions Interrupts definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IT_IE CEC_CFGR_IE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Flags_Definitions Flags definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_FLAG_TSOM CEC_CSR_TSOM
|
||||
#define CEC_FLAG_TEOM CEC_CSR_TEOM
|
||||
#define CEC_FLAG_TERR CEC_CSR_TERR
|
||||
#define CEC_FLAG_TBTRF CEC_CSR_TBTRF
|
||||
#define CEC_FLAG_RSOM CEC_CSR_RSOM
|
||||
#define CEC_FLAG_REOM CEC_CSR_REOM
|
||||
#define CEC_FLAG_RERR CEC_CSR_RERR
|
||||
#define CEC_FLAG_RBTF CEC_CSR_RBTF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Macros CEC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CEC handle gstate & RxState
|
||||
* @param __HANDLE__ CEC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
|
||||
} while(0)
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Checks whether or not the specified CEC interrupt flag is set.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* @arg CEC_FLAG_TERR: Tx Error
|
||||
* @arg CEC_FLAG_TBTRF:Tx Block Transfer Finished
|
||||
* @arg CEC_FLAG_RERR: Rx Error
|
||||
* @arg CEC_FLAG_RBTF: Rx Block Transfer Finished
|
||||
* @retval ITStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) READ_BIT((__HANDLE__)->Instance->CSR,(__FLAG__))
|
||||
|
||||
/** @brief Clears the CEC's pending flags.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg CEC_CSR_TERR: Tx Error
|
||||
* @arg CEC_FLAG_TBTRF: Tx Block Transfer Finished
|
||||
* @arg CEC_CSR_RERR: Rx Error
|
||||
* @arg CEC_CSR_RBTF: Rx Block Transfer Finished
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
do { \
|
||||
uint32_t tmp = 0x0U; \
|
||||
tmp = (__HANDLE__)->Instance->CSR & 0x00000002U; \
|
||||
(__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFCU) | tmp);\
|
||||
} while(0U)
|
||||
|
||||
/** @brief Enables the specified CEC interrupt.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_IE : Interrupt Enable.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Disables the specified CEC interrupt.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_IE : Interrupt Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Checks whether or not the specified CEC interrupt is enabled.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_IE : Interrupt Enable
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Enables the CEC device
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
|
||||
|
||||
/** @brief Disables the CEC device
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
|
||||
|
||||
/** @brief Set Transmission Start flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
|
||||
|
||||
/** @brief Set Transmission End flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
|
||||
|
||||
/** @brief Get Transmission Start flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
|
||||
|
||||
/** @brief Get Transmission End flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
|
||||
|
||||
/** @brief Clear OAR register
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->OAR, CEC_OAR_OA)
|
||||
|
||||
/** @brief Set OAR register
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __ADDRESS__ Own Address value.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) MODIFY_REG((__HANDLE__)->Instance->OAR, CEC_OAR_OA, (__ADDRESS__));
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CEC_Exported_Functions CEC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
|
||||
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
|
||||
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
|
||||
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
|
||||
pCEC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief CEC Transmit/Receive functions
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
|
||||
const uint8_t *pData, uint32_t Size);
|
||||
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
|
||||
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
|
||||
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief CEC control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec);
|
||||
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Types CEC Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Variables CEC Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Constants CEC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Macros CEC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \
|
||||
((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE))
|
||||
|
||||
#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \
|
||||
((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE))
|
||||
|
||||
/** @brief Check CEC message size.
|
||||
* The message size is the payload size: without counting the header,
|
||||
* it varies from 0 byte (ping operation, one header only, no payload) to
|
||||
* 15 bytes (1 opcode and up to 14 operands following the header).
|
||||
* @param __SIZE__ CEC message size.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
|
||||
|
||||
/** @brief Check CEC device Own Address Register (OAR) setting.
|
||||
* @param __ADDRESS__ CEC own address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
|
||||
|
||||
/** @brief Check CEC initiator or destination logical address setting.
|
||||
* Initiator and destination addresses are coded over 4 bits.
|
||||
* @param __ADDRESS__ CEC initiator or logical address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Functions CEC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* CEC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_CEC_H */
|
||||
|
||||
398
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_conf_template.h
Normal file
398
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_conf_template.h
Normal file
@@ -0,0 +1,398 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32f1xx_hal_conf.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_CONF_H
|
||||
#define __STM32F1xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_CAN_MODULE_ENABLED
|
||||
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
|
||||
#define HAL_CEC_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_DAC_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_ETH_MODULE_ENABLED
|
||||
#define HAL_EXTI_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_HCD_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_I2S_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_NAND_MODULE_ENABLED
|
||||
#define HAL_NOR_MODULE_ENABLED
|
||||
#define HAL_PCCARD_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
#define HAL_SD_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_SRAM_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
#define HAL_MMC_MODULE_ENABLED
|
||||
|
||||
/* ########################## Oscillator Values adaptation ####################*/
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#if defined(USE_STM3210C_EVAL)
|
||||
#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
|
||||
#else
|
||||
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
|
||||
#endif
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature. */
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0U
|
||||
#define PREFETCH_ENABLE 1U
|
||||
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
|
||||
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
|
||||
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
|
||||
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
|
||||
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
|
||||
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
|
||||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
|
||||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
|
||||
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
|
||||
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
|
||||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1U */
|
||||
|
||||
/* ################## Ethernet peripheral configuration ##################### */
|
||||
|
||||
/* Section 1 : Ethernet peripheral configuration */
|
||||
|
||||
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
|
||||
#define MAC_ADDR0 2U
|
||||
#define MAC_ADDR1 0U
|
||||
#define MAC_ADDR2 0U
|
||||
#define MAC_ADDR3 0U
|
||||
#define MAC_ADDR4 0U
|
||||
#define MAC_ADDR5 0U
|
||||
|
||||
/* Definition of the Ethernet driver buffers size and count */
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||
#define ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
|
||||
/* Section 2: PHY configuration section */
|
||||
|
||||
/* DP83848 PHY Address*/
|
||||
#define DP83848_PHY_ADDRESS 0x01U
|
||||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
||||
#define PHY_RESET_DELAY 0x000000FFU
|
||||
/* PHY Configuration delay */
|
||||
#define PHY_CONFIG_DELAY 0x00000FFFU
|
||||
|
||||
#define PHY_READ_TO 0x0000FFFFU
|
||||
#define PHY_WRITE_TO 0x0000FFFFU
|
||||
|
||||
/* Section 3: Common PHY Registers */
|
||||
|
||||
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
|
||||
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
|
||||
|
||||
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
|
||||
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
|
||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
|
||||
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
|
||||
|
||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
|
||||
|
||||
/* Section 4: Extended PHY Registers */
|
||||
|
||||
#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
|
||||
#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
|
||||
#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
|
||||
|
||||
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
|
||||
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
|
||||
|
||||
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
|
||||
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
|
||||
|
||||
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
|
||||
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
|
||||
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver
|
||||
* Deactivated: CRC code cleaned from driver
|
||||
*/
|
||||
|
||||
#define USE_SPI_CRC 1U
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_can.h"
|
||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
|
||||
#include "Legacy/stm32f1xx_hal_can_legacy.h"
|
||||
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCCARD_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_pccard.h"
|
||||
#endif /* HAL_PCCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MMC_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_mmc.h"
|
||||
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_CONF_H */
|
||||
|
||||
|
||||
|
||||
181
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_crc.h
Normal file
181
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_crc.h
Normal file
@@ -0,0 +1,181 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_CRC_H
|
||||
#define STM32F1xx_HAL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Types CRC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
|
||||
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
|
||||
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
|
||||
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
|
||||
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
|
||||
} HAL_CRC_StateTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief CRC Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CRC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRC Locking object */
|
||||
|
||||
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
|
||||
|
||||
} CRC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Macros CRC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRC handle state.
|
||||
* @param __HANDLE__ CRC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Reset CRC Data Register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
|
||||
|
||||
/**
|
||||
* @brief Store data in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __VALUE__ Value to be stored in the ID register
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
|
||||
|
||||
/**
|
||||
* @brief Return the data stored in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval Value of the ID register
|
||||
*/
|
||||
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Macros CRC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_CRC_H */
|
||||
457
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dac.h
Normal file
457
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dac.h
Normal file
@@ -0,0 +1,457 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_dac.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DAC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_DAC_H
|
||||
#define STM32F1xx_HAL_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
#if defined(DAC)
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Types DAC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
|
||||
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
|
||||
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
|
||||
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
|
||||
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
|
||||
|
||||
} HAL_DAC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __DAC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
{
|
||||
DAC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DAC locking object */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DAC Error code */
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
|
||||
void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
|
||||
|
||||
void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
} DAC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC Configuration regular Channel structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
|
||||
} DAC_ChannelConfTypeDef;
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL DAC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
|
||||
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
|
||||
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
|
||||
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
|
||||
|
||||
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
|
||||
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
|
||||
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
|
||||
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
|
||||
|
||||
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
|
||||
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
|
||||
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
|
||||
} HAL_DAC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DAC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants DAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Error_Code DAC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
|
||||
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
|
||||
#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer DAC output buffer
|
||||
* @{
|
||||
*/
|
||||
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
|
||||
#define DAC_OUTPUTBUFFER_DISABLE (DAC_CR_BOFF1)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection DAC Channel selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_CHANNEL_1 0x00000000U
|
||||
|
||||
#define DAC_CHANNEL_2 0x00000010U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment DAC data alignment
|
||||
* @{
|
||||
*/
|
||||
#define DAC_ALIGN_12B_R 0x00000000U
|
||||
#define DAC_ALIGN_12B_L 0x00000004U
|
||||
#define DAC_ALIGN_8B_R 0x00000008U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition DAC flags definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
|
||||
|
||||
#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_IT_definition DAC IT definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
|
||||
|
||||
#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Macros DAC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DAC handle state.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the DAC channel.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __DAC_Channel__ specifies the DAC channel
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
|
||||
|
||||
/** @brief Disable the DAC channel.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __DAC_Channel__ specifies the DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
|
||||
|
||||
/** @brief Set DHR12R1 alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
|
||||
|
||||
|
||||
/** @brief Set DHR12R2 alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
|
||||
|
||||
|
||||
/** @brief Set DHR12RD alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Enable the DAC interrupt.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the DAC interrupt.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified DAC interrupt source is enabled or not.
|
||||
* @param __HANDLE__ DAC handle
|
||||
* @param __INTERRUPT__ DAC interrupt source to check
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval State of interruption (SET or RESET)
|
||||
*/
|
||||
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Get the selected DAC's flag status.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __FLAG__ specifies the DAC flag to get.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
|
||||
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the DAC's flag.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __FLAG__ specifies the DAC flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
|
||||
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
||||
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
||||
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
||||
((ALIGN) == DAC_ALIGN_12B_L) || \
|
||||
((ALIGN) == DAC_ALIGN_8B_R))
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DAC HAL Extended module */
|
||||
#include "stm32f1xx_hal_dac_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
|
||||
uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
|
||||
|
||||
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/* DAC callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
|
||||
pDAC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
|
||||
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions DAC Private Functions
|
||||
* @{
|
||||
*/
|
||||
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32F1xx_HAL_DAC_H */
|
||||
276
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dac_ex.h
Normal file
276
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dac_ex.h
Normal file
@@ -0,0 +1,276 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_dac_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DAC HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_DAC_EX_H
|
||||
#define STM32F1xx_HAL_DAC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
#if defined(DAC)
|
||||
|
||||
/** @addtogroup DACEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
|
||||
* @{
|
||||
*/
|
||||
#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_trigger_selection DAC trigger selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||
/* For STM32F10x high-density and XL-density devices: TIM8 */
|
||||
#define DAC_TRIGGER_T8_TRGO ((uint32_t) DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
|
||||
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
|
||||
|
||||
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||
/* For STM32F10x connectivity line devices and STM32F100x devices: TIM3 */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t) DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
#endif /* STM32F100xB || STM32F100xE || STM32F105xC || STM32F107xC */
|
||||
|
||||
/* Availability of trigger from TIM5 and TIM15: */
|
||||
/* - For STM32F10x value line devices STM32F100xB: */
|
||||
/* trigger from TIM15 is available, TIM5 not available. */
|
||||
/* - For STM32F10x value line devices STM32F100xE: */
|
||||
/* trigger from TIM15 and TIM5 are both available, */
|
||||
/* selection depends on remap (with TIM5 as default configuration). */
|
||||
/* - Other STM32F1 devices: */
|
||||
/* trigger from TIM5 is available, TIM15 not available. */
|
||||
#if defined (STM32F100xB)
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
|
||||
#else
|
||||
|
||||
#define DAC_TRIGGER_T5_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
|
||||
#if defined (STM32F100xE)
|
||||
/*!< DAC trigger availability depending on STM32F1 devices:
|
||||
For STM32F100x high-density value line devices, the TIM15 TRGO event can be selected
|
||||
as replacement of TIM5 TRGO if the MISC_REMAP bit in the AFIO_MAPR2 register is set.
|
||||
Refer to macro "__HAL_AFIO_REMAP_MISC_ENABLE()/__HAL_AFIO_REMAP_MISC_DISABLE()".
|
||||
Otherwise, TIM5 TRGO is used and TIM15 TRGO is not used (default case).
|
||||
For more details please refer to the AFIO section. */
|
||||
#define DAC_TRIGGER_T15_TRGO DAC_TRIGGER_T5_TRGO
|
||||
#endif /* STM32F100xE */
|
||||
|
||||
#endif /* STM32F100xB */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DACEx_Private_Macros DACEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
|
||||
#if defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
#endif /* STM32F100xE || STM32F105xC || STM32F107xC */
|
||||
#if defined (STM32F100xB)
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
#endif /* STM32F100xB */
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Extended features functions ***********************************************/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||
uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
|
||||
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
|
||||
/* are called by HAL_DAC_Start_DMA */
|
||||
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_DAC_EX_H */
|
||||
2141
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_eth.h
Normal file
2141
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_eth.h
Normal file
File diff suppressed because it is too large
Load Diff
324
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_hcd.h
Normal file
324
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_hcd.h
Normal file
@@ -0,0 +1,324 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_hcd.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of HCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_HCD_H
|
||||
#define STM32F1xx_HAL_HCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_ll_usb.h"
|
||||
|
||||
#if defined (USB_OTG_FS)
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HCD HCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Types HCD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HCD_STATE_RESET = 0x00,
|
||||
HAL_HCD_STATE_READY = 0x01,
|
||||
HAL_HCD_STATE_ERROR = 0x02,
|
||||
HAL_HCD_STATE_BUSY = 0x03,
|
||||
HAL_HCD_STATE_TIMEOUT = 0x04
|
||||
} HCD_StateTypeDef;
|
||||
|
||||
typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
|
||||
typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
|
||||
typedef USB_OTG_HCTypeDef HCD_HCTypeDef;
|
||||
typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
|
||||
typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
typedef struct __HCD_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
{
|
||||
HCD_TypeDef *Instance; /*!< Register base address */
|
||||
HCD_InitTypeDef Init; /*!< HCD required parameters */
|
||||
HCD_HCTypeDef hc[16]; /*!< Host channels parameters */
|
||||
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
|
||||
__IO HCD_StateTypeDef State; /*!< HCD communication state */
|
||||
__IO uint32_t ErrorCode; /*!< HCD Error code */
|
||||
void *pData; /*!< Pointer Stack Handler */
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */
|
||||
void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */
|
||||
void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */
|
||||
void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */
|
||||
void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */
|
||||
void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
|
||||
HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */
|
||||
|
||||
void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
} HCD_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Constants HCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Speed HCD Speed
|
||||
* @{
|
||||
*/
|
||||
#define HCD_SPEED_FULL USBH_FSLS_SPEED
|
||||
#define HCD_SPEED_LOW USBH_FSLS_SPEED
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Device_Speed HCD Device Speed
|
||||
* @{
|
||||
*/
|
||||
#define HCD_DEVICE_SPEED_HIGH 0U
|
||||
#define HCD_DEVICE_SPEED_FULL 1U
|
||||
#define HCD_DEVICE_SPEED_LOW 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_PHY_Module HCD PHY Module
|
||||
* @{
|
||||
*/
|
||||
#define HCD_PHY_ULPI 1U
|
||||
#define HCD_PHY_EMBEDDED 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Error_Code_definition HCD Error Code definition
|
||||
* @brief HCD Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Macros HCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \
|
||||
((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
|
||||
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||
|
||||
#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
|
||||
#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
|
||||
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
|
||||
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
|
||||
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup HCD_Exported_Functions HCD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint8_t epnum, uint8_t dev_address,
|
||||
uint8_t speed, uint8_t ep_type, uint16_t mps);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
|
||||
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
|
||||
* @brief HAL USB OTG HCD Callback ID enumeration definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
|
||||
HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
|
||||
HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
|
||||
HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
|
||||
HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
|
||||
|
||||
HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
|
||||
HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
|
||||
|
||||
} HAL_HCD_CallbackIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
|
||||
* @brief HAL USB OTG HCD Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */
|
||||
typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
|
||||
uint8_t epnum,
|
||||
HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
|
||||
HAL_HCD_CallbackIDTypeDef CallbackID,
|
||||
pHCD_CallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
|
||||
HAL_HCD_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
|
||||
pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint8_t direction, uint8_t ep_type,
|
||||
uint8_t token, uint8_t *pbuff,
|
||||
uint16_t length, uint8_t do_ping);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint8_t addr, uint8_t PortNbr);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
|
||||
HCD_URBStateTypeDef urb_state);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd);
|
||||
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
|
||||
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Macros HCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_HCD_H */
|
||||
738
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h
Normal file
738
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h
Normal file
@@ -0,0 +1,738 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_I2C_H
|
||||
#define __STM32F1xx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
||||
* @brief I2C Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockSpeed; /*!< Specifies the clock frequency.
|
||||
This parameter must be set to a value lower than 400kHz */
|
||||
|
||||
uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
|
||||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_addressing_mode */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_dual_addressing_mode */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_general_call_addressing_mode */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_nostretch_mode */
|
||||
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structure definition
|
||||
* @note HAL I2C State value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : Abort (Abort user request on going)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
|
||||
* b4 (not used)
|
||||
* x : Should be set to 0
|
||||
* b3
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)
|
||||
* 1 : Listen (Peripheral in Address Listen Mode)
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (Peripheral busy with some configuration or internal operations)
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
||||
* @brief HAL Mode structure definition
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :\n
|
||||
* b7 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b6\n
|
||||
* 0 : None\n
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
|
||||
* b5\n
|
||||
* 0 : None\n
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
|
||||
* b4\n
|
||||
* 0 : None\n
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)\n
|
||||
* b3-b2-b1-b0 (not used)\n
|
||||
* xxxx : Should be set to 0000
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||
|
||||
} HAL_I2C_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
||||
* @brief I2C Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */
|
||||
#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
|
||||
#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */
|
||||
#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */
|
||||
#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
||||
* @brief I2C handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __I2C_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< I2C transfer options */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
|
||||
context for internal usage */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||
|
||||
__IO uint32_t Devaddress; /*!< I2C Target device address */
|
||||
|
||||
__IO uint32_t Memaddress; /*!< I2C Target memory address */
|
||||
|
||||
__IO uint32_t MemaddSize; /*!< I2C Target memory address size */
|
||||
|
||||
__IO uint32_t EventCount; /*!< I2C Event counter */
|
||||
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
|
||||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
|
||||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
|
||||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
|
||||
|
||||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
|
||||
|
||||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
} I2C_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL I2C Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
|
||||
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
|
||||
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
|
||||
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
|
||||
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
|
||||
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
|
||||
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
|
||||
|
||||
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
|
||||
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2C_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2C Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
|
||||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUTYCYCLE_2 0x00000000U
|
||||
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_addressing_mode I2C addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT 0x00004000U
|
||||
#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE 0x00000000U
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE 0x00000000U
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_nostretch_mode I2C nostretch mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE 0x00000000U
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT 0x00000001U
|
||||
#define I2C_MEMADD_SIZE_16BIT 0x00000010U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_RECEIVE 0x00000000U
|
||||
#define I2C_DIRECTION_TRANSMIT 0x00000001U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FIRST_FRAME 0x00000001U
|
||||
#define I2C_FIRST_AND_NEXT_FRAME 0x00000002U
|
||||
#define I2C_NEXT_FRAME 0x00000004U
|
||||
#define I2C_FIRST_AND_LAST_FRAME 0x00000008U
|
||||
#define I2C_LAST_FRAME_NO_STOP 0x00000010U
|
||||
#define I2C_LAST_FRAME 0x00000020U
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition in all use cases (direction change or not)
|
||||
*/
|
||||
#define I2C_OTHER_FRAME (0x00AA0000U)
|
||||
#define I2C_OTHER_AND_LAST_FRAME (0xAA000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||
* @brief I2C Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_BUF I2C_CR2_ITBUFEN
|
||||
#define I2C_IT_EVT I2C_CR2_ITEVTEN
|
||||
#define I2C_IT_ERR I2C_CR2_ITERREN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_OVR 0x00010800U
|
||||
#define I2C_FLAG_AF 0x00010400U
|
||||
#define I2C_FLAG_ARLO 0x00010200U
|
||||
#define I2C_FLAG_BERR 0x00010100U
|
||||
#define I2C_FLAG_TXE 0x00010080U
|
||||
#define I2C_FLAG_RXNE 0x00010040U
|
||||
#define I2C_FLAG_STOPF 0x00010010U
|
||||
#define I2C_FLAG_ADD10 0x00010008U
|
||||
#define I2C_FLAG_BTF 0x00010004U
|
||||
#define I2C_FLAG_ADDR 0x00010002U
|
||||
#define I2C_FLAG_SB 0x00010001U
|
||||
#define I2C_FLAG_DUALF 0x00100080U
|
||||
#define I2C_FLAG_GENCALL 0x00100010U
|
||||
#define I2C_FLAG_TRA 0x00100004U
|
||||
#define I2C_FLAG_BUSY 0x00100002U
|
||||
#define I2C_FLAG_MSL 0x00100001U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2C handle state.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/** @brief Enable or disable the specified I2C interrupts.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_IT_BUF: Buffer interrupt enable
|
||||
* @arg I2C_IT_EVT: Event interrupt enable
|
||||
* @arg I2C_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
|
||||
|
||||
/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_IT_BUF: Buffer interrupt enable
|
||||
* @arg I2C_IT_EVT: Event interrupt enable
|
||||
* @arg I2C_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2C_FLAG_OVR: Overrun/Underrun flag
|
||||
* @arg I2C_FLAG_AF: Acknowledge failure flag
|
||||
* @arg I2C_FLAG_ARLO: Arbitration lost flag
|
||||
* @arg I2C_FLAG_BERR: Bus error flag
|
||||
* @arg I2C_FLAG_TXE: Data register empty flag
|
||||
* @arg I2C_FLAG_RXNE: Data register not empty flag
|
||||
* @arg I2C_FLAG_STOPF: Stop detection flag
|
||||
* @arg I2C_FLAG_ADD10: 10-bit header sent flag
|
||||
* @arg I2C_FLAG_BTF: Byte transfer finished flag
|
||||
* @arg I2C_FLAG_ADDR: Address sent flag
|
||||
* Address matched flag
|
||||
* @arg I2C_FLAG_SB: Start bit flag
|
||||
* @arg I2C_FLAG_DUALF: Dual flag
|
||||
* @arg I2C_FLAG_GENCALL: General call header flag
|
||||
* @arg I2C_FLAG_TRA: Transmitter/Receiver flag
|
||||
* @arg I2C_FLAG_BUSY: Bus busy flag
|
||||
* @arg I2C_FLAG_MSL: Master/Slave flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \
|
||||
(((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \
|
||||
(((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET))
|
||||
|
||||
/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
|
||||
* @arg I2C_FLAG_AF: Acknowledge failure flag
|
||||
* @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
|
||||
* @arg I2C_FLAG_BERR: Bus error flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
|
||||
|
||||
/** @brief Clears the I2C ADDR pending flag.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
tmpreg = (__HANDLE__)->Instance->SR1; \
|
||||
tmpreg = (__HANDLE__)->Instance->SR2; \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Clears the I2C STOPF pending flag.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
tmpreg = (__HANDLE__)->Instance->SR1; \
|
||||
SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
|
||||
|
||||
/** @brief Disable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions******************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_MASK 0x0000FFFFU
|
||||
#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz */
|
||||
#define I2C_MIN_PCLK_FREQ_FAST 4000000U /*!< 4 MHz */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Macros I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
|
||||
#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
|
||||
#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
|
||||
#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
|
||||
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
|
||||
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
|
||||
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
|
||||
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
|
||||
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
|
||||
|
||||
#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0)))
|
||||
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
|
||||
|
||||
#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
|
||||
#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0)))
|
||||
#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1))))
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
|
||||
|
||||
/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
|
||||
((CYCLE) == I2C_DUTYCYCLE_16_9))
|
||||
#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLE))
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U)
|
||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
|
||||
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
|
||||
|
||||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
|
||||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F1xx_HAL_I2C_H */
|
||||
|
||||
554
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2s.h
Normal file
554
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2s.h
Normal file
@@ -0,0 +1,554 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_i2s.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_I2S_H
|
||||
#define STM32F1xx_HAL_I2S_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
#if defined(SPI_I2S_SUPPORT)
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Types I2S Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
|
||||
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Standard */
|
||||
|
||||
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
} I2S_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
|
||||
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
|
||||
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
|
||||
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
|
||||
} HAL_I2S_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2S handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __I2S_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
{
|
||||
SPI_TypeDef *Instance; /*!< I2S registers base address */
|
||||
|
||||
I2S_InitTypeDef Init; /*!< I2S communication parameters */
|
||||
|
||||
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
|
||||
|
||||
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
|
||||
|
||||
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
|
||||
|
||||
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
|
||||
(This field is initialized at the
|
||||
same value as transfer size at the
|
||||
beginning of the transfer and
|
||||
decremented when a sample is received
|
||||
NbSamplesReceived = RxBufferSize-RxBufferCount) */
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
|
||||
|
||||
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
|
||||
|
||||
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2S Error code
|
||||
This parameter can be a value of @ref I2S_Error */
|
||||
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
|
||||
void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
|
||||
void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
|
||||
void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
|
||||
void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
|
||||
void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
} I2S_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
* @brief HAL I2S Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */
|
||||
HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */
|
||||
HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */
|
||||
HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */
|
||||
HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */
|
||||
HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */
|
||||
HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2S_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2S Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
|
||||
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Constants I2S Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup I2S_Error I2S Error
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
|
||||
#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
|
||||
#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
|
||||
#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
|
||||
#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Mode I2S Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MODE_SLAVE_TX (0x00000000U)
|
||||
#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
|
||||
#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
|
||||
#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Standard I2S Standard
|
||||
* @{
|
||||
*/
|
||||
#define I2S_STANDARD_PHILIPS (0x00000000U)
|
||||
#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
|
||||
#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
|
||||
#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
|
||||
#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_Format I2S Data Format
|
||||
* @{
|
||||
*/
|
||||
#define I2S_DATAFORMAT_16B (0x00000000U)
|
||||
#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
|
||||
#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
|
||||
#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MCLK_Output I2S MCLK Output
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
|
||||
#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
|
||||
* @{
|
||||
*/
|
||||
#define I2S_AUDIOFREQ_192K (192000U)
|
||||
#define I2S_AUDIOFREQ_96K (96000U)
|
||||
#define I2S_AUDIOFREQ_48K (48000U)
|
||||
#define I2S_AUDIOFREQ_44K (44100U)
|
||||
#define I2S_AUDIOFREQ_32K (32000U)
|
||||
#define I2S_AUDIOFREQ_22K (22050U)
|
||||
#define I2S_AUDIOFREQ_16K (16000U)
|
||||
#define I2S_AUDIOFREQ_11K (11025U)
|
||||
#define I2S_AUDIOFREQ_8K (8000U)
|
||||
#define I2S_AUDIOFREQ_DEFAULT (2U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CPOL_LOW (0x00000000U)
|
||||
#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_IT_TXE SPI_CR2_TXEIE
|
||||
#define I2S_IT_RXNE SPI_CR2_RXNEIE
|
||||
#define I2S_IT_ERR SPI_CR2_ERRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Flags_Definition I2S Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FLAG_TXE SPI_SR_TXE
|
||||
#define I2S_FLAG_RXNE SPI_SR_RXNE
|
||||
|
||||
#define I2S_FLAG_UDR SPI_SR_UDR
|
||||
#define I2S_FLAG_OVR SPI_SR_OVR
|
||||
#define I2S_FLAG_FRE SPI_SR_FRE
|
||||
|
||||
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
|
||||
#define I2S_FLAG_BSY SPI_SR_BSY
|
||||
|
||||
#define I2S_FLAG_MASK (SPI_SR_RXNE\
|
||||
| SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_CHSIDE | SPI_SR_BSY)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_macros I2S Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2S handle state
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2S_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
|
||||
|
||||
/** @brief Disable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
|
||||
|
||||
/** @brief Enable the specified I2S interrupts.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
|
||||
|
||||
/** @brief Disable the specified I2S interrupts.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2S flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg I2S_FLAG_UDR: Underrun flag
|
||||
* @arg I2S_FLAG_OVR: Overrun flag
|
||||
* @arg I2S_FLAG_FRE: Frame error flag
|
||||
* @arg I2S_FLAG_CHSIDE: Channel Side flag
|
||||
* @arg I2S_FLAG_BSY: Busy flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the I2S OVR pending flag.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
|
||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_ovr); \
|
||||
}while(0U)
|
||||
/** @brief Clears the I2S UDR pending flag.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
|
||||
__IO uint32_t tmpreg_udr = 0x00U;\
|
||||
tmpreg_udr = ((__HANDLE__)->Instance->SR);\
|
||||
UNUSED(tmpreg_udr); \
|
||||
}while(0U)
|
||||
/** @brief Flush the I2S DR Register.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
|
||||
__IO uint32_t tmpreg_dr = 0x00U;\
|
||||
tmpreg_dr = ((__HANDLE__)->Instance->DR);\
|
||||
UNUSED(tmpreg_dr); \
|
||||
}while(0U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2S_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
|
||||
pI2S_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
|
||||
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
|
||||
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Macros I2S Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of I2S SR register.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg I2S_FLAG_UDR: Underrun error flag
|
||||
* @arg I2S_FLAG_OVR: Overrun flag
|
||||
* @arg I2S_FLAG_CHSIDE: Channel side flag
|
||||
* @arg I2S_FLAG_BSY: Busy flag
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
|
||||
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __CR2__ copy of I2S CR2 register.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks if I2S Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the I2S Mode.
|
||||
* This parameter can be a value of @ref I2S_Mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
|
||||
((__MODE__) == I2S_MODE_SLAVE_RX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_TX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_RX))
|
||||
|
||||
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
|
||||
((__STANDARD__) == I2S_STANDARD_MSB) || \
|
||||
((__STANDARD__) == I2S_STANDARD_LSB) || \
|
||||
((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
|
||||
((__STANDARD__) == I2S_STANDARD_PCM_LONG))
|
||||
|
||||
#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_24B) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_32B))
|
||||
|
||||
#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
|
||||
((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
|
||||
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
|
||||
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
|
||||
|
||||
/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
|
||||
* @param __CPOL__ specifies the I2S serial clock steady state.
|
||||
* This parameter can be a value of @ref I2S_Clock_Polarity
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
|
||||
((__CPOL__) == I2S_CPOL_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SPI_I2S_SUPPORT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_I2S_H */
|
||||
|
||||
670
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_irda.h
Normal file
670
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_irda.h
Normal file
@@ -0,0 +1,670 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_irda.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IRDA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_IRDA_H
|
||||
#define __STM32F1xx_HAL_IRDA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Types IRDA Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief IRDA Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (16 * (hirda->Init.BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref IRDA_Word_Length */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref IRDA_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref IRDA_Mode */
|
||||
|
||||
uint8_t Prescaler; /*!< Specifies the Prescaler value to be programmed
|
||||
in the IrDA low-power Baud Register, for defining pulse width on which
|
||||
burst acceptance/rejection will be decided. This value is used as divisor
|
||||
of system clock to achieve required pulse width. */
|
||||
|
||||
uint32_t IrDAMode; /*!< Specifies the IrDA mode
|
||||
This parameter can be a value of @ref IRDA_Low_Power */
|
||||
} IRDA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA State structures definition
|
||||
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
|
||||
* - gState contains IRDA state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : (Not Used)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 IP initialisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized. HAL IRDA Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 IP initialisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between gState and RxState values */
|
||||
HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
|
||||
Value is allowed for gState only */
|
||||
} HAL_IRDA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __IRDA_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
{
|
||||
USART_TypeDef *Instance; /*!< USART registers base address */
|
||||
|
||||
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
|
||||
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< IRDA Error code */
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
|
||||
|
||||
void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
|
||||
|
||||
void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
|
||||
|
||||
void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
|
||||
|
||||
void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
|
||||
|
||||
void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
|
||||
|
||||
void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
|
||||
|
||||
void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
|
||||
|
||||
|
||||
void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
} IRDA_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL IRDA Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
|
||||
HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
|
||||
HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
|
||||
HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
|
||||
HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
|
||||
HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
|
||||
HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
|
||||
HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
|
||||
|
||||
HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
|
||||
HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
|
||||
|
||||
} HAL_IRDA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA Callback pointer definition
|
||||
*/
|
||||
typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
|
||||
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Constants IRDA Exported constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup IRDA_Error_Code IRDA Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_IRDA_ERROR_PE 0x00000001U /*!< Parity error */
|
||||
#define HAL_IRDA_ERROR_NE 0x00000002U /*!< Noise error */
|
||||
#define HAL_IRDA_ERROR_FE 0x00000004U /*!< Frame error */
|
||||
#define HAL_IRDA_ERROR_ORE 0x00000008U /*!< Overrun error */
|
||||
#define HAL_IRDA_ERROR_DMA 0x00000010U /*!< DMA transfer error */
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Word_Length IRDA Word Length
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_WORDLENGTH_8B 0x00000000U
|
||||
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Parity IRDA Parity
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PARITY_NONE 0x00000000U
|
||||
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
|
||||
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Mode IRDA Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
|
||||
#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
|
||||
#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Low_Power IRDA Low Power
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
|
||||
#define IRDA_POWERMODE_NORMAL 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Flags IRDA Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the SR register
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_FLAG_TXE ((uint32_t)USART_SR_TXE)
|
||||
#define IRDA_FLAG_TC ((uint32_t)USART_SR_TC)
|
||||
#define IRDA_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
|
||||
#define IRDA_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
|
||||
#define IRDA_FLAG_ORE ((uint32_t)USART_SR_ORE)
|
||||
#define IRDA_FLAG_NE ((uint32_t)USART_SR_NE)
|
||||
#define IRDA_FLAG_FE ((uint32_t)USART_SR_FE)
|
||||
#define IRDA_FLAG_PE ((uint32_t)USART_SR_PE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
|
||||
* Elements values convention: 0xY000XXXX
|
||||
* - XXXX : Interrupt mask in the XX register
|
||||
* - Y : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
|
||||
#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
|
||||
#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
|
||||
#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
|
||||
#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
|
||||
|
||||
#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
|
||||
|
||||
#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
|
||||
#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset IRDA handle gstate & RxState
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
||||
} while(0U)
|
||||
#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Flush the IRDA DR register
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
|
||||
|
||||
/** @brief Check whether the specified IRDA flag is set or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_FLAG_TXE: Transmit data register empty flag
|
||||
* @arg IRDA_FLAG_TC: Transmission Complete flag
|
||||
* @arg IRDA_FLAG_RXNE: Receive data register not empty flag
|
||||
* @arg IRDA_FLAG_IDLE: Idle Line detection flag
|
||||
* @arg IRDA_FLAG_ORE: OverRun Error flag
|
||||
* @arg IRDA_FLAG_NE: Noise Error flag
|
||||
* @arg IRDA_FLAG_FE: Framing Error flag
|
||||
* @arg IRDA_FLAG_PE: Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the specified IRDA pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg IRDA_FLAG_TC: Transmission Complete flag.
|
||||
* @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
|
||||
*
|
||||
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
|
||||
* error) and IDLE (Idle line detected) flags are cleared by software
|
||||
* sequence: a read operation to USART_SR register followed by a read
|
||||
* operation to USART_DR register.
|
||||
* @note RXNE flag can be also cleared by a read to the USART_DR register.
|
||||
* @note TC flag can be also cleared by software sequence: a read operation to
|
||||
* USART_SR register followed by a write operation to USART_DR register.
|
||||
* @note TXE flag is cleared only by a write to the USART_DR register.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
||||
|
||||
/** @brief Clear the IRDA PE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
tmpreg = (__HANDLE__)->Instance->SR; \
|
||||
tmpreg = (__HANDLE__)->Instance->DR; \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Clear the IRDA FE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the IRDA NE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the IRDA ORE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the IRDA IDLE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Enable the specified IRDA interrupt.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
|
||||
(((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
|
||||
/** @brief Disable the specified IRDA interrupt.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
|
||||
(((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @param __IT__ specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_ERR: Error interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == IRDA_CR2_REG_INDEX)? \
|
||||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
|
||||
|
||||
/** @brief Enable UART/USART associated to IRDA Handle
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
|
||||
|
||||
/** @brief Disable UART/USART associated to IRDA Handle
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup IRDA_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions **************************************************/
|
||||
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
|
||||
uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Private_Constants IRDA Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief IRDA interruptions flag mask
|
||||
*
|
||||
*/
|
||||
#define IRDA_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
|
||||
USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
|
||||
|
||||
#define IRDA_CR1_REG_INDEX 1U
|
||||
#define IRDA_CR2_REG_INDEX 2U
|
||||
#define IRDA_CR3_REG_INDEX 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Private_Macros IRDA Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
|
||||
((LENGTH) == IRDA_WORDLENGTH_9B))
|
||||
|
||||
#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
|
||||
((PARITY) == IRDA_PARITY_EVEN) || \
|
||||
((PARITY) == IRDA_PARITY_ODD))
|
||||
|
||||
#define IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
|
||||
|
||||
#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
|
||||
((MODE) == IRDA_POWERMODE_NORMAL))
|
||||
|
||||
#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
|
||||
|
||||
#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
|
||||
|
||||
#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
|
||||
|
||||
#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) ((((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
|
||||
|
||||
/* UART BRR = mantissa + overflow + fraction
|
||||
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
|
||||
#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
|
||||
(IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
|
||||
(IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Private_Functions IRDA Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_IRDA_H */
|
||||
|
||||
747
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_mmc.h
Normal file
747
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_mmc.h
Normal file
@@ -0,0 +1,747 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_mmc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of MMC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_MMC_H
|
||||
#define STM32F1xx_HAL_MMC_H
|
||||
|
||||
#if defined(SDIO)
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_ll_sdmmc.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup MMC_Exported_Types MMC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */
|
||||
HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */
|
||||
HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */
|
||||
HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
|
||||
HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
|
||||
HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
|
||||
HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfer State */
|
||||
HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
|
||||
}HAL_MMC_StateTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef uint32_t HAL_MMC_CardStateTypeDef;
|
||||
|
||||
#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */
|
||||
#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
|
||||
#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
|
||||
#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
|
||||
#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
|
||||
#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
|
||||
#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
|
||||
#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
|
||||
#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#define MMC_InitTypeDef SDIO_InitTypeDef
|
||||
#define MMC_TypeDef SDIO_TypeDef
|
||||
|
||||
/**
|
||||
* @brief MMC Card Information Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CardType; /*!< Specifies the card Type */
|
||||
|
||||
uint32_t Class; /*!< Specifies the class of the card class */
|
||||
|
||||
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
|
||||
|
||||
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
|
||||
|
||||
uint32_t BlockSize; /*!< Specifies one block size in bytes */
|
||||
|
||||
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
|
||||
|
||||
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
|
||||
|
||||
}HAL_MMC_CardInfoTypeDef;
|
||||
|
||||
/**
|
||||
* @brief MMC handle Structure definition
|
||||
*/
|
||||
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
|
||||
typedef struct __MMC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
|
||||
{
|
||||
MMC_TypeDef *Instance; /*!< MMC registers base address */
|
||||
|
||||
MMC_InitTypeDef Init; /*!< MMC required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< MMC locking object */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
|
||||
|
||||
uint32_t TxXferSize; /*!< MMC Tx Transfer size */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
|
||||
|
||||
uint32_t RxXferSize; /*!< MMC Rx Transfer size */
|
||||
|
||||
__IO uint32_t Context; /*!< MMC transfer context */
|
||||
|
||||
__IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< MMC Card Error codes */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
|
||||
|
||||
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
|
||||
|
||||
uint32_t CSD[4U]; /*!< MMC card specific data table */
|
||||
|
||||
uint32_t CID[4U]; /*!< MMC card identification number table */
|
||||
|
||||
uint32_t Ext_CSD[128];
|
||||
|
||||
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
|
||||
void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
|
||||
void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
|
||||
void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
|
||||
void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
|
||||
|
||||
void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc);
|
||||
void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc);
|
||||
#endif
|
||||
}MMC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t CSDStruct; /*!< CSD structure */
|
||||
__IO uint8_t SysSpecVersion; /*!< System specification version */
|
||||
__IO uint8_t Reserved1; /*!< Reserved */
|
||||
__IO uint8_t TAAC; /*!< Data read access time 1 */
|
||||
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
|
||||
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
|
||||
__IO uint16_t CardComdClasses; /*!< Card command classes */
|
||||
__IO uint8_t RdBlockLen; /*!< Max. read data block length */
|
||||
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
|
||||
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
|
||||
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
|
||||
__IO uint8_t DSRImpl; /*!< DSR implemented */
|
||||
__IO uint8_t Reserved2; /*!< Reserved */
|
||||
__IO uint32_t DeviceSize; /*!< Device Size */
|
||||
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
|
||||
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
|
||||
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
|
||||
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
|
||||
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
|
||||
__IO uint8_t EraseGrSize; /*!< Erase group size */
|
||||
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
|
||||
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
|
||||
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
|
||||
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
|
||||
__IO uint8_t WrSpeedFact; /*!< Write speed factor */
|
||||
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
|
||||
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
|
||||
__IO uint8_t Reserved3; /*!< Reserved */
|
||||
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
|
||||
__IO uint8_t FileFormatGroup; /*!< File format group */
|
||||
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
|
||||
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
|
||||
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
|
||||
__IO uint8_t FileFormat; /*!< File format */
|
||||
__IO uint8_t ECC; /*!< ECC code */
|
||||
__IO uint8_t CSD_CRC; /*!< CSD CRC */
|
||||
__IO uint8_t Reserved4; /*!< Always 1 */
|
||||
|
||||
}HAL_MMC_CardCSDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
|
||||
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
|
||||
__IO uint32_t ProdName1; /*!< Product Name part1 */
|
||||
__IO uint8_t ProdName2; /*!< Product Name part2 */
|
||||
__IO uint8_t ProdRev; /*!< Product Revision */
|
||||
__IO uint32_t ProdSN; /*!< Product Serial Number */
|
||||
__IO uint8_t Reserved1; /*!< Reserved1 */
|
||||
__IO uint16_t ManufactDate; /*!< Manufacturing Date */
|
||||
__IO uint8_t CID_CRC; /*!< CID CRC */
|
||||
__IO uint8_t Reserved2; /*!< Always 1 */
|
||||
|
||||
}HAL_MMC_CardCIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
|
||||
/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */
|
||||
HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */
|
||||
HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */
|
||||
HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */
|
||||
|
||||
HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
|
||||
HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
|
||||
}HAL_MMC_CallbackIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup MMC_Exported_Constants Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define MMC_BLOCKSIZE 512U /*!< Block size is 512 bytes */
|
||||
|
||||
/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
|
||||
#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
|
||||
#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
|
||||
#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
|
||||
#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
|
||||
#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
|
||||
#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
|
||||
#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
|
||||
#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
|
||||
number of transferred bytes does not match the block length */
|
||||
#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
|
||||
#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
|
||||
#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
|
||||
#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
|
||||
command or if there was an attempt to access a locked card */
|
||||
#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
|
||||
#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
|
||||
#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
|
||||
#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
|
||||
#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
|
||||
#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
|
||||
#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
|
||||
#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
|
||||
#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
|
||||
#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
|
||||
#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
|
||||
of erase sequence command was received */
|
||||
#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
|
||||
#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
|
||||
#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
|
||||
#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
|
||||
#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
|
||||
#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
|
||||
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
|
||||
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
|
||||
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
|
||||
|
||||
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
|
||||
* @{
|
||||
*/
|
||||
#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
|
||||
#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
|
||||
#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
|
||||
#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
|
||||
#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
|
||||
#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
|
||||
#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief
|
||||
*/
|
||||
#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */
|
||||
#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */
|
||||
#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */
|
||||
#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */
|
||||
#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */
|
||||
#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */
|
||||
#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
|
||||
* @{
|
||||
*/
|
||||
#define MMC_LOW_CAPACITY_CARD 0x00000000U /*!< MMC Card Capacity <=2Gbytes */
|
||||
#define MMC_HIGH_CAPACITY_CARD 0x00000001U /*!< MMC Card Capacity >2Gbytes and <2Tbytes */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup MMC_Exported_macros MMC Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset MMC handle state.
|
||||
* @param __HANDLE__ : MMC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_MMC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable the MMC device.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Disable the MMC device.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Enable the SDMMC DMA transfer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Disable the SDMMC DMA transfer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Enable the MMC device interrupt.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the MMC device interrupt.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified MMC flag is set or not.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
|
||||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
|
||||
* @arg SDIO_FLAG_TXACT: Data transmit in progress
|
||||
* @arg SDIO_FLAG_RXACT: Data receive in progress
|
||||
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
||||
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
|
||||
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
|
||||
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
|
||||
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
|
||||
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
|
||||
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
|
||||
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
|
||||
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @retval The new state of MMC FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the MMC's pending flags.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
|
||||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified MMC interrupt has occurred or not.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval The new state of MMC IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the MMC's interrupt pending bits.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup MMC_Exported_Functions MMC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
|
||||
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
|
||||
HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
|
||||
/* Non-Blocking mode: IT */
|
||||
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
|
||||
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
|
||||
|
||||
/* Callback in non blocking modes (DMA) */
|
||||
void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
|
||||
|
||||
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
|
||||
/* MMC callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
|
||||
* @{
|
||||
*/
|
||||
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
|
||||
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
|
||||
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
|
||||
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
|
||||
HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
|
||||
uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
|
||||
HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Types MMC Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Defines MMC Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Variables MMC Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Constants MMC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Macros MMC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Functions MMC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SDIO */
|
||||
|
||||
#endif /* STM32F1xx_HAL_MMC_H */
|
||||
379
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_nand.h
Normal file
379
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_nand.h
Normal file
@@ -0,0 +1,379 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_nand.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of NAND HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_NAND_H
|
||||
#define STM32F1xx_HAL_NAND_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(FSMC_BANK3)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_ll_fsmc.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup NAND_Exported_Types NAND Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL NAND State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
|
||||
HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
|
||||
HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
|
||||
HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
|
||||
} HAL_NAND_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND Memory electronic signature Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*<! NAND memory electronic signature maker and device IDs */
|
||||
|
||||
uint8_t Maker_Id;
|
||||
|
||||
uint8_t Device_Id;
|
||||
|
||||
uint8_t Third_Id;
|
||||
|
||||
uint8_t Fourth_Id;
|
||||
} NAND_IDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND Memory address Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t Page; /*!< NAND memory Page address */
|
||||
|
||||
uint16_t Plane; /*!< NAND memory Zone address */
|
||||
|
||||
uint16_t Block; /*!< NAND memory Block address */
|
||||
|
||||
} NAND_AddressTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND Memory info Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
|
||||
for 8 bits addressing or words for 16 bits addressing */
|
||||
|
||||
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
|
||||
for 8 bits addressing or words for 16 bits addressing */
|
||||
|
||||
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
|
||||
|
||||
uint32_t BlockNbr; /*!< NAND memory number of total blocks */
|
||||
|
||||
uint32_t PlaneNbr; /*!< NAND memory number of planes */
|
||||
|
||||
uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
|
||||
|
||||
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
|
||||
parameter is mandatory for some NAND parts after the read
|
||||
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
|
||||
This parameter could be ENABLE or DISABLE
|
||||
Please check the Read Mode sequence in the NAND device datasheet */
|
||||
} NAND_DeviceConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __NAND_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
|
||||
{
|
||||
FSMC_NAND_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< NAND locking object */
|
||||
|
||||
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
|
||||
|
||||
NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */
|
||||
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */
|
||||
void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */
|
||||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
|
||||
} NAND_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL NAND Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
|
||||
HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
|
||||
HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
|
||||
} HAL_NAND_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL NAND Callback pointer definition
|
||||
*/
|
||||
typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
|
||||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup NAND_Exported_Macros NAND Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset NAND handle state
|
||||
* @param __HANDLE__ specifies the NAND handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_NAND_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
|
||||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup NAND_Exported_Functions NAND Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
|
||||
FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
|
||||
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
|
||||
|
||||
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint8_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint8_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint16_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint16_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
|
||||
|
||||
uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
/* NAND callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
|
||||
pNAND_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
|
||||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* NAND Control functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
|
||||
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
|
||||
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* NAND State functions *******************************************************/
|
||||
HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
|
||||
uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup NAND_Private_Constants NAND Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define NAND_DEVICE1 0x70000000UL
|
||||
#define NAND_DEVICE2 0x80000000UL
|
||||
#define NAND_WRITE_TIMEOUT 0x01000000UL
|
||||
|
||||
#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
|
||||
#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
|
||||
|
||||
#define NAND_CMD_AREA_A ((uint8_t)0x00)
|
||||
#define NAND_CMD_AREA_B ((uint8_t)0x01)
|
||||
#define NAND_CMD_AREA_C ((uint8_t)0x50)
|
||||
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
|
||||
|
||||
#define NAND_CMD_WRITE0 ((uint8_t)0x80)
|
||||
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
|
||||
#define NAND_CMD_ERASE0 ((uint8_t)0x60)
|
||||
#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
|
||||
#define NAND_CMD_READID ((uint8_t)0x90)
|
||||
#define NAND_CMD_STATUS ((uint8_t)0x70)
|
||||
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
|
||||
#define NAND_CMD_RESET ((uint8_t)0xFF)
|
||||
|
||||
/* NAND memory status */
|
||||
#define NAND_VALID_ADDRESS 0x00000100UL
|
||||
#define NAND_INVALID_ADDRESS 0x00000200UL
|
||||
#define NAND_TIMEOUT_ERROR 0x00000400UL
|
||||
#define NAND_BUSY 0x00000000UL
|
||||
#define NAND_ERROR 0x00000001UL
|
||||
#define NAND_READY 0x00000040UL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup NAND_Private_Macros NAND Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief NAND memory address computation.
|
||||
* @param __ADDRESS__ NAND memory address.
|
||||
* @param __HANDLE__ NAND handle.
|
||||
* @retval NAND Raw address value
|
||||
*/
|
||||
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
|
||||
(((__ADDRESS__)->Block + \
|
||||
(((__ADDRESS__)->Plane) * \
|
||||
((__HANDLE__)->Config.PlaneSize))) * \
|
||||
((__HANDLE__)->Config.BlockSize)))
|
||||
|
||||
/**
|
||||
* @brief NAND memory Column address computation.
|
||||
* @param __HANDLE__ NAND handle.
|
||||
* @retval NAND Raw address value
|
||||
*/
|
||||
#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
|
||||
|
||||
/**
|
||||
* @brief NAND memory address cycling.
|
||||
* @param __ADDRESS__ NAND memory address.
|
||||
* @retval NAND address cycling value.
|
||||
*/
|
||||
#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
|
||||
#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
|
||||
#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
|
||||
#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
|
||||
|
||||
/**
|
||||
* @brief NAND memory Columns cycling.
|
||||
* @param __ADDRESS__ NAND memory address.
|
||||
* @retval NAND Column address cycling value.
|
||||
*/
|
||||
#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */
|
||||
#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FSMC_BANK3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_NAND_H */
|
||||
326
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_nor.h
Normal file
326
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_nor.h
Normal file
@@ -0,0 +1,326 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_nor.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of NOR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_NOR_H
|
||||
#define STM32F1xx_HAL_NOR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(FSMC_BANK1)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_ll_fsmc.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
/** @defgroup NOR_Exported_Types NOR Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL SRAM State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
|
||||
HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
|
||||
HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
|
||||
HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
|
||||
HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
|
||||
} HAL_NOR_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NOR Status typedef
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NOR_STATUS_SUCCESS = 0U,
|
||||
HAL_NOR_STATUS_ONGOING,
|
||||
HAL_NOR_STATUS_ERROR,
|
||||
HAL_NOR_STATUS_TIMEOUT
|
||||
} HAL_NOR_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NOR ID typedef
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
|
||||
|
||||
uint16_t Device_Code1;
|
||||
|
||||
uint16_t Device_Code2;
|
||||
|
||||
uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
|
||||
These codes can be accessed by performing read operations with specific
|
||||
control signals and addresses set.They can also be accessed by issuing
|
||||
an Auto Select command */
|
||||
} NOR_IDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NOR CFI typedef
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*!< Defines the information stored in the memory's Common flash interface
|
||||
which contains a description of various electrical and timing parameters,
|
||||
density information and functions supported by the memory */
|
||||
|
||||
uint16_t CFI_1;
|
||||
|
||||
uint16_t CFI_2;
|
||||
|
||||
uint16_t CFI_3;
|
||||
|
||||
uint16_t CFI_4;
|
||||
} NOR_CFITypeDef;
|
||||
|
||||
/**
|
||||
* @brief NOR handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __NOR_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
|
||||
|
||||
{
|
||||
FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
|
||||
|
||||
FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< NOR locking object */
|
||||
|
||||
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
|
||||
|
||||
uint32_t CommandSet; /*!< NOR algorithm command set and control */
|
||||
|
||||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */
|
||||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
|
||||
} NOR_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL NOR Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */
|
||||
HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */
|
||||
} HAL_NOR_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL NOR Callback pointer definition
|
||||
*/
|
||||
typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
|
||||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup NOR_Exported_Macros NOR Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset NOR handle state
|
||||
* @param __HANDLE__ specifies the NOR handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_NOR_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
|
||||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup NOR_Exported_Functions NOR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing,
|
||||
FSMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
|
||||
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
|
||||
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
|
||||
void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
|
||||
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
|
||||
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
|
||||
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
|
||||
|
||||
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
|
||||
uint32_t uwBufferSize);
|
||||
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
|
||||
uint32_t uwBufferSize);
|
||||
|
||||
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
|
||||
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
|
||||
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
|
||||
|
||||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
||||
/* NOR callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
|
||||
pNOR_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
|
||||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* NOR Control functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
|
||||
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* NOR State functions ********************************************************/
|
||||
HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
|
||||
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup NOR_Private_Constants NOR Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* NOR device IDs addresses */
|
||||
#define MC_ADDRESS ((uint16_t)0x0000)
|
||||
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
|
||||
#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
|
||||
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
|
||||
|
||||
/* NOR CFI IDs addresses */
|
||||
#define CFI1_ADDRESS ((uint16_t)0x0061)
|
||||
#define CFI2_ADDRESS ((uint16_t)0x0062)
|
||||
#define CFI3_ADDRESS ((uint16_t)0x0063)
|
||||
#define CFI4_ADDRESS ((uint16_t)0x0064)
|
||||
|
||||
/* NOR operation wait timeout */
|
||||
#define NOR_TMEOUT ((uint16_t)0xFFFF)
|
||||
|
||||
/* NOR memory data width */
|
||||
#define NOR_MEMORY_8B ((uint8_t)0x00)
|
||||
#define NOR_MEMORY_16B ((uint8_t)0x01)
|
||||
|
||||
/* NOR memory device read/write start address */
|
||||
#define NOR_MEMORY_ADRESS1 (0x60000000U)
|
||||
#define NOR_MEMORY_ADRESS2 (0x64000000U)
|
||||
#define NOR_MEMORY_ADRESS3 (0x68000000U)
|
||||
#define NOR_MEMORY_ADRESS4 (0x6C000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup NOR_Private_Macros NOR Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief NOR memory address shifting.
|
||||
* @param __NOR_ADDRESS NOR base address
|
||||
* @param __NOR_MEMORY_WIDTH_ NOR memory width
|
||||
* @param __ADDRESS__ NOR memory address
|
||||
* @retval NOR shifted address value
|
||||
*/
|
||||
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
|
||||
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
|
||||
((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
|
||||
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
|
||||
|
||||
/**
|
||||
* @brief NOR memory write data to specified address.
|
||||
* @param __ADDRESS__ NOR memory address
|
||||
* @param __DATA__ Data to write
|
||||
* @retval None
|
||||
*/
|
||||
#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \
|
||||
(*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
|
||||
__DSB(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FSMC_BANK1 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_NOR_H */
|
||||
282
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pccard.h
Normal file
282
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pccard.h
Normal file
@@ -0,0 +1,282 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_pccard.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PCCARD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_PCCARD_H
|
||||
#define STM32F1xx_HAL_PCCARD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(FSMC_BANK4)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_ll_fsmc.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCCARD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL PCCARD State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */
|
||||
HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */
|
||||
HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */
|
||||
HAL_PCCARD_STATE_ERROR = 0x04U /*!< PCCARD peripheral error */
|
||||
} HAL_PCCARD_StateTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCCARD_STATUS_SUCCESS = 0U,
|
||||
HAL_PCCARD_STATUS_ONGOING,
|
||||
HAL_PCCARD_STATUS_ERROR,
|
||||
HAL_PCCARD_STATUS_TIMEOUT
|
||||
} HAL_PCCARD_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC_PCCARD handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __PCCARD_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
|
||||
{
|
||||
FSMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
|
||||
|
||||
FSMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
|
||||
|
||||
__IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< PCCARD Lock */
|
||||
|
||||
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */
|
||||
void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */
|
||||
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
|
||||
} PCCARD_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL PCCARD Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCCARD_MSP_INIT_CB_ID = 0x00U, /*!< PCCARD MspInit Callback ID */
|
||||
HAL_PCCARD_MSP_DEINIT_CB_ID = 0x01U, /*!< PCCARD MspDeInit Callback ID */
|
||||
HAL_PCCARD_IT_CB_ID = 0x02U /*!< PCCARD IT Callback ID */
|
||||
} HAL_PCCARD_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL PCCARD Callback pointer definition
|
||||
*/
|
||||
typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
|
||||
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset PCCARD handle state
|
||||
* @param __HANDLE__ specifies the PCCARD handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_PCCARD_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
|
||||
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PCCARD_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCCARD_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
|
||||
FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming,
|
||||
FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
|
||||
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
|
||||
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
|
||||
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PCCARD_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
|
||||
uint8_t *pStatus);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
|
||||
uint8_t *pStatus);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
|
||||
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
|
||||
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
|
||||
void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
|
||||
|
||||
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
|
||||
/* PCCARD callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId,
|
||||
pPCCARD_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard,
|
||||
HAL_PCCARD_CallbackIDTypeDef CallbackId);
|
||||
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PCCARD_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* PCCARD State functions *******************************************************/
|
||||
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
|
||||
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
|
||||
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define PCCARD_DEVICE_ADDRESS 0x90000000U
|
||||
#define PCCARD_ATTRIBUTE_SPACE_ADDRESS 0x98000000U /* Attribute space size to @0x9BFF FFFF */
|
||||
#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
|
||||
#define PCCARD_IO_SPACE_ADDRESS 0x9C000000U /* IO space size to @0x9FFF FFFF */
|
||||
#define PCCARD_IO_SPACE_PRIMARY_ADDR 0x9C0001F0U /* IO space size to @0x9FFF FFFF */
|
||||
|
||||
/* Flash-ATA registers description */
|
||||
#define ATA_DATA ((uint8_t)0x00) /* Data register */
|
||||
#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
|
||||
#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
|
||||
#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
|
||||
#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
|
||||
#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
|
||||
#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
|
||||
#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
|
||||
#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
|
||||
#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */
|
||||
|
||||
/* Flash-ATA commands */
|
||||
#define ATA_READ_SECTOR_CMD ((uint8_t)0x20)
|
||||
#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30)
|
||||
#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0)
|
||||
#define ATA_IDENTIFY_CMD ((uint8_t)0xEC)
|
||||
|
||||
/* PC Card/Compact Flash status */
|
||||
#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60)
|
||||
#define PCCARD_BUSY ((uint8_t)0x80)
|
||||
#define PCCARD_PROGR ((uint8_t)0x01)
|
||||
#define PCCARD_READY ((uint8_t)0x40)
|
||||
|
||||
#define PCCARD_SECTOR_SIZE 255U /* In half words */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Compact Flash redefinition */
|
||||
#define HAL_CF_Init HAL_PCCARD_Init
|
||||
#define HAL_CF_DeInit HAL_PCCARD_DeInit
|
||||
#define HAL_CF_MspInit HAL_PCCARD_MspInit
|
||||
#define HAL_CF_MspDeInit HAL_PCCARD_MspDeInit
|
||||
|
||||
#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
|
||||
#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
|
||||
#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
|
||||
#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
|
||||
#define HAL_CF_Reset HAL_PCCARD_Reset
|
||||
#define HAL_CF_IRQHandler HAL_PCCARD_IRQHandler
|
||||
#define HAL_CF_ITCallback HAL_PCCARD_ITCallback
|
||||
|
||||
#define HAL_CF_GetState HAL_PCCARD_GetState
|
||||
#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
|
||||
#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
|
||||
|
||||
#define HAL_CF_STATUS_SUCCESS HAL_PCCARD_STATUS_SUCCESS
|
||||
#define HAL_CF_STATUS_ONGOING HAL_PCCARD_STATUS_ONGOING
|
||||
#define HAL_CF_STATUS_ERROR HAL_PCCARD_STATUS_ERROR
|
||||
#define HAL_CF_STATUS_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
|
||||
#define HAL_CF_StatusTypeDef HAL_PCCARD_StatusTypeDef
|
||||
|
||||
#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
|
||||
#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
|
||||
#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
|
||||
#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
|
||||
#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
|
||||
|
||||
#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
|
||||
#define CF_BUSY PCCARD_BUSY
|
||||
#define CF_PROGR PCCARD_PROGR
|
||||
#define CF_READY PCCARD_READY
|
||||
|
||||
#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FSMC_BANK4 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_PCCARD_H */
|
||||
1055
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h
Normal file
1055
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h
Normal file
File diff suppressed because it is too large
Load Diff
85
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h
Normal file
85
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h
Normal file
@@ -0,0 +1,85 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_pcd_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PCD HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_PCD_EX_H
|
||||
#define STM32F1xx_HAL_PCD_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
#if defined (USB) || defined (USB_OTG_FS)
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCDEx
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (USB_OTG_FS)
|
||||
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
|
||||
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
#if defined (USB)
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
|
||||
uint16_t ep_kind, uint32_t pmaadress);
|
||||
|
||||
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
|
||||
#endif /* defined (USB) */
|
||||
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
|
||||
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB) || defined (USB_OTG_FS) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
#endif /* STM32F1xx_HAL_PCD_EX_H */
|
||||
604
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h
Normal file
604
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h
Normal file
@@ -0,0 +1,604 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of RTC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_RTC_H
|
||||
#define __STM32F1xx_HAL_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) (((PREDIV) <= 0xFFFFFU) || ((PREDIV) == RTC_AUTO_1_SECOND))
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
|
||||
#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A)
|
||||
#define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUTSOURCE_NONE) || \
|
||||
((__OUTPUT__) == RTC_OUTPUTSOURCE_CALIBCLOCK) || \
|
||||
((__OUTPUT__) == RTC_OUTPUTSOURCE_ALARM) || \
|
||||
((__OUTPUT__) == RTC_OUTPUTSOURCE_SECOND))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup RTC_Timeout_Value Default Timeout Value
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TIMEOUT_VALUE 1000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_EXTI_Line_Event RTC EXTI Line event
|
||||
* @{
|
||||
*/
|
||||
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Types RTC Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 23 */
|
||||
|
||||
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
} RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
|
||||
|
||||
uint32_t Alarm; /*!< Specifies the alarm ID (only 1 alarm ID for STM32F1).
|
||||
This parameter can be a value of @ref RTC_Alarms_Definitions */
|
||||
} RTC_AlarmTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
|
||||
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
|
||||
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
|
||||
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
|
||||
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
|
||||
|
||||
} HAL_RTCStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF or RTC_AUTO_1_SECOND
|
||||
If RTC_AUTO_1_SECOND is selected, AsynchPrediv will be set automatically to get 1sec timebase */
|
||||
|
||||
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC Tamper pin.
|
||||
This parameter can be a value of @ref RTC_output_source_to_output_on_the_Tamper_pin */
|
||||
|
||||
} RTC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay (not necessary for HAL_RTC_SetDate).
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
|
||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
||||
|
||||
uint8_t Date; /*!< Specifies the RTC Date.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
|
||||
uint8_t Year; /*!< Specifies the RTC Date Year.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
|
||||
|
||||
} RTC_DateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Time Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __RTC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
|
||||
{
|
||||
RTC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
RTC_InitTypeDef Init; /*!< RTC required parameters */
|
||||
|
||||
RTC_DateTypeDef DateToUpdate; /*!< Current date set by user and updated automatically */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< RTC locking object */
|
||||
|
||||
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
|
||||
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */
|
||||
|
||||
void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */
|
||||
|
||||
void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
|
||||
|
||||
} RTC_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL RTC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */
|
||||
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */
|
||||
HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */
|
||||
HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */
|
||||
} HAL_RTC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL RTC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Constants RTC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Automatic_Prediv_1_Second Automatic calculation of prediv for 1sec timebase
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AUTO_1_SECOND 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FORMAT_BIN 0x000000000U
|
||||
#define RTC_FORMAT_BCD 0x000000001U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Month_Date_Definitions Month Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Coded in BCD format */
|
||||
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
|
||||
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
|
||||
#define RTC_MONTH_MARCH ((uint8_t)0x03)
|
||||
#define RTC_MONTH_APRIL ((uint8_t)0x04)
|
||||
#define RTC_MONTH_MAY ((uint8_t)0x05)
|
||||
#define RTC_MONTH_JUNE ((uint8_t)0x06)
|
||||
#define RTC_MONTH_JULY ((uint8_t)0x07)
|
||||
#define RTC_MONTH_AUGUST ((uint8_t)0x08)
|
||||
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
|
||||
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
|
||||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
|
||||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
|
||||
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
|
||||
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
|
||||
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
|
||||
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
|
||||
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
|
||||
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x00)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarms_Definitions Alarms Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARM_A 0U /*!< Specify alarm ID (mainly for legacy purposes) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin Output source to output on the Tamper pin
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_OUTPUTSOURCE_NONE 0x00000000U /*!< No output on the TAMPER pin */
|
||||
#define RTC_OUTPUTSOURCE_CALIBCLOCK BKP_RTCCR_CCO /*!< RTC clock with a frequency divided by 64 on the TAMPER pin */
|
||||
#define RTC_OUTPUTSOURCE_ALARM BKP_RTCCR_ASOE /*!< Alarm pulse signal on the TAMPER pin */
|
||||
#define RTC_OUTPUTSOURCE_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Second pulse signal on the TAMPER pin */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_OW RTC_CRH_OWIE /*!< Overflow interrupt */
|
||||
#define RTC_IT_ALRA RTC_CRH_ALRIE /*!< Alarm interrupt */
|
||||
#define RTC_IT_SEC RTC_CRH_SECIE /*!< Second interrupt */
|
||||
#define RTC_IT_TAMP1 BKP_CSR_TPIE /*!< TAMPER Pin interrupt enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flags_Definitions Flags Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RTOFF RTC_CRL_RTOFF /*!< RTC Operation OFF flag */
|
||||
#define RTC_FLAG_RSF RTC_CRL_RSF /*!< Registers Synchronized flag */
|
||||
#define RTC_FLAG_OW RTC_CRL_OWF /*!< Overflow flag */
|
||||
#define RTC_FLAG_ALRAF RTC_CRL_ALRF /*!< Alarm flag */
|
||||
#define RTC_FLAG_SEC RTC_CRL_SECF /*!< Second flag */
|
||||
#define RTC_FLAG_TAMP1F BKP_CSR_TEF /*!< Tamper Interrupt Flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_macros RTC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset RTC handle state
|
||||
* @param __HANDLE__: RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
|
||||
(__HANDLE__)->State = HAL_RTC_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL;\
|
||||
(__HANDLE__)->MspDeInitCallback = NULL;\
|
||||
}while(0u)
|
||||
#else
|
||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Disable the write protection for RTC registers.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
|
||||
|
||||
/**
|
||||
* @brief Enable the write protection for RTC registers.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC Alarm interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Alarm interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be checked
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Alarm's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_ALRAF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CRL) & (__INTERRUPT__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm's pending flags.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_ALRAF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) &= ~(__FLAG__)
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on ALARM Exti Line 17.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on ALARM Exti Line 17.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Enable event on ALARM Exti Line 17.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on ALARM Exti Line 17.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
|
||||
/**
|
||||
* @brief ALARM EXTI line configuration: set falling edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the ALARM Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
|
||||
/**
|
||||
* @brief ALARM EXTI line configuration: set rising edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable the ALARM Extended Interrupt Rising Trigger.
|
||||
* This parameter can be:
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief ALARM EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||
do{ \
|
||||
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Disable the ALARM Extended Interrupt Rising & Falling Trigger.
|
||||
* This parameter can be:
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do{ \
|
||||
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified ALARM EXTI interrupt flag is set or not.
|
||||
* @retval EXTI ALARM Line Status.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & (RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Clear the ALARM EXTI flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = (RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RTC_EXTI_LINE_ALARM_EVENT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include RTC HAL Extension module */
|
||||
#include "stm32f1xx_hal_rtc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RTC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/** @addtogroup RTC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* RTC Time and Date functions ************************************************/
|
||||
/** @addtogroup RTC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* RTC Alarm functions ********************************************************/
|
||||
/** @addtogroup RTC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
|
||||
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
|
||||
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions *************************************************/
|
||||
/** @addtogroup RTC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/** @addtogroup RTC_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_RTC_H */
|
||||
409
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h
Normal file
409
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h
Normal file
@@ -0,0 +1,409 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_rtc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of RTC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_RTC_EX_H
|
||||
#define __STM32F1xx_HAL_RTC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTCEx_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Alias_For_Legacy Alias define maintained for legacy
|
||||
* @{
|
||||
*/
|
||||
#define HAL_RTCEx_TamperTimeStampIRQHandler HAL_RTCEx_TamperIRQHandler
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_TAMPER(__TAMPER__) ((__TAMPER__) == RTC_TAMPER_1)
|
||||
|
||||
#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
|
||||
((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
|
||||
|
||||
#if RTC_BKP_NUMBER > 10U
|
||||
#define IS_RTC_BKP(BKP) (((BKP) <= (uint32_t)RTC_BKP_DR10) || (((BKP) >= (uint32_t)RTC_BKP_DR11) && ((BKP) <= (uint32_t)RTC_BKP_DR42)))
|
||||
#else
|
||||
#define IS_RTC_BKP(BKP) ((BKP) <= (uint32_t)RTC_BKP_NUMBER)
|
||||
#endif
|
||||
#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007FU)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief RTC Tamper structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Tamper; /*!< Specifies the Tamper Pin.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
|
||||
|
||||
uint32_t Trigger; /*!< Specifies the Tamper Trigger.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
|
||||
|
||||
} RTC_TamperTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPER_1 BKP_CR_TPE /*!< Select tamper to be enabled (mainly for legacy purposes) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPERTRIGGER_LOWLEVEL BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
|
||||
#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x00000000U /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions
|
||||
* @{
|
||||
*/
|
||||
#if RTC_BKP_NUMBER > 0U
|
||||
#define RTC_BKP_DR1 0x00000001U
|
||||
#define RTC_BKP_DR2 0x00000002U
|
||||
#define RTC_BKP_DR3 0x00000003U
|
||||
#define RTC_BKP_DR4 0x00000004U
|
||||
#define RTC_BKP_DR5 0x00000005U
|
||||
#define RTC_BKP_DR6 0x00000006U
|
||||
#define RTC_BKP_DR7 0x00000007U
|
||||
#define RTC_BKP_DR8 0x00000008U
|
||||
#define RTC_BKP_DR9 0x00000009U
|
||||
#define RTC_BKP_DR10 0x0000000AU
|
||||
#endif /* RTC_BKP_NUMBER > 0 */
|
||||
|
||||
#if RTC_BKP_NUMBER > 10U
|
||||
#define RTC_BKP_DR11 0x00000010U
|
||||
#define RTC_BKP_DR12 0x00000011U
|
||||
#define RTC_BKP_DR13 0x00000012U
|
||||
#define RTC_BKP_DR14 0x00000013U
|
||||
#define RTC_BKP_DR15 0x00000014U
|
||||
#define RTC_BKP_DR16 0x00000015U
|
||||
#define RTC_BKP_DR17 0x00000016U
|
||||
#define RTC_BKP_DR18 0x00000017U
|
||||
#define RTC_BKP_DR19 0x00000018U
|
||||
#define RTC_BKP_DR20 0x00000019U
|
||||
#define RTC_BKP_DR21 0x0000001AU
|
||||
#define RTC_BKP_DR22 0x0000001BU
|
||||
#define RTC_BKP_DR23 0x0000001CU
|
||||
#define RTC_BKP_DR24 0x0000001DU
|
||||
#define RTC_BKP_DR25 0x0000001EU
|
||||
#define RTC_BKP_DR26 0x0000001FU
|
||||
#define RTC_BKP_DR27 0x00000020U
|
||||
#define RTC_BKP_DR28 0x00000021U
|
||||
#define RTC_BKP_DR29 0x00000022U
|
||||
#define RTC_BKP_DR30 0x00000023U
|
||||
#define RTC_BKP_DR31 0x00000024U
|
||||
#define RTC_BKP_DR32 0x00000025U
|
||||
#define RTC_BKP_DR33 0x00000026U
|
||||
#define RTC_BKP_DR34 0x00000027U
|
||||
#define RTC_BKP_DR35 0x00000028U
|
||||
#define RTC_BKP_DR36 0x00000029U
|
||||
#define RTC_BKP_DR37 0x0000002AU
|
||||
#define RTC_BKP_DR38 0x0000002BU
|
||||
#define RTC_BKP_DR39 0x0000002CU
|
||||
#define RTC_BKP_DR40 0x0000002DU
|
||||
#define RTC_BKP_DR41 0x0000002EU
|
||||
#define RTC_BKP_DR42 0x0000002FU
|
||||
#endif /* RTC_BKP_NUMBER > 10 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC Tamper interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_TAMP1: Tamper A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(BKP->CSR, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Tamper interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_TAMP1: Tamper A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(BKP->CSR, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_TAMP1
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & ((__INTERRUPT__))) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Tamper's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_TAMP1F
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) ((((BKP->CSR) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Tamper's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_TAMP1
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & (BKP_CSR_TEF)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Tamper's pending flags.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_TAMP1F
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT(BKP->CSR, BKP_CSR_CTE | BKP_CSR_CTI)
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC Second interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_SEC: Second A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_SECOND_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Second interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Second interrupt sources to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_SEC: Second A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_SECOND_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Second interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_SEC: Second A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_SECOND_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Second's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_SEC
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_SECOND_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Second's pending flags.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_SEC
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_SECOND_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) &= ~(__FLAG__)
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC Overflow interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_OW: Overflow A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_OVERFLOW_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Overflow interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_OW: Overflow A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_OVERFLOW_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Overflow interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_OW: Overflow A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_OVERFLOW_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__))) ) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Overflow's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_OW
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_OVERFLOW_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Overflow's pending flags.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_OW
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_OVERFLOW_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RTCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* RTC Tamper functions *****************************************/
|
||||
/** @addtogroup RTCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
|
||||
void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* RTC Second functions *****************************************/
|
||||
/** @addtogroup RTCEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Extension Control functions ************************************************/
|
||||
/** @addtogroup RTCEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
|
||||
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
|
||||
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_RTC_EX_H */
|
||||
758
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sd.h
Normal file
758
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sd.h
Normal file
@@ -0,0 +1,758 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_sd.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of SD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_SD_H
|
||||
#define STM32F1xx_HAL_SD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(SDIO)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_ll_sdmmc.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SD SD
|
||||
* @brief SD HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SD_Exported_Types SD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */
|
||||
HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */
|
||||
HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */
|
||||
HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
|
||||
HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
|
||||
HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */
|
||||
HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfer State */
|
||||
HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
|
||||
}HAL_SD_StateTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef uint32_t HAL_SD_CardStateTypeDef;
|
||||
|
||||
#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */
|
||||
#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
|
||||
#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
|
||||
#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
|
||||
#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
|
||||
#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
|
||||
#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
|
||||
#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
|
||||
#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#define SD_InitTypeDef SDIO_InitTypeDef
|
||||
#define SD_TypeDef SDIO_TypeDef
|
||||
|
||||
/**
|
||||
* @brief SD Card Information Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CardType; /*!< Specifies the card Type */
|
||||
|
||||
uint32_t CardVersion; /*!< Specifies the card version */
|
||||
|
||||
uint32_t Class; /*!< Specifies the class of the card class */
|
||||
|
||||
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
|
||||
|
||||
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
|
||||
|
||||
uint32_t BlockSize; /*!< Specifies one block size in bytes */
|
||||
|
||||
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
|
||||
|
||||
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
|
||||
|
||||
}HAL_SD_CardInfoTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SD handle Structure definition
|
||||
*/
|
||||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
|
||||
typedef struct __SD_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
|
||||
{
|
||||
SD_TypeDef *Instance; /*!< SD registers base address */
|
||||
|
||||
SD_InitTypeDef Init; /*!< SD required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SD locking object */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
|
||||
|
||||
uint32_t TxXferSize; /*!< SD Tx Transfer size */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
|
||||
|
||||
uint32_t RxXferSize; /*!< SD Rx Transfer size */
|
||||
|
||||
__IO uint32_t Context; /*!< SD transfer context */
|
||||
|
||||
__IO HAL_SD_StateTypeDef State; /*!< SD card State */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< SD Card Error codes */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
|
||||
|
||||
HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
|
||||
|
||||
uint32_t CSD[4]; /*!< SD card specific data table */
|
||||
|
||||
uint32_t CID[4]; /*!< SD card identification number table */
|
||||
|
||||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
|
||||
void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd);
|
||||
void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd);
|
||||
void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd);
|
||||
void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd);
|
||||
|
||||
void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd);
|
||||
void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd);
|
||||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
|
||||
}SD_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t CSDStruct; /*!< CSD structure */
|
||||
__IO uint8_t SysSpecVersion; /*!< System specification version */
|
||||
__IO uint8_t Reserved1; /*!< Reserved */
|
||||
__IO uint8_t TAAC; /*!< Data read access time 1 */
|
||||
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
|
||||
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
|
||||
__IO uint16_t CardComdClasses; /*!< Card command classes */
|
||||
__IO uint8_t RdBlockLen; /*!< Max. read data block length */
|
||||
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
|
||||
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
|
||||
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
|
||||
__IO uint8_t DSRImpl; /*!< DSR implemented */
|
||||
__IO uint8_t Reserved2; /*!< Reserved */
|
||||
__IO uint32_t DeviceSize; /*!< Device Size */
|
||||
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
|
||||
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
|
||||
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
|
||||
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
|
||||
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
|
||||
__IO uint8_t EraseGrSize; /*!< Erase group size */
|
||||
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
|
||||
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
|
||||
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
|
||||
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
|
||||
__IO uint8_t WrSpeedFact; /*!< Write speed factor */
|
||||
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
|
||||
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
|
||||
__IO uint8_t Reserved3; /*!< Reserved */
|
||||
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
|
||||
__IO uint8_t FileFormatGroup; /*!< File format group */
|
||||
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
|
||||
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
|
||||
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
|
||||
__IO uint8_t FileFormat; /*!< File format */
|
||||
__IO uint8_t ECC; /*!< ECC code */
|
||||
__IO uint8_t CSD_CRC; /*!< CSD CRC */
|
||||
__IO uint8_t Reserved4; /*!< Always 1 */
|
||||
}HAL_SD_CardCSDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
|
||||
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
|
||||
__IO uint32_t ProdName1; /*!< Product Name part1 */
|
||||
__IO uint8_t ProdName2; /*!< Product Name part2 */
|
||||
__IO uint8_t ProdRev; /*!< Product Revision */
|
||||
__IO uint32_t ProdSN; /*!< Product Serial Number */
|
||||
__IO uint8_t Reserved1; /*!< Reserved1 */
|
||||
__IO uint16_t ManufactDate; /*!< Manufacturing Date */
|
||||
__IO uint8_t CID_CRC; /*!< CID CRC */
|
||||
__IO uint8_t Reserved2; /*!< Always 1 */
|
||||
|
||||
}HAL_SD_CardCIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
|
||||
__IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
|
||||
__IO uint16_t CardType; /*!< Carries information about card type */
|
||||
__IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
|
||||
__IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
|
||||
__IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
|
||||
__IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
|
||||
__IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
|
||||
__IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
|
||||
__IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
|
||||
|
||||
}HAL_SD_CardStatusTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
|
||||
/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */
|
||||
HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */
|
||||
HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */
|
||||
HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */
|
||||
|
||||
HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */
|
||||
HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */
|
||||
}HAL_SD_CallbackIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SD_Exported_Constants Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
|
||||
|
||||
/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
|
||||
#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
|
||||
#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
|
||||
#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
|
||||
#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
|
||||
#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
|
||||
#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
|
||||
#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
|
||||
#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
|
||||
number of transferred bytes does not match the block length */
|
||||
#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
|
||||
#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
|
||||
#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
|
||||
#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
|
||||
command or if there was an attempt to access a locked card */
|
||||
#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
|
||||
#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
|
||||
#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
|
||||
#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
|
||||
#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
|
||||
#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
|
||||
#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
|
||||
#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
|
||||
#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
|
||||
#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
|
||||
#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
|
||||
of erase sequence command was received */
|
||||
#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
|
||||
#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
|
||||
#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
|
||||
#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
|
||||
#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
|
||||
#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
|
||||
#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
|
||||
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
|
||||
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
|
||||
|
||||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
|
||||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
|
||||
* @{
|
||||
*/
|
||||
#define SD_CONTEXT_NONE 0x00000000U /*!< None */
|
||||
#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
|
||||
#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
|
||||
#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
|
||||
#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
|
||||
#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
|
||||
#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
|
||||
* @{
|
||||
*/
|
||||
#define CARD_SDSC 0x00000000U /*!< SD Standard Capacity <2Go */
|
||||
#define CARD_SDHC_SDXC 0x00000001U /*!< SD High Capacity <32Go, SD Extended Capacity <2To */
|
||||
#define CARD_SECURED 0x00000003U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
|
||||
* @{
|
||||
*/
|
||||
#define CARD_V1_X 0x00000000U
|
||||
#define CARD_V2_X 0x00000001U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup SD_Exported_macros SD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset SD handle state.
|
||||
* @param __HANDLE__ : SD handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_SD_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET)
|
||||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the SD device.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Disable the SD device.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Enable the SDMMC DMA transfer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Disable the SDMMC DMA transfer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Enable the SD device interrupt.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the SD device interrupt.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified SD flag is set or not.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
|
||||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
|
||||
* @arg SDIO_FLAG_TXACT: Data transmit in progress
|
||||
* @arg SDIO_FLAG_RXACT: Data receive in progress
|
||||
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
||||
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
|
||||
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
|
||||
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
|
||||
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
|
||||
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
|
||||
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
|
||||
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
|
||||
* @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
|
||||
* @retval The new state of SD FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the SD's pending flags.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
|
||||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified SD interrupt has occurred or not.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
|
||||
* @retval The new state of SD IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the SD's interrupt pending bits.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup SD_Exported_Functions SD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
|
||||
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
|
||||
HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
|
||||
/* Non-Blocking mode: IT */
|
||||
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
|
||||
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
|
||||
|
||||
/* Callback in non blocking modes (DMA) */
|
||||
void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
|
||||
|
||||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
|
||||
/* SD callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);
|
||||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group4 SD card related functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
|
||||
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
|
||||
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
|
||||
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
|
||||
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
|
||||
HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
|
||||
uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
|
||||
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Types SD Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Defines SD Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Variables SD Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Constants SD Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Macros SD Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Functions SD Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* SDIO */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32F1xx_HAL_SD_H */
|
||||
743
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_smartcard.h
Normal file
743
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_smartcard.h
Normal file
@@ -0,0 +1,743 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_smartcard.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of SMARTCARD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_SMARTCARD_H
|
||||
#define __STM32F1xx_HAL_SMARTCARD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SMARTCARD Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (16 * (hsc->Init.BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref SMARTCARD_Word_Length */
|
||||
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref SMARTCARD_Stop_Bits */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref SMARTCARD_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits).*/
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref SMARTCARD_Mode */
|
||||
|
||||
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
|
||||
|
||||
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref SMARTCARD_Clock_Phase */
|
||||
|
||||
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref SMARTCARD_Last_Bit */
|
||||
|
||||
uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
|
||||
to provide the smartcard clock. The value given in the register (5 significant bits)
|
||||
is multiplied by 2 to give the division factor of the source clock frequency.
|
||||
This parameter can be a value of @ref SMARTCARD_Prescaler */
|
||||
|
||||
uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
|
||||
|
||||
uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state.
|
||||
This parameter can be a value of @ref SMARTCARD_NACK_State */
|
||||
}SMARTCARD_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SMARTCARD State structures definition
|
||||
* @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
|
||||
* - gState contains SMARTCARD state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : (Not Used)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 IP initialization status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized. HAL SMARTCARD Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 IP initialization status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between gState and RxState values */
|
||||
HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
|
||||
Value is allowed for gState only */
|
||||
}HAL_SMARTCARD_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SMARTCARD handle Structure definition
|
||||
*/
|
||||
typedef struct __SMARTCARD_HandleTypeDef
|
||||
{
|
||||
USART_TypeDef *Instance; /*!< USART registers base address */
|
||||
|
||||
SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
|
||||
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
|
||||
|
||||
__IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< SmartCard Error code */
|
||||
|
||||
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
|
||||
void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Tx Complete Callback */
|
||||
|
||||
void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Rx Complete Callback */
|
||||
|
||||
void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Error Callback */
|
||||
|
||||
void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Complete Callback */
|
||||
|
||||
void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Transmit Complete Callback */
|
||||
|
||||
void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Receive Complete Callback */
|
||||
|
||||
void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Msp DeInit callback */
|
||||
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
|
||||
|
||||
} SMARTCARD_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL SMARTCARD Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */
|
||||
HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */
|
||||
HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */
|
||||
HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */
|
||||
HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */
|
||||
HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */
|
||||
|
||||
HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */
|
||||
HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */
|
||||
|
||||
} HAL_SMARTCARD_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SMARTCARD Callback pointer definition
|
||||
*/
|
||||
typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc); /*!< pointer to an SMARTCARD callback function */
|
||||
|
||||
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMARTCARD_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_SMARTCARD_ERROR_PE 0x00000001U /*!< Parity error */
|
||||
#define HAL_SMARTCARD_ERROR_NE 0x00000002U /*!< Noise error */
|
||||
#define HAL_SMARTCARD_ERROR_FE 0x00000004U /*!< Frame error */
|
||||
#define HAL_SMARTCARD_ERROR_ORE 0x00000008U /*!< Overrun error */
|
||||
#define HAL_SMARTCARD_ERROR_DMA 0x00000010U /*!< DMA transfer error */
|
||||
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
|
||||
#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Parity SMARTCARD Parity
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
|
||||
#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Mode SMARTCARD Mode
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
|
||||
#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
|
||||
#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_POLARITY_LOW 0x00000000U
|
||||
#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_PHASE_1EDGE 0x00000000U
|
||||
#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_LASTBIT_DISABLE 0x00000000U
|
||||
#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
|
||||
#define SMARTCARD_NACK_DISABLE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
|
||||
#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U /*!< SYSCLK divided by 2 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U /*!< SYSCLK divided by 4 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U /*!< SYSCLK divided by 6 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U /*!< SYSCLK divided by 8 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U /*!< SYSCLK divided by 10 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U /*!< SYSCLK divided by 12 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U /*!< SYSCLK divided by 14 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U /*!< SYSCLK divided by 16 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U /*!< SYSCLK divided by 18 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU /*!< SYSCLK divided by 20 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU /*!< SYSCLK divided by 22 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU /*!< SYSCLK divided by 24 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU /*!< SYSCLK divided by 26 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU /*!< SYSCLK divided by 28 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU /*!< SYSCLK divided by 30 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U /*!< SYSCLK divided by 32 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U /*!< SYSCLK divided by 34 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U /*!< SYSCLK divided by 36 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U /*!< SYSCLK divided by 38 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U /*!< SYSCLK divided by 40 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U /*!< SYSCLK divided by 42 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U /*!< SYSCLK divided by 44 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U /*!< SYSCLK divided by 46 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U /*!< SYSCLK divided by 48 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U /*!< SYSCLK divided by 50 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU /*!< SYSCLK divided by 52 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU /*!< SYSCLK divided by 54 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU /*!< SYSCLK divided by 56 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU /*!< SYSCLK divided by 58 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU /*!< SYSCLK divided by 60 */
|
||||
#define SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU /*!< SYSCLK divided by 62 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SmartCard_Flags SMARTCARD Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the SR register
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE)
|
||||
#define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC)
|
||||
#define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
|
||||
#define SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
|
||||
#define SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE)
|
||||
#define SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE)
|
||||
#define SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE)
|
||||
#define SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
|
||||
* Elements values convention: 0xY000XXXX
|
||||
* - XXXX : Interrupt mask in the Y register
|
||||
* - Y : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 11: CR3 register
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
|
||||
#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
|
||||
#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
|
||||
#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
|
||||
#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
|
||||
#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SMARTCARD handle gstate & RxState
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
|
||||
} while(0U)
|
||||
#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Flush the Smartcard DR register
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
|
||||
|
||||
/** @brief Check whether the specified Smartcard flag is set or not.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
|
||||
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag
|
||||
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
|
||||
* @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
|
||||
* @arg SMARTCARD_FLAG_ORE: Overrun Error flag
|
||||
* @arg SMARTCARD_FLAG_NE: Noise Error flag
|
||||
* @arg SMARTCARD_FLAG_FE: Framing Error flag
|
||||
* @arg SMARTCARD_FLAG_PE: Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the specified Smartcard pending flags.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
|
||||
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
|
||||
*
|
||||
* @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun
|
||||
* error) flags are cleared by software sequence: a read operation to
|
||||
* USART_SR register followed by a read operation to USART_DR register.
|
||||
* @note RXNE flag can be also cleared by a read to the USART_DR register.
|
||||
* @note TC flag can be also cleared by software sequence: a read operation to
|
||||
* USART_SR register followed by a write operation to USART_DR register.
|
||||
* @note TXE flag is cleared only by a write to the USART_DR register.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
||||
|
||||
/** @brief Clear the SMARTCARD PE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
tmpreg = (__HANDLE__)->Instance->SR; \
|
||||
tmpreg = (__HANDLE__)->Instance->DR; \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Clear the SMARTCARD FE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the SMARTCARD NE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the SMARTCARD ORE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the SMARTCARD IDLE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Enable the specified SmartCard interrupt.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
|
||||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
|
||||
|
||||
/** @brief Disable the specified SmartCard interrupt.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
|
||||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
|
||||
|
||||
/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the SmartCard Handle.
|
||||
* @param __IT__ specifies the SMARTCARD interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
|
||||
* @arg SMARTCARD_IT_ERR: Error interrupt
|
||||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
|
||||
|
||||
/** @brief Enable the USART associated to the SMARTCARD Handle
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable the USART associated to the SMARTCARD Handle
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/** @brief Macros to enable the SmartCard DMA request.
|
||||
* @param __HANDLE__ specifies the SmartCard Handle.
|
||||
* @param __REQUEST__ specifies the SmartCard DMA request.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
|
||||
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
|
||||
|
||||
/** @brief Macros to disable the SmartCard DMA request.
|
||||
* @param __HANDLE__ specifies the SmartCard Handle.
|
||||
* @param __REQUEST__ specifies the SmartCard DMA request.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
|
||||
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SMARTCARD_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARD_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARD_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc);
|
||||
|
||||
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARD_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions **************************************************/
|
||||
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsc);
|
||||
uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief SMARTCARD interruptions flag mask
|
||||
*
|
||||
*/
|
||||
#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
|
||||
USART_CR1_IDLEIE | USART_CR3_EIE )
|
||||
|
||||
#define SMARTCARD_CR1_REG_INDEX 1U
|
||||
#define SMARTCARD_CR3_REG_INDEX 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
|
||||
#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
|
||||
((STOPBITS) == SMARTCARD_STOPBITS_1_5))
|
||||
#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
|
||||
((PARITY) == SMARTCARD_PARITY_ODD))
|
||||
#define IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
|
||||
#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
|
||||
#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
|
||||
#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
|
||||
((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
|
||||
#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
|
||||
((NACK) == SMARTCARD_NACK_DISABLE))
|
||||
#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
|
||||
|
||||
#define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25U)/(4U*(__BAUD__)))
|
||||
#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100U)
|
||||
#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) ((((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U) + 50U) / 100U)
|
||||
/* SMARTCARD BRR = mantissa + overflow + fraction
|
||||
= (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
|
||||
#define SMARTCARD_BRR(__PCLK__, __BAUD__) (((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4U) + \
|
||||
(SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0xF0U)) + \
|
||||
(SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0FU))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_SMARTCARD_H */
|
||||
|
||||
734
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h
Normal file
734
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h
Normal file
@@ -0,0 +1,734 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_spi.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of SPI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_SPI_H
|
||||
#define STM32F1xx_HAL_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SPI_Exported_Types SPI Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SPI Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the SPI operating mode.
|
||||
This parameter can be a value of @ref SPI_Mode */
|
||||
|
||||
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
|
||||
This parameter can be a value of @ref SPI_Direction */
|
||||
|
||||
uint32_t DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_Data_Size */
|
||||
|
||||
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||
|
||||
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
|
||||
This parameter can be a value of @ref SPI_TI_mode */
|
||||
|
||||
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
|
||||
This parameter can be a value of @ref SPI_CRC_Calculation */
|
||||
|
||||
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
|
||||
This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
|
||||
} SPI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SPI State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
|
||||
HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
|
||||
HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
|
||||
HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
|
||||
} HAL_SPI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SPI handle Structure definition
|
||||
*/
|
||||
typedef struct __SPI_HandleTypeDef
|
||||
{
|
||||
SPI_TypeDef *Instance; /*!< SPI registers base address */
|
||||
|
||||
SPI_InitTypeDef Init; /*!< SPI communication parameters */
|
||||
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< SPI Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
|
||||
|
||||
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
|
||||
|
||||
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< SPI Error code */
|
||||
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
||||
void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
|
||||
void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
|
||||
void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
|
||||
void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
|
||||
void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
|
||||
void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
|
||||
void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
|
||||
void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
|
||||
void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
||||
} SPI_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
* @brief HAL SPI Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
|
||||
HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
|
||||
HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
|
||||
HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */
|
||||
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */
|
||||
HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */
|
||||
HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
|
||||
HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
|
||||
HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
|
||||
HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
|
||||
|
||||
} HAL_SPI_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SPI Callback pointer definition
|
||||
*/
|
||||
typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
|
||||
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SPI_Exported_Constants SPI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Error_Code SPI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
|
||||
#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
|
||||
#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
|
||||
#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */
|
||||
#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Mode SPI Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPI_MODE_SLAVE (0x00000000U)
|
||||
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Direction SPI Direction Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPI_DIRECTION_2LINES (0x00000000U)
|
||||
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
|
||||
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Data_Size SPI Data Size
|
||||
* @{
|
||||
*/
|
||||
#define SPI_DATASIZE_8BIT (0x00000000U)
|
||||
#define SPI_DATASIZE_16BIT SPI_CR1_DFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define SPI_POLARITY_LOW (0x00000000U)
|
||||
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Phase SPI Clock Phase
|
||||
* @{
|
||||
*/
|
||||
#define SPI_PHASE_1EDGE (0x00000000U)
|
||||
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
|
||||
* @{
|
||||
*/
|
||||
#define SPI_NSS_SOFT SPI_CR1_SSM
|
||||
#define SPI_NSS_HARD_INPUT (0x00000000U)
|
||||
#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
|
||||
#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
|
||||
#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
|
||||
#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
|
||||
#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
|
||||
#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
|
||||
#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
|
||||
#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FIRSTBIT_MSB (0x00000000U)
|
||||
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_TI_mode SPI TI Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPI_TIMODE_DISABLE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
|
||||
* @{
|
||||
*/
|
||||
#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
|
||||
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
|
||||
* @{
|
||||
*/
|
||||
#define SPI_IT_TXE SPI_CR2_TXEIE
|
||||
#define SPI_IT_RXNE SPI_CR2_RXNEIE
|
||||
#define SPI_IT_ERR SPI_CR2_ERRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Flags_definition SPI Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
|
||||
#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
|
||||
#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
|
||||
#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
|
||||
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
|
||||
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
|
||||
#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY\
|
||||
| SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup SPI_Exported_Macros SPI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SPI handle state.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified SPI interrupts.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified SPI interrupts.
|
||||
* @param __HANDLE__ specifies the SPI handle.
|
||||
* This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified SPI interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg SPI_FLAG_CRCERR: CRC error flag
|
||||
* @arg SPI_FLAG_MODF: Mode fault flag
|
||||
* @arg SPI_FLAG_OVR: Overrun flag
|
||||
* @arg SPI_FLAG_BSY: Busy flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the SPI CRCERR pending flag.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
|
||||
|
||||
/** @brief Clear the SPI MODF pending flag.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_modf = 0x00U; \
|
||||
tmpreg_modf = (__HANDLE__)->Instance->SR; \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
|
||||
UNUSED(tmpreg_modf); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Clear the SPI OVR pending flag.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_ovr); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Enable the SPI peripheral.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
|
||||
|
||||
/** @brief Disable the SPI peripheral.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup SPI_Private_Constants SPI Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define SPI_INVALID_CRC_ERROR 0U /* CRC error wrongly detected */
|
||||
#define SPI_VALID_CRC_ERROR 1U /* CRC error is true */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SPI_Private_Macros SPI Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Set the SPI transmit-only mode.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
|
||||
|
||||
/** @brief Set the SPI receive-only mode.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
|
||||
|
||||
/** @brief Reset the CRC calculation of the SPI.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_RESET_CRC(__HANDLE__) \
|
||||
do{ \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
|
||||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of SPI SR register.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg SPI_FLAG_CRCERR: CRC error flag
|
||||
* @arg SPI_FLAG_MODF: Mode fault flag
|
||||
* @arg SPI_FLAG_OVR: Overrun flag
|
||||
* @arg SPI_FLAG_BSY: Busy flag
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
|
||||
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __CR2__ copy of SPI CR2 register.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
|
||||
(__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks if SPI Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Mode.
|
||||
* This parameter can be a value of @ref SPI_Mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
|
||||
((__MODE__) == SPI_MODE_MASTER))
|
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Direction Mode.
|
||||
* This parameter can be a value of @ref SPI_Direction
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
|
||||
((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
|
||||
((__MODE__) == SPI_DIRECTION_1LINE))
|
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is 2 lines.
|
||||
* @param __MODE__ specifies the SPI Direction Mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
|
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
|
||||
* @param __MODE__ specifies the SPI Direction Mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
|
||||
((__MODE__) == SPI_DIRECTION_1LINE))
|
||||
|
||||
/** @brief Checks if SPI Data Size parameter is in allowed range.
|
||||
* @param __DATASIZE__ specifies the SPI Data Size.
|
||||
* This parameter can be a value of @ref SPI_Data_Size
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
|
||||
((__DATASIZE__) == SPI_DATASIZE_8BIT))
|
||||
|
||||
/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
|
||||
* @param __CPOL__ specifies the SPI serial clock steady state.
|
||||
* This parameter can be a value of @ref SPI_Clock_Polarity
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
|
||||
((__CPOL__) == SPI_POLARITY_HIGH))
|
||||
|
||||
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
|
||||
* @param __CPHA__ specifies the SPI Clock Phase.
|
||||
* This parameter can be a value of @ref SPI_Clock_Phase
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
|
||||
((__CPHA__) == SPI_PHASE_2EDGE))
|
||||
|
||||
/** @brief Checks if SPI Slave Select parameter is in allowed range.
|
||||
* @param __NSS__ specifies the SPI Slave Select management parameter.
|
||||
* This parameter can be a value of @ref SPI_Slave_Select_management
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_INPUT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_OUTPUT))
|
||||
|
||||
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
|
||||
* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
|
||||
* This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
|
||||
|
||||
/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
|
||||
* @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
|
||||
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
|
||||
((__BIT__) == SPI_FIRSTBIT_LSB))
|
||||
|
||||
/** @brief Checks if SPI TI mode parameter is disabled.
|
||||
* @param __MODE__ SPI_TIMODE_DISABLE. Device not support Ti Mode.
|
||||
* This parameter can be a value of @ref SPI_TI_mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE)
|
||||
|
||||
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
|
||||
* @param __CALCULATION__ specifies the SPI CRC calculation enable state.
|
||||
* This parameter can be a value of @ref SPI_CRC_Calculation
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
|
||||
((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
|
||||
|
||||
/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
|
||||
* @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
|
||||
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
|
||||
((__POLYNOMIAL__) <= 0xFFFFU) && \
|
||||
(((__POLYNOMIAL__)&0x1U) != 0U))
|
||||
|
||||
/** @brief Checks if DMA handle is valid.
|
||||
* @param __HANDLE__ specifies a DMA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup SPI_Private_Functions SPI Private Functions
|
||||
* @{
|
||||
*/
|
||||
uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SPI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
||||
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
|
||||
pSPI_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
|
||||
|
||||
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi);
|
||||
uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_SPI_H */
|
||||
|
||||
232
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h
Normal file
232
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h
Normal file
@@ -0,0 +1,232 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_sram.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of SRAM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_SRAM_H
|
||||
#define STM32F1xx_HAL_SRAM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(FSMC_BANK1)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_ll_fsmc.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup SRAM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SRAM_Exported_Types SRAM Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief HAL SRAM State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
|
||||
HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
|
||||
HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
|
||||
HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
|
||||
HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
|
||||
|
||||
} HAL_SRAM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SRAM handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __SRAM_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
||||
{
|
||||
FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
|
||||
|
||||
FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SRAM locking object */
|
||||
|
||||
__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
|
||||
|
||||
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
|
||||
|
||||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
|
||||
void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */
|
||||
void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */
|
||||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
||||
} SRAM_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL SRAM Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */
|
||||
HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
|
||||
HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
|
||||
HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
|
||||
} HAL_SRAM_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SRAM Callback pointer definition
|
||||
*/
|
||||
typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
|
||||
typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
|
||||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SRAM handle state
|
||||
* @param __HANDLE__ SRAM handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
|
||||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
|
||||
FSMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
|
||||
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
|
||||
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
|
||||
uint32_t BufferSize);
|
||||
|
||||
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
|
||||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
||||
/* SRAM callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
|
||||
pSRAM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
|
||||
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
|
||||
pSRAM_DmaCallbackTypeDef pCallback);
|
||||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SRAM Control functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
|
||||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SRAM State functions ******************************************************/
|
||||
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FSMC_BANK1 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_SRAM_H */
|
||||
915
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
Normal file
915
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
Normal file
@@ -0,0 +1,915 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_uart.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of UART HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_UART_H
|
||||
#define __STM32F1xx_HAL_UART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup UART_Exported_Types UART Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief UART Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (16 * (huart->Init.BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref UART_Word_Length */
|
||||
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref UART_Stop_Bits */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref UART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref UART_Mode */
|
||||
|
||||
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
|
||||
This parameter can be a value of @ref UART_Hardware_Flow_Control */
|
||||
|
||||
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
|
||||
This parameter can be a value of @ref UART_Over_Sampling. This feature is only available
|
||||
on STM32F100xx family, so OverSampling parameter should always be set to 16. */
|
||||
} UART_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL UART State structures definition
|
||||
* @note HAL UART State value is a combination of 2 different substates: gState and RxState.
|
||||
* - gState contains UART state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : (Not Used)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized. HAL UART Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (Peripheral busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between gState and RxState values */
|
||||
HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
HAL_UART_STATE_ERROR = 0xE0U /*!< Error
|
||||
Value is allowed for gState only */
|
||||
} HAL_UART_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL UART Reception type definition
|
||||
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
|
||||
* This parameter can be a value of @ref UART_Reception_Type_Values :
|
||||
* HAL_UART_RECEPTION_STANDARD = 0x00U,
|
||||
* HAL_UART_RECEPTION_TOIDLE = 0x01U,
|
||||
*/
|
||||
typedef uint32_t HAL_UART_RxTypeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL UART Rx Event type definition
|
||||
* @note HAL UART Rx Event type value aims to identify which type of Event has occurred
|
||||
* leading to call of the RxEvent callback.
|
||||
* This parameter can be a value of @ref UART_RxEvent_Type_Values :
|
||||
* HAL_UART_RXEVENT_TC = 0x00U,
|
||||
* HAL_UART_RXEVENT_HT = 0x01U,
|
||||
* HAL_UART_RXEVENT_IDLE = 0x02U,
|
||||
*/
|
||||
typedef uint32_t HAL_UART_RxEventTypeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief UART handle Structure definition
|
||||
*/
|
||||
typedef struct __UART_HandleTypeDef
|
||||
{
|
||||
USART_TypeDef *Instance; /*!< UART registers base address */
|
||||
|
||||
UART_InitTypeDef Init; /*!< UART communication parameters */
|
||||
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< UART Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< UART Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
|
||||
|
||||
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
|
||||
|
||||
__IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_UART_StateTypeDef */
|
||||
|
||||
__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_UART_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< UART Error code */
|
||||
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */
|
||||
void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */
|
||||
void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */
|
||||
void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */
|
||||
void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */
|
||||
void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */
|
||||
void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
|
||||
void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
|
||||
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
|
||||
void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */
|
||||
|
||||
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
|
||||
} UART_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL UART Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */
|
||||
HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */
|
||||
HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */
|
||||
HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */
|
||||
HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */
|
||||
HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */
|
||||
HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */
|
||||
HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */
|
||||
HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */
|
||||
|
||||
HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */
|
||||
HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */
|
||||
|
||||
} HAL_UART_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL UART Callback pointer definition
|
||||
*/
|
||||
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
|
||||
typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
|
||||
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup UART_Exported_Constants UART Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UART_Error_Code UART Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */
|
||||
#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */
|
||||
#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */
|
||||
#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */
|
||||
#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_Word_Length UART Word Length
|
||||
* @{
|
||||
*/
|
||||
#define UART_WORDLENGTH_8B 0x00000000U
|
||||
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_Stop_Bits UART Number of Stop Bits
|
||||
* @{
|
||||
*/
|
||||
#define UART_STOPBITS_1 0x00000000U
|
||||
#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_Parity UART Parity
|
||||
* @{
|
||||
*/
|
||||
#define UART_PARITY_NONE 0x00000000U
|
||||
#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
|
||||
#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
|
||||
* @{
|
||||
*/
|
||||
#define UART_HWCONTROL_NONE 0x00000000U
|
||||
#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
|
||||
#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
|
||||
#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_Mode UART Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
|
||||
#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
|
||||
#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_State UART State
|
||||
* @{
|
||||
*/
|
||||
#define UART_STATE_DISABLE 0x00000000U
|
||||
#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_Over_Sampling UART Over Sampling
|
||||
* @{
|
||||
*/
|
||||
#define UART_OVERSAMPLING_16 0x00000000U
|
||||
#if defined(USART_CR1_OVER8)
|
||||
#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
|
||||
#endif /* USART_CR1_OVER8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
|
||||
* @{
|
||||
*/
|
||||
#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U
|
||||
#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_WakeUp_functions UART Wakeup Functions
|
||||
* @{
|
||||
*/
|
||||
#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U
|
||||
#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_Flags UART FLags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the SR register
|
||||
* @{
|
||||
*/
|
||||
#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
|
||||
#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
|
||||
#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
|
||||
#define UART_FLAG_TC ((uint32_t)USART_SR_TC)
|
||||
#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
|
||||
#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
|
||||
#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
|
||||
#define UART_FLAG_NE ((uint32_t)USART_SR_NE)
|
||||
#define UART_FLAG_FE ((uint32_t)USART_SR_FE)
|
||||
#define UART_FLAG_PE ((uint32_t)USART_SR_PE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_Interrupt_definition UART Interrupt Definitions
|
||||
* Elements values convention: 0xY000XXXX
|
||||
* - XXXX : Interrupt mask (16 bits) in the Y register
|
||||
* - Y : Interrupt source register (2bits)
|
||||
* - 0001: CR1 register
|
||||
* - 0010: CR2 register
|
||||
* - 0011: CR3 register
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
|
||||
#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
|
||||
#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
|
||||
#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
|
||||
#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
|
||||
|
||||
#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
|
||||
|
||||
#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
|
||||
#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_Reception_Type_Values UART Reception type values
|
||||
* @{
|
||||
*/
|
||||
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
|
||||
#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values
|
||||
* @{
|
||||
*/
|
||||
#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */
|
||||
#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */
|
||||
#define HAL_UART_RXEVENT_IDLE (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup UART_Exported_Macros UART Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset UART handle gstate & RxState
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* UART Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
|
||||
} while(0U)
|
||||
#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Flushes the UART DR register
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* UART Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
*/
|
||||
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
|
||||
|
||||
/** @brief Checks whether the specified UART flag is set or not.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* UART Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
|
||||
* @arg UART_FLAG_LBD: LIN Break detection flag
|
||||
* @arg UART_FLAG_TXE: Transmit data register empty flag
|
||||
* @arg UART_FLAG_TC: Transmission Complete flag
|
||||
* @arg UART_FLAG_RXNE: Receive data register not empty flag
|
||||
* @arg UART_FLAG_IDLE: Idle Line detection flag
|
||||
* @arg UART_FLAG_ORE: Overrun Error flag
|
||||
* @arg UART_FLAG_NE: Noise Error flag
|
||||
* @arg UART_FLAG_FE: Framing Error flag
|
||||
* @arg UART_FLAG_PE: Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the specified UART pending flag.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* UART Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
|
||||
* @arg UART_FLAG_LBD: LIN Break detection flag.
|
||||
* @arg UART_FLAG_TC: Transmission Complete flag.
|
||||
* @arg UART_FLAG_RXNE: Receive data register not empty flag.
|
||||
*
|
||||
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
|
||||
* error) and IDLE (Idle line detected) flags are cleared by software
|
||||
* sequence: a read operation to USART_SR register followed by a read
|
||||
* operation to USART_DR register.
|
||||
* @note RXNE flag can be also cleared by a read to the USART_DR register.
|
||||
* @note TC flag can be also cleared by software sequence: a read operation to
|
||||
* USART_SR register followed by a write operation to USART_DR register.
|
||||
* @note TXE flag is cleared only by a write to the USART_DR register.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
||||
|
||||
/** @brief Clears the UART PE pending flag.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* UART Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
tmpreg = (__HANDLE__)->Instance->SR; \
|
||||
tmpreg = (__HANDLE__)->Instance->DR; \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Clears the UART FE pending flag.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* UART Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clears the UART NE pending flag.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* UART Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clears the UART ORE pending flag.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* UART Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clears the UART IDLE pending flag.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* UART Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Enable the specified UART interrupt.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* UART Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @param __INTERRUPT__ specifies the UART interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg UART_IT_CTS: CTS change interrupt
|
||||
* @arg UART_IT_LBD: LIN Break detection interrupt
|
||||
* @arg UART_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg UART_IT_TC: Transmission complete interrupt
|
||||
* @arg UART_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg UART_IT_IDLE: Idle line detection interrupt
|
||||
* @arg UART_IT_PE: Parity Error interrupt
|
||||
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
|
||||
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
|
||||
|
||||
/** @brief Disable the specified UART interrupt.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* UART Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @param __INTERRUPT__ specifies the UART interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg UART_IT_CTS: CTS change interrupt
|
||||
* @arg UART_IT_LBD: LIN Break detection interrupt
|
||||
* @arg UART_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg UART_IT_TC: Transmission complete interrupt
|
||||
* @arg UART_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg UART_IT_IDLE: Idle line detection interrupt
|
||||
* @arg UART_IT_PE: Parity Error interrupt
|
||||
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
|
||||
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
|
||||
|
||||
/** @brief Checks whether the specified UART interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* UART Handle selects the USARTx or UARTy peripheral
|
||||
* (USART,UART availability and x,y values depending on device).
|
||||
* @param __IT__ specifies the UART interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
|
||||
* @arg UART_IT_LBD: LIN Break detection interrupt
|
||||
* @arg UART_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg UART_IT_TC: Transmission complete interrupt
|
||||
* @arg UART_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg UART_IT_IDLE: Idle line detection interrupt
|
||||
* @arg UART_IT_ERR: Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
|
||||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
|
||||
|
||||
/** @brief Enable CTS flow control
|
||||
* @note This macro allows to enable CTS hardware flow control for a given UART instance,
|
||||
* without need to call HAL_UART_Init() function.
|
||||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
|
||||
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
|
||||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
|
||||
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
|
||||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
|
||||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature).
|
||||
* It is used to select the USART peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
|
||||
do{ \
|
||||
ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
|
||||
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Disable CTS flow control
|
||||
* @note This macro allows to disable CTS hardware flow control for a given UART instance,
|
||||
* without need to call HAL_UART_Init() function.
|
||||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
|
||||
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
|
||||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
|
||||
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
|
||||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
|
||||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature).
|
||||
* It is used to select the USART peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
|
||||
do{ \
|
||||
ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
|
||||
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Enable RTS flow control
|
||||
* This macro allows to enable RTS hardware flow control for a given UART instance,
|
||||
* without need to call HAL_UART_Init() function.
|
||||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
|
||||
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
|
||||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
|
||||
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
|
||||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
|
||||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature).
|
||||
* It is used to select the USART peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
|
||||
do{ \
|
||||
ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
|
||||
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Disable RTS flow control
|
||||
* This macro allows to disable RTS hardware flow control for a given UART instance,
|
||||
* without need to call HAL_UART_Init() function.
|
||||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
|
||||
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
|
||||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
|
||||
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
|
||||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
|
||||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature).
|
||||
* It is used to select the USART peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
|
||||
do{ \
|
||||
ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
|
||||
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
|
||||
} while(0U)
|
||||
#if defined(USART_CR3_ONEBIT)
|
||||
|
||||
/** @brief Macro to enable the UART's one bit sample method
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
|
||||
|
||||
/** @brief Macro to disable the UART's one bit sample method
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
|
||||
&= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
|
||||
#endif /* UART_ONE_BIT_SAMPLE_Feature */
|
||||
|
||||
/** @brief Enable UART
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable UART
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup UART_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
|
||||
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
|
||||
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
|
||||
void HAL_UART_MspInit(UART_HandleTypeDef *huart);
|
||||
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
|
||||
pUART_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
|
||||
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
|
||||
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
|
||||
|
||||
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
|
||||
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
|
||||
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
|
||||
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
|
||||
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
|
||||
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
|
||||
void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
|
||||
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
|
||||
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
|
||||
|
||||
void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UART_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UART_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions **************************************************/
|
||||
HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart);
|
||||
uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup UART_Private_Constants UART Private Constants
|
||||
* @{
|
||||
*/
|
||||
/** @brief UART interruptions flag mask
|
||||
*
|
||||
*/
|
||||
#define UART_IT_MASK 0x0000FFFFU
|
||||
|
||||
#define UART_CR1_REG_INDEX 1U
|
||||
#define UART_CR2_REG_INDEX 2U
|
||||
#define UART_CR3_REG_INDEX 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup UART_Private_Macros UART Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
|
||||
((LENGTH) == UART_WORDLENGTH_9B))
|
||||
#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
|
||||
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
|
||||
((STOPBITS) == UART_STOPBITS_2))
|
||||
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
|
||||
((PARITY) == UART_PARITY_EVEN) || \
|
||||
((PARITY) == UART_PARITY_ODD))
|
||||
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
|
||||
(((CONTROL) == UART_HWCONTROL_NONE) || \
|
||||
((CONTROL) == UART_HWCONTROL_RTS) || \
|
||||
((CONTROL) == UART_HWCONTROL_CTS) || \
|
||||
((CONTROL) == UART_HWCONTROL_RTS_CTS))
|
||||
#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
|
||||
#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
|
||||
((STATE) == UART_STATE_ENABLE))
|
||||
#if defined(USART_CR1_OVER8)
|
||||
#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
|
||||
((SAMPLING) == UART_OVERSAMPLING_8))
|
||||
#endif /* USART_CR1_OVER8 */
|
||||
#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
|
||||
#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
|
||||
((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
|
||||
#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
|
||||
((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
|
||||
#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 4500000U)
|
||||
#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
|
||||
|
||||
#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
|
||||
#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
|
||||
#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U)\
|
||||
+ 50U) / 100U)
|
||||
/* UART BRR = mantissa + overflow + fraction
|
||||
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
|
||||
#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
|
||||
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
|
||||
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
|
||||
|
||||
#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
|
||||
#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
|
||||
#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U)\
|
||||
+ 50U) / 100U)
|
||||
/* UART BRR = mantissa + overflow + fraction
|
||||
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
|
||||
#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
|
||||
((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
|
||||
(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup UART_Private_Functions UART Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_UART_H */
|
||||
|
||||
648
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_usart.h
Normal file
648
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_usart.h
Normal file
@@ -0,0 +1,648 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_usart.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of USART HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_USART_H
|
||||
#define __STM32F1xx_HAL_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup USART_Exported_Types USART Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief USART Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (16 * (husart->Init.BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USART_Word_Length */
|
||||
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Mode */
|
||||
|
||||
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||
|
||||
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase */
|
||||
|
||||
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit */
|
||||
} USART_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
|
||||
HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
|
||||
HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
|
||||
HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||
HAL_USART_STATE_ERROR = 0x04U /*!< Error */
|
||||
} HAL_USART_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USART handle Structure definition
|
||||
*/
|
||||
typedef struct __USART_HandleTypeDef
|
||||
{
|
||||
USART_TypeDef *Instance; /*!< USART registers base address */
|
||||
|
||||
USART_InitTypeDef Init; /*!< Usart communication parameters */
|
||||
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< Usart Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to Usart Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< Usart Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< Usart Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< Usart Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_USART_StateTypeDef State; /*!< Usart communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< USART Error code */
|
||||
|
||||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
|
||||
void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */
|
||||
void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */
|
||||
void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */
|
||||
void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */
|
||||
void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */
|
||||
void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */
|
||||
void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */
|
||||
|
||||
void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */
|
||||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
|
||||
|
||||
} USART_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL USART Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */
|
||||
HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */
|
||||
HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */
|
||||
HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */
|
||||
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */
|
||||
HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */
|
||||
HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */
|
||||
|
||||
HAL_USART_MSPINIT_CB_ID = 0x07U, /*!< USART MspInit callback ID */
|
||||
HAL_USART_MSPDEINIT_CB_ID = 0x08U /*!< USART MspDeInit callback ID */
|
||||
|
||||
} HAL_USART_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL USART Callback pointer definition
|
||||
*/
|
||||
typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */
|
||||
|
||||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup USART_Exported_Constants USART Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Error_Code USART Error Code
|
||||
* @brief USART Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_USART_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_USART_ERROR_PE 0x00000001U /*!< Parity error */
|
||||
#define HAL_USART_ERROR_NE 0x00000002U /*!< Noise error */
|
||||
#define HAL_USART_ERROR_FE 0x00000004U /*!< Frame error */
|
||||
#define HAL_USART_ERROR_ORE 0x00000008U /*!< Overrun error */
|
||||
#define HAL_USART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
|
||||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_USART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Word_Length USART Word Length
|
||||
* @{
|
||||
*/
|
||||
#define USART_WORDLENGTH_8B 0x00000000U
|
||||
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
|
||||
* @{
|
||||
*/
|
||||
#define USART_STOPBITS_1 0x00000000U
|
||||
#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
|
||||
#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
|
||||
#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Parity USART Parity
|
||||
* @{
|
||||
*/
|
||||
#define USART_PARITY_NONE 0x00000000U
|
||||
#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
|
||||
#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Mode USART Mode
|
||||
* @{
|
||||
*/
|
||||
#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
|
||||
#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
|
||||
#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock USART Clock
|
||||
* @{
|
||||
*/
|
||||
#define USART_CLOCK_DISABLE 0x00000000U
|
||||
#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Polarity USART Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define USART_POLARITY_LOW 0x00000000U
|
||||
#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Phase USART Clock Phase
|
||||
* @{
|
||||
*/
|
||||
#define USART_PHASE_1EDGE 0x00000000U
|
||||
#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Last_Bit USART Last Bit
|
||||
* @{
|
||||
*/
|
||||
#define USART_LASTBIT_DISABLE 0x00000000U
|
||||
#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_NACK_State USART NACK State
|
||||
* @{
|
||||
*/
|
||||
#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
|
||||
#define USART_NACK_DISABLE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Flags USART Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the SR register
|
||||
* @{
|
||||
*/
|
||||
#define USART_FLAG_TXE ((uint32_t)USART_SR_TXE)
|
||||
#define USART_FLAG_TC ((uint32_t)USART_SR_TC)
|
||||
#define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
|
||||
#define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
|
||||
#define USART_FLAG_ORE ((uint32_t)USART_SR_ORE)
|
||||
#define USART_FLAG_NE ((uint32_t)USART_SR_NE)
|
||||
#define USART_FLAG_FE ((uint32_t)USART_SR_FE)
|
||||
#define USART_FLAG_PE ((uint32_t)USART_SR_PE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Interrupt_definition USART Interrupts Definition
|
||||
* Elements values convention: 0xY000XXXX
|
||||
* - XXXX : Interrupt mask in the XX register
|
||||
* - Y : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* @{
|
||||
*/
|
||||
#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
|
||||
#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
|
||||
#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
|
||||
#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
|
||||
#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
|
||||
#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup USART_Exported_Macros USART Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset USART handle state
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_USART_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
|
||||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Check whether the specified USART flag is set or not.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg USART_FLAG_TXE: Transmit data register empty flag
|
||||
* @arg USART_FLAG_TC: Transmission Complete flag
|
||||
* @arg USART_FLAG_RXNE: Receive data register not empty flag
|
||||
* @arg USART_FLAG_IDLE: Idle Line detection flag
|
||||
* @arg USART_FLAG_ORE: Overrun Error flag
|
||||
* @arg USART_FLAG_NE: Noise Error flag
|
||||
* @arg USART_FLAG_FE: Framing Error flag
|
||||
* @arg USART_FLAG_PE: Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the specified USART pending flags.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg USART_FLAG_TC: Transmission Complete flag.
|
||||
* @arg USART_FLAG_RXNE: Receive data register not empty flag.
|
||||
*
|
||||
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
|
||||
* error) and IDLE (Idle line detected) flags are cleared by software
|
||||
* sequence: a read operation to USART_SR register followed by a read
|
||||
* operation to USART_DR register.
|
||||
* @note RXNE flag can be also cleared by a read to the USART_DR register.
|
||||
* @note TC flag can be also cleared by software sequence: a read operation to
|
||||
* USART_SR register followed by a write operation to USART_DR register.
|
||||
* @note TXE flag is cleared only by a write to the USART_DR register.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
||||
|
||||
/** @brief Clear the USART PE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
tmpreg = (__HANDLE__)->Instance->SR; \
|
||||
tmpreg = (__HANDLE__)->Instance->DR; \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Clear the USART FE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the USART NE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the USART ORE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Clear the USART IDLE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
|
||||
|
||||
/** @brief Enables or disables the specified USART interrupts.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @param __INTERRUPT__ specifies the USART interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg USART_IT_TC: Transmission complete interrupt
|
||||
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg USART_IT_IDLE: Idle line detection interrupt
|
||||
* @arg USART_IT_PE: Parity Error interrupt
|
||||
* @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
|
||||
(((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
|
||||
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
|
||||
(((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
|
||||
|
||||
/** @brief Checks whether the specified USART interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @param __IT__ specifies the USART interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg USART_IT_TC: Transmission complete interrupt
|
||||
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg USART_IT_IDLE: Idle line detection interrupt
|
||||
* @arg USART_IT_ERR: Error interrupt
|
||||
* @arg USART_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \
|
||||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
|
||||
|
||||
/** @brief Macro to enable the USART's one bit sample method
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT)
|
||||
|
||||
/** @brief Macro to disable the USART's one bit sample method
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
|
||||
&= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
|
||||
|
||||
/** @brief Enable USART
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable USART
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup USART_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
|
||||
pUSART_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
|
||||
|
||||
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart);
|
||||
uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup USART_Private_Constants USART Private Constants
|
||||
* @{
|
||||
*/
|
||||
/** @brief USART interruptions flag mask
|
||||
*
|
||||
*/
|
||||
#define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
|
||||
USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
|
||||
|
||||
#define USART_CR1_REG_INDEX 1U
|
||||
#define USART_CR2_REG_INDEX 2U
|
||||
#define USART_CR3_REG_INDEX 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup USART_Private_Macros USART Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
|
||||
((NACK) == USART_NACK_DISABLE))
|
||||
|
||||
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
|
||||
((LASTBIT) == USART_LASTBIT_ENABLE))
|
||||
|
||||
#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || \
|
||||
((CPHA) == USART_PHASE_2EDGE))
|
||||
|
||||
#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || \
|
||||
((CPOL) == USART_POLARITY_HIGH))
|
||||
|
||||
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
|
||||
((CLOCK) == USART_CLOCK_ENABLE))
|
||||
|
||||
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
|
||||
((LENGTH) == USART_WORDLENGTH_9B))
|
||||
|
||||
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
|
||||
((STOPBITS) == USART_STOPBITS_0_5) || \
|
||||
((STOPBITS) == USART_STOPBITS_1_5) || \
|
||||
((STOPBITS) == USART_STOPBITS_2))
|
||||
|
||||
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
|
||||
((PARITY) == USART_PARITY_EVEN) || \
|
||||
((PARITY) == USART_PARITY_ODD))
|
||||
|
||||
#define IS_USART_MODE(MODE) ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00U) && ((MODE) != 0x00U))
|
||||
|
||||
#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 4500000U)
|
||||
|
||||
#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
|
||||
|
||||
#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
|
||||
|
||||
#define USART_DIVFRAQ(_PCLK_, _BAUD_) ((((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
|
||||
|
||||
/* UART BRR = mantissa + overflow + fraction
|
||||
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF0) << 1) + (UART DIVFRAQ & 0x0FU) */
|
||||
|
||||
#define USART_BRR(_PCLK_, _BAUD_) (((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
|
||||
((USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U) << 1U)) + \
|
||||
(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @addtogroup USART_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_USART_H */
|
||||
|
||||
299
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_wwdg.h
Normal file
299
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_wwdg.h
Normal file
@@ -0,0 +1,299 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of WWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_WWDG_H
|
||||
#define STM32F1xx_HAL_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Types WWDG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief WWDG Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
|
||||
This parameter can be a value of @ref WWDG_Prescaler */
|
||||
|
||||
uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
|
||||
This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
|
||||
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
|
||||
This parameter can be a value of @ref WWDG_EWI_Mode */
|
||||
|
||||
} WWDG_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief WWDG handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __WWDG_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
{
|
||||
WWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
|
||||
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
|
||||
|
||||
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
} WWDG_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL WWDG common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
|
||||
HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
|
||||
} HAL_WWDG_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL WWDG Callback pointer definition
|
||||
*/
|
||||
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
|
||||
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Flag_definition WWDG Flag definition
|
||||
* @brief WWDG Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Prescaler WWDG Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
|
||||
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
|
||||
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
|
||||
#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
|
||||
#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Private_Macros WWDG Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
|
||||
((__PRESCALER__) == WWDG_PRESCALER_2) || \
|
||||
((__PRESCALER__) == WWDG_PRESCALER_4) || \
|
||||
((__PRESCALER__) == WWDG_PRESCALER_8))
|
||||
|
||||
#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
|
||||
|
||||
#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
|
||||
|
||||
#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
|
||||
((__MODE__) == WWDG_EWI_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the WWDG peripheral.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
|
||||
|
||||
/**
|
||||
* @brief Enable the WWDG early wakeup interrupt.
|
||||
* @param __HANDLE__: WWDG handle
|
||||
* @param __INTERRUPT__ specifies the interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_IT_EWI: Early wakeup interrupt
|
||||
* @note Once enabled this interrupt cannot be disabled except by a system reset.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the selected WWDG interrupt has occurred or not.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __INTERRUPT__ specifies the it to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
|
||||
* @retval The new state of WWDG_FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
|
||||
|
||||
/** @brief Clear the WWDG interrupt pending bits.
|
||||
* bits to clear the selected interrupt pending bits.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||
*/
|
||||
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified WWDG flag is set or not.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||
* @retval The new state of WWDG_FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the WWDG's pending flags.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
||||
|
||||
/** @brief Check whether the specified WWDG interrupt source is enabled or not.
|
||||
* @param __HANDLE__ WWDG Handle.
|
||||
* @param __INTERRUPT__ specifies the WWDG interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
|
||||
* @retval state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup WWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
|
||||
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
|
||||
pWWDG_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ******************************************************/
|
||||
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
|
||||
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
|
||||
void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_WWDG_H */
|
||||
|
||||
3929
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h
Normal file
3929
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h
Normal file
File diff suppressed because it is too large
Load Diff
201
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_crc.h
Normal file
201
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_crc.h
Normal file
@@ -0,0 +1,201 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_ll_crc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_LL_CRC_H
|
||||
#define STM32F1xx_LL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(CRC)
|
||||
|
||||
/** @defgroup CRC_LL CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in CRC register
|
||||
* @param __INSTANCE__ CRC Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
|
||||
|
||||
/**
|
||||
* @brief Read a value in CRC register
|
||||
* @param __INSTANCE__ CRC Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reset the CRC calculation unit.
|
||||
* @note If Programmable Initial CRC value feature
|
||||
* is available, also set the Data Register to the value stored in the
|
||||
* CRC_INIT register, otherwise, reset Data Register to its default value.
|
||||
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
|
||||
* @param CRCx CRC Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
|
||||
{
|
||||
SET_BIT(CRCx->CR, CRC_CR_RESET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EF_Data_Management Data_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write given 32-bit data to the CRC calculator
|
||||
* @rmtoll DR DR LL_CRC_FeedData32
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
|
||||
{
|
||||
WRITE_REG(CRCx->DR, InData);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current CRC calculation result. 32 bits value is returned.
|
||||
* @rmtoll DR DR LL_CRC_ReadData32
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->DR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return data stored in the Independent Data(IDR) register.
|
||||
* @note This register can be used as a temporary storage location for one byte.
|
||||
* @rmtoll IDR IDR LL_CRC_Read_IDR
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->IDR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store data in the Independent Data(IDR) register.
|
||||
* @note This register can be used as a temporary storage location for one byte.
|
||||
* @rmtoll IDR IDR LL_CRC_Write_IDR
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
|
||||
{
|
||||
*((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(CRC) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_LL_CRC_H */
|
||||
1348
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dac.h
Normal file
1348
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dac.h
Normal file
File diff suppressed because it is too large
Load Diff
969
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h
Normal file
969
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h
Normal file
@@ -0,0 +1,969 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_ll_fsmc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FSMC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_LL_FSMC_H
|
||||
#define STM32F1xx_LL_FSMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FSMC_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FSMC_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined(FSMC_BANK1)
|
||||
|
||||
#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
|
||||
((__BANK__) == FSMC_NORSRAM_BANK2) || \
|
||||
((__BANK__) == FSMC_NORSRAM_BANK3) || \
|
||||
((__BANK__) == FSMC_NORSRAM_BANK4))
|
||||
#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
|
||||
((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
|
||||
#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
|
||||
((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
|
||||
((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
|
||||
#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
|
||||
((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
|
||||
((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
|
||||
#define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \
|
||||
((__SIZE__) == FSMC_PAGE_SIZE_128) || \
|
||||
((__SIZE__) == FSMC_PAGE_SIZE_256) || \
|
||||
((__SIZE__) == FSMC_PAGE_SIZE_512) || \
|
||||
((__SIZE__) == FSMC_PAGE_SIZE_1024))
|
||||
#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
|
||||
((__MODE__) == FSMC_ACCESS_MODE_B) || \
|
||||
((__MODE__) == FSMC_ACCESS_MODE_C) || \
|
||||
((__MODE__) == FSMC_ACCESS_MODE_D))
|
||||
#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
|
||||
((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
|
||||
#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
|
||||
((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
|
||||
#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
|
||||
((__MODE__) == FSMC_WRAP_MODE_ENABLE))
|
||||
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
|
||||
((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
|
||||
#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
|
||||
((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
|
||||
#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
|
||||
((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
|
||||
#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
|
||||
((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
|
||||
#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
|
||||
((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
|
||||
#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
|
||||
#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
|
||||
((__BURST__) == FSMC_WRITE_BURST_ENABLE))
|
||||
#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
|
||||
((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
|
||||
#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
|
||||
#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
|
||||
#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
|
||||
#define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
|
||||
#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
|
||||
#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
|
||||
#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
|
||||
#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
|
||||
|
||||
#endif /* FSMC_BANK1 */
|
||||
#if defined(FSMC_BANK3)
|
||||
|
||||
#define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3)
|
||||
#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
|
||||
((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
|
||||
#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
|
||||
((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
|
||||
#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
|
||||
((__STATE__) == FSMC_NAND_ECC_ENABLE))
|
||||
|
||||
#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
|
||||
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
|
||||
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
|
||||
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
|
||||
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
|
||||
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
|
||||
#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
|
||||
#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
|
||||
#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
|
||||
#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
|
||||
#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
|
||||
#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
|
||||
#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
|
||||
|
||||
#endif /* FSMC_BANK3 */
|
||||
#if defined(FSMC_BANK4)
|
||||
#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
|
||||
|
||||
#endif /* FSMC_BANK4 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(FSMC_BANK1)
|
||||
#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
|
||||
#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
|
||||
#endif /* FSMC_BANK1 */
|
||||
#if defined(FSMC_BANK3)
|
||||
#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
|
||||
#endif /* FSMC_BANK3 */
|
||||
#if defined(FSMC_BANK4)
|
||||
#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
|
||||
#endif /* FSMC_BANK4 */
|
||||
|
||||
#if defined(FSMC_BANK1)
|
||||
#define FSMC_NORSRAM_DEVICE FSMC_Bank1
|
||||
#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
|
||||
#endif /* FSMC_BANK1 */
|
||||
#if defined(FSMC_BANK3)
|
||||
#define FSMC_NAND_DEVICE FSMC_Bank2_3
|
||||
#endif /* FSMC_BANK3 */
|
||||
#if defined(FSMC_BANK4)
|
||||
#define FSMC_PCCARD_DEVICE FSMC_Bank4
|
||||
#endif /* FSMC_BANK4 */
|
||||
|
||||
#if defined(FSMC_BANK1)
|
||||
/**
|
||||
* @brief FSMC NORSRAM Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
|
||||
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
|
||||
|
||||
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
|
||||
multiplexed on the data bus or not.
|
||||
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing*/
|
||||
|
||||
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
|
||||
the corresponding memory device.
|
||||
This parameter can be a value of @ref FSMC_Memory_Type */
|
||||
|
||||
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
|
||||
|
||||
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
|
||||
valid only with synchronous burst Flash memories.
|
||||
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
|
||||
|
||||
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
|
||||
the Flash memory in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
|
||||
|
||||
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
|
||||
memory, valid only when accessing Flash memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wrap_Mode */
|
||||
|
||||
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
|
||||
clock cycle before the wait state or during the wait state,
|
||||
valid only when accessing memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Timing */
|
||||
|
||||
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device
|
||||
by the FSMC.
|
||||
This parameter can be a value of @ref FSMC_Write_Operation */
|
||||
|
||||
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
|
||||
signal, valid for Flash memory access in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal */
|
||||
|
||||
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
|
||||
This parameter can be a value of @ref FSMC_Extended_Mode */
|
||||
|
||||
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
|
||||
valid only with asynchronous Flash memories.
|
||||
This parameter can be a value of @ref FSMC_AsynchronousWait */
|
||||
|
||||
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
|
||||
This parameter can be a value of @ref FSMC_Write_Burst */
|
||||
|
||||
|
||||
uint32_t PageSize; /*!< Specifies the memory page size.
|
||||
This parameter can be a value of @ref FSMC_Page_Size */
|
||||
} FSMC_NORSRAM_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NORSRAM Timing parameters structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address setup time.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
|
||||
@note This parameter is not used with synchronous NOR Flash memories. */
|
||||
|
||||
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address hold time.
|
||||
This parameter can be a value between Min_Data = 1 and Max_Data = 15.
|
||||
@note This parameter is not used with synchronous NOR Flash memories. */
|
||||
|
||||
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the data setup time.
|
||||
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
|
||||
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
|
||||
NOR Flash memories. */
|
||||
|
||||
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the bus turnaround.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
|
||||
@note This parameter is only used for multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
|
||||
HCLK cycles. This parameter can be a value between Min_Data = 2 and
|
||||
Max_Data = 16.
|
||||
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
|
||||
accesses. */
|
||||
|
||||
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
|
||||
to the memory before getting the first data.
|
||||
The parameter value depends on the memory type as shown below:
|
||||
- It must be set to 0 in case of a CRAM
|
||||
- It is don't care in asynchronous NOR, SRAM or ROM accesses
|
||||
- It may assume a value between Min_Data = 2 and Max_Data = 17
|
||||
in NOR Flash memories with synchronous burst mode enable */
|
||||
|
||||
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
|
||||
This parameter can be a value of @ref FSMC_Access_Mode */
|
||||
} FSMC_NORSRAM_TimingTypeDef;
|
||||
#endif /* FSMC_BANK1 */
|
||||
|
||||
#if defined(FSMC_BANK3)
|
||||
/**
|
||||
* @brief FSMC NAND Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
|
||||
This parameter can be a value of @ref FSMC_NAND_Bank */
|
||||
|
||||
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
|
||||
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||
|
||||
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be any value of @ref FSMC_NAND_Data_Width */
|
||||
|
||||
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
|
||||
This parameter can be any value of @ref FSMC_ECC */
|
||||
|
||||
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
|
||||
This parameter can be any value of @ref FSMC_ECC_Page_Size */
|
||||
|
||||
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
|
||||
|
||||
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
|
||||
} FSMC_NAND_InitTypeDef;
|
||||
#endif /* FSMC_BANK3 */
|
||||
|
||||
#if defined(FSMC_BANK3) || defined(FSMC_BANK4)
|
||||
/**
|
||||
* @brief FSMC NAND Timing parameters structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
|
||||
the command assertion for NAND-Flash read or write access
|
||||
to common/Attribute or I/O memory space (depending on
|
||||
the memory space timing to be configured).
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
|
||||
|
||||
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
|
||||
command for NAND-Flash read or write access to
|
||||
common/Attribute or I/O memory space (depending on the
|
||||
memory space timing to be configured).
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
|
||||
|
||||
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
|
||||
(and data for write access) after the command de-assertion
|
||||
for NAND-Flash read or write access to common/Attribute
|
||||
or I/O memory space (depending on the memory space timing
|
||||
to be configured).
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
|
||||
|
||||
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
|
||||
data bus is kept in HiZ after the start of a NAND-Flash
|
||||
write access to common/Attribute or I/O memory space (depending
|
||||
on the memory space timing to be configured).
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
|
||||
} FSMC_NAND_PCC_TimingTypeDef;
|
||||
#endif /* FSMC_BANK3 */
|
||||
|
||||
#if defined(FSMC_BANK4)
|
||||
/**
|
||||
* @brief FSMC PCCARD Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
|
||||
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||
|
||||
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
|
||||
|
||||
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
|
||||
} FSMC_PCCARD_InitTypeDef;
|
||||
#endif /* FSMC_BANK4 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants
|
||||
* @{
|
||||
*/
|
||||
#if defined(FSMC_BANK1)
|
||||
|
||||
/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NORSRAM_BANK1 (0x00000000U)
|
||||
#define FSMC_NORSRAM_BANK2 (0x00000002U)
|
||||
#define FSMC_NORSRAM_BANK3 (0x00000004U)
|
||||
#define FSMC_NORSRAM_BANK4 (0x00000006U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
|
||||
#define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Memory_Type FSMC Memory Type
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_MEMORY_TYPE_SRAM (0x00000000U)
|
||||
#define FSMC_MEMORY_TYPE_PSRAM (0x00000004U)
|
||||
#define FSMC_MEMORY_TYPE_NOR (0x00000008U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
|
||||
#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
|
||||
#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
|
||||
#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
|
||||
#define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
|
||||
#define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WRAP_MODE_DISABLE (0x00000000U)
|
||||
#define FSMC_WRAP_MODE_ENABLE (0x00000400U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
|
||||
#define FSMC_WAIT_TIMING_DURING_WS (0x00000800U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Write_Operation FSMC Write Operation
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WRITE_OPERATION_DISABLE (0x00000000U)
|
||||
#define FSMC_WRITE_OPERATION_ENABLE (0x00001000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U)
|
||||
#define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_EXTENDED_MODE_DISABLE (0x00000000U)
|
||||
#define FSMC_EXTENDED_MODE_ENABLE (0x00004000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
|
||||
#define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Page_Size FSMC Page Size
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_PAGE_SIZE_NONE (0x00000000U)
|
||||
#define FSMC_PAGE_SIZE_128 (0x00010000U)
|
||||
#define FSMC_PAGE_SIZE_256 (0x00020000U)
|
||||
#define FSMC_PAGE_SIZE_512 (0x00030000U)
|
||||
#define FSMC_PAGE_SIZE_1024 (0x00040000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Write_Burst FSMC Write Burst
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WRITE_BURST_DISABLE (0x00000000U)
|
||||
#define FSMC_WRITE_BURST_ENABLE (0x00080000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Continous_Clock FSMC Continuous Clock
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
|
||||
#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Access_Mode FSMC Access Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_ACCESS_MODE_A (0x00000000U)
|
||||
#define FSMC_ACCESS_MODE_B (0x10000000U)
|
||||
#define FSMC_ACCESS_MODE_C (0x20000000U)
|
||||
#define FSMC_ACCESS_MODE_D (0x30000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK1 */
|
||||
|
||||
#if defined(FSMC_BANK3) || defined(FSMC_BANK4)
|
||||
|
||||
/** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_BANK2 (0x00000010U)
|
||||
#define FSMC_NAND_BANK3 (0x00000100U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_feature FSMC Wait feature
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U)
|
||||
#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
|
||||
* @{
|
||||
*/
|
||||
#if defined(FSMC_BANK4)
|
||||
#define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U)
|
||||
#endif /* FSMC_BANK4 */
|
||||
#define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U)
|
||||
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_ECC FSMC ECC
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_ECC_DISABLE (0x00000000U)
|
||||
#define FSMC_NAND_ECC_ENABLE (0x00000040U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK3 || FSMC_Bank4 */
|
||||
|
||||
|
||||
/** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#if defined(FSMC_BANK3) || defined(FSMC_BANK4)
|
||||
#define FSMC_IT_RISING_EDGE (0x00000008U)
|
||||
#define FSMC_IT_LEVEL (0x00000010U)
|
||||
#define FSMC_IT_FALLING_EDGE (0x00000020U)
|
||||
#endif /* FSMC_BANK3 || FSMC_Bank4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition
|
||||
* @{
|
||||
*/
|
||||
#if defined(FSMC_BANK3) || defined(FSMC_BANK4)
|
||||
#define FSMC_FLAG_RISING_EDGE (0x00000001U)
|
||||
#define FSMC_FLAG_LEVEL (0x00000002U)
|
||||
#define FSMC_FLAG_FALLING_EDGE (0x00000004U)
|
||||
#define FSMC_FLAG_FEMPT (0x00000040U)
|
||||
#endif /* FSMC_BANK3 || FSMC_Bank4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined(FSMC_BANK1)
|
||||
/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros
|
||||
* @brief macros to handle NOR device enable/disable and read/write operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the NORSRAM device access.
|
||||
* @param __INSTANCE__ FSMC_NORSRAM Instance
|
||||
* @param __BANK__ FSMC_NORSRAM Bank
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
|
||||
|= FSMC_BCRx_MBKEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the NORSRAM device access.
|
||||
* @param __INSTANCE__ FSMC_NORSRAM Instance
|
||||
* @param __BANK__ FSMC_NORSRAM Bank
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
|
||||
&= ~FSMC_BCRx_MBKEN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK1 */
|
||||
|
||||
#if defined(FSMC_BANK3)
|
||||
/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
|
||||
* @brief macros to handle NAND device enable/disable
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the NAND device access.
|
||||
* @param __INSTANCE__ FSMC_NAND Instance
|
||||
* @param __BANK__ FSMC_NAND Bank
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \
|
||||
((__INSTANCE__)->PCR2 |= FSMC_PCRx_PBKEN) : \
|
||||
((__INSTANCE__)->PCR3 |= FSMC_PCRx_PBKEN))
|
||||
|
||||
/**
|
||||
* @brief Disable the NAND device access.
|
||||
* @param __INSTANCE__ FSMC_NAND Instance
|
||||
* @param __BANK__ FSMC_NAND Bank
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \
|
||||
CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN) : \
|
||||
CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK3 */
|
||||
|
||||
#if defined(FSMC_BANK4)
|
||||
/** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros
|
||||
* @brief macros to handle PCCARD read/write operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the PCCARD device access.
|
||||
* @param __INSTANCE__ FSMC_PCCARD Instance
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCRx_PBKEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the PCCARD device access.
|
||||
* @param __INSTANCE__ FSMC_PCCARD Instance
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCRx_PBKEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FSMC_BANK4 */
|
||||
#if defined(FSMC_BANK3)
|
||||
/** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt
|
||||
* @brief macros to handle NAND interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the NAND device interrupt.
|
||||
* @param __INSTANCE__ FSMC_NAND instance
|
||||
* @param __BANK__ FSMC_NAND Bank
|
||||
* @param __INTERRUPT__ FSMC_NAND interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
||||
* @arg FSMC_IT_LEVEL: Interrupt level.
|
||||
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \
|
||||
((__INSTANCE__)->SR2 |= (__INTERRUPT__)) : \
|
||||
((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Disable the NAND device interrupt.
|
||||
* @param __INSTANCE__ FSMC_NAND Instance
|
||||
* @param __BANK__ FSMC_NAND Bank
|
||||
* @param __INTERRUPT__ FSMC_NAND interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
||||
* @arg FSMC_IT_LEVEL: Interrupt level.
|
||||
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \
|
||||
((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)) : \
|
||||
((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Get flag status of the NAND device.
|
||||
* @param __INSTANCE__ FSMC_NAND Instance
|
||||
* @param __BANK__ FSMC_NAND Bank
|
||||
* @param __FLAG__ FSMC_NAND flag
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
||||
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
||||
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
||||
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \
|
||||
(((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)) : \
|
||||
(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear flag status of the NAND device.
|
||||
* @param __INSTANCE__ FSMC_NAND Instance
|
||||
* @param __BANK__ FSMC_NAND Bank
|
||||
* @param __FLAG__ FSMC_NAND flag
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
||||
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
||||
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
||||
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \
|
||||
((__INSTANCE__)->SR2 &= ~(__FLAG__)) : \
|
||||
((__INSTANCE__)->SR3 &= ~(__FLAG__)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK3 */
|
||||
|
||||
#if defined(FSMC_BANK4)
|
||||
/** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt
|
||||
* @brief macros to handle PCCARD interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the PCCARD device interrupt.
|
||||
* @param __INSTANCE__ FSMC_PCCARD instance
|
||||
* @param __INTERRUPT__ FSMC_PCCARD interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
||||
* @arg FSMC_IT_LEVEL: Interrupt level.
|
||||
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the PCCARD device interrupt.
|
||||
* @param __INSTANCE__ FSMC_PCCARD instance
|
||||
* @param __INTERRUPT__ FSMC_PCCARD interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
||||
* @arg FSMC_IT_LEVEL: Interrupt level.
|
||||
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Get flag status of the PCCARD device.
|
||||
* @param __INSTANCE__ FSMC_PCCARD instance
|
||||
* @param __FLAG__ FSMC_PCCARD flag
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
||||
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
||||
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
||||
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear flag status of the PCCARD device.
|
||||
* @param __INSTANCE__ FSMC_PCCARD instance
|
||||
* @param __FLAG__ FSMC_PCCARD flag
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
||||
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
||||
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
||||
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK4 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(FSMC_BANK1)
|
||||
/** @defgroup FSMC_LL_NORSRAM NOR SRAM
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
|
||||
const FSMC_NORSRAM_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
|
||||
const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
|
||||
const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
|
||||
uint32_t ExtendedMode);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
|
||||
FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK1 */
|
||||
|
||||
#if defined(FSMC_BANK3)
|
||||
/** @defgroup FSMC_LL_NAND NAND
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, const FSMC_NAND_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
|
||||
const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
|
||||
const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
|
||||
uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK3 */
|
||||
|
||||
#if defined(FSMC_BANK4)
|
||||
/** @defgroup FSMC_LL_PCCARD PCCARD
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, const FSMC_PCCARD_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
|
||||
const FSMC_NAND_PCC_TimingTypeDef *Timing);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
|
||||
const FSMC_NAND_PCC_TimingTypeDef *Timing);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
|
||||
const FSMC_NAND_PCC_TimingTypeDef *Timing);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK4 */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_LL_FSMC_H */
|
||||
1782
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_i2c.h
Normal file
1782
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_i2c.h
Normal file
File diff suppressed because it is too large
Load Diff
1000
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h
Normal file
1000
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h
Normal file
File diff suppressed because it is too large
Load Diff
1135
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h
Normal file
1135
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h
Normal file
File diff suppressed because it is too large
Load Diff
1951
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h
Normal file
1951
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h
Normal file
File diff suppressed because it is too large
Load Diff
2569
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h
Normal file
2569
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h
Normal file
File diff suppressed because it is too large
Load Diff
641
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h
Normal file
641
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h
Normal file
@@ -0,0 +1,641 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_ll_usb.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of USB Low Layer HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_LL_USB_H
|
||||
#define STM32F1xx_LL_USB_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
#if defined (USB) || defined (USB_OTG_FS)
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USB_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
#ifndef HAL_USB_TIMEOUT
|
||||
#define HAL_USB_TIMEOUT 0xF000000U
|
||||
#endif /* define HAL_USB_TIMEOUT */
|
||||
|
||||
#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS
|
||||
#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U
|
||||
#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */
|
||||
|
||||
/**
|
||||
* @brief USB Mode definition
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
USB_DEVICE_MODE = 0,
|
||||
USB_HOST_MODE = 1,
|
||||
USB_DRD_MODE = 2
|
||||
} USB_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief URB States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
URB_IDLE = 0,
|
||||
URB_DONE,
|
||||
URB_NOTREADY,
|
||||
URB_NYET,
|
||||
URB_ERROR,
|
||||
URB_STALL
|
||||
} USB_URBStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Host channel States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HC_IDLE = 0,
|
||||
HC_XFRC,
|
||||
HC_HALTED,
|
||||
HC_ACK,
|
||||
HC_NAK,
|
||||
HC_NYET,
|
||||
HC_STALL,
|
||||
HC_XACTERR,
|
||||
HC_BBLERR,
|
||||
HC_DATATGLERR
|
||||
} USB_HCStateTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB Instance Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t dev_endpoints; /*!< Device Endpoints number.
|
||||
This parameter depends on the used USB core.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
#if defined (USB_OTG_FS)
|
||||
uint8_t Host_channels; /*!< Host Channels number.
|
||||
This parameter Depends on the used USB core.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
uint8_t dma_enable; /*!< USB DMA state.
|
||||
If DMA is not supported this parameter shall be set by default to zero */
|
||||
|
||||
uint8_t speed; /*!< USB Core speed.
|
||||
This parameter can be any value of @ref PCD_Speed/HCD_Speed
|
||||
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
|
||||
|
||||
uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
|
||||
|
||||
uint8_t phy_itface; /*!< Select the used PHY interface.
|
||||
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
|
||||
|
||||
uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
|
||||
|
||||
uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */
|
||||
|
||||
uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */
|
||||
|
||||
uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */
|
||||
|
||||
#if defined (USB_OTG_FS)
|
||||
uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
|
||||
|
||||
uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
|
||||
|
||||
uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
} USB_CfgTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t num; /*!< Endpoint number
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint8_t is_in; /*!< Endpoint direction
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t is_stall; /*!< Endpoint stall condition
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
#if defined (USB_OTG_FS)
|
||||
uint8_t is_iso_incomplete; /*!< Endpoint isoc condition
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
uint8_t type; /*!< Endpoint type
|
||||
This parameter can be any value of @ref USB_LL_EP_Type */
|
||||
|
||||
uint8_t data_pid_start; /*!< Initial data PID
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
#if defined (USB)
|
||||
uint16_t pmaadress; /*!< PMA Address
|
||||
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
|
||||
|
||||
uint16_t pmaaddr0; /*!< PMA Address0
|
||||
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
|
||||
|
||||
uint16_t pmaaddr1; /*!< PMA Address1
|
||||
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
|
||||
|
||||
uint8_t doublebuffer; /*!< Double buffer enable
|
||||
This parameter can be 0 or 1 */
|
||||
#endif /* defined (USB) */
|
||||
|
||||
uint32_t maxpacket; /*!< Endpoint Max packet size
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
||||
|
||||
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
|
||||
|
||||
uint32_t xfer_len; /*!< Current transfer length */
|
||||
|
||||
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
|
||||
|
||||
#if defined (USB_OTG_FS)
|
||||
uint8_t even_odd_frame; /*!< IFrame parity
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint16_t tx_fifo_num; /*!< Transmission FIFO number
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
|
||||
|
||||
uint32_t xfer_size; /*!< requested transfer size */
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
#if defined (USB)
|
||||
uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
|
||||
|
||||
uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
|
||||
#endif /* defined (USB) */
|
||||
} USB_EPTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t dev_addr; /*!< USB device address.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
|
||||
|
||||
uint8_t ch_num; /*!< Host channel number.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint8_t ep_num; /*!< Endpoint number.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint8_t ep_is_in; /*!< Endpoint direction
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t speed; /*!< USB Host Channel speed.
|
||||
This parameter can be any value of @ref HCD_Device_Speed:
|
||||
(HCD_DEVICE_SPEED_xxx) */
|
||||
|
||||
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
|
||||
|
||||
uint8_t hub_port_nbr; /*!< USB HUB port number */
|
||||
uint8_t hub_addr; /*!< USB HUB address */
|
||||
|
||||
uint8_t ep_type; /*!< Endpoint Type.
|
||||
This parameter can be any value of @ref USB_LL_EP_Type */
|
||||
|
||||
uint16_t max_packet; /*!< Endpoint Max packet size.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
||||
|
||||
uint8_t data_pid; /*!< Initial data PID.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
|
||||
|
||||
uint32_t XferSize; /*!< OTG Channel transfer size. */
|
||||
|
||||
uint32_t xfer_len; /*!< Current transfer length. */
|
||||
|
||||
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
|
||||
|
||||
uint8_t toggle_in; /*!< IN transfer current toggle flag.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t toggle_out; /*!< OUT transfer current toggle flag
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
|
||||
|
||||
uint32_t ErrCnt; /*!< Host channel error count. */
|
||||
|
||||
USB_URBStateTypeDef urb_state; /*!< URB state.
|
||||
This parameter can be any value of @ref USB_URBStateTypeDef */
|
||||
|
||||
USB_HCStateTypeDef state; /*!< Host Channel state.
|
||||
This parameter can be any value of @ref USB_HCStateTypeDef */
|
||||
} USB_HCTypeDef;
|
||||
|
||||
#if defined (USB_OTG_FS)
|
||||
typedef USB_ModeTypeDef USB_OTG_ModeTypeDef;
|
||||
typedef USB_CfgTypeDef USB_OTG_CfgTypeDef;
|
||||
typedef USB_EPTypeDef USB_OTG_EPTypeDef;
|
||||
typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef;
|
||||
typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef;
|
||||
typedef USB_HCTypeDef USB_OTG_HCTypeDef;
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PCD_Exported_Constants PCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (USB_OTG_FS)
|
||||
/** @defgroup USB_OTG_CORE VERSION ID
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_CORE_ID_300A 0x4F54300AU
|
||||
#define USB_OTG_CORE_ID_310A 0x4F54310AU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_Core_Mode_ USB Core Mode
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_MODE_DEVICE 0U
|
||||
#define USB_OTG_MODE_HOST 1U
|
||||
#define USB_OTG_MODE_DRD 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_SPEED_FULL 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_EMBEDDED_PHY 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
|
||||
* @{
|
||||
*/
|
||||
#ifndef USBD_FS_TRDT_VALUE
|
||||
#define USBD_FS_TRDT_VALUE 5U
|
||||
#define USBD_DEFAULT_TRDT_VALUE 9U
|
||||
#endif /* USBD_HS_TRDT_VALUE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
|
||||
#define USB_OTG_MAX_EP0_SIZE 64U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
|
||||
* @{
|
||||
*/
|
||||
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
|
||||
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
|
||||
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
|
||||
* @{
|
||||
*/
|
||||
#define DCFG_FRAME_INTERVAL_80 0U
|
||||
#define DCFG_FRAME_INTERVAL_85 1U
|
||||
#define DCFG_FRAME_INTERVAL_90 2U
|
||||
#define DCFG_FRAME_INTERVAL_95 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
|
||||
* @{
|
||||
*/
|
||||
#define EP_MPS_64 0U
|
||||
#define EP_MPS_32 1U
|
||||
#define EP_MPS_16 2U
|
||||
#define EP_MPS_8 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
|
||||
* @{
|
||||
*/
|
||||
#define EP_TYPE_CTRL 0U
|
||||
#define EP_TYPE_ISOC 1U
|
||||
#define EP_TYPE_BULK 2U
|
||||
#define EP_TYPE_INTR 3U
|
||||
#define EP_TYPE_MSK 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
|
||||
* @{
|
||||
*/
|
||||
#define EP_SPEED_LOW 0U
|
||||
#define EP_SPEED_FULL 1U
|
||||
#define EP_SPEED_HIGH 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type
|
||||
* @{
|
||||
*/
|
||||
#define HC_PID_DATA0 0U
|
||||
#define HC_PID_DATA2 1U
|
||||
#define HC_PID_DATA1 2U
|
||||
#define HC_PID_SETUP 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL Device Speed
|
||||
* @{
|
||||
*/
|
||||
#define USBD_FS_SPEED 2U
|
||||
#define USBH_FSLS_SPEED 1U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USB_OTG_FS)
|
||||
/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
|
||||
* @{
|
||||
*/
|
||||
#define STS_GOUT_NAK 1U
|
||||
#define STS_DATA_UPDT 2U
|
||||
#define STS_XFER_COMP 3U
|
||||
#define STS_SETUP_COMP 4U
|
||||
#define STS_SETUP_UPDT 6U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
|
||||
* @{
|
||||
*/
|
||||
#define HCFG_30_60_MHZ 0U
|
||||
#define HCFG_48_MHZ 1U
|
||||
#define HCFG_6_MHZ 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines
|
||||
* @{
|
||||
*/
|
||||
#define HFIR_6_MHZ 6000U
|
||||
#define HFIR_60_MHZ 60000U
|
||||
#define HFIR_48_MHZ 48000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
|
||||
* @{
|
||||
*/
|
||||
#define HPRT0_PRTSPD_HIGH_SPEED 0U
|
||||
#define HPRT0_PRTSPD_FULL_SPEED 1U
|
||||
#define HPRT0_PRTSPD_LOW_SPEED 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define HCCHAR_CTRL 0U
|
||||
#define HCCHAR_ISOC 1U
|
||||
#define HCCHAR_BULK 2U
|
||||
#define HCCHAR_INTR 3U
|
||||
|
||||
#define GRXSTS_PKTSTS_IN 2U
|
||||
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
|
||||
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
|
||||
#define GRXSTS_PKTSTS_CH_HALTED 7U
|
||||
|
||||
#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU
|
||||
|
||||
#define HC_MAX_PKT_CNT 256U
|
||||
|
||||
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
|
||||
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
|
||||
|
||||
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
|
||||
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
|
||||
+ USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
|
||||
|
||||
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
|
||||
+ USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
|
||||
|
||||
#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
|
||||
|
||||
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
|
||||
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
|
||||
+ USB_OTG_HOST_CHANNEL_BASE\
|
||||
+ ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
|
||||
|
||||
|
||||
#define EP_ADDR_MSK 0xFU
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
#if defined (USB)
|
||||
#define BTABLE_ADDRESS 0x000U
|
||||
#define PMA_ACCESS 2U
|
||||
|
||||
#ifndef USB_EP_RX_STRX
|
||||
#define USB_EP_RX_STRX (0x3U << 12)
|
||||
#endif /* USB_EP_RX_STRX */
|
||||
|
||||
#define EP_ADDR_MSK 0x7U
|
||||
|
||||
#ifndef USE_USB_DOUBLE_BUFFER
|
||||
#define USE_USB_DOUBLE_BUFFER 1U
|
||||
#endif /* USE_USB_DOUBLE_BUFFER */
|
||||
#endif /* defined (USB) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined (USB_OTG_FS)
|
||||
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
|
||||
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
|
||||
|
||||
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
|
||||
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
|
||||
* @{
|
||||
*/
|
||||
#if defined (USB_OTG_FS)
|
||||
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
|
||||
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode);
|
||||
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
|
||||
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
|
||||
HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
|
||||
uint8_t ch_ep_num, uint16_t len);
|
||||
|
||||
void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||
HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address);
|
||||
HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, const uint8_t *psetup);
|
||||
uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx);
|
||||
uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum);
|
||||
uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
|
||||
uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
|
||||
void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
|
||||
|
||||
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
|
||||
HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state);
|
||||
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx);
|
||||
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx);
|
||||
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
|
||||
uint8_t epnum, uint8_t dev_address, uint8_t speed,
|
||||
uint8_t ep_type, uint16_t mps);
|
||||
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
|
||||
USB_OTG_HCTypeDef *hc);
|
||||
|
||||
uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
|
||||
HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
|
||||
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
#if defined (USB)
|
||||
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
|
||||
HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed);
|
||||
|
||||
HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx);
|
||||
HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num);
|
||||
|
||||
#if defined (HAL_PCD_MODULE_ENABLED)
|
||||
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
#endif /* defined (HAL_PCD_MODULE_ENABLED) */
|
||||
|
||||
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
|
||||
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
|
||||
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src,
|
||||
uint8_t ch_ep_num, uint16_t len);
|
||||
|
||||
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||
|
||||
uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx);
|
||||
uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);
|
||||
uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
|
||||
uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx);
|
||||
uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
|
||||
void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt);
|
||||
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
|
||||
|
||||
void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
|
||||
uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
|
||||
void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
|
||||
uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
#endif /* defined (USB) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB) || defined (USB_OTG_FS) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
#endif /* STM32F1xx_LL_USB_H */
|
||||
316
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_wwdg.h
Normal file
316
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_wwdg.h
Normal file
@@ -0,0 +1,316 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_ll_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of WWDG LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_LL_WWDG_H
|
||||
#define STM32F1xx_LL_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (WWDG)
|
||||
|
||||
/** @defgroup WWDG_LL WWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EC_IT IT Defines
|
||||
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
|
||||
* @{
|
||||
*/
|
||||
#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
|
||||
* @{
|
||||
*/
|
||||
#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
|
||||
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
|
||||
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
|
||||
#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Write a value in WWDG register
|
||||
* @param __INSTANCE__ WWDG Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in WWDG register
|
||||
* @param __INSTANCE__ WWDG Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
|
||||
* @note It is enabled by setting the WDGA bit in the WWDG_CR register,
|
||||
* then it cannot be disabled again except by a reset.
|
||||
* This bit is set by software and only cleared by hardware after a reset.
|
||||
* When WDGA = 1, the watchdog can generate a reset.
|
||||
* @rmtoll CR WDGA LL_WWDG_Enable
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if Window Watchdog is enabled
|
||||
* @rmtoll CR WDGA LL_WWDG_IsEnabled
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
|
||||
* @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
|
||||
* This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
|
||||
* A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
|
||||
* Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
|
||||
* @rmtoll CR T LL_WWDG_SetCounter
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Counter 0..0x7F (7 bit counter value)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Counter Value (7 bits counter value)
|
||||
* @rmtoll CR T LL_WWDG_GetCounter
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval 7 bit Watchdog Counter value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->CR, WWDG_CR_T));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the time base of the prescaler (WDGTB).
|
||||
* @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
|
||||
* is decremented every (4096 x 2expWDGTB) PCLK cycles
|
||||
* @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Prescaler This parameter can be one of the following values:
|
||||
* @arg @ref LL_WWDG_PRESCALER_1
|
||||
* @arg @ref LL_WWDG_PRESCALER_2
|
||||
* @arg @ref LL_WWDG_PRESCALER_4
|
||||
* @arg @ref LL_WWDG_PRESCALER_8
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Prescaler Value
|
||||
* @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_WWDG_PRESCALER_1
|
||||
* @arg @ref LL_WWDG_PRESCALER_2
|
||||
* @arg @ref LL_WWDG_PRESCALER_4
|
||||
* @arg @ref LL_WWDG_PRESCALER_8
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
|
||||
* @note This window value defines when write in the WWDG_CR register
|
||||
* to program Watchdog counter is allowed.
|
||||
* Watchdog counter value update must occur only when the counter value
|
||||
* is lower than the Watchdog window register value.
|
||||
* Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
|
||||
* (in the control register) is refreshed before the downcounter has reached
|
||||
* the watchdog window register value.
|
||||
* Physically is possible to set the Window lower then 0x40 but it is not recommended.
|
||||
* To generate an immediate reset, it is possible to set the Counter lower than 0x40.
|
||||
* @rmtoll CFR W LL_WWDG_SetWindow
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Window 0x00..0x7F (7 bit Window value)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Window Value (7 bits value)
|
||||
* @rmtoll CFR W LL_WWDG_GetWindow
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval 7 bit Watchdog Window value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
|
||||
* @note This bit is set by hardware when the counter has reached the value 0x40.
|
||||
* It must be cleared by software by writing 0.
|
||||
* A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
|
||||
* @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
|
||||
* @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_IT_Management IT_Management
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the Early Wakeup Interrupt.
|
||||
* @note When set, an interrupt occurs whenever the counter reaches value 0x40.
|
||||
* This interrupt is only cleared by hardware after a reset
|
||||
* @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Early Wakeup Interrupt is enabled
|
||||
* @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* WWDG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_LL_WWDG_H */
|
||||
Reference in New Issue
Block a user