Начало
This commit is contained in:
295
Source/Internal/ecan.c
Normal file
295
Source/Internal/ecan.c
Normal file
@@ -0,0 +1,295 @@
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||
|
||||
#include "filter_bat2.h"
|
||||
#include "measure.h"
|
||||
#include "package.h" // DSP281x Headerfile Include File
|
||||
|
||||
#include "ecan.h" // DSP281x Headerfile Include File
|
||||
#include "tools.h" // DSP281x Headerfile Include File
|
||||
|
||||
#include "RS485.h"
|
||||
#include "message.h"
|
||||
#include "peripher.h"
|
||||
|
||||
|
||||
// Prototype statements for functions found within this file.
|
||||
interrupt void CANa_handler(void);
|
||||
interrupt void CANa_reset_err(void);
|
||||
interrupt void CANb_handler(void);
|
||||
interrupt void CANb_reset_err(void);
|
||||
|
||||
// Global variable for this example
|
||||
Uint32 ErrorCount;
|
||||
Uint32 MessageReceivedCount;
|
||||
Uint32 MessageTransivedCount=0;
|
||||
|
||||
Uint32 TestMbox1 = 0;
|
||||
Uint32 TestMbox2 = 0;
|
||||
Uint32 TestMbox3 = 0;
|
||||
|
||||
int CanTimeOutErrorTR = 0;
|
||||
|
||||
int wait=0;
|
||||
|
||||
void InitCan(int Port, int DevNum)
|
||||
{
|
||||
struct ECAN_REGS ECanShadow;
|
||||
|
||||
volatile struct ECAN_REGS * ECanRegs;
|
||||
volatile struct ECAN_MBOXES * ECanMboxes;
|
||||
volatile struct MOTO_REGS * ECanMOTORegs;
|
||||
|
||||
// Configure CAN pins using GPIO regs here
|
||||
EALLOW;
|
||||
|
||||
if(!Port)
|
||||
{
|
||||
ECanRegs = &ECanaRegs;
|
||||
ECanMboxes = &ECanaMboxes;
|
||||
ECanMOTORegs = &ECanaMOTORegs;
|
||||
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
ECanRegs = &ECanbRegs;
|
||||
ECanMboxes = &ECanbMboxes;
|
||||
ECanMOTORegs = &ECanbMOTORegs;
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2;
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2;
|
||||
}
|
||||
|
||||
// Configure the eCAN RX and TX pins for eCAN transmissions
|
||||
ECanRegs->CANTIOC.all = 8; // only 3rd bit, TXFUNC, is significant
|
||||
ECanRegs->CANRIOC.all = 8; // only 3rd bit, RXFUNC, is significant
|
||||
|
||||
// Specify that 8 bits will be sent/received
|
||||
ECanMboxes->MBOX0.MSGCTRL.all = 0x00000008;
|
||||
ECanMboxes->MBOX1.MSGCTRL.all = 0x00000008;
|
||||
ECanMboxes->MBOX2.MSGCTRL.all = 0x00000008;
|
||||
|
||||
// Disable all Mailboxes
|
||||
// Required before writing the MSGIDs
|
||||
ECanRegs->CANME.all = 0;
|
||||
|
||||
// 0 àùèê
|
||||
ECanRegs->CANMD.bit.MD0 = 0; // Ïåðåäà÷à
|
||||
ECanMboxes->MBOX0.MSGID.all = 0;
|
||||
ECanMboxes->MBOX0.MSGID.bit.IDE = 1; // extended id
|
||||
ECanMboxes->MBOX0.MSGID.bit.STDMSGID = (CanDevAdr <<2 ) + (1<<10);
|
||||
|
||||
// 1 àùèê
|
||||
ECanRegs->CANMD.bit.MD1 = 1; // Ïðèåì
|
||||
ECanMboxes->MBOX1.MSGID.all = 0;
|
||||
ECanMboxes->MBOX1.MSGID.bit.IDE = 1;
|
||||
ECanMboxes->MBOX1.MSGID.bit.AME = 1; // Ìàñêà
|
||||
ECanMboxes->MBOX1.MSGID.bit.STDMSGID = (CanDevAdr << 2); // ó ïðèåìà ïðèîðèòåò âûøå
|
||||
ECanaLAMRegs.LAM1.all = 0x000FFFFF;
|
||||
|
||||
// 2 àùèê
|
||||
ECanRegs->CANMD.bit.MD2 = 1; // Ïðèåì
|
||||
ECanMboxes->MBOX2.MSGID.all = 0;
|
||||
ECanMboxes->MBOX2.MSGID.bit.IDE = 1; // extended id
|
||||
ECanMboxes->MBOX2.MSGID.bit.AME = 1; // Ìàñêà
|
||||
ECanMboxes->MBOX2.MSGID.bit.STDMSGID = (0x1F << 2);
|
||||
ECanaLAMRegs.LAM2.all = 0x000FFFFF;
|
||||
|
||||
// âûáèðàåì òîëüêî 3 àùèêa äëà ðàáîòû, îñòàëüíûå çàïðåùàåì
|
||||
ECanRegs->CANME.all = 0x00000007;
|
||||
|
||||
// Clear all TAn bits
|
||||
ECanRegs->CANTA.all = 0xFFFFFFFF;
|
||||
// Clear all RMPn bits
|
||||
ECanRegs->CANRMP.all = 0xFFFFFFFF;
|
||||
// Clear all interrupt flag bits
|
||||
ECanRegs->CANGIF0.all = 0xFFFFFFFF;
|
||||
ECanRegs->CANGIF1.all = 0xFFFFFFFF;
|
||||
// Clear all error and status bits
|
||||
ECanRegs->CANES.all=0xffffffff;
|
||||
|
||||
// Request permission to change the configuration registers
|
||||
ECanShadow.CANMC.all = 0;
|
||||
ECanShadow.CANMC.bit.MBCC = 1; // Mailbox timestamp counter clear bit
|
||||
ECanShadow.CANMC.bit.TCC = 1; // Time stamp counter MSB clear bit
|
||||
ECanShadow.CANMC.bit.SCB = 1; // eCAN mode (reqd to access 32 mailboxes)
|
||||
ECanShadow.CANMC.bit.WUBA = 1; // Wake up on bus activity
|
||||
ECanShadow.CANMC.bit.ABO = 1; // Auto bus on
|
||||
ECanShadow.CANMC.bit.CCR = 1;
|
||||
// ECanShadow.CANMC.bit.STM = 1; // self-test loop-back
|
||||
ECanRegs->CANMC.all = ECanShadow.CANMC.all;
|
||||
while(!ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be set..
|
||||
|
||||
// íàñòðèâàåì ñêîðîñòü CAN
|
||||
ECanShadow.CANBTC.all = ECanRegs->CANBTC.all;
|
||||
ECanShadow.CANBTC.bit.SJWREG=1;
|
||||
|
||||
ECanShadow.CANBTC.bit.BRPREG = (CLKMULT * 12) - 1;
|
||||
ECanShadow.CANBTC.bit.TSEG1REG = 6;
|
||||
ECanShadow.CANBTC.bit.TSEG2REG = 1;
|
||||
|
||||
ECanRegs->CANBTC.all = ECanShadow.CANBTC.all;
|
||||
ECanShadow.CANMC.bit.CCR = 0; // Set CCR = 0
|
||||
ECanRegs->CANMC.all = ECanShadow.CANMC.all;
|
||||
while(ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be cleared..
|
||||
|
||||
// çàäàåì òàéìàóòû äëà îæèäàíèà îòïðàâêè ïîëó÷åíèà ïîñûëêè
|
||||
ECanMOTORegs->MOTO0 = 550000;
|
||||
ECanMOTORegs->MOTO1 = 550000;
|
||||
|
||||
ECanRegs->CANTOC.all = 1;
|
||||
ECanRegs->CANTOS.all = 0; // clear all time-out flags
|
||||
ECanRegs->CANTSC = 0; // clear time-out counter
|
||||
|
||||
ECanShadow.CANGIM.all = 0;
|
||||
|
||||
ECanRegs->CANMIM.all = 2+4; // Enable interrupts of box 1 and 2
|
||||
ECanRegs->CANMIL.all = 0x00000000; // All mailbox interrupts are generated on interrupt line 0.
|
||||
ECanShadow.CANGIM.bit.I0EN = 1;
|
||||
|
||||
ECanShadow.CANGIM.bit.MTOM = 1;
|
||||
ECanShadow.CANGIM.bit.I1EN = 1;
|
||||
ECanShadow.CANGIM.bit.GIL = 1;
|
||||
ECanRegs->CANGIM.all = ECanShadow.CANGIM.all;
|
||||
|
||||
PieVectTable.ECAN0INTA = &CANa_handler;
|
||||
PieCtrlRegs.PIEIER9.bit.INTx5=1; // PIE Group 9, INT6
|
||||
PieVectTable.ECAN1INTA = &CANa_reset_err;
|
||||
PieCtrlRegs.PIEIER9.bit.INTx6=1; // PIE Group 9, INT6
|
||||
|
||||
IER |= M_INT9; // Enable CPU INT
|
||||
|
||||
EDIS;
|
||||
|
||||
// çàâåðøèëè íàñòðîéêó CAN àùèêîâ
|
||||
|
||||
MessageReceivedCount = 0;
|
||||
ErrorCount = 0;
|
||||
CanTimeOutErrorTR=0;
|
||||
MessageTransivedCount=0;
|
||||
}
|
||||
|
||||
void CAN_send(int Port, int data[], int Addr, int Qua)
|
||||
{
|
||||
unsigned long hiword,loword;
|
||||
volatile struct ECAN_REGS * ECanRegs;
|
||||
volatile struct ECAN_MBOXES * ECanMboxes;
|
||||
ECanRegs = &ECanaRegs;
|
||||
ECanMboxes = &ECanaMboxes;
|
||||
|
||||
if(wait)
|
||||
if(!(ECanRegs->CANTA.all & 1))
|
||||
if(!(ECanRegs->CANAA.all & 1))
|
||||
return;
|
||||
|
||||
ECanRegs->CANTA.all = 1;
|
||||
ECanRegs->CANAA.all = 1;
|
||||
|
||||
loword= ((((Uint32)data[Addr+0]) & 0xffff)<<16)|
|
||||
((((Uint32)data[Addr+1]) & 0xffff) );
|
||||
hiword= ((((Uint32)data[Addr+2]) & 0xffff)<<16)|
|
||||
((((Uint32)data[Addr+3]) & 0xffff) );
|
||||
|
||||
ECanMboxes->MBOX0.MDH.all = hiword;
|
||||
ECanMboxes->MBOX0.MDL.all = loword;
|
||||
|
||||
EALLOW;
|
||||
ECanRegs->CANME.bit.ME0 = 0;
|
||||
ECanMboxes->MBOX0.MSGID.bit.EXTMSGID_L = Addr;
|
||||
ECanMboxes->MBOX0.MSGCTRL.all = Qua*2;
|
||||
|
||||
ECanRegs->CANME.bit.ME0 = 1;
|
||||
|
||||
ECanRegs->CANTSC = 0; // clear time-out counter
|
||||
EDIS;
|
||||
|
||||
ECanRegs->CANTRS.all = 1; // çàïóñòèòü ïåðåäà÷ó
|
||||
|
||||
wait=1;
|
||||
|
||||
if(Desk==dsk_SHKF) toggle_LED_OUT_2();
|
||||
else led1_toggle();
|
||||
}
|
||||
|
||||
|
||||
void Handlai(volatile struct MBOX * ECanMbox)
|
||||
{
|
||||
unsigned int adr,qua;
|
||||
unsigned long hiword,loword;
|
||||
int Data[4];
|
||||
|
||||
hiword = ECanMbox->MDH.all;
|
||||
loword = ECanMbox->MDL.all;
|
||||
|
||||
adr = ECanMbox->MSGID.bit.EXTMSGID_L & 0x07F;
|
||||
qua = ECanMbox->MSGCTRL.all / 2;
|
||||
|
||||
if(adr>= 4 && adr<= 7) LoneLeft=0;
|
||||
if(adr>=10 && adr<=13) LoneRite=0;
|
||||
|
||||
Data[0] = (loword>>16) & 0xffff;
|
||||
Data[1] = (loword ) & 0xffff;
|
||||
Data[2] = (hiword>>16) & 0xffff;
|
||||
Data[3] = (hiword ) & 0xffff;
|
||||
|
||||
if(qua ) if(adr < ANSWER_LEN) modbus[adr] = Data[0]; adr++;
|
||||
if(qua>1) if(adr < ANSWER_LEN) modbus[adr] = Data[1]; adr++;
|
||||
if(qua>2) if(adr < ANSWER_LEN) modbus[adr] = Data[2]; adr++;
|
||||
if(qua>3) if(adr < ANSWER_LEN) modbus[adr] = Data[3];
|
||||
|
||||
led2_toggle();
|
||||
}
|
||||
|
||||
interrupt void CANa_handler(void)
|
||||
{
|
||||
unsigned long mask=1;
|
||||
int box;
|
||||
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
box = ECanaRegs.CANGIF0.bit.MIV0;
|
||||
mask <<= box;
|
||||
ECanaRegs.CANRMP.all = mask;
|
||||
|
||||
Handlai(&ECanaMboxes.MBOX0 + box);
|
||||
|
||||
// Handlai(&ECanaMboxes);
|
||||
|
||||
// ECanaRegs.CANRMP.all = 2;
|
||||
PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
}
|
||||
|
||||
interrupt void CANa_reset_err(void)
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
ECanaRegs.CANTRR.all = 1;
|
||||
CanTimeOutErrorTR++;
|
||||
|
||||
PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
Reference in New Issue
Block a user