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216
Source/Internal/ADC.c
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216
Source/Internal/ADC.c
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#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
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#include "DSP2833x_Examples.h" // DSP281x Examples Include File
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#include "DSP2833x_SWPrioritizedIsrLevels.h"
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#include "ADC.h"
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#include "log_to_mem.h"
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#include "RS485.h"
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#include "filter_bat2.h"
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#include "measure.h"
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#include "message.h"
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#include "package.h"
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#include "peripher.h"
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float ADC_table[ADC_MAX];
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int prev_ok[ADC_MAX];
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int ADC_skip[TPL_MAX];
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float MesPerSec;
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unsigned int COUNT_ONE_CANAL;
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unsigned int COUNT_ONE_CANAL;
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unsigned int COUNT_DISCHARGE;
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unsigned int COUNT_TRANSICIA;
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unsigned int FILTER_CLIP;
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long WAKE, WAKE_TIME;
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// Prototype statements for functions found within this file.
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interrupt void adc_isr(void);
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void setup_adc()
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{
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long CLKdiv,HSPCLKdiv,Rate;
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int i;
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// Interrupts that are used in this example are re-mapped to
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// ISR functions found within this file.
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EALLOW; // This is needed to write to EALLOW protected register
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PieVectTable.ADCINT = &adc_isr;
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EDIS; // This is needed to disable write to EALLOW protected registers
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InitAdc(); // For this example, init the ADC
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// Enable ADCINT in PIE
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PieCtrlRegs.PIEIER1.bit.INTx6 = 1;
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IER |= M_INT1; // Enable CPU Interrupt 1
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// Configure ADC
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if(Desk==dsk_BKSD)
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{
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AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x0000; // Setup 2 conv's on SEQ1
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AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; //0x5;//0x7; // Setup ADCINA3 as 1st SEQ1 conv.
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}
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if(Desk==dsk_COMM)
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{
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AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x0001; // Setup 2 conv's on SEQ1
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AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x5; // ñíà÷àëà òîæå áóäóò òåìïåðàòóðû
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AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x4; // Setup ADCINA2 as 2nd SEQ1 conv.
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/* À íàïðàæåíèé íàì òóò è íå íàäî
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AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x7; // Setup ADCINA2 as 2nd SEQ1 conv.
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AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x2; // Setup ADCINA2 as 2nd SEQ1 conv.
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AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x3; // Setup ADCINA2 as 2nd SEQ1 conv.
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AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x6; // Setup ADCINA2 as 2nd SEQ1 conv.
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AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x1; // Setup ADCINA2 as 2nd SEQ1 conv.
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*/ }
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AdcRegs.ADCREFSEL.bit.REF_SEL=1;
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AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1; // Enable SOCA from ePWM to start SEQ1
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AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS)
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AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit
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AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode
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AdcRegs.ADCTRL1.bit.ACQ_PS = 15;
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AdcRegs.ADCTRL1.bit.CONT_RUN = 0;
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// AdcRegs.ADCTRL1.bit.CPS=1;
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AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
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// Assumes ePWM1 clock is already enabled in InitSysCtrl();
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EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
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EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount
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EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
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EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value
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EPwm1Regs.TBCTL.bit.HSPCLKDIV = CLKMULT;
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EPwm1Regs.TBCTL.bit.CLKDIV=2;
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CLKdiv = 1<<EPwm1Regs.TBCTL.bit.CLKDIV;
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if(EPwm1Regs.TBCTL.bit.HSPCLKDIV) HSPCLKdiv = 2*EPwm1Regs.TBCTL.bit.HSPCLKDIV;
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else HSPCLKdiv = 1;
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Rate = (SYSCLKOUT/(HSPCLKdiv*CLKdiv))/ADC_FREQ;
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EPwm1Regs.TBPRD = Rate;//0x4000; // Set period for ePWM1
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EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start
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if(TermoRS)
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{
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MesPerSec = 250;
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COUNT_ONE_CANAL = ADC_FREQ/250; // 15
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COUNT_DISCHARGE = 4;
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COUNT_TRANSICIA = 9;
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FILTER_CLIP = 40;
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WAKE_TIME =7L * ADC_FREQ;
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}
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if(TermoAD)
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{
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MesPerSec = 15;
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COUNT_ONE_CANAL = ADC_FREQ/15; // 250;
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COUNT_DISCHARGE = ADC_FREQ/145; // 25;
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COUNT_TRANSICIA = ADC_FREQ/25; // 150;
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FILTER_CLIP = 200;
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WAKE_TIME =3L * ADC_FREQ;
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}
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WAKE = WAKE_TIME;
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for(i=0;i<ADC_MAX;i++)
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ADC_table[i]=
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prev_ok[i]=0;
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}
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interrupt void adc_isr(void)
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{
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static int cownt_one_canal=0;
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static int cownt_cans=0;
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int code_tpl_canal=0;
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float Temper,Filter;
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int i,n;
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static int ok, cwnt_ok[2]={0,0};
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// Set interrupt priority:
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volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
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IER |= M_INT1;
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IER &= MINT1; // Set "global" priority
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PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority
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PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
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EINT;
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if(WAKE) WAKE--;
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if(WAKE > WAKE_TIME - 10) goto fin;
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if(Caliber_time)
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{
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if(!--Caliber_time)
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{
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cTermoCal = 0;
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cSaveParam = 1;
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} }
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if(cownt_one_canal==COUNT_DISCHARGE)
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{
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code_tpl_canal = cownt_cans;
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if(TermoAD)
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{
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if(cownt_cans == TPL_CANS ) code_tpl_canal = TERMOPAIR-1;
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if(cownt_cans == TPL_CANS+1) code_tpl_canal = TERMOPAIR-2; // ïîòîìó ÷òî 300 è 400 íàîáîðîò
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}
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select_tpl_canal(code_tpl_canal);
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}
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if(cownt_one_canal > COUNT_TRANSICIA)
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for(i=0;i<TermoSW;i++)
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{
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n = TermoSW*cownt_cans+i;
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Temper = *(&AdcRegs.ADCRESULT0 + i) >>4;
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Filter = filterbat(&adc_filter[n],Temper);
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ok = abs(ADC_table[n]-Temper) < FILTER_CLIP;
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if(ok) cwnt_ok[i]++;
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if(ok|!prev_ok[n])
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{
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if(WAKE)ADC_table[n] = Temper;
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else ADC_table[n] = Filter;
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} }
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if(++cownt_one_canal>=COUNT_ONE_CANAL)
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{ cownt_one_canal=0;
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select_tpl_255();
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for(i=0;i<TermoSW;i++)
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{
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n = TermoSW*cownt_cans+i;
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Temper_count(n);
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prev_ok[n] = cwnt_ok[i];
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cwnt_ok[i] = 0;
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}
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if(ADC_skip[++cownt_cans]) cownt_cans++;
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if( cownt_cans >= TPL_CANS+2)
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cownt_cans=0;
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}
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fin:
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// Reinitialize for next ADC sequence
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AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1
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AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
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// Restore registers saved:
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DINT;
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PieCtrlRegs.PIEIER1.all = TempPIEIER;
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return;
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}
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