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+:0A7CB4000600080033000B000A0070 +:207CBE002800000012C191A400003EA500007DA400002AA500006CA4000018A500005BA4D7 +:207CDE000000FFA400003CA40000EBA400002BA40000DFA400000DA40000CEA40000FCA360 +:187CFE000000BBA40000EBA30000AAA40000D4A30000BAA3000000005F +:00000001FF diff --git a/Bin/UKSSTMS320F28335.map b/Bin/UKSSTMS320F28335.map new file mode 100644 index 0000000..9a89b4f --- /dev/null +++ b/Bin/UKSSTMS320F28335.map @@ -0,0 +1,34 @@ +******************************************************************************** +TMS320C2000 Hex Converter v5.2.7 +******************************************************************************** + +INPUT FILE NAME: +OUTPUT FORMAT: Binary + +PHYSICAL MEMORY PARAMETERS + Default data width : 16 + Default memory width : 8 (LS-->MS) + Default output width : 8 + +BOOT LOADER PARAMETERS + Table Type: SERIAL PORT (SCI 8 bit Mode) + Entry Point: 0x0000b8fa + + +OUTPUT TRANSLATION MAP +-------------------------------------------------------------------------------- +00000000..003fffff Page=0 Memory Width=8 ROM Width=8 +-------------------------------------------------------------------------------- + OUTPUT FILES: D:\project12\Balsam_167\bin\UKSSTMS320F28335.bin [b0..b7] + + CONTENTS: 00000000..00007d15 BOOT TABLE + .cinit : dest=0000ba94 size=0000027f width=00000002 + .text : dest=00008000 size=00003a94 width=00000002 + ramfuncs : dest=0000c15d size=00000023 width=00000002 + .econst : dest=0000c000 size=00000112 width=00000002 + .switch : dest=0000c112 size=00000028 width=00000002 + +-------------------------------------------------------------------------------- +00000000..003fffff Page=1 Memory Width=8 ROM Width=8 "*DEFAULT PAGE 1*" +-------------------------------------------------------------------------------- + NO CONTENTS diff --git a/Bin/hex2000.exe b/Bin/hex2000.exe new file mode 100644 index 0000000..37a8d77 Binary files /dev/null and b/Bin/hex2000.exe differ diff --git a/Bin/hex2000V6.1.0.exe b/Bin/hex2000V6.1.0.exe new file mode 100644 index 0000000..37659ad Binary files /dev/null and b/Bin/hex2000V6.1.0.exe differ diff --git a/Debug.lkf b/Debug.lkf new file mode 100644 index 0000000..a877a25 --- /dev/null +++ b/Debug.lkf @@ -0,0 +1,31 @@ +-z -c -e_c_int00 -m"D:/project12/Balsam_167/UKSSTMS320F28335.map" -o"D:/project12/Balsam_167/bin/UKSSTMS320F28335.out" -stack0x3f0 -w -x -i"D:/CCStudio_v3.3PLA/C2000/xdais/lib" -i"D:/CCStudio_v3.3PLA/bios_5_33_05/packages/ti/bios/lib" -i"D:/CCStudio_v3.3PLA/bios_5_33_05/packages/ti/rtdx/lib/c2000" -i"D:/ti/cgt/C2000 Code Generation Tools 5.2.15/lib" -l"rts2800_fpu32.lib" +"D:\project12\Balsam_167\F28335.cmd" +"D:\project12\Balsam_167\Source\External\v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" +"D:\project12\Balsam_167\Debug\ADC.obj" +"D:\project12\Balsam_167\Debug\bios.obj" +"D:\project12\Balsam_167\Debug\cntrl_adr.obj" +"D:\project12\Balsam_167\Debug\crc16.obj" +"D:\project12\Balsam_167\Debug\DAC.obj" +"D:\project12\Balsam_167\Debug\DSP2833x_Adc.obj" +"D:\project12\Balsam_167\Debug\DSP2833x_ADC_cal.obj" +"D:\project12\Balsam_167\Debug\DSP2833x_CpuTimers.obj" +"D:\project12\Balsam_167\Debug\DSP2833x_GlobalVariableDefs.obj" +"D:\project12\Balsam_167\Debug\DSP2833x_PieCtrl.obj" +"D:\project12\Balsam_167\Debug\DSP2833x_SWPrioritizedDefaultIsr.obj" +"D:\project12\Balsam_167\Debug\DSP2833x_SWPrioritizedPieVect.obj" +"D:\project12\Balsam_167\Debug\DSP2833x_SysCtrl.obj" +"D:\project12\Balsam_167\Debug\DSP2833x_usDelay.obj" +"D:\project12\Balsam_167\Debug\DSP2833x_Xintf.obj" +"D:\project12\Balsam_167\Debug\ecan.obj" +"D:\project12\Balsam_167\Debug\filter_bat2.obj" +"D:\project12\Balsam_167\Debug\kanal.obj" +"D:\project12\Balsam_167\Debug\log_to_mem.obj" +"D:\project12\Balsam_167\Debug\main.obj" +"D:\project12\Balsam_167\Debug\measure.obj" +"D:\project12\Balsam_167\Debug\message.obj" +"D:\project12\Balsam_167\Debug\peripher.obj" +"D:\project12\Balsam_167\Debug\pulto.obj" +"D:\project12\Balsam_167\Debug\RS485.obj" +"D:\project12\Balsam_167\Debug\spise2p.obj" +"D:\project12\Balsam_167\Debug\tools.obj" +"D:\project12\Balsam_167\Libraries\rts2800_fpu32.lib" diff --git a/Doc/Balsam 167 data stru.xls b/Doc/Balsam 167 data stru.xls new file mode 100644 index 0000000..0fa2ce1 Binary files /dev/null and b/Doc/Balsam 167 data stru.xls differ diff --git a/F28335.cmd b/F28335.cmd new file mode 100644 index 0000000..fffa02b --- /dev/null +++ b/F28335.cmd @@ -0,0 +1,206 @@ +/* +// TI File $Revision: /main/10 $ +// Checkin $Date: July 9, 2008 13:43:56 $ +//########################################################################### +// +// FILE: F28335.cmd +// +// TITLE: Linker Command File For F28335 Device +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. + */ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAML0 : origin = 0x008000, length = 0x004000 /* on-chip RAM block L0 */ +/* RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ +/* RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ +// RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ + RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ + + ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */ + FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */ + FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */ + FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */ + FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */ + FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */ + FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */ + FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ + + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML5 : origin = 0x00D000, length = 0x003000 /* on-chip RAM block L1 */ +/* RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */ +/* RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */ + ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ + FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */ +} + +/* Allocate sections to memory blocks. + Note: + codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code + execution when booting to flash + ramfuncs user defined section to store functions that will be copied from Flash into RAM +*/ + +SECTIONS +{ + + /* Allocate program areas: */ + .cinit : > RAML0 PAGE = 0 + .pinit : > RAML0 PAGE = 0 + .text : > RAML0 PAGE = 0 + codestart : > BEGIN PAGE = 0 + ramfuncs : LOAD = RAML4, + RUN = RAML4, + LOAD_START(_RamfuncsLoadStart), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + PAGE = 0 + + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAML5 PAGE = 1 + .esysmem : > RAML0 PAGE = 0 + + .logg : > ZONE7A PAGE = 1 + + /* Initalized sections go in Flash */ + /* For SDFlash to program these, they must be allocated to page 0 */ + .econst : > RAML4 PAGE = 0 + .switch : > RAML4 PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: * / + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 +/* DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 +*/ + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + + /* .reset is a standard section used by the compiler. It contains the */ + /* the address of the start of _c_int00 for C Code. /* + /* When using the boot ROM this section and the CPU vector */ + /* table is not needed. Thus the default type is set here to */ + /* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ + diff --git a/Libraries/IQmath.lib b/Libraries/IQmath.lib new file mode 100644 index 0000000..340caf0 Binary files /dev/null and b/Libraries/IQmath.lib differ diff --git a/Libraries/IQmath_fpu32.lib b/Libraries/IQmath_fpu32.lib new file mode 100644 index 0000000..426802a Binary files /dev/null and b/Libraries/IQmath_fpu32.lib differ diff --git a/Libraries/SFO_TI_Build.lib b/Libraries/SFO_TI_Build.lib new file mode 100644 index 0000000..1956f36 Binary files /dev/null and b/Libraries/SFO_TI_Build.lib differ diff --git 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b/Libraries/rts2800.lib new file mode 100644 index 0000000..7fa16db Binary files /dev/null and b/Libraries/rts2800.lib differ diff --git a/Libraries/rts2800_eh.lib b/Libraries/rts2800_eh.lib new file mode 100644 index 0000000..c370613 Binary files /dev/null and b/Libraries/rts2800_eh.lib differ diff --git a/Libraries/rts2800_fpu32.lib b/Libraries/rts2800_fpu32.lib new file mode 100644 index 0000000..d6093e1 Binary files /dev/null and b/Libraries/rts2800_fpu32.lib differ diff --git a/Libraries/rts2800_fpu32_eh.lib b/Libraries/rts2800_fpu32_eh.lib new file mode 100644 index 0000000..8006f5c Binary files /dev/null and b/Libraries/rts2800_fpu32_eh.lib differ diff --git a/Libraries/rts2800_fpu32_fast_supplement.lib b/Libraries/rts2800_fpu32_fast_supplement.lib new file mode 100644 index 0000000..05f9301 Binary files /dev/null and b/Libraries/rts2800_fpu32_fast_supplement.lib differ diff --git a/Libraries/rts2800_ml.lib b/Libraries/rts2800_ml.lib new file mode 100644 index 0000000..fb34b0f Binary files /dev/null and b/Libraries/rts2800_ml.lib differ diff --git a/Libraries/rts2800_ml_eh.lib b/Libraries/rts2800_ml_eh.lib new file mode 100644 index 0000000..189b3a9 Binary files /dev/null and b/Libraries/rts2800_ml_eh.lib differ diff --git a/Source/External/v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h b/Source/External/v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h new file mode 100644 index 0000000..8919b97 --- /dev/null +++ b/Source/External/v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h @@ -0,0 +1,147 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// Non-Peripheral Interrupts: +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// Group 1 PIE Interrupt Service Routines: +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// Group 2 PIE Interrupt Service Routines: +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// Group 3 PIE Interrupt Service Routines: +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// Group 4 PIE Interrupt Service Routines: +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// Group 5 PIE Interrupt Service Routines: +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// Group 6 PIE Interrupt Service Routines: +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// Group 7 PIE Interrupt Service Routines: +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// Group 8 PIE Interrupt Service Routines: +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// Group 9 PIE Interrupt Service Routines: +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// Group 10 PIE Interrupt Service Routines: + +// Group 11 PIE Interrupt Service Routines: + +// Group 12 PIE Interrupt Service Routines: +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// Catch-all for Reserved Locations For testing purposes: +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/include/DSP2833x_Dma_defines.h b/Source/External/v120/DSP2833x_common/include/DSP2833x_Dma_defines.h new file mode 100644 index 0000000..7b8dfaf --- /dev/null +++ b/Source/External/v120/DSP2833x_common/include/DSP2833x_Dma_defines.h @@ -0,0 +1,81 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// MODE +//========================== +// PERINTSEL bits +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 +// OVERINTE bit +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 +// PERINTE bit +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 +// CHINTMODE bits +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 +// ONESHOT bits +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 +// CONTINOUS bit +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 +// SYNCE bit +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 +// SYNCSEL bit +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 +// DATASIZE bit +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 +// CHINTE bit +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + + + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h b/Source/External/v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h new file mode 100644 index 0000000..061842f --- /dev/null +++ b/Source/External/v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h @@ -0,0 +1,164 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// TBCTL (Time-Base Control) +//========================== +// CTRMODE bits +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 +// PHSEN bit +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 +// PRDLD bit +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 +// SYNCOSEL bits +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 +// HSPCLKDIV and CLKDIV bits +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 +// PHSDIR bit +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// CMPCTL (Compare Control) +//========================== +// LOADAMODE and LOADBMODE bits +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 +// SHDWAMODE and SHDWBMODE bits +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// AQCTLA and AQCTLB (Action Qualifier Control) +//============================================= +// ZRO, PRD, CAU, CAD, CBU, CBD bits +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// DBCTL (Dead-Band Control) +//========================== +// OUT MODE bits +#define DB_DISABLE 0x0 +#define DBA_ENABLE 0x1 +#define DBB_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 +// POLSEL bits +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 +// IN MODE +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// CHPCTL (chopper control) +//========================== +// CHPEN bit +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 +// CHPFREQ bits +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 +// CHPDUTY bits +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// TZSEL (Trip Zone Select) +//========================== +// CBCn and OSHTn bits +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// TZCTL (Trip Zone Control) +//========================== +// TZA and TZB bits +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// ETSEL (Event Trigger Select) +//============================= +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// ETPS (Event Trigger Pre-scale) +//=============================== +// INTPRD, SOCAPRD, SOCBPRD bits +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + + +//-------------------------------- +// HRPWM (High Resolution PWM) +//================================ +// HRCNFG +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/include/DSP2833x_Examples.h b/Source/External/v120/DSP2833x_common/include/DSP2833x_Examples.h new file mode 100644 index 0000000..7ababcb --- /dev/null +++ b/Source/External/v120/DSP2833x_common/include/DSP2833x_Examples.h @@ -0,0 +1,143 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------- + Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +-----------------------------------------------------------------------------*/ +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR CLKMULT*2 + +//#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode +//---------------------------------------------------------------------------- + + +/*----------------------------------------------------------------------------- + Specify the clock rate of the CPU (SYSCLKOUT) in nS. + + Take into account the input clock frequency and the PLL multiplier + selected in step 1. + + Use one of the values provided, or define your own. + The trailing L is required tells the compiler to treat + the number as a 64-bit value. + + Only one statement should be uncommented. + + Example 1:150 MHz devices: + CLKIN is a 30MHz crystal. + + In step 1 the user specified PLLCR = 0xA for a + 150Mhz CPU clock (SYSCLKOUT = 150MHz). + + In this case, the CPU_RATE will be 6.667L + Uncomment the line: #define CPU_RATE 6.667L + + Example 2: 100 MHz devices: + CLKIN is a 20MHz crystal. + + In step 1 the user specified PLLCR = 0xA for a + 100Mhz CPU clock (SYSCLKOUT = 100MHz). + + In this case, the CPU_RATE will be 10.000L + Uncomment the line: #define CPU_RATE 10.000L +-----------------------------------------------------------------------------*/ +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +//---------------------------------------------------------------------------- + +/*----------------------------------------------------------------------------- + Target device (in DSP2833x_Device.h) determines CPU frequency + (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz + (for 28332). User does not have to change anything here. +-----------------------------------------------------------------------------*/ +#if DSP28_28332 // DSP28_28332 device only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + + +//--------------------------------------------------------------------------- +// Include Example Header Files: +// + +#include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the + // .c files. + +#include "DSP2833x_ePwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2C_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28332 0xED +#define PARTNO_28235 0xE8 +#define PARTNO_28234 0xE7 +#define PARTNO_28232 0xE6 + + +// Include files not used with DSP/BIOS +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultISR.h" +#endif + + +// DO NOT MODIFY THIS LINE. +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L) + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h b/Source/External/v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h new file mode 100644 index 0000000..9c90607 --- /dev/null +++ b/Source/External/v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h @@ -0,0 +1,207 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +/*---- shared global function prototypes -----------------------------------*/ +extern void InitAdc(void); + +extern void DMAInitialize(void); +// DMA Channel 1 +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH1(void); +// DMA Channel 2 +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH2(void); +// DMA Channel 3 +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH3(void); +// DMA Channel 4 +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH4(void); +// DMA Channel 5 +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH5(void); +// DMA Channel 6 +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void XintfInit(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// DSP28_DBGIER.asm +extern void SetDBGIER(Uint16 dbgier); + +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +extern void InitFlash(void); + + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + + +//--------------------------------------------------------------------------- +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/include/DSP2833x_I2c_defines.h b/Source/External/v120/DSP2833x_common/include/DSP2833x_I2c_defines.h new file mode 100644 index 0000000..ce3f1f7 --- /dev/null +++ b/Source/External/v120/DSP2833x_common/include/DSP2833x_I2c_defines.h @@ -0,0 +1,117 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +//-------------------------------------------- +// Defines +//-------------------------------------------- + +// Error Messages +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// Clear Status Flags +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// Interrupt Source Messages +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// I2CMSG structure defines +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// I2C Slave State defines +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// I2C Slave Receiver messages defines +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// I2C State defines +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// I2C Message Commands for I2CMSG struct +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// Generic defines +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + + +//-------------------------------------------- +// Structures +//-------------------------------------------- + +// I2C Message Structure +struct I2CMSG { + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + Uint16 MemoryHighAddr; // EEPROM address of data associated with msg (high byte) + Uint16 MemoryLowAddr; // EEPROM address of data associated with msg (low byte) + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that + // MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h b/Source/External/v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h new file mode 100644 index 0000000..c3f3ea1 --- /dev/null +++ b/Source/External/v120/DSP2833x_common/include/DSP2833x_SWPrioritizedIsrLevels.h @@ -0,0 +1,5850 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 4, 2007 14:25:21 $ +//########################################################################### +// +// FILE: DSP2833x_SWPrioritizedIsrLevels.h +// +// TITLE: DSP28 Devices Software Prioritized Interrupt Service Routine +// Level definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_SW_PRIORITZIED_ISR_H +#define DSP2833x_SW_PRIORITZIED_ISR_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//------------------------------------------------------------------------------- +// Interrupt Enable Register Allocation For 2833x Devices: +//------------------------------------------------------------------------------- +// Interrupts can be enabled/disabled using the CPU interrupt enable register +// (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12). +//------------------------------------------------------------------------------- +//------------------------------------------------------------------------------- +// Set "Global" Interrupt Priority Level (IER register): +//------------------------------------------------------------------------------- +// The user must set the appropriate priority level for each of the CPU +// interrupts. This is termed as the "global" priority. The priority level +// must be a number between 1 (highest) to 16 (lowest). A value of 0 must +// be entered for reserved interrupts or interrupts that are not used. This +// will also reduce code size by not including ISR's that are not used. +// +// Note: The priority levels below are used to calculate the IER register +// interrupt masks MINT1 to MINT16. +// +// +// Note: The priority levels shown here may not make sense in a +// real application. This is for demonstration purposes only!!! +// +// The user should change these to values that make sense for +// their application. +// +// 0 = not used +// 1 = highest priority +// ... +// 16 = lowest priority +#define INT1PL 2 // Group1 Interrupts (PIEIER1) +#define INT2PL 0 // Group2 Interrupts (PIEIER2) +#define INT3PL 4 // Group3 Interrupts (PIEIER3) +#define INT4PL 2 // Group4 Interrupts (PIEIER4) +#define INT5PL 2 // Group5 Interrupts (PIEIER5) +#define INT6PL 3 // Group6 Interrupts (PIEIER6) +#define INT7PL 0 // reserved +#define INT8PL 0 // reserved +#define INT9PL 1 // Group9 Interrupts (PIEIER9) +#define INT10PL 0 // reserved +#define INT11PL 0 // reserved +#define INT12PL 0 // reserved +#define INT13PL 4 // XINT13 +#define INT14PL 4 // INT14 (TINT2) +#define INT15PL 4 // DATALOG +#define INT16PL 4 // RTOSINT + +//------------------------------------------------------------------------------- +// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers): +//------------------------------------------------------------------------------- +// The user must set the appropriate priority level for each of the PIE +// interrupts. This is termed as the "group" priority. The priority level +// must be a number between 1 (highest) to 8 (lowest). A value of 0 must +// be entered for reserved interrupts or interrupts that are not used. This +// will also reduce code size by not including ISR's that are not used: +// +// Note: The priority levels below are used to calculate the following +// PIEIER register interrupt masks: +// MG11 to MG18 +// MG21 to MG28 +// MG31 to MG38 +// MG41 to MG48 +// MG51 to MG58 +// MG61 to MG68 +// MG71 to MG78 +// MG81 to MG88 +// MG91 to MG98 +// MG101 to MG108 +// MG111 to MG118 +// MG121 to MG128 +// +// Note: The priority levels shown here may not make sense in a +// real application. This is for demonstration purposes only!!! +// +// The user should change these to values that make sense for +// their application. +// +// 0 = not used +// 1 = highest priority +// ... +// 8 = lowest priority +// +#define G11PL 7 // SEQ1INT (ADC) +#define G12PL 6 // SEQ2INT (ADC) +#define G13PL 0 // reserved +#define G14PL 1 // XINT1 (External) +#define G15PL 3 // XINT2 (External) +#define G16PL 2 // ADCINT (ADC) +#define G17PL 1 // TINT0 (CPU Timer 0) +#define G18PL 5 // WAKEINT (WD/LPM) + +#define G21PL 4 // EPWM1_TZINT (ePWM1 Trip) +#define G22PL 3 // EPWM2_TZINT (ePWM2 Trip) +#define G23PL 2 // EPWM3_TZINT (ePWM3 Trip) +#define G24PL 1 // EPWM4_TZINT (ePWM4 Trip) +#define G25PL 5 // EPWM5_TZINT (ePWM5 Trip) +#define G26PL 6 // EPWM6_TZINT (ePWM6 Trip) +#define G27PL 0 // reserved +#define G28PL 0 // reserved + +#define G31PL 4 // EPWM1_INT (ePWM1 Int) +#define G32PL 1 // EPWM2_INT (ePWM2 Int) +#define G33PL 1 // EPWM3_INT (ePWM3 Int) +#define G34PL 2 // EPWM4_INT (ePWM4 Int) +#define G35PL 2 // EPWM5_INT (ePWM5 Int) +#define G36PL 1 // EPWM6_INT (ePWM6 Int) +#define G37PL 0 // reserved +#define G38PL 0 // reserved + +#define G41PL 2 // ECAP1_INT (eCAP1 Int) +#define G42PL 1 // ECAP2_INT (eCAP2 Int) +#define G43PL 3 // ECAP3_INT (eCAP3 Int) +#define G44PL 3 // ECAP4_INT (eCAP4 Int) +#define G45PL 5 // ECAP5_INT (eCAP5 Int) +#define G46PL 5 // ECAP6_INT (eCAP6 Int) +#define G47PL 0 // reserved +#define G48PL 0 // reserved + +#define G51PL 2 // EQEP1_INT (eQEP1 Int) +#define G52PL 1 // EQEP2_INT (eQEP2 Int) +#define G53PL 0 // reserved +#define G54PL 0 // reserved +#define G55PL 0 // reserved +#define G56PL 0 // reserved +#define G57PL 0 // reserved +#define G58PL 0 // reserved + +#define G61PL 3 // SPIRXINTA (SPI-A) +#define G62PL 1 // SPITXINTA (SPI-A) +#define G63PL 4 // MRINTB (McBSP-B) +#define G64PL 6 // MXINTB (McBSP-B) +#define G65PL 2 // MRINTA (McBSP-A) +#define G66PL 1 // MXINTA (McBSP-A) +#define G67PL 0 // reserved +#define G68PL 0 // reserved + +#define G71PL 5 // DINTCH1 (DMA) +#define G72PL 4 // DINTCH2 (DMA) +#define G73PL 4 // DINTCH3 (DMA) +#define G74PL 2 // DINTCH4 (DMA) +#define G75PL 3 // DINTCH5 (DMA) +#define G76PL 1 // DINTCH6 (DMA) +#define G77PL 0 // reserved +#define G78PL 0 // reserved + +#define G81PL 1 // I2CINT1A (I2C-A) +#define G82PL 2 // I2CINT2A (I2C-A) +#define G83PL 0 // reserved +#define G84PL 0 // reserved +#define G85PL 4 // SCIRXINTC (SCI-C) +#define G86PL 3 // SCITXINTC (SCI-C) +#define G87PL 0 // reserved +#define G88PL 0 // reserved + +#define G91PL 1 // SCIRXINTA (SCI-A) +#define G92PL 5 // SCITXINTA (SCI-A) +#define G93PL 3 // SCIRXINTB (SCI-B) +#define G94PL 4 // SCITXINTB (SCI-B) +#define G95PL 1 // ECAN0INTA (ECAN-A) +#define G96PL 1 // ECAN1INTA (ECAN-A) +#define G97PL 2 // ECAN0INTB (ECAN-B) +#define G98PL 4 // ECAN1INTB (ECAN-B) + +#define G101PL 0 // reserved +#define G102PL 0 // reserved +#define G103PL 0 // reserved +#define G104PL 0 // reserved +#define G105PL 0 // reserved +#define G106PL 0 // reserved +#define G107PL 0 // reserved +#define G108PL 0 // reserved + +#define G111PL 0 // reserved +#define G112PL 0 // reserved +#define G113PL 0 // reserved +#define G114PL 0 // reserved +#define G115PL 0 // reserved +#define G116PL 0 // reserved +#define G117PL 0 // reserved +#define G118PL 0 // reserved + +#define G121PL 5 // XINT3 (External) +#define G122PL 3 // XINT4 (External) +#define G123PL 2 // XINT5 (External) +#define G124PL 2 // XINT6 (External) +#define G125PL 1 // XINT7 (External) +#define G126PL 0 // reserved +#define G127PL 6 // LVF (FPA32) +#define G128PL 1 // LUF (FPA32) + + +// There should be no need to modify code below this line +//------------------------------------------------------------------------------- +// Automatically generate IER interrupt masks MINT1 to MINT16: +// + +// Beginning of MINT1: +#if (INT1PL == 0) +#define MINT1_1PL ~(1 << 0) +#else +#define MINT1_1PL 0xFFFF +#endif + +#if (INT2PL >= INT1PL) || (INT2PL == 0) +#define MINT1_2PL ~(1 << 1) +#else +#define MINT1_2PL 0xFFFF +#endif + +#if (INT3PL >= INT1PL) || (INT3PL == 0) +#define MINT1_3PL ~(1 << 2) +#else +#define MINT1_3PL 0xFFFF +#endif + +#if (INT4PL >= INT1PL) || (INT4PL == 0) +#define MINT1_4PL ~(1 << 3) +#else +#define MINT1_4PL 0xFFFF +#endif + +#if (INT5PL >= INT1PL) || (INT5PL == 0) +#define MINT1_5PL ~(1 << 4) +#else +#define MINT1_5PL 0xFFFF +#endif + +#if (INT6PL >= INT1PL) || (INT6PL == 0) +#define MINT1_6PL ~(1 << 5) +#else +#define MINT1_6PL 0xFFFF +#endif + +#if (INT7PL >= INT1PL) || (INT7PL == 0) +#define MINT1_7PL ~(1 << 6) +#else +#define MINT1_7PL 0xFFFF +#endif + +#if (INT8PL >= INT1PL) || (INT8PL == 0) +#define MINT1_8PL ~(1 << 7) +#else +#define MINT1_8PL 0xFFFF +#endif + +#if (INT9PL >= INT1PL) || (INT9PL == 0) +#define MINT1_9PL ~(1 << 8) +#else +#define MINT1_9PL 0xFFFF +#endif + +#if (INT10PL >= INT1PL) || (INT10PL == 0) +#define MINT1_10PL ~(1 << 9) +#else +#define MINT1_10PL 0xFFFF +#endif + +#if (INT11PL >= INT1PL) || (INT11PL == 0) +#define MINT1_11PL ~(1 << 10) +#else +#define MINT1_11PL 0xFFFF +#endif + +#if (INT12PL >= INT1PL) || (INT12PL == 0) +#define MINT1_12PL ~(1 << 11) +#else +#define MINT1_12PL 0xFFFF +#endif + +#if (INT13PL >= INT1PL) || (INT13PL == 0) +#define MINT1_13PL ~(1 << 12) +#else +#define MINT1_13PL 0xFFFF +#endif + +#if (INT14PL >= INT1PL) || (INT14PL == 0) +#define MINT1_14PL ~(1 << 13) +#else +#define MINT1_14PL 0xFFFF +#endif + +#if (INT15PL >= INT1PL) || (INT15PL == 0) +#define MINT1_15PL ~(1 << 14) +#else +#define MINT1_15PL 0xFFFF +#endif + +#if (INT16PL >= INT1PL) || (INT16PL == 0) +#define MINT1_16PL ~(1 << 15) +#else +#define MINT1_16PL 0xFFFF +#endif + +#define MINT1 (MINT1_1PL & MINT1_2PL & MINT1_3PL & MINT1_4PL & \ + MINT1_5PL & MINT1_6PL & MINT1_7PL & MINT1_8PL & \ + MINT1_9PL & MINT1_10PL & MINT1_11PL & MINT1_12PL & \ + MINT1_13PL & MINT1_14PL & MINT1_15PL & MINT1_16PL) +// End Of MINT1. + +// Beginning of MINT2: +#if (INT1PL >= INT2PL) || (INT1PL == 0) +#define MINT2_1PL ~(1 << 0) +#else +#define MINT2_1PL 0xFFFF +#endif + +#if (INT2PL == 0) +#define MINT2_2PL ~(1 << 1) +#else +#define MINT2_2PL 0xFFFF +#endif + +#if (INT3PL >= INT2PL) || (INT3PL == 0) +#define MINT2_3PL ~(1 << 2) +#else +#define MINT2_3PL 0xFFFF +#endif + +#if (INT4PL >= INT2PL) || (INT4PL == 0) +#define MINT2_4PL ~(1 << 3) +#else +#define MINT2_4PL 0xFFFF +#endif + +#if (INT5PL >= INT2PL) || (INT5PL == 0) +#define MINT2_5PL ~(1 << 4) +#else +#define MINT2_5PL 0xFFFF +#endif + +#if (INT6PL >= INT2PL) || (INT6PL == 0) +#define MINT2_6PL ~(1 << 5) +#else +#define MINT2_6PL 0xFFFF +#endif + +#if (INT7PL >= INT2PL) || (INT7PL == 0) +#define MINT2_7PL ~(1 << 6) +#else +#define MINT2_7PL 0xFFFF +#endif + +#if (INT8PL >= INT2PL) || (INT8PL == 0) +#define MINT2_8PL ~(1 << 7) +#else +#define MINT2_8PL 0xFFFF +#endif + +#if (INT9PL >= INT2PL) || (INT9PL == 0) +#define MINT2_9PL ~(1 << 8) +#else +#define MINT2_9PL 0xFFFF +#endif + +#if (INT10PL >= INT2PL) || (INT10PL == 0) +#define MINT2_10PL ~(1 << 9) +#else +#define MINT2_10PL 0xFFFF +#endif + +#if (INT11PL >= INT2PL) || (INT11PL == 0) +#define MINT2_11PL ~(1 << 10) +#else +#define MINT2_11PL 0xFFFF +#endif + +#if (INT12PL >= INT2PL) || (INT12PL == 0) +#define MINT2_12PL ~(1 << 11) +#else +#define MINT2_12PL 0xFFFF +#endif + +#if (INT13PL >= INT2PL) || (INT13PL == 0) +#define MINT2_13PL ~(1 << 12) +#else +#define MINT2_13PL 0xFFFF +#endif + +#if (INT14PL >= INT2PL) || (INT14PL == 0) +#define MINT2_14PL ~(1 << 13) +#else +#define MINT2_14PL 0xFFFF +#endif + +#if (INT15PL >= INT2PL) || (INT15PL == 0) +#define MINT2_15PL ~(1 << 14) +#else +#define MINT2_15PL 0xFFFF +#endif + +#if (INT16PL >= INT2PL) || (INT16PL == 0) +#define MINT2_16PL ~(1 << 15) +#else +#define MINT2_16PL 0xFFFF +#endif + +#define MINT2 (MINT2_1PL & MINT2_2PL & MINT2_3PL & MINT2_4PL & \ + MINT2_5PL & MINT2_6PL & MINT2_7PL & MINT2_8PL & \ + MINT2_9PL & MINT2_10PL & MINT2_11PL & MINT2_12PL & \ + MINT2_13PL & MINT2_14PL & MINT2_15PL & MINT2_16PL) +// End Of MINT2. + +// Beginning of MINT3: +#if (INT1PL >= INT3PL) || (INT1PL == 0) +#define MINT3_1PL ~(1 << 0) +#else +#define MINT3_1PL 0xFFFF +#endif + +#if (INT2PL >= INT3PL) || (INT2PL == 0) +#define MINT3_2PL ~(1 << 1) +#else +#define MINT3_2PL 0xFFFF +#endif + +#if (INT3PL == 0) +#define MINT3_3PL ~(1 << 2) +#else +#define MINT3_3PL 0xFFFF +#endif + +#if (INT4PL >= INT3PL) || (INT4PL == 0) +#define MINT3_4PL ~(1 << 3) +#else +#define MINT3_4PL 0xFFFF +#endif + +#if (INT5PL >= INT3PL) || (INT5PL == 0) +#define MINT3_5PL ~(1 << 4) +#else +#define MINT3_5PL 0xFFFF +#endif + +#if (INT6PL >= INT3PL) || (INT6PL == 0) +#define MINT3_6PL ~(1 << 5) +#else +#define MINT3_6PL 0xFFFF +#endif + +#if (INT7PL >= INT3PL) || (INT7PL == 0) +#define MINT3_7PL ~(1 << 6) +#else +#define MINT3_7PL 0xFFFF +#endif + +#if (INT8PL >= INT3PL) || (INT8PL == 0) +#define MINT3_8PL ~(1 << 7) +#else +#define MINT3_8PL 0xFFFF +#endif + +#if (INT9PL >= INT3PL) || (INT9PL == 0) +#define MINT3_9PL ~(1 << 8) +#else +#define MINT3_9PL 0xFFFF +#endif + +#if (INT10PL >= INT3PL) || (INT10PL == 0) +#define MINT3_10PL ~(1 << 9) +#else +#define MINT3_10PL 0xFFFF +#endif + +#if (INT11PL >= INT3PL) || (INT11PL == 0) +#define MINT3_11PL ~(1 << 10) +#else +#define MINT3_11PL 0xFFFF +#endif + +#if (INT12PL >= INT3PL) || (INT12PL == 0) +#define MINT3_12PL ~(1 << 11) +#else +#define MINT3_12PL 0xFFFF +#endif + +#if (INT13PL >= INT3PL) || (INT13PL == 0) +#define MINT3_13PL ~(1 << 12) +#else +#define MINT3_13PL 0xFFFF +#endif + +#if (INT14PL >= INT3PL) || (INT14PL == 0) +#define MINT3_14PL ~(1 << 13) +#else +#define MINT3_14PL 0xFFFF +#endif + +#if (INT15PL >= INT3PL) || (INT15PL == 0) +#define MINT3_15PL ~(1 << 14) +#else +#define MINT3_15PL 0xFFFF +#endif + +#if (INT16PL >= INT3PL) || (INT16PL == 0) +#define MINT3_16PL ~(1 << 15) +#else +#define MINT3_16PL 0xFFFF +#endif + +#define MINT3 (MINT3_1PL & MINT3_2PL & MINT3_3PL & MINT3_4PL & \ + MINT3_5PL & MINT3_6PL & MINT3_7PL & MINT3_8PL & \ + MINT3_9PL & MINT3_10PL & MINT3_11PL & MINT3_12PL & \ + MINT3_13PL & MINT3_14PL & MINT3_15PL & MINT3_16PL) +// End Of MINT3. + +// Beginning of MINT4: +#if (INT1PL >= INT4PL) || (INT1PL == 0) +#define MINT4_1PL ~(1 << 0) +#else +#define MINT4_1PL 0xFFFF +#endif + +#if (INT2PL >= INT4PL) || (INT2PL == 0) +#define MINT4_2PL ~(1 << 1) +#else +#define MINT4_2PL 0xFFFF +#endif + +#if (INT3PL >= INT4PL) || (INT3PL == 0) +#define MINT4_3PL ~(1 << 2) +#else +#define MINT4_3PL 0xFFFF +#endif + +#if (INT4PL == 0) +#define MINT4_4PL ~(1 << 3) +#else +#define MINT4_4PL 0xFFFF +#endif + +#if (INT5PL >= INT4PL) || (INT5PL == 0) +#define MINT4_5PL ~(1 << 4) +#else +#define MINT4_5PL 0xFFFF +#endif + +#if (INT6PL >= INT4PL) || (INT6PL == 0) +#define MINT4_6PL ~(1 << 5) +#else +#define MINT4_6PL 0xFFFF +#endif + +#if (INT7PL >= INT4PL) || (INT7PL == 0) +#define MINT4_7PL ~(1 << 6) +#else +#define MINT4_7PL 0xFFFF +#endif + +#if (INT8PL >= INT4PL) || (INT8PL == 0) +#define MINT4_8PL ~(1 << 7) +#else +#define MINT4_8PL 0xFFFF +#endif + +#if (INT9PL >= INT4PL) || (INT9PL == 0) +#define MINT4_9PL ~(1 << 8) +#else +#define MINT4_9PL 0xFFFF +#endif + +#if (INT10PL >= INT4PL) || (INT10PL == 0) +#define MINT4_10PL ~(1 << 9) +#else +#define MINT4_10PL 0xFFFF +#endif + +#if (INT11PL >= INT4PL) || (INT11PL == 0) +#define MINT4_11PL ~(1 << 10) +#else +#define MINT4_11PL 0xFFFF +#endif + +#if (INT12PL >= INT4PL) || (INT12PL == 0) +#define MINT4_12PL ~(1 << 11) +#else +#define MINT4_12PL 0xFFFF +#endif + +#if (INT13PL >= INT4PL) || (INT13PL == 0) +#define MINT4_13PL ~(1 << 12) +#else +#define MINT4_13PL 0xFFFF +#endif + +#if (INT14PL >= INT4PL) || (INT14PL == 0) +#define MINT4_14PL ~(1 << 13) +#else +#define MINT4_14PL 0xFFFF +#endif + +#if (INT15PL >= INT4PL) || (INT15PL == 0) +#define MINT4_15PL ~(1 << 14) +#else +#define MINT4_15PL 0xFFFF +#endif + +#if (INT16PL >= INT4PL) || (INT16PL == 0) +#define MINT4_16PL ~(1 << 15) +#else +#define MINT4_16PL 0xFFFF +#endif + +#define MINT4 (MINT4_1PL & MINT4_2PL & MINT4_3PL & MINT4_4PL & \ + MINT4_5PL & MINT4_6PL & MINT4_7PL & MINT4_8PL & \ + MINT4_9PL & MINT4_10PL & MINT4_11PL & MINT4_12PL & \ + MINT4_13PL & MINT4_14PL & MINT4_15PL & MINT4_16PL) +// End Of MINT4. + +// Beginning of MINT5: +#if (INT1PL >= INT5PL) || (INT1PL == 0) +#define MINT5_1PL ~(1 << 0) +#else +#define MINT5_1PL 0xFFFF +#endif + +#if (INT2PL >= INT5PL) || (INT2PL == 0) +#define MINT5_2PL ~(1 << 1) +#else +#define MINT5_2PL 0xFFFF +#endif + +#if (INT3PL >= INT5PL) || (INT3PL == 0) +#define MINT5_3PL ~(1 << 2) +#else +#define MINT5_3PL 0xFFFF +#endif + +#if (INT4PL >= INT5PL) || (INT4PL == 0) +#define MINT5_4PL ~(1 << 3) +#else +#define MINT5_4PL 0xFFFF +#endif + +#if (INT5PL == 0) +#define MINT5_5PL ~(1 << 4) +#else +#define MINT5_5PL 0xFFFF +#endif + +#if (INT6PL >= INT5PL) || (INT6PL == 0) +#define MINT5_6PL ~(1 << 5) +#else +#define MINT5_6PL 0xFFFF +#endif + +#if (INT7PL >= INT5PL) || (INT7PL == 0) +#define MINT5_7PL ~(1 << 6) +#else +#define MINT5_7PL 0xFFFF +#endif + +#if (INT8PL >= INT5PL) || (INT8PL == 0) +#define MINT5_8PL ~(1 << 7) +#else +#define MINT5_8PL 0xFFFF +#endif + +#if (INT9PL >= INT5PL) || (INT9PL == 0) +#define MINT5_9PL ~(1 << 8) +#else +#define MINT5_9PL 0xFFFF +#endif + +#if (INT10PL >= INT5PL) || (INT10PL == 0) +#define MINT5_10PL ~(1 << 9) +#else +#define MINT5_10PL 0xFFFF +#endif + +#if (INT11PL >= INT5PL) || (INT11PL == 0) +#define MINT5_11PL ~(1 << 10) +#else +#define MINT5_11PL 0xFFFF +#endif + +#if (INT12PL >= INT5PL) || (INT12PL == 0) +#define MINT5_12PL ~(1 << 11) +#else +#define MINT5_12PL 0xFFFF +#endif + +#if (INT13PL >= INT5PL) || (INT13PL == 0) +#define MINT5_13PL ~(1 << 12) +#else +#define MINT5_13PL 0xFFFF +#endif + +#if (INT14PL >= INT5PL) || (INT14PL == 0) +#define MINT5_14PL ~(1 << 13) +#else +#define MINT5_14PL 0xFFFF +#endif + +#if (INT15PL >= INT5PL) || (INT15PL == 0) +#define MINT5_15PL ~(1 << 14) +#else +#define MINT5_15PL 0xFFFF +#endif + +#if (INT16PL >= INT5PL) || (INT16PL == 0) +#define MINT5_16PL ~(1 << 15) +#else +#define MINT5_16PL 0xFFFF +#endif + +#define MINT5 (MINT5_1PL & MINT5_2PL & MINT5_3PL & MINT5_4PL & \ + MINT5_5PL & MINT5_6PL & MINT5_7PL & MINT5_8PL & \ + MINT5_9PL & MINT5_10PL & MINT5_11PL & MINT5_12PL & \ + MINT5_13PL & MINT5_14PL & MINT5_15PL & MINT5_16PL) +// End Of MINT5. + +// Beginning of MINT6: +#if (INT1PL >= INT6PL) || (INT1PL == 0) +#define MINT6_1PL ~(1 << 0) +#else +#define MINT6_1PL 0xFFFF +#endif + +#if (INT2PL >= INT6PL) || (INT2PL == 0) +#define MINT6_2PL ~(1 << 1) +#else +#define MINT6_2PL 0xFFFF +#endif + +#if (INT3PL >= INT6PL) || (INT3PL == 0) +#define MINT6_3PL ~(1 << 2) +#else +#define MINT6_3PL 0xFFFF +#endif + +#if (INT4PL >= INT6PL) || (INT4PL == 0) +#define MINT6_4PL ~(1 << 3) +#else +#define MINT6_4PL 0xFFFF +#endif + +#if (INT5PL >= INT6PL) || (INT5PL == 0) +#define MINT6_5PL ~(1 << 4) +#else +#define MINT6_5PL 0xFFFF +#endif + +#if (INT6PL == 0) +#define MINT6_6PL ~(1 << 5) +#else +#define MINT6_6PL 0xFFFF +#endif + +#if (INT7PL >= INT6PL) || (INT7PL == 0) +#define MINT6_7PL ~(1 << 6) +#else +#define MINT6_7PL 0xFFFF +#endif + +#if (INT8PL >= INT6PL) || (INT8PL == 0) +#define MINT6_8PL ~(1 << 7) +#else +#define MINT6_8PL 0xFFFF +#endif + +#if (INT9PL >= INT6PL) || (INT9PL == 0) +#define MINT6_9PL ~(1 << 8) +#else +#define MINT6_9PL 0xFFFF +#endif + +#if (INT10PL >= INT6PL) || (INT10PL == 0) +#define MINT6_10PL ~(1 << 9) +#else +#define MINT6_10PL 0xFFFF +#endif + +#if (INT11PL >= INT6PL) || (INT11PL == 0) +#define MINT6_11PL ~(1 << 10) +#else +#define MINT6_11PL 0xFFFF +#endif + +#if (INT12PL >= INT6PL) || (INT12PL == 0) +#define MINT6_12PL ~(1 << 11) +#else +#define MINT6_12PL 0xFFFF +#endif + +#if (INT13PL >= INT6PL) || (INT13PL == 0) +#define MINT6_13PL ~(1 << 12) +#else +#define MINT6_13PL 0xFFFF +#endif + +#if (INT14PL >= INT6PL) || (INT14PL == 0) +#define MINT6_14PL ~(1 << 13) +#else +#define MINT6_14PL 0xFFFF +#endif + +#if (INT15PL >= INT6PL) || (INT15PL == 0) +#define MINT6_15PL ~(1 << 14) +#else +#define MINT6_15PL 0xFFFF +#endif + +#if (INT16PL >= INT6PL) || (INT16PL == 0) +#define MINT6_16PL ~(1 << 15) +#else +#define MINT6_16PL 0xFFFF +#endif + +#define MINT6 (MINT6_1PL & MINT6_2PL & MINT6_3PL & MINT6_4PL & \ + MINT6_5PL & MINT6_6PL & MINT6_7PL & MINT6_8PL & \ + MINT6_9PL & MINT6_10PL & MINT6_11PL & MINT6_12PL & \ + MINT6_13PL & MINT6_14PL & MINT6_15PL & MINT6_16PL) +// End Of MINT6. + +// Beginning of MINT7: +#if (INT1PL >= INT7PL) || (INT1PL == 0) +#define MINT7_1PL ~(1 << 0) +#else +#define MINT7_1PL 0xFFFF +#endif + +#if (INT2PL >= INT7PL) || (INT2PL == 0) +#define MINT7_2PL ~(1 << 1) +#else +#define MINT7_2PL 0xFFFF +#endif + +#if (INT3PL >= INT7PL) || (INT3PL == 0) +#define MINT7_3PL ~(1 << 2) +#else +#define MINT7_3PL 0xFFFF +#endif + +#if (INT4PL >= INT7PL) || (INT4PL == 0) +#define MINT7_4PL ~(1 << 3) +#else +#define MINT7_4PL 0xFFFF +#endif + +#if (INT5PL >= INT7PL) || (INT5PL == 0) +#define MINT7_5PL ~(1 << 4) +#else +#define MINT7_5PL 0xFFFF +#endif + +#if (INT6PL >= INT7PL) || (INT6PL == 0) +#define MINT7_6PL ~(1 << 5) +#else +#define MINT7_6PL 0xFFFF +#endif + +#if (INT7PL == 0) +#define MINT7_7PL ~(1 << 6) +#else +#define MINT7_7PL 0xFFFF +#endif + +#if (INT8PL >= INT7PL) || (INT8PL == 0) +#define MINT7_8PL ~(1 << 7) +#else +#define MINT7_8PL 0xFFFF +#endif + +#if (INT9PL >= INT7PL) || (INT9PL == 0) +#define MINT7_9PL ~(1 << 8) +#else +#define MINT7_9PL 0xFFFF +#endif + +#if (INT10PL >= INT7PL) || (INT10PL == 0) +#define MINT7_10PL ~(1 << 9) +#else +#define MINT7_10PL 0xFFFF +#endif + +#if (INT11PL >= INT7PL) || (INT11PL == 0) +#define MINT7_11PL ~(1 << 10) +#else +#define MINT7_11PL 0xFFFF +#endif + +#if (INT12PL >= INT7PL) || (INT12PL == 0) +#define MINT7_12PL ~(1 << 11) +#else +#define MINT7_12PL 0xFFFF +#endif + +#if (INT13PL >= INT7PL) || (INT13PL == 0) +#define MINT7_13PL ~(1 << 12) +#else +#define MINT7_13PL 0xFFFF +#endif + +#if (INT14PL >= INT7PL) || (INT14PL == 0) +#define MINT7_14PL ~(1 << 13) +#else +#define MINT7_14PL 0xFFFF +#endif + +#if (INT15PL >= INT7PL) || (INT15PL == 0) +#define MINT7_15PL ~(1 << 14) +#else +#define MINT7_15PL 0xFFFF +#endif + +#if (INT16PL >= INT7PL) || (INT16PL == 0) +#define MINT7_16PL ~(1 << 15) +#else +#define MINT7_16PL 0xFFFF +#endif + +#define MINT7 (MINT7_1PL & MINT7_2PL & MINT7_3PL & MINT7_4PL & \ + MINT7_5PL & MINT7_6PL & MINT7_7PL & MINT7_8PL & \ + MINT7_9PL & MINT7_10PL & MINT7_11PL & MINT7_12PL & \ + MINT7_13PL & MINT7_14PL & MINT7_15PL & MINT7_16PL) +// End Of MINT7. + +// Beginning of MINT8: +#if (INT1PL >= INT8PL) || (INT1PL == 0) +#define MINT8_1PL ~(1 << 0) +#else +#define MINT8_1PL 0xFFFF +#endif + +#if (INT2PL >= INT8PL) || (INT2PL == 0) +#define MINT8_2PL ~(1 << 1) +#else +#define MINT8_2PL 0xFFFF +#endif + +#if (INT3PL >= INT8PL) || (INT3PL == 0) +#define MINT8_3PL ~(1 << 2) +#else +#define MINT8_3PL 0xFFFF +#endif + +#if (INT4PL >= INT8PL) || (INT4PL == 0) +#define MINT8_4PL ~(1 << 3) +#else +#define MINT8_4PL 0xFFFF +#endif + +#if (INT5PL >= INT8PL) || (INT5PL == 0) +#define MINT8_5PL ~(1 << 4) +#else +#define MINT8_5PL 0xFFFF +#endif + +#if (INT6PL >= INT8PL) || (INT6PL == 0) +#define MINT8_6PL ~(1 << 5) +#else +#define MINT8_6PL 0xFFFF +#endif + +#if (INT7PL >= INT8PL) || (INT7PL == 0) +#define MINT8_7PL ~(1 << 6) +#else +#define MINT8_7PL 0xFFFF +#endif + +#if (INT8PL == 0) +#define MINT8_8PL ~(1 << 7) +#else +#define MINT8_8PL 0xFFFF +#endif + +#if (INT9PL >= INT8PL) || (INT9PL == 0) +#define MINT8_9PL ~(1 << 8) +#else +#define MINT8_9PL 0xFFFF +#endif + +#if (INT10PL >= INT8PL) || (INT10PL == 0) +#define MINT8_10PL ~(1 << 9) +#else +#define MINT8_10PL 0xFFFF +#endif + +#if (INT11PL >= INT8PL) || (INT11PL == 0) +#define MINT8_11PL ~(1 << 10) +#else +#define MINT8_11PL 0xFFFF +#endif + +#if (INT12PL >= INT8PL) || (INT12PL == 0) +#define MINT8_12PL ~(1 << 11) +#else +#define MINT8_12PL 0xFFFF +#endif + +#if (INT13PL >= INT8PL) || (INT13PL == 0) +#define MINT8_13PL ~(1 << 12) +#else +#define MINT8_13PL 0xFFFF +#endif + +#if (INT14PL >= INT8PL) || (INT14PL == 0) +#define MINT8_14PL ~(1 << 13) +#else +#define MINT8_14PL 0xFFFF +#endif + +#if (INT15PL >= INT8PL) || (INT15PL == 0) +#define MINT8_15PL ~(1 << 14) +#else +#define MINT8_15PL 0xFFFF +#endif + +#if (INT16PL >= INT8PL) || (INT16PL == 0) +#define MINT8_16PL ~(1 << 15) +#else +#define MINT8_16PL 0xFFFF +#endif + +#define MINT8 (MINT8_1PL & MINT8_2PL & MINT8_3PL & MINT8_4PL & \ + MINT8_5PL & MINT8_6PL & MINT8_7PL & MINT8_8PL & \ + MINT8_9PL & MINT8_10PL & MINT8_11PL & MINT8_12PL & \ + MINT8_13PL & MINT8_14PL & MINT8_15PL & MINT8_16PL) +// End Of MINT8. + +// Beginning of MINT9: +#if (INT1PL >= INT9PL) || (INT1PL == 0) +#define MINT9_1PL ~(1 << 0) +#else +#define MINT9_1PL 0xFFFF +#endif + +#if (INT2PL >= INT9PL) || (INT2PL == 0) +#define MINT9_2PL ~(1 << 1) +#else +#define MINT9_2PL 0xFFFF +#endif + +#if (INT3PL >= INT9PL) || (INT3PL == 0) +#define MINT9_3PL ~(1 << 2) +#else +#define MINT9_3PL 0xFFFF +#endif + +#if (INT4PL >= INT9PL) || (INT4PL == 0) +#define MINT9_4PL ~(1 << 3) +#else +#define MINT9_4PL 0xFFFF +#endif + +#if (INT5PL >= INT9PL) || (INT5PL == 0) +#define MINT9_5PL ~(1 << 4) +#else +#define MINT9_5PL 0xFFFF +#endif + +#if (INT6PL >= INT9PL) || (INT6PL == 0) +#define MINT9_6PL ~(1 << 5) +#else +#define MINT9_6PL 0xFFFF +#endif + +#if (INT7PL >= INT9PL) || (INT7PL == 0) +#define MINT9_7PL ~(1 << 6) +#else +#define MINT9_7PL 0xFFFF +#endif + +#if (INT8PL >= INT9PL) || (INT8PL == 0) +#define MINT9_8PL ~(1 << 7) +#else +#define MINT9_8PL 0xFFFF +#endif + +#if (INT9PL == 0) +#define MINT9_9PL ~(1 << 8) +#else +#define MINT9_9PL 0xFFFF +#endif + +#if (INT10PL >= INT9PL) || (INT10PL == 0) +#define MINT9_10PL ~(1 << 9) +#else +#define MINT9_10PL 0xFFFF +#endif + +#if (INT11PL >= INT9PL) || (INT11PL == 0) +#define MINT9_11PL ~(1 << 10) +#else +#define MINT9_11PL 0xFFFF +#endif + +#if (INT12PL >= INT9PL) || (INT12PL == 0) +#define MINT9_12PL ~(1 << 11) +#else +#define MINT9_12PL 0xFFFF +#endif + +#if (INT13PL >= INT9PL) || (INT13PL == 0) +#define MINT9_13PL ~(1 << 12) +#else +#define MINT9_13PL 0xFFFF +#endif + +#if (INT14PL >= INT9PL) || (INT14PL == 0) +#define MINT9_14PL ~(1 << 13) +#else +#define MINT9_14PL 0xFFFF +#endif + +#if (INT15PL >= INT9PL) || (INT15PL == 0) +#define MINT9_15PL ~(1 << 14) +#else +#define MINT9_15PL 0xFFFF +#endif + +#if (INT16PL >= INT9PL) || (INT16PL == 0) +#define MINT9_16PL ~(1 << 15) +#else +#define MINT9_16PL 0xFFFF +#endif + +#define MINT9 (MINT9_1PL & MINT9_2PL & MINT9_3PL & MINT9_4PL & \ + MINT9_5PL & MINT9_6PL & MINT9_7PL & MINT9_8PL & \ + MINT9_9PL & MINT9_10PL & MINT9_11PL & MINT9_12PL & \ + MINT9_13PL & MINT9_14PL & MINT9_15PL & MINT9_16PL) +// End Of MINT9. + +// Beginning of MINT10: +#if (INT1PL >= INT10PL) || (INT1PL == 0) +#define MINT10_1PL ~(1 << 0) +#else +#define MINT10_1PL 0xFFFF +#endif + +#if (INT2PL >= INT10PL) || (INT2PL == 0) +#define MINT10_2PL ~(1 << 1) +#else +#define MINT10_2PL 0xFFFF +#endif + +#if (INT3PL >= INT10PL) || (INT3PL == 0) +#define MINT10_3PL ~(1 << 2) +#else +#define MINT10_3PL 0xFFFF +#endif + +#if (INT4PL >= INT10PL) || (INT4PL == 0) +#define MINT10_4PL ~(1 << 3) +#else +#define MINT10_4PL 0xFFFF +#endif + +#if (INT5PL >= INT10PL) || (INT5PL == 0) +#define MINT10_5PL ~(1 << 4) +#else +#define MINT10_5PL 0xFFFF +#endif + +#if (INT6PL >= INT10PL) || (INT6PL == 0) +#define MINT10_6PL ~(1 << 5) +#else +#define MINT10_6PL 0xFFFF +#endif + +#if (INT7PL >= INT10PL) || (INT7PL == 0) +#define MINT10_7PL ~(1 << 6) +#else +#define MINT10_7PL 0xFFFF +#endif + +#if (INT8PL >= INT10PL) || (INT8PL == 0) +#define MINT10_8PL ~(1 << 7) +#else +#define MINT10_8PL 0xFFFF +#endif + +#if (INT9PL >= INT10PL) || (INT9PL == 0) +#define MINT10_9PL ~(1 << 8) +#else +#define MINT10_9PL 0xFFFF +#endif + +#if (INT10PL == 0) +#define MINT10_10PL ~(1 << 9) +#else +#define MINT10_10PL 0xFFFF +#endif + +#if (INT11PL >= INT10PL) || (INT11PL == 0) +#define MINT10_11PL ~(1 << 10) +#else +#define MINT10_11PL 0xFFFF +#endif + +#if (INT12PL >= INT10PL) || (INT12PL == 0) +#define MINT10_12PL ~(1 << 11) +#else +#define MINT10_12PL 0xFFFF +#endif + +#if (INT13PL >= INT10PL) || (INT13PL == 0) +#define MINT10_13PL ~(1 << 12) +#else +#define MINT10_13PL 0xFFFF +#endif + +#if (INT14PL >= INT10PL) || (INT14PL == 0) +#define MINT10_14PL ~(1 << 13) +#else +#define MINT10_14PL 0xFFFF +#endif + +#if (INT15PL >= INT10PL) || (INT15PL == 0) +#define MINT10_15PL ~(1 << 14) +#else +#define MINT10_15PL 0xFFFF +#endif + +#if (INT16PL >= INT10PL) || (INT16PL == 0) +#define MINT10_16PL ~(1 << 15) +#else +#define MINT10_16PL 0xFFFF +#endif + +#define MINT10 (MINT10_1PL & MINT10_2PL & MINT10_3PL & MINT10_4PL & \ + MINT10_5PL & MINT10_6PL & MINT10_7PL & MINT10_8PL & \ + MINT10_9PL & MINT10_10PL & MINT10_11PL & MINT10_12PL & \ + MINT10_13PL & MINT10_14PL & MINT10_15PL & MINT10_16PL) +// End Of MINT10. + +// Beginning of MINT11: +#if (INT1PL >= INT11PL) || (INT1PL == 0) +#define MINT11_1PL ~(1 << 0) +#else +#define MINT11_1PL 0xFFFF +#endif + +#if (INT2PL >= INT11PL) || (INT2PL == 0) +#define MINT11_2PL ~(1 << 1) +#else +#define MINT11_2PL 0xFFFF +#endif + +#if (INT3PL >= INT11PL) || (INT3PL == 0) +#define MINT11_3PL ~(1 << 2) +#else +#define MINT11_3PL 0xFFFF +#endif + +#if (INT4PL >= INT11PL) || (INT4PL == 0) +#define MINT11_4PL ~(1 << 3) +#else +#define MINT11_4PL 0xFFFF +#endif + +#if (INT5PL >= INT11PL) || (INT5PL == 0) +#define MINT11_5PL ~(1 << 4) +#else +#define MINT11_5PL 0xFFFF +#endif + +#if (INT6PL >= INT11PL) || (INT6PL == 0) +#define MINT11_6PL ~(1 << 5) +#else +#define MINT11_6PL 0xFFFF +#endif + +#if (INT7PL >= INT11PL) || (INT7PL == 0) +#define MINT11_7PL ~(1 << 6) +#else +#define MINT11_7PL 0xFFFF +#endif + +#if (INT8PL >= INT11PL) || (INT8PL == 0) +#define MINT11_8PL ~(1 << 7) +#else +#define MINT11_8PL 0xFFFF +#endif + +#if (INT9PL >= INT11PL) || (INT9PL == 0) +#define MINT11_9PL ~(1 << 8) +#else +#define MINT11_9PL 0xFFFF +#endif + +#if (INT10PL >= INT11PL) || (INT10PL == 0) +#define MINT11_10PL ~(1 << 9) +#else +#define MINT11_10PL 0xFFFF +#endif + +#if (INT11PL == 0) +#define MINT11_11PL ~(1 << 10) +#else +#define MINT11_11PL 0xFFFF +#endif + +#if (INT12PL >= INT11PL) || (INT12PL == 0) +#define MINT11_12PL ~(1 << 11) +#else +#define MINT11_12PL 0xFFFF +#endif + +#if (INT13PL >= INT11PL) || (INT13PL == 0) +#define MINT11_13PL ~(1 << 12) +#else +#define MINT11_13PL 0xFFFF +#endif + +#if (INT14PL >= INT11PL) || (INT14PL == 0) +#define MINT11_14PL ~(1 << 13) +#else +#define MINT11_14PL 0xFFFF +#endif + +#if (INT15PL >= INT11PL) || (INT15PL == 0) +#define MINT11_15PL ~(1 << 14) +#else +#define MINT11_15PL 0xFFFF +#endif + +#if (INT16PL >= INT11PL) || (INT16PL == 0) +#define MINT11_16PL ~(1 << 15) +#else +#define MINT11_16PL 0xFFFF +#endif + +#define MINT11 (MINT11_1PL & MINT11_2PL & MINT11_3PL & MINT11_4PL & \ + MINT11_5PL & MINT11_6PL & MINT11_7PL & MINT11_8PL & \ + MINT11_9PL & MINT11_10PL & MINT11_11PL & MINT11_12PL & \ + MINT11_13PL & MINT11_14PL & MINT11_15PL & MINT11_16PL) +// End Of MINT11. + +// Beginning of MINT12: +#if (INT1PL >= INT12PL) || (INT1PL == 0) +#define MINT12_1PL ~(1 << 0) +#else +#define MINT12_1PL 0xFFFF +#endif + +#if (INT2PL >= INT12PL) || (INT2PL == 0) +#define MINT12_2PL ~(1 << 1) +#else +#define MINT12_2PL 0xFFFF +#endif + +#if (INT3PL >= INT12PL) || (INT3PL == 0) +#define MINT12_3PL ~(1 << 2) +#else +#define MINT12_3PL 0xFFFF +#endif + +#if (INT4PL >= INT12PL) || (INT4PL == 0) +#define MINT12_4PL ~(1 << 3) +#else +#define MINT12_4PL 0xFFFF +#endif + +#if (INT5PL >= INT12PL) || (INT5PL == 0) +#define MINT12_5PL ~(1 << 4) +#else +#define MINT12_5PL 0xFFFF +#endif + +#if (INT6PL >= INT12PL) || (INT6PL == 0) +#define MINT12_6PL ~(1 << 5) +#else +#define MINT12_6PL 0xFFFF +#endif + +#if (INT7PL >= INT12PL) || (INT7PL == 0) +#define MINT12_7PL ~(1 << 6) +#else +#define MINT12_7PL 0xFFFF +#endif + +#if (INT8PL >= INT12PL) || (INT8PL == 0) +#define MINT12_8PL ~(1 << 7) +#else +#define MINT12_8PL 0xFFFF +#endif + +#if (INT9PL >= INT12PL) || (INT9PL == 0) +#define MINT12_9PL ~(1 << 8) +#else +#define MINT12_9PL 0xFFFF +#endif + +#if (INT10PL >= INT12PL) || (INT10PL == 0) +#define MINT12_10PL ~(1 << 9) +#else +#define MINT12_10PL 0xFFFF +#endif + +#if (INT11PL >= INT12PL) || (INT11PL == 0) +#define MINT12_11PL ~(1 << 10) +#else +#define MINT12_11PL 0xFFFF +#endif + +#if (INT12PL == 0) +#define MINT12_12PL ~(1 << 11) +#else +#define MINT12_12PL 0xFFFF +#endif + +#if (INT13PL >= INT12PL) || (INT13PL == 0) +#define MINT12_13PL ~(1 << 12) +#else +#define MINT12_13PL 0xFFFF +#endif + +#if (INT14PL >= INT12PL) || (INT14PL == 0) +#define MINT12_14PL ~(1 << 13) +#else +#define MINT12_14PL 0xFFFF +#endif + +#if (INT15PL >= INT12PL) || (INT15PL == 0) +#define MINT12_15PL ~(1 << 14) +#else +#define MINT12_15PL 0xFFFF +#endif + +#if (INT16PL >= INT12PL) || (INT16PL == 0) +#define MINT12_16PL ~(1 << 15) +#else +#define MINT12_16PL 0xFFFF +#endif + +#define MINT12 (MINT12_1PL & MINT12_2PL & MINT12_3PL & MINT12_4PL & \ + MINT12_5PL & MINT12_6PL & MINT12_7PL & MINT12_8PL & \ + MINT12_9PL & MINT12_10PL & MINT12_11PL & MINT12_12PL & \ + MINT12_13PL & MINT12_14PL & MINT12_15PL & MINT12_16PL) +// End Of MINT12. + +// Beginning of MINT13: +#if (INT1PL >= INT13PL) || (INT1PL == 0) +#define MINT13_1PL ~(1 << 0) +#else +#define MINT13_1PL 0xFFFF +#endif + +#if (INT2PL >= INT13PL) || (INT2PL == 0) +#define MINT13_2PL ~(1 << 1) +#else +#define MINT13_2PL 0xFFFF +#endif + +#if (INT3PL >= INT13PL) || (INT3PL == 0) +#define MINT13_3PL ~(1 << 2) +#else +#define MINT13_3PL 0xFFFF +#endif + +#if (INT4PL >= INT13PL) || (INT4PL == 0) +#define MINT13_4PL ~(1 << 3) +#else +#define MINT13_4PL 0xFFFF +#endif + +#if (INT5PL >= INT13PL) || (INT5PL == 0) +#define MINT13_5PL ~(1 << 4) +#else +#define MINT13_5PL 0xFFFF +#endif + +#if (INT6PL >= INT13PL) || (INT6PL == 0) +#define MINT13_6PL ~(1 << 5) +#else +#define MINT13_6PL 0xFFFF +#endif + +#if (INT7PL >= INT13PL) || (INT7PL == 0) +#define MINT13_7PL ~(1 << 6) +#else +#define MINT13_7PL 0xFFFF +#endif + +#if (INT8PL >= INT13PL) || (INT8PL == 0) +#define MINT13_8PL ~(1 << 7) +#else +#define MINT13_8PL 0xFFFF +#endif + +#if (INT9PL >= INT13PL) || (INT9PL == 0) +#define MINT13_9PL ~(1 << 8) +#else +#define MINT13_9PL 0xFFFF +#endif + +#if (INT10PL >= INT13PL) || (INT10PL == 0) +#define MINT13_10PL ~(1 << 9) +#else +#define MINT13_10PL 0xFFFF +#endif + +#if (INT11PL >= INT13PL) || (INT11PL == 0) +#define MINT13_11PL ~(1 << 10) +#else +#define MINT13_11PL 0xFFFF +#endif + +#define MINT13_12PL ~(1 << 11) + +#if (INT13PL == 0) +#define MINT13_13PL ~(1 << 12) +#else +#define MINT13_13PL 0xFFFF +#endif + +#if (INT14PL >= INT13PL) || (INT14PL == 0) +#define MINT13_14PL ~(1 << 13) +#else +#define MINT13_14PL 0xFFFF +#endif + +#if (INT15PL >= INT13PL) || (INT15PL == 0) +#define MINT13_15PL ~(1 << 14) +#else +#define MINT13_15PL 0xFFFF +#endif + +#if (INT16PL >= INT13PL) || (INT16PL == 0) +#define MINT13_16PL ~(1 << 15) +#else +#define MINT13_16PL 0xFFFF +#endif + +#define MINT13 (MINT13_1PL & MINT13_2PL & MINT13_3PL & MINT13_4PL & \ + MINT13_5PL & MINT13_6PL & MINT13_7PL & MINT13_8PL & \ + MINT13_9PL & MINT13_10PL & MINT13_11PL & MINT13_12PL & \ + MINT13_13PL & MINT13_14PL & MINT13_15PL & MINT13_16PL) +// End Of MINT13. + +// Beginning of MINT14: +#if (INT1PL >= INT14PL) || (INT1PL == 0) +#define MINT14_1PL ~(1 << 0) +#else +#define MINT14_1PL 0xFFFF +#endif + +#if (INT2PL >= INT14PL) || (INT2PL == 0) +#define MINT14_2PL ~(1 << 1) +#else +#define MINT14_2PL 0xFFFF +#endif + +#if (INT3PL >= INT14PL) || (INT3PL == 0) +#define MINT14_3PL ~(1 << 2) +#else +#define MINT14_3PL 0xFFFF +#endif + +#if (INT4PL >= INT14PL) || (INT4PL == 0) +#define MINT14_4PL ~(1 << 3) +#else +#define MINT14_4PL 0xFFFF +#endif + +#if (INT5PL >= INT14PL) || (INT5PL == 0) +#define MINT14_5PL ~(1 << 4) +#else +#define MINT14_5PL 0xFFFF +#endif + +#if (INT6PL >= INT14PL) || (INT6PL == 0) +#define MINT14_6PL ~(1 << 5) +#else +#define MINT14_6PL 0xFFFF +#endif + +#if (INT7PL >= INT14PL) || (INT7PL == 0) +#define MINT14_7PL ~(1 << 6) +#else +#define MINT14_7PL 0xFFFF +#endif + +#if (INT8PL >= INT14PL) || (INT8PL == 0) +#define MINT14_8PL ~(1 << 7) +#else +#define MINT14_8PL 0xFFFF +#endif + +#if (INT9PL >= INT14PL) || (INT9PL == 0) +#define MINT14_9PL ~(1 << 8) +#else +#define MINT14_9PL 0xFFFF +#endif + +#if (INT10PL >= INT14PL) || (INT10PL == 0) +#define MINT14_10PL ~(1 << 9) +#else +#define MINT14_10PL 0xFFFF +#endif + +#if (INT11PL >= INT14PL) || (INT11PL == 0) +#define MINT14_11PL ~(1 << 10) +#else +#define MINT14_11PL 0xFFFF +#endif + +#if (INT12PL >= INT14PL) || (INT12PL == 0) +#define MINT14_12PL ~(1 << 11) +#else +#define MINT14_12PL 0xFFFF +#endif + +#if (INT13PL >= INT14PL) || (INT13PL == 0) +#define MINT14_13PL ~(1 << 12) +#else +#define MINT14_13PL 0xFFFF +#endif + +#define MINT14_14PL ~(1 << 13) + +#if (INT15PL >= INT14PL) || (INT15PL == 0) +#define MINT14_15PL ~(1 << 14) +#else +#define MINT14_15PL 0xFFFF +#endif + +#if (INT16PL >= INT14PL) || (INT16PL == 0) +#define MINT14_16PL ~(1 << 15) +#else +#define MINT14_16PL 0xFFFF +#endif + +#define MINT14 (MINT14_1PL & MINT14_2PL & MINT14_3PL & MINT14_4PL & \ + MINT14_5PL & MINT14_6PL & MINT14_7PL & MINT14_8PL & \ + MINT14_9PL & MINT14_10PL & MINT14_11PL & MINT14_12PL & \ + MINT14_13PL & MINT14_14PL & MINT14_15PL & MINT14_16PL) +// End Of MINT14. + +// Beginning of MINT15: +#if (INT1PL >= INT15PL) || (INT1PL == 0) +#define MINT15_1PL ~(1 << 0) +#else +#define MINT15_1PL 0xFFFF +#endif + +#if (INT2PL >= INT15PL) || (INT2PL == 0) +#define MINT15_2PL ~(1 << 1) +#else +#define MINT15_2PL 0xFFFF +#endif + +#if (INT3PL >= INT15PL) || (INT3PL == 0) +#define MINT15_3PL ~(1 << 2) +#else +#define MINT15_3PL 0xFFFF +#endif + +#if (INT4PL >= INT15PL) || (INT4PL == 0) +#define MINT15_4PL ~(1 << 3) +#else +#define MINT15_4PL 0xFFFF +#endif + +#if (INT5PL >= INT15PL) || (INT5PL == 0) +#define MINT15_5PL ~(1 << 4) +#else +#define MINT15_5PL 0xFFFF +#endif + +#if (INT6PL >= INT15PL) || (INT6PL == 0) +#define MINT15_6PL ~(1 << 5) +#else +#define MINT15_6PL 0xFFFF +#endif + +#if (INT7PL >= INT15PL) || (INT7PL == 0) +#define MINT15_7PL ~(1 << 6) +#else +#define MINT15_7PL 0xFFFF +#endif + +#if (INT8PL >= INT15PL) || (INT8PL == 0) +#define MINT15_8PL ~(1 << 7) +#else +#define MINT15_8PL 0xFFFF +#endif + +#if (INT9PL >= INT15PL) || (INT9PL == 0) +#define MINT15_9PL ~(1 << 8) +#else +#define MINT15_9PL 0xFFFF +#endif + +#if (INT10PL >= INT15PL) || (INT10PL == 0) +#define MINT15_10PL ~(1 << 9) +#else +#define MINT15_10PL 0xFFFF +#endif + +#if (INT11PL >= INT15PL) || (INT11PL == 0) +#define MINT15_11PL ~(1 << 10) +#else +#define MINT15_11PL 0xFFFF +#endif + +#if (INT12PL >= INT15PL) || (INT12PL == 0) +#define MINT15_12PL ~(1 << 11) +#else +#define MINT15_12PL 0xFFFF +#endif + +#if (INT13PL >= INT15PL) || (INT13PL == 0) +#define MINT15_13PL ~(1 << 12) +#else +#define MINT15_13PL 0xFFFF +#endif + +#if (INT14PL >= INT15PL) || (INT14PL == 0) +#define MINT15_14PL ~(1 << 13) +#else +#define MINT15_14PL 0xFFFF +#endif + +#define MINT15_15PL ~(1 << 14) + +#if (INT16PL >= INT15PL) || (INT16PL == 0) +#define MINT15_16PL ~(1 << 15) +#else +#define MINT15_16PL 0xFFFF +#endif + +#define MINT15 (MINT15_1PL & MINT15_2PL & MINT15_3PL & MINT15_4PL & \ + MINT15_5PL & MINT15_6PL & MINT15_7PL & MINT15_8PL & \ + MINT15_9PL & MINT15_10PL & MINT15_11PL & MINT15_12PL & \ + MINT15_13PL & MINT15_14PL & MINT15_15PL & MINT15_16PL) +// End Of MINT15. + +// Beginning of MINT16: +#if (INT1PL >= INT16PL) || (INT1PL == 0) +#define MINT16_1PL ~(1 << 0) +#else +#define MINT16_1PL 0xFFFF +#endif + +#if (INT2PL >= INT16PL) || (INT2PL == 0) +#define MINT16_2PL ~(1 << 1) +#else +#define MINT16_2PL 0xFFFF +#endif + +#if (INT3PL >= INT16PL) || (INT3PL == 0) +#define MINT16_3PL ~(1 << 2) +#else +#define MINT16_3PL 0xFFFF +#endif + +#if (INT4PL >= INT16PL) || (INT4PL == 0) +#define MINT16_4PL ~(1 << 3) +#else +#define MINT16_4PL 0xFFFF +#endif + +#if (INT5PL >= INT16PL) || (INT5PL == 0) +#define MINT16_5PL ~(1 << 4) +#else +#define MINT16_5PL 0xFFFF +#endif + +#if (INT6PL >= INT16PL) || (INT6PL == 0) +#define MINT16_6PL ~(1 << 5) +#else +#define MINT16_6PL 0xFFFF +#endif + +#if (INT7PL >= INT16PL) || (INT7PL == 0) +#define MINT16_7PL ~(1 << 6) +#else +#define MINT16_7PL 0xFFFF +#endif + +#if (INT8PL >= INT16PL) || (INT8PL == 0) +#define MINT16_8PL ~(1 << 7) +#else +#define MINT16_8PL 0xFFFF +#endif + +#if (INT9PL >= INT16PL) || (INT9PL == 0) +#define MINT16_9PL ~(1 << 8) +#else +#define MINT16_9PL 0xFFFF +#endif + +#if (INT10PL >= INT16PL) || (INT10PL == 0) +#define MINT16_10PL ~(1 << 9) +#else +#define MINT16_10PL 0xFFFF +#endif + +#if (INT11PL >= INT16PL) || (INT11PL == 0) +#define MINT16_11PL ~(1 << 10) +#else +#define MINT16_11PL 0xFFFF +#endif + +#if (INT12PL >= INT16PL) || (INT12PL == 0) +#define MINT16_12PL ~(1 << 11) +#else +#define MINT16_12PL 0xFFFF +#endif + +#if (INT13PL >= INT16PL) || (INT13PL == 0) +#define MINT16_13PL ~(1 << 12) +#else +#define MINT16_13PL 0xFFFF +#endif + +#if (INT14PL >= INT16PL) || (INT14PL == 0) +#define MINT16_14PL ~(1 << 13) +#else +#define MINT16_14PL 0xFFFF +#endif + +#if (INT15PL >= INT16PL) || (INT15PL == 0) +#define MINT16_15PL ~(1 << 14) +#else +#define MINT16_15PL 0xFFFF +#endif + +#define MINT16_16PL ~(1 << 15) + +#define MINT16 (MINT16_1PL & MINT16_2PL & MINT16_3PL & MINT16_4PL & \ + MINT16_5PL & MINT16_6PL & MINT16_7PL & MINT16_8PL & \ + MINT16_9PL & MINT16_10PL & MINT16_11PL & MINT16_12PL & \ + MINT16_13PL & MINT16_14PL & MINT16_15PL & MINT16_16PL) +// End Of MINT16. + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG11 to MG18: + +// Beginning of MG11: +#if (G12PL >= G11PL) || (G12PL == 0) +#define MG11_12PL ~(1 << 1) +#else +#define MG11_12PL 0xFFFF +#endif + +#if (G13PL >= G11PL) || (G13PL == 0) +#define MG11_13PL ~(1 << 2) +#else +#define MG11_13PL 0xFFFF +#endif + +#if (G14PL >= G11PL) || (G14PL == 0) +#define MG11_14PL ~(1 << 3) +#else +#define MG11_14PL 0xFFFF +#endif + +#if (G15PL >= G11PL) || (G15PL == 0) +#define MG11_15PL ~(1 << 4) +#else +#define MG11_15PL 0xFFFF +#endif + +#if (G16PL >= G11PL) || (G16PL == 0) +#define MG11_16PL ~(1 << 5) +#else +#define MG11_16PL 0xFFFF +#endif + +#if (G17PL >= G11PL) || (G17PL == 0) +#define MG11_17PL ~(1 << 6) +#else +#define MG11_17PL 0xFFFF +#endif + +#if (G18PL >= G11PL) || (G18PL == 0) +#define MG11_18PL ~(1 << 7) +#else +#define MG11_18PL 0xFFFF +#endif + +#define MG11_11PL 0x00FE +#define MG11 (MG11_11PL & MG11_12PL & MG11_13PL & MG11_14PL & \ + MG11_15PL & MG11_16PL & MG11_17PL & MG11_18PL) +// End of MG11: + +// Beginning of MG12: +#if (G11PL >= G12PL) || (G11PL == 0) +#define MG12_11PL ~(1) +#else +#define MG12_11PL 0xFFFF +#endif +#if (G13PL >= G12PL) || (G13PL == 0) +#define MG12_13PL ~(1 << 2) +#else +#define MG12_13PL 0xFFFF +#endif +#if (G14PL >= G12PL) || (G14PL == 0) +#define MG12_14PL ~(1 << 3) +#else +#define MG12_14PL 0xFFFF +#endif +#if (G15PL >= G12PL) || (G15PL == 0) +#define MG12_15PL ~(1 << 4) +#else +#define MG12_15PL 0xFFFF +#endif +#if (G16PL >= G12PL) || (G16PL == 0) +#define MG12_16PL ~(1 << 5) +#else +#define MG12_16PL 0xFFFF +#endif +#if (G17PL >= G12PL) || (G17PL == 0) +#define MG12_17PL ~(1 << 6) +#else +#define MG12_17PL 0xFFFF +#endif +#if (G18PL >= G12PL) || (G18PL == 0) +#define MG12_18PL ~(1 << 7) +#else +#define MG12_18PL 0xFFFF +#endif +#define MG12_12PL 0x00FD +#define MG12 (MG12_11PL & MG12_12PL & MG12_13PL & MG12_14PL & \ + MG12_15PL & MG12_16PL & MG12_17PL & MG12_18PL) +// End of MG12: + +// Beginning of MG13: +#if (G11PL >= G13PL) || (G11PL == 0) +#define MG13_11PL ~(1) +#else +#define MG13_11PL 0xFFFF +#endif +#if (G12PL >= G13PL) || (G12PL == 0) +#define MG13_12PL ~(1 << 1) +#else +#define MG13_12PL 0xFFFF +#endif +#if (G14PL >= G13PL) || (G14PL == 0) +#define MG13_14PL ~(1 << 3) +#else +#define MG13_14PL 0xFFFF +#endif +#if (G15PL >= G13PL) || (G15PL == 0) +#define MG13_15PL ~(1 << 4) +#else +#define MG13_15PL 0xFFFF +#endif +#if (G16PL >= G13PL) || (G16PL == 0) +#define MG13_16PL ~(1 << 5) +#else +#define MG13_16PL 0xFFFF +#endif +#if (G17PL >= G13PL) || (G17PL == 0) +#define MG13_17PL ~(1 << 6) +#else +#define MG13_17PL 0xFFFF +#endif +#if (G18PL >= G13PL) || (G18PL == 0) +#define MG13_18PL ~(1 << 7) +#else +#define MG13_18PL 0xFFFF +#endif +#define MG13_13PL 0x00FB +#define MG13 (MG13_11PL & MG13_12PL & MG13_13PL & MG13_14PL & \ + MG13_15PL & MG13_16PL & MG13_17PL & MG13_18PL) +// End of MG13: + +// Beginning of MG14: +#if (G11PL >= G14PL) || (G11PL == 0) +#define MG14_11PL ~(1) +#else +#define MG14_11PL 0xFFFF +#endif +#if (G12PL >= G14PL) || (G12PL == 0) +#define MG14_12PL ~(1 << 1) +#else +#define MG14_12PL 0xFFFF +#endif +#if (G13PL >= G14PL) || (G13PL == 0) +#define MG14_13PL ~(1 << 2) +#else +#define MG14_13PL 0xFFFF +#endif +#if (G15PL >= G14PL) || (G15PL == 0) +#define MG14_15PL ~(1 << 4) +#else +#define MG14_15PL 0xFFFF +#endif +#if (G16PL >= G14PL) || (G16PL == 0) +#define MG14_16PL ~(1 << 5) +#else +#define MG14_16PL 0xFFFF +#endif +#if (G17PL >= G14PL) || (G17PL == 0) +#define MG14_17PL ~(1 << 6) +#else +#define MG14_17PL 0xFFFF +#endif +#if (G18PL >= G14PL) || (G18PL == 0) +#define MG14_18PL ~(1 << 7) +#else +#define MG14_18PL 0xFFFF +#endif +#define MG14_14PL 0x00F7 +#define MG14 (MG14_11PL & MG14_12PL & MG14_13PL & MG14_14PL & \ + MG14_15PL & MG14_16PL & MG14_17PL & MG14_18PL) +// End of MG14: + +// Beginning of MG15: +#if (G11PL >= G15PL) || (G11PL == 0) +#define MG15_11PL ~(1) +#else +#define MG15_11PL 0xFFFF +#endif +#if (G12PL >= G15PL) || (G12PL == 0) +#define MG15_12PL ~(1 << 1) +#else +#define MG15_12PL 0xFFFF +#endif +#if (G13PL >= G15PL) || (G13PL == 0) +#define MG15_13PL ~(1 << 2) +#else +#define MG15_13PL 0xFFFF +#endif +#if (G14PL >= G15PL) || (G14PL == 0) +#define MG15_14PL ~(1 << 3) +#else +#define MG15_14PL 0xFFFF +#endif +#if (G16PL >= G15PL) || (G16PL == 0) +#define MG15_16PL ~(1 << 5) +#else +#define MG15_16PL 0xFFFF +#endif +#if (G17PL >= G15PL) || (G17PL == 0) +#define MG15_17PL ~(1 << 6) +#else +#define MG15_17PL 0xFFFF +#endif +#if (G18PL >= G15PL) || (G18PL == 0) +#define MG15_18PL ~(1 << 7) +#else +#define MG15_18PL 0xFFFF +#endif +#define MG15_15PL 0x00EF +#define MG15 (MG15_11PL & MG15_12PL & MG15_13PL & MG15_14PL & \ + MG15_15PL & MG15_16PL & MG15_17PL & MG15_18PL) +// End of MG15: + +// Beginning of MG16: +#if (G11PL >= G16PL) || (G11PL == 0) +#define MG16_11PL ~(1) +#else +#define MG16_11PL 0xFFFF +#endif +#if (G12PL >= G16PL) || (G12PL == 0) +#define MG16_12PL ~(1 << 1) +#else +#define MG16_12PL 0xFFFF +#endif +#if (G13PL >= G16PL) || (G13PL == 0) +#define MG16_13PL ~(1 << 2) +#else +#define MG16_13PL 0xFFFF +#endif +#if (G14PL >= G16PL) || (G14PL == 0) +#define MG16_14PL ~(1 << 3) +#else +#define MG16_14PL 0xFFFF +#endif +#if (G15PL >= G16PL) || (G15PL == 0) +#define MG16_15PL ~(1 << 4) +#else +#define MG16_15PL 0xFFFF +#endif +#if (G17PL >= G16PL) || (G17PL == 0) +#define MG16_17PL ~(1 << 6) +#else +#define MG16_17PL 0xFFFF +#endif +#if (G18PL >= G16PL) || (G18PL == 0) +#define MG16_18PL ~(1 << 7) +#else +#define MG16_18PL 0xFFFF +#endif +#define MG16_16PL 0x00DF +#define MG16 (MG16_11PL & MG16_12PL & MG16_13PL & MG16_14PL & \ + MG16_15PL & MG16_16PL & MG16_17PL & MG16_18PL) +// End of MG16: + +// Beginning of MG17: +#if (G11PL >= G17PL) || (G11PL == 0) +#define MG17_11PL ~(1) +#else +#define MG17_11PL 0xFFFF +#endif +#if (G12PL >= G17PL) || (G12PL == 0) +#define MG17_12PL ~(1 << 1) +#else +#define MG17_12PL 0xFFFF +#endif +#if (G13PL >= G17PL) || (G13PL == 0) +#define MG17_13PL ~(1 << 2) +#else +#define MG17_13PL 0xFFFF +#endif +#if (G14PL >= G17PL) || (G14PL == 0) +#define MG17_14PL ~(1 << 3) +#else +#define MG17_14PL 0xFFFF +#endif +#if (G15PL >= G17PL) || (G15PL == 0) +#define MG17_15PL ~(1 << 4) +#else +#define MG17_15PL 0xFFFF +#endif +#if (G16PL >= G17PL) || (G16PL == 0) +#define MG17_16PL ~(1 << 5) +#else +#define MG17_16PL 0xFFFF +#endif +#if (G18PL >= G17PL) || (G18PL == 0) +#define MG17_18PL ~(1 << 7) +#else +#define MG17_18PL 0xFFFF +#endif +#define MG17_17PL 0x00BF +#define MG17 (MG17_11PL & MG17_12PL & MG17_13PL & MG17_14PL & \ + MG17_15PL & MG17_16PL & MG17_17PL & MG17_18PL) +// End of MG17: + +// Beginning of MG18: +#if (G11PL >= G18PL) || (G11PL == 0) +#define MG18_11PL ~(1) +#else +#define MG18_11PL 0xFFFF +#endif +#if (G12PL >= G18PL) || (G12PL == 0) +#define MG18_12PL ~(1 << 1) +#else +#define MG18_12PL 0xFFFF +#endif +#if (G13PL >= G18PL) || (G13PL == 0) +#define MG18_13PL ~(1 << 2) +#else +#define MG18_13PL 0xFFFF +#endif +#if (G14PL >= G18PL) || (G14PL == 0) +#define MG18_14PL ~(1 << 3) +#else +#define MG18_14PL 0xFFFF +#endif +#if (G15PL >= G18PL) || (G15PL == 0) +#define MG18_15PL ~(1 << 4) +#else +#define MG18_15PL 0xFFFF +#endif +#if (G16PL >= G18PL) || (G16PL == 0) +#define MG18_16PL ~(1 << 5) +#else +#define MG18_16PL 0xFFFF +#endif +#if (G17PL >= G18PL) || (G17PL == 0) +#define MG18_17PL ~(1 << 6) +#else +#define MG18_17PL 0xFFFF +#endif +#define MG18_18PL 0x007F +#define MG18 (MG18_11PL & MG18_12PL & MG18_13PL & MG18_14PL & \ + MG18_15PL & MG18_16PL & MG18_17PL & MG18_18PL) +// End of MG18: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG21 to MG28: +// + +// Beginning of MG21: +#if (G22PL >= G21PL) || (G22PL == 0) +#define MG21_12PL ~(1 << 1) +#else +#define MG21_12PL 0xFFFF +#endif +#if (G23PL >= G21PL) || (G23PL == 0) +#define MG21_13PL ~(1 << 2) +#else +#define MG21_13PL 0xFFFF +#endif +#if (G24PL >= G21PL) || (G24PL == 0) +#define MG21_14PL ~(1 << 3) +#else +#define MG21_14PL 0xFFFF +#endif +#if (G25PL >= G21PL) || (G25PL == 0) +#define MG21_15PL ~(1 << 4) +#else +#define MG21_15PL 0xFFFF +#endif +#if (G26PL >= G21PL) || (G26PL == 0) +#define MG21_16PL ~(1 << 5) +#else +#define MG21_16PL 0xFFFF +#endif +#if (G27PL >= G21PL) || (G27PL == 0) +#define MG21_17PL ~(1 << 6) +#else +#define MG21_17PL 0xFFFF +#endif +#if (G28PL >= G21PL) || (G28PL == 0) +#define MG21_18PL ~(1 << 7) +#else +#define MG21_18PL 0xFFFF +#endif +#define MG21_11PL 0x00FE +#define MG21 (MG21_11PL & MG21_12PL & MG21_13PL & MG21_14PL & \ + MG21_15PL & MG21_16PL & MG21_17PL & MG21_18PL) +// End of MG21: + +// Beginning of MG22: +#if (G21PL >= G22PL) || (G21PL == 0) +#define MG22_11PL ~(1) +#else +#define MG22_11PL 0xFFFF +#endif +#if (G23PL >= G22PL) || (G23PL == 0) +#define MG22_13PL ~(1 << 2) +#else +#define MG22_13PL 0xFFFF +#endif +#if (G24PL >= G22PL) || (G24PL == 0) +#define MG22_14PL ~(1 << 3) +#else +#define MG22_14PL 0xFFFF +#endif +#if (G25PL >= G22PL) || (G25PL == 0) +#define MG22_15PL ~(1 << 4) +#else +#define MG22_15PL 0xFFFF +#endif +#if (G26PL >= G22PL) || (G26PL == 0) +#define MG22_16PL ~(1 << 5) +#else +#define MG22_16PL 0xFFFF +#endif +#if (G27PL >= G22PL) || (G27PL == 0) +#define MG22_17PL ~(1 << 6) +#else +#define MG22_17PL 0xFFFF +#endif +#if (G28PL >= G22PL) || (G28PL == 0) +#define MG22_18PL ~(1 << 7) +#else +#define MG22_18PL 0xFFFF +#endif +#define MG22_12PL 0x00FD +#define MG22 (MG22_11PL & MG22_12PL & MG22_13PL & MG22_14PL & \ + MG22_15PL & MG22_16PL & MG22_17PL & MG22_18PL) +// End of MG22: + +// Beginning of MG23: +#if (G21PL >= G23PL) || (G21PL == 0) +#define MG23_11PL ~(1) +#else +#define MG23_11PL 0xFFFF +#endif +#if (G22PL >= G23PL) || (G22PL == 0) +#define MG23_12PL ~(1 << 1) +#else +#define MG23_12PL 0xFFFF +#endif +#if (G24PL >= G23PL) || (G24PL == 0) +#define MG23_14PL ~(1 << 3) +#else +#define MG23_14PL 0xFFFF +#endif +#if (G25PL >= G23PL) || (G25PL == 0) +#define MG23_15PL ~(1 << 4) +#else +#define MG23_15PL 0xFFFF +#endif +#if (G26PL >= G23PL) || (G26PL == 0) +#define MG23_16PL ~(1 << 5) +#else +#define MG23_16PL 0xFFFF +#endif +#if (G27PL >= G23PL) || (G27PL == 0) +#define MG23_17PL ~(1 << 6) +#else +#define MG23_17PL 0xFFFF +#endif +#if (G28PL >= G23PL) || (G28PL == 0) +#define MG23_18PL ~(1 << 7) +#else +#define MG23_18PL 0xFFFF +#endif +#define MG23_13PL 0x00FB +#define MG23 (MG23_11PL & MG23_12PL & MG23_13PL & MG23_14PL & \ + MG23_15PL & MG23_16PL & MG23_17PL & MG23_18PL) +// End of MG23: + +// Beginning of MG24: +#if (G21PL >= G24PL) || (G21PL == 0) +#define MG24_11PL ~(1) +#else +#define MG24_11PL 0xFFFF +#endif +#if (G22PL >= G24PL) || (G22PL == 0) +#define MG24_12PL ~(1 << 1) +#else +#define MG24_12PL 0xFFFF +#endif +#if (G23PL >= G24PL) || (G23PL == 0) +#define MG24_13PL ~(1 << 2) +#else +#define MG24_13PL 0xFFFF +#endif +#if (G25PL >= G24PL) || (G25PL == 0) +#define MG24_15PL ~(1 << 4) +#else +#define MG24_15PL 0xFFFF +#endif +#if (G26PL >= G24PL) || (G26PL == 0) +#define MG24_16PL ~(1 << 5) +#else +#define MG24_16PL 0xFFFF +#endif +#if (G27PL >= G24PL) || (G27PL == 0) +#define MG24_17PL ~(1 << 6) +#else +#define MG24_17PL 0xFFFF +#endif +#if (G28PL >= G24PL) || (G28PL == 0) +#define MG24_18PL ~(1 << 7) +#else +#define MG24_18PL 0xFFFF +#endif +#define MG24_14PL 0x00F7 +#define MG24 (MG24_11PL & MG24_12PL & MG24_13PL & MG24_14PL & \ + MG24_15PL & MG24_16PL & MG24_17PL & MG24_18PL) +// End of MG24: + +// Beginning of MG25: +#if (G21PL >= G25PL) || (G21PL == 0) +#define MG25_11PL ~(1) +#else +#define MG25_11PL 0xFFFF +#endif +#if (G22PL >= G25PL) || (G22PL == 0) +#define MG25_12PL ~(1 << 1) +#else +#define MG25_12PL 0xFFFF +#endif +#if (G23PL >= G25PL) || (G23PL == 0) +#define MG25_13PL ~(1 << 2) +#else +#define MG25_13PL 0xFFFF +#endif +#if (G24PL >= G25PL) || (G24PL == 0) +#define MG25_14PL ~(1 << 3) +#else +#define MG25_14PL 0xFFFF +#endif +#if (G26PL >= G25PL) || (G26PL == 0) +#define MG25_16PL ~(1 << 5) +#else +#define MG25_16PL 0xFFFF +#endif +#if (G27PL >= G25PL) || (G27PL == 0) +#define MG25_17PL ~(1 << 6) +#else +#define MG25_17PL 0xFFFF +#endif +#if (G28PL >= G25PL) || (G28PL == 0) +#define MG25_18PL ~(1 << 7) +#else +#define MG25_18PL 0xFFFF +#endif +#define MG25_15PL 0x00EF +#define MG25 (MG25_11PL & MG25_12PL & MG25_13PL & MG25_14PL & \ + MG25_15PL & MG25_16PL & MG25_17PL & MG25_18PL) +// End of MG25: + +// Beginning of MG26: +#if (G21PL >= G26PL) || (G21PL == 0) +#define MG26_11PL ~(1) +#else +#define MG26_11PL 0xFFFF +#endif +#if (G22PL >= G26PL) || (G22PL == 0) +#define MG26_12PL ~(1 << 1) +#else +#define MG26_12PL 0xFFFF +#endif +#if (G23PL >= G26PL) || (G23PL == 0) +#define MG26_13PL ~(1 << 2) +#else +#define MG26_13PL 0xFFFF +#endif +#if (G24PL >= G26PL) || (G24PL == 0) +#define MG26_14PL ~(1 << 3) +#else +#define MG26_14PL 0xFFFF +#endif +#if (G25PL >= G26PL) || (G25PL == 0) +#define MG26_15PL ~(1 << 4) +#else +#define MG26_15PL 0xFFFF +#endif +#if (G27PL >= G26PL) || (G27PL == 0) +#define MG26_17PL ~(1 << 6) +#else +#define MG26_17PL 0xFFFF +#endif +#if (G28PL >= G26PL) || (G28PL == 0) +#define MG26_18PL ~(1 << 7) +#else +#define MG26_18PL 0xFFFF +#endif +#define MG26_16PL 0x00DF +#define MG26 (MG26_11PL & MG26_12PL & MG26_13PL & MG26_14PL & \ + MG26_15PL & MG26_16PL & MG26_17PL & MG26_18PL) +// End of MG26: + +// Beginning of MG27: +#if (G21PL >= G27PL) || (G21PL == 0) +#define MG27_11PL ~(1) +#else +#define MG27_11PL 0xFFFF +#endif +#if (G22PL >= G27PL) || (G22PL == 0) +#define MG27_12PL ~(1 << 1) +#else +#define MG27_12PL 0xFFFF +#endif +#if (G23PL >= G27PL) || (G23PL == 0) +#define MG27_13PL ~(1 << 2) +#else +#define MG27_13PL 0xFFFF +#endif +#if (G24PL >= G27PL) || (G24PL == 0) +#define MG27_14PL ~(1 << 3) +#else +#define MG27_14PL 0xFFFF +#endif +#if (G25PL >= G27PL) || (G25PL == 0) +#define MG27_15PL ~(1 << 4) +#else +#define MG27_15PL 0xFFFF +#endif +#if (G26PL >= G27PL) || (G26PL == 0) +#define MG27_16PL ~(1 << 5) +#else +#define MG27_16PL 0xFFFF +#endif +#if (G28PL >= G27PL) || (G28PL == 0) +#define MG27_18PL ~(1 << 7) +#else +#define MG27_18PL 0xFFFF +#endif +#define MG27_17PL 0x00BF +#define MG27 (MG27_11PL & MG27_12PL & MG27_13PL & MG27_14PL & \ + MG27_15PL & MG27_16PL & MG27_17PL & MG27_18PL) +// End of MG27: + +// Beginning of MG28: +#if (G21PL >= G28PL) || (G21PL == 0) +#define MG28_11PL ~(1) +#else +#define MG28_11PL 0xFFFF +#endif +#if (G22PL >= G28PL) || (G22PL == 0) +#define MG28_12PL ~(1 << 1) +#else +#define MG28_12PL 0xFFFF +#endif +#if (G23PL >= G28PL) || (G23PL == 0) +#define MG28_13PL ~(1 << 2) +#else +#define MG28_13PL 0xFFFF +#endif +#if (G24PL >= G28PL) || (G24PL == 0) +#define MG28_14PL ~(1 << 3) +#else +#define MG28_14PL 0xFFFF +#endif +#if (G25PL >= G28PL) || (G25PL == 0) +#define MG28_15PL ~(1 << 4) +#else +#define MG28_15PL 0xFFFF +#endif +#if (G26PL >= G28PL) || (G26PL == 0) +#define MG28_16PL ~(1 << 5) +#else +#define MG28_16PL 0xFFFF +#endif +#if (G27PL >= G28PL) || (G27PL == 0) +#define MG28_17PL ~(1 << 6) +#else +#define MG28_17PL 0xFFFF +#endif +#define MG28_18PL 0x007F +#define MG28 (MG28_11PL & MG28_12PL & MG28_13PL & MG28_14PL & \ + MG28_15PL & MG28_16PL & MG28_17PL & MG28_18PL) +// End of MG28: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG31 to MG38: +// + +// Beginning of MG31: +#if (G32PL >= G31PL) || (G32PL == 0) +#define MG31_12PL ~(1 << 1) +#else +#define MG31_12PL 0xFFFF +#endif +#if (G33PL >= G31PL) || (G33PL == 0) +#define MG31_13PL ~(1 << 2) +#else +#define MG31_13PL 0xFFFF +#endif +#if (G34PL >= G31PL) || (G34PL == 0) +#define MG31_14PL ~(1 << 3) +#else +#define MG31_14PL 0xFFFF +#endif +#if (G35PL >= G31PL) || (G35PL == 0) +#define MG31_15PL ~(1 << 4) +#else +#define MG31_15PL 0xFFFF +#endif +#if (G36PL >= G31PL) || (G36PL == 0) +#define MG31_16PL ~(1 << 5) +#else +#define MG31_16PL 0xFFFF +#endif +#if (G37PL >= G31PL) || (G37PL == 0) +#define MG31_17PL ~(1 << 6) +#else +#define MG31_17PL 0xFFFF +#endif +#if (G38PL >= G31PL) || (G38PL == 0) +#define MG31_18PL ~(1 << 7) +#else +#define MG31_18PL 0xFFFF +#endif +#define MG31_11PL 0x00FE +#define MG31 (MG31_11PL & MG31_12PL & MG31_13PL & MG31_14PL & \ + MG31_15PL & MG31_16PL & MG31_17PL & MG31_18PL) +// End of MG31: + +// Beginning of MG32: +#if (G31PL >= G32PL) || (G31PL == 0) +#define MG32_11PL ~(1) +#else +#define MG32_11PL 0xFFFF +#endif +#if (G33PL >= G32PL) || (G33PL == 0) +#define MG32_13PL ~(1 << 2) +#else +#define MG32_13PL 0xFFFF +#endif +#if (G34PL >= G32PL) || (G34PL == 0) +#define MG32_14PL ~(1 << 3) +#else +#define MG32_14PL 0xFFFF +#endif +#if (G35PL >= G32PL) || (G35PL == 0) +#define MG32_15PL ~(1 << 4) +#else +#define MG32_15PL 0xFFFF +#endif +#if (G36PL >= G32PL) || (G36PL == 0) +#define MG32_16PL ~(1 << 5) +#else +#define MG32_16PL 0xFFFF +#endif +#if (G37PL >= G32PL) || (G37PL == 0) +#define MG32_17PL ~(1 << 6) +#else +#define MG32_17PL 0xFFFF +#endif +#if (G38PL >= G32PL) || (G38PL == 0) +#define MG32_18PL ~(1 << 7) +#else +#define MG32_18PL 0xFFFF +#endif +#define MG32_12PL 0x00FD +#define MG32 (MG32_11PL & MG32_12PL & MG32_13PL & MG32_14PL & \ + MG32_15PL & MG32_16PL & MG32_17PL & MG32_18PL) +// End of MG32: + +// Beginning of MG33: +#if (G31PL >= G33PL) || (G31PL == 0) +#define MG33_11PL ~(1) +#else +#define MG33_11PL 0xFFFF +#endif +#if (G32PL >= G33PL) || (G32PL == 0) +#define MG33_12PL ~(1 << 1) +#else +#define MG33_12PL 0xFFFF +#endif +#if (G34PL >= G33PL) || (G34PL == 0) +#define MG33_14PL ~(1 << 3) +#else +#define MG33_14PL 0xFFFF +#endif +#if (G35PL >= G33PL) || (G35PL == 0) +#define MG33_15PL ~(1 << 4) +#else +#define MG33_15PL 0xFFFF +#endif +#if (G36PL >= G33PL) || (G36PL == 0) +#define MG33_16PL ~(1 << 5) +#else +#define MG33_16PL 0xFFFF +#endif +#if (G37PL >= G33PL) || (G37PL == 0) +#define MG33_17PL ~(1 << 6) +#else +#define MG33_17PL 0xFFFF +#endif +#if (G38PL >= G33PL) || (G38PL == 0) +#define MG33_18PL ~(1 << 7) +#else +#define MG33_18PL 0xFFFF +#endif +#define MG33_13PL 0x00FB +#define MG33 (MG33_11PL & MG33_12PL & MG33_13PL & MG33_14PL & \ + MG33_15PL & MG33_16PL & MG33_17PL & MG33_18PL) +// End of MG33: + +// Beginning of MG34: +#if (G31PL >= G34PL) || (G31PL == 0) +#define MG34_11PL ~(1) +#else +#define MG34_11PL 0xFFFF +#endif +#if (G32PL >= G34PL) || (G32PL == 0) +#define MG34_12PL ~(1 << 1) +#else +#define MG34_12PL 0xFFFF +#endif +#if (G33PL >= G34PL) || (G33PL == 0) +#define MG34_13PL ~(1 << 2) +#else +#define MG34_13PL 0xFFFF +#endif +#if (G35PL >= G34PL) || (G35PL == 0) +#define MG34_15PL ~(1 << 4) +#else +#define MG34_15PL 0xFFFF +#endif +#if (G36PL >= G34PL) || (G36PL == 0) +#define MG34_16PL ~(1 << 5) +#else +#define MG34_16PL 0xFFFF +#endif +#if (G37PL >= G34PL) || (G37PL == 0) +#define MG34_17PL ~(1 << 6) +#else +#define MG34_17PL 0xFFFF +#endif +#if (G38PL >= G34PL) || (G38PL == 0) +#define MG34_18PL ~(1 << 7) +#else +#define MG34_18PL 0xFFFF +#endif +#define MG34_14PL 0x00F7 +#define MG34 (MG34_11PL & MG34_12PL & MG34_13PL & MG34_14PL & \ + MG34_15PL & MG34_16PL & MG34_17PL & MG34_18PL) +// End of MG34: + +// Beginning of MG35: +#if (G31PL >= G35PL) || (G31PL == 0) +#define MG35_11PL ~(1) +#else +#define MG35_11PL 0xFFFF +#endif +#if (G32PL >= G35PL) || (G32PL == 0) +#define MG35_12PL ~(1 << 1) +#else +#define MG35_12PL 0xFFFF +#endif +#if (G33PL >= G35PL) || (G33PL == 0) +#define MG35_13PL ~(1 << 2) +#else +#define MG35_13PL 0xFFFF +#endif +#if (G34PL >= G35PL) || (G34PL == 0) +#define MG35_14PL ~(1 << 3) +#else +#define MG35_14PL 0xFFFF +#endif +#if (G36PL >= G35PL) || (G36PL == 0) +#define MG35_16PL ~(1 << 5) +#else +#define MG35_16PL 0xFFFF +#endif +#if (G37PL >= G35PL) || (G37PL == 0) +#define MG35_17PL ~(1 << 6) +#else +#define MG35_17PL 0xFFFF +#endif +#if (G38PL >= G35PL) || (G38PL == 0) +#define MG35_18PL ~(1 << 7) +#else +#define MG35_18PL 0xFFFF +#endif +#define MG35_15PL 0x00EF +#define MG35 (MG35_11PL & MG35_12PL & MG35_13PL & MG35_14PL & \ + MG35_15PL & MG35_16PL & MG35_17PL & MG35_18PL) +// End of MG35: + +// Beginning of MG36: +#if (G31PL >= G36PL) || (G31PL == 0) +#define MG36_11PL ~(1) +#else +#define MG36_11PL 0xFFFF +#endif +#if (G32PL >= G36PL) || (G32PL == 0) +#define MG36_12PL ~(1 << 1) +#else +#define MG36_12PL 0xFFFF +#endif +#if (G33PL >= G36PL) || (G33PL == 0) +#define MG36_13PL ~(1 << 2) +#else +#define MG36_13PL 0xFFFF +#endif +#if (G34PL >= G36PL) || (G34PL == 0) +#define MG36_14PL ~(1 << 3) +#else +#define MG36_14PL 0xFFFF +#endif +#if (G35PL >= G36PL) || (G35PL == 0) +#define MG36_15PL ~(1 << 4) +#else +#define MG36_15PL 0xFFFF +#endif +#if (G37PL >= G36PL) || (G37PL == 0) +#define MG36_17PL ~(1 << 6) +#else +#define MG36_17PL 0xFFFF +#endif +#if (G38PL >= G36PL) || (G38PL == 0) +#define MG36_18PL ~(1 << 7) +#else +#define MG36_18PL 0xFFFF +#endif +#define MG36_16PL 0x00DF +#define MG36 (MG36_11PL & MG36_12PL & MG36_13PL & MG36_14PL & \ + MG36_15PL & MG36_16PL & MG36_17PL & MG36_18PL) +// End of MG36: + +// Beginning of MG37: +#if (G31PL >= G37PL) || (G31PL == 0) +#define MG37_11PL ~(1) +#else +#define MG37_11PL 0xFFFF +#endif +#if (G32PL >= G37PL) || (G32PL == 0) +#define MG37_12PL ~(1 << 1) +#else +#define MG37_12PL 0xFFFF +#endif +#if (G33PL >= G37PL) || (G33PL == 0) +#define MG37_13PL ~(1 << 2) +#else +#define MG37_13PL 0xFFFF +#endif +#if (G34PL >= G37PL) || (G34PL == 0) +#define MG37_14PL ~(1 << 3) +#else +#define MG37_14PL 0xFFFF +#endif +#if (G35PL >= G37PL) || (G35PL == 0) +#define MG37_15PL ~(1 << 4) +#else +#define MG37_15PL 0xFFFF +#endif +#if (G36PL >= G37PL) || (G36PL == 0) +#define MG37_16PL ~(1 << 5) +#else +#define MG37_16PL 0xFFFF +#endif +#if (G38PL >= G37PL) || (G38PL == 0) +#define MG37_18PL ~(1 << 7) +#else +#define MG37_18PL 0xFFFF +#endif +#define MG37_17PL 0x00BF +#define MG37 (MG37_11PL & MG37_12PL & MG37_13PL & MG37_14PL & \ + MG37_15PL & MG37_16PL & MG37_17PL & MG37_18PL) +// End of MG37: + +// Beginning of MG38: +#if (G31PL >= G38PL) || (G31PL == 0) +#define MG38_11PL ~(1) +#else +#define MG38_11PL 0xFFFF +#endif +#if (G32PL >= G38PL) || (G32PL == 0) +#define MG38_12PL ~(1 << 1) +#else +#define MG38_12PL 0xFFFF +#endif +#if (G33PL >= G38PL) || (G33PL == 0) +#define MG38_13PL ~(1 << 2) +#else +#define MG38_13PL 0xFFFF +#endif +#if (G34PL >= G38PL) || (G34PL == 0) +#define MG38_14PL ~(1 << 3) +#else +#define MG38_14PL 0xFFFF +#endif +#if (G35PL >= G38PL) || (G35PL == 0) +#define MG38_15PL ~(1 << 4) +#else +#define MG38_15PL 0xFFFF +#endif +#if (G36PL >= G38PL) || (G36PL == 0) +#define MG38_16PL ~(1 << 5) +#else +#define MG38_16PL 0xFFFF +#endif +#if (G37PL >= G38PL) || (G37PL == 0) +#define MG38_17PL ~(1 << 6) +#else +#define MG38_17PL 0xFFFF +#endif +#define MG38_18PL 0x007F +#define MG38 (MG38_11PL & MG38_12PL & MG38_13PL & MG38_14PL & \ + MG38_15PL & MG38_16PL & MG38_17PL & MG38_18PL) +// End of MG38: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG41 to MG48: +// + +// Beginning of MG41: +#if (G42PL >= G41PL) || (G42PL == 0) +#define MG41_12PL ~(1 << 1) +#else +#define MG41_12PL 0xFFFF +#endif +#if (G43PL >= G41PL) || (G43PL == 0) +#define MG41_13PL ~(1 << 2) +#else +#define MG41_13PL 0xFFFF +#endif +#if (G44PL >= G41PL) || (G44PL == 0) +#define MG41_14PL ~(1 << 3) +#else +#define MG41_14PL 0xFFFF +#endif +#if (G45PL >= G41PL) || (G45PL == 0) +#define MG41_15PL ~(1 << 4) +#else +#define MG41_15PL 0xFFFF +#endif +#if (G46PL >= G41PL) || (G46PL == 0) +#define MG41_16PL ~(1 << 5) +#else +#define MG41_16PL 0xFFFF +#endif +#if (G47PL >= G41PL) || (G47PL == 0) +#define MG41_17PL ~(1 << 6) +#else +#define MG41_17PL 0xFFFF +#endif +#if (G48PL >= G41PL) || (G48PL == 0) +#define MG41_18PL ~(1 << 7) +#else +#define MG41_18PL 0xFFFF +#endif +#define MG41_11PL 0x00FE +#define MG41 (MG41_11PL & MG41_12PL & MG41_13PL & MG41_14PL & \ + MG41_15PL & MG41_16PL & MG41_17PL & MG41_18PL) +// End of MG41: + +// Beginning of MG42: +#if (G41PL >= G42PL) || (G41PL == 0) +#define MG42_11PL ~(1) +#else +#define MG42_11PL 0xFFFF +#endif +#if (G43PL >= G42PL) || (G43PL == 0) +#define MG42_13PL ~(1 << 2) +#else +#define MG42_13PL 0xFFFF +#endif +#if (G44PL >= G42PL) || (G44PL == 0) +#define MG42_14PL ~(1 << 3) +#else +#define MG42_14PL 0xFFFF +#endif +#if (G45PL >= G42PL) || (G45PL == 0) +#define MG42_15PL ~(1 << 4) +#else +#define MG42_15PL 0xFFFF +#endif +#if (G46PL >= G42PL) || (G46PL == 0) +#define MG42_16PL ~(1 << 5) +#else +#define MG42_16PL 0xFFFF +#endif +#if (G47PL >= G42PL) || (G47PL == 0) +#define MG42_17PL ~(1 << 6) +#else +#define MG42_17PL 0xFFFF +#endif +#if (G48PL >= G42PL) || (G48PL == 0) +#define MG42_18PL ~(1 << 7) +#else +#define MG42_18PL 0xFFFF +#endif +#define MG42_12PL 0x00FD +#define MG42 (MG42_11PL & MG42_12PL & MG42_13PL & MG42_14PL & \ + MG42_15PL & MG42_16PL & MG42_17PL & MG42_18PL) +// End of MG42: + +// Beginning of MG43: +#if (G41PL >= G43PL) || (G41PL == 0) +#define MG43_11PL ~(1) +#else +#define MG43_11PL 0xFFFF +#endif +#if (G42PL >= G43PL) || (G42PL == 0) +#define MG43_12PL ~(1 << 1) +#else +#define MG43_12PL 0xFFFF +#endif +#if (G44PL >= G43PL) || (G44PL == 0) +#define MG43_14PL ~(1 << 3) +#else +#define MG43_14PL 0xFFFF +#endif +#if (G45PL >= G43PL) || (G45PL == 0) +#define MG43_15PL ~(1 << 4) +#else +#define MG43_15PL 0xFFFF +#endif +#if (G46PL >= G43PL) || (G46PL == 0) +#define MG43_16PL ~(1 << 5) +#else +#define MG43_16PL 0xFFFF +#endif +#if (G47PL >= G43PL) || (G47PL == 0) +#define MG43_17PL ~(1 << 6) +#else +#define MG43_17PL 0xFFFF +#endif +#if (G48PL >= G43PL) || (G48PL == 0) +#define MG43_18PL ~(1 << 7) +#else +#define MG43_18PL 0xFFFF +#endif +#define MG43_13PL 0x00FB +#define MG43 (MG43_11PL & MG43_12PL & MG43_13PL & MG43_14PL & \ + MG43_15PL & MG43_16PL & MG43_17PL & MG43_18PL) +// End of MG43: + +// Beginning of MG44: +#if (G41PL >= G44PL) || (G41PL == 0) +#define MG44_11PL ~(1) +#else +#define MG44_11PL 0xFFFF +#endif +#if (G42PL >= G44PL) || (G42PL == 0) +#define MG44_12PL ~(1 << 1) +#else +#define MG44_12PL 0xFFFF +#endif +#if (G43PL >= G44PL) || (G43PL == 0) +#define MG44_13PL ~(1 << 2) +#else +#define MG44_13PL 0xFFFF +#endif +#if (G45PL >= G44PL) || (G45PL == 0) +#define MG44_15PL ~(1 << 4) +#else +#define MG44_15PL 0xFFFF +#endif +#if (G46PL >= G44PL) || (G46PL == 0) +#define MG44_16PL ~(1 << 5) +#else +#define MG44_16PL 0xFFFF +#endif +#if (G47PL >= G44PL) || (G47PL == 0) +#define MG44_17PL ~(1 << 6) +#else +#define MG44_17PL 0xFFFF +#endif +#if (G48PL >= G44PL) || (G48PL == 0) +#define MG44_18PL ~(1 << 7) +#else +#define MG44_18PL 0xFFFF +#endif +#define MG44_14PL 0x00F7 +#define MG44 (MG44_11PL & MG44_12PL & MG44_13PL & MG44_14PL & \ + MG44_15PL & MG44_16PL & MG44_17PL & MG44_18PL) +// End of MG44: + +// Beginning of MG45: +#if (G41PL >= G45PL) || (G41PL == 0) +#define MG45_11PL ~(1) +#else +#define MG45_11PL 0xFFFF +#endif +#if (G42PL >= G45PL) || (G42PL == 0) +#define MG45_12PL ~(1 << 1) +#else +#define MG45_12PL 0xFFFF +#endif +#if (G43PL >= G45PL) || (G43PL == 0) +#define MG45_13PL ~(1 << 2) +#else +#define MG45_13PL 0xFFFF +#endif +#if (G44PL >= G45PL) || (G44PL == 0) +#define MG45_14PL ~(1 << 3) +#else +#define MG45_14PL 0xFFFF +#endif +#if (G46PL >= G45PL) || (G46PL == 0) +#define MG45_16PL ~(1 << 5) +#else +#define MG45_16PL 0xFFFF +#endif +#if (G47PL >= G45PL) || (G47PL == 0) +#define MG45_17PL ~(1 << 6) +#else +#define MG45_17PL 0xFFFF +#endif +#if (G48PL >= G45PL) || (G48PL == 0) +#define MG45_18PL ~(1 << 7) +#else +#define MG45_18PL 0xFFFF +#endif +#define MG45_15PL 0x00EF +#define MG45 (MG45_11PL & MG45_12PL & MG45_13PL & MG45_14PL & \ + MG45_15PL & MG45_16PL & MG45_17PL & MG45_18PL) +// End of MG45: + +// Beginning of MG46: +#if (G41PL >= G46PL) || (G41PL == 0) +#define MG46_11PL ~(1) +#else +#define MG46_11PL 0xFFFF +#endif +#if (G42PL >= G46PL) || (G42PL == 0) +#define MG46_12PL ~(1 << 1) +#else +#define MG46_12PL 0xFFFF +#endif +#if (G43PL >= G46PL) || (G43PL == 0) +#define MG46_13PL ~(1 << 2) +#else +#define MG46_13PL 0xFFFF +#endif +#if (G44PL >= G46PL) || (G44PL == 0) +#define MG46_14PL ~(1 << 3) +#else +#define MG46_14PL 0xFFFF +#endif +#if (G45PL >= G46PL) || (G45PL == 0) +#define MG46_15PL ~(1 << 4) +#else +#define MG46_15PL 0xFFFF +#endif +#if (G47PL >= G46PL) || (G47PL == 0) +#define MG46_17PL ~(1 << 6) +#else +#define MG46_17PL 0xFFFF +#endif +#if (G48PL >= G46PL) || (G48PL == 0) +#define MG46_18PL ~(1 << 7) +#else +#define MG46_18PL 0xFFFF +#endif +#define MG46_16PL 0x00DF +#define MG46 (MG46_11PL & MG46_12PL & MG46_13PL & MG46_14PL & \ + MG46_15PL & MG46_16PL & MG46_17PL & MG46_18PL) +// End of MG46: + +// Beginning of MG47: +#if (G41PL >= G47PL) || (G41PL == 0) +#define MG47_11PL ~(1) +#else +#define MG47_11PL 0xFFFF +#endif +#if (G42PL >= G47PL) || (G42PL == 0) +#define MG47_12PL ~(1 << 1) +#else +#define MG47_12PL 0xFFFF +#endif +#if (G43PL >= G47PL) || (G43PL == 0) +#define MG47_13PL ~(1 << 2) +#else +#define MG47_13PL 0xFFFF +#endif +#if (G44PL >= G47PL) || (G44PL == 0) +#define MG47_14PL ~(1 << 3) +#else +#define MG47_14PL 0xFFFF +#endif +#if (G45PL >= G47PL) || (G45PL == 0) +#define MG47_15PL ~(1 << 4) +#else +#define MG47_15PL 0xFFFF +#endif +#if (G46PL >= G47PL) || (G46PL == 0) +#define MG47_16PL ~(1 << 5) +#else +#define MG47_16PL 0xFFFF +#endif +#if (G48PL >= G47PL) || (G48PL == 0) +#define MG47_18PL ~(1 << 7) +#else +#define MG47_18PL 0xFFFF +#endif +#define MG47_17PL 0x00BF +#define MG47 (MG47_11PL & MG47_12PL & MG47_13PL & MG47_14PL & \ + MG47_15PL & MG47_16PL & MG47_17PL & MG47_18PL) +// End of MG47: + +// Beginning of MG48: +#if (G41PL >= G48PL) || (G41PL == 0) +#define MG48_11PL ~(1) +#else +#define MG48_11PL 0xFFFF +#endif +#if (G42PL >= G48PL) || (G42PL == 0) +#define MG48_12PL ~(1 << 1) +#else +#define MG48_12PL 0xFFFF +#endif +#if (G43PL >= G48PL) || (G43PL == 0) +#define MG48_13PL ~(1 << 2) +#else +#define MG48_13PL 0xFFFF +#endif +#if (G44PL >= G48PL) || (G44PL == 0) +#define MG48_14PL ~(1 << 3) +#else +#define MG48_14PL 0xFFFF +#endif +#if (G45PL >= G48PL) || (G45PL == 0) +#define MG48_15PL ~(1 << 4) +#else +#define MG48_15PL 0xFFFF +#endif +#if (G46PL >= G48PL) || (G46PL == 0) +#define MG48_16PL ~(1 << 5) +#else +#define MG48_16PL 0xFFFF +#endif +#if (G47PL >= G48PL) || (G47PL == 0) +#define MG48_17PL ~(1 << 6) +#else +#define MG48_17PL 0xFFFF +#endif +#define MG48_18PL 0x007F +#define MG48 (MG48_11PL & MG48_12PL & MG48_13PL & MG48_14PL & \ + MG48_15PL & MG48_16PL & MG48_17PL & MG48_18PL) +// End of MG48: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG51 to MG58: +// + +// Beginning of MG51: +#if (G52PL >= G51PL) || (G52PL == 0) +#define MG51_12PL ~(1 << 1) +#else +#define MG51_12PL 0xFFFF +#endif +#if (G53PL >= G51PL) || (G53PL == 0) +#define MG51_13PL ~(1 << 2) +#else +#define MG51_13PL 0xFFFF +#endif +#if (G54PL >= G51PL) || (G54PL == 0) +#define MG51_14PL ~(1 << 3) +#else +#define MG51_14PL 0xFFFF +#endif +#if (G55PL >= G51PL) || (G55PL == 0) +#define MG51_15PL ~(1 << 4) +#else +#define MG51_15PL 0xFFFF +#endif +#if (G56PL >= G51PL) || (G56PL == 0) +#define MG51_16PL ~(1 << 5) +#else +#define MG51_16PL 0xFFFF +#endif +#if (G57PL >= G51PL) || (G57PL == 0) +#define MG51_17PL ~(1 << 6) +#else +#define MG51_17PL 0xFFFF +#endif +#if (G58PL >= G51PL) || (G58PL == 0) +#define MG51_18PL ~(1 << 7) +#else +#define MG51_18PL 0xFFFF +#endif +#define MG51_11PL 0x00FE +#define MG51 (MG51_11PL & MG51_12PL & MG51_13PL & MG51_14PL & \ + MG51_15PL & MG51_16PL & MG51_17PL & MG51_18PL) +// End of MG51: + +// Beginning of MG52: +#if (G51PL >= G52PL) || (G51PL == 0) +#define MG52_11PL ~(1) +#else +#define MG52_11PL 0xFFFF +#endif +#if (G53PL >= G52PL) || (G53PL == 0) +#define MG52_13PL ~(1 << 2) +#else +#define MG52_13PL 0xFFFF +#endif +#if (G54PL >= G52PL) || (G54PL == 0) +#define MG52_14PL ~(1 << 3) +#else +#define MG52_14PL 0xFFFF +#endif +#if (G55PL >= G52PL) || (G55PL == 0) +#define MG52_15PL ~(1 << 4) +#else +#define MG52_15PL 0xFFFF +#endif +#if (G56PL >= G52PL) || (G56PL == 0) +#define MG52_16PL ~(1 << 5) +#else +#define MG52_16PL 0xFFFF +#endif +#if (G57PL >= G52PL) || (G57PL == 0) +#define MG52_17PL ~(1 << 6) +#else +#define MG52_17PL 0xFFFF +#endif +#if (G58PL >= G52PL) || (G58PL == 0) +#define MG52_18PL ~(1 << 7) +#else +#define MG52_18PL 0xFFFF +#endif +#define MG52_12PL 0x00FD +#define MG52 (MG52_11PL & MG52_12PL & MG52_13PL & MG52_14PL & \ + MG52_15PL & MG52_16PL & MG52_17PL & MG52_18PL) +// End of MG52: + +// Beginning of MG53: +#if (G51PL >= G53PL) || (G51PL == 0) +#define MG53_11PL ~(1) +#else +#define MG53_11PL 0xFFFF +#endif +#if (G52PL >= G53PL) || (G52PL == 0) +#define MG53_12PL ~(1 << 1) +#else +#define MG53_12PL 0xFFFF +#endif +#if (G54PL >= G53PL) || (G54PL == 0) +#define MG53_14PL ~(1 << 3) +#else +#define MG53_14PL 0xFFFF +#endif +#if (G55PL >= G53PL) || (G55PL == 0) +#define MG53_15PL ~(1 << 4) +#else +#define MG53_15PL 0xFFFF +#endif +#if (G56PL >= G53PL) || (G56PL == 0) +#define MG53_16PL ~(1 << 5) +#else +#define MG53_16PL 0xFFFF +#endif +#if (G57PL >= G53PL) || (G57PL == 0) +#define MG53_17PL ~(1 << 6) +#else +#define MG53_17PL 0xFFFF +#endif +#if (G58PL >= G53PL) || (G58PL == 0) +#define MG53_18PL ~(1 << 7) +#else +#define MG53_18PL 0xFFFF +#endif +#define MG53_13PL 0x00FB +#define MG53 (MG53_11PL & MG53_12PL & MG53_13PL & MG53_14PL & \ + MG53_15PL & MG53_16PL & MG53_17PL & MG53_18PL) +// End of MG53: + +// Beginning of MG54: +#if (G51PL >= G54PL) || (G51PL == 0) +#define MG54_11PL ~(1) +#else +#define MG54_11PL 0xFFFF +#endif +#if (G52PL >= G54PL) || (G52PL == 0) +#define MG54_12PL ~(1 << 1) +#else +#define MG54_12PL 0xFFFF +#endif +#if (G53PL >= G54PL) || (G53PL == 0) +#define MG54_13PL ~(1 << 2) +#else +#define MG54_13PL 0xFFFF +#endif +#if (G55PL >= G54PL) || (G55PL == 0) +#define MG54_15PL ~(1 << 4) +#else +#define MG54_15PL 0xFFFF +#endif +#if (G56PL >= G54PL) || (G56PL == 0) +#define MG54_16PL ~(1 << 5) +#else +#define MG54_16PL 0xFFFF +#endif +#if (G57PL >= G54PL) || (G57PL == 0) +#define MG54_17PL ~(1 << 6) +#else +#define MG54_17PL 0xFFFF +#endif +#if (G58PL >= G54PL) || (G58PL == 0) +#define MG54_18PL ~(1 << 7) +#else +#define MG54_18PL 0xFFFF +#endif +#define MG54_14PL 0x00F7 +#define MG54 (MG54_11PL & MG54_12PL & MG54_13PL & MG54_14PL & \ + MG54_15PL & MG54_16PL & MG54_17PL & MG54_18PL) +// End of MG54: + +// Beginning of MG55: +#if (G51PL >= G55PL) || (G51PL == 0) +#define MG55_11PL ~(1) +#else +#define MG55_11PL 0xFFFF +#endif +#if (G52PL >= G55PL) || (G52PL == 0) +#define MG55_12PL ~(1 << 1) +#else +#define MG55_12PL 0xFFFF +#endif +#if (G53PL >= G55PL) || (G53PL == 0) +#define MG55_13PL ~(1 << 2) +#else +#define MG55_13PL 0xFFFF +#endif +#if (G54PL >= G55PL) || (G54PL == 0) +#define MG55_14PL ~(1 << 3) +#else +#define MG55_14PL 0xFFFF +#endif +#if (G56PL >= G55PL) || (G56PL == 0) +#define MG55_16PL ~(1 << 5) +#else +#define MG55_16PL 0xFFFF +#endif +#if (G57PL >= G55PL) || (G57PL == 0) +#define MG55_17PL ~(1 << 6) +#else +#define MG55_17PL 0xFFFF +#endif +#if (G58PL >= G55PL) || (G58PL == 0) +#define MG55_18PL ~(1 << 7) +#else +#define MG55_18PL 0xFFFF +#endif +#define MG55_15PL 0x00EF +#define MG55 (MG55_11PL & MG55_12PL & MG55_13PL & MG55_14PL & \ + MG55_15PL & MG55_16PL & MG55_17PL & MG55_18PL) +// End of MG55: + +// Beginning of MG56: +#if (G51PL >= G56PL) || (G51PL == 0) +#define MG56_11PL ~(1) +#else +#define MG56_11PL 0xFFFF +#endif +#if (G52PL >= G56PL) || (G52PL == 0) +#define MG56_12PL ~(1 << 1) +#else +#define MG56_12PL 0xFFFF +#endif +#if (G53PL >= G56PL) || (G53PL == 0) +#define MG56_13PL ~(1 << 2) +#else +#define MG56_13PL 0xFFFF +#endif +#if (G54PL >= G56PL) || (G54PL == 0) +#define MG56_14PL ~(1 << 3) +#else +#define MG56_14PL 0xFFFF +#endif +#if (G55PL >= G56PL) || (G55PL == 0) +#define MG56_15PL ~(1 << 4) +#else +#define MG56_15PL 0xFFFF +#endif +#if (G57PL >= G56PL) || (G57PL == 0) +#define MG56_17PL ~(1 << 6) +#else +#define MG56_17PL 0xFFFF +#endif +#if (G58PL >= G56PL) || (G58PL == 0) +#define MG56_18PL ~(1 << 7) +#else +#define MG56_18PL 0xFFFF +#endif +#define MG56_16PL 0x00DF +#define MG56 (MG56_11PL & MG56_12PL & MG56_13PL & MG56_14PL & \ + MG56_15PL & MG56_16PL & MG56_17PL & MG56_18PL) +// End of MG56: + +// Beginning of MG57: +#if (G51PL >= G57PL) || (G51PL == 0) +#define MG57_11PL ~(1) +#else +#define MG57_11PL 0xFFFF +#endif +#if (G52PL >= G57PL) || (G52PL == 0) +#define MG57_12PL ~(1 << 1) +#else +#define MG57_12PL 0xFFFF +#endif +#if (G53PL >= G57PL) || (G53PL == 0) +#define MG57_13PL ~(1 << 2) +#else +#define MG57_13PL 0xFFFF +#endif +#if (G54PL >= G57PL) || (G54PL == 0) +#define MG57_14PL ~(1 << 3) +#else +#define MG57_14PL 0xFFFF +#endif +#if (G55PL >= G57PL) || (G55PL == 0) +#define MG57_15PL ~(1 << 4) +#else +#define MG57_15PL 0xFFFF +#endif +#if (G56PL >= G57PL) || (G56PL == 0) +#define MG57_16PL ~(1 << 5) +#else +#define MG57_16PL 0xFFFF +#endif +#if (G58PL >= G57PL) || (G58PL == 0) +#define MG57_18PL ~(1 << 7) +#else +#define MG57_18PL 0xFFFF +#endif +#define MG57_17PL 0x00BF +#define MG57 (MG57_11PL & MG57_12PL & MG57_13PL & MG57_14PL & \ + MG57_15PL & MG57_16PL & MG57_17PL & MG57_18PL) +// End of MG57: + +// Beginning of MG58: +#if (G51PL >= G58PL) || (G51PL == 0) +#define MG58_11PL ~(1) +#else +#define MG58_11PL 0xFFFF +#endif +#if (G52PL >= G58PL) || (G52PL == 0) +#define MG58_12PL ~(1 << 1) +#else +#define MG58_12PL 0xFFFF +#endif +#if (G53PL >= G58PL) || (G53PL == 0) +#define MG58_13PL ~(1 << 2) +#else +#define MG58_13PL 0xFFFF +#endif +#if (G54PL >= G58PL) || (G54PL == 0) +#define MG58_14PL ~(1 << 3) +#else +#define MG58_14PL 0xFFFF +#endif +#if (G55PL >= G58PL) || (G55PL == 0) +#define MG58_15PL ~(1 << 4) +#else +#define MG58_15PL 0xFFFF +#endif +#if (G56PL >= G58PL) || (G56PL == 0) +#define MG58_16PL ~(1 << 5) +#else +#define MG58_16PL 0xFFFF +#endif +#if (G57PL >= G58PL) || (G57PL == 0) +#define MG58_17PL ~(1 << 6) +#else +#define MG58_17PL 0xFFFF +#endif +#define MG58_18PL 0x007F +#define MG58 (MG58_11PL & MG58_12PL & MG58_13PL & MG58_14PL & \ + MG58_15PL & MG58_16PL & MG58_17PL & MG58_18PL) +// End of MG58: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG61 to MG68: +// + +// Beginning of MG61: +#if (G62PL >= G61PL) || (G62PL == 0) +#define MG61_12PL ~(1 << 1) +#else +#define MG61_12PL 0xFFFF +#endif +#if (G63PL >= G61PL) || (G63PL == 0) +#define MG61_13PL ~(1 << 2) +#else +#define MG61_13PL 0xFFFF +#endif +#if (G64PL >= G61PL) || (G64PL == 0) +#define MG61_14PL ~(1 << 3) +#else +#define MG61_14PL 0xFFFF +#endif +#if (G65PL >= G61PL) || (G65PL == 0) +#define MG61_15PL ~(1 << 4) +#else +#define MG61_15PL 0xFFFF +#endif +#if (G66PL >= G61PL) || (G66PL == 0) +#define MG61_16PL ~(1 << 5) +#else +#define MG61_16PL 0xFFFF +#endif +#if (G67PL >= G61PL) || (G67PL == 0) +#define MG61_17PL ~(1 << 6) +#else +#define MG61_17PL 0xFFFF +#endif +#if (G68PL >= G61PL) || (G68PL == 0) +#define MG61_18PL ~(1 << 7) +#else +#define MG61_18PL 0xFFFF +#endif +#define MG61_11PL 0x00FE +#define MG61 (MG61_11PL & MG61_12PL & MG61_13PL & MG61_14PL & \ + MG61_15PL & MG61_16PL & MG61_17PL & MG61_18PL) +// End of MG61: + +// Beginning of MG62: +#if (G61PL >= G62PL) || (G61PL == 0) +#define MG62_11PL ~(1) +#else +#define MG62_11PL 0xFFFF +#endif +#if (G63PL >= G62PL) || (G63PL == 0) +#define MG62_13PL ~(1 << 2) +#else +#define MG62_13PL 0xFFFF +#endif +#if (G64PL >= G62PL) || (G64PL == 0) +#define MG62_14PL ~(1 << 3) +#else +#define MG62_14PL 0xFFFF +#endif +#if (G65PL >= G62PL) || (G65PL == 0) +#define MG62_15PL ~(1 << 4) +#else +#define MG62_15PL 0xFFFF +#endif +#if (G66PL >= G62PL) || (G66PL == 0) +#define MG62_16PL ~(1 << 5) +#else +#define MG62_16PL 0xFFFF +#endif +#if (G67PL >= G62PL) || (G67PL == 0) +#define MG62_17PL ~(1 << 6) +#else +#define MG62_17PL 0xFFFF +#endif +#if (G68PL >= G62PL) || (G68PL == 0) +#define MG62_18PL ~(1 << 7) +#else +#define MG62_18PL 0xFFFF +#endif +#define MG62_12PL 0x00FD +#define MG62 (MG62_11PL & MG62_12PL & MG62_13PL & MG62_14PL & \ + MG62_15PL & MG62_16PL & MG62_17PL & MG62_18PL) +// End of MG62: + +// Beginning of MG63: +#if (G61PL >= G63PL) || (G61PL == 0) +#define MG63_11PL ~(1) +#else +#define MG63_11PL 0xFFFF +#endif +#if (G62PL >= G63PL) || (G62PL == 0) +#define MG63_12PL ~(1 << 1) +#else +#define MG63_12PL 0xFFFF +#endif +#if (G64PL >= G63PL) || (G64PL == 0) +#define MG63_14PL ~(1 << 3) +#else +#define MG63_14PL 0xFFFF +#endif +#if (G65PL >= G63PL) || (G65PL == 0) +#define MG63_15PL ~(1 << 4) +#else +#define MG63_15PL 0xFFFF +#endif +#if (G66PL >= G63PL) || (G66PL == 0) +#define MG63_16PL ~(1 << 5) +#else +#define MG63_16PL 0xFFFF +#endif +#if (G67PL >= G63PL) || (G67PL == 0) +#define MG63_17PL ~(1 << 6) +#else +#define MG63_17PL 0xFFFF +#endif +#if (G68PL >= G63PL) || (G68PL == 0) +#define MG63_18PL ~(1 << 7) +#else +#define MG63_18PL 0xFFFF +#endif +#define MG63_13PL 0x00FB +#define MG63 (MG63_11PL & MG63_12PL & MG63_13PL & MG63_14PL & \ + MG63_15PL & MG63_16PL & MG63_17PL & MG63_18PL) +// End of MG63: + +// Beginning of MG64: +#if (G61PL >= G64PL) || (G61PL == 0) +#define MG64_11PL ~(1) +#else +#define MG64_11PL 0xFFFF +#endif +#if (G62PL >= G64PL) || (G62PL == 0) +#define MG64_12PL ~(1 << 1) +#else +#define MG64_12PL 0xFFFF +#endif +#if (G63PL >= G64PL) || (G63PL == 0) +#define MG64_13PL ~(1 << 2) +#else +#define MG64_13PL 0xFFFF +#endif +#if (G65PL >= G64PL) || (G65PL == 0) +#define MG64_15PL ~(1 << 4) +#else +#define MG64_15PL 0xFFFF +#endif +#if (G66PL >= G64PL) || (G66PL == 0) +#define MG64_16PL ~(1 << 5) +#else +#define MG64_16PL 0xFFFF +#endif +#if (G67PL >= G64PL) || (G67PL == 0) +#define MG64_17PL ~(1 << 6) +#else +#define MG64_17PL 0xFFFF +#endif +#if (G68PL >= G64PL) || (G68PL == 0) +#define MG64_18PL ~(1 << 7) +#else +#define MG64_18PL 0xFFFF +#endif +#define MG64_14PL 0x00F7 +#define MG64 (MG64_11PL & MG64_12PL & MG64_13PL & MG64_14PL & \ + MG64_15PL & MG64_16PL & MG64_17PL & MG64_18PL) +// End of MG64: + +// Beginning of MG65: +#if (G61PL >= G65PL) || (G61PL == 0) +#define MG65_11PL ~(1) +#else +#define MG65_11PL 0xFFFF +#endif +#if (G62PL >= G65PL) || (G62PL == 0) +#define MG65_12PL ~(1 << 1) +#else +#define MG65_12PL 0xFFFF +#endif +#if (G63PL >= G65PL) || (G63PL == 0) +#define MG65_13PL ~(1 << 2) +#else +#define MG65_13PL 0xFFFF +#endif +#if (G64PL >= G65PL) || (G64PL == 0) +#define MG65_14PL ~(1 << 3) +#else +#define MG65_14PL 0xFFFF +#endif +#if (G66PL >= G65PL) || (G66PL == 0) +#define MG65_16PL ~(1 << 5) +#else +#define MG65_16PL 0xFFFF +#endif +#if (G67PL >= G65PL) || (G67PL == 0) +#define MG65_17PL ~(1 << 6) +#else +#define MG65_17PL 0xFFFF +#endif +#if (G68PL >= G65PL) || (G68PL == 0) +#define MG65_18PL ~(1 << 7) +#else +#define MG65_18PL 0xFFFF +#endif +#define MG65_15PL 0x00EF +#define MG65 (MG65_11PL & MG65_12PL & MG65_13PL & MG65_14PL & \ + MG65_15PL & MG65_16PL & MG65_17PL & MG65_18PL) +// End of MG65: + +// Beginning of MG66: +#if (G61PL >= G66PL) || (G61PL == 0) +#define MG66_11PL ~(1) +#else +#define MG66_11PL 0xFFFF +#endif +#if (G62PL >= G66PL) || (G62PL == 0) +#define MG66_12PL ~(1 << 1) +#else +#define MG66_12PL 0xFFFF +#endif +#if (G63PL >= G66PL) || (G63PL == 0) +#define MG66_13PL ~(1 << 2) +#else +#define MG66_13PL 0xFFFF +#endif +#if (G64PL >= G66PL) || (G64PL == 0) +#define MG66_14PL ~(1 << 3) +#else +#define MG66_14PL 0xFFFF +#endif +#if (G65PL >= G66PL) || (G65PL == 0) +#define MG66_15PL ~(1 << 4) +#else +#define MG66_15PL 0xFFFF +#endif +#if (G67PL >= G66PL) || (G67PL == 0) +#define MG66_17PL ~(1 << 6) +#else +#define MG66_17PL 0xFFFF +#endif +#if (G68PL >= G66PL) || (G68PL == 0) +#define MG66_18PL ~(1 << 7) +#else +#define MG66_18PL 0xFFFF +#endif +#define MG66_16PL 0x00DF +#define MG66 (MG66_11PL & MG66_12PL & MG66_13PL & MG66_14PL & \ + MG66_15PL & MG66_16PL & MG66_17PL & MG66_18PL) +// End of MG66: + +// Beginning of MG67: +#if (G61PL >= G67PL) || (G61PL == 0) +#define MG67_11PL ~(1) +#else +#define MG67_11PL 0xFFFF +#endif +#if (G62PL >= G67PL) || (G62PL == 0) +#define MG67_12PL ~(1 << 1) +#else +#define MG67_12PL 0xFFFF +#endif +#if (G63PL >= G67PL) || (G63PL == 0) +#define MG67_13PL ~(1 << 2) +#else +#define MG67_13PL 0xFFFF +#endif +#if (G64PL >= G67PL) || (G64PL == 0) +#define MG67_14PL ~(1 << 3) +#else +#define MG67_14PL 0xFFFF +#endif +#if (G65PL >= G67PL) || (G65PL == 0) +#define MG67_15PL ~(1 << 4) +#else +#define MG67_15PL 0xFFFF +#endif +#if (G66PL >= G67PL) || (G66PL == 0) +#define MG67_16PL ~(1 << 5) +#else +#define MG67_16PL 0xFFFF +#endif +#if (G68PL >= G67PL) || (G68PL == 0) +#define MG67_18PL ~(1 << 7) +#else +#define MG67_18PL 0xFFFF +#endif +#define MG67_17PL 0x00BF +#define MG67 (MG67_11PL & MG67_12PL & MG67_13PL & MG67_14PL & \ + MG67_15PL & MG67_16PL & MG67_17PL & MG67_18PL) +// End of MG67: + +// Beginning of MG68: +#if (G61PL >= G68PL) || (G61PL == 0) +#define MG68_11PL ~(1) +#else +#define MG68_11PL 0xFFFF +#endif +#if (G62PL >= G68PL) || (G62PL == 0) +#define MG68_12PL ~(1 << 1) +#else +#define MG68_12PL 0xFFFF +#endif +#if (G63PL >= G68PL) || (G63PL == 0) +#define MG68_13PL ~(1 << 2) +#else +#define MG68_13PL 0xFFFF +#endif +#if (G64PL >= G68PL) || (G64PL == 0) +#define MG68_14PL ~(1 << 3) +#else +#define MG68_14PL 0xFFFF +#endif +#if (G65PL >= G68PL) || (G65PL == 0) +#define MG68_15PL ~(1 << 4) +#else +#define MG68_15PL 0xFFFF +#endif +#if (G66PL >= G68PL) || (G66PL == 0) +#define MG68_16PL ~(1 << 5) +#else +#define MG68_16PL 0xFFFF +#endif +#if (G67PL >= G68PL) || (G67PL == 0) +#define MG68_17PL ~(1 << 6) +#else +#define MG68_17PL 0xFFFF +#endif +#define MG68_18PL 0x007F +#define MG68 (MG68_11PL & MG68_12PL & MG68_13PL & MG68_14PL & \ + MG68_15PL & MG68_16PL & MG68_17PL & MG68_18PL) +// End of MG68: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG71 to MG78: +// + +// Beginning of MG71: +#if (G72PL >= G71PL) || (G72PL == 0) +#define MG71_12PL ~(1 << 1) +#else +#define MG71_12PL 0xFFFF +#endif +#if (G73PL >= G71PL) || (G73PL == 0) +#define MG71_13PL ~(1 << 2) +#else +#define MG71_13PL 0xFFFF +#endif +#if (G74PL >= G71PL) || (G74PL == 0) +#define MG71_14PL ~(1 << 3) +#else +#define MG71_14PL 0xFFFF +#endif +#if (G75PL >= G71PL) || (G75PL == 0) +#define MG71_15PL ~(1 << 4) +#else +#define MG71_15PL 0xFFFF +#endif +#if (G76PL >= G71PL) || (G76PL == 0) +#define MG71_16PL ~(1 << 5) +#else +#define MG71_16PL 0xFFFF +#endif +#if (G77PL >= G71PL) || (G77PL == 0) +#define MG71_17PL ~(1 << 6) +#else +#define MG71_17PL 0xFFFF +#endif +#if (G78PL >= G71PL) || (G78PL == 0) +#define MG71_18PL ~(1 << 7) +#else +#define MG71_18PL 0xFFFF +#endif +#define MG71_11PL 0x00FE +#define MG71 (MG71_11PL & MG71_12PL & MG71_13PL & MG71_14PL & \ + MG71_15PL & MG71_16PL & MG71_17PL & MG71_18PL) +// End of MG71: + +// Beginning of MG72: +#if (G71PL >= G72PL) || (G71PL == 0) +#define MG72_11PL ~(1) +#else +#define MG72_11PL 0xFFFF +#endif +#if (G73PL >= G72PL) || (G73PL == 0) +#define MG72_13PL ~(1 << 2) +#else +#define MG72_13PL 0xFFFF +#endif +#if (G74PL >= G72PL) || (G74PL == 0) +#define MG72_14PL ~(1 << 3) +#else +#define MG72_14PL 0xFFFF +#endif +#if (G75PL >= G72PL) || (G75PL == 0) +#define MG72_15PL ~(1 << 4) +#else +#define MG72_15PL 0xFFFF +#endif +#if (G76PL >= G72PL) || (G76PL == 0) +#define MG72_16PL ~(1 << 5) +#else +#define MG72_16PL 0xFFFF +#endif +#if (G77PL >= G72PL) || (G77PL == 0) +#define MG72_17PL ~(1 << 6) +#else +#define MG72_17PL 0xFFFF +#endif +#if (G78PL >= G72PL) || (G78PL == 0) +#define MG72_18PL ~(1 << 7) +#else +#define MG72_18PL 0xFFFF +#endif +#define MG72_12PL 0x00FD +#define MG72 (MG72_11PL & MG72_12PL & MG72_13PL & MG72_14PL & \ + MG72_15PL & MG72_16PL & MG72_17PL & MG72_18PL) +// End of MG72: + +// Beginning of MG73: +#if (G71PL >= G73PL) || (G71PL == 0) +#define MG73_11PL ~(1) +#else +#define MG73_11PL 0xFFFF +#endif +#if (G72PL >= G73PL) || (G72PL == 0) +#define MG73_12PL ~(1 << 1) +#else +#define MG73_12PL 0xFFFF +#endif +#if (G74PL >= G73PL) || (G74PL == 0) +#define MG73_14PL ~(1 << 3) +#else +#define MG73_14PL 0xFFFF +#endif +#if (G75PL >= G73PL) || (G75PL == 0) +#define MG73_15PL ~(1 << 4) +#else +#define MG73_15PL 0xFFFF +#endif +#if (G76PL >= G73PL) || (G76PL == 0) +#define MG73_16PL ~(1 << 5) +#else +#define MG73_16PL 0xFFFF +#endif +#if (G77PL >= G73PL) || (G77PL == 0) +#define MG73_17PL ~(1 << 6) +#else +#define MG73_17PL 0xFFFF +#endif +#if (G78PL >= G73PL) || (G78PL == 0) +#define MG73_18PL ~(1 << 7) +#else +#define MG73_18PL 0xFFFF +#endif +#define MG73_13PL 0x00FB +#define MG73 (MG73_11PL & MG73_12PL & MG73_13PL & MG73_14PL & \ + MG73_15PL & MG73_16PL & MG73_17PL & MG73_18PL) +// End of MG73: + +// Beginning of MG74: +#if (G71PL >= G74PL) || (G71PL == 0) +#define MG74_11PL ~(1) +#else +#define MG74_11PL 0xFFFF +#endif +#if (G72PL >= G74PL) || (G72PL == 0) +#define MG74_12PL ~(1 << 1) +#else +#define MG74_12PL 0xFFFF +#endif +#if (G73PL >= G74PL) || (G73PL == 0) +#define MG74_13PL ~(1 << 2) +#else +#define MG74_13PL 0xFFFF +#endif +#if (G75PL >= G74PL) || (G75PL == 0) +#define MG74_15PL ~(1 << 4) +#else +#define MG74_15PL 0xFFFF +#endif +#if (G76PL >= G74PL) || (G76PL == 0) +#define MG74_16PL ~(1 << 5) +#else +#define MG74_16PL 0xFFFF +#endif +#if (G77PL >= G74PL) || (G77PL == 0) +#define MG74_17PL ~(1 << 6) +#else +#define MG74_17PL 0xFFFF +#endif +#if (G78PL >= G74PL) || (G78PL == 0) +#define MG74_18PL ~(1 << 7) +#else +#define MG74_18PL 0xFFFF +#endif +#define MG74_14PL 0x00F7 +#define MG74 (MG74_11PL & MG74_12PL & MG74_13PL & MG74_14PL & \ + MG74_15PL & MG74_16PL & MG74_17PL & MG74_18PL) +// End of MG74: + +// Beginning of MG75: +#if (G71PL >= G75PL) || (G71PL == 0) +#define MG75_11PL ~(1) +#else +#define MG75_11PL 0xFFFF +#endif +#if (G72PL >= G75PL) || (G72PL == 0) +#define MG75_12PL ~(1 << 1) +#else +#define MG75_12PL 0xFFFF +#endif +#if (G73PL >= G75PL) || (G73PL == 0) +#define MG75_13PL ~(1 << 2) +#else +#define MG75_13PL 0xFFFF +#endif +#if (G74PL >= G75PL) || (G74PL == 0) +#define MG75_14PL ~(1 << 3) +#else +#define MG75_14PL 0xFFFF +#endif +#if (G76PL >= G75PL) || (G76PL == 0) +#define MG75_16PL ~(1 << 5) +#else +#define MG75_16PL 0xFFFF +#endif +#if (G77PL >= G75PL) || (G77PL == 0) +#define MG75_17PL ~(1 << 6) +#else +#define MG75_17PL 0xFFFF +#endif +#if (G78PL >= G75PL) || (G78PL == 0) +#define MG75_18PL ~(1 << 7) +#else +#define MG75_18PL 0xFFFF +#endif +#define MG75_15PL 0x00EF +#define MG75 (MG75_11PL & MG75_12PL & MG75_13PL & MG75_14PL & \ + MG75_15PL & MG75_16PL & MG75_17PL & MG75_18PL) +// End of MG75: + +// Beginning of MG76: +#if (G71PL >= G76PL) || (G71PL == 0) +#define MG76_11PL ~(1) +#else +#define MG76_11PL 0xFFFF +#endif +#if (G72PL >= G76PL) || (G72PL == 0) +#define MG76_12PL ~(1 << 1) +#else +#define MG76_12PL 0xFFFF +#endif +#if (G73PL >= G76PL) || (G73PL == 0) +#define MG76_13PL ~(1 << 2) +#else +#define MG76_13PL 0xFFFF +#endif +#if (G74PL >= G76PL) || (G74PL == 0) +#define MG76_14PL ~(1 << 3) +#else +#define MG76_14PL 0xFFFF +#endif +#if (G75PL >= G76PL) || (G75PL == 0) +#define MG76_15PL ~(1 << 4) +#else +#define MG76_15PL 0xFFFF +#endif +#if (G77PL >= G76PL) || (G77PL == 0) +#define MG76_17PL ~(1 << 6) +#else +#define MG76_17PL 0xFFFF +#endif +#if (G78PL >= G76PL) || (G78PL == 0) +#define MG76_18PL ~(1 << 7) +#else +#define MG76_18PL 0xFFFF +#endif +#define MG76_16PL 0x00DF +#define MG76 (MG76_11PL & MG76_12PL & MG76_13PL & MG76_14PL & \ + MG76_15PL & MG76_16PL & MG76_17PL & MG76_18PL) +// End of MG76: + +// Beginning of MG77: +#if (G71PL >= G77PL) || (G71PL == 0) +#define MG77_11PL ~(1) +#else +#define MG77_11PL 0xFFFF +#endif +#if (G72PL >= G77PL) || (G72PL == 0) +#define MG77_12PL ~(1 << 1) +#else +#define MG77_12PL 0xFFFF +#endif +#if (G73PL >= G77PL) || (G73PL == 0) +#define MG77_13PL ~(1 << 2) +#else +#define MG77_13PL 0xFFFF +#endif +#if (G74PL >= G77PL) || (G74PL == 0) +#define MG77_14PL ~(1 << 3) +#else +#define MG77_14PL 0xFFFF +#endif +#if (G75PL >= G77PL) || (G75PL == 0) +#define MG77_15PL ~(1 << 4) +#else +#define MG77_15PL 0xFFFF +#endif +#if (G76PL >= G77PL) || (G76PL == 0) +#define MG77_16PL ~(1 << 5) +#else +#define MG77_16PL 0xFFFF +#endif +#if (G78PL >= G77PL) || (G78PL == 0) +#define MG77_18PL ~(1 << 7) +#else +#define MG77_18PL 0xFFFF +#endif +#define MG77_17PL 0x00BF +#define MG77 (MG77_11PL & MG77_12PL & MG77_13PL & MG77_14PL & \ + MG77_15PL & MG77_16PL & MG77_17PL & MG77_18PL) +// End of MG77: + +// Beginning of MG78: +#if (G71PL >= G78PL) || (G71PL == 0) +#define MG78_11PL ~(1) +#else +#define MG78_11PL 0xFFFF +#endif +#if (G72PL >= G78PL) || (G72PL == 0) +#define MG78_12PL ~(1 << 1) +#else +#define MG78_12PL 0xFFFF +#endif +#if (G73PL >= G78PL) || (G73PL == 0) +#define MG78_13PL ~(1 << 2) +#else +#define MG78_13PL 0xFFFF +#endif +#if (G74PL >= G78PL) || (G74PL == 0) +#define MG78_14PL ~(1 << 3) +#else +#define MG78_14PL 0xFFFF +#endif +#if (G75PL >= G78PL) || (G75PL == 0) +#define MG78_15PL ~(1 << 4) +#else +#define MG78_15PL 0xFFFF +#endif +#if (G76PL >= G78PL) || (G76PL == 0) +#define MG78_16PL ~(1 << 5) +#else +#define MG78_16PL 0xFFFF +#endif +#if (G77PL >= G78PL) || (G77PL == 0) +#define MG78_17PL ~(1 << 6) +#else +#define MG78_17PL 0xFFFF +#endif +#define MG78_18PL 0x007F +#define MG78 (MG78_11PL & MG78_12PL & MG78_13PL & MG78_14PL & \ + MG78_15PL & MG78_16PL & MG78_17PL & MG78_18PL) +// End of MG78: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG81 to MG88: +// + +// Beginning of MG81: +#if (G82PL >= G81PL) || (G82PL == 0) +#define MG81_12PL ~(1 << 1) +#else +#define MG81_12PL 0xFFFF +#endif +#if (G83PL >= G81PL) || (G83PL == 0) +#define MG81_13PL ~(1 << 2) +#else +#define MG81_13PL 0xFFFF +#endif +#if (G84PL >= G81PL) || (G84PL == 0) +#define MG81_14PL ~(1 << 3) +#else +#define MG81_14PL 0xFFFF +#endif +#if (G85PL >= G81PL) || (G85PL == 0) +#define MG81_15PL ~(1 << 4) +#else +#define MG81_15PL 0xFFFF +#endif +#if (G86PL >= G81PL) || (G86PL == 0) +#define MG81_16PL ~(1 << 5) +#else +#define MG81_16PL 0xFFFF +#endif +#if (G87PL >= G81PL) || (G87PL == 0) +#define MG81_17PL ~(1 << 6) +#else +#define MG81_17PL 0xFFFF +#endif +#if (G88PL >= G81PL) || (G88PL == 0) +#define MG81_18PL ~(1 << 7) +#else +#define MG81_18PL 0xFFFF +#endif +#define MG81_11PL 0x00FE +#define MG81 (MG81_11PL & MG81_12PL & MG81_13PL & MG81_14PL & \ + MG81_15PL & MG81_16PL & MG81_17PL & MG81_18PL) +// End of MG81: + +// Beginning of MG82: +#if (G81PL >= G82PL) || (G81PL == 0) +#define MG82_11PL ~(1) +#else +#define MG82_11PL 0xFFFF +#endif +#if (G83PL >= G82PL) || (G83PL == 0) +#define MG82_13PL ~(1 << 2) +#else +#define MG82_13PL 0xFFFF +#endif +#if (G84PL >= G82PL) || (G84PL == 0) +#define MG82_14PL ~(1 << 3) +#else +#define MG82_14PL 0xFFFF +#endif +#if (G85PL >= G82PL) || (G85PL == 0) +#define MG82_15PL ~(1 << 4) +#else +#define MG82_15PL 0xFFFF +#endif +#if (G86PL >= G82PL) || (G86PL == 0) +#define MG82_16PL ~(1 << 5) +#else +#define MG82_16PL 0xFFFF +#endif +#if (G87PL >= G82PL) || (G87PL == 0) +#define MG82_17PL ~(1 << 6) +#else +#define MG82_17PL 0xFFFF +#endif +#if (G88PL >= G82PL) || (G88PL == 0) +#define MG82_18PL ~(1 << 7) +#else +#define MG82_18PL 0xFFFF +#endif +#define MG82_12PL 0x00FD +#define MG82 (MG82_11PL & MG82_12PL & MG82_13PL & MG82_14PL & \ + MG82_15PL & MG82_16PL & MG82_17PL & MG82_18PL) +// End of MG82: + +// Beginning of MG83: +#if (G81PL >= G83PL) || (G81PL == 0) +#define MG83_11PL ~(1) +#else +#define MG83_11PL 0xFFFF +#endif +#if (G82PL >= G83PL) || (G82PL == 0) +#define MG83_12PL ~(1 << 1) +#else +#define MG83_12PL 0xFFFF +#endif +#if (G84PL >= G83PL) || (G84PL == 0) +#define MG83_14PL ~(1 << 3) +#else +#define MG83_14PL 0xFFFF +#endif +#if (G85PL >= G83PL) || (G85PL == 0) +#define MG83_15PL ~(1 << 4) +#else +#define MG83_15PL 0xFFFF +#endif +#if (G86PL >= G83PL) || (G86PL == 0) +#define MG83_16PL ~(1 << 5) +#else +#define MG83_16PL 0xFFFF +#endif +#if (G87PL >= G83PL) || (G87PL == 0) +#define MG83_17PL ~(1 << 6) +#else +#define MG83_17PL 0xFFFF +#endif +#if (G88PL >= G83PL) || (G88PL == 0) +#define MG83_18PL ~(1 << 7) +#else +#define MG83_18PL 0xFFFF +#endif +#define MG83_13PL 0x00FB +#define MG83 (MG83_11PL & MG83_12PL & MG83_13PL & MG83_14PL & \ + MG83_15PL & MG83_16PL & MG83_17PL & MG83_18PL) +// End of MG83: + +// Beginning of MG84: +#if (G81PL >= G84PL) || (G81PL == 0) +#define MG84_11PL ~(1) +#else +#define MG84_11PL 0xFFFF +#endif +#if (G82PL >= G84PL) || (G82PL == 0) +#define MG84_12PL ~(1 << 1) +#else +#define MG84_12PL 0xFFFF +#endif +#if (G83PL >= G84PL) || (G83PL == 0) +#define MG84_13PL ~(1 << 2) +#else +#define MG84_13PL 0xFFFF +#endif +#if (G85PL >= G84PL) || (G85PL == 0) +#define MG84_15PL ~(1 << 4) +#else +#define MG84_15PL 0xFFFF +#endif +#if (G86PL >= G84PL) || (G86PL == 0) +#define MG84_16PL ~(1 << 5) +#else +#define MG84_16PL 0xFFFF +#endif +#if (G87PL >= G84PL) || (G87PL == 0) +#define MG84_17PL ~(1 << 6) +#else +#define MG84_17PL 0xFFFF +#endif +#if (G88PL >= G84PL) || (G88PL == 0) +#define MG84_18PL ~(1 << 7) +#else +#define MG84_18PL 0xFFFF +#endif +#define MG84_14PL 0x00F7 +#define MG84 (MG84_11PL & MG84_12PL & MG84_13PL & MG84_14PL & \ + MG84_15PL & MG84_16PL & MG84_17PL & MG84_18PL) +// End of MG84: + +// Beginning of MG85: +#if (G81PL >= G85PL) || (G81PL == 0) +#define MG85_11PL ~(1) +#else +#define MG85_11PL 0xFFFF +#endif +#if (G82PL >= G85PL) || (G82PL == 0) +#define MG85_12PL ~(1 << 1) +#else +#define MG85_12PL 0xFFFF +#endif +#if (G83PL >= G85PL) || (G83PL == 0) +#define MG85_13PL ~(1 << 2) +#else +#define MG85_13PL 0xFFFF +#endif +#if (G84PL >= G85PL) || (G84PL == 0) +#define MG85_14PL ~(1 << 3) +#else +#define MG85_14PL 0xFFFF +#endif +#if (G86PL >= G85PL) || (G86PL == 0) +#define MG85_16PL ~(1 << 5) +#else +#define MG85_16PL 0xFFFF +#endif +#if (G87PL >= G85PL) || (G87PL == 0) +#define MG85_17PL ~(1 << 6) +#else +#define MG85_17PL 0xFFFF +#endif +#if (G88PL >= G85PL) || (G88PL == 0) +#define MG85_18PL ~(1 << 7) +#else +#define MG85_18PL 0xFFFF +#endif +#define MG85_15PL 0x00EF +#define MG85 (MG85_11PL & MG85_12PL & MG85_13PL & MG85_14PL & \ + MG85_15PL & MG85_16PL & MG85_17PL & MG85_18PL) +// End of MG85: + +// Beginning of MG86: +#if (G81PL >= G86PL) || (G81PL == 0) +#define MG86_11PL ~(1) +#else +#define MG86_11PL 0xFFFF +#endif +#if (G82PL >= G86PL) || (G82PL == 0) +#define MG86_12PL ~(1 << 1) +#else +#define MG86_12PL 0xFFFF +#endif +#if (G83PL >= G86PL) || (G83PL == 0) +#define MG86_13PL ~(1 << 2) +#else +#define MG86_13PL 0xFFFF +#endif +#if (G84PL >= G86PL) || (G84PL == 0) +#define MG86_14PL ~(1 << 3) +#else +#define MG86_14PL 0xFFFF +#endif +#if (G85PL >= G86PL) || (G85PL == 0) +#define MG86_15PL ~(1 << 4) +#else +#define MG86_15PL 0xFFFF +#endif +#if (G87PL >= G86PL) || (G87PL == 0) +#define MG86_17PL ~(1 << 6) +#else +#define MG86_17PL 0xFFFF +#endif +#if (G88PL >= G86PL) || (G88PL == 0) +#define MG86_18PL ~(1 << 7) +#else +#define MG86_18PL 0xFFFF +#endif +#define MG86_16PL 0x00DF +#define MG86 (MG86_11PL & MG86_12PL & MG86_13PL & MG86_14PL & \ + MG86_15PL & MG86_16PL & MG86_17PL & MG86_18PL) +// End of MG86: + +// Beginning of MG87: +#if (G81PL >= G87PL) || (G81PL == 0) +#define MG87_11PL ~(1) +#else +#define MG87_11PL 0xFFFF +#endif +#if (G82PL >= G87PL) || (G82PL == 0) +#define MG87_12PL ~(1 << 1) +#else +#define MG87_12PL 0xFFFF +#endif +#if (G83PL >= G87PL) || (G83PL == 0) +#define MG87_13PL ~(1 << 2) +#else +#define MG87_13PL 0xFFFF +#endif +#if (G84PL >= G87PL) || (G84PL == 0) +#define MG87_14PL ~(1 << 3) +#else +#define MG87_14PL 0xFFFF +#endif +#if (G85PL >= G87PL) || (G85PL == 0) +#define MG87_15PL ~(1 << 4) +#else +#define MG87_15PL 0xFFFF +#endif +#if (G86PL >= G87PL) || (G86PL == 0) +#define MG87_16PL ~(1 << 5) +#else +#define MG87_16PL 0xFFFF +#endif +#if (G88PL >= G87PL) || (G88PL == 0) +#define MG87_18PL ~(1 << 7) +#else +#define MG87_18PL 0xFFFF +#endif +#define MG87_17PL 0x00BF +#define MG87 (MG87_11PL & MG87_12PL & MG87_13PL & MG87_14PL & \ + MG87_15PL & MG87_16PL & MG87_17PL & MG87_18PL) +// End of MG87: + +// Beginning of MG88: +#if (G81PL >= G88PL) || (G81PL == 0) +#define MG88_11PL ~(1) +#else +#define MG88_11PL 0xFFFF +#endif +#if (G82PL >= G88PL) || (G82PL == 0) +#define MG88_12PL ~(1 << 1) +#else +#define MG88_12PL 0xFFFF +#endif +#if (G83PL >= G88PL) || (G83PL == 0) +#define MG88_13PL ~(1 << 2) +#else +#define MG88_13PL 0xFFFF +#endif +#if (G84PL >= G88PL) || (G84PL == 0) +#define MG88_14PL ~(1 << 3) +#else +#define MG88_14PL 0xFFFF +#endif +#if (G85PL >= G88PL) || (G85PL == 0) +#define MG88_15PL ~(1 << 4) +#else +#define MG88_15PL 0xFFFF +#endif +#if (G86PL >= G88PL) || (G86PL == 0) +#define MG88_16PL ~(1 << 5) +#else +#define MG88_16PL 0xFFFF +#endif +#if (G87PL >= G88PL) || (G87PL == 0) +#define MG88_17PL ~(1 << 6) +#else +#define MG88_17PL 0xFFFF +#endif +#define MG88_18PL 0x007F +#define MG88 (MG88_11PL & MG88_12PL & MG88_13PL & MG88_14PL & \ + MG88_15PL & MG88_16PL & MG88_17PL & MG88_18PL) +// End of MG88: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG91 to MG98: +// + +// Beginning of MG91: +#if (G92PL >= G91PL) || (G92PL == 0) +#define MG91_12PL ~(1 << 1) +#else +#define MG91_12PL 0xFFFF +#endif +#if (G93PL >= G91PL) || (G93PL == 0) +#define MG91_13PL ~(1 << 2) +#else +#define MG91_13PL 0xFFFF +#endif +#if (G94PL >= G91PL) || (G94PL == 0) +#define MG91_14PL ~(1 << 3) +#else +#define MG91_14PL 0xFFFF +#endif +#if (G95PL >= G91PL) || (G95PL == 0) +#define MG91_15PL ~(1 << 4) +#else +#define MG91_15PL 0xFFFF +#endif +#if (G96PL >= G91PL) || (G96PL == 0) +#define MG91_16PL ~(1 << 5) +#else +#define MG91_16PL 0xFFFF +#endif +#if (G97PL >= G91PL) || (G97PL == 0) +#define MG91_17PL ~(1 << 6) +#else +#define MG91_17PL 0xFFFF +#endif +#if (G98PL >= G91PL) || (G98PL == 0) +#define MG91_18PL ~(1 << 7) +#else +#define MG91_18PL 0xFFFF +#endif +#define MG91_11PL 0x00FE +#define MG91 (MG91_11PL & MG91_12PL & MG91_13PL & MG91_14PL & \ + MG91_15PL & MG91_16PL & MG91_17PL & MG91_18PL) +// End of MG91: + +// Beginning of MG92: +#if (G91PL >= G92PL) || (G91PL == 0) +#define MG92_11PL ~(1) +#else +#define MG92_11PL 0xFFFF +#endif +#if (G93PL >= G92PL) || (G93PL == 0) +#define MG92_13PL ~(1 << 2) +#else +#define MG92_13PL 0xFFFF +#endif +#if (G94PL >= G92PL) || (G94PL == 0) +#define MG92_14PL ~(1 << 3) +#else +#define MG92_14PL 0xFFFF +#endif +#if (G95PL >= G92PL) || (G95PL == 0) +#define MG92_15PL ~(1 << 4) +#else +#define MG92_15PL 0xFFFF +#endif +#if (G96PL >= G92PL) || (G96PL == 0) +#define MG92_16PL ~(1 << 5) +#else +#define MG92_16PL 0xFFFF +#endif +#if (G97PL >= G92PL) || (G97PL == 0) +#define MG92_17PL ~(1 << 6) +#else +#define MG92_17PL 0xFFFF +#endif +#if (G98PL >= G92PL) || (G98PL == 0) +#define MG92_18PL ~(1 << 7) +#else +#define MG92_18PL 0xFFFF +#endif +#define MG92_12PL 0x00FD +#define MG92 (MG92_11PL & MG92_12PL & MG92_13PL & MG92_14PL & \ + MG92_15PL & MG92_16PL & MG92_17PL & MG92_18PL) +// End of MG92: + +// Beginning of MG93: +#if (G91PL >= G93PL) || (G91PL == 0) +#define MG93_11PL ~(1) +#else +#define MG93_11PL 0xFFFF +#endif +#if (G92PL >= G93PL) || (G92PL == 0) +#define MG93_12PL ~(1 << 1) +#else +#define MG93_12PL 0xFFFF +#endif +#if (G94PL >= G93PL) || (G94PL == 0) +#define MG93_14PL ~(1 << 3) +#else +#define MG93_14PL 0xFFFF +#endif +#if (G95PL >= G93PL) || (G95PL == 0) +#define MG93_15PL ~(1 << 4) +#else +#define MG93_15PL 0xFFFF +#endif +#if (G96PL >= G93PL) || (G96PL == 0) +#define MG93_16PL ~(1 << 5) +#else +#define MG93_16PL 0xFFFF +#endif +#if (G97PL >= G93PL) || (G97PL == 0) +#define MG93_17PL ~(1 << 6) +#else +#define MG93_17PL 0xFFFF +#endif +#if (G98PL >= G93PL) || (G98PL == 0) +#define MG93_18PL ~(1 << 7) +#else +#define MG93_18PL 0xFFFF +#endif +#define MG93_13PL 0x00FB +#define MG93 (MG93_11PL & MG93_12PL & MG93_13PL & MG93_14PL & \ + MG93_15PL & MG93_16PL & MG93_17PL & MG93_18PL) +// End of MG93: + +// Beginning of MG94: +#if (G91PL >= G94PL) || (G91PL == 0) +#define MG94_11PL ~(1) +#else +#define MG94_11PL 0xFFFF +#endif +#if (G92PL >= G94PL) || (G92PL == 0) +#define MG94_12PL ~(1 << 1) +#else +#define MG94_12PL 0xFFFF +#endif +#if (G93PL >= G94PL) || (G93PL == 0) +#define MG94_13PL ~(1 << 2) +#else +#define MG94_13PL 0xFFFF +#endif +#if (G95PL >= G94PL) || (G95PL == 0) +#define MG94_15PL ~(1 << 4) +#else +#define MG94_15PL 0xFFFF +#endif +#if (G96PL >= G94PL) || (G96PL == 0) +#define MG94_16PL ~(1 << 5) +#else +#define MG94_16PL 0xFFFF +#endif +#if (G97PL >= G94PL) || (G97PL == 0) +#define MG94_17PL ~(1 << 6) +#else +#define MG94_17PL 0xFFFF +#endif +#if (G98PL >= G94PL) || (G98PL == 0) +#define MG94_18PL ~(1 << 7) +#else +#define MG94_18PL 0xFFFF +#endif +#define MG94_14PL 0x00F7 +#define MG94 (MG94_11PL & MG94_12PL & MG94_13PL & MG94_14PL & \ + MG94_15PL & MG94_16PL & MG94_17PL & MG94_18PL) +// End of MG94: + +// Beginning of MG95: +#if (G91PL >= G95PL) || (G91PL == 0) +#define MG95_11PL ~(1) +#else +#define MG95_11PL 0xFFFF +#endif +#if (G92PL >= G95PL) || (G92PL == 0) +#define MG95_12PL ~(1 << 1) +#else +#define MG95_12PL 0xFFFF +#endif +#if (G93PL >= G95PL) || (G93PL == 0) +#define MG95_13PL ~(1 << 2) +#else +#define MG95_13PL 0xFFFF +#endif +#if (G94PL >= G95PL) || (G94PL == 0) +#define MG95_14PL ~(1 << 3) +#else +#define MG95_14PL 0xFFFF +#endif +#if (G96PL >= G95PL) || (G96PL == 0) +#define MG95_16PL ~(1 << 5) +#else +#define MG95_16PL 0xFFFF +#endif +#if (G97PL >= G95PL) || (G97PL == 0) +#define MG95_17PL ~(1 << 6) +#else +#define MG95_17PL 0xFFFF +#endif +#if (G98PL >= G95PL) || (G98PL == 0) +#define MG95_18PL ~(1 << 7) +#else +#define MG95_18PL 0xFFFF +#endif +#define MG95_15PL 0x00EF +#define MG95 (MG95_11PL & MG95_12PL & MG95_13PL & MG95_14PL & \ + MG95_15PL & MG95_16PL & MG95_17PL & MG95_18PL) +// End of MG95: + +// Beginning of MG96: +#if (G91PL >= G96PL) || (G91PL == 0) +#define MG96_11PL ~(1) +#else +#define MG96_11PL 0xFFFF +#endif +#if (G92PL >= G96PL) || (G92PL == 0) +#define MG96_12PL ~(1 << 1) +#else +#define MG96_12PL 0xFFFF +#endif +#if (G93PL >= G96PL) || (G93PL == 0) +#define MG96_13PL ~(1 << 2) +#else +#define MG96_13PL 0xFFFF +#endif +#if (G94PL >= G96PL) || (G94PL == 0) +#define MG96_14PL ~(1 << 3) +#else +#define MG96_14PL 0xFFFF +#endif +#if (G95PL >= G96PL) || (G95PL == 0) +#define MG96_15PL ~(1 << 4) +#else +#define MG96_15PL 0xFFFF +#endif +#if (G97PL >= G96PL) || (G97PL == 0) +#define MG96_17PL ~(1 << 6) +#else +#define MG96_17PL 0xFFFF +#endif +#if (G98PL >= G96PL) || (G98PL == 0) +#define MG96_18PL ~(1 << 7) +#else +#define MG96_18PL 0xFFFF +#endif +#define MG96_16PL 0x00DF +#define MG96 (MG96_11PL & MG96_12PL & MG96_13PL & MG96_14PL & \ + MG96_15PL & MG96_16PL & MG96_17PL & MG96_18PL) +// End of MG96: + +// Beginning of MG97: +#if (G91PL >= G97PL) || (G91PL == 0) +#define MG97_11PL ~(1) +#else +#define MG97_11PL 0xFFFF +#endif +#if (G92PL >= G97PL) || (G92PL == 0) +#define MG97_12PL ~(1 << 1) +#else +#define MG97_12PL 0xFFFF +#endif +#if (G93PL >= G97PL) || (G93PL == 0) +#define MG97_13PL ~(1 << 2) +#else +#define MG97_13PL 0xFFFF +#endif +#if (G94PL >= G97PL) || (G94PL == 0) +#define MG97_14PL ~(1 << 3) +#else +#define MG97_14PL 0xFFFF +#endif +#if (G95PL >= G97PL) || (G95PL == 0) +#define MG97_15PL ~(1 << 4) +#else +#define MG97_15PL 0xFFFF +#endif +#if (G96PL >= G97PL) || (G96PL == 0) +#define MG97_16PL ~(1 << 5) +#else +#define MG97_16PL 0xFFFF +#endif +#if (G98PL >= G97PL) || (G98PL == 0) +#define MG97_18PL ~(1 << 7) +#else +#define MG97_18PL 0xFFFF +#endif +#define MG97_17PL 0x00BF +#define MG97 (MG97_11PL & MG97_12PL & MG97_13PL & MG97_14PL & \ + MG97_15PL & MG97_16PL & MG97_17PL & MG97_18PL) +// End of MG97: + +// Beginning of MG98: +#if (G91PL >= G98PL) || (G91PL == 0) +#define MG98_11PL ~(1) +#else +#define MG98_11PL 0xFFFF +#endif +#if (G92PL >= G98PL) || (G92PL == 0) +#define MG98_12PL ~(1 << 1) +#else +#define MG98_12PL 0xFFFF +#endif +#if (G93PL >= G98PL) || (G93PL == 0) +#define MG98_13PL ~(1 << 2) +#else +#define MG98_13PL 0xFFFF +#endif +#if (G94PL >= G98PL) || (G94PL == 0) +#define MG98_14PL ~(1 << 3) +#else +#define MG98_14PL 0xFFFF +#endif +#if (G95PL >= G98PL) || (G95PL == 0) +#define MG98_15PL ~(1 << 4) +#else +#define MG98_15PL 0xFFFF +#endif +#if (G96PL >= G98PL) || (G96PL == 0) +#define MG98_16PL ~(1 << 5) +#else +#define MG98_16PL 0xFFFF +#endif +#if (G97PL >= G98PL) || (G97PL == 0) +#define MG98_17PL ~(1 << 6) +#else +#define MG98_17PL 0xFFFF +#endif +#define MG98_18PL 0x007F +#define MG98 (MG98_11PL & MG98_12PL & MG98_13PL & MG98_14PL & \ + MG98_15PL & MG98_16PL & MG98_17PL & MG98_18PL) +// End of MG98: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG101 to MG108: +// + +// Beginning of MG101: +#if (G102PL >= G101PL) || (G102PL == 0) +#define MG101_12PL ~(1 << 1) +#else +#define MG101_12PL 0xFFFF +#endif +#if (G103PL >= G101PL) || (G103PL == 0) +#define MG101_13PL ~(1 << 2) +#else +#define MG101_13PL 0xFFFF +#endif +#if (G104PL >= G101PL) || (G104PL == 0) +#define MG101_14PL ~(1 << 3) +#else +#define MG101_14PL 0xFFFF +#endif +#if (G105PL >= G101PL) || (G105PL == 0) +#define MG101_15PL ~(1 << 4) +#else +#define MG101_15PL 0xFFFF +#endif +#if (G106PL >= G101PL) || (G106PL == 0) +#define MG101_16PL ~(1 << 5) +#else +#define MG101_16PL 0xFFFF +#endif +#if (G107PL >= G101PL) || (G107PL == 0) +#define MG101_17PL ~(1 << 6) +#else +#define MG101_17PL 0xFFFF +#endif +#if (G108PL >= G101PL) || (G108PL == 0) +#define MG101_18PL ~(1 << 7) +#else +#define MG101_18PL 0xFFFF +#endif +#define MG101_11PL 0x00FE +#define MG101 (MG101_11PL & MG101_12PL & MG101_13PL & MG101_14PL & \ + MG101_15PL & MG101_16PL & MG101_17PL & MG101_18PL) +// End of MG101: + +// Beginning of MG102: +#if (G101PL >= G102PL) || (G101PL == 0) +#define MG102_11PL ~(1) +#else +#define MG102_11PL 0xFFFF +#endif +#if (G103PL >= G102PL) || (G103PL == 0) +#define MG102_13PL ~(1 << 2) +#else +#define MG102_13PL 0xFFFF +#endif +#if (G104PL >= G102PL) || (G104PL == 0) +#define MG102_14PL ~(1 << 3) +#else +#define MG102_14PL 0xFFFF +#endif +#if (G105PL >= G102PL) || (G105PL == 0) +#define MG102_15PL ~(1 << 4) +#else +#define MG102_15PL 0xFFFF +#endif +#if (G106PL >= G102PL) || (G106PL == 0) +#define MG102_16PL ~(1 << 5) +#else +#define MG102_16PL 0xFFFF +#endif +#if (G107PL >= G102PL) || (G107PL == 0) +#define MG102_17PL ~(1 << 6) +#else +#define MG102_17PL 0xFFFF +#endif +#if (G108PL >= G102PL) || (G108PL == 0) +#define MG102_18PL ~(1 << 7) +#else +#define MG102_18PL 0xFFFF +#endif +#define MG102_12PL 0x00FD +#define MG102 (MG102_11PL & MG102_12PL & MG102_13PL & MG102_14PL & \ + MG102_15PL & MG102_16PL & MG102_17PL & MG102_18PL) +// End of MG102: + +// Beginning of MG103: +#if (G101PL >= G103PL) || (G101PL == 0) +#define MG103_11PL ~(1) +#else +#define MG103_11PL 0xFFFF +#endif +#if (G102PL >= G103PL) || (G102PL == 0) +#define MG103_12PL ~(1 << 1) +#else +#define MG103_12PL 0xFFFF +#endif +#if (G104PL >= G103PL) || (G104PL == 0) +#define MG103_14PL ~(1 << 3) +#else +#define MG103_14PL 0xFFFF +#endif +#if (G105PL >= G103PL) || (G105PL == 0) +#define MG103_15PL ~(1 << 4) +#else +#define MG103_15PL 0xFFFF +#endif +#if (G106PL >= G103PL) || (G106PL == 0) +#define MG103_16PL ~(1 << 5) +#else +#define MG103_16PL 0xFFFF +#endif +#if (G107PL >= G103PL) || (G107PL == 0) +#define MG103_17PL ~(1 << 6) +#else +#define MG103_17PL 0xFFFF +#endif +#if (G108PL >= G103PL) || (G108PL == 0) +#define MG103_18PL ~(1 << 7) +#else +#define MG103_18PL 0xFFFF +#endif +#define MG103_13PL 0x00FB +#define MG103 (MG103_11PL & MG103_12PL & MG103_13PL & MG103_14PL & \ + MG103_15PL & MG103_16PL & MG103_17PL & MG103_18PL) +// End of MG103: + +// Beginning of MG104: +#if (G101PL >= G104PL) || (G101PL == 0) +#define MG104_11PL ~(1) +#else +#define MG104_11PL 0xFFFF +#endif +#if (G102PL >= G104PL) || (G102PL == 0) +#define MG104_12PL ~(1 << 1) +#else +#define MG104_12PL 0xFFFF +#endif +#if (G103PL >= G104PL) || (G103PL == 0) +#define MG104_13PL ~(1 << 2) +#else +#define MG104_13PL 0xFFFF +#endif +#if (G105PL >= G104PL) || (G105PL == 0) +#define MG104_15PL ~(1 << 4) +#else +#define MG104_15PL 0xFFFF +#endif +#if (G106PL >= G104PL) || (G106PL == 0) +#define MG104_16PL ~(1 << 5) +#else +#define MG104_16PL 0xFFFF +#endif +#if (G107PL >= G104PL) || (G107PL == 0) +#define MG104_17PL ~(1 << 6) +#else +#define MG104_17PL 0xFFFF +#endif +#if (G108PL >= G104PL) || (G108PL == 0) +#define MG104_18PL ~(1 << 7) +#else +#define MG104_18PL 0xFFFF +#endif +#define MG104_14PL 0x00F7 +#define MG104 (MG104_11PL & MG104_12PL & MG104_13PL & MG104_14PL & \ + MG104_15PL & MG104_16PL & MG104_17PL & MG104_18PL) +// End of MG104: + +// Beginning of MG105: +#if (G101PL >= G105PL) || (G101PL == 0) +#define MG105_11PL ~(1) +#else +#define MG105_11PL 0xFFFF +#endif +#if (G102PL >= G105PL) || (G102PL == 0) +#define MG105_12PL ~(1 << 1) +#else +#define MG105_12PL 0xFFFF +#endif +#if (G103PL >= G105PL) || (G103PL == 0) +#define MG105_13PL ~(1 << 2) +#else +#define MG105_13PL 0xFFFF +#endif +#if (G104PL >= G105PL) || (G104PL == 0) +#define MG105_14PL ~(1 << 3) +#else +#define MG105_14PL 0xFFFF +#endif +#if (G106PL >= G105PL) || (G106PL == 0) +#define MG105_16PL ~(1 << 5) +#else +#define MG105_16PL 0xFFFF +#endif +#if (G107PL >= G105PL) || (G107PL == 0) +#define MG105_17PL ~(1 << 6) +#else +#define MG105_17PL 0xFFFF +#endif +#if (G108PL >= G105PL) || (G108PL == 0) +#define MG105_18PL ~(1 << 7) +#else +#define MG105_18PL 0xFFFF +#endif +#define MG105_15PL 0x00EF +#define MG105 (MG105_11PL & MG105_12PL & MG105_13PL & MG105_14PL & \ + MG105_15PL & MG105_16PL & MG105_17PL & MG105_18PL) +// End of MG105: + +// Beginning of MG106: +#if (G101PL >= G106PL) || (G101PL == 0) +#define MG106_11PL ~(1) +#else +#define MG106_11PL 0xFFFF +#endif +#if (G102PL >= G106PL) || (G102PL == 0) +#define MG106_12PL ~(1 << 1) +#else +#define MG106_12PL 0xFFFF +#endif +#if (G103PL >= G106PL) || (G103PL == 0) +#define MG106_13PL ~(1 << 2) +#else +#define MG106_13PL 0xFFFF +#endif +#if (G104PL >= G106PL) || (G104PL == 0) +#define MG106_14PL ~(1 << 3) +#else +#define MG106_14PL 0xFFFF +#endif +#if (G105PL >= G106PL) || (G105PL == 0) +#define MG106_15PL ~(1 << 4) +#else +#define MG106_15PL 0xFFFF +#endif +#if (G107PL >= G106PL) || (G107PL == 0) +#define MG106_17PL ~(1 << 6) +#else +#define MG106_17PL 0xFFFF +#endif +#if (G108PL >= G106PL) || (G108PL == 0) +#define MG106_18PL ~(1 << 7) +#else +#define MG106_18PL 0xFFFF +#endif +#define MG106_16PL 0x00DF +#define MG106 (MG106_11PL & MG106_12PL & MG106_13PL & MG106_14PL & \ + MG106_15PL & MG106_16PL & MG106_17PL & MG106_18PL) +// End of MG106: + +// Beginning of MG107: +#if (G101PL >= G107PL) || (G101PL == 0) +#define MG107_11PL ~(1) +#else +#define MG107_11PL 0xFFFF +#endif +#if (G102PL >= G107PL) || (G102PL == 0) +#define MG107_12PL ~(1 << 1) +#else +#define MG107_12PL 0xFFFF +#endif +#if (G103PL >= G107PL) || (G103PL == 0) +#define MG107_13PL ~(1 << 2) +#else +#define MG107_13PL 0xFFFF +#endif +#if (G104PL >= G107PL) || (G104PL == 0) +#define MG107_14PL ~(1 << 3) +#else +#define MG107_14PL 0xFFFF +#endif +#if (G105PL >= G107PL) || (G105PL == 0) +#define MG107_15PL ~(1 << 4) +#else +#define MG107_15PL 0xFFFF +#endif +#if (G106PL >= G107PL) || (G106PL == 0) +#define MG107_16PL ~(1 << 5) +#else +#define MG107_16PL 0xFFFF +#endif +#if (G108PL >= G107PL) || (G108PL == 0) +#define MG107_18PL ~(1 << 7) +#else +#define MG107_18PL 0xFFFF +#endif +#define MG107_17PL 0x00BF +#define MG107 (MG107_11PL & MG107_12PL & MG107_13PL & MG107_14PL & \ + MG107_15PL & MG107_16PL & MG107_17PL & MG107_18PL) +// End of MG107: + +// Beginning of MG108: +#if (G101PL >= G108PL) || (G101PL == 0) +#define MG108_11PL ~(1) +#else +#define MG108_11PL 0xFFFF +#endif +#if (G102PL >= G108PL) || (G102PL == 0) +#define MG108_12PL ~(1 << 1) +#else +#define MG108_12PL 0xFFFF +#endif +#if (G103PL >= G108PL) || (G103PL == 0) +#define MG108_13PL ~(1 << 2) +#else +#define MG108_13PL 0xFFFF +#endif +#if (G104PL >= G108PL) || (G104PL == 0) +#define MG108_14PL ~(1 << 3) +#else +#define MG108_14PL 0xFFFF +#endif +#if (G105PL >= G108PL) || (G105PL == 0) +#define MG108_15PL ~(1 << 4) +#else +#define MG108_15PL 0xFFFF +#endif +#if (G106PL >= G108PL) || (G106PL == 0) +#define MG108_16PL ~(1 << 5) +#else +#define MG108_16PL 0xFFFF +#endif +#if (G107PL >= G108PL) || (G107PL == 0) +#define MG108_17PL ~(1 << 6) +#else +#define MG108_17PL 0xFFFF +#endif +#define MG108_18PL 0x007F +#define MG108 (MG108_11PL & MG108_12PL & MG108_13PL & MG108_14PL & \ + MG108_15PL & MG108_16PL & MG108_17PL & MG108_18PL) +// End of MG108: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG111 to MG118: +// + +// Beginning of MG111: +#if (G112PL >= G111PL) || (G112PL == 0) +#define MG111_12PL ~(1 << 1) +#else +#define MG111_12PL 0xFFFF +#endif +#if (G113PL >= G111PL) || (G113PL == 0) +#define MG111_13PL ~(1 << 2) +#else +#define MG111_13PL 0xFFFF +#endif +#if (G114PL >= G111PL) || (G114PL == 0) +#define MG111_14PL ~(1 << 3) +#else +#define MG111_14PL 0xFFFF +#endif +#if (G115PL >= G111PL) || (G115PL == 0) +#define MG111_15PL ~(1 << 4) +#else +#define MG111_15PL 0xFFFF +#endif +#if (G116PL >= G111PL) || (G116PL == 0) +#define MG111_16PL ~(1 << 5) +#else +#define MG111_16PL 0xFFFF +#endif +#if (G117PL >= G111PL) || (G117PL == 0) +#define MG111_17PL ~(1 << 6) +#else +#define MG111_17PL 0xFFFF +#endif +#if (G118PL >= G111PL) || (G118PL == 0) +#define MG111_18PL ~(1 << 7) +#else +#define MG111_18PL 0xFFFF +#endif +#define MG111_11PL 0x00FE +#define MG111 (MG111_11PL & MG111_12PL & MG111_13PL & MG111_14PL & \ + MG111_15PL & MG111_16PL & MG111_17PL & MG111_18PL) +// End of MG111: + +// Beginning of MG112: +#if (G111PL >= G112PL) || (G111PL == 0) +#define MG112_11PL ~(1) +#else +#define MG112_11PL 0xFFFF +#endif +#if (G113PL >= G112PL) || (G113PL == 0) +#define MG112_13PL ~(1 << 2) +#else +#define MG112_13PL 0xFFFF +#endif +#if (G114PL >= G112PL) || (G114PL == 0) +#define MG112_14PL ~(1 << 3) +#else +#define MG112_14PL 0xFFFF +#endif +#if (G115PL >= G112PL) || (G115PL == 0) +#define MG112_15PL ~(1 << 4) +#else +#define MG112_15PL 0xFFFF +#endif +#if (G116PL >= G112PL) || (G116PL == 0) +#define MG112_16PL ~(1 << 5) +#else +#define MG112_16PL 0xFFFF +#endif +#if (G117PL >= G112PL) || (G117PL == 0) +#define MG112_17PL ~(1 << 6) +#else +#define MG112_17PL 0xFFFF +#endif +#if (G118PL >= G112PL) || (G118PL == 0) +#define MG112_18PL ~(1 << 7) +#else +#define MG112_18PL 0xFFFF +#endif +#define MG112_12PL 0x00FD +#define MG112 (MG112_11PL & MG112_12PL & MG112_13PL & MG112_14PL & \ + MG112_15PL & MG112_16PL & MG112_17PL & MG112_18PL) +// End of MG112: + +// Beginning of MG113: +#if (G111PL >= G113PL) || (G111PL == 0) +#define MG113_11PL ~(1) +#else +#define MG113_11PL 0xFFFF +#endif +#if (G112PL >= G113PL) || (G112PL == 0) +#define MG113_12PL ~(1 << 1) +#else +#define MG113_12PL 0xFFFF +#endif +#if (G114PL >= G113PL) || (G114PL == 0) +#define MG113_14PL ~(1 << 3) +#else +#define MG113_14PL 0xFFFF +#endif +#if (G115PL >= G113PL) || (G115PL == 0) +#define MG113_15PL ~(1 << 4) +#else +#define MG113_15PL 0xFFFF +#endif +#if (G116PL >= G113PL) || (G116PL == 0) +#define MG113_16PL ~(1 << 5) +#else +#define MG113_16PL 0xFFFF +#endif +#if (G117PL >= G113PL) || (G117PL == 0) +#define MG113_17PL ~(1 << 6) +#else +#define MG113_17PL 0xFFFF +#endif +#if (G118PL >= G113PL) || (G118PL == 0) +#define MG113_18PL ~(1 << 7) +#else +#define MG113_18PL 0xFFFF +#endif +#define MG113_13PL 0x00FB +#define MG113 (MG113_11PL & MG113_12PL & MG113_13PL & MG113_14PL & \ + MG113_15PL & MG113_16PL & MG113_17PL & MG113_18PL) +// End of MG113: + +// Beginning of MG114: +#if (G111PL >= G114PL) || (G111PL == 0) +#define MG114_11PL ~(1) +#else +#define MG114_11PL 0xFFFF +#endif +#if (G112PL >= G114PL) || (G112PL == 0) +#define MG114_12PL ~(1 << 1) +#else +#define MG114_12PL 0xFFFF +#endif +#if (G113PL >= G114PL) || (G113PL == 0) +#define MG114_13PL ~(1 << 2) +#else +#define MG114_13PL 0xFFFF +#endif +#if (G115PL >= G114PL) || (G115PL == 0) +#define MG114_15PL ~(1 << 4) +#else +#define MG114_15PL 0xFFFF +#endif +#if (G116PL >= G114PL) || (G116PL == 0) +#define MG114_16PL ~(1 << 5) +#else +#define MG114_16PL 0xFFFF +#endif +#if (G117PL >= G114PL) || (G117PL == 0) +#define MG114_17PL ~(1 << 6) +#else +#define MG114_17PL 0xFFFF +#endif +#if (G118PL >= G114PL) || (G118PL == 0) +#define MG114_18PL ~(1 << 7) +#else +#define MG114_18PL 0xFFFF +#endif +#define MG114_14PL 0x00F7 +#define MG114 (MG114_11PL & MG114_12PL & MG114_13PL & MG114_14PL & \ + MG114_15PL & MG114_16PL & MG114_17PL & MG114_18PL) +// End of MG114: + +// Beginning of MG115: +#if (G111PL >= G115PL) || (G111PL == 0) +#define MG115_11PL ~(1) +#else +#define MG115_11PL 0xFFFF +#endif +#if (G112PL >= G115PL) || (G112PL == 0) +#define MG115_12PL ~(1 << 1) +#else +#define MG115_12PL 0xFFFF +#endif +#if (G113PL >= G115PL) || (G113PL == 0) +#define MG115_13PL ~(1 << 2) +#else +#define MG115_13PL 0xFFFF +#endif +#if (G114PL >= G115PL) || (G114PL == 0) +#define MG115_14PL ~(1 << 3) +#else +#define MG115_14PL 0xFFFF +#endif +#if (G116PL >= G115PL) || (G116PL == 0) +#define MG115_16PL ~(1 << 5) +#else +#define MG115_16PL 0xFFFF +#endif +#if (G117PL >= G115PL) || (G117PL == 0) +#define MG115_17PL ~(1 << 6) +#else +#define MG115_17PL 0xFFFF +#endif +#if (G118PL >= G115PL) || (G118PL == 0) +#define MG115_18PL ~(1 << 7) +#else +#define MG115_18PL 0xFFFF +#endif +#define MG115_15PL 0x00EF +#define MG115 (MG115_11PL & MG115_12PL & MG115_13PL & MG115_14PL & \ + MG115_15PL & MG115_16PL & MG115_17PL & MG115_18PL) +// End of MG115: + +// Beginning of MG116: +#if (G111PL >= G116PL) || (G111PL == 0) +#define MG116_11PL ~(1) +#else +#define MG116_11PL 0xFFFF +#endif +#if (G112PL >= G116PL) || (G112PL == 0) +#define MG116_12PL ~(1 << 1) +#else +#define MG116_12PL 0xFFFF +#endif +#if (G113PL >= G116PL) || (G113PL == 0) +#define MG116_13PL ~(1 << 2) +#else +#define MG116_13PL 0xFFFF +#endif +#if (G114PL >= G116PL) || (G114PL == 0) +#define MG116_14PL ~(1 << 3) +#else +#define MG116_14PL 0xFFFF +#endif +#if (G115PL >= G116PL) || (G115PL == 0) +#define MG116_15PL ~(1 << 4) +#else +#define MG116_15PL 0xFFFF +#endif +#if (G117PL >= G116PL) || (G117PL == 0) +#define MG116_17PL ~(1 << 6) +#else +#define MG116_17PL 0xFFFF +#endif +#if (G118PL >= G116PL) || (G118PL == 0) +#define MG116_18PL ~(1 << 7) +#else +#define MG116_18PL 0xFFFF +#endif +#define MG116_16PL 0x00DF +#define MG116 (MG116_11PL & MG116_12PL & MG116_13PL & MG116_14PL & \ + MG116_15PL & MG116_16PL & MG116_17PL & MG116_18PL) +// End of MG116: + +// Beginning of MG117: +#if (G111PL >= G117PL) || (G111PL == 0) +#define MG117_11PL ~(1) +#else +#define MG117_11PL 0xFFFF +#endif +#if (G112PL >= G117PL) || (G112PL == 0) +#define MG117_12PL ~(1 << 1) +#else +#define MG117_12PL 0xFFFF +#endif +#if (G113PL >= G117PL) || (G113PL == 0) +#define MG117_13PL ~(1 << 2) +#else +#define MG117_13PL 0xFFFF +#endif +#if (G114PL >= G117PL) || (G114PL == 0) +#define MG117_14PL ~(1 << 3) +#else +#define MG117_14PL 0xFFFF +#endif +#if (G115PL >= G117PL) || (G115PL == 0) +#define MG117_15PL ~(1 << 4) +#else +#define MG117_15PL 0xFFFF +#endif +#if (G116PL >= G117PL) || (G116PL == 0) +#define MG117_16PL ~(1 << 5) +#else +#define MG117_16PL 0xFFFF +#endif +#if (G118PL >= G117PL) || (G118PL == 0) +#define MG117_18PL ~(1 << 7) +#else +#define MG117_18PL 0xFFFF +#endif +#define MG117_17PL 0x00BF +#define MG117 (MG117_11PL & MG117_12PL & MG117_13PL & MG117_14PL & \ + MG117_15PL & MG117_16PL & MG117_17PL & MG117_18PL) +// End of MG117: + +// Beginning of MG118: +#if (G111PL >= G118PL) || (G111PL == 0) +#define MG118_11PL ~(1) +#else +#define MG118_11PL 0xFFFF +#endif +#if (G112PL >= G118PL) || (G112PL == 0) +#define MG118_12PL ~(1 << 1) +#else +#define MG118_12PL 0xFFFF +#endif +#if (G113PL >= G118PL) || (G113PL == 0) +#define MG118_13PL ~(1 << 2) +#else +#define MG118_13PL 0xFFFF +#endif +#if (G114PL >= G118PL) || (G114PL == 0) +#define MG118_14PL ~(1 << 3) +#else +#define MG118_14PL 0xFFFF +#endif +#if (G115PL >= G118PL) || (G115PL == 0) +#define MG118_15PL ~(1 << 4) +#else +#define MG118_15PL 0xFFFF +#endif +#if (G116PL >= G118PL) || (G116PL == 0) +#define MG118_16PL ~(1 << 5) +#else +#define MG118_16PL 0xFFFF +#endif +#if (G117PL >= G118PL) || (G117PL == 0) +#define MG118_17PL ~(1 << 6) +#else +#define MG118_17PL 0xFFFF +#endif +#define MG118_18PL 0x007F +#define MG118 (MG118_11PL & MG118_12PL & MG118_13PL & MG118_14PL & \ + MG118_15PL & MG118_16PL & MG118_17PL & MG118_18PL) +// End of MG118: + +//------------------------------------------------------------------------------- +// Automatically generate PIEIER1 interrupt masks MG121 to MG128: +// + +// Beginning of MG121: +#if (G122PL >= G121PL) || (G122PL == 0) +#define MG121_12PL ~(1 << 1) +#else +#define MG121_12PL 0xFFFF +#endif +#if (G123PL >= G121PL) || (G123PL == 0) +#define MG121_13PL ~(1 << 2) +#else +#define MG121_13PL 0xFFFF +#endif +#if (G124PL >= G121PL) || (G124PL == 0) +#define MG121_14PL ~(1 << 3) +#else +#define MG121_14PL 0xFFFF +#endif +#if (G125PL >= G121PL) || (G125PL == 0) +#define MG121_15PL ~(1 << 4) +#else +#define MG121_15PL 0xFFFF +#endif +#if (G126PL >= G121PL) || (G126PL == 0) +#define MG121_16PL ~(1 << 5) +#else +#define MG121_16PL 0xFFFF +#endif +#if (G127PL >= G121PL) || (G127PL == 0) +#define MG121_17PL ~(1 << 6) +#else +#define MG121_17PL 0xFFFF +#endif +#if (G128PL >= G121PL) || (G128PL == 0) +#define MG121_18PL ~(1 << 7) +#else +#define MG121_18PL 0xFFFF +#endif +#define MG121_11PL 0x00FE +#define MG121 (MG121_11PL & MG121_12PL & MG121_13PL & MG121_14PL & \ + MG121_15PL & MG121_16PL & MG121_17PL & MG121_18PL) +// End of MG121: + +// Beginning of MG121: +#if (G121PL >= G122PL) || (G121PL == 0) +#define MG122_11PL ~(1) +#else +#define MG122_11PL 0xFFFF +#endif +#if (G123PL >= G122PL) || (G123PL == 0) +#define MG122_13PL ~(1 << 2) +#else +#define MG122_13PL 0xFFFF +#endif +#if (G124PL >= G122PL) || (G124PL == 0) +#define MG122_14PL ~(1 << 3) +#else +#define MG122_14PL 0xFFFF +#endif +#if (G125PL >= G122PL) || (G125PL == 0) +#define MG122_15PL ~(1 << 4) +#else +#define MG122_15PL 0xFFFF +#endif +#if (G126PL >= G122PL) || (G126PL == 0) +#define MG122_16PL ~(1 << 5) +#else +#define MG122_16PL 0xFFFF +#endif +#if (G127PL >= G122PL) || (G127PL == 0) +#define MG122_17PL ~(1 << 6) +#else +#define MG122_17PL 0xFFFF +#endif +#if (G128PL >= G122PL) || (G128PL == 0) +#define MG122_18PL ~(1 << 7) +#else +#define MG122_18PL 0xFFFF +#endif +#define MG122_12PL 0x00FD +#define MG122 (MG122_11PL & MG122_12PL & MG122_13PL & MG122_14PL & \ + MG122_15PL & MG122_16PL & MG122_17PL & MG122_18PL) +// End of MG122: + +// Beginning of MG123: +#if (G121PL >= G123PL) || (G121PL == 0) +#define MG123_11PL ~(1) +#else +#define MG123_11PL 0xFFFF +#endif +#if (G122PL >= G123PL) || (G122PL == 0) +#define MG123_12PL ~(1 << 1) +#else +#define MG123_12PL 0xFFFF +#endif +#if (G124PL >= G123PL) || (G124PL == 0) +#define MG123_14PL ~(1 << 3) +#else +#define MG123_14PL 0xFFFF +#endif +#if (G125PL >= G123PL) || (G125PL == 0) +#define MG123_15PL ~(1 << 4) +#else +#define MG123_15PL 0xFFFF +#endif +#if (G126PL >= G123PL) || (G126PL == 0) +#define MG123_16PL ~(1 << 5) +#else +#define MG123_16PL 0xFFFF +#endif +#if (G127PL >= G123PL) || (G127PL == 0) +#define MG123_17PL ~(1 << 6) +#else +#define MG123_17PL 0xFFFF +#endif +#if (G128PL >= G123PL) || (G128PL == 0) +#define MG123_18PL ~(1 << 7) +#else +#define MG123_18PL 0xFFFF +#endif +#define MG123_13PL 0x00FB +#define MG123 (MG123_11PL & MG123_12PL & MG123_13PL & MG123_14PL & \ + MG123_15PL & MG123_16PL & MG123_17PL & MG123_18PL) +// End of MG123: + +// Beginning of MG124: +#if (G121PL >= G124PL) || (G121PL == 0) +#define MG124_11PL ~(1) +#else +#define MG124_11PL 0xFFFF +#endif +#if (G122PL >= G124PL) || (G122PL == 0) +#define MG124_12PL ~(1 << 1) +#else +#define MG124_12PL 0xFFFF +#endif +#if (G123PL >= G124PL) || (G123PL == 0) +#define MG124_13PL ~(1 << 2) +#else +#define MG124_13PL 0xFFFF +#endif +#if (G125PL >= G124PL) || (G125PL == 0) +#define MG124_15PL ~(1 << 4) +#else +#define MG124_15PL 0xFFFF +#endif +#if (G126PL >= G124PL) || (G126PL == 0) +#define MG124_16PL ~(1 << 5) +#else +#define MG124_16PL 0xFFFF +#endif +#if (G127PL >= G124PL) || (G127PL == 0) +#define MG124_17PL ~(1 << 6) +#else +#define MG124_17PL 0xFFFF +#endif +#if (G128PL >= G124PL) || (G128PL == 0) +#define MG124_18PL ~(1 << 7) +#else +#define MG124_18PL 0xFFFF +#endif +#define MG124_14PL 0x00F7 +#define MG124 (MG124_11PL & MG124_12PL & MG124_13PL & MG124_14PL & \ + MG124_15PL & MG124_16PL & MG124_17PL & MG124_18PL) +// End of MG124: + +// Beginning of MG125: +#if (G121PL >= G125PL) || (G121PL == 0) +#define MG125_11PL ~(1) +#else +#define MG125_11PL 0xFFFF +#endif +#if (G122PL >= G125PL) || (G122PL == 0) +#define MG125_12PL ~(1 << 1) +#else +#define MG125_12PL 0xFFFF +#endif +#if (G123PL >= G125PL) || (G123PL == 0) +#define MG125_13PL ~(1 << 2) +#else +#define MG125_13PL 0xFFFF +#endif +#if (G124PL >= G125PL) || (G124PL == 0) +#define MG125_14PL ~(1 << 3) +#else +#define MG125_14PL 0xFFFF +#endif +#if (G126PL >= G125PL) || (G126PL == 0) +#define MG125_16PL ~(1 << 5) +#else +#define MG125_16PL 0xFFFF +#endif +#if (G127PL >= G125PL) || (G127PL == 0) +#define MG125_17PL ~(1 << 6) +#else +#define MG125_17PL 0xFFFF +#endif +#if (G128PL >= G125PL) || (G128PL == 0) +#define MG125_18PL ~(1 << 7) +#else +#define MG125_18PL 0xFFFF +#endif +#define MG125_15PL 0x00EF +#define MG125 (MG125_11PL & MG125_12PL & MG125_13PL & MG125_14PL & \ + MG125_15PL & MG125_16PL & MG125_17PL & MG125_18PL) +// End of MG125: + +// Beginning of MG126: +#if (G121PL >= G126PL) || (G121PL == 0) +#define MG126_11PL ~(1) +#else +#define MG126_11PL 0xFFFF +#endif +#if (G122PL >= G126PL) || (G122PL == 0) +#define MG126_12PL ~(1 << 1) +#else +#define MG126_12PL 0xFFFF +#endif +#if (G123PL >= G126PL) || (G123PL == 0) +#define MG126_13PL ~(1 << 2) +#else +#define MG126_13PL 0xFFFF +#endif +#if (G124PL >= G126PL) || (G124PL == 0) +#define MG126_14PL ~(1 << 3) +#else +#define MG126_14PL 0xFFFF +#endif +#if (G125PL >= G126PL) || (G125PL == 0) +#define MG126_15PL ~(1 << 4) +#else +#define MG126_15PL 0xFFFF +#endif +#if (G127PL >= G126PL) || (G127PL == 0) +#define MG126_17PL ~(1 << 6) +#else +#define MG126_17PL 0xFFFF +#endif +#if (G128PL >= G126PL) || (G128PL == 0) +#define MG126_18PL ~(1 << 7) +#else +#define MG126_18PL 0xFFFF +#endif +#define MG126_16PL 0x00DF +#define MG126 (MG126_11PL & MG126_12PL & MG126_13PL & MG126_14PL & \ + MG126_15PL & MG126_16PL & MG126_17PL & MG126_18PL) +// End of MG126: + +// Beginning of MG127: +#if (G121PL >= G127PL) || (G121PL == 0) +#define MG127_11PL ~(1) +#else +#define MG127_11PL 0xFFFF +#endif +#if (G122PL >= G127PL) || (G122PL == 0) +#define MG127_12PL ~(1 << 1) +#else +#define MG127_12PL 0xFFFF +#endif +#if (G123PL >= G127PL) || (G123PL == 0) +#define MG127_13PL ~(1 << 2) +#else +#define MG127_13PL 0xFFFF +#endif +#if (G124PL >= G127PL) || (G124PL == 0) +#define MG127_14PL ~(1 << 3) +#else +#define MG127_14PL 0xFFFF +#endif +#if (G125PL >= G127PL) || (G125PL == 0) +#define MG127_15PL ~(1 << 4) +#else +#define MG127_15PL 0xFFFF +#endif +#if (G126PL >= G127PL) || (G126PL == 0) +#define MG127_16PL ~(1 << 5) +#else +#define MG127_16PL 0xFFFF +#endif +#if (G128PL >= G127PL) || (G128PL == 0) +#define MG127_18PL ~(1 << 7) +#else +#define MG127_18PL 0xFFFF +#endif +#define MG127_17PL 0x00BF +#define MG127 (MG127_11PL & MG127_12PL & MG127_13PL & MG127_14PL & \ + MG127_15PL & MG127_16PL & MG127_17PL & MG127_18PL) +// End of MG127: + +// Beginning of MG128: +#if (G121PL >= G128PL) || (G121PL == 0) +#define MG128_11PL ~(1) +#else +#define MG128_11PL 0xFFFF +#endif +#if (G122PL >= G128PL) || (G122PL == 0) +#define MG128_12PL ~(1 << 1) +#else +#define MG128_12PL 0xFFFF +#endif +#if (G123PL >= G128PL) || (G123PL == 0) +#define MG128_13PL ~(1 << 2) +#else +#define MG128_13PL 0xFFFF +#endif +#if (G124PL >= G128PL) || (G124PL == 0) +#define MG128_14PL ~(1 << 3) +#else +#define MG128_14PL 0xFFFF +#endif +#if (G125PL >= G128PL) || (G125PL == 0) +#define MG128_15PL ~(1 << 4) +#else +#define MG128_15PL 0xFFFF +#endif +#if (G126PL >= G128PL) || (G126PL == 0) +#define MG128_16PL ~(1 << 5) +#else +#define MG128_16PL 0xFFFF +#endif +#if (G127PL >= G128PL) || (G127PL == 0) +#define MG128_17PL ~(1 << 6) +#else +#define MG128_17PL 0xFFFF +#endif +#define MG128_18PL 0x007F +#define MG128 (MG128_11PL & MG128_12PL & MG128_13PL & MG128_14PL & \ + MG128_15PL & MG128_16PL & MG128_17PL & MG128_18PL) +// End of MG128: + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // eof + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/include/DSP28x_Project.h b/Source/External/v120/DSP2833x_common/include/DSP28x_Project.h new file mode 100644 index 0000000..399c1db --- /dev/null +++ b/Source/External/v120/DSP2833x_common/include/DSP28x_Project.h @@ -0,0 +1,22 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/Source/External/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm b/Source/External/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm new file mode 100644 index 0000000..7108ffa --- /dev/null +++ b/Source/External/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm @@ -0,0 +1,42 @@ +;; TI File $Revision: /main/1 $ +;; Checkin $Date: July 30, 2007 10:29:23 $ +;;########################################################################### +;; +;; FILE: ADC_cal.asm +;; +;; TITLE: 2833x Boot Rom ADC Cal routine. +;; +;; Functions: +;; +;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and ADCOFFTRIM registers +;; Notes: +;; +;;########################################################################### +;; $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;; $Release Date: August 1, 2008 $ +;;########################################################################### + + .def _ADC_cal + .asg "0x711C", ADCREFSEL_LOC + +;----------------------------------------------- +; _ADC_cal +;----------------------------------------------- +;----------------------------------------------- +; This is the ADC cal routine.This routine is programmed into +; reserved memory by the factory. 0xAAAA and 0xBBBB are place- +; holders for calibration data. +;The actual values programmed by TI are device specific. +; +; This function assumes that the clocks have been +; enabled to the ADC module. +;----------------------------------------------- + + .sect ".adc_cal" + +_ADC_cal + MOVW DP, #ADCREFSEL_LOC >> 6 + MOV @28, #0xAAAA ; actual value may not be 0xAAAA + MOV @29, #0xBBBB ; actual value may not be 0xBBBB + LRETR +;eof ---------- diff --git a/Source/External/v120/DSP2833x_common/source/DSP2833x_Adc.c b/Source/External/v120/DSP2833x_common/source/DSP2833x_Adc.c new file mode 100644 index 0000000..730415b --- /dev/null +++ b/Source/External/v120/DSP2833x_common/source/DSP2833x_Adc.c @@ -0,0 +1,65 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: October 23, 2007 13:34:09 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.c +// +// TITLE: DSP2833x ADC Initialization & Support Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#define ADC_usDELAY 5000L + +//--------------------------------------------------------------------------- +// InitAdc: +//--------------------------------------------------------------------------- +// This function initializes ADC to a known state. +// +void InitAdc(void) +{ + extern void DSP28x_usDelay(Uint32 Count); + + + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from TI reserved + // OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the + // Boot ROM. If the boot ROM code is bypassed during the debug process, the + // following function MUST be called for the ADC to function according + // to specification. The clocks to the ADC MUST be enabled before calling this + // function. + // See the device data manual and/or the ADC Reference + // Manual for more information. + + EALLOW; + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; + ADC_cal(); + EDIS; + + + + + // To powerup the ADC the ADCENCLK bit should be set first to enable + // clocks, followed by powering up the bandgap, reference circuitry, and ADC core. + // Before the first conversion is performed a 5ms delay must be observed + // after power up to give all analog circuits time to power up and settle + + // Please note that for the delay function below to operate correctly the + // CPU_RATE define statement in the DSP2833x_Examples.h file must + // contain the correct CPU clock period in nanoseconds. + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x01; + AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits + DELAY_US(ADC_usDELAY); // Delay before converting ADC channels +//pause_us(50L); +} + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c b/Source/External/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c new file mode 100644 index 0000000..b0dfd76 --- /dev/null +++ b/Source/External/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c @@ -0,0 +1,115 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: March 16, 2007 08:37:30 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.c +// +// TITLE: CPU 32-bit Timers Initialization & Support Functions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +struct CPUTIMER_VARS CpuTimer0; + +// CpuTimer 1 and CpuTimer2 are used by DSP BIOS & other RTOS. Comment out if using DSP BIOS or other RTOS. +struct CPUTIMER_VARS CpuTimer1; +struct CPUTIMER_VARS CpuTimer2; + +//--------------------------------------------------------------------------- +// InitCpuTimers: +//--------------------------------------------------------------------------- +// This function initializes all three CPU timers to a known state. +// +void InitCpuTimers(void) +{ + // CPU Timer 0 + // Initialize address pointers to respective timer registers: + CpuTimer0.RegsAddr = &CpuTimer0Regs; + // Initialize timer period to maximum: + CpuTimer0Regs.PRD.all = 0xFFFFFFFF; + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + CpuTimer0Regs.TPR.all = 0; + CpuTimer0Regs.TPRH.all = 0; + // Make sure timer is stopped: + CpuTimer0Regs.TCR.bit.TSS = 1; + // Reload all counter register with period value: + CpuTimer0Regs.TCR.bit.TRB = 1; + // Reset interrupt counters: + CpuTimer0.InterruptCount = 0; + + +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// Initialize address pointers to respective timer registers: + CpuTimer1.RegsAddr = &CpuTimer1Regs; + CpuTimer2.RegsAddr = &CpuTimer2Regs; + // Initialize timer period to maximum: + CpuTimer1Regs.PRD.all = 0xFFFFFFFF; + CpuTimer2Regs.PRD.all = 0xFFFFFFFF; + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + CpuTimer1Regs.TPR.all = 0; + CpuTimer1Regs.TPRH.all = 0; + CpuTimer2Regs.TPR.all = 0; + CpuTimer2Regs.TPRH.all = 0; + // Make sure timers are stopped: + CpuTimer1Regs.TCR.bit.TSS = 1; + CpuTimer2Regs.TCR.bit.TSS = 1; + // Reload all counter register with period value: + CpuTimer1Regs.TCR.bit.TRB = 1; + CpuTimer2Regs.TCR.bit.TRB = 1; + // Reset interrupt counters: + CpuTimer1.InterruptCount = 0; + CpuTimer2.InterruptCount = 0; + +} + +//--------------------------------------------------------------------------- +// ConfigCpuTimer: +//--------------------------------------------------------------------------- +// This function initializes the selected timer to the period specified +// by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz" +// and the period in "uSeconds". The timer is held in the stopped state +// after configuration. +// +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) +{ + Uint32 temp; + + // Initialize timer period: + Timer->CPUFreqInMHz = Freq; + Timer->PeriodInUSec = Period; + temp = (long) (Freq * Period); + Timer->RegsAddr->PRD.all = temp; + + // Set pre-scale counter to divide by 1 (SYSCLKOUT): + Timer->RegsAddr->TPR.all = 0; + Timer->RegsAddr->TPRH.all = 0; + + // Initialize timer control register: + Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer + Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer + Timer->RegsAddr->TCR.bit.SOFT = 0; + Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled + Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt + + // Reset interrupt counter: + Timer->InterruptCount = 0; +} + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c b/Source/External/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c new file mode 100644 index 0000000..f1eafe3 --- /dev/null +++ b/Source/External/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c @@ -0,0 +1,83 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:35 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.c +// +// TITLE: DSP2833x Device PIE Control Register Initialization Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitPieCtrl: +//--------------------------------------------------------------------------- +// This function initializes the PIE control registers to a known state. +// +void InitPieCtrl(void) +{ + // Disable Interrupts at the CPU level: + DINT; + + // Disable the PIE + PieCtrlRegs.PIECTRL.bit.ENPIE = 0; + + // Clear all PIEIER registers: + PieCtrlRegs.PIEIER1.all = 0; + PieCtrlRegs.PIEIER2.all = 0; + PieCtrlRegs.PIEIER3.all = 0; + PieCtrlRegs.PIEIER4.all = 0; + PieCtrlRegs.PIEIER5.all = 0; + PieCtrlRegs.PIEIER6.all = 0; + PieCtrlRegs.PIEIER7.all = 0; + PieCtrlRegs.PIEIER8.all = 0; + PieCtrlRegs.PIEIER9.all = 0; + PieCtrlRegs.PIEIER10.all = 0; + PieCtrlRegs.PIEIER11.all = 0; + PieCtrlRegs.PIEIER12.all = 0; + + // Clear all PIEIFR registers: + PieCtrlRegs.PIEIFR1.all = 0; + PieCtrlRegs.PIEIFR2.all = 0; + PieCtrlRegs.PIEIFR3.all = 0; + PieCtrlRegs.PIEIFR4.all = 0; + PieCtrlRegs.PIEIFR5.all = 0; + PieCtrlRegs.PIEIFR6.all = 0; + PieCtrlRegs.PIEIFR7.all = 0; + PieCtrlRegs.PIEIFR8.all = 0; + PieCtrlRegs.PIEIFR9.all = 0; + PieCtrlRegs.PIEIFR10.all = 0; + PieCtrlRegs.PIEIFR11.all = 0; + PieCtrlRegs.PIEIFR12.all = 0; + + +} + +//--------------------------------------------------------------------------- +// EnableInterrupts: +//--------------------------------------------------------------------------- +// This function enables the PIE module and CPU interrupts +// +void EnableInterrupts() +{ + + // Enable the PIE + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // Enables PIE to drive a pulse into the CPU + PieCtrlRegs.PIEACK.all = 0xFFFF; + + // Enable Interrupts at the CPU level + EINT; + +} + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/source/DSP2833x_PieVect.c b/Source/External/v120/DSP2833x_common/source/DSP2833x_PieVect.c new file mode 100644 index 0000000..d163c54 --- /dev/null +++ b/Source/External/v120/DSP2833x_common/source/DSP2833x_PieVect.c @@ -0,0 +1,204 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:38 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.c +// +// TITLE: DSP2833x Devices PIE Vector Table Initialization Functions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +const struct PIE_VECT_TABLE PieVectTableInit = { + + PIE_RESERVED, // 0 Reserved space + PIE_RESERVED, // 1 Reserved space + PIE_RESERVED, // 2 Reserved space + PIE_RESERVED, // 3 Reserved space + PIE_RESERVED, // 4 Reserved space + PIE_RESERVED, // 5 Reserved space + PIE_RESERVED, // 6 Reserved space + PIE_RESERVED, // 7 Reserved space + PIE_RESERVED, // 8 Reserved space + PIE_RESERVED, // 9 Reserved space + PIE_RESERVED, // 10 Reserved space + PIE_RESERVED, // 11 Reserved space + PIE_RESERVED, // 12 Reserved space + + +// Non-Peripheral Interrupts + INT13_ISR, // XINT13 or CPU-Timer 1 + INT14_ISR, // CPU-Timer2 + DATALOG_ISR, // Datalogging interrupt + RTOSINT_ISR, // RTOS interrupt + EMUINT_ISR, // Emulation interrupt + NMI_ISR, // Non-maskable interrupt + ILLEGAL_ISR, // Illegal operation TRAP + USER1_ISR, // User Defined trap 1 + USER2_ISR, // User Defined trap 2 + USER3_ISR, // User Defined trap 3 + USER4_ISR, // User Defined trap 4 + USER5_ISR, // User Defined trap 5 + USER6_ISR, // User Defined trap 6 + USER7_ISR, // User Defined trap 7 + USER8_ISR, // User Defined trap 8 + USER9_ISR, // User Defined trap 9 + USER10_ISR, // User Defined trap 10 + USER11_ISR, // User Defined trap 11 + USER12_ISR, // User Defined trap 12 + +// Group 1 PIE Vectors + SEQ1INT_ISR, // 1.1 ADC + SEQ2INT_ISR, // 1.2 ADC + rsvd_ISR, // 1.3 + XINT1_ISR, // 1.4 + XINT2_ISR, // 1.5 + ADCINT_ISR, // 1.6 ADC + TINT0_ISR, // 1.7 Timer 0 + WAKEINT_ISR, // 1.8 WD, Low Power + +// Group 2 PIE Vectors + EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone + EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone + EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone + EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone + EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone + EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone + rsvd_ISR, // 2.7 + rsvd_ISR, // 2.8 + +// Group 3 PIE Vectors + EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt + EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt + EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt + EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt + EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt + EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt + rsvd_ISR, // 3.7 + rsvd_ISR, // 3.8 + +// Group 4 PIE Vectors + ECAP1_INT_ISR, // 4.1 ECAP-1 + ECAP2_INT_ISR, // 4.2 ECAP-2 + ECAP3_INT_ISR, // 4.3 ECAP-3 + ECAP4_INT_ISR, // 4.4 ECAP-4 + ECAP5_INT_ISR, // 4.5 ECAP-5 + ECAP6_INT_ISR, // 4.6 ECAP-6 + rsvd_ISR, // 4.7 + rsvd_ISR, // 4.8 + +// Group 5 PIE Vectors + EQEP1_INT_ISR, // 5.1 EQEP-1 + EQEP2_INT_ISR, // 5.2 EQEP-2 + rsvd_ISR, // 5.3 + rsvd_ISR, // 5.4 + rsvd_ISR, // 5.5 + rsvd_ISR, // 5.6 + rsvd_ISR, // 5.7 + rsvd_ISR, // 5.8 + + +// Group 6 PIE Vectors + SPIRXINTA_ISR, // 6.1 SPI-A + SPITXINTA_ISR, // 6.2 SPI-A + MRINTA_ISR, // 6.3 McBSP-A + MXINTA_ISR, // 6.4 McBSP-A + MRINTB_ISR, // 6.5 McBSP-B + MXINTB_ISR, // 6.6 McBSP-B + rsvd_ISR, // 6.7 + rsvd_ISR, // 6.8 + + +// Group 7 PIE Vectors + DINTCH1_ISR, // 7.1 DMA channel 1 + DINTCH2_ISR, // 7.2 DMA channel 2 + DINTCH3_ISR, // 7.3 DMA channel 3 + DINTCH4_ISR, // 7.4 DMA channel 4 + DINTCH5_ISR, // 7.5 DMA channel 5 + DINTCH6_ISR, // 7.6 DMA channel 6 + rsvd_ISR, // 7.7 + rsvd_ISR, // 7.8 + +// Group 8 PIE Vectors + I2CINT1A_ISR, // 8.1 I2C + I2CINT2A_ISR, // 8.2 I2C + rsvd_ISR, // 8.3 + rsvd_ISR, // 8.4 + SCIRXINTC_ISR, // 8.5 SCI-C + SCITXINTC_ISR, // 8.6 SCI-C + rsvd_ISR, // 8.7 + rsvd_ISR, // 8.8 + +// Group 9 PIE Vectors + SCIRXINTA_ISR, // 9.1 SCI-A + SCITXINTA_ISR, // 9.2 SCI-A + SCIRXINTB_ISR, // 9.3 SCI-B + SCITXINTB_ISR, // 9.4 SCI-B + ECAN0INTA_ISR, // 9.5 eCAN-A + ECAN1INTA_ISR, // 9.6 eCAN-A + ECAN0INTB_ISR, // 9.7 eCAN-B + ECAN1INTB_ISR, // 9.8 eCAN-B + +// Group 10 PIE Vectors + rsvd_ISR, // 10.1 + rsvd_ISR, // 10.2 + rsvd_ISR, // 10.3 + rsvd_ISR, // 10.4 + rsvd_ISR, // 10.5 + rsvd_ISR, // 10.6 + rsvd_ISR, // 10.7 + rsvd_ISR, // 10.8 + +// Group 11 PIE Vectors + rsvd_ISR, // 11.1 + rsvd_ISR, // 11.2 + rsvd_ISR, // 11.3 + rsvd_ISR, // 11.4 + rsvd_ISR, // 11.5 + rsvd_ISR, // 11.6 + rsvd_ISR, // 11.7 + rsvd_ISR, // 11.8 + +// Group 12 PIE Vectors + XINT3_ISR, // 12.1 + XINT4_ISR, // 12.2 + XINT5_ISR, // 12.3 + XINT6_ISR, // 12.4 + XINT7_ISR, // 12.5 + rsvd_ISR, // 12.6 + LVF_ISR, // 12.7 + LUF_ISR, // 12.8 +}; + + +//--------------------------------------------------------------------------- +// InitPieVectTable: +//--------------------------------------------------------------------------- +// This function initializes the PIE vector table to a known state. +// This function must be executed after boot time. +// + +void InitPieVectTable(void) +{ + int16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + EALLOW; + for(i=0; i < 128; i++) + *Dest++ = *Source++; + EDIS; + + // Enable the PIE Vector Table + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + +} + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c b/Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c new file mode 100644 index 0000000..bf821e1 --- /dev/null +++ b/Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c @@ -0,0 +1,1863 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 14, 2008 11:28:12 $ +//########################################################################### +// +// FILE: DSP2833x_SWPrioritizedDefaultIsr.c +// +// TITLE: DSP2833x Device Default Software Prioritized Interrupt Service Routines. +// +//########################################################################### +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + + +// Connected to INT13 of CPU (use MINT13 mask): +// Note CPU-Timer1 is reserved for TI use, however XINT13 +// ISR can be used by the user. +#if (INT13PL != 0) +interrupt void INT13_ISR(void) // INT13 or CPU-Timer1 +{ + IER |= MINT13; // Set "global" priority + EINT; + + // Insert ISR Code here + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to INT14 of CPU (use MINT14 mask): +#if (INT14PL != 0) +interrupt void INT14_ISR(void) // CPU-Timer2 +{ + IER |= MINT14; // Set "global" priority + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to INT15 of CPU (use MINT15 mask): +#if (INT15PL != 0) +interrupt void DATALOG_ISR(void) // Datalogging interrupt +{ + IER |= MINT15; // Set "global" priority + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to INT16 of CPU (use MINT16 mask): +#if (INT16PL != 0) +interrupt void RTOSINT_ISR(void) // RTOS interrupt +{ + IER |= MINT16; // Set "global" priority + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to EMUINT of CPU (non-maskable): +interrupt void EMUINT_ISR(void) // Emulation interrupt +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// Connected to NMI of CPU (non-maskable): +interrupt void NMI_ISR(void) // Non-maskable interrupt +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +interrupt void USER1_ISR(void) // User Defined trap 1 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER2_ISR(void) // User Defined trap 2 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER3_ISR(void) // User Defined trap 3 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER4_ISR(void) // User Defined trap 4 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER5_ISR(void) // User Defined trap 5 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER6_ISR(void) // User Defined trap 6 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER7_ISR(void) // User Defined trap 7 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER8_ISR(void) // User Defined trap 8 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER9_ISR(void) // User Defined trap 9 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER10_ISR(void) // User Defined trap 10 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER11_ISR(void) // User Defined trap 11 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + +interrupt void USER12_ISR(void) // User Defined trap 12 +{ + EINT; + + // Insert ISR Code here....... + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} + + +// ----------------------------------------------------------- +// PIE Group 1 - MUXed into CPU INT1 +// ----------------------------------------------------------- + +// Connected to PIEIER1_1 (use MINT1 and MG11 masks): +#if (G11PL != 0) +interrupt void SEQ1INT_ISR( void ) // ADC +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER1_2 (use MINT1 and MG12 masks): +#if (G12PL != 0) +interrupt void SEQ2INT_ISR( void ) // ADC +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG12; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// Connected to PIEIER1_4 (use MINT1 and MG14 masks): +#if (G14PL != 0) +interrupt void XINT1_ISR(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG14; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER1_5 (use MINT1 and MG15 masks): +#if (G15PL != 0) +interrupt void XINT2_ISR(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG15; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + + +// Connected to PIEIER1_6 (use MINT1 and MG16 masks): +#if (G16PL != 0) +interrupt void ADCINT_ISR(void) // ADC +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG16; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER1_7 (use MINT1 and MG17 masks): +#if (G17PL != 0) +interrupt void TINT0_ISR(void) // CPU-Timer 0 +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG17; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER1_8 (use MINT1 and MG18 masks): +#if (G18PL != 0) +interrupt void WAKEINT_ISR(void) // WD/LPM +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; + IER |= M_INT1; + IER &= MINT1; // Set "global" priority + PieCtrlRegs.PIEIER1.all &= MG18; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER1.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 2 - MUXed into CPU INT2 +// ----------------------------------------------------------- + +// Connected to PIEIER2_1 (use MINT2 and MG21 masks): +#if (G21PL != 0) +interrupt void EPWM1_TZINT_ISR(void) // ePWM1 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG21; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER2_2 (use MINT2 and MG22 masks): +#if (G22PL != 0) +interrupt void EPWM2_TZINT_ISR(void) // ePWM2 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG22; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER2_3 (use MINT2 and MG23 masks): +#if (G23PL != 0) +interrupt void EPWM3_TZINT_ISR(void) // ePWM3 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG23; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER2_4 (use MINT2 and MG24 masks): +#if (G24PL != 0) +interrupt void EPWM4_TZINT_ISR(void) // ePWM4 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG24; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER2_5 (use MINT2 and MG25 masks): +#if (G25PL != 0) +interrupt void EPWM5_TZINT_ISR(void) // ePWM5 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG25; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER2_6 (use MINT2 and MG26 masks): +#if (G26PL != 0) +interrupt void EPWM6_TZINT_ISR(void) // ePWM6 Trip Zone +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG26; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 3 - MUXed into CPU INT3 +// ----------------------------------------------------------- + + +// Connected to PIEIER3_1 (use MINT3 and MG31 masks): +#if (G31PL != 0) +interrupt void EPWM1_INT_ISR(void) // ePWM1 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG31; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER3_2 (use MINT3 and MG32 masks): +#if (G32PL != 0) +interrupt void EPWM2_INT_ISR(void) // ePWM2 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG32; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER3_3 (use MINT3 and MG33 masks): +#if (G33PL != 0) +interrupt void EPWM3_INT_ISR(void) // ePWM3 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG33; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER3_4 (use MINT3 and MG34 masks): +#if (G34PL != 0) +interrupt void EPWM4_INT_ISR(void) // ePWM4 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG34; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER3_5 (use MINT3 and MG35 masks): +#if (G35PL != 0) +interrupt void EPWM5_INT_ISR(void) // ePWM5 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG35; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER3_6 (use MINT3 and MG36 masks): +#if (G36PL != 0) +interrupt void EPWM6_INT_ISR(void) // ePWM6 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG36; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 4 - MUXed into CPU INT4 +// ----------------------------------------------------------- + + +// Connected to PIEIER4_1 (use MINT4 and MG41 masks): +#if (G41PL != 0) +interrupt void ECAP1_INT_ISR(void) // eCAP1 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG41; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_2 (use MINT4 and MG42 masks): +#if (G42PL != 0) +interrupt void ECAP2_INT_ISR(void) // eCAP2 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG42; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_3 (use MINT4 and MG43 masks): +#if (G43PL != 0) +interrupt void ECAP3_INT_ISR(void) // eCAP3 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG43; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_4 (use MINT4 and MG44 masks): +#if (G44PL != 0) +interrupt void ECAP4_INT_ISR(void) // eCAP4 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG44; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_5 (use MINT4 and MG45 masks): +#if (G45PL != 0) +interrupt void ECAP5_INT_ISR(void) // eCAP5 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG45; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER4_6 (use MINT4 and MG46 masks): +#if (G46PL != 0) +interrupt void ECAP6_INT_ISR(void) // eCAP6 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG46; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + + +// ----------------------------------------------------------- +// PIE Group 5 - MUXed into CPU INT5 +// ----------------------------------------------------------- + +// Connected to PIEIER5_1 (use MINT5 and MG51 masks): +#if (G51PL != 0) +interrupt void EQEP1_INT_ISR(void) // eQEP1 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT5; + IER &= MINT5; // Set "global" priority + PieCtrlRegs.PIEIER5.all &= MG51; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER5.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER5_2 (use MINT5 and MG52 masks): +#if (G52PL != 0) +interrupt void EQEP2_INT_ISR(void) // eQEP2 Interrupt +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT5; + IER &= MINT5; // Set "global" priority + PieCtrlRegs.PIEIER5.all &= MG52; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER5.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// ----------------------------------------------------------- +// PIE Group 6 - MUXed into CPU INT6 +// ----------------------------------------------------------- + +// Connected to PIEIER6_1 (use MINT6 and MG61 masks): +#if (G61PL != 0) +interrupt void SPIRXINTA_ISR(void) // SPI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG61; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER6_2 (use MINT6 and MG62 masks): +#if (G62PL != 0) +interrupt void SPITXINTA_ISR(void) // SPI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG62; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER6_3 (use MINT6 and MG63 masks): +#if (G63PL != 0) +interrupt void MRINTB_ISR(void) // McBSP-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG63; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER6_4 (use MINT6 and MG64 masks): +#if (G64PL != 0) +interrupt void MXINTB_ISR(void) // McBSP-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG64; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + + +// Connected to PIEIER6_5 (use MINT6 and MG65 masks): +#if (G65PL != 0) +interrupt void MRINTA_ISR(void) // McBSP-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG65; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER6_6 (use MINT6 and MG66 masks): +#if (G66PL != 0) +interrupt void MXINTA_ISR(void) // McBSP-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all; + IER |= M_INT6; + IER &= MINT6; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG66; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER6.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 7 - MUXed into CPU INT7 +// ----------------------------------------------------------- + +// Connected to PIEIER7_1 (use MINT7 and MG71 masks): +#if (G71PL != 0) +interrupt void DINTCH1_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG71; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER7_2 (use MINT7 and MG72 masks): +#if (G72PL != 0) +interrupt void DINTCH2_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG72; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); +} +#endif + +// Connected to PIEIER7_3 (use MINT7 and MG73 masks): +#if (G73PL != 0) +interrupt void DINTCH3_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG73; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER7_4 (use MINT7 and MG74 masks): +#if (G74PL != 0) +interrupt void DINTCH4_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG74; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + + +// Connected to PIEIER7_5 (use MINT7 and MG75 masks): +#if (G75PL != 0) +interrupt void DINTCH5_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG75; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER7_6 (use MINT7 and MG76 masks): +#if (G76PL != 0) +interrupt void DINTCH6_ISR(void) // DMA +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all; + IER |= M_INT7; + IER &= MINT7; // Set "global" priority + PieCtrlRegs.PIEIER7.all &= MG76; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER7.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// ----------------------------------------------------------- +// PIE Group 8 - MUXed into CPU INT8 +// ----------------------------------------------------------- + +// Connected to PIEIER8_1 (use MINT8 and MG81 masks): +#if (G81PL != 0) +interrupt void I2CINT1A_ISR(void) // I2C-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG81; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER8_2 (use MINT8 and MG82 masks): +#if (G82PL != 0) +interrupt void I2CINT2A_ISR(void) // I2C-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG82; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER8_5 (use MINT8 and MG85 masks): +#if (G85PL != 0) +interrupt void SCIRXINTC_ISR(void) // SCI-C +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER6.all &= MG85; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER8_6 (use MINT8 and MG86 masks): +#if (G82PL != 0) +interrupt void SCITXINTC_ISR(void) // SCI-C +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all; + IER |= M_INT8; + IER &= MINT8; // Set "global" priority + PieCtrlRegs.PIEIER8.all &= MG86; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER8.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// ----------------------------------------------------------- +// PIE Group 9 - MUXed into CPU INT9 +// ----------------------------------------------------------- + +// Connected to PIEIER9_1 (use MINT9 and MG91 masks): +#if (G91PL != 0) +interrupt void SCIRXINTA_ISR(void) // SCI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_2 (use MINT9 and MG92 masks): +#if (G92PL != 0) +interrupt void SCITXINTA_ISR(void) // SCI-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// Connected to PIEIER9_3 (use MINT9 and MG93 masks): +#if (G93PL != 0) +interrupt void SCIRXINTB_ISR(void) // SCI-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_4 (use MINT9 and MG94 masks): +#if (G94PL != 0) +interrupt void SCITXINTB_ISR(void) // SCI-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_5 (use MINT9 and MG95 masks): +#if (G95PL != 0) +interrupt void ECAN0INTA_ISR(void) // eCAN-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_6 (use MINT9 and MG96 masks): +#if (G96PL != 0) +interrupt void ECAN1INTA_ISR(void) // eCAN-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_7 (use MINT9 and MG97 masks): +#if (G97PL != 0) +interrupt void ECAN0INTB_ISR(void) // eCAN-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER9_8 (use MINT9 and MG98 masks): +#if (G98PL != 0) +interrupt void ECAN1INTB_ISR(void) // eCAN-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// ----------------------------------------------------------- +// PIE Group 10 - MUXed into CPU INT10 +// ----------------------------------------------------------- +// ----------------------------------------------------------- +// PIE Group 11 - MUXed into CPU INT11 +// ----------------------------------------------------------- +// ----------------------------------------------------------- +// PIE Group 12 - MUXed into CPU INT12 +// ----------------------------------------------------------- + +// Connected to PIEIER9_1 (use MINT12 and MG121 masks): +#if (G121PL != 0) +interrupt void XINT3_ISR(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG121; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_2 (use MINT12 and MG122 masks): +#if (G122PL != 0) +interrupt void XINT4_ISR(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG122; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +// Connected to PIEIER12_3 (use MINT12 and MG123 masks): +#if (G123PL != 0) +interrupt void XINT5_ISR(void) // SCI-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG123; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_4 (use MINT12 and MG124 masks): +#if (G124PL != 0) +interrupt void XINT6_ISR(void) // SCI-B +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG124; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_5 (use MINT12 and MG125 masks): +#if (G125PL != 0) +interrupt void XINT7_ISR(void) // eCAN-A +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG125; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_7 (use MINT12 and MG127 masks): +#if (G127PL != 0) +interrupt void LVF_ISR(void) // FPU +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG127; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + +// Connected to PIEIER12_8 (use MINT12 and MG128 masks): +#if (G128PL != 0) +interrupt void LUF_ISR(void) // FPU +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all; + IER |= M_INT12; + IER &= MINT12; // Set "global" priority + PieCtrlRegs.PIEIER12.all &= MG128; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + // Insert ISR Code here....... + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER12.all = TempPIEIER; + + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + asm (" ESTOP0"); + for(;;); + +} +#endif + + +//--------------------------------------------------------------------------- +// Catch All Default ISRs: +// + +interrupt void PIE_RESERVED(void) // Reserved space. For test. +{ + asm (" ESTOP0"); + for(;;); +} + +interrupt void INT_NOTUSED_ISR(void) // Reserved space. For test. +{ + asm (" ESTOP0"); + for(;;); +} + +interrupt void rsvd_ISR(void) // For test +{ + asm (" ESTOP0"); + for(;;); +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c b/Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c new file mode 100644 index 0000000..99379ea --- /dev/null +++ b/Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c @@ -0,0 +1,511 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 4, 2007 14:25:31 $ +//########################################################################### +// +// FILE: DSP2833x_SWPiroritizedPieVect.c +// +// TITLE: DSP2833x Devices SW Prioritized PIE Vector Table Initialization. +// +//########################################################################### +// +// Original Source by A.T. +// +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +const struct PIE_VECT_TABLE PieVectTableInit = { + + PIE_RESERVED, // Reserved space + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + PIE_RESERVED, // reserved + +// Non-Peripheral Interrupts: + #if (INT13PL != 0) + INT13_ISR, // XINT13 + #else + INT_NOTUSED_ISR, + #endif + + #if (INT14PL != 0) + INT14_ISR, // CPU-Timer2 + #else + INT_NOTUSED_ISR, + #endif + + #if (INT15PL != 0) + DATALOG_ISR, // Datalogging interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (INT16PL != 0) + RTOSINT_ISR, // RTOS interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, // reserved interrupt + NMI_ISR, // Non-maskable interrupt + ILLEGAL_ISR, // Illegal operation TRAP + USER1_ISR, // User Defined trap 1 + USER2_ISR, // User Defined trap 2 + USER3_ISR, // User Defined trap 3 + USER4_ISR, // User Defined trap 4 + USER5_ISR, // User Defined trap 5 + USER6_ISR, // User Defined trap 6 + USER7_ISR, // User Defined trap 7 + USER8_ISR, // User Defined trap 8 + USER9_ISR, // User Defined trap 9 + USER10_ISR, // User Defined trap 10 + USER11_ISR, // User Defined trap 11 + USER12_ISR, // User Defined trap 12 + +// Group 1 PIE Vectors: + #if (G11PL != 0) + SEQ1INT_ISR, // ADC + #else + INT_NOTUSED_ISR, + #endif + + #if (G12PL != 0) + SEQ2INT_ISR, // ADC + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + + #if (G14PL != 0) + XINT1_ISR, // External + #else + INT_NOTUSED_ISR, + #endif + + #if (G15PL != 0) + XINT2_ISR, // External + #else + INT_NOTUSED_ISR, + #endif + + #if (G16PL != 0) + ADCINT_ISR, // ADC + #else + INT_NOTUSED_ISR, + #endif + + #if (G17PL != 0) + TINT0_ISR, // Timer 0 + #else + INT_NOTUSED_ISR, + #endif + + #if (G18PL != 0) + WAKEINT_ISR, // WD & Low Power + #else + INT_NOTUSED_ISR, + #endif + +// Group 2 PIE Vectors: + #if (G21PL != 0) + EPWM1_TZINT_ISR, // ePWM1 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G22PL != 0) + EPWM2_TZINT_ISR, // ePWM2 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G23PL != 0) + EPWM3_TZINT_ISR, // ePWM3 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G24PL != 0) + EPWM4_TZINT_ISR, // ePWM4 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G25PL != 0) + EPWM5_TZINT_ISR, // ePWM5 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + #if (G26PL != 0) + EPWM6_TZINT_ISR, // ePWM6 Trip Zone + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 3 PIE Vectors: + #if (G31PL != 0) + EPWM1_INT_ISR, // ePWM1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G32PL != 0) + EPWM2_INT_ISR, // ePWM2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G33PL != 0) + EPWM3_INT_ISR, // ePWM3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G34PL != 0) + EPWM4_INT_ISR, // ePWM4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G35PL != 0) + EPWM5_INT_ISR, // ePWM5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G36PL != 0) + EPWM6_INT_ISR, // ePWM6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 4 PIE Vectors: + #if (G41PL != 0) + ECAP1_INT_ISR, // eCAP1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G42PL != 0) + ECAP2_INT_ISR, // eCAP2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G43PL != 0) + ECAP3_INT_ISR, // eCAP3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G44PL != 0) + ECAP4_INT_ISR, // eCAP4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G45PL != 0) + ECAP5_INT_ISR, // eCAP5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G46PL != 0) + ECAP6_INT_ISR, // eCAP6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 5 PIE Vectors: + #if (G51PL != 0) + EQEP1_INT_ISR, // eQEP1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G52PL != 0) + EQEP2_INT_ISR, // eQEP2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + +// Group 6 PIE Vectors: + #if (G61PL != 0) + SPIRXINTA_ISR, // SPI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G62PL != 0) + SPITXINTA_ISR, // SPI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G63PL != 0) + MRINTB_ISR, // McBSP-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G64PL != 0) + MXINTB_ISR, // McBSP-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G65PL != 0) + MRINTA_ISR, // McBSP-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G66PL != 0) + MXINTA_ISR, // McBSP-A + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 7 PIE Vectors: + #if (G71PL != 0) + DINTCH1_ISR, // DMA-Channel 1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G72PL != 0) + DINTCH2_ISR, // DMA-Channel 2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G73PL != 0) + DINTCH3_ISR, // DMA-Channel 3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G74PL != 0) + DINTCH4_ISR, // DMA-Channel 4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G75PL != 0) + DINTCH5_ISR, // DMA-Channel 5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G76PL != 0) + DINTCH6_ISR, // DMA-Channel 6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 8 PIE Vectors: + #if (G81PL != 0) + I2CINT1A_ISR, // I2C-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G82PL != 0) + I2CINT2A_ISR, // I2C-A + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + + #if (G85PL != 0) + SCIRXINTC_ISR, // SCI-C + #else + INT_NOTUSED_ISR, + #endif + + #if (G86PL != 0) + SCITXINTC_ISR, // SCI-C + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + rsvd_ISR, + +// Group 9 PIE Vectors: + #if (G91PL != 0) + SCIRXINTA_ISR, // SCI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G92PL != 0) + SCITXINTA_ISR, // SCI-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G93PL != 0) + SCIRXINTB_ISR, // SCI-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G94PL != 0) + SCITXINTB_ISR, // SCI-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G95PL != 0) + ECAN0INTA_ISR, // eCAN-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G96PL != 0) + ECAN1INTA_ISR, // eCAN-A + #else + INT_NOTUSED_ISR, + #endif + + #if (G97PL != 0) + ECAN0INTB_ISR, // eCAN-B + #else + INT_NOTUSED_ISR, + #endif + + #if (G98PL != 0) + ECAN1INTB_ISR, // eCAN-B + #else + INT_NOTUSED_ISR, + #endif + +// Group 10 PIE Vectors + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + +// Group 11 PIE Vectors + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + rsvd_ISR, + +// Group 12 PIE Vectors + #if (G121PL != 0) + XINT3_ISR, // External interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G122PL != 0) + XINT4_ISR, // External interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + #if (G123PL != 0) + XINT5_ISR, // External interrupt 5 + #else + INT_NOTUSED_ISR, + #endif + + #if (G124PL != 0) + XINT6_ISR, // External interrupt 6 + #else + INT_NOTUSED_ISR, + #endif + + #if (G125PL != 0) + XINT7_ISR, // External interrupt 7 + #else + INT_NOTUSED_ISR, + #endif + + rsvd_ISR, + + #if (G127PL != 0) + LVF_ISR, // Latched overflow flag + #else + INT_NOTUSED_ISR, + #endif + + #if (G128PL != 0) + LUF_ISR, // Latched underflow flag + #else + INT_NOTUSED_ISR, + #endif +}; + +//--------------------------------------------------------------------------- +// InitPieVectTable: +//--------------------------------------------------------------------------- +// This function initializes the PIE vector table to a known state. +// This function must be executed after boot time. +// + +void InitPieVectTable(void) +{ + int16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + EALLOW; + for(i=0; i < 128; i++) { + *Dest++ = *Source++; + } + EDIS; +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c b/Source/External/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c new file mode 100644 index 0000000..7d9ea10 --- /dev/null +++ b/Source/External/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c @@ -0,0 +1,415 @@ +// TI File $Revision: /main/7 $ +// Checkin $Date: September 20, 2007 13:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.c +// +// TITLE: DSP2833x Device System Control Initialization & Support Functions. +// +// DESCRIPTION: +// +// Example initialization of system resources. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +//#include "RS485.h" +//#include "message.h" + +// Functions that will be run from RAM need to be assigned to +// a different section. This section will then be mapped to a load and +// run address using the linker cmd file. + +#pragma CODE_SECTION(InitFlash, "ramfuncs"); + +//--------------------------------------------------------------------------- +// InitSysCtrl: +//--------------------------------------------------------------------------- +// This function initializes the System Control registers to a known state. +// - Disables the watchdog +// - Set the PLLCR for proper SYSCLKOUT frequency +// - Set the pre-scaler for the high and low frequency peripheral clocks +// - Enable the clocks to the peripherals + +long SYSCLKOUT, LSPCLK, HSPCLK; + +void InitSysCtrl(void) +{ + + // Disable the watchdog + DisableDog(); + + // Initialize the PLL control: PLLCR and DIVSEL + // DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h + InitPll(DSP28_PLLCR,DSP28_DIVSEL); + + // Initialize the peripheral clocks + InitPeripheralClocks(); +} + + +//--------------------------------------------------------------------------- +// Example: InitFlash: +//--------------------------------------------------------------------------- +// This function initializes the Flash Control registers + +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results + +void InitFlash(void) +{ + EALLOW; + //Enable Flash Pipeline mode to improve performance + //of code executed from Flash. + FlashRegs.FOPT.bit.ENPIPE = 1; + + // CAUTION + //Minimum waitstates required for the flash operating + //at a given CPU rate must be characterized by TI. + //Refer to the datasheet for the latest information. +#if CPU_FRQ_150MHZ + //Set the Paged Waitstate for the Flash + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5; + + //Set the Random Waitstate for the Flash + FlashRegs.FBANKWAIT.bit.RANDWAIT = 5; + + //Set the Waitstate for the OTP + FlashRegs.FOTPWAIT.bit.OTPWAIT = 8; +#endif + +#if CPU_FRQ_100MHZ + //Set the Paged Waitstate for the Flash + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3; + + //Set the Random Waitstate for the Flash + FlashRegs.FBANKWAIT.bit.RANDWAIT = 3; + + //Set the Waitstate for the OTP + FlashRegs.FOTPWAIT.bit.OTPWAIT = 5; +#endif + // CAUTION + //ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED + FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF; + FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; + EDIS; + + //Force a pipeline flush to ensure that the write to + //the last register configured occurs before returning. + + asm(" RPT #7 || NOP"); +} + + +//--------------------------------------------------------------------------- +// Example: ServiceDog: +//--------------------------------------------------------------------------- +// This function resets the watchdog timer. +// Enable this function for using ServiceDog in the application + +void ServiceDog(void) +{ + if(SysCtrlRegs.PLLCR.bit.DIV == DSP28_PLLCR) + if(SysCtrlRegs.PLLSTS.bit.DIVSEL == DSP28_DIVSEL) + { + EALLOW; + SysCtrlRegs.WDKEY = 0x0055; + SysCtrlRegs.WDKEY = 0x00AA; + EDIS; + return; +} } + + +//--------------------------------------------------------------------------- +// Example: DisableDog: +//--------------------------------------------------------------------------- +// This function disables the watchdog timer. + +void DisableDog(void) +{ + EALLOW; + SysCtrlRegs.WDCR= 0x0068; + EDIS; +} + +//--------------------------------------------------------------------------- +// Example: InitPll: +//--------------------------------------------------------------------------- +// This function initializes the PLLCR register. + +void InitPll(Uint16 divval, Uint16 divsel) +{ + long clkVal; + + // Make sure the PLL is not running in limp mode + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0) + { + // Missing external clock has been detected + // Replace this line with a call to an appropriate + // SystemShutdown(); function. + asm(" ESTOP0"); + } + + // DIVSEL MUST be 0 before PLLCR can be changed from + // 0x0000. It is set to 0 by an external reset XRSn + // This puts us in 1/4 + if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 0; + EDIS; + } + + // Change the PLLCR +// if (SysCtrlRegs.PLLCR.bit.DIV != val) + { + + EALLOW; + // Before setting PLLCR turn off missing clock detect logic + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1; + SysCtrlRegs.PLLCR.bit.DIV = divval; + EDIS; + + clkVal = (divval)?divval:1; + clkVal = XCLKIN * clkVal; + + // Optional: Wait for PLL to lock. + // During this time the CPU will switch to OSCCLK/2 until + // the PLL is stable. Once the PLL is stable the CPU will + // switch to the new PLL value. + // + // This time-to-lock is monitored by a PLL lock counter. + // + // Code is not required to sit and wait for the PLL to lock. + // However, if the code does anything that is timing critical, + // and requires the correct clock be locked, then it is best to + // wait until this switching has completed. + + // Wait for the PLL lock bit to be set. + + // The watchdog should be disabled before this loop, or fed within + // the loop via ServiceDog(). + + // Uncomment to disable the watchdog + DisableDog(); + + while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1) + { + // Uncomment to service the watchdog + // ServiceDog(); + } + + EALLOW; + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0; + EDIS; + } + + // If switching to 1/2 + if((divsel == 1)||(divsel == 2)) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel; + EDIS; + } + + if(divsel == 0) clkVal /= 4; + if(divsel == 1) clkVal /= 4; + if(divsel == 2) clkVal /= 2; + + // If switching to 1/1 + // * First go to 1/2 and let the power settle + // The time required will depend on the system, this is only an example + // * Then switch to 1/1 + + if((divval == 0) && (divsel == 3)) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 2; + DELAY_US(50L); +// pause_us(50L); + SysCtrlRegs.PLLSTS.bit.DIVSEL = 3; + EDIS; + } + + SYSCLKOUT = clkVal; +} + +//-------------------------------------------------------------------------- +// Example: InitPeripheralClocks: +//--------------------------------------------------------------------------- +// This function initializes the clocks to the peripheral modules. +// First the high and low clock prescalers are set +// Second the clocks are enabled to each peripheral. +// To reduce power, leave clocks to unused peripherals disabled +// +// Note: If a peripherals clock is not enabled then you cannot +// read or write to the registers for that peripheral + +void InitPeripheralClocks(void) +{ + long Val; + + EALLOW; + +// HISPCP/LOSPCP prescale register settings, normally it will be set to default values + +#if CLKMULT == 0 + SysCtrlRegs.HISPCP.all = 0x0000; +#endif +#if CLKMULT == 1 + SysCtrlRegs.HISPCP.all = 0x0000; +#endif +#if CLKMULT == 2 + SysCtrlRegs.HISPCP.all = 0x0001; +#endif +#if CLKMULT == 3 + SysCtrlRegs.HISPCP.all = 0x0002; +#endif +#if CLKMULT == 4 + SysCtrlRegs.HISPCP.all = 0x0002; +#endif +#if CLKMULT == 5 + SysCtrlRegs.HISPCP.all = 0x0003; +#endif + + SysCtrlRegs.LOSPCP.all = 0x0000; + + Val = (SysCtrlRegs.HISPCP.all)? + SysCtrlRegs.HISPCP.all*2 : 1; + Val = SYSCLKOUT / Val; + + HSPCLK = Val; + + Val = (SysCtrlRegs.LOSPCP.all)? + SysCtrlRegs.LOSPCP.all*2 : 1; + Val = SYSCLKOUT / Val; + LSPCLK = Val; + +// XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT + // XTIMCLK = SYSCLKOUT/2 + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + // XCLKOUT = XTIMCLK/2 + XintfRegs.XINTCNF2.bit.CLKMODE = 1; + // Enable XCLKOUT + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + +// Peripheral clock enables set for the selected peripherals. +// If you are not using a peripheral leave the clock off +// to save on power. +// +// Note: not all peripherals are available on all 2833x derivates. +// Refer to the datasheet for your particular device. +// +// This function is not written to be an example of efficient code. + + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC + + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from TI reserved + // OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the + // Boot ROM. If the boot ROM code is bypassed during the debug process, the + // following function MUST be called for the ADC to function according + // to specification. The clocks to the ADC MUST be enabled before calling this + // function. + // See the device data manual and/or the ADC Reference + // Manual for more information. + + ADC_cal(); + + + SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C + SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A + SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B + SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C + SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A + SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A + SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B + SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A + SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B + + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM + SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1 + SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2 + SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3 + SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4 + SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5 + SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6 + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM + + SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3 + SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4 + SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5 + SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6 + SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1 + SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2 + SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1 + SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2 + + SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2 + + SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock + SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK + SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock + + EDIS; +} + +//--------------------------------------------------------------------------- +// Example: CsmUnlock: +//--------------------------------------------------------------------------- +// This function unlocks the CSM. User must replace 0xFFFF's with current +// password for the DSP. Returns 1 if unlock is successful. + +#define STATUS_FAIL 0 +#define STATUS_SUCCESS 1 + +Uint16 CsmUnlock() +{ + volatile Uint16 temp; + + // Load the key registers with the current password. The 0xFFFF's are dummy + // passwords. User should replace them with the correct password for the DSP. + + EALLOW; + CsmRegs.KEY0 = 0xFFFF; + CsmRegs.KEY1 = 0xFFFF; + CsmRegs.KEY2 = 0xFFFF; + CsmRegs.KEY3 = 0xFFFF; + CsmRegs.KEY4 = 0xFFFF; + CsmRegs.KEY5 = 0xFFFF; + CsmRegs.KEY6 = 0xFFFF; + CsmRegs.KEY7 = 0xFFFF; + EDIS; + + // Perform a dummy read of the password locations + // if they match the key values, the CSM will unlock + + temp = CsmPwl.PSWD0; + temp = CsmPwl.PSWD1; + temp = CsmPwl.PSWD2; + temp = CsmPwl.PSWD3; + temp = CsmPwl.PSWD4; + temp = CsmPwl.PSWD5; + temp = CsmPwl.PSWD6; + temp = CsmPwl.PSWD7; + + // If the CSM unlocked, return succes, otherwise return + // failure. + if (CsmRegs.CSMSCR.bit.SECURE == 0) return STATUS_SUCCESS; + else return STATUS_FAIL; + +} + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/source/DSP2833x_Xintf.c b/Source/External/v120/DSP2833x_common/source/DSP2833x_Xintf.c new file mode 100644 index 0000000..0d3619a --- /dev/null +++ b/Source/External/v120/DSP2833x_common/source/DSP2833x_Xintf.c @@ -0,0 +1,243 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: August 16, 2007 11:06:26 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.c +// +// TITLE: DSP2833x Device External Interface Init & Support Functions. +// +// DESCRIPTION: +// +// Example initialization function for the external interface (XINTF). +// This example configures the XINTF to its default state. For an +// example of how this function being used refer to the +// examples/run_from_xintf project. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +//--------------------------------------------------------------------------- +// InitXINTF: +//--------------------------------------------------------------------------- +// This function initializes the External Interface the default reset state. +// +// Do not modify the timings of the XINTF while running from the XINTF. Doing +// so can yield unpredictable results + + +void InitXintf(void) +{ + // This shows how to write to the XINTF registers. The + // values used here are the default state after reset. + // Different hardware will require a different configuration. + + // For an example of an XINTF configuration used with the + // F28335 eZdsp, refer to the examples/run_from_xintf project. + + // Any changes to XINTF timing should only be made by code + // running outside of the XINTF. + + // All Zones--------------------------------- + // Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + // No write buffering + XintfRegs.XINTCNF2.bit.WRBUFF = 0; + // XCLKOUT is enabled + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + // XCLKOUT = XTIMCLK/2 + XintfRegs.XINTCNF2.bit.CLKMODE = 1; + + + // Zone 0------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING0.bit.XWRLEAD = 3; + XintfRegs.XTIMING0.bit.XWRACTIVE = 7; + XintfRegs.XTIMING0.bit.XWRTRAIL = 3; + // Zone read timing + XintfRegs.XTIMING0.bit.XRDLEAD = 3; + XintfRegs.XTIMING0.bit.XRDACTIVE = 7; + XintfRegs.XTIMING0.bit.XRDTRAIL = 3; + + // double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING0.bit.X2TIMING = 1; + + // Zone will sample XREADY signal + XintfRegs.XTIMING0.bit.USEREADY = 1; + XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous + + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + XintfRegs.XTIMING0.bit.XSIZE = 3; + + // Zone 6------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING6.bit.XWRLEAD = 3; + XintfRegs.XTIMING6.bit.XWRACTIVE = 7; + XintfRegs.XTIMING6.bit.XWRTRAIL = 3; + // Zone read timing + XintfRegs.XTIMING6.bit.XRDLEAD = 3; + XintfRegs.XTIMING6.bit.XRDACTIVE = 7; + XintfRegs.XTIMING6.bit.XRDTRAIL = 3; + + // double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING6.bit.X2TIMING = 1; + + // Zone will sample XREADY signal + XintfRegs.XTIMING6.bit.USEREADY = 1; + XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous + + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + XintfRegs.XTIMING6.bit.XSIZE = 3; + + + // Zone 7------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING7.bit.XWRLEAD = 3; + XintfRegs.XTIMING7.bit.XWRACTIVE = 7; + XintfRegs.XTIMING7.bit.XWRTRAIL = 3; + // Zone read timing + XintfRegs.XTIMING7.bit.XRDLEAD = 3; + XintfRegs.XTIMING7.bit.XRDACTIVE = 7; + XintfRegs.XTIMING7.bit.XRDTRAIL = 3; + + // double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING7.bit.X2TIMING = 1; + + // Zone will sample XREADY signal + XintfRegs.XTIMING7.bit.USEREADY = 1; + XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous + + // Size must be either: + // 0,1 = x32 or + // 1,1 = x16 other values are reserved + XintfRegs.XTIMING7.bit.XSIZE = 3; + + // Bank switching + // Assume Zone 7 is slow, so add additional BCYC cycles + // when ever switching from Zone 7 to another Zone. + // This will help avoid bus contention. + XintfRegs.XBANK.bit.BANK = 7; + XintfRegs.XBANK.bit.BCYC = 7; + EDIS; + //Force a pipeline flush to ensure that the write to + //the last register configured occurs before returning. + + InitXintf16Gpio(); +// InitXintf32Gpio(); + + asm(" RPT #7 || NOP"); + +} + +void InitXintf32Gpio() +{ + EALLOW; + GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31 + GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30 + GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29 + GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28 + GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27 + GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26 + GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25 + GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24 + GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23 + GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22 + GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21 + GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20 + GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19 + GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18 + GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17 + GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16 + + GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input + GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input + + + InitXintf16Gpio(); +} + +void InitXintf16Gpio() +{ + EALLOW; + GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15 + GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14 + GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13 + GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12 + GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11 + GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10 + GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19 + GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0 + + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n + GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1 + GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2 + GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3 + GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4 + GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5 + GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6 + GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7 + + GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8 + GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9 + GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10 + GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11 + GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12 + GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13 + GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14 + GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15 + + GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16 +// GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17 +// GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18 +// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19 + +// GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY + GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0 + +// GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0 + GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7 +// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6 + EDIS; +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_common/source/DSP2833x_usDelay.asm b/Source/External/v120/DSP2833x_common/source/DSP2833x_usDelay.asm new file mode 100644 index 0000000..d3878b4 --- /dev/null +++ b/Source/External/v120/DSP2833x_common/source/DSP2833x_usDelay.asm @@ -0,0 +1,76 @@ +;// TI File $Revision: /main/4 $ +;// Checkin $Date: July 30, 2007 10:28:57 $ +;//########################################################################### +;// +;// FILE: DSP2833x_usDelay.asm +;// +;// TITLE: Simple delay function +;// +;// DESCRIPTION: +;// +;// This is a simple delay function that can be used to insert a specified +;// delay into code. +;// +;// This function is only accurate if executed from internal zero-waitstate +;// SARAM. If it is executed from waitstate memory then the delay will be +;// longer then specified. +;// +;// To use this function: +;// +;// 1 - update the CPU clock speed in the DSP2833x_Examples.h +;// file. For example: +;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed +;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed +;// +;// 2 - Call this function by using the DELAY_US(A) macro +;// that is defined in the DSP2833x_Examples.h file. This macro +;// will convert the number of microseconds specified +;// into a loop count for use with this function. +;// This count will be based on the CPU frequency you specify. +;// +;// 3 - For the most accurate delay +;// - Execute this function in 0 waitstate RAM. +;// - Disable interrupts before calling the function +;// If you do not disable interrupts, then think of +;// this as an "at least" delay function as the actual +;// delay may be longer. +;// +;// The C assembly call from the DELAY_US(time) macro will +;// look as follows: +;// +;// extern void Delay(long LoopCount); +;// +;// MOV AL,#LowLoopCount +;// MOV AH,#HighLoopCount +;// LCR _Delay +;// +;// Or as follows (if count is less then 16-bits): +;// +;// MOV ACC,#LoopCount +;// LCR _Delay +;// +;// +;//########################################################################### +;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +;// $Release Date: August 1, 2008 $ +;//########################################################################### + + .def _DSP28x_usDelay + .sect ".text" + + .global __DSP28x_usDelay +_DSP28x_usDelay: + SUB ACC,#1 + BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0 + LRETR + +;There is a 9/10 cycle overhead and each loop +;takes five cycles. The LoopCount is given by +;the following formula: +; DELAY_CPU_CYCLES = 9 + 5*LoopCount +; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 +; The macro DELAY_US(A) performs this calculation for you +; +;//=========================================================================== +;// End of file. +;//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/cmd/DSP2833x_Headers_BIOS.cmd b/Source/External/v120/DSP2833x_headers/cmd/DSP2833x_Headers_BIOS.cmd new file mode 100644 index 0000000..fe2d6c5 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/cmd/DSP2833x_Headers_BIOS.cmd @@ -0,0 +1,183 @@ +/* +// TI File $Revision: /main/9 $ +// Checkin $Date: August 8, 2008 11:09:25 $ +//########################################################################### +// +// FILE: DSP2833x_Headers_BIOS.cmd +// +// TITLE: DSP2833x Peripheral registers linker command file +// +// DESCRIPTION: +// +// This file is for use in BIOS applications. +// +// Linker command file to place the peripheral structures +// used within the DSP2833x headerfiles into the correct memory +// mapped locations. +// +// This version of the file does not include the PieVectorTable structure. +// For non-BIOS applications, please use the DSP2833x_Headers_nonBIOS.cmd +// file which includes the PieVectorTable structure. +// +//##################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//##################################################################### +*/ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ + FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ + CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ + + ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ + + XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + + DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ + + MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ + + ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ + ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ + ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ + ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ + ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ + + ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ + ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ + ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ + ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ + ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ + + EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */ + + ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ + + GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ + GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ + GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ + + SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ + SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ + SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ + XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ + + ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ + + SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ + + SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ + + I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ + + CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ + + PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ +} + + +SECTIONS +{ +/*** The PIE Vector table is called PIEVECT by DSP/BIOS ***/ + PieVectTableFile : > PIEVECT, PAGE = 1, TYPE = DSECT + +/*** Peripheral Frame 0 Register Structures ***/ + DevEmuRegsFile : > DEV_EMU, PAGE = 1 + FlashRegsFile : > FLASH_REGS, PAGE = 1 + CsmRegsFile : > CSM, PAGE = 1 + AdcMirrorFile : > ADC_MIRROR, PAGE = 1 + XintfRegsFile : > XINTF, PAGE = 1 + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + DmaRegsFile : > DMA, PAGE = 1 + +/*** Peripheral Frame 3 Register Structures ***/ + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + +/*** Peripheral Frame 1 Register Structures ***/ + ECanaRegsFile : > ECANA, PAGE = 1 + ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 + ECanaMboxesFile : > ECANA_MBOX PAGE = 1 + ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 + ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 + + ECanbRegsFile : > ECANB, PAGE = 1 + ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 + ECanbMboxesFile : > ECANB_MBOX PAGE = 1 + ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 + ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 + + EPwm1RegsFile : > EPWM1 PAGE = 1 + EPwm2RegsFile : > EPWM2 PAGE = 1 + EPwm3RegsFile : > EPWM3 PAGE = 1 + EPwm4RegsFile : > EPWM4 PAGE = 1 + EPwm5RegsFile : > EPWM5 PAGE = 1 + EPwm6RegsFile : > EPWM6 PAGE = 1 + + ECap1RegsFile : > ECAP1 PAGE = 1 + ECap2RegsFile : > ECAP2 PAGE = 1 + ECap3RegsFile : > ECAP3 PAGE = 1 + ECap4RegsFile : > ECAP4 PAGE = 1 + ECap5RegsFile : > ECAP5 PAGE = 1 + ECap6RegsFile : > ECAP6 PAGE = 1 + + EQep1RegsFile : > EQEP1 PAGE = 1 + EQep2RegsFile : > EQEP2 PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 + GpioDataRegsFile : > GPIODAT PAGE = 1 + GpioIntRegsFile : > GPIOINT PAGE = 1 + +/*** Peripheral Frame 2 Register Structures ***/ + SysCtrlRegsFile : > SYSTEM, PAGE = 1 + SpiaRegsFile : > SPIA, PAGE = 1 + SciaRegsFile : > SCIA, PAGE = 1 + XIntruptRegsFile : > XINTRUPT, PAGE = 1 + AdcRegsFile : > ADC, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + +/*** Code Security Module Register Structures ***/ + CsmPwlFile : > CSM_PWL, PAGE = 1 + +/*** Device Part ID Register Structures ***/ + PartIdRegsFile : > PARTID, PAGE = 1 + +} + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ \ No newline at end of file diff --git a/Source/External/v120/DSP2833x_headers/cmd/DSP2833x_Headers_nonBIOS.cmd b/Source/External/v120/DSP2833x_headers/cmd/DSP2833x_Headers_nonBIOS.cmd new file mode 100644 index 0000000..9da1026 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/cmd/DSP2833x_Headers_nonBIOS.cmd @@ -0,0 +1,183 @@ +/* +// TI File $Revision: /main/8 $ +// Checkin $Date: June 2, 2008 11:12:24 $ +//########################################################################### +// +// FILE: DSP2833x_Headers_nonBIOS.cmd +// +// TITLE: DSP2833x Peripheral registers linker command file +// +// DESCRIPTION: +// +// This file is for use in Non-BIOS applications. +// +// Linker command file to place the peripheral structures +// used within the DSP2833x headerfiles into the correct memory +// mapped locations. +// +// This version of the file includes the PieVectorTable structure. +// For BIOS applications, please use the DSP2833x_Headers_BIOS.cmd file +// which does not include the PieVectorTable structure. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ + FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ + CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ + + ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ + + XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */ + + DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ + + MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ + + ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ + ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ + ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ + ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ + ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ + + ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ + ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ + ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ + ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ + ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ + + EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */ + + ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ + + GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ + GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ + GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ + + SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ + SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ + SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ + XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ + + ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ + + SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ + + SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ + + I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ + + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ + + PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ +} + + +SECTIONS +{ + PieVectTableFile : > PIE_VECT, PAGE = 1 + +/*** Peripheral Frame 0 Register Structures ***/ + DevEmuRegsFile : > DEV_EMU, PAGE = 1 + FlashRegsFile : > FLASH_REGS, PAGE = 1 + CsmRegsFile : > CSM, PAGE = 1 + AdcMirrorFile : > ADC_MIRROR, PAGE = 1 + XintfRegsFile : > XINTF, PAGE = 1 + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + DmaRegsFile : > DMA, PAGE = 1 + +/*** Peripheral Frame 3 Register Structures ***/ + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + +/*** Peripheral Frame 1 Register Structures ***/ + ECanaRegsFile : > ECANA, PAGE = 1 + ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 + ECanaMboxesFile : > ECANA_MBOX PAGE = 1 + ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 + ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 + + ECanbRegsFile : > ECANB, PAGE = 1 + ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 + ECanbMboxesFile : > ECANB_MBOX PAGE = 1 + ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 + ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 + + EPwm1RegsFile : > EPWM1 PAGE = 1 + EPwm2RegsFile : > EPWM2 PAGE = 1 + EPwm3RegsFile : > EPWM3 PAGE = 1 + EPwm4RegsFile : > EPWM4 PAGE = 1 + EPwm5RegsFile : > EPWM5 PAGE = 1 + EPwm6RegsFile : > EPWM6 PAGE = 1 + + ECap1RegsFile : > ECAP1 PAGE = 1 + ECap2RegsFile : > ECAP2 PAGE = 1 + ECap3RegsFile : > ECAP3 PAGE = 1 + ECap4RegsFile : > ECAP4 PAGE = 1 + ECap5RegsFile : > ECAP5 PAGE = 1 + ECap6RegsFile : > ECAP6 PAGE = 1 + + EQep1RegsFile : > EQEP1 PAGE = 1 + EQep2RegsFile : > EQEP2 PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 + GpioDataRegsFile : > GPIODAT PAGE = 1 + GpioIntRegsFile : > GPIOINT PAGE = 1 + +/*** Peripheral Frame 2 Register Structures ***/ + SysCtrlRegsFile : > SYSTEM, PAGE = 1 + SpiaRegsFile : > SPIA, PAGE = 1 + SciaRegsFile : > SCIA, PAGE = 1 + XIntruptRegsFile : > XINTRUPT, PAGE = 1 + AdcRegsFile : > ADC, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + +/*** Code Security Module Register Structures ***/ + CsmPwlFile : > CSM_PWL, PAGE = 1 + +/*** Device Part ID Register Structures ***/ + PartIdRegsFile : > PARTID, PAGE = 1 + +} + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_Adc.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_Adc.h new file mode 100644 index 0000000..5c8467a --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_Adc.h @@ -0,0 +1,264 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// ADC Individual Register Bit Definitions: + +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; // ADC Control 1 + union ADCTRL2_REG ADCTRL2; // ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; // Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; // Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; // Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; // Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; // Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; // Autosequence status register + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; // ADC Control 3 + union ADCST_REG ADCST; // ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; // Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; // Offset Trim Register +}; + + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +//--------------------------------------------------------------------------- +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif // end of DSP2833x_ADC_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_CpuTimers.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_CpuTimers.h new file mode 100644 index 0000000..3475801 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_CpuTimers.h @@ -0,0 +1,190 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// CPU Timer Register Bit Definitions: +// +// +// TCR: Control register bit definitions: +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// TPR: Pre-scale low bit definitions: +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// TPRH: Pre-scale high bit definitions: +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// TIM, TIMH: Timer register definitions: +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// PRD, PRDH: Period register definitions: +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +//--------------------------------------------------------------------------- +// CPU Timer Register File: +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +//--------------------------------------------------------------------------- +// CPU Timer Support Variables: +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +//--------------------------------------------------------------------------- +// Function prototypes and external definitions: +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +//--------------------------------------------------------------------------- +// Usefull Timer Operations: +// +// Start Timer: +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// Stop Timer: +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// Reload Timer With period Value: +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// Read 32-Bit Timer Value: +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// Read 32-Bit Period Value: +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. + +// Start Timer: +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + + +// Stop Timer: +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// Reload Timer With period Value: +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// Read 32-Bit Timer Value: +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// Read 32-Bit Period Value: +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_DMA.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_DMA.h new file mode 100644 index 0000000..e8b0d59 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_DMA.h @@ -0,0 +1,295 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Channel MODE register bit definitions: +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single burst transfer + // 1 first interrupt triggers burst, continue until transfer count is zero + Uint16 CONTINUOUS:1; // 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap counter + // 1 sync signal controls destination wrap counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +//---------------------------------------------------- +// Channel CONTROL register bit definitions: +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +//---------------------------------------------------- +// DMACTRL register bit definitions: +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +//---------------------------------------------------- +// DEBUGCTRL register bit definitions: +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + + +//---------------------------------------------------- +// PRIORITYCTRL1 register bit definitions: +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + + +//---------------------------------------------------- +// PRIORITYSTAT register bit definitions: +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active and interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// Burst Size +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// Burst Count +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + + + +//---------------------------------------------------- +// DMA Channel Registers: +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + int16 SRC_BURST_STEP; // Source Burst Step Register + int16 DST_BURST_STEP; // Destination Burst Step Register + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + int16 SRC_TRANSFER_STEP; // Source Transfer Step Register + int16 DST_TRANSFER_STEP; // Destination Transfer Step Register + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register + Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register + int16 DST_WRAP_STEP; // Destination Wrap Step Register + + Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register + Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register + Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register + Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register + + Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register + Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register + Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register + Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register +}; + +//---------------------------------------------------- +// DMA Registers: +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + + +//--------------------------------------------------------------------------- +// External References & Function Declarations: +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_DevEmu.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_DevEmu.h new file mode 100644 index 0000000..3a765c6 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_DevEmu.h @@ -0,0 +1,97 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: June 2, 2008 11:12:30 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// Device Emulation Register Bit Definitions: +// +// Device Configuration Register Bit Definitions +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 MONPRIV:1; // 20 MONPRIV enable bit + Uint16 rsvd5:1; // 21 reserved + Uint16 EMU0SEL:2; // 23,22 EMU0 Mux select + Uint16 EMU1SEL:2; // 25,24 EMU1 Mux select + Uint16 MCBSPCON:1; // 26 McBSP-B to EMU0/EMU1 pins control + Uint16 rsvd6:5; // 31:27 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// CLASSID +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// PARTID +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + + + +//--------------------------------------------------------------------------- +// Device Emulation Register References & Function Declarations: +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_Device.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_Device.h new file mode 100644 index 0000000..0cf9a3b --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_Device.h @@ -0,0 +1,368 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +#define TARGET 1 +//--------------------------------------------------------------------------- +// User To Select Target Device: + +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28332 0 // Selects '28332/'28232 + + +//--------------------------------------------------------------------------- +// Common CPU Definitions: +// + +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + + + +//--------------------------------------------------------------------------- +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// + +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +typedef union +{ + struct + { + unsigned int bit0: 1; + unsigned int bit1: 1; + unsigned int bit2: 1; + unsigned int bit3: 1; + unsigned int bit4: 1; + unsigned int bit5: 1; + unsigned int bit6: 1; + unsigned int bit7: 1; + + } bit; + + struct + { + unsigned int quad_0 :4; + unsigned int quad_1 :4; + + } qua; + + unsigned short all; + +} BAITE; + +typedef union +{ + struct + { + unsigned int bit0: 1; + unsigned int bit1: 1; + unsigned int bit2: 1; + unsigned int bit3: 1; + unsigned int bit4: 1; + unsigned int bit5: 1; + unsigned int bit6: 1; + unsigned int bit7: 1; + unsigned int bit8: 1; + unsigned int bit9: 1; + unsigned int bitA: 1; + unsigned int bitB: 1; + unsigned int bitC: 1; + unsigned int bitD: 1; + unsigned int bitE: 1; + unsigned int bitF: 1; + + } bit; + + struct + { + unsigned int quad_0 :4; + unsigned int quad_1 :4; + unsigned int quad_2 :4; + unsigned int quad_3 :4; + + } qua; + + struct + { + unsigned int byte_0 :8; + unsigned int byte_1 :8; + + } byt; + + int all; + +} WORDE; + +typedef union +{ + struct + { + unsigned int bit00: 1; + unsigned int bit01: 1; + unsigned int bit02: 1; + unsigned int bit03: 1; + unsigned int bit04: 1; + unsigned int bit05: 1; + unsigned int bit06: 1; + unsigned int bit07: 1; + unsigned int bit08: 1; + unsigned int bit09: 1; + unsigned int bit0A: 1; + unsigned int bit0B: 1; + unsigned int bit0C: 1; + unsigned int bit0D: 1; + unsigned int bit0E: 1; + unsigned int bit0F: 1; + unsigned int bit10: 1; + unsigned int bit11: 1; + unsigned int bit12: 1; + unsigned int bit13: 1; + unsigned int bit14: 1; + unsigned int bit15: 1; + unsigned int bit16: 1; + unsigned int bit17: 1; + unsigned int bit18: 1; + unsigned int bit19: 1; + unsigned int bit1A: 1; + unsigned int bit1B: 1; + unsigned int bit1C: 1; + unsigned int bit1D: 1; + unsigned int bit1E: 1; + unsigned int bit1F: 1; + + } bit; + + struct + { + unsigned int quad_0 :4; + unsigned int quad_1 :4; + unsigned int quad_2 :4; + unsigned int quad_3 :4; + unsigned int quad_4 :4; + unsigned int quad_5 :4; + unsigned int quad_6 :4; + unsigned int quad_7 :4; + + } qua; + + struct + { + unsigned int byte_0 :8; + unsigned int byte_1 :8; + unsigned int byte_2 :8; + unsigned int byte_3 :8; + + } byt; + + struct + { + unsigned int word_0 :16; + unsigned int word_1 :16; + + } wrd; + + unsigned long all; + +} LONGE; + +#define XCLKIN 30000000 // external oscillator frequency +extern long SYSCLKOUT, LSPCLK, HSPCLK; + +#define CLKMULT 2L // 1 to 5 + +#define LOWORD(l)((short int)( (long int)(l) &0xFFFF)) +#define HIWORD(l)((short int)(((long int)(l)>>16)&0xFFFF)) + +#define LOBYTE(w)((char)( (short int)(w) &0xFF)) +#define HIBYTE(w)((char)(((short int)(w)>>8)&0xFF)) + +#define BYTE3(l)((char)(((long int)(l)>>24)&0xFF)) +#define BYTE2(l)((char)(((long int)(l)>>16)&0xFF)) +#define BYTE1(l)((char)(((long int)(l)>> 8)&0xFF)) +#define BYTE0(l)((char)( (long int)(l) &0xFF)) + +//--------------------------------------------------------------------------- +// Include All Peripheral Header Files: +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_McBSP.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the + +#if DSP28_28335 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_ECan.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_ECan.h new file mode 100644 index 0000000..65988ca --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_ECan.h @@ -0,0 +1,1161 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +/* --------------------------------------------------- */ +/* eCAN Control & Status Registers */ +/* ----------------------------------------------------*/ + +/* eCAN Mailbox enable register (CANME) bit definitions */ +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +/* eCAN Mailbox direction register (CANMD) bit definitions */ +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx + +}; + +/* Allow access to the bit fields or entire register */ +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +/* eCAN Transmit Request Set register (CANTRS) bit definitions */ +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +/* eCAN Transmit Request Reset register (CANTRR) bit definitions */ +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +/* eCAN Transmit Acknowledge register (CANTA) bit definitions */ +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +/* eCAN Transmit Abort Acknowledge register (CANAA) bit definitions */ +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +/* eCAN Received Message Pending register (CANRMP) bit definitions */ +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +/* eCAN Received Message Lost register (CANRML) bit definitions */ +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +/* eCAN Remote Frame Pending register (CANRFP) bit definitions */ +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +/* eCAN Global Acceptance Mask register (CANGAM) bit definitions */ +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +/* Allow access to the bit fields or entire register */ +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + + +/* eCAN Master Control register (CANMC) bit definitions */ +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +/* eCAN Bit -timing configuration register (CANBTC) bit definitions */ +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +/* eCAN Error & Status register (CANES) bit definitions */ +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + + +/* eCAN Transmit Error Counter register (CANTEC) bit definitions */ +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +/* eCAN Receive Error Counter register (CANREC) bit definitions */ +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +/* eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions */ +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +/* eCAN Global Interrupt Mask register (CANGIM) bit definitions */ +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + + +/* eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions */ +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + + +/* eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions */ +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +/* eCAN Mailbox Interrupt Level register (CANMIL) bit definitions */ +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 + +}; + +/* Allow access to the bit fields or entire register */ +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + + +/* eCAN Overwrite Protection Control register (CANOPC) bit definitions */ +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + + +/* eCAN TX I/O Control Register (CANTIOC) bit definitions */ +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +/* eCAN RX I/O Control Register (CANRIOC) bit definitions */ +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + + +/* eCAN Time-out Control register (CANTOC) bit definitions */ +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + + +/* eCAN Time-out Status register (CANTOS) bit definitions */ +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +/**************************************/ +/* eCAN Control & Status register file */ +/**************************************/ + +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status + +}; + +/* --------------------------------------------------- */ +/* eCAN Mailbox Registers */ +/* ----------------------------------------------------*/ + +/* eCAN Message ID (MSGID) bit definitions */ +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 + +}; + +/* Allow access to the bit fields or entire register */ +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +/* eCAN Message Control Register (MSGCTRL) bit definitions */ +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +/* Allow access to the bit fields or entire register */ +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +/* eCAN Message Data Register low (MDR_L) word definitions */ +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +/* eCAN Message Data Register low (MDR_L) byte definitions */ +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + + +/* Allow access to the bit fields or entire register */ + +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + + + +/* eCAN Message Data Register high (MDR_H) word definitions */ +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +/* eCAN Message Data Register low (MDR_H) byte definitions */ +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +/* Allow access to the bit fields or entire register */ +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +/**************************************/ +/* eCAN Mailboxes */ +/**************************************/ + +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +/* eCAN Local Acceptance Mask (LAM) bit definitions */ +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +/* Allow access to the bit fields or entire register */ +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + + +/**************************************/ +/* eCAN Local Acceptance Masks */ +/**************************************/ + +/* eCAN LAM File */ +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +/* Mailbox MOTS File */ + +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +/* Mailbox MOTO File */ + +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + + +//--------------------------------------------------------------------------- +// eCAN External References & Function Declarations: +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_ECap.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_ECap.h new file mode 100644 index 0000000..b82bd7f --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_ECap.h @@ -0,0 +1,151 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Capture control register 1 bit definitions */ +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + + +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +//---------------------------------------------------- +// Capture control register 2 bit definitions */ +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + + +//---------------------------------------------------- +// ECAP interrupt enable register bit definitions */ +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +//---------------------------------------------------- +// ECAP interrupt flag register bit definitions */ +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + + +//---------------------------------------------------- + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + + + + +//--------------------------------------------------------------------------- +// GPI/O External References & Function Declarations: +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_EPwm.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_EPwm.h new file mode 100644 index 0000000..9195752 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_EPwm.h @@ -0,0 +1,423 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Time base control register bit definitions */ +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +//---------------------------------------------------- +// Time base status register bit definitions */ +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +//---------------------------------------------------- +// Compare control register bit definitions */ +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +//---------------------------------------------------- +// Action qualifier register bit definitions */ +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +//---------------------------------------------------- +// Action qualifier SW force register bit definitions */ +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +//---------------------------------------------------- +// Action qualifier continuous SW force register bit definitions */ +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + + +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +//---------------------------------------------------- +// Dead-band generator control register bit definitions +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone select register bit definitions +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone control register bit definitions */ +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone control register bit definitions */ +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + + +//---------------------------------------------------- +// Trip zone flag register bit definitions */ +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +//---------------------------------------------------- +// Trip zone flag clear register bit definitions */ +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +//---------------------------------------------------- +// Trip zone flag force register bit definitions */ +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +//---------------------------------------------------- +// Event trigger select register bit definitions */ +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + + +//---------------------------------------------------- +// Event trigger pre-scale register bit definitions */ +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +//---------------------------------------------------- +// Event trigger Flag register bit definitions */ +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + + +//---------------------------------------------------- +// Event trigger Clear register bit definitions */ +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +//---------------------------------------------------- +// Event trigger Force register bit definitions */ +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; +//---------------------------------------------------- +// PWM chopper control register bit definitions */ +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + + +struct TBPHS_HRPWM_REG { // bits description + Uint16 TBPHSHR; // 15:0 Extension register for HRPWM Phase (8 bits) + Uint16 TBPHS; // 31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + + +//--------------------------------------------------------------------------- +// External References & Function Declarations: +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_EQep.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_EQep.h new file mode 100644 index 0000000..c330165 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_EQep.h @@ -0,0 +1,242 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// Capture decoder control register bit definitions */ +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + + +//---------------------------------------------------- +// QEP control register bit definitions */ +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + + +//---------------------------------------------------- +// Quadrature capture control register bit definitions */ +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + + + +//---------------------------------------------------- +// Position compare control register bit definitions */ +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +//---------------------------------------------------- +// QEP interrupt control register bit definitions */ +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + + +//---------------------------------------------------- +// QEP interrupt status register bit definitions */ +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +//---------------------------------------------------- +// QEP interrupt force register bit definitions */ +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +//---------------------------------------------------- +// QEP status register bit definitions */ +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +//---------------------------------------------------- + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + + + + +//--------------------------------------------------------------------------- +// GPI/O External References & Function Declarations: +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_Gpio.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_Gpio.h new file mode 100644 index 0000000..5759c81 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_Gpio.h @@ -0,0 +1,391 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//---------------------------------------------------- +// GPIO A control register bit definitions */ +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +//---------------------------------------------------- +// GPIO B control register bit definitions */ +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +//---------------------------------------------------- +// GPIO A Qual/MUX select register bit definitions */ +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +//---------------------------------------------------- +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions */ +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + + + + +//---------------------------------------------------- +// GPIO Xint1/XINT2/XNMI select register bit definitions */ +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + union GPA1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + union GPA2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + union GPA1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15) + union GPA2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31) + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + union GPADAT_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31) + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + union GPB1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + union GPB2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + union GPBDAT_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63) + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + union GPCDAT_REG GPCPUD; // GPIO C Pull Up Disable Register (GPIO64 to 95) +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + union GPADAT_REG GPASET; // GPIO Data Set Register (GPIO0 to 31) + union GPADAT_REG GPACLEAR; // GPIO Data Clear Register (GPIO0 to 31) + union GPADAT_REG GPATOGGLE; // GPIO Data Toggle Register (GPIO0 to 31) + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + union GPBDAT_REG GPBSET; // GPIO Data Set Register (GPIO32 to 63) + union GPBDAT_REG GPBCLEAR; // GPIO Data Clear Register (GPIO32 to 63) + union GPBDAT_REG GPBTOGGLE; // GPIO Data Toggle Register (GPIO32 to 63) + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + union GPCDAT_REG GPCCLEAR; // GPIO Data Clear Register (GPIO64 to 95) + union GPCDAT_REG GPCTOGGLE; // GPIO Data Toggle Register (GPIO64 to 95) + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; // XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; // XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; // XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; // XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; // XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; // XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; // XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; // XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; // Low power modes GP I/O input select +}; + + +//--------------------------------------------------------------------------- +// GPI/O External References & Function Declarations: +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_I2c.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_I2c.h new file mode 100644 index 0000000..382c12d --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_I2c.h @@ -0,0 +1,193 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//---------------------------------------------------- +// I2C interrupt vector register bit definitions */ +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +//---------------------------------------------------- +// I2C interrupt mask register bit definitions */ +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +//---------------------------------------------------- +// I2C status register bit definitions */ +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + + +//---------------------------------------------------- +// I2C mode control register bit definitions */ +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +//---------------------------------------------------- +// I2C pre-scaler register bit definitions */ +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + + +//---------------------------------------------------- +// TX FIFO control register bit definitions */ +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved + +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +//---------------------------------------------------- +// RX FIFO control register bit definitions */ +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + + +//---------------------------------------------------- + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + Uint16 rsvd1; // reserved + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + + + + +//--------------------------------------------------------------------------- +// External References & Function Declarations: +// +extern volatile struct I2C_REGS I2caRegs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_Mcbsp.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_Mcbsp.h new file mode 100644 index 0000000..05e4af9 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_Mcbsp.h @@ -0,0 +1,715 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// McBSP Individual Register Bit Definitions: +// +// McBSP DRR2 register bit definitions: +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// McBSP DRR1 register bit definitions: +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// McBSP DXR2 register bit definitions: +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// McBSP DXR1 register bit definitions: +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// SPCR2 control register bit definitions: +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// SPCR1 control register bit definitions: +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 ABIS:1; // 6 ABIS mode select + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// RCR2 control register bit definitions: +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// RCR1 control register bit definitions: +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// XCR2 control register bit definitions: + +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// XCR1 control register bit definitions: +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// SRGR2 Sample rate generator control register bit definitions: +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// SRGR1 control register bit definitions: +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// MCR2 Multichannel control register bit definitions: +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// MCR1 Multichannel control register bit definitions: +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// RCERA control register bit definitions: +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// RCERB control register bit definitions: +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// XCERA control register bit definitions: +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// XCERB control register bit definitions: +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// PCR control register bit definitions: +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// RCERC control register bit definitions: +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// RCERD control register bit definitions: +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// XCERC control register bit definitions: +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// XCERD control register bit definitions: +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// RCERE control register bit definitions: +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// RCERF control register bit definitions: +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// XCERF control register bit definitions: +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// RCERG control register bit definitions: +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// XCERG control register bit definitions: +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// XCERH control register bit definitions: +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + + +// McBSP Interrupt enable register for RINT/XINT +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + + +//--------------------------------------------------------------------------- +// McBSP Register File: +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for RINT/XINT + Uint16 rsvd2; // reserved +}; + +//--------------------------------------------------------------------------- +// McBSP External References & Function Declarations: +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_PieCtrl.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_PieCtrl.h new file mode 100644 index 0000000..1ab6e9d --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_PieCtrl.h @@ -0,0 +1,153 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// PIE Control Register Bit Definitions: +// +// PIECTRL: Register bit definitions: +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// PIEIER: Register bit definitions: +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// PIEIFR: Register bit definitions: +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// PIEACK: Register bit definitions: +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +//--------------------------------------------------------------------------- +// PIE Control Register File: +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +//--------------------------------------------------------------------------- +// PIE Control Registers External References & Function Declarations: +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_PieVect.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_PieVect.h new file mode 100644 index 0000000..acddab7 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_PieVect.h @@ -0,0 +1,208 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// PIE Interrupt Vector Table Definition: +// +// Create a user type called PINT (pointer to interrupt): + +typedef interrupt void(*PINT)(void); + +// Define Vector Table: +struct PIE_VECT_TABLE { + +// Reset is never fetched from this table. +// It will always be fetched from 0x3FFFC0 in +// boot ROM + + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + +// Non-Peripheral Interrupts: + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + +// Group 1 PIE Peripheral Vectors: + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + +// Group 2 PIE Peripheral Vectors: + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + +// Group 3 PIE Peripheral Vectors: + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + +// Group 4 PIE Peripheral Vectors: + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + +// Group 5 PIE Peripheral Vectors: + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + +// Group 6 PIE Peripheral Vectors: + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + +// Group 7 PIE Peripheral Vectors: + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + +// Group 8 PIE Peripheral Vectors: + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + +// Group 9 PIE Peripheral Vectors: + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + +// Group 10 PIE Peripheral Vectors: + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + +// Group 11 PIE Peripheral Vectors: + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + +// Group 12 PIE Peripheral Vectors: + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +//--------------------------------------------------------------------------- +// PIE Interrupt Vector Table External References & Function Declarations: +// +extern struct PIE_VECT_TABLE PieVectTable; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_Sci.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_Sci.h new file mode 100644 index 0000000..7c17822 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_Sci.h @@ -0,0 +1,235 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// SCI Individual Register Bit Definitions + +//---------------------------------------------------------- +// SCICCR communication control register bit definitions: +// + +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +//------------------------------------------- +// SCICTL1 control register 1 bit definitions: +// + +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved + +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +//--------------------------------------------- +// SCICTL2 control register 2 bit definitions: +// + +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved + +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +//--------------------------------------------------- +// SCIRXST Receiver status register bit definitions: +// + +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag + +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +//---------------------------------------------------- +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions: +// + +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +//-------------------------------------------------- +// SCIPRI Priority control register bit definitions: +// +// + +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +//------------------------------------------------- +// SCI FIFO Transmit register bit definitions: +// +// + +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels + +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +//------------------------------------------------ +// SCI FIFO recieve register bit definitions: +// +// + +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow + +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// SCI FIFO control register bit definitions: +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +//--------------------------------------------------------------------------- +// SCI Register File: +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +//--------------------------------------------------------------------------- +// SCI External References & Function Declarations: +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_Spi.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_Spi.h new file mode 100644 index 0000000..1325c59 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_Spi.h @@ -0,0 +1,183 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SPI Individual Register Bit Definitions: +// +// SPI FIFO Transmit register bit definitions: +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +//-------------------------------------------- +// SPI FIFO recieve register bit definitions: +// +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow + +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +//-------------------------------------------- +// SPI FIFO control register bit definitions: +// +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +//--------------------------------------------- +// SPI configuration register bit definitions: +// +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +//------------------------------------------------- +// SPI operation control register bit definitions: +// +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +//-------------------------------------- +// SPI status register bit definitions: +// +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +//------------------------------------------------ +// SPI priority control register bit definitions: +// +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +//--------------------------------------------------------------------------- +// SPI Register File: +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +//--------------------------------------------------------------------------- +// SPI External References & Function Declarations: +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_SysCtrl.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_SysCtrl.h new file mode 100644 index 0000000..f8bc343 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_SysCtrl.h @@ -0,0 +1,383 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// System Control Individual Register Bit Definitions: +// + + +// PLL Status Register +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// High speed peripheral clock register bit definitions: +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// Low speed peripheral clock register bit definitions: +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// Peripheral clock control register 0 bit definitions: +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// Peripheral clock control register 1 bit definitions: +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + + +// Peripheral clock control register 2 bit definitions: +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + + + +// PLL control register bit definitions: +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// Low Power Mode 0 control register bit definitions: +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// Dual-mapping configuration register bit definitions: +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +//--------------------------------------------------------------------------- +// System Control Register File: +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + union HISPCP_REG HISPCP; // 10: High-speed peripheral clock pre-scaler + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + Uint16 SCSR; // 18: System control and status register + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + Uint16 WDCR; // 25: WD timer control register + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + + +/* --------------------------------------------------- */ +/* CSM Registers */ +/* */ +/* ----------------------------------------------------*/ + +/* CSM Status & Control register bit definitions */ +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit + +}; + +/* Allow access to the bit fields or entire register */ +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +/* CSM Register File */ +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +/* Password locations */ +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + + + +/* Flash Registers */ + +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + + +/* Flash Option Register bit definitions */ +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +/* Flash Power Modes Register bit definitions */ +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + + +/* Flash Status Register bit definitions */ +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +/* Flash Sleep to Standby Wait Counter Register bit definitions */ +struct FSTDBYWAIT_BITS { // bit description + Uint16 STDBYWAIT:9; // 0-8 Bank/Pump Sleep to Standby Wait Count bits + Uint16 rsvd:7; // 9-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +/* Flash Standby to Active Wait Counter Register bit definitions */ +struct FACTIVEWAIT_BITS { // bit description + Uint16 ACTIVEWAIT:9; // 0-8 Bank/Pump Standby to Active Wait Count bits + Uint16 rsvd:7; // 9-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +/* Bank Read Access Wait State Register bit definitions */ +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +/* OTP Read Access Wait State Register bit definitions */ +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +/* Allow access to the bit fields or entire register */ +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + union FSTDBYWAIT_REG FSTDBYWAIT; // Pump/Bank Sleep to Standby Wait State Register + union FACTIVEWAIT_REG FACTIVEWAIT; // Pump/Bank Standby to Active Wait State Register + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +//--------------------------------------------------------------------------- +// System Control External References & Function Declarations: +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_XIntrupt.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_XIntrupt.h new file mode 100644 index 0000000..6f860f6 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_XIntrupt.h @@ -0,0 +1,83 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + + + + +//--------------------------------------------------------------------------- +// External Interrupt Register File: +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +//--------------------------------------------------------------------------- +// External Interrupt References & Function Declarations: +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/Source/External/v120/DSP2833x_headers/include/DSP2833x_Xintf.h b/Source/External/v120/DSP2833x_headers/include/DSP2833x_Xintf.h new file mode 100644 index 0000000..cb68744 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/include/DSP2833x_Xintf.h @@ -0,0 +1,120 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: March 20, 2007 16:34:08 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +// XINTF timing register bit definitions: +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// XINTF control register bit definitions: +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// XINTF bank switching register bit definitions: +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + + +//--------------------------------------------------------------------------- +// XINTF Register File: +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +//--------------------------------------------------------------------------- +// XINTF External References & Function Declarations: +// +extern volatile struct XINTF_REGS XintfRegs; + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/Source/External/v120/DSP2833x_headers/source/DSP2833x_GlobalVariableDefs.c b/Source/External/v120/DSP2833x_headers/source/DSP2833x_GlobalVariableDefs.c new file mode 100644 index 0000000..d7cd332 --- /dev/null +++ b/Source/External/v120/DSP2833x_headers/source/DSP2833x_GlobalVariableDefs.c @@ -0,0 +1,444 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: June 2, 2008 11:12:33 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalVariableDefs.c +// +// TITLE: DSP2833x Global Variables and Data Section Pragmas. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File + +//--------------------------------------------------------------------------- +// Define Global Peripheral Variables: +// +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcRegsFile") +#else +#pragma DATA_SECTION(AdcRegs,"AdcRegsFile"); +#endif +volatile struct ADC_REGS AdcRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcMirrorFile") +#else +#pragma DATA_SECTION(AdcMirror,"AdcMirrorFile"); +#endif +volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer0RegsFile") +#else +#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer0Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer1RegsFile") +#else +#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer1Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer2RegsFile") +#else +#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer2Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CsmPwlFile") +#else +#pragma DATA_SECTION(CsmPwl,"CsmPwlFile"); +#endif +volatile struct CSM_PWL CsmPwl; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CsmRegsFile") +#else +#pragma DATA_SECTION(CsmRegs,"CsmRegsFile"); +#endif +volatile struct CSM_REGS CsmRegs; + + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DevEmuRegsFile") +#else +#pragma DATA_SECTION(DevEmuRegs,"DevEmuRegsFile"); +#endif +volatile struct DEV_EMU_REGS DevEmuRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaRegsFile") +#else +#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); +#endif +volatile struct DMA_REGS DmaRegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaRegsFile") +#else +#pragma DATA_SECTION(ECanaRegs,"ECanaRegsFile"); +#endif +volatile struct ECAN_REGS ECanaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMboxesFile") +#else +#pragma DATA_SECTION(ECanaMboxes,"ECanaMboxesFile"); +#endif +volatile struct ECAN_MBOXES ECanaMboxes; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaLAMRegsFile") +#else +#pragma DATA_SECTION(ECanaLAMRegs,"ECanaLAMRegsFile"); +#endif +volatile struct LAM_REGS ECanaLAMRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMOTSRegsFile") +#else +#pragma DATA_SECTION(ECanaMOTSRegs,"ECanaMOTSRegsFile"); +#endif +volatile struct MOTS_REGS ECanaMOTSRegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMOTORegsFile") +#else +#pragma DATA_SECTION(ECanaMOTORegs,"ECanaMOTORegsFile"); +#endif +volatile struct MOTO_REGS ECanaMOTORegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbRegsFile") +#else +#pragma DATA_SECTION(ECanbRegs,"ECanbRegsFile"); +#endif +volatile struct ECAN_REGS ECanbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMboxesFile") +#else +#pragma DATA_SECTION(ECanbMboxes,"ECanbMboxesFile"); +#endif +volatile struct ECAN_MBOXES ECanbMboxes; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbLAMRegsFile") +#else +#pragma DATA_SECTION(ECanbLAMRegs,"ECanbLAMRegsFile"); +#endif +volatile struct LAM_REGS ECanbLAMRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMOTSRegsFile") +#else +#pragma DATA_SECTION(ECanbMOTSRegs,"ECanbMOTSRegsFile"); +#endif +volatile struct MOTS_REGS ECanbMOTSRegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMOTORegsFile") +#else +#pragma DATA_SECTION(ECanbMOTORegs,"ECanbMOTORegsFile"); +#endif +volatile struct MOTO_REGS ECanbMOTORegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm1RegsFile") +#else +#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); +#endif +volatile struct EPWM_REGS EPwm1Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm2RegsFile") +#else +#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); +#endif +volatile struct EPWM_REGS EPwm2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm3RegsFile") +#else +#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); +#endif +volatile struct EPWM_REGS EPwm3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm4RegsFile") +#else +#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); +#endif +volatile struct EPWM_REGS EPwm4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm5RegsFile") +#else +#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); +#endif +volatile struct EPWM_REGS EPwm5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm6RegsFile") +#else +#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); +#endif +volatile struct EPWM_REGS EPwm6Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap1RegsFile") +#else +#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); +#endif +volatile struct ECAP_REGS ECap1Regs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap2RegsFile") +#else +#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); +#endif +volatile struct ECAP_REGS ECap2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap3RegsFile") +#else +#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); +#endif +volatile struct ECAP_REGS ECap3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap4RegsFile") +#else +#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); +#endif +volatile struct ECAP_REGS ECap4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap5RegsFile") +#else +#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); +#endif +volatile struct ECAP_REGS ECap5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap6RegsFile") +#else +#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); +#endif +volatile struct ECAP_REGS ECap6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep1RegsFile") +#else +#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); +#endif +volatile struct EQEP_REGS EQep1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep2RegsFile") +#else +#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); +#endif +volatile struct EQEP_REGS EQep2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioCtrlRegsFile") +#else +#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); +#endif +volatile struct GPIO_CTRL_REGS GpioCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioDataRegsFile") +#else +#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); +#endif +volatile struct GPIO_DATA_REGS GpioDataRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioIntRegsFile") +#else +#pragma DATA_SECTION(GpioIntRegs,"GpioIntRegsFile"); +#endif +volatile struct GPIO_INT_REGS GpioIntRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2caRegsFile") +#else +#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); +#endif +volatile struct I2C_REGS I2caRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspaRegsFile") +#else +#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); +#endif +volatile struct MCBSP_REGS McbspaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspbRegsFile") +#else +#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile"); +#endif +volatile struct MCBSP_REGS McbspbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PartIdRegsFile") +#else +#pragma DATA_SECTION(PartIdRegs,"PartIdRegsFile"); +#endif +volatile struct PARTID_REGS PartIdRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieCtrlRegsFile") +#else +#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); +#endif +volatile struct PIE_CTRL_REGS PieCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieVectTableFile") +#else +#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); +#endif +struct PIE_VECT_TABLE PieVectTable; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SciaRegsFile") +#else +#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); +#endif +volatile struct SCI_REGS SciaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScibRegsFile") +#else +#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); +#endif +volatile struct SCI_REGS ScibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScicRegsFile") +#else +#pragma DATA_SECTION(ScicRegs,"ScicRegsFile"); +#endif +volatile struct SCI_REGS ScicRegs; + + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpiaRegsFile") +#else +#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); +#endif +volatile struct SPI_REGS SpiaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SysCtrlRegsFile") +#else +#pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile"); +#endif +volatile struct SYS_CTRL_REGS SysCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("FlashRegsFile") +#else +#pragma DATA_SECTION(FlashRegs,"FlashRegsFile"); +#endif +volatile struct FLASH_REGS FlashRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XIntruptRegsFile") +#else +#pragma DATA_SECTION(XIntruptRegs,"XIntruptRegsFile"); +#endif +volatile struct XINTRUPT_REGS XIntruptRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XintfRegsFile") +#else +#pragma DATA_SECTION(XintfRegs,"XintfRegsFile"); +#endif +volatile struct XINTF_REGS XintfRegs; + + + +//=========================================================================== +// End of file. +//=========================================================================== + + + + + + + + + diff --git a/Source/Internal/ADC.c b/Source/Internal/ADC.c new file mode 100644 index 0000000..119d8a4 --- /dev/null +++ b/Source/Internal/ADC.c @@ -0,0 +1,338 @@ +#include "DSP2833x_Device.h" // DSP281x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP281x Examples Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "ADC.h" + +#include "log_to_mem.h" +#include "RS485.h" +#include "filter_bat2.h" + +#include "measure.h" +#include "message.h" +#include "package.h" + +#include "peripher.h" + +Uint16 adc_table_lem[4]; +Uint16 ADC_table[28]; // Ïîòîìó ÷òî +4 êàëèáð +Uint16 prev_ok[28]; + +unsigned int COUNT_ONE_CANAL; +unsigned int COUNT_DISCHARGE; +unsigned int COUNT_TRANSICIA; +unsigned int FILTER_CLIP; + +long WAKE, WAKE_TIME; + +// Prototype statements for functions found within this file. +interrupt void adc_isr(void); + +void setup_adc() +{ + long CLKdiv,HSPCLKdiv,Rate; + int i; + + #if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT + #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz + #endif + #if (CPU_FRQ_100MHZ) + #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz + #endif + +// Specific clock setting for this example: +// EALLOW; +// SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK +// EDIS; + +// Interrupts that are used in this example are re-mapped to +// ISR functions found within this file. + EALLOW; // This is needed to write to EALLOW protected register + PieVectTable.ADCINT = &adc_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + InitAdc(); // For this example, init the ADC + +// Enable ADCINT in PIE + PieCtrlRegs.PIEIER1.bit.INTx6 = 1; + IER |= M_INT1; // Enable CPU Interrupt 1 +// EINT; // Enable Global interrupt INTM +// ERTM; // Enable Global realtime interrupt DBGM + + for(i=0;i<28;i++) + ADC_table[i]= + prev_ok[i] = 0; + +// Configure ADC + if(Desk==dsk_LOAD) + { + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x0005; // Setup 2 conv's on SEQ1 + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x3; // òåìïåðàòóðà (êîòîðîé íåò) + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // îìåãà + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x5; // íàïðóãà 1 + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x4; // íàïðóãà 2 + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x7; // òîê 1 + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x2; // òîê 2 + } + + if(Desk==dsk_BKST) + { + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x0002; // Setup 2 conv's on SEQ1 + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; //0x5;//0x7; // Setup ADCINA3 as 1st SEQ1 conv. + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; //0x4;// Setup ADCINA2 as 2nd SEQ1 conv. + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; //0x4;// Setup ADCINA2 as 2nd SEQ1 conv. + } + + if(Desk==dsk_COMM) + { + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x0006; // Setup 2 conv's on SEQ1 + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x5; // ñíà÷àëà òîæå áóäóò òåìïåðàòóðû + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x4; // Setup ADCINA2 as 2nd SEQ1 conv. + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x7; // Setup ADCINA2 as 2nd SEQ1 conv. + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x2; // Setup ADCINA2 as 2nd SEQ1 conv. + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x3; // Setup ADCINA2 as 2nd SEQ1 conv. + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x6; // Setup ADCINA2 as 2nd SEQ1 conv. + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x1; // Setup ADCINA2 as 2nd SEQ1 conv. + } + + if(Desk==dsk_BKSD) + { + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x0000; // Setup 2 conv's on SEQ1 + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup ADCINA3 as 1st SEQ1 conv. + } + + if(Desk==dsk_SHKF) + { + AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x000F; // Setup 2 conv's on SEQ1 + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x2; // 380 Ô1 + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x3; // 380 Ô2 + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x6; // 31 Ô1 + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0xC; // 31 Ô2 ? + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0xA; // 31 UC1 + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0xB; // 31 UC2 + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x7; // 24 ÏÓ + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x4; // 24 ÏÓ + + AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x5; // 24 ÏÊ áûëî 5 + AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x1; // 15 Äð + AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xE; // +24 Äò + AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0x0; // +24 Äò + AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0x8; // -24 Äò áûëî 8 + + AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xF;//0xF; // ÄÒ° 1 + AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0xD;//0xD; // ÄÒ° 2 + AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0x9;//0x9; + } + + AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1 + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit + + AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode + + AdcRegs.ADCTRL1.bit.CONT_RUN=0; + AdcRegs.ADCTRL1.bit.ACQ_PS = 15; + +//AdcRegs.ADCTRL1.bit.CPS=1; + + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE + +// Assumes ePWM1 clock is already enabled in InitSysCtrl(); + EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group + EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount + EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event + EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value + + EPwm1Regs.TBCTL.bit.HSPCLKDIV = CLKMULT; + EPwm1Regs.TBCTL.bit.CLKDIV=2; + + CLKdiv = 1<>4; Current_count(i); + } } + + if(Desk==dsk_LOAD) + { + Temper = AdcRegs.ADCRESULT1 >> 4; + modbus[0x63] = Temper; + Temper = filterbat(&adc_filter[0],Temper); + modbus[0x1D] = (Temper-DAC_04)/(DAC_20-DAC_04)*(200-40)+40; + } + + if(Desk==dsk_SHKF) + { + for(i=0;i=tpl_cans) cownt_cans=0; + +// Èìåííî çäåñü íåò äûð +// if(sens_type[cownt_cans]) + { + i++; + Temper= *(&AdcRegs.ADCRESULT0 + cownt_cans) >>4; + ADC_table[cownt_cans]=filterbat(&adc_filter[cownt_cans],Temper); + if(sens_type[cownt_cans]==TERMO_AD) Temper_count(cownt_cans,0); + else Power_count(cownt_cans); + } } } + + if(TermoSW) + { + if(cownt_one_canal==COUNT_DISCHARGE) + { + code_tpl_canal = cownt_cans; + + if(TermoAD) + { + if(cownt_cans == TPL_CANS ) code_tpl_canal = TERMOPAIR-1; + if(cownt_cans == TPL_CANS+1) code_tpl_canal = TERMOPAIR-2; // ïîòîìó ÷òî 300 è 400 íàîáîðîò + } + select_tpl_canal(code_tpl_canal); + } + + if(cownt_one_canal > COUNT_TRANSICIA) + for(i=0;i>4; + + ok = abs(ADC_table[n]-Temper) < FILTER_CLIP; + + if(ok) cwnt_ok[i]++; + + if(ok|!prev_ok[n]) + { + Filter = filterbat(&adc_filter[n],Temper); + + if(WAKE)ADC_table[n] = Temper; + else ADC_table[n] = Filter; + } + } +/* +if(cownt_cans == TPL_CANS) +{ +Test_mem_limit(8); + +modbus[0x2F]=Log.Adres; + +for(i=0;i<1;i++) +{ + Log_to_mem(*(&AdcRegs.ADCRESULT0 + i) >>4); + Log_to_mem(ADC_table[2*cownt_cans+i]); +} +} +*/ + if(++cownt_one_canal>=COUNT_ONE_CANAL) + { cownt_one_canal=0; + + select_tpl_255(); + + for(i=0;i= TPL_CANS+2) + { cownt_cans=0; + + for(i=0;i= period_dac) + { + count_dac=0; + + if(WAKEpowse) + { + --WAKEpowse; + + if( (WAKEpowse == DAC_FREQ/2*6)|| + (WAKEpowse == DAC_FREQ/2*5)|| + (WAKEpowse == DAC_FREQ/2*4)|| + (WAKEpowse == DAC_FREQ/2*3)|| + (WAKEpowse == DAC_FREQ/2*2)|| + (WAKEpowse == DAC_FREQ/2*1) ) + { + Init_DAC(); x=1; + } } + + else + { + if(cUMPstart) + { + if(count_load > (time_dac/2))count_load++; + + if(++count_load > time_dac) count_load = time_dac; + +// sinus = ((float)(DAC_stop - DAC_go) / 16.0 * count_load) + ((float)(DAC_go - 4.0) / 16.0 * time_dac); + sinus = (10.0 / 16.0 * count_load) + (2.0 / 16.0 * time_dac); + } + else + { count_load = 0; + sinus=0; + x = (x+1)&0x3FF; + } + + if(!x || cInitDac) + { + Init_DAC(); x=1; cInitDac=0; + } + else + { + kod = (int)sinus; + + Anal_output(kod, time_dac); +} } } } diff --git a/Source/Internal/Include/ADC.h b/Source/Internal/Include/ADC.h new file mode 100644 index 0000000..ff176ab --- /dev/null +++ b/Source/Internal/Include/ADC.h @@ -0,0 +1,8 @@ + +extern Uint16 adc_table_lem[]; +extern Uint16 ADC_table[]; + +void setup_adc(void); + +extern long WAKE,WAKE_TIME; + diff --git a/Source/Internal/Include/DAC.h b/Source/Internal/Include/DAC.h new file mode 100644 index 0000000..31e0786 --- /dev/null +++ b/Source/Internal/Include/DAC.h @@ -0,0 +1,7 @@ +void Load_runner(void); +void Anal_output(long vrot, long maxx); +void Init_DAC(void); +void Setup_DAC_time(void); + +extern unsigned long IMPowse; +extern unsigned int period_dac, time_dac; diff --git a/Source/Internal/Include/GPIO_table.h b/Source/Internal/Include/GPIO_table.h new file mode 100644 index 0000000..1c8079b --- /dev/null +++ b/Source/Internal/Include/GPIO_table.h @@ -0,0 +1,388 @@ +#define COMM_gpio00_dir 0UL +#define COMM_gpio01_dir 0UL +#define COMM_gpio02_dir 0UL +#define COMM_gpio03_dir 0UL +#define COMM_gpio04_dir 0UL +#define COMM_gpio05_dir 0UL +#define COMM_gpio06_dir 0UL +#define COMM_gpio07_dir 0UL +#define COMM_gpio08_dir 0UL +#define COMM_gpio09_dir 0UL +#define COMM_gpio10_dir 0UL +#define COMM_gpio11_dir 0UL + +#define COMM_gpio19_dir 1UL // 63 — SPI +#define COMM_gpio20_dir 0UL // 64 2:9B mode 2 +#define COMM_gpio21_dir 0UL // 65 2:9A mode 4 +#define COMM_gpio22_dir 0UL // 66 2:12C mode 1 +#define COMM_gpio23_dir 0UL +#define COMM_gpio24_dir 1UL // 68 2:12A select +#define COMM_gpio25_dir 1UL // 69 2:11C select +#define COMM_gpio26_dir 0UL +#define COMM_gpio27_dir 1UL // 73 2:11A select + +#define COMM_gpio32_dir 1UL // 74 2:10B DIOD green +#define COMM_gpio33_dir 0UL +#define COMM_gpio34_dir 1UL // 142 — SCI + +#define COMM_gpio48_dir 1UL // 88 2:14C DIOD red +#define COMM_gpio49_dir 1UL // 89 2:14B select +#define COMM_gpio50_dir 0UL // 90 2:14A input 2 +#define COMM_gpio51_dir 0UL // 91 2:13C mode !8 +#define COMM_gpio52_dir 1UL // 94 2:13B select +#define COMM_gpio53_dir 0UL // 95 2:13A input 1 + +#define COMM_gpio58_dir 1UL // 100 1:13C rez 1 +#define COMM_gpio59_dir 1UL // 110 1:13B gotov +#define COMM_gpio60_dir 1UL // 111 1:13A led 1 +#define COMM_gpio61_dir 1UL // 112 1:14C rez 2 +#define COMM_gpio62_dir 0UL +#define COMM_gpio63_dir 1UL // 114 1:14A led 2 + +//=========================================================================== + +#define BKSD_gpio00_dir 0UL // 5 2:7A oil +#define BKSD_gpio01_dir 1UL // 6 2:4A select +#define BKSD_gpio02_dir 0UL // 7 2:7B oil +#define BKSD_gpio03_dir 1UL // 10 2:4B select +#define BKSD_gpio04_dir 0UL // 11 2:7C oil +#define BKSD_gpio05_dir 0UL +#define BKSD_gpio06_dir 0UL +#define BKSD_gpio07_dir 1UL // 16 2:3A select +#define BKSD_gpio08_dir 1UL // 17 2:6B select +#define BKSD_gpio09_dir 1UL // 18 2:3B select +#define BKSD_gpio10_dir 0UL // 19 2:6C oil +#define BKSD_gpio11_dir 1UL // 20 2:3C select + +#define BKSD_gpio19_dir 1UL // 63 — SPI +#define BKSD_gpio20_dir 0UL // 64 2:9B mode 2 +#define BKSD_gpio21_dir 0UL // 65 2:9A mode 4 +#define BKSD_gpio22_dir 0UL // 66 2:12C mode 1 +#define BKSD_gpio23_dir 0UL +#define BKSD_gpio24_dir 0UL +#define BKSD_gpio25_dir 0UL +#define BKSD_gpio26_dir 0UL +#define BKSD_gpio27_dir 0UL + +#define BKSD_gpio32_dir 1UL // 74 2:10B DIOD green +#define BKSD_gpio33_dir 0UL +#define BKSD_gpio34_dir 1UL // 142 — SCI + +#define BKSD_gpio48_dir 1UL // 88 2:14C DIOD red +#define BKSD_gpio49_dir 0UL // 89 2:14B input 2 +#define BKSD_gpio50_dir 0UL // 90 2:14A input 1 +#define BKSD_gpio51_dir 0UL // 91 2:13C mode !8 +#define BKSD_gpio52_dir 0UL +#define BKSD_gpio53_dir 0UL + +#define BKSD_gpio58_dir 0UL +#define BKSD_gpio59_dir 1UL // 110 1:13B gotov +#define BKSD_gpio60_dir 1UL // 111 1:13A led 1 +#define BKSD_gpio61_dir 1UL // 112 1:14C rez 2 +#define BKSD_gpio62_dir 1UL // 113 1:14B rez 1 +#define BKSD_gpio63_dir 1UL // 114 1:14A led 2 + +//=========================================================================== + +#define BKST_gpio00_dir 1UL // 5 2:7A select +#define BKST_gpio01_dir 1UL // 6 2:4A select +#define BKST_gpio02_dir 0UL +#define BKST_gpio03_dir 1UL // 10 2:4B select +#define BKST_gpio04_dir 0UL +#define BKST_gpio05_dir 0UL +#define BKST_gpio06_dir 1UL // 13 2:6A select +#define BKST_gpio07_dir 1UL // 16 2:3A select +#define BKST_gpio08_dir 1UL // 17 2:6B select +#define BKST_gpio09_dir 1UL // 18 2:3B select +#define BKST_gpio10_dir 0UL +#define BKST_gpio11_dir 1UL // 20 2:3C select + +#define BKST_gpio19_dir 1UL // 63 — SPI +#define BKST_gpio20_dir 0UL // 64 2:9B mode 2 +#define BKST_gpio21_dir 0UL // 65 2:9A mode 4 +#define BKST_gpio22_dir 0UL // 66 2:12C mode 1 +#define BKST_gpio23_dir 0UL +#define BKST_gpio24_dir 1UL // 68 2:12A select +#define BKST_gpio25_dir 0UL +#define BKST_gpio26_dir 0UL +#define BKST_gpio27_dir 1UL // 73 2:11A select + +#define BKST_gpio32_dir 1UL // 74 2:10B DIOD green +#define BKST_gpio33_dir 0UL +#define BKST_gpio34_dir 1UL // 142 — SCI + +#define BKST_gpio48_dir 1UL // 88 2:14C DIOD red +#define BKST_gpio49_dir 0UL +#define BKST_gpio50_dir 1UL // 90 2:14A select +#define BKST_gpio51_dir 0UL // 91 2:13C mode !8 +#define BKST_gpio52_dir 0UL +#define BKST_gpio53_dir 1UL // 95 2:13A select + +#define BKST_gpio58_dir 1UL // 100 1:13C rez 1 +#define BKST_gpio59_dir 1UL // 110 1:13B gotov +#define BKST_gpio60_dir 1UL // 111 1:13A led 1 +#define BKST_gpio61_dir 1UL // 112 1:14C rez 2 +#define BKST_gpio62_dir 1UL // 113 1:14B led 2 +#define BKST_gpio63_dir 0UL // 114 1:14A input + +//=========================================================================== + +#define PULT_gpio00_dir 1UL // 5 2:7A gotov +#define PULT_gpio01_dir 0UL +#define PULT_gpio02_dir 1UL // 7 2:7B ro 1 +#define PULT_gpio03_dir 0UL +#define PULT_gpio04_dir 0UL +#define PULT_gpio05_dir 0UL +#define PULT_gpio06_dir 1UL // 13 2:6A kanal +#define PULT_gpio07_dir 0UL +#define PULT_gpio08_dir 1UL // 17 2:6B kanal +#define PULT_gpio09_dir 0UL +#define PULT_gpio10_dir 0UL +#define PULT_gpio11_dir 0UL + +#define PULT_gpio19_dir 1UL // 63 — SPI +#define PULT_gpio20_dir 0UL // 64 2:9B mode 2 +#define PULT_gpio21_dir 0UL // 65 2:9A mode 4 +#define PULT_gpio22_dir 0UL // 66 2:12C mode 1 +#define PULT_gpio23_dir 0UL // 67 2:12B button +#define PULT_gpio24_dir 0UL // 68 2:12A button +#define PULT_gpio25_dir 0UL +#define PULT_gpio26_dir 0UL // 72 2:11B button +#define PULT_gpio27_dir 0UL // 73 2:11A button + +#define PULT_gpio32_dir 1UL // 74 2:10B DIOD green +#define PULT_gpio33_dir 0UL +#define PULT_gpio34_dir 1UL // 142 — SCI + +#define PULT_gpio48_dir 1UL // 88 2:14C DIOD red +#define PULT_gpio49_dir 0UL // 89 2:14B button +#define PULT_gpio50_dir 0UL // 90 2:14A button +#define PULT_gpio51_dir 0UL // 91 2:13C mode !8 +#define PULT_gpio52_dir 0UL // 94 2:13B button +#define PULT_gpio53_dir 0UL // 95 2:13A button + +#define PULT_gpio58_dir 0UL +#define PULT_gpio59_dir 0UL +#define PULT_gpio60_dir 0UL +#define PULT_gpio61_dir 0UL +#define PULT_gpio62_dir 0UL +#define PULT_gpio63_dir 0UL + +//=========================================================================== + +#define PLT2_gpio00_dir 1UL // 5 2:7A gotov +#define PLT2_gpio01_dir 0UL +#define PLT2_gpio02_dir 0UL +#define PLT2_gpio03_dir 1UL // 10 2:4B res_pb +#define PLT2_gpio04_dir 0UL // 11 2:7C button +#define PLT2_gpio05_dir 0UL // 12 2:4C button +#define PLT2_gpio06_dir 1UL // 13 2:6A kanal +#define PLT2_gpio07_dir 0UL +#define PLT2_gpio08_dir 1UL // 17 2:6B kanal +#define PLT2_gpio09_dir 1UL // 18 2:3B res_lb +#define PLT2_gpio10_dir 0UL +#define PLT2_gpio11_dir 0UL + +#define PLT2_gpio19_dir 1UL // 63 × SPI +#define PLT2_gpio20_dir 0UL // 64 2:9B mode 2 +#define PLT2_gpio21_dir 0UL // 65 2:9A mode 4 +#define PLT2_gpio22_dir 0UL // 66 2:12C mode 1 +#define PLT2_gpio23_dir 0UL // 67 2:12B button +#define PLT2_gpio24_dir 0UL // 68 2:12A button +#define PLT2_gpio25_dir 0UL // 69 2:11C button +#define PLT2_gpio26_dir 0UL // 72 2:11B button +#define PLT2_gpio27_dir 0UL // 73 2:11A button + +#define PLT2_gpio32_dir 1UL // 74 2:10B DIOD green +#define PLT2_gpio33_dir 0UL // 75 2:10C button +#define PLT2_gpio34_dir 1UL // 142 × SCI + +#define PLT2_gpio48_dir 0UL // 88 2:14C button +#define PLT2_gpio49_dir 0UL // 89 2:14B button +#define PLT2_gpio50_dir 0UL // 90 2:14A button +#define PLT2_gpio51_dir 0UL // 91 2:13C mode !8 +#define PLT2_gpio52_dir 0UL // 94 2:13B button +#define PLT2_gpio53_dir 0UL // 95 2:13A button + +#define PLT2_gpio58_dir 0UL +#define PLT2_gpio59_dir 0UL +#define PLT2_gpio60_dir 0UL +#define PLT2_gpio61_dir 0UL +#define PLT2_gpio62_dir 0UL +#define PLT2_gpio63_dir 0UL + +//=========================================================================== + +#define SHKF_gpio00_dir 0UL // 5 2:7A input +#define SHKF_gpio01_dir 0UL // 6 2:4A input +#define SHKF_gpio02_dir 0UL // 7 2:7B input +#define SHKF_gpio03_dir 0UL // 10 2:4B input +#define SHKF_gpio04_dir 0UL // 11 2:7C input +#define SHKF_gpio05_dir 0UL // 12 2:4C input +#define SHKF_gpio06_dir 0UL // 13 2:6A input +#define SHKF_gpio07_dir 0UL // 16 2:3A input +#define SHKF_gpio08_dir 0UL // 17 2:6B input +#define SHKF_gpio09_dir 0UL // 18 2:3B input +#define SHKF_gpio10_dir 0UL // 19 2:6C input +#define SHKF_gpio11_dir 0UL // 20 2:3C input + +#define SHKF_gpio19_dir 1UL // 63 — SPI +#define SHKF_gpio20_dir 0UL // 64 2:9B mode 2 +#define SHKF_gpio21_dir 0UL // 65 2:9A mode 4 +#define SHKF_gpio22_dir 0UL // 66 2:12C mode 1 +#define SHKF_gpio23_dir 0UL // 67 2:12B input +#define SHKF_gpio24_dir 0UL // 68 2:12A input +#define SHKF_gpio25_dir 0UL // 69 2:11C input +#define SHKF_gpio26_dir 0UL // 72 2:11B input +#define SHKF_gpio27_dir 0UL // 73 2:11A input + +#define SHKF_gpio32_dir 0UL // 74 2:10B input +#define SHKF_gpio33_dir 0UL // 75 2:10C input +#define SHKF_gpio34_dir 1UL // 142 — SCI + +#define SHKF_gpio48_dir 1UL // 88 2:14C DIOD red +#define SHKF_gpio49_dir 0UL // 89 2:14B input +#define SHKF_gpio50_dir 0UL // 90 2:14A input +#define SHKF_gpio51_dir 0UL // 91 2:13C mode !8 +#define SHKF_gpio52_dir 0UL // 94 2:13B input +#define SHKF_gpio53_dir 0UL // 95 2:13A input + +#define SHKF_gpio58_dir 1UL // 100 1:13C rez 1 +#define SHKF_gpio59_dir 1UL // 110 1:13B gotov +#define SHKF_gpio60_dir 1UL // 111 1:13A led 1 +#define SHKF_gpio61_dir 1UL // 112 1:14C rez 2 +#define SHKF_gpio62_dir 0UL +#define SHKF_gpio63_dir 1UL // 114 1:14A led 2 + +//=========================================================================== + +#define LOAD_gpio00_dir 0UL +#define LOAD_gpio01_dir 1UL // 6 2:4A led 2 +#define LOAD_gpio02_dir 0UL +#define LOAD_gpio03_dir 1UL // 10 2:4B res_out 2 +#define LOAD_gpio04_dir 0UL +#define LOAD_gpio05_dir 0UL +#define LOAD_gpio06_dir 0UL // 13 2:6A omega d +#define LOAD_gpio07_dir 1UL // 16 2:3A led 1 +#define LOAD_gpio08_dir 0UL // 17 2:6B start 1 +#define LOAD_gpio09_dir 1UL // 18 2:3B res_out 1 +#define LOAD_gpio10_dir 0UL +#define LOAD_gpio11_dir 0UL // 20 2:3C res_in 0 + +#define LOAD_gpio19_dir 1UL // 63 — SPI +#define LOAD_gpio20_dir 0UL // 64 2:9B mode 2 +#define LOAD_gpio21_dir 0UL // 65 2:9A mode 4 +#define LOAD_gpio22_dir 0UL // 66 2:12C mode 1 +#define LOAD_gpio23_dir 0UL +#define LOAD_gpio24_dir 0UL +#define LOAD_gpio25_dir 0UL +#define LOAD_gpio26_dir 0UL +#define LOAD_gpio27_dir 0UL + +#define LOAD_gpio32_dir 1UL // 74 2:10B DIOD green +#define LOAD_gpio33_dir 0UL +#define LOAD_gpio34_dir 1UL // 142 — SCI + +#define LOAD_gpio48_dir 1UL // 88 2:14C DIOD red +#define LOAD_gpio49_dir 0UL +#define LOAD_gpio50_dir 0UL +#define LOAD_gpio51_dir 0UL // 91 2:13C mode !8 +#define LOAD_gpio52_dir 0UL +#define LOAD_gpio53_dir 0UL + +#define LOAD_gpio58_dir 1UL // 100 1:13C stop_dptb +#define LOAD_gpio59_dir 1UL // 110 1:13B csdac +#define LOAD_gpio60_dir 1UL // 111 1:13A didac +#define LOAD_gpio61_dir 1UL // 112 1:14C gotov +#define LOAD_gpio62_dir 1UL // 113 1:14B start_dptb +#define LOAD_gpio63_dir 1UL // 114 1:14A clkdac + +//=========================================================================== + +#define COMM_GPADIR (COMM_gpio00_dir ) + (COMM_gpio01_dir<<1) + (COMM_gpio02_dir<<2) + (COMM_gpio03_dir<<3) + \ + (COMM_gpio04_dir<<4) + (COMM_gpio05_dir<<5) + (COMM_gpio06_dir<<6) + (COMM_gpio07_dir<<7) + \ + (COMM_gpio08_dir<<8) + (COMM_gpio09_dir<<9) + (COMM_gpio10_dir<<10)+ (COMM_gpio11_dir<<11)+ \ + (COMM_gpio19_dir<<19)+ \ + (COMM_gpio20_dir<<20)+ (COMM_gpio21_dir<<21)+ (COMM_gpio22_dir<<22)+ (COMM_gpio23_dir<<23)+ \ + (COMM_gpio24_dir<<24)+ (COMM_gpio25_dir<<25)+ (COMM_gpio26_dir<<26)+ (COMM_gpio27_dir<<27); +#define COMM_GPBDIR (COMM_gpio32_dir )+ (COMM_gpio33_dir<<1) + (COMM_gpio34_dir<<2 )+ \ + (COMM_gpio48_dir<<16)+ (COMM_gpio49_dir<<17)+ (COMM_gpio50_dir<<18)+ (COMM_gpio51_dir<<19)+ \ + (COMM_gpio52_dir<<20)+ (COMM_gpio53_dir<<21)+ \ + (COMM_gpio58_dir<<26)+ (COMM_gpio59_dir<<27)+ \ + (COMM_gpio60_dir<<28)+ (COMM_gpio61_dir<<29)+ (COMM_gpio62_dir<<30)+ (COMM_gpio63_dir<<31); + +#define BKSD_GPADIR (BKSD_gpio00_dir ) + (BKSD_gpio01_dir<<1) + (BKSD_gpio02_dir<<2) + (BKSD_gpio03_dir<<3) + \ + (BKSD_gpio04_dir<<4) + (BKSD_gpio05_dir<<5) + (BKSD_gpio06_dir<<6) + (BKSD_gpio07_dir<<7) + \ + (BKSD_gpio08_dir<<8) + (BKSD_gpio09_dir<<9) + (BKSD_gpio10_dir<<10)+ (BKSD_gpio11_dir<<11)+ \ + (BKSD_gpio19_dir<<19)+ \ + (BKSD_gpio20_dir<<20)+ (BKSD_gpio21_dir<<21)+ (BKSD_gpio22_dir<<22)+ (BKSD_gpio23_dir<<23)+ \ + (BKSD_gpio24_dir<<24)+ (BKSD_gpio25_dir<<25)+ (BKSD_gpio26_dir<<26)+ (BKSD_gpio27_dir<<27); +#define BKSD_GPBDIR (BKSD_gpio32_dir )+ (BKSD_gpio33_dir<<1) + (BKSD_gpio34_dir<<2 )+ \ + (BKSD_gpio48_dir<<16)+ (BKSD_gpio49_dir<<17)+ (BKSD_gpio50_dir<<18)+ (BKSD_gpio51_dir<<19)+ \ + (BKSD_gpio52_dir<<20)+ (BKSD_gpio53_dir<<21)+ \ + (BKSD_gpio58_dir<<26)+ (BKSD_gpio59_dir<<27)+ \ + (BKSD_gpio60_dir<<28)+ (BKSD_gpio61_dir<<29)+ (BKSD_gpio62_dir<<30)+ (BKSD_gpio63_dir<<31); + +#define BKST_GPADIR (BKST_gpio00_dir ) + (BKST_gpio01_dir<<1) + (BKST_gpio02_dir<<2) + (BKST_gpio03_dir<<3) + \ + (BKST_gpio04_dir<<4) + (BKST_gpio05_dir<<5) + (BKST_gpio06_dir<<6) + (BKST_gpio07_dir<<7) + \ + (BKST_gpio08_dir<<8) + (BKST_gpio09_dir<<9) + (BKST_gpio10_dir<<10)+ (BKST_gpio11_dir<<11)+ \ + (BKST_gpio19_dir<<19)+ \ + (BKST_gpio20_dir<<20)+ (BKST_gpio21_dir<<21)+ (BKST_gpio22_dir<<22)+ (BKST_gpio23_dir<<23)+ \ + (BKST_gpio24_dir<<24)+ (BKST_gpio25_dir<<25)+ (BKST_gpio26_dir<<26)+ (BKST_gpio27_dir<<27); +#define BKST_GPBDIR (BKST_gpio32_dir )+ (BKST_gpio33_dir<<1) + (BKST_gpio34_dir<<2 )+ \ + (BKST_gpio48_dir<<16)+ (BKST_gpio49_dir<<17)+ (BKST_gpio50_dir<<18)+ (BKST_gpio51_dir<<19)+ \ + (BKST_gpio52_dir<<20)+ (BKST_gpio53_dir<<21)+ \ + (BKST_gpio58_dir<<26)+ (BKST_gpio59_dir<<27)+ \ + (BKST_gpio60_dir<<28)+ (BKST_gpio61_dir<<29)+ (BKST_gpio62_dir<<30)+ (BKST_gpio63_dir<<31); + +#define PULT_GPADIR (PULT_gpio00_dir ) + (PULT_gpio01_dir<<1) + (PULT_gpio02_dir<<2) + (PULT_gpio03_dir<<3) + \ + (PULT_gpio04_dir<<4) + (PULT_gpio05_dir<<5) + (PULT_gpio06_dir<<6) + (PULT_gpio07_dir<<7) + \ + (PULT_gpio08_dir<<8) + (PULT_gpio09_dir<<9) + (PULT_gpio10_dir<<10)+ (PULT_gpio11_dir<<11)+ \ + (PULT_gpio19_dir<<19)+ \ + (PULT_gpio20_dir<<20)+ (PULT_gpio21_dir<<21)+ (PULT_gpio22_dir<<22)+ (PULT_gpio23_dir<<23)+ \ + (PULT_gpio24_dir<<24)+ (PULT_gpio25_dir<<25)+ (PULT_gpio26_dir<<26)+ (PULT_gpio27_dir<<27); +#define PULT_GPBDIR (PULT_gpio32_dir )+ (PULT_gpio33_dir<<1) + (PULT_gpio34_dir<<2 )+ \ + (PULT_gpio48_dir<<16)+ (PULT_gpio49_dir<<17)+ (PULT_gpio50_dir<<18)+ (PULT_gpio51_dir<<19)+ \ + (PULT_gpio52_dir<<20)+ (PULT_gpio53_dir<<21)+ \ + (PULT_gpio58_dir<<26)+ (PULT_gpio59_dir<<27)+ \ + (PULT_gpio60_dir<<28)+ (PULT_gpio61_dir<<29)+ (PULT_gpio62_dir<<30)+ (PULT_gpio63_dir<<31); + +#define PLT2_GPADIR (PLT2_gpio00_dir ) + (PLT2_gpio01_dir<<1) + (PLT2_gpio02_dir<<2) + (PLT2_gpio03_dir<<3) + \ + (PLT2_gpio04_dir<<4) + (PLT2_gpio05_dir<<5) + (PLT2_gpio06_dir<<6) + (PLT2_gpio07_dir<<7) + \ + (PLT2_gpio08_dir<<8) + (PLT2_gpio09_dir<<9) + (PLT2_gpio10_dir<<10)+ (PLT2_gpio11_dir<<11)+ \ + (PLT2_gpio19_dir<<19)+ \ + (PLT2_gpio20_dir<<20)+ (PLT2_gpio21_dir<<21)+ (PLT2_gpio22_dir<<22)+ (PLT2_gpio23_dir<<23)+ \ + (PLT2_gpio24_dir<<24)+ (PLT2_gpio25_dir<<25)+ (PLT2_gpio26_dir<<26)+ (PLT2_gpio27_dir<<27); +#define PLT2_GPBDIR (PLT2_gpio32_dir )+ (PLT2_gpio33_dir<<1) + (PLT2_gpio34_dir<<2 )+ \ + (PLT2_gpio48_dir<<16)+ (PLT2_gpio49_dir<<17)+ (PLT2_gpio50_dir<<18)+ (PLT2_gpio51_dir<<19)+ \ + (PLT2_gpio52_dir<<20)+ (PLT2_gpio53_dir<<21)+ \ + (PLT2_gpio58_dir<<26)+ (PLT2_gpio59_dir<<27)+ \ + (PLT2_gpio60_dir<<28)+ (PLT2_gpio61_dir<<29)+ (PLT2_gpio62_dir<<30)+ (PLT2_gpio63_dir<<31); + +#define SHKF_GPADIR (SHKF_gpio00_dir ) + (SHKF_gpio01_dir<<1) + (SHKF_gpio02_dir<<2) + (SHKF_gpio03_dir<<3) + \ + (SHKF_gpio04_dir<<4) + (SHKF_gpio05_dir<<5) + (SHKF_gpio06_dir<<6) + (SHKF_gpio07_dir<<7) + \ + (SHKF_gpio08_dir<<8) + (SHKF_gpio09_dir<<9) + (SHKF_gpio10_dir<<10)+ (SHKF_gpio11_dir<<11)+ \ + (SHKF_gpio19_dir<<19)+ \ + (SHKF_gpio20_dir<<20)+ (SHKF_gpio21_dir<<21)+ (SHKF_gpio22_dir<<22)+ (SHKF_gpio23_dir<<23)+ \ + (SHKF_gpio24_dir<<24)+ (SHKF_gpio25_dir<<25)+ (SHKF_gpio26_dir<<26)+ (SHKF_gpio27_dir<<27); +#define SHKF_GPBDIR (SHKF_gpio32_dir )+ (SHKF_gpio33_dir<<1) + (SHKF_gpio34_dir<<2 )+ \ + (SHKF_gpio48_dir<<16)+ (SHKF_gpio49_dir<<17)+ (SHKF_gpio50_dir<<18)+ (SHKF_gpio51_dir<<19)+ \ + (SHKF_gpio52_dir<<20)+ (SHKF_gpio53_dir<<21)+ \ + (SHKF_gpio58_dir<<26)+ (SHKF_gpio59_dir<<27)+ \ + (SHKF_gpio60_dir<<28)+ (SHKF_gpio61_dir<<29)+ (SHKF_gpio62_dir<<30)+ (SHKF_gpio63_dir<<31); + +#define LOAD_GPADIR (LOAD_gpio00_dir ) + (LOAD_gpio01_dir<<1) + (LOAD_gpio02_dir<<2) + (LOAD_gpio03_dir<<3) + \ + (LOAD_gpio04_dir<<4) + (LOAD_gpio05_dir<<5) + (LOAD_gpio06_dir<<6) + (LOAD_gpio07_dir<<7) + \ + (LOAD_gpio08_dir<<8) + (LOAD_gpio09_dir<<9) + (LOAD_gpio10_dir<<10)+ (LOAD_gpio11_dir<<11)+ \ + (LOAD_gpio19_dir<<19)+ \ + (LOAD_gpio20_dir<<20)+ (LOAD_gpio21_dir<<21)+ (LOAD_gpio22_dir<<22)+ (LOAD_gpio23_dir<<23)+ \ + (LOAD_gpio24_dir<<24)+ (LOAD_gpio25_dir<<25)+ (LOAD_gpio26_dir<<26)+ (LOAD_gpio27_dir<<27); +#define LOAD_GPBDIR (LOAD_gpio32_dir )+ (LOAD_gpio33_dir<<1) + (LOAD_gpio34_dir<<2 )+ \ + (LOAD_gpio48_dir<<16)+ (LOAD_gpio49_dir<<17)+ (LOAD_gpio50_dir<<18)+ (LOAD_gpio51_dir<<19)+ \ + (LOAD_gpio52_dir<<20)+ (LOAD_gpio53_dir<<21)+ \ + (LOAD_gpio58_dir<<26)+ (LOAD_gpio59_dir<<27)+ \ + (LOAD_gpio60_dir<<28)+ (LOAD_gpio61_dir<<29)+ (LOAD_gpio62_dir<<30)+ (LOAD_gpio63_dir<<31); + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/Source/Internal/Include/RS485.h b/Source/Internal/Include/RS485.h new file mode 100644 index 0000000..3e4ca38 --- /dev/null +++ b/Source/Internal/Include/RS485.h @@ -0,0 +1,138 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */ +/**************************************************************** + RS485.h + **************************************************************** + * Ïðîöåäóðû ðàáîòû ñ UART * + ****************************************************************/ +#ifndef _RS485 +#define _RS485 + +#ifdef __cplusplus + extern "C" { +#endif + +//#include "DSP2833x_Device.h" // DSP281x Headerfile Include File +//#include "DSP2833x_Sci.h" +//#include "cntrl_adr.h" +//#include "params.h" + +#define COM_1 1 +#define COM_2 2 + +#define MAX_RECEIVE_LENGTH 400 // 80 //150 +#define MAX_SEND_LENGTH 400 //150 + +#define TIME_WAIT_RS_BYTE_OUT 1000 +#define TIME_WAIT_RS_LOST_BYTE 100 +#define RS_TIME_OUT (SECOND*10) + +#define Rec_Bloc_Begin 0x200000 +#define Rec_Bloc_End 0x2F0000 +#define Rec_Bloc_Length (Rec_Bloc_End-Rec_Bloc_Begin) + +/* Message RS declaration */ +typedef struct +{ + volatile struct SCI_REGS *SciRegs; + + unsigned int commnumber; // Íîìåð ïîðòà + unsigned long RS_Length; // Äëèíà ïàêåòà + + unsigned int *pRS_RecvPtr; // Áóôåð ïðèåìà + unsigned int *pRS_SendPtr; // Áóôåð ïîñûëêè + unsigned int *pRecvPtr; + + unsigned int RS_PrevCmd; // Ïðåäûäóùàà êîììàíäà + unsigned int RS_Cmd; // Òåêóùàà êîììàíäà + unsigned int RS_Header[MAX_RECEIVE_LENGTH]; // Çàãîëîâîê + unsigned int flag_TIMEOUT_to_Send; // Ôëàã îæèäàíèà òàéìàóòà íà îòñûëêó + unsigned int flag_TIMEOUT_to_Receive; // Ôëàã îæèäàíèà òàéìàóòà íà ïðèåì + unsigned int RS_DataReady; // Ôëàã ãîòîâíîñòè RS äàííûõ + unsigned int buffer[MAX_SEND_LENGTH]; // Áóôåð äëà îòñûëêè ïî RS + + unsigned int addr_answer; // àäðåñ êóäà îòâå÷àòü â ðåæèìå âåäóùåãî + unsigned int addr_recive; // àäðåñ ïî êîòîðîìó íàñ çàïðîñèëè + unsigned int flag_LEADING; // Ôëàã ðåæèìà êîíòðîëëåðà (ïî óìîë÷àíèþ âåäîìûé) + unsigned long RS_RecvLen; + unsigned long RS_SLength; // Äëèíà ïàêåòà äëà ïîñûëêè + unsigned long RS_SendLen; // Êîëè÷åñòâî áàéò óæå ïåðåäàëè + char RS_SendBlockMode; // Ðåæèì ïåðåäà÷è + char RS_Flag9bit; // äëà RS485???????? + int BS_LoadOK; // Ôëàã óñïåøíîñòè ïðèåìà áëîêà + int RS_FlagBegin; + int RS_HeaderCnt; + int RS_FlagSkiping; + unsigned long curr_baud; + unsigned long time_wait_rs_out; + +} RS_DATA; + +extern RS_DATA rs_a,rs_b; + +extern unsigned int + RS_Len[70]; /* Äåéñòâèòåëüíàà äëèíà êîìàíäû (îòëàäî÷íîé) + 1 */ + +interrupt void RSA_RX_Handler(void); +interrupt void RSA_TX_Handler(void); +interrupt void RSB_RX_Handler(void); +interrupt void RSB_TX_Handler(void); + +/* èíèöèëèçàöèà ïåðåìåííûõ rs_a,rs_b*/ +void create_uart_vars(char size_cmd15); + +/** Ïîâòîðíàà èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà, èñïîëüçóåòñà ïîñëå ïîäâèñà */ +/** Íàñòðîéêà ðåæèìà ïðèåìà/ïåðåäà÷è */ +void RS_SetBitMode(RS_DATA *rs_arr, int n); + +/** Ïîñûëêà áëîêà áàéòîâ. + Ïîñûëàåò ìàññèâà 32-áèòíûõ öåëûõ ÷èñåë ñòàðøèå áèòû äîëæíû áûòü 0. + @precondition Ðàáîòà ô-öèè çàâèñèò îò ìàêðî RS_TRANSMIT_INTR + @param buf àäðåñ ìàññèâà + @param len êîëè÷åñòâî áàéò + @see RS_BSend, RS_TRANSMIT_INTR +*/ +int RS_Send(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len); + +/** Ïîñûëêà áëîêà óïàêîâàííûõ áàéòîâ. + @precondition Ðàáîòà ô-öèè çàâèñèò îò ìàêðî RS_TRANSMIT_INTR + @param buf àäðåñ ìàññèâà + @param len êîëè÷åñòâî 8-áèòíûõ áàéò + @see RS_Send, RS_TRANSMIT_INTR + */ +int RS_BSend(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len); + +/** Èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà */ +void setup_uart(char commnumber,unsigned long speed_baud); /* speed_baud - ñêîðîñòü ëèíèè â áîäàõ */ + +void RS_SetLineMode(RS_DATA *rs_arr, int bit, char parity, int stop); +void RS_SetLineSpeed(RS_DATA *rs_arr, unsigned long speed); + +// Transmit a character from the SCI' +#define SCI_send(x,y) x->SciRegs->SCITXBUF=(unsigned char)(y) + +// Îæèäàíèå çàâåðøåíèà ïåðåäà÷è UART +// wait for TRDY =1 for empty state +#define RS_Wait4OK(x) while(!(x->SciRegs->SCICTL2.bit.TXEMPTY)) + +/** Ïåðåêëþ÷åíèå ëèíèè íà ïðèåì */ +#define RS_Line_to_receive(x) if(x->commnumber==COM_2) GpioDataRegs.GPBDAT.bit.GPIO34 = 1; + +/** Ïåðåêëþ÷åíèå ëèíèè íà ïåðåäà÷ó */ +#define RS_Line_to_send(x) if(x->commnumber==COM_2) GpioDataRegs.GPBDAT.bit.GPIO34 = 0; + +/** Ðàçðåøåíèå ïðåðûâàíèé ïî ïîëó÷åíèþ ñèìâîëà è îøèáêàì îò UART */ +#define enableUARTInt(x) x->SciRegs->SCICTL2.all=2 +#define enableUARTIntW(x) x->SciRegs->SCICTL2.all=1 + +void clear_timer_rs_live(RS_DATA *rs_arr); +void test_rs_live(RS_DATA *rs_arr); + +#ifdef __cplusplus + } +#endif + +#endif /* _RS485 */ + diff --git a/Source/Internal/Include/bios_dsp.h b/Source/Internal/Include/bios_dsp.h new file mode 100644 index 0000000..2575cfa --- /dev/null +++ b/Source/Internal/Include/bios_dsp.h @@ -0,0 +1,120 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */ +/****************************************************************/ +/* Bios_dsp.h */ +/****************************************************************/ + /* Îñíîâíûå êîììàíäû BIOS */ +/****************************************************************/ +#ifndef _BIOS_DSP +#define _BIOS_DSP + +#ifdef __cplusplus + extern "C" { +#endif + +#define BM_PACKED 1 +#define BM_CHAR32 0 + +#define CHIEF 1 +#define SLAVE 0 + +#define ADR_FOR_SPECIAL 0x100 +#define CMD_MODBUS_3 3 +#define ANS_MODBUS_4 4 +#define CMD_MODBUS_15 5 +#define CMD_MODBUS_6 6 +#define ANS_MODBUS_6 7 +#define CMD_MODBUS_16 16 +/* + +CMD_MODBUS_3 = 3, + ANS_MODBUS_3 = 4, + CMD_MODBUS_15 = 5, + CMD_MODBUS_6 = 6, + ANS_MODBUS_6 = 7, + CMD_MODBUS_16 = 16, + */ +enum { + CMD_LOAD=51, CMD_UPLOAD, CMD_RUN, CMD_XFLASH, CMD_TFLASH, + CMD_PEEK, CMD_POKE, CMD_INITLOAD, CMD_INIT,CMD_EXTEND, + + CMD_VECTOR=61, + CMD_IMPULSE, + /* ñòàíäàðòíûå êîìàíäû */ + CMD_STD=65, CMD_STD_ANS + }; + +enum {false=0, true}; + + +/** Âîçâðàùàåò íîìåð êîììàíäû, åñëè åñòü èëè -1 åñëè òðàíçàêöèé íå áûëî */ +int get_command(RS_DATA *rs_arr); + +/** Ñòàíäàðòíûé îòâåò, áåç ïàðàìåòðîâ */ +void Answer(RS_DATA *rs_arr,int n); + +/* íà÷àëüíûå óñòàíîâêè (íå ðàáîòàåò)*/ +void init(RS_DATA *rs_arr); + +/**@name Êîììàíäû +* Êîììàíäû, âûçûâàåìûå ÷åðåç ïîñëåäîâàòåëüíûé êàíàë*/ +//@{ + +/** Èíèöèèðîâàòü çàãðóçêó áëîêà. + Íàñòðàèâàåò ïðèåì áëîêà äàííûõ */ +void initload(RS_DATA *rs_arr); + +/** Çàãðóçêà áëîêà. + Âûçûâàåòñà ïîñëå çàãðóçêè áëîêà ÷åðåç RS */ +void load(RS_DATA *rs_arr); + +/** Âûïîëíèòü ïðîãðàììó â ôîðìàòå Serial Boot. + @precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà + Àäðåñ ïðîãðàììû áåðåòñà èç çàãîëîâêà è + ñðàâíèâàåòñà ñ ïåðåìåííîé RecvPtr, çàïîëíàåìîé â ô-öèè load + @see load */ +void run (RS_DATA *rs_arr); + +/** Ïðî÷èòàòü à÷åéêó ïàìàòè */ +void peek(RS_DATA *rs_arr); + +/** Çàïèñàòü â à÷åéêó ïàìàòè */ +void poke(RS_DATA *rs_arr); + +/** Ïåðåäàòü áëîê ïàìàòè */ +void upload(RS_DATA *rs_arr); + +/** Ïðîøèòü XILINX. + @precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà + Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è + ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load, + òàê æå ñìîòðèò ìàãè÷åñêîå ñëîâî â íà÷àëå ïðîøèâêè + @see load */ +void xflash(RS_DATA *rs_arr); + +/** Ïðîøèòü TMS. + @precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà + Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è + ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load + @see load */ +void tflash(RS_DATA *rs_arr); + + +/* ðàñøèðåííûå êîìàíäû äëà áèîñà */ +void extendbios(RS_DATA *rs_arr); + + +void write_memory(unsigned long addr, unsigned int data); +unsigned int read_memory(unsigned long addr); + + +//@} + + +#ifdef __cplusplus + } +#endif + +#endif/* _BIOS_DSP */ diff --git a/Source/Internal/Include/caliber.h b/Source/Internal/Include/caliber.h new file mode 100644 index 0000000..5da8d7b --- /dev/null +++ b/Source/Internal/Include/caliber.h @@ -0,0 +1,85 @@ +#if BALSAM == 167 //------------------------------------------------------------- + int def_cal[][8] = { + +// ÁÊÑÑ òðàíñ 100 1 100 2 150 1 150 2 + 0, 0, 0, 0, 455, 441, 2459, 2392, // Áîðò 0 + 0, 0, 0, 0, 462, 439, 2442, 2400, // Áîðò 1 + +// Ñèëîâîé UA1 UB1 UA2 UB2 300 1 300 2 400 1 400 2 + 4936, 4877, 4972, 4857, 1886, 1898, 2517, 2535, // Áîðò 0 + 4876, 5005, 4876, 4847, 1898, 1873, 2535, 2502, // Áîðò 1 + +// ÓÌÏ UA UC IA IC 20mA O 4mA O 20mA I 4mA I + 3820, 3790, 3505, 3380, 1736, 683, 854, 14, // Áîðò 0 1062 1980 + 3835, 3785, 3522, 3332, 1745, 689, 860, 17, // Áîðò 1 1720 2405 + +// ÁÊÑÑÄ 100 Ohm 150 Ohm + 1281, 1272, 0, 0, 622, 2263, 0, 0, + +// ÂÝÏ 380Ô1 380Ô2 300 1 300 2 400 1 400 2 + 1290, 1285, 0, 0, 2045, 2045, 2725, 2725 }; +#endif //--------------------------------------------------------------------- + + +#if BALSAM == 166 //------------------------------------------------------------- + int def_cal[][8] = { + +// Ñèëîâîé UA1 UB1 UA2 UB2 300 1 300 2 400 1 400 2 + 4936, 4877, 4972, 4857, 1960, 1920, 2610, 2570, // Áîðò 0 + 4876, 5005, 4876, 4847, 1950, 1965, 2600, 2615, // Áîðò 1 + +// ÓÌÏ UA UC IA IC 20mA O 4mA O 20mA I 4mA I + 3820, 3790, 3505, 3380, 1718, 673, 854, 14, // Áîðò 0 + 3835, 3785, 3522, 3332, 1697, 653, 860, 17, // Áîðò 1 + +// ÂÝÏ 380Ô1 380Ô2 300 1 300 2 400 1 400 2 + 1281, 1272, 0, 0, 2049, 2050, 2749, 2750 }; +#endif //--------------------------------------------------------------------- + +#if BALSAM == 165 //------------------------------------------------------------- + int def_cal[][8] = { + +// Ñèëîâîé UA1 UB1 UA2 UB2 300 1 300 2 400 1 400 2 + 5130, 4960, 4925, 5070, 1881, 1881, 2506, 2516, // Áîðò 0 + 5020, 5040, 4950, 5030, 1871, 1879, 2507, 2514, // Áîðò 1 + +// ÓÌÏ UA UC IA IC 20mA O 4mA O 20mA I 4mA I + 3890, 3865, 5100, 4850, 1730, 675, 854, 14, // Áîðò 0 + 3845, 3800, 3250, 3100, 1044, 0, 860, 17, // Áîðò 1 + +// ÂÝÏ 380Ô1 380Ô2 300 1 300 2 400 1 400 2 + 1289, 1280, 0, 0, 2073, 2071, 2773, 2771 }; +#endif //--------------------------------------------------------------------- + +#if BALSAM == 164 //------------------------------------------------------------- + int def_cal[][8] = { + +// Ñèëîâîé UA1 UB1 UA2 UB2 300 1 300 2 400 1 400 2 + 7573, 7573, 7573, 7573, 1979, 1888, 2592, 2513, // Áîðò 0 + 7573, 7573, 7573, 7573, 1970, 1907, 2584, 2558, // Áîðò 1 + +// ÓÌÏ UA UC IA IC 20mA O 4mA O 20mA I 4mA I + 3920, 3905, 3300, 3220, 1015, 0, 854, 14, // Áîðò 0 + 3835, 3785, 5100, 4600, 1750, 680, 860, 17, // Áîðò 1 + +// ÂÝÏ 380Ô1 380Ô2 300 1 300 2 400 1 400 2 + 1266, 1267, 0, 0, 2063, 2040, 2678, 2655 }; +#endif //--------------------------------------------------------------------- + + +/* +#if PXXXXX == 1 //------------------------------------------------------------- + int def_cal[][6] = { + +// Ñèëîâîé UA1 UB1 UA2 UB2 300 1 300 2 400 1 400 2 + 0400, 0400, 0400, 0400, 1950, 1950, 2600, 2600, // Áîðò 0 + 0400, 0400, 0400, 0400, 1950, 1950, 2600, 2600, // Áîðò 1 + +// ÓÌÏ UA UC IA IC 20mA 4mA + 0400, 0400, 4800, 4800, 0, 0, 0, 0, // Áîðò 0 + 0400, 0400, 4800, 4800, 0, 0, 0, 0, // Áîðò 1 + +// ÂÝÏ 380Ô1 380Ô2 300 1 300 2 400 1 400 2 + 1270, 1270, 0, 0, 1950, 1950, 2600, 2600 }; +#endif //--------------------------------------------------------------------- +*/ diff --git a/Source/Internal/Include/cntrl_adr.h b/Source/Internal/Include/cntrl_adr.h new file mode 100644 index 0000000..100021f --- /dev/null +++ b/Source/Internal/Include/cntrl_adr.h @@ -0,0 +1,44 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */ +/**************************************************************** + cntrl_adr.h + **************************************************************** + * Àäðåñ êîíòðîëëåðà * + ****************************************************************/ + +#ifndef _CNTRL_ADR +#define _CNTRL_ADR + +#ifdef __cplusplus + extern "C" { +#endif + +/** àäðåñ êîíòðîëëåðà äëà ïîñûëêè âñåì ÀÈÍàì */ +extern int ADDR_FOR_ALL; + +/** àäðåñ êîíòðîëëåðà äëà ïîñûëêè îòâåòà */ +extern const int ADDR_ANSWER; + +/** àäðåñà òåðìèíàëà äëà ïîñûëêè îòâåòà */ +extern const int ADDR_TERMINAL; + +/* Àäðåñ êîíòðîëëåðà */ +extern int CNTRL_ADDR; + +/* Óíèâåðñàëüíûé àäðåñ êîíòðîëëåðà */ +extern const int CNTRL_ADDR_UNIVERSAL; + +/** Óñòàíîâêà àäðåñà êîíòðîëëåðà äëà ïðîøèâêè */ +void set_cntrl_addr (int cntrl_addr,int cntrl_addr_for_all); + + +extern int cntr_addr_c; +extern int cntr_addr_c_all; + +#ifdef __cplusplus + } +#endif + +#endif /* _CNTRL_ADR */ diff --git a/Source/Internal/Include/crc16.h b/Source/Internal/Include/crc16.h new file mode 100644 index 0000000..a1787cc --- /dev/null +++ b/Source/Internal/Include/crc16.h @@ -0,0 +1,8 @@ +typedef unsigned short WORD; +typedef unsigned char byte; + + +unsigned int get_crc_ccitt(unsigned int crc, unsigned int *buf, unsigned long size ); +unsigned int get_crc_16(unsigned int crc,unsigned int *buf,unsigned long size ); +unsigned int get_crc_16b(unsigned int crc,unsigned int *buf,unsigned long size ); +int get_crc16(unsigned int *buf, int size ); diff --git a/Source/Internal/Include/ecan.h b/Source/Internal/Include/ecan.h new file mode 100644 index 0000000..d252d5d --- /dev/null +++ b/Source/Internal/Include/ecan.h @@ -0,0 +1,3 @@ +void InitCan(int Port, int DevNum); +void CAN_send(int Port, int data[], int Addr); +extern int CAN_input_data[]; diff --git a/Source/Internal/Include/filter_bat2.h b/Source/Internal/Include/filter_bat2.h new file mode 100644 index 0000000..a002e9b --- /dev/null +++ b/Source/Internal/Include/filter_bat2.h @@ -0,0 +1,49 @@ +#ifndef _FILTER_BAT2 +#define _FILTER_BAT2 + +#ifdef __cplusplus + extern "C" { +#endif + +#define K1_FILTER_BATTER2_1HZ 0.0000096 +#define K2_FILTER_BATTER2_1HZ 1.94468056 +#define K3_FILTER_BATTER2_1HZ -0.94471895 + +#define K1_FILTER_BATTER2_3HZ 0.00008766 +#define K2_FILTER_BATTER2_3HZ 1.97347532 +#define K3_FILTER_BATTER2_3HZ -0.97382594 + +#define K1_FILTER_BATTER2_5HZ 0.00024135 +#define K2_FILTER_BATTER2_5HZ 1.95581276 +#define K3_FILTER_BATTER2_5HZ -0.95677816 + +#define K1_FILTER_BATTER2_10HZ 0.00094411 +#define K2_FILTER_BATTER2_10HZ 1.91126422 +#define K3_FILTER_BATTER2_10HZ -0.91504065 + +typedef struct { float k_0; + float k_1; + float k_2; + float i_0; + float i_1; + float i_2; + float u_0; + float u_1; + float u_2; + } FILTERBAT; + + +#define DEF_FILTERBAT { K1_FILTER_BATTER2_3HZ, \ + K2_FILTER_BATTER2_3HZ, \ + K3_FILTER_BATTER2_3HZ, \ + 0,0,0,0,0,0} + +float filterbat(FILTERBAT *b, float InpVarCurr); + + +#ifdef __cplusplus + } +#endif + +#endif /* _FILTER_BAT2 */ + diff --git a/Source/Internal/Include/kanal.h b/Source/Internal/Include/kanal.h new file mode 100644 index 0000000..fce5473 --- /dev/null +++ b/Source/Internal/Include/kanal.h @@ -0,0 +1 @@ +void kanal_Send(int adr, long dat, int dot); diff --git a/Source/Internal/Include/log_to_mem.h b/Source/Internal/Include/log_to_mem.h new file mode 100644 index 0000000..f6a9e82 --- /dev/null +++ b/Source/Internal/Include/log_to_mem.h @@ -0,0 +1,49 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2001ã. */ +/****************************************************************/ +/* log_to_mem.h + **************************************************************** + * Çàïèñü ëîãîâ â ïàìyòü * + ****************************************************************/ + +#ifndef _LOG_TO_MEM +#define _LOG_TO_MEM + +#ifdef __cplusplus + extern "C" { +#endif + +/* Îïðåäåëåíèa äëa ðàáîòû ëîããåðà */ +#define LOG_PAGE_START 0x0200000 +#define LOG_PAGE_LEN 0xFA00 + +extern int no_write, never_write; // Ôëàãè, ÷òîáû íå ïèñàòü (åñëè ÷òî) + +typedef struct +{ + unsigned long Start; + unsigned long Finis; + unsigned long Adres; + unsigned int Circl; + +} LOG; + +extern LOG Log; + +/* Çàïèñü ñëîâa â ïàìàòü, ãäå ëîãè ëåæàò */ +#define Log_to_mem(x) *(int *)(Log.Adres++) = x + +/* Ïðîâåðêà ãðàíèöû ïàìàòè äëà ëîãîâ */ +//#define Test_mem_limit(x) if(Log.Adres > (Log.Finis - (x))) Log.Adres = Log.Start +#define Test_mem_limit(x) if(Log.Adres > (Log.Finis - (x))) Log.Adres -=(x) + +/* Î÷èñòêà ïàìàòè (îáíóëåíèå) */ +void clear_mem(); + +#ifdef __cplusplus + } +#endif + +#endif /* _LOG_TO_MEM */ diff --git a/Source/Internal/Include/measure.h b/Source/Internal/Include/measure.h new file mode 100644 index 0000000..357ca3c --- /dev/null +++ b/Source/Internal/Include/measure.h @@ -0,0 +1,122 @@ +// âãâ +#ifndef _MEASURE +#define _MEASURE + +interrupt void cpu_timer1_isr_SENS(void); + +void Init_sensors(void); +void Init_sensors_more(void); +void Init_packMask(void); +void Temper_count(int chan, int ovn); +void Current_count(int chan); +void Power_count(int chan); +void calc_sensor_koef(void); +void Is_Voltage_Hi(void); +void calc_volta_edge(void); + +int er_anal(int term, unsigned int * count, long edge, int pre); + +typedef union +{ + struct + { + unsigned int Tear :1; + unsigned int res :1; + unsigned int Wry :1; + unsigned int Out :1; + unsigned int Over :1; + unsigned int Hyper :1; + unsigned int Contr :1; + unsigned int res2 :1; + + unsigned int Stop :1; + unsigned int Ready :1; + unsigned int Discr1 :1; + unsigned int Discr2 :1; + unsigned int Discr3 :1; + unsigned int Discr4 :1; + unsigned int Ignor :1; + unsigned int Bypas :1; + + } bit; + unsigned int all; + +#define Imit Discr4 + +} ERROR; + +typedef union +{ + struct + { + unsigned int Error :1; + unsigned int Alarm :1; + unsigned int OverHeat :1; + unsigned int SubHeat :1; + unsigned int OutHeat :1; + unsigned int Test_lamp :1; + + } bit; + unsigned int all; + +} FLAG; + +#define NOER 0xE000//C +#define EROR 0x01FF + +#define READY_FREQ (500.0 * 2)// Ãö +#define BLINK_FREQ 2 // Ãö +#define BLINK_TIME (READY_FREQ / BLINK_FREQ) + +#define CANPOWSE 20 + +#define ADC_FREQ 3750 //3885.0//777//2000//20000 //777 //3885 // Ãö (777*5) +#define DAC_FREQ 200//5 // Ãö + +#define LOAD_TIME 30//15 // sec + +extern unsigned int Caliber_time; + +#define SENS_ERR_WAIT 10 + +#define maximum_bright 10 + +#define Pi 3.1415926535897932384626433832795 +#define Pi_2 1.5707963267948966192313216916398 + +#define ZERO 27 + +#define Cooling 5 // (°Ñ) Ãèñòåðåçèñ ïî ñíàòèþ ïåðåãðåâà + +#define COSPi6 0.86602540378443864676372317075294 + +#define RADIX2 1.4142135623730950488016887242097 + +#define POWER_380 0 // ïèòàíèå 380 +#define POWER_38O 1 // ïèòàíèå 380 +#define CURRENT 2 // òîê +#define VOLTAGE 3 // íàïðàæåíèå +#define POWER_31 4 // ïèòàíèå 31 +#define POWER_27 5 // ïèòàíèå 24 +#define POWER_24 6 // ïèòàíèå 24 +#define POWER_15 7 // ïèòàíèå 15 +#define TERMO_AD 8 // òåðìîäàò÷èê ìåëêîñõåìà +#define TERMO_RS 9 // òåðìîðåçèñòîð +#define TRM_OBEH 10 // òåðìîäàò÷èê îâåí + +extern int TPL_CANS,tpl_cans; + +extern int READY; + +extern FILTERBAT filter[]; +extern FILTERBAT adc_filter[]; +extern FILTERBAT out_filter[]; + +extern int sens_type[]; +extern int ext_temp[], ext_diag[]; + +extern unsigned long Lonely; +extern unsigned int CanPowse,CanGO; +extern unsigned int Maska[][8]; + +#endif //_MEASURE diff --git a/Source/Internal/Include/message.h b/Source/Internal/Include/message.h new file mode 100644 index 0000000..350e495 --- /dev/null +++ b/Source/Internal/Include/message.h @@ -0,0 +1,42 @@ +#ifndef MESSAGE_H +#define MESSAGE_H + +typedef unsigned char CHAR; + +#define ANSWER_LEN 0x80 //70 // 16+16+16+16+6 +#define REPLY_LEN 0x19 + +#define byte_hi byte_1 +#define byte_lo byte_0 + +typedef struct +{ + unsigned char Address; // Àäðåñ êîíòðîëëåðà + unsigned char Number; // Íîìåð êîìàíäû + + BAITE byte0; + BAITE byte1; + BAITE byte2; + BAITE byte3; + BAITE byte4; + BAITE byte5; + BAITE byte6; + BAITE byte7; + + unsigned char crc_lo; + unsigned char crc_hi; + unsigned char add_byte; +} CMD_TO_TMS; + +extern int modbus[]; + +void ReceiveCommandModbus3(RS_DATA *rs_arr); +void ReceiveCommandModbus6(RS_DATA *rs_arr); +void SendCommandModbus4(RS_DATA *rs_arr); +void ReceiveAnswerModbus4(RS_DATA *rs_arr); + +void Save_params(void); +void Load_params(void); +void Default_params(void); + +#endif //MESSAGE_H diff --git a/Source/Internal/Include/package.h b/Source/Internal/Include/package.h new file mode 100644 index 0000000..1a9d3d3 --- /dev/null +++ b/Source/Internal/Include/package.h @@ -0,0 +1,168 @@ +#ifndef PACKAGE +#define PACKAGE + +#define BALSAM 167 + +#if BALSAM == 167 +#define OBOROT STRAIGHT +#define CALIB_RS +#define OWEN +#endif +#if BALSAM == 166 +#define OBOROT REVERSE +#endif +#if BALSAM == 165 +#define OBOROT STRAIGHT +#endif +#if BALSAM == 164 +#define OBOROT REVERSE +#endif + +#define ONBOARDCALIBER +#define TERMOPAIR 14 +#define CURRENTOS (TERMOPAIR*2) + +//----------------------------------------------- +#define adr_TRN1 1 +#define adr_TRN2 2 +#define adr_POW1 3 +#define adr_POW2 4 +#define adr_LOA1 5 +#define adr_LOA2 6 +#define adr_ENG1 7 +#define adr_PULT 8 +#define adr_SHKF 9 +//------------------- +#define adr_REC1 0xff +#define adr_REC2 0xff +#define adr_INV1 0xff +#define adr_INV2 0xff +#define adr_BRK1 0xff +#define adr_BRK2 0xff +#define adr_ENG2 0xff +#define adr_PLT1 0xff +#define adr_PLT2 0xff +#define adr_DSTR 0xff + +//----------------------------------------------- +#define dsk_COMM 1 +#define dsk_BKSD 2 +#define dsk_BKST 3 +#define dsk_EPLT 4 +#define dsk_SHKF 5 +#define dsk_LOAD 6 +//----------------------------------------------- + +//----------------------------------------------- +#define TPL_TRN 10 +#if BALSAM == 167 +#define TPL_POW 7 +#define OWEN_DT 2 +#else +#define TPL_POW 8 +#define OWEN_DT 0 +#endif +#define TPL_ENG 8 +#define TPL_SHK 15 +//----------------------------------------------- + +#define Modbus ((WORDE *)modbus) + +#define start_error 0x00 +#define start_data 0x18 +#define start_hi_edge 0x30 +#define start_lo_edge 0x48 + +#define sens_error ((ERROR *)(modbus+start_error)) +#define sens_data (modbus+start_data) +#define sens_hi_edge (modbus+start_hi_edge) +#define sens_lo_edge (modbus+start_lo_edge) + +#define InputRep0 Modbus[0].bit.bitA +#define InputRep1 Modbus[0].bit.bitB +#define InputRep2 Modbus[0].bit.bitC + +#define Inputs Modbus[0x10] +#define Buttons Modbus[0x16] + +#define Jumpers modbus[0x17] + +#define bTestLamp Buttons.bit.bit0 +#define bSecretBt Buttons.bit.bit1 +#define bTermoCal Buttons.bit.bit2 + +#define Cancount (modbus+0x60) // ïàóçà ìåæäó I ïîñûëêàìè CAN +#define Bright (modbus+0x62) // àðêîñòü ñèãíàëüíûõ ëàìïî÷åê +#define Brightness modbus[0x62] // àðêîñòü ñèãíàëüíûõ ëàìïî÷åê + +#define Owncount modbus[0x63] // ïàóçà ìåæäó îïðîñàìè OWEN + +/* Íå âðåìà! +#define DAC_go modbus[0x64] // íà÷àëî çàðàäà +#define DAC_stop modbus[0x65] // êîíåö çàðàäà +*/ + +#define m_FAST 0 +#define m_SLOW 1 + +#define Zero_lev (modbus+0x70) + +#define DAC_20 modbus[0x6E] +#define DAC_04 modbus[0x6F] + +#define DAC_max() modbus[0x78] // 751//0x0000 804 +#define DAC_min() modbus[0x79] // 2162//0x0FFF 2373 +#define DAC_cal() modbus[0x7A] + +#define Caliber (modbus+0x74) + +#define K380_1 Caliber[0] +#define K380_2 Caliber[1] + +#define KPOW_1 Caliber[0] +#define KPOW_2 Caliber[1] +#define KPOW_3 Caliber[2] +#define KPOW_4 Caliber[3] + +#define NormaU Caliber[8] +#define DeltaU Caliber[9] + +#define TCaliber (modbus+0x78) + +#define K300_1 TCaliber[0] +#define K300_2 TCaliber[1] +#define K400_1 TCaliber[2] +#define K400_2 TCaliber[3] + +#define K100_1 TCaliber[0] +#define K100_2 TCaliber[1] +#define K150_1 TCaliber[2] +#define K150_2 TCaliber[3] + +#define K100_D TCaliber[0] +#define K150_D TCaliber[1] + +#define LastMode Modbus[126].all + +#define Commands Modbus[127].all +#define cTestLamp Modbus[127].bit.bit0 +#define cDefParam Modbus[127].bit.bit1 +#define cSaveParam Modbus[127].bit.bit2 +#define cLoadParam Modbus[127].bit.bit3 + +#define cTermoCal Modbus[127].bit.bit4 +#define cKoefCalc Modbus[127].bit.bit5 + +#define cUMPreset Modbus[127].bit.bit6 +#define cUMPstart Modbus[127].bit.bit7 +#define cInitDac Modbus[127].bit.bit8 +#define cCalibrDac Modbus[127].bit.bit9 + +#define cSecretBt Modbus[127].bit.bitA +#define cLiteFire Modbus[127].bit.bitB +#define cRawMeat Modbus[127].bit.bitC + +#define cReset Modbus[127].bit.bitF + +#endif //PACKAGE + diff --git a/Source/Internal/Include/peripher.h b/Source/Internal/Include/peripher.h new file mode 100644 index 0000000..3d1eecf --- /dev/null +++ b/Source/Internal/Include/peripher.h @@ -0,0 +1,153 @@ +#include "DSP2833x_Device.h" // DSP281x Headerfile Include File + +extern int Mode,Desk,TermoAD,TermoRS,TermoSW,Kurrent,Kalibro,Owen; + +void setup_leds_line(void); +void unsetup_leds_line(void); + +#define led1_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1 +#define led2_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO48=1 +#define led1_off() GpioDataRegs.GPBSET.bit.GPIO32=1 +#define led2_off() GpioDataRegs.GPBSET.bit.GPIO48=1 +#define led1_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1 +#define led2_on() GpioDataRegs.GPBCLEAR.bit.GPIO48=1 + + +// READY --------------------------------------------------------- +static inline void dat_READY(int x) +{ if(Desk==dsk_LOAD) GpioDataRegs.GPBDAT.bit.GPIO61=!x; else + GpioDataRegs.GPBDAT.bit.GPIO59=!x; } +static inline void set_READY(void) +{ if(Desk==dsk_LOAD) GpioDataRegs.GPBCLEAR.bit.GPIO61=1; else + GpioDataRegs.GPBCLEAR.bit.GPIO59=1; } +static inline void clear_READY(void) +{ if(Desk==dsk_LOAD) GpioDataRegs.GPBSET.bit.GPIO61=1; else + GpioDataRegs.GPBSET.bit.GPIO59=1; } +static inline void toggle_READY(void) +{ if(Desk==dsk_LOAD) GpioDataRegs.GPBTOGGLE.bit.GPIO61=1;else + GpioDataRegs.GPBTOGGLE.bit.GPIO59=1;} + +// PULT READY ----------------------------------------------------- +static inline void dat_ONLINE(int x) +{ GpioDataRegs.GPADAT.bit.GPIO0=!x; } +static inline void set_ONLINE(void) +{ GpioDataRegs.GPASET.bit.GPIO0=1; } +static inline void clear_ONLINE(void) +{ GpioDataRegs.GPACLEAR.bit.GPIO0=1; } +static inline void toggle_ONLINE(void) +{ GpioDataRegs.GPATOGGLE.bit.GPIO0=1; } + +// LED OUT 1 ----------------------------------------------------- +static inline void dat_LED_OUT_1(int x) +{ if(Desk==dsk_BKST || Desk==dsk_COMM) + GpioDataRegs.GPBDAT.bit.GPIO60=!x; else + if(Desk==dsk_LOAD) GpioDataRegs.GPADAT.bit.GPIO7=!x; else + GpioDataRegs.GPBDAT.bit.GPIO60=x; } +static inline void set_LED_OUT_1(void) +{ if(Desk==dsk_BKST || Desk==dsk_COMM) + GpioDataRegs.GPBCLEAR.bit.GPIO60=1; else + if(Desk==dsk_LOAD) GpioDataRegs.GPACLEAR.bit.GPIO7=1; else + GpioDataRegs.GPBSET.bit.GPIO60=1; } +static inline void clear_LED_OUT_1(void) +{ if(Desk==dsk_BKST || Desk==dsk_COMM) + GpioDataRegs.GPBSET.bit.GPIO60=1; else + if(Desk==dsk_LOAD) GpioDataRegs.GPASET.bit.GPIO7=1; else + GpioDataRegs.GPBCLEAR.bit.GPIO60=1; } +static inline void toggle_LED_OUT_1(void) +{ if(Desk==dsk_LOAD) GpioDataRegs.GPATOGGLE.bit.GPIO7=1; else + GpioDataRegs.GPBTOGGLE.bit.GPIO60=1;} + +// LED OUT 2 ----------------------------------------------------- +static inline void dat_LED_OUT_2(int x) +{ if(Desk==dsk_LOAD) GpioDataRegs.GPADAT.bit.GPIO1=!x; else + if(Desk==dsk_BKST) GpioDataRegs.GPBDAT.bit.GPIO62=!x; else + if(Desk==dsk_COMM) GpioDataRegs.GPBDAT.bit.GPIO63=!x; else + GpioDataRegs.GPBDAT.bit.GPIO63=x; } +static inline void set_LED_OUT_2(void) +{ if(Desk==dsk_LOAD) GpioDataRegs.GPACLEAR.bit.GPIO1=1; else + if(Desk==dsk_BKST) GpioDataRegs.GPBCLEAR.bit.GPIO62=1; else + if(Desk==dsk_COMM) GpioDataRegs.GPBCLEAR.bit.GPIO63=1; else + GpioDataRegs.GPBSET.bit.GPIO63=1; } +static inline void clear_LED_OUT_2(void) +{ if(Desk==dsk_LOAD) GpioDataRegs.GPASET.bit.GPIO7=1; else + if(Desk==dsk_BKST) GpioDataRegs.GPBSET.bit.GPIO62=1; else + if(Desk==dsk_COMM) GpioDataRegs.GPBSET.bit.GPIO63=1; else + GpioDataRegs.GPBCLEAR.bit.GPIO63=1; } +static inline void toggle_LED_OUT_2(void) +{ if(Desk==dsk_LOAD) GpioDataRegs.GPATOGGLE.bit.GPIO1=1; else + if(Desk==dsk_BKST) GpioDataRegs.GPBTOGGLE.bit.GPIO62=1;else + GpioDataRegs.GPBTOGGLE.bit.GPIO63=1;} + +// RES OUT 1 ----------------------------------------------------- +static inline void dat_RES_OUT_1(int x) +{ + if(Desk==dsk_LOAD || Desk==dsk_EPLT) + GpioDataRegs.GPADAT.bit.GPIO9=!x; else + if(Desk==dsk_BKSD) GpioDataRegs.GPBDAT.bit.GPIO62=!x; else + GpioDataRegs.GPBDAT.bit.GPIO58=!x; } +static inline void set_RES_OUT_1(void) +{ + if(Desk==dsk_LOAD || Desk==dsk_EPLT) + GpioDataRegs.GPACLEAR.bit.GPIO9=1; else + if(Desk==dsk_BKSD) GpioDataRegs.GPBCLEAR.bit.GPIO62=1; else + GpioDataRegs.GPBCLEAR.bit.GPIO58=1; } +static inline void clear_RES_OUT_1(void) +{ + if(Desk==dsk_LOAD || Desk==dsk_EPLT) + GpioDataRegs.GPASET.bit.GPIO9=1; else + if(Desk==dsk_BKSD) GpioDataRegs.GPBSET.bit.GPIO62=1; else + GpioDataRegs.GPBSET.bit.GPIO58=1; } +static inline void toggle_RES_OUT_1(void) +{ + if(Desk==dsk_LOAD || Desk==dsk_EPLT) + GpioDataRegs.GPATOGGLE.bit.GPIO9=1; else + if(Desk==dsk_BKSD) GpioDataRegs.GPBTOGGLE.bit.GPIO62=1;else + GpioDataRegs.GPBTOGGLE.bit.GPIO58=1;} + +// RES OUT 2 ----------------------------------------------------- +static inline void dat_RES_OUT_2(int x) +{ if(Desk==dsk_LOAD || Desk==dsk_EPLT) + GpioDataRegs.GPADAT.bit.GPIO3=!x; else + GpioDataRegs.GPBDAT.bit.GPIO61=x; } +static inline void set_RES_OUT_2(void) +{ if(Desk==dsk_LOAD || Desk==dsk_EPLT) + GpioDataRegs.GPACLEAR.bit.GPIO3=1; else + GpioDataRegs.GPBCLEAR.bit.GPIO61=1; } +static inline void clear_RES_OUT_2(void) +{ if(Desk==dsk_LOAD || Desk==dsk_EPLT) + GpioDataRegs.GPASET.bit.GPIO3=1; else + GpioDataRegs.GPBSET.bit.GPIO61=1; } +static inline void toggle_RES_OUT_2(void) +{ if(Desk==dsk_LOAD || Desk==dsk_EPLT) + GpioDataRegs.GPATOGGLE.bit.GPIO3=1; else + GpioDataRegs.GPBTOGGLE.bit.GPIO61=1;} + +// START DPTB ----------------------------------------------------- +static inline void dat_START_DPTB(int x) +{ GpioDataRegs.GPBDAT.bit.GPIO62=x; } +static inline void set_START_DPTB(void) +{ GpioDataRegs.GPBSET.bit.GPIO62=1; } +static inline void clear_START_DPTB(void) +{ GpioDataRegs.GPBCLEAR.bit.GPIO62=1; } +static inline void toggle_START_DPTB(void) +{ GpioDataRegs.GPBTOGGLE.bit.GPIO62=1;} + +// STOP DPTB ----------------------------------------------------- +static inline void dat_STOP_DPTB(int x) +{ GpioDataRegs.GPBDAT.bit.GPIO58=x; } +static inline void set_STOP_DPTB(void) +{ GpioDataRegs.GPBSET.bit.GPIO58=1; } +static inline void clear_STOP_DPTB(void) +{ GpioDataRegs.GPBCLEAR.bit.GPIO58=1; } +static inline void toggle_STOP_DPTB(void) +{ GpioDataRegs.GPBTOGGLE.bit.GPIO58=1;} + +extern LONGE DigErr; + +void select_tpl_canal(int n_tpl); +void select_tpl_255(void); + +void get_Mode(void); +void get_Buttons(void); + + diff --git a/Source/Internal/Include/pulto.h b/Source/Internal/Include/pulto.h new file mode 100644 index 0000000..fb41363 --- /dev/null +++ b/Source/Internal/Include/pulto.h @@ -0,0 +1,3 @@ +//void what_is(void); + +interrupt void cpu_timer1_isr_PULT(void); diff --git a/Source/Internal/Include/spise2p.h b/Source/Internal/Include/spise2p.h new file mode 100644 index 0000000..1e41c26 --- /dev/null +++ b/Source/Internal/Include/spise2p.h @@ -0,0 +1,134 @@ +/*===================================================================== +File name : SPISE2P.H + +Originator : Settu Duraisamy + C2000 Applications Team + Texas Instruments + +Description : + Header file containing object definitions, proto type + declaration and default object initializers for + SPI Serial EEPROM driver using VSPI + +Date : 30/6/2003 (DD/MM/YYYY) +=======================================================================*/ + +#ifndef __SPISE2P_H__ + +#define __SPISE2P_H__ + +// ¨ìêîñòü ïàìàòè â áàéòàõ +#define SEEPROM_LEN 0x10000 + +#define NULL 0 + +#define SIXTEEN_BIT 15 +#define EIGHT_BIT 07 + +/***************************************************************/ +/* Configurable Parameter for SPI bus Serial EEPROM */ +/***************************************************************/ +#define SPISE2P_DATA_WIDTH SIXTEEN_BIT//EIGHT_BIT +#define SPISE2P_ADDR_WIDTH SIXTEEN_BIT +#define SPIBAUD_REG_VAL 1//12 +#define SPICLK_PHASE 1 +#define SPICLK_POLARITY 0 + +#define SPIBAUD_RATE 100000 +//10000000 + +/**************************************************************/ +/**************************************************************/ + +/* Serial EEPROM Command words, left justified */ +#define SPISE2P_READ_CMD 0x0300 +#define SPISE2P_WRITE_CMD 0x0200 +#define SPISE2P_WRDI_CMD 0x0400 +#define SPISE2P_WREN_CMD 0x0600 +#define SPISE2P_RDSR_CMD 0x0500 +#define SPISE2P_WRSR_CMD 0x0100 + +#define SPISE2P_RDID_CMD 0x0A00 + +#define SPISE2P_DUMMY_DATA 0x0000 +#define SPISE2P_BUSY_MASK 0x01 + +/* Symbolic constant for SPICCR to transfer 8bit or 16 bit value*/ +#define SPISE2P_TFR16BIT 0x80|(SPICLK_POLARITY<<6)|SIXTEEN_BIT +#define SPISE2P_TFR8BIT 0x80|(SPICLK_POLARITY<<6)|EIGHT_BIT + +/* Status valus */ +#define SPISE2P_WRRQ 1 /* Write Requset */ +#define SPISE2P_RDRQ 2 /* Read request */ +#define SPISE2P_WRIP 4 /* Write in progress */ +#define SPISE2P_RDIP 8 /* Read in progress */ + +/* Message declaration */ +typedef struct { + unsigned int *dataPtr; /* Data pointer */ + unsigned long nrData; /* number of data */ + unsigned long se2pAddr; /* se2pAddr */ + }SE2P_DATA; + + +/* Object declaration */ +typedef struct { + SE2P_DATA *msgPtr; + unsigned int csr; /* control/status register */ + void (*init)(void *); + void (*tick)(void *); + void (*csset)(void); + void (*csclr)(void); + }SPISE2P_DRV; + +#define SPISE2P_DRV_DEFAULTS { NULL,\ + 0,\ + (void (*)(void *))SPISE2P_DRV_init,\ + (void (*)(void *))SPISE2P_DRV_tick,\ + (void (*)(void))SPISE2P_DRV_csset,\ + (void (*)(void))SPISE2P_DRV_csclr} + +typedef SPISE2P_DRV *SPISE2P_DRV_handle; + +void SPISE2P_DRV_init(SPISE2P_DRV * ); +void SPISE2P_DRV_tick(SPISE2P_DRV *); +void SPISE2P_DRV_csset(void); +void SPISE2P_DRV_csclr(void); + +unsigned int spiSe2pFree(SPISE2P_DRV *se2p); +void spiSe2pWrite(SPISE2P_DRV *se2p, SE2P_DATA *data); +void spiSe2pRead(SPISE2P_DRV *se2p, SE2P_DATA *data); + +#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT) + #define PROM_LEN 0x8000 + #define PAGE_LEN 0x20 + #define WORD_LEN 2 +#else + #define PROM_LEN 0x4000 + #define PAGE_LEN 0x40 + #define WORD_LEN 1 +#endif + +/* Óñòàíîâêà äðàéâåðà ñåðèàëüíîé EEPROM. ** +** Èíèöèàëèçàöèà SPI è ïðî÷. Òàêæå íàñòðîéêà òàéìåðà. ** +** Äðàéâåð ðàáîòàåò íà ïðåðûâàíèàõ îò òàéìåðà 2! */ +void InitSeeprom(void); + +/* Çàïèñü áëîêà â SEEPROM. Ïàðàìåòðû òàêîâû: ** +** adres - àäðåñ â åïðîìêå, êóäà ïèñàòü. ** +** adres = 0..0x8000, åñëè äëèíà ñëîâà 8 áèò ** +** adres = 0..0x4000, åñëè äëèíà ñëîâà 16 áèò ** +** buf - óêàçàòåëü íà ïàìàòü, îòêóäà ïèñàòü. ** +** size - äëèíà áëîêà â áàéòàõ. Ïî-ëþáîìó â áàéòàõ! */ +void Seeprom_write(unsigned int adres, unsigned int buf[], unsigned int size); + +/* ×òåíèå áëîêà èç SEEPROM. Ïàðàìåòðû òàêîâû: ** +** adres - àäðåñ â åïðîìêå, îòêóäà ÷èòàòü. ** +** adres = 0..0x8000, åñëè äëèíà ñëîâà 8 áèò ** +** adres = 0..0x4000, åñëè äëèíà ñëîâà 16 áèò ** +** buf - óêàçàòåëü íà ïàìàòü, êóäà ÷èòàòü. ** +** size - äëèíà áëîêà â áàéòàõ. Ïî-ëþáîìó â áàéòàõ! */ +void Seeprom_read(unsigned int adres, unsigned int buf[], unsigned int size); + +#endif + diff --git a/Source/Internal/Include/tools.h b/Source/Internal/Include/tools.h new file mode 100644 index 0000000..27df89b --- /dev/null +++ b/Source/Internal/Include/tools.h @@ -0,0 +1,7 @@ +#ifndef TOOLS_H +#define TOOLS_H + +void init_zone7(void); +void pause_us(unsigned long t); + +#endif //TOOLS_H diff --git a/Source/Internal/RS485.c b/Source/Internal/RS485.c new file mode 100644 index 0000000..0b248c9 --- /dev/null +++ b/Source/Internal/RS485.c @@ -0,0 +1,559 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */ +/**************************************************************** + RS485.ñ + **************************************************************** + * Ïðîöåäóðû ðàáîòû ñ UART * + ****************************************************************/ + +//#include "big_dsp_module.h" + + +#include "DSP2833x_Device.h" +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "RS485.h" +#include "bios_dsp.h" +#include "cntrl_adr.h" + +#include "tools.h" + +//#include "flash_tools.h" + + +RS_DATA rs_a,rs_b; + +unsigned int RS_Len[70]={0}; + +static char size_cmd15=1; + +void RS_RX_Handler(RS_DATA *rs_arr); +void RS_TX_Handler(RS_DATA *rs_arr); + +/** Îáðàáîò÷èê ïðåðûâàíèé UART - ïðèíàòî */ +interrupt void RSA_RX_Handler(void) +{ +// Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + clear_timer_rs_live(&rs_a); + RS_RX_Handler(&rs_a); + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +interrupt void RSB_RX_Handler(void) +{ +// Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + clear_timer_rs_live(&rs_b); + RS_RX_Handler(&rs_b); + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +interrupt void RSA_TX_Handler(void) +{ +// Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + clear_timer_rs_live(&rs_a); + RS_TX_Handler(&rs_a); + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +interrupt void RSB_TX_Handler(void) +{ +// Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + clear_timer_rs_live(&rs_b); + RS_TX_Handler(&rs_b); + +// Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +/** Îáðàáîò÷èê ïðåðûâàíèé UART - ïðèíàòî */ +void RS_RX_Handler(RS_DATA *rs_arr) +{ + char Rc; + char RS_BytePtr; + +// led1_on(); + + for(;;) // 'goto' ýòî íå îïåðàòîð àçûêà Ñ + { + if(!rs_arr->SciRegs->SCIRXST.bit.RXRDY) // Receiver ready flag + { + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; + rs_arr->SciRegs->SCIFFRX.bit.RXFFINTCLR=1; // Clear INT flag + return; // êñòàòè ýòî åäèíñòâåííûé âûõîä èç ïðåðûâàíèà + } + + Rc = rs_arr->SciRegs->SCIRXBUF.bit.RXDT; // ×èòàåì ñèìâîë â ëþáîì ñëó÷àå + + if(rs_arr->SciRegs->SCIRXST.bit.RXERROR) // Receiver error flag + { + rs_arr->SciRegs->SCICTL1.bit.SWRESET=0; // Reset SCI + rs_arr->SciRegs->SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset + + continue; + } + + if(rs_arr->RS_DataReady) continue; // Íå çàáðàëè äàííûå + + if (rs_arr->RS_Flag9bit==1) // äëà RS485???????? + { + // Èíèöèàëèçèðóåì ïåðåìåííûå è ôëàãè + rs_arr->RS_FlagBegin = true; // Æäåì çàãîëîâîê + rs_arr->RS_RecvLen = 0; + rs_arr->RS_FlagSkiping = false; + rs_arr->RS_HeaderCnt = 0; + rs_arr->RS_Cmd = 0; + } + + if(rs_arr->RS_FlagSkiping) continue; // Íå íàì + + if (rs_arr->RS_FlagBegin) // Çàãîëîâîê + { + if (rs_arr->RS_HeaderCnt==0) // Àäðåñ êîíòðîëëåðà èëè ñòàíäàðòíàà êîìàíäà + { + if( (Rc == CNTRL_ADDR_UNIVERSAL) || (Rc == CNTRL_ADDR && CNTRL_ADDR!=0) || ((Rc == rs_arr->addr_answer) && rs_arr->flag_LEADING) + || ((Rc == ADDR_FOR_ALL && ADDR_FOR_ALL!=0) && !rs_arr->flag_LEADING)) + + { + rs_arr->addr_recive=Rc; // çàïîìíèëè àäðåñ ïî êîòîðîìó íàñ çàïðîñèëè + rs_arr->RS_Header[rs_arr->RS_HeaderCnt++] = Rc; // Ïåðâûé áàéò + RS_SetBitMode(rs_arr,8); // ïåðåñòðîèëèñü â 8-áèò ðåæèì + } + else + { + rs_arr->RS_FlagSkiping = true; // Íå íàøåìó êîíòðîëëåðó + rs_arr->RS_FlagBegin = false; // îñòàëèñü â 9-áèò ðåæèìå +// led1_off(); + } + } + else + { + rs_arr->RS_Header[rs_arr->RS_HeaderCnt++] = Rc; // Âòîðîé áàéò è ò.ä. + + if (rs_arr->RS_HeaderCnt == 7 && rs_arr->RS_Cmd==CMD_MODBUS_16 && !rs_arr->flag_LEADING) + { + RS_Len[CMD_MODBUS_16] = (10+Rc); + } + + if (rs_arr->RS_HeaderCnt == 3) + if (rs_arr->RS_Cmd == ANS_MODBUS_4) + { + RS_Len[rs_arr->RS_Cmd] = Rc + 5; + } + + // åñëè âòîðîé áàéò - ýòî êîìàíäà + if (rs_arr->RS_HeaderCnt == 2) + { + rs_arr->RS_Cmd = Rc; + // Ïðîâåðêà äëèíû ïîñûëêè + // CMD_LOAD - ìëàäøàà íà äàííûé ìîìåíò + // CMD_STD_ANS - ñòàðøàà íà äàííûé ìîìåíò + if ((rs_arr->RS_Cmd < CMD_MODBUS_3) || (rs_arr->RS_Cmd > CMD_STD_ANS) || (RS_Len[rs_arr->RS_Cmd]<3) + || ((rs_arr->RS_Cmd == CMD_LOAD)&&(rs_arr->RS_PrevCmd != CMD_INITLOAD)) + ) + { + RS_SetBitMode(rs_arr,9); // Ïîëó÷èëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485? + rs_arr->RS_HeaderCnt = 0; // Ïîòîìó ÷òî êîìàíäà íå òà + rs_arr->RS_FlagBegin = true; + rs_arr->RS_FlagSkiping = false; + rs_arr->RS_Cmd=0; +// led1_off(); + continue; + } + if (rs_arr->RS_Cmd == CMD_LOAD) // Äëà ýòîé êîìàíäû çàãîëîâîê î÷åíü êîðîòêèé + rs_arr->RS_FlagBegin = false;// äàëüøå èäóò äàííûå + } + + if( (rs_arr->RS_HeaderCnt >= RS_Len[rs_arr->RS_Cmd]) || + (rs_arr->RS_HeaderCnt >= sizeof(rs_arr->RS_Header))) + { // Ïîëó÷èëè çàãîëîâîê + RS_SetBitMode(rs_arr,9); // Ïîëó÷èëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485? + rs_arr->RS_FlagBegin = false; + rs_arr->RS_FlagSkiping = true; + rs_arr->RS_DataReady = true; + rs_arr->RS_Cmd=0; +// led1_off(); + } } } + else // Ïîòîê äàííûõ + { + if(rs_arr->pRS_RecvPtr<(unsigned int *)Rec_Bloc_Begin || rs_arr->pRS_RecvPtr>(unsigned int *)Rec_Bloc_End) + { + rs_arr->pRS_RecvPtr = (unsigned int *)Rec_Bloc_Begin; // Íà ïðîãðàììó íàäåéñà, à ñàì íå ïëîøàé + rs_arr->pRecvPtr = (unsigned int *)Rec_Bloc_Begin; // Íà ïðîãðàììó íàäåéñà, à ñàì íå ïëîøàé + } + if(rs_arr->RS_PrevCmd != CMD_INITLOAD) continue; // Ìû çäåñü îêàçàëèñü ïî êàêîé-òî ÷óäîâèùíîé îøèáêå + + if(rs_arr->RS_DataReady) // Åñëè äàííûå â îñíîâíîì öèêëå íå çàáðàíû, + { // òî ïðîïóñêàåì ñëåäóþùóþ ïîñûëêó + rs_arr->RS_FlagSkiping = true; // Èãíîðèðóåì äî ñëåäóþùåãî çàãîëîâêà +// led1_off(); + continue; + } + RS_BytePtr = rs_arr->RS_RecvLen++ % 2; + if(RS_BytePtr) *rs_arr->pRS_RecvPtr++ |= Rc; // Ïîëó÷èëè ñëîâî + else *rs_arr->pRS_RecvPtr = Rc<<8; + + if(rs_arr->RS_Length <= rs_arr->RS_RecvLen) // Êîíåö ïîñûëêè + { + rs_arr->RS_PrevCmd = rs_arr->RS_Header[1] = CMD_LOAD; + RS_SetBitMode(rs_arr,9); // Ïîëó÷èëè âñå äàííûå ïåðåñòðîèëèñü â 9-áèò äëà RS485? + rs_arr->RS_FlagSkiping = true; // Èãíîðèðóåì äî ñëåäóþùåãî çàãîëîâêà + rs_arr->RS_DataReady = true; // Ôëàã â îñíîâíîé öèêë - äàííûå ïîëó÷åíû +// led1_off(); +} } } } + +/** Îáðàáîò÷èê ïðåðûâàíèé UART - ïîñëàíî */ +void RS_TX_Handler(RS_DATA *rs_arr) +{ + char RS_BytePtr; +// unsigned int i; + + if(rs_arr->RS_SendBlockMode == BM_CHAR32) + { + if(++rs_arr->RS_SendLen >= rs_arr->RS_SLength) + { + enableUARTInt(rs_arr); /* Çàïðåùàåì ïðåðûâàíèà ïî ïåðåäà÷å */ + } + SCI_send(rs_arr,*(rs_arr->pRS_SendPtr++)); + + if(rs_arr->RS_SendLen >= rs_arr->RS_SLength) + { + RS_Wait4OK(rs_arr); +// for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Ïàóçà äëà PC */ + RS_SetBitMode(rs_arr,9); /* Ïåðåäàëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485?*/ + RS_Line_to_receive(rs_arr); /* ðåæèì ïðèåìà RS485 */ + + rs_arr->flag_TIMEOUT_to_Send=false; /* ñáðîñèëè ôëàã îæèäàíèà òàéìàóòà */ + } + } + else /* BM_PACKED */ + { + + RS_BytePtr = (rs_arr->RS_SendLen++) % 2; + if(rs_arr->RS_SendLen >= rs_arr->RS_SLength) + { + enableUARTInt(rs_arr); /* Çàïðåùàåì ïðåðûâàíèà ïî ïåðåäà÷å */ + } + if(RS_BytePtr) SCI_send(rs_arr, LOBYTE( *(rs_arr->pRS_SendPtr++) )); + else SCI_send(rs_arr, HIBYTE( *rs_arr->pRS_SendPtr )); + + if(rs_arr->RS_SendLen >= rs_arr->RS_SLength) + { + RS_Wait4OK(rs_arr); +// for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Ïàóçà äëà PC */ +// RS_SetBitMode(rs_arr,9); /* Ïåðåäàëè âñå ïåðåñòðîèëèñü â 9-áèò äëà RS485?*/ +// RS_Line_to_receive(); /* ðåæèì ïðèåìà RS485 */ + + } + } + + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; +// rs_arr->SciRegs->SCIFFTX.bit.TXINTCLR=1; // Clear INT flag +} + +/** Èíèöèàëèçàöèà ìàññèâà äëèí êîìàíä */ +void setup_arr_cmd_length() +{ + int i; + + for (i=0;i<70;i++) RS_Len[i]=i; + + RS_Len[CMD_LOAD] = 12; + RS_Len[CMD_UPLOAD] = 12; + RS_Len[CMD_RUN] = 8; + RS_Len[CMD_XFLASH] = 9; + RS_Len[CMD_TFLASH] = 16; + RS_Len[CMD_PEEK] = 8; + RS_Len[CMD_POKE] = 12; + RS_Len[CMD_INITLOAD] = 12; + RS_Len[CMD_INIT] = 5; + RS_Len[CMD_VECTOR] = size_cmd15-2; //sizeof(CMD_TO_TMS)-2; + RS_Len[CMD_STD] = size_cmd15-1; //sizeof(CMD_TO_TMS)-1; + RS_Len[CMD_IMPULSE] = 8; + RS_Len[CMD_MODBUS_3] = 8; + RS_Len[ANS_MODBUS_4] = 3+48*2+2; + RS_Len[CMD_MODBUS_6] = 8; + RS_Len[CMD_MODBUS_16] = 13; + RS_Len[CMD_MODBUS_15] = 27; + RS_Len[CMD_EXTEND] = 18; +} + +/** Íàñòðîéêà ðåæèìà ïðèåìà/ïåðåäà÷è */ +void RS_SetBitMode(RS_DATA *rs_arr,int n) +{ + if(n == 8) + { + RS_SetLineMode(rs_arr,8,'N',1); /* ðåæèì ëèíèè */ + rs_arr->RS_Flag9bit=0; + } + if(n == 9) + { + RS_SetLineMode(rs_arr,8,'N',1); /* ðåæèì ëèíèè */ + rs_arr->RS_Flag9bit=1; +} } + +/** Ïîñûëêà áëîêà áàéòîâ. + Ïîñûëàåò ìàññèâà 32-áèòíûõ öåëûõ ÷èñåë ñòàðøèå áèòû äîëæíû áûòü 0. + @precondition Ðàáîòà ô-öèè çàâèñèò îò ìàêðî RS_TRANSMIT_INTR + @param buf àäðåñ ìàññèâà + @param len êîëè÷åñòâî áàéò + @see RS_BSend, RS_TRANSMIT_INTR */ +int RS_Send(RS_DATA *rs_arr,unsigned int *pBuf,unsigned long len) +{ + unsigned int i; + for (i=0; i <= 30000; i++){} /* Ïàóçà äëà PC */ + + RS_Line_to_send(rs_arr); /* ðåæèì ïåðåäà÷è RS485 */ + + for (i=0; i <= 10000; i++){} /* Ïàóçà äëà PC */ + + rs_arr->RS_SLength = len; /* Íàñòðàèâàåì ïåðåìåííûå */ + rs_arr->pRS_SendPtr = pBuf + 1; + + rs_arr->RS_SendBlockMode = BM_CHAR32; + + RS_Wait4OK(rs_arr); /* Äîæèäàåìñà óõîäà */ + RS_SetBitMode(rs_arr,8); /* Îñòàëüíûå â 8-áèò ðåæèìå */ + + rs_arr->RS_SendLen = 1; /* Äâà áàéòà óæå ïåðåäàëè */ + if(len > 1) + { + enableUARTIntW(rs_arr); /* Ðàçðåøàåì ïðåðûâàíèà ïî ïåðåäà÷å */ + SCI_send(rs_arr, *pBuf); // Ïåðåäàåì âòîðîé áàéò ïî ïðåðûâàíèþ + } + else + { + SCI_send(rs_arr, *pBuf); // Ïåðåäàåì âòîðîé áàéò ïî ïðåðûâàíèþ + RS_Wait4OK(rs_arr); /* Äîæèäàåìñà óõîäà áåç ïðåðûâàíèà */ + for (i=0; i <= TIME_WAIT_RS_BYTE_OUT; i++){} /* Ïàóçà äëà PC */ + RS_SetBitMode(rs_arr,9); /* Îáðàòíî â 9-áèò ðåæèì */ + RS_Line_to_receive(rs_arr); /* ðåæèì ïðèåìà RS485 */ + } + return 0; +} + +// Ïîñûëêà áëîêà óïàêîâàííûõ áàéòîâ +int RS_BSend(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len) +{ + + RS_Line_to_send(rs_arr); // ðåæèì ïåðåäà÷è RS485 + + rs_arr->RS_SLength = len; // Íàñòðàèâàåì ïåðåìåííûå + rs_arr->pRS_SendPtr = pBuf; + rs_arr->RS_SendBlockMode = BM_PACKED; + + RS_Wait4OK(rs_arr); // Îæèäàåì î÷èñòêè è óõîäà ïîñëåäíåãî áàéòà + RS_SetBitMode(rs_arr,8); /* Îñòàëüíûå â 8-áèò ðåæèìå */ + + rs_arr->RS_SendLen = 1; // Îäèí áàéò óæå ïåðåäàëè + + enableUARTIntW(rs_arr); /* Ðàçðåøàåì ïðåðûâàíèà ïî ïåðåäà÷å */ + + SCI_send(rs_arr,HIBYTE(*pBuf));// Ïåðåäàåì ïåðâûé áàéò + + return 0; +} + +/** Óñòàíàâëèâàåò ñêîðîñòü îáìåíà. + @param speed ñêîðîñòü RS â áîä */ +/** Óñòàíàâëèâàåò ñêîðîñòü îáìåíà. + @param speed ñêîðîñòü RS â áîä */ +void RS_SetLineSpeed(RS_DATA *rs_arr,unsigned long speed) +{ + long SciBaud; + + SciBaud = LSPCLK/(speed*8.0); + +// if((SciBaud-(unsigned int)SciBaud)>0.5) SciBaud++; + + rs_arr->SciRegs->SCIHBAUD = HIBYTE((int)SciBaud); + rs_arr->SciRegs->SCILBAUD = LOBYTE((int)SciBaud); +} + + +/** Èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà */ +void create_uart_vars(char size_cmd15_set) +{ + size_cmd15=size_cmd15_set; + rs_a.commnumber=COM_1; + rs_b.commnumber=COM_2; +} + + + +/** Èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà */ + +void setup_uart(char commnumber, unsigned long speed_baud) +{ + volatile struct SCI_REGS *SciRegs; + RS_DATA *rs_arr; + + if(commnumber==COM_1) + { + rs_a.SciRegs = &SciaRegs; + rs_arr = &rs_a; + + EALLOW; + + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // SCITXDA - SCI-A transmit(O) + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // SCIRXDA - SCI-A receive (I) + + PieVectTable.SCIRXINTA = &RSA_RX_Handler; + PieVectTable.SCITXINTA = &RSA_TX_Handler; + PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1 + PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2 + IER |= M_INT9; // Enable CPU INT + EDIS; + } + + if(commnumber==COM_2) + { + rs_b.SciRegs = &ScibRegs; + rs_arr = &rs_b; + + EALLOW; + + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; // SCITXDB - SCI-B transmit(O) + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; // SCIRXDB - SCI-B receive (I) + + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO 34 - general purpose I/O 34 (default) + GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; // Configures the GPIO pin as an output + + PieVectTable.SCIRXINTB = &RSB_RX_Handler; + PieVectTable.SCITXINTB = &RSB_TX_Handler; + + PieCtrlRegs.PIEIER9.bit.INTx3=1; // PIE Group 9, INT3 + PieCtrlRegs.PIEIER9.bit.INTx4=1; // PIE Group 9, INT4 + IER |= M_INT9; // Enable CPU INT + EDIS; + } + + rs_arr->commnumber = commnumber; + SciRegs = rs_arr->SciRegs; + RS_SetLineMode(rs_arr,8,'N',1); + +// enable TX, RX, internal SCICLK, +// Disable RX ERR, SLEEP, TXWAKE + + SciRegs->SCIFFCT.bit.ABDCLR=1; + SciRegs->SCIFFCT.bit.CDC=0; + + SciRegs->SCICTL1.bit.RXERRINTENA=0; + SciRegs->SCICTL1.bit.SWRESET=0; + SciRegs->SCICTL1.bit.TXWAKE=0; + SciRegs->SCICTL1.bit.SLEEP=0; + SciRegs->SCICTL1.bit.TXENA=1; + SciRegs->SCICTL1.bit.RXENA=1; + + SciRegs->SCIFFTX.bit.SCIFFENA=0; // fifo off + SciRegs->SCIFFRX.bit.RXFFIL=1; // Äëèíà íàèìåíüøåé êîìàíäû + + setup_arr_cmd_length(); + RS_SetLineSpeed(rs_arr,speed_baud); // ñêîðîñòü ëèíèè + RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485 + enableUARTInt(rs_arr); // ðàçðåøåíèå ïðåðûâàíèé UART + RS_SetBitMode(rs_arr,9); + rs_arr->RS_PrevCmd = 0; // íå áûëî íèêàêèõ êîìàíä + rs_arr->flag_TIMEOUT_to_Send = 0; + rs_arr->flag_LEADING = 0; + + SciRegs->SCIFFRX.bit.RXFFINTCLR=1; // Clear INT flag + SciRegs->SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset +} + +/** Íàñòðîéêà ðåæèìà ëèíèè. + @param bit êîëè÷åñòâî áèò äàííûõ + @param parity ðåæèì ÷åòíîñòè (N,O,E,M,S) + @param stop êîëè÷åñòâî ñòîïîâûõ áèò */ +void RS_SetLineMode(RS_DATA *rs_arr, int bit, char parity, int stop) +{ + volatile struct SCI_REGS *SciRegs; +/* +SCICCR - SCI Communication Control Register +Bit Bit Name Designation Functions +2-0 SCI CHAR2-0 SCICHAR Select the character (data) length (one to eight bits). +3 ADDR/IDLE MODE ADDRIDLE_MODE The idle-line mode (0) is usually used for normal communications because the address-bit mode adds an extra bit to the frame. The idle-line mode does not add this extra bit and is compatible with RS-232 type communications. +4 LOOP BACK ENABLE LOOPBKENA This bit enables (1) the Loop Back test mode where the Tx pin is internally connected to the Rx pin. +5 PARITY ENABLE PARITYENA Enables the parity function if set to 1, or disables the parity function if cleared to 0. +6 EVEN/ODD PARITY PARITY If parity is enabled, selects odd parity if cleared to 0 or even parity if set to 1. +7 STOP BITS STOPBITS Determines the number of stop bits transmitted-one stop bit if cleared to 0 or two stop bits if set to 1. +*/ + + SciRegs = rs_arr->SciRegs; + + if(bit>0 && bit<9) SciRegs->SCICCR.bit.SCICHAR = bit-1; + + switch(parity) + { + case 'N': SciRegs->SCICCR.bit.PARITYENA = 0; + break; + case 'O': SciRegs->SCICCR.bit.PARITYENA = 1; + SciRegs->SCICCR.bit.PARITY = 0; + break; + case 'E': SciRegs->SCICCR.bit.PARITYENA = 1; + SciRegs->SCICCR.bit.PARITY = 1; + break; + } + + if (stop==1) SciRegs->SCICCR.bit.STOPBITS = 0; + if (stop==2) SciRegs->SCICCR.bit.STOPBITS = 1; + + SciRegs->SCICCR.bit.LOOPBKENA = 0; //0 + SciRegs->SCICCR.bit.ADDRIDLE_MODE = 0; +} + +void clear_timer_rs_live(RS_DATA *rs_arr) +{ + rs_arr->time_wait_rs_out=0; +} + +/* ïðîâåðêà íà æèâó÷åñòü RS */ +void test_rs_live(RS_DATA *rs_arr) +{ +/* if (rs_arr->time_wait_rs_out < RS_TIME_OUT) + rs_arr->time_wait_rs_out++; + else + { + rs_arr->time_wait_rs_out=0; + RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485 + RS_SetBitMode(rs_arr,9); +}*/ } diff --git a/Source/Internal/bios.c b/Source/Internal/bios.c new file mode 100644 index 0000000..e03ac19 --- /dev/null +++ b/Source/Internal/bios.c @@ -0,0 +1,425 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */ +/**************************************************************** + Bios.c + ************************************************************** + Îñíîâíûå êîììàíäû BIOS * + äëà ðàáîòû ñ RS232 +****************************************************************/ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "RS485.h" +#include "bios_dsp.h" +#include "crc16.h" +#include "spise2p.h" +#include "log_to_mem.h" +//#include "flash_tools.h" +//#include "spartan_tools.h" +//#include "big_dsp_module.h" + +int flag_DEBUG = false; /* Ôëàã îòëàäî÷íîãî ðåæèìà */ + + +//static unsigned int *RecvPtr; +//static int BS_LoadOK = false; /** Ôëàã óñïåøíîñòè ïðèåìà áëîêà */ + +/**********************************************************/ +/* Ïðîòîòèïû ôóíêöèé, èñïîëüçóåìûõ è îïðåäåëåííûõ â ôàéëå */ +/**********************************************************/ +//static int _getbyte(int *addr, int offs); + +unsigned int read_memory(unsigned long addr) +{ + return (*(volatile int *)(addr)); +} + +void write_memory(unsigned long addr, unsigned int data) +{ + (*(volatile int *)( addr )) = data; +} + + +/** Âîçâðàùàåò íîìåð êîììàíäû, åñëè åñòü èëè -1 åñëè òðàíçàêöèé íå áûëî */ +int get_command(RS_DATA *rs_arr) +{ + int cmd; + unsigned int crc, rcrc; + + if(rs_arr->RS_DataReady) // Äàííûå ïî RS ïðèøëè + { + rs_arr->RS_DataReady = false; + cmd = rs_arr->RS_Header[1]; // Ïðî÷èòàëè íîìåð êîìàíäû + + // Ïðîâåðàåì äëèíó êîìàíäû äëà ñ÷èòûâàíèà CRC + if((RS_Len[cmd]<3) || (RS_Len[cmd]>MAX_RECEIVE_LENGTH)) + { + RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485 + RS_SetBitMode(rs_arr,9); + return -1; + } + + if(cmd == CMD_LOAD) // Åñëè êîìàíäà çàãðóçêè + { + rs_arr->RS_PrevCmd = cmd; + return cmd; // Íåò ïðîâåðêè crc + } + else // Âñå îñòàëüíûå êîìàíäû + { + // Ñ÷èòûâàåì crc èç ïîñûëêè + crc = (rs_arr->RS_Header[RS_Len[cmd]-1] << 8) | + (rs_arr->RS_Header[RS_Len[cmd]-2]) ; + } + // Ðàññ÷èòûâàåì crc èç ïîñûëêè + rcrc = 0xffff; + rcrc = get_crc_16( rcrc, rs_arr->RS_Header, (RS_Len[cmd]-2) ); + + if(crc == rcrc) // Ïðîâåðàåì crc + { + rs_arr->RS_PrevCmd = cmd; + return cmd; + } + else + { + RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485 + RS_SetBitMode(rs_arr,9); + } } + + return -1; +} + +/** Ñòàíäàðòíûé îòâåò, áåç ïàðàìåòðîâ */ +void Answer(RS_DATA *rs_arr,int n) +{ + int crc; + + flag_DEBUG = true; // Ôëàã îòëàäî÷íîãî ðåæèìà + + rs_arr->buffer[0] = rs_arr->addr_recive; //CNTRL_ADDR; + rs_arr->buffer[1] = n; + + crc = 0xffff; + crc = get_crc_16( crc, rs_arr->buffer, 2); + + rs_arr->buffer[2] = LOBYTE(crc); + rs_arr->buffer[3] = HIBYTE(crc); + + rs_arr->buffer[4] = 0; + rs_arr->buffer[5] = 0; + RS_Send(rs_arr,rs_arr->buffer, 6); +} + +/* Âíóòðåííàà ô-öèà */ +static char _getbyte(unsigned int *addr, int32 offs) +{ + unsigned int *address; + unsigned int byte; + + address = addr + offs/2; + byte = *address; + if(offs%2) return LOBYTE(byte); + else return HIBYTE(byte); +} + + +/* íà÷àëüíûå óñòàíîâêè (íå ðàáîòàåò)*/ +void init(RS_DATA *rs_arr) +{ +/* + if(rs_arr->RS_Header[2]==3) + { + if (rs_arr->curr_baud!=57600) + { RS_SetLineSpeed(rs_arr,57600); + rs_arr->curr_baud= 57600; + } } + + if(rs_arr->RS_Header[2]==4) + { + if (rs_arr->curr_baud!=115200) + { RS_SetLineSpeed(rs_arr,115200); + rs_arr->curr_baud= 115200; + } } + + Answer(rs_arr,CMD_INIT); + rs_arr->BS_LoadOK = false; +*/ +} + +/**@name Êîììàíäû +* Êîììàíäû, âûçûâàåìûå ÷åðåç ïîñëåäîâàòåëüíûé êàíàë +*/ +//@{ + +/** Èíèöèèðîâàòü çàãðóçêó áëîêà. + Íàñòðàèâàåò ïðèåì áëîêà äàííûõ */ +void initload(RS_DATA *rs_arr) +{ + unsigned long Address; + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + rs_arr->RS_Length = rs_arr->RS_Header[9] & 0xFF; + rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[8] & 0xFF); + rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[7] & 0xFF); + rs_arr->RS_Length = (rs_arr->RS_Length<<8) | (rs_arr->RS_Header[6] & 0xFF); + + rs_arr->RS_Length += 2; + rs_arr->pRS_RecvPtr = (unsigned int *)Address; //(unsigned int *)Address; + rs_arr->pRecvPtr = (unsigned int *)Address; //(unsigned int *)Address; + + no_write = 1; + + Answer(rs_arr,CMD_INITLOAD); +} + +/** Çàãðóçêà áëîêà. + Âûçûâàåòñà ïîñëå çàãðóçêè áëîêà ÷åðåç RS */ +void load(RS_DATA *rs_arr) +{ + unsigned int rcrc, crc; + + crc = (_getbyte(rs_arr->pRecvPtr, rs_arr->RS_Length-1) << 8) + + _getbyte(rs_arr->pRecvPtr, rs_arr->RS_Length-2); + + rs_arr->RS_Header[0] = rs_arr->addr_recive; + +// CNTRL_ADDR; + rs_arr->RS_Header[1]=CMD_LOAD; + + rcrc = 0xffff; + rcrc = get_crc_16( rcrc, rs_arr->RS_Header, 2); + rcrc = get_crc_16b( rcrc, rs_arr->pRecvPtr, rs_arr->RS_Length-2); + + if(rcrc == crc) + { + Answer(rs_arr,CMD_LOAD); + rs_arr->BS_LoadOK = true; + } + else + { + rs_arr->BS_LoadOK = false; + RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485 + RS_SetBitMode(rs_arr,9); +} } + +/** Âûïîëíèòü ïðîãðàììó â ôîðìàòå Serial Boot. + @precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà + Àäðåñ ïðîãðàììû áåðåòñà èç çàãîëîâêà è + ñðàâíèâàåòñà ñ ïåðåìåííîé RecvPtr, çàïîëíàåìîé â ô-öèè load + @see load */ +void run (RS_DATA *rs_arr) +{ + return; +} + +/** Ïðî÷èòàòü à÷åéêó ïàìàòè */ +void peek(RS_DATA *rs_arr) +{ + unsigned long Address; + unsigned int Data, crc; + + flag_DEBUG = true; // Ôëàã îòëàäî÷íîãî ðåæèìà + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + if(Addressbuffer[0] = rs_arr->addr_recive; //CNTRL_ADDR; + rs_arr->buffer[1] = CMD_PEEK; + + rs_arr->buffer[2] = LOBYTE(Data); + rs_arr->buffer[3] = HIBYTE(Data); + + rs_arr->buffer[4] = LOBYTE(CpuTimer2.InterruptCount); + rs_arr->buffer[5] = HIBYTE(CpuTimer2.InterruptCount); + + crc = 0xffff; + crc = get_crc_16(crc, rs_arr->buffer, 6); + + rs_arr->buffer[6] = LOBYTE(crc); + rs_arr->buffer[7] = HIBYTE(crc); + rs_arr->buffer[8] = 0; + rs_arr->buffer[9] = 0; + + RS_Send(rs_arr,rs_arr->buffer, 10); + +} + +/** Çàïèñàòü â à÷åéêó ïàìàòè */ +void poke(RS_DATA *rs_arr) +{ + unsigned long Address; + unsigned int Data; + + Address = rs_arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Data = 0; + Data = (Data<<8) | (rs_arr->RS_Header[7] & 0xFF); + Data = (Data<<8) | (rs_arr->RS_Header[6] & 0xFF); + + if(AddressRS_Header[5] & 0xFF; + Address = (Address<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Length = rs_arr->RS_Header[9] & 0xFF; + Length = (Length<<8) | (rs_arr->RS_Header[8] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[7] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[6] & 0xFF); + + rs_arr->buffer[0] = rs_arr->addr_recive; //CNTRL_ADDR; + rs_arr->buffer[1] = CMD_UPLOAD; + + crc = 0xffff; + crc = get_crc_16( crc, rs_arr->buffer, 2); + crc = get_crc_16b( crc, (unsigned int *)Address, Length); + + RS_Send(rs_arr,rs_arr->buffer, 1); // <=2 áàéò ïî ôëàãó + + rs_arr->buffer[0] = CMD_UPLOAD; + RS_Send(rs_arr,rs_arr->buffer, 1); // <=2 áàéò ïî ôëàãó + + RS_Wait4OK(rs_arr); + RS_BSend(rs_arr,(unsigned int*)Address, Length); + RS_Wait4OK(rs_arr); + + rs_arr->buffer[0] = LOBYTE(crc); + rs_arr->buffer[1] = HIBYTE(crc); + rs_arr->buffer[2] = 0; + rs_arr->buffer[3] = 0; + RS_Send(rs_arr,rs_arr->buffer, 4+2); + +} + +/** Ïðîøèòü XILINX. + @precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà + Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è + ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load, + òàê æå ñìîòðèò ìàãè÷åñêîå ñëîâî â íà÷àëå ïðîøèâêè + @see load */ +void xflash(RS_DATA *rs_arr) +{ + return; +} + +/** Ïðîøèòü TMS. + @precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà + Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è + ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load + @see load */ +void tflash(RS_DATA *rs_arr) +{ +// volatile unsigned long Address1,Address2; +// volatile unsigned long Length, LengthW; +/* + if(!rs_arr->BS_LoadOK) + { + RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485 + RS_SetBitMode(rs_arr,9); + return; + } + + Address1 = rs_arr->RS_Header[5] & 0xFF; + Address1 = (Address1<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Address2 = rs_arr->RS_Header[9] & 0xFF; + Address2 = (Address2<<8) | (rs_arr->RS_Header[8] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[7] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[6] & 0xFF); + + Length = rs_arr->RS_Header[13] & 0xFF; + Length = (Length<<8) | (rs_arr->RS_Header[12] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[11] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[10] & 0xFF); + + LengthW = Length/2; + if (LengthW*2 0x180000) || ((Address2+LengthW) > 0x180000) ) + { + RS_Line_to_receive(rs_arr); // ðåæèì ïðèåìà RS485 + RS_SetBitMode(rs_arr,9); + return; + } + + run_flash_data(Address1,Address2, LengthW ); + + Answer(rs_arr,CMD_TFLASH); +*/ + return; +} + +/** Ïðîøèòü TMS. + @precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà + Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è + ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load + @see load */ +void extendbios(RS_DATA *rs_arr) +{ + volatile unsigned long Address1,Address2,Length; + unsigned int code; + + Address1 = rs_arr->RS_Header[5] & 0xFF; + Address1 = (Address1<<8) | (rs_arr->RS_Header[4] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[3] & 0xFF); + Address1 = (Address1<<8) | (rs_arr->RS_Header[2] & 0xFF); + + Address2 = rs_arr->RS_Header[9] & 0xFF; + Address2 = (Address2<<8) | (rs_arr->RS_Header[8] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[7] & 0xFF); + Address2 = (Address2<<8) | (rs_arr->RS_Header[6] & 0xFF); + + Length = rs_arr->RS_Header[13] & 0xFF; + Length = (Length<<8) | (rs_arr->RS_Header[12] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[11] & 0xFF); + Length = (Length<<8) | (rs_arr->RS_Header[10] & 0xFF); + + code=rs_arr->RS_Header[14] & 0xFF; + + switch ( code ) + { + // Ïðîøèâàåì EPROM Èç RAM + case 4: Seeprom_write(Address1,(unsigned int*)Address2,Length); + break; + // ×èòàåì èç EPROM â RAM + case 5: Seeprom_read(Address1,(unsigned int*)Address2,Length); + break; + + default: + return; + } + + Answer(rs_arr,CMD_EXTEND); + return; +} + +//@} diff --git a/Source/Internal/cntrl_adr.c b/Source/Internal/cntrl_adr.c new file mode 100644 index 0000000..2f29cdb --- /dev/null +++ b/Source/Internal/cntrl_adr.c @@ -0,0 +1,43 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */ +/**************************************************************** + cntrl_adr.c + **************************************************************** + * Àäðåñ êîíòðîëëåðà * + ****************************************************************/ + +#include "cntrl_adr.h" + +#define ADDR_FOR_ALL_DEF 10 +#define ADDR_ANSWER_DEF 0x33 +#define ADDR_TERMINAL_DEF 11 +#define ADDR_UNIVERSAL_DEF 10 + + +/** Óñòàíîâêà àäðåñà êîíòðîëëåðà äëà ïîñûëêè âñåì ÀÈÍàì */ +int ADDR_FOR_ALL = ADDR_FOR_ALL_DEF; + +/** Óñòàíîâêà àäðåñà êîíòðîëëåðà äëà ïîñûëêè îòâåòà */ +const int ADDR_ANSWER = ADDR_ANSWER_DEF; + +/** Óñòàíîâêà àäðåñà òåðìèíàëà äëà ïîñûëêè îòâåòà */ +const int ADDR_TERMINAL = ADDR_TERMINAL_DEF; + +/* Óíèâåðñàëüíûé àäðåñ êîíòðîëëåðà */ +const int CNTRL_ADDR_UNIVERSAL=ADDR_UNIVERSAL_DEF; + +/* Àäðåñ êîíòðîëëåðà */ +int CNTRL_ADDR=1; + +int cntr_addr_c; +int cntr_addr_c_all; + +/** Óñòàíîâêà àäðåñà êîíòðîëëåðà äëà ïðîøèâêè */ +void set_cntrl_addr (int cntrl_addr,int cntrl_addr_for_all) +{ + CNTRL_ADDR = cntrl_addr; + ADDR_FOR_ALL = cntrl_addr_for_all; +} + diff --git a/Source/Internal/crc16.c b/Source/Internal/crc16.c new file mode 100644 index 0000000..756fa01 --- /dev/null +++ b/Source/Internal/crc16.c @@ -0,0 +1,196 @@ +#include "crc16.h" +#define MAKE_TABS 0 /* Builds tables below */ +#define FAST_CRC 1 /* If fast CRC should be used */ +#define ONLY_CRC16 1 + +#define Poln 0xA001 + + +#if FAST_CRC & !MAKE_TABS + +#if !ONLY_CRC16 + +static WORD crc_ccitt_tab[] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 +}; +#endif + +WORD crc_16_tab[] = { + 0x0000, 0xc0c1, 0xc181, 0x0140, 0xc301, 0x03c0, 0x0280, 0xc241, + 0xc601, 0x06c0, 0x0780, 0xc741, 0x0500, 0xc5c1, 0xc481, 0x0440, + 0xcc01, 0x0cc0, 0x0d80, 0xcd41, 0x0f00, 0xcfc1, 0xce81, 0x0e40, + 0x0a00, 0xcac1, 0xcb81, 0x0b40, 0xc901, 0x09c0, 0x0880, 0xc841, + 0xd801, 0x18c0, 0x1980, 0xd941, 0x1b00, 0xdbc1, 0xda81, 0x1a40, + 0x1e00, 0xdec1, 0xdf81, 0x1f40, 0xdd01, 0x1dc0, 0x1c80, 0xdc41, + 0x1400, 0xd4c1, 0xd581, 0x1540, 0xd701, 0x17c0, 0x1680, 0xd641, + 0xd201, 0x12c0, 0x1380, 0xd341, 0x1100, 0xd1c1, 0xd081, 0x1040, + 0xf001, 0x30c0, 0x3180, 0xf141, 0x3300, 0xf3c1, 0xf281, 0x3240, + 0x3600, 0xf6c1, 0xf781, 0x3740, 0xf501, 0x35c0, 0x3480, 0xf441, + 0x3c00, 0xfcc1, 0xfd81, 0x3d40, 0xff01, 0x3fc0, 0x3e80, 0xfe41, + 0xfa01, 0x3ac0, 0x3b80, 0xfb41, 0x3900, 0xf9c1, 0xf881, 0x3840, + 0x2800, 0xe8c1, 0xe981, 0x2940, 0xeb01, 0x2bc0, 0x2a80, 0xea41, + 0xee01, 0x2ec0, 0x2f80, 0xef41, 0x2d00, 0xedc1, 0xec81, 0x2c40, + 0xe401, 0x24c0, 0x2580, 0xe541, 0x2700, 0xe7c1, 0xe681, 0x2640, + 0x2200, 0xe2c1, 0xe381, 0x2340, 0xe101, 0x21c0, 0x2080, 0xe041, + 0xa001, 0x60c0, 0x6180, 0xa141, 0x6300, 0xa3c1, 0xa281, 0x6240, + 0x6600, 0xa6c1, 0xa781, 0x6740, 0xa501, 0x65c0, 0x6480, 0xa441, + 0x6c00, 0xacc1, 0xad81, 0x6d40, 0xaf01, 0x6fc0, 0x6e80, 0xae41, + 0xaa01, 0x6ac0, 0x6b80, 0xab41, 0x6900, 0xa9c1, 0xa881, 0x6840, + 0x7800, 0xb8c1, 0xb981, 0x7940, 0xbb01, 0x7bc0, 0x7a80, 0xba41, + 0xbe01, 0x7ec0, 0x7f80, 0xbf41, 0x7d00, 0xbdc1, 0xbc81, 0x7c40, + 0xb401, 0x74c0, 0x7580, 0xb541, 0x7700, 0xb7c1, 0xb681, 0x7640, + 0x7200, 0xb2c1, 0xb381, 0x7340, 0xb101, 0x71c0, 0x7080, 0xb041, + 0x5000, 0x90c1, 0x9181, 0x5140, 0x9301, 0x53c0, 0x5280, 0x9241, + 0x9601, 0x56c0, 0x5780, 0x9741, 0x5500, 0x95c1, 0x9481, 0x5440, + 0x9c01, 0x5cc0, 0x5d80, 0x9d41, 0x5f00, 0x9fc1, 0x9e81, 0x5e40, + 0x5a00, 0x9ac1, 0x9b81, 0x5b40, 0x9901, 0x59c0, 0x5880, 0x9841, + 0x8801, 0x48c0, 0x4980, 0x8941, 0x4b00, 0x8bc1, 0x8a81, 0x4a40, + 0x4e00, 0x8ec1, 0x8f81, 0x4f40, 0x8d01, 0x4dc0, 0x4c80, 0x8c41, + 0x4400, 0x84c1, 0x8581, 0x4540, 0x8701, 0x47c0, 0x4680, 0x8641, + 0x8201, 0x42c0, 0x4380, 0x8341, 0x4100, 0x81c1, 0x8081, 0x4040 +}; +#endif + + +#if !ONLY_CRC16 + +/* CRC-CCITT is based on the polynomial x^16 + x^12 + x^5 + 1. Bits */ +/* are sent MSB to LSB. */ +unsigned int get_crc_ccitt(unsigned int crc,unsigned int *buf,unsigned long size ) +{ +#if !(FAST_CRC & !MAKE_TABS) + register int i; +#endif + + while (size--) { +#if FAST_CRC & !MAKE_TABS + crc = (crc << 8) ^ crc_ccitt_tab[ (crc >> 8) ^ *buf++ ]; +#else + crc ^= (WORD)(*buf++) << 8; + for (i = 0; i < 8; i++) { + if (crc & 0x8000) + crc = (crc << 1) ^ 0x1021; + else + crc <<= 1; + } +#endif + } return crc; +} +#endif + + +/* CRC-16 is based on the polynomial x^16 + x^15 + x^2 + 1. Bits are */ +/* sent LSB to MSB. */ +unsigned int get_crc_16(unsigned int crc,unsigned int *buf,unsigned long size ) +{ +#if !(FAST_CRC & !MAKE_TABS) + register unsigned int i; + register unsigned int ch; +#endif + + while (size--) { +#if FAST_CRC & !MAKE_TABS + + crc = (crc >> 8) ^ crc_16_tab[ (crc ^ *buf++) & 0xff ]; + crc = crc & 0xffff; +#else + ch = *buf++; + for (i = 0; i < 8; i++) { + if ((crc ^ ch) & 1) + crc = (crc >> 1) ^ 0xa001; + else + crc >>= 1; + ch >>= 1; + } +#endif + } return (crc & 0xffff); +} + + + +unsigned int get_crc_16b(unsigned int crc,unsigned int *buf,unsigned long size ) +{ + +unsigned int x, dword, byte; +unsigned long i; + + + + for (i = 0; i < size; i++) + { + x = i % 2; + + dword = buf[i/2]; +// dword = *buf; + + + if (x == 0) + { + byte = ((dword >> 8)&0xFF); + } + + if (x == 1) + { + byte = (dword & 0xFF); + } + + crc = (crc >> 8) ^ crc_16_tab[ (crc ^ (byte) ) & 0xff ]; + crc = crc & 0xffff; + +// crc = crc + ((byte) & 0xff); + + } + + return (crc & 0xffff); +} + +int get_crc16(unsigned int *buf, int size ) +{ + int crc16,i,j; + + crc16=0xFFFF; + for(i=0;i>1)^Poln; + else crc16=crc16>>1; + + crc16=crc16^((buf[i]>>8)&0xFF); + for (j=0;j<8;j++) + if(crc16&1) crc16=(crc16>>1)^Poln; + else crc16=crc16>>1; + } + return crc16; +} diff --git a/Source/Internal/ecan.c b/Source/Internal/ecan.c new file mode 100644 index 0000000..82b901b --- /dev/null +++ b/Source/Internal/ecan.c @@ -0,0 +1,259 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "filter_bat2.h" +#include "measure.h" +#include "package.h" // DSP281x Headerfile Include File + +#include "ecan.h" // DSP281x Headerfile Include File +#include "tools.h" // DSP281x Headerfile Include File + +#include "RS485.h" +#include "message.h" +#include "peripher.h" + + +// Prototype statements for functions found within this file. +interrupt void CANa_handler(void); +interrupt void CANa_reset_err(void); + +// Global variable for this example +Uint32 ErrorCount; +Uint32 MessageReceivedCount; +Uint32 MessageTransivedCount=0; + +Uint32 TestMbox1 = 0; +Uint32 TestMbox2 = 0; +Uint32 TestMbox3 = 0; + +int CanTimeOutErrorTR = 0; + +int wait=0; + +void InitCan(int Port, int DevNum) +{ + struct ECAN_REGS ECanShadow; + + volatile struct ECAN_REGS * ECanRegs; + volatile struct ECAN_MBOXES * ECanMboxes; + volatile struct MOTO_REGS * ECanMOTORegs; + + long id = 0x80BA0000; + + DevNum--; + if(DevNum<0)DevNum=0; + if(DevNum>15)DevNum=15; + +// Configure CAN pins using GPIO regs here + EALLOW; + + ECanRegs = &ECanaRegs; + ECanMboxes = &ECanaMboxes; + ECanMOTORegs = &ECanaMOTORegs; + + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; + +// Configure the eCAN RX and TX pins for eCAN transmissions + ECanRegs->CANTIOC.all = 8; // only 3rd bit, TXFUNC, is significant + ECanRegs->CANRIOC.all = 8; // only 3rd bit, RXFUNC, is significant + +// Specify that 8 bits will be sent/received + ECanMboxes->MBOX0.MSGCTRL.all = 0x00000008; + ECanMboxes->MBOX1.MSGCTRL.all = 0x00000008; + +// Disable all Mailboxes +// Required before writing the MSGIDs + ECanRegs->CANME.all = 0; + +// çàäàåì àäðåñ 0 àùèêa íà ïåðåäà÷ó + ECanMboxes->MBOX0.MSGID.all = id + 0x10 + DevNum; + +// çàäàåì àäðåñ 1 àùèêa íà ïðèåì + ECanMboxes->MBOX1.MSGID.all = id + DevNum; //ïîìåíàòü!!!! 1 è 0!!! + +// çàäàåì ðåæèìû ðàáîòû àùèêa 0 íà ïåðåäà÷ó, îñòàëüíûå íà ïðèåì + ECanRegs->CANMD.all = 0xFFFFFFFE; + +// âûáèðàåì òîëüêî 2 àùèêa äëà ðàáîòû, îñòàëüíûå çàïðåùàåì + ECanRegs->CANME.all = 0x00000003; + +// Clear all TAn bits + ECanRegs->CANTA.all = 0xFFFFFFFF; +// Clear all RMPn bits + ECanRegs->CANRMP.all = 0xFFFFFFFF; +// Clear all interrupt flag bits + ECanRegs->CANGIF0.all = 0xFFFFFFFF; + ECanRegs->CANGIF1.all = 0xFFFFFFFF; +// Clear all error and status bits + ECanRegs->CANES.all=0xffffffff; + +// Request permission to change the configuration registers + ECanShadow.CANMC.all = 0; + ECanShadow.CANMC.bit.MBCC = 1; // Mailbox timestamp counter clear bit + ECanShadow.CANMC.bit.TCC = 1; // Time stamp counter MSB clear bit + ECanShadow.CANMC.bit.SCB = 1; // eCAN mode (reqd to access 32 mailboxes) + ECanShadow.CANMC.bit.WUBA = 1; // Wake up on bus activity + ECanShadow.CANMC.bit.ABO = 1; // Auto bus on + ECanShadow.CANMC.bit.CCR = 1; +// ECanShadow.CANMC.bit.STM = 1; // self-test loop-back + ECanRegs->CANMC.all = ECanShadow.CANMC.all; + while(!ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be set.. + +// íàñòðèâàåì ñêîðîñòü CAN + ECanShadow.CANBTC.all = ECanRegs->CANBTC.all; + ECanShadow.CANBTC.bit.SJWREG=1; + + ECanShadow.CANBTC.bit.BRPREG = (CLKMULT * 3) - 1; + ECanShadow.CANBTC.bit.TSEG1REG = 15; + ECanShadow.CANBTC.bit.TSEG2REG = 2; + + ECanRegs->CANBTC.all = ECanShadow.CANBTC.all; + ECanShadow.CANMC.bit.CCR = 0; // Set CCR = 0 + ECanRegs->CANMC.all = ECanShadow.CANMC.all; + while(ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be cleared.. + +// çàäàåì òàéìàóòû äëà îæèäàíèà îòïðàâêè ïîëó÷åíèà ïîñûëêè + ECanMOTORegs->MOTO0 = 550000; + ECanMOTORegs->MOTO1 = 550000; + + ECanRegs->CANTOC.all = 1; + ECanRegs->CANTOS.all = 0; // clear all time-out flags + ECanRegs->CANTSC = 0; // clear time-out counter + + ECanShadow.CANGIM.all = 0; + + ECanRegs->CANMIM.all = 2; // Enable interrupts of box 1 + ECanRegs->CANMIL.all = 0x00000000; // All mailbox interrupts are generated on interrupt line 0. + ECanShadow.CANGIM.bit.I0EN = 1; + + ECanShadow.CANGIM.bit.MTOM = 1; + ECanShadow.CANGIM.bit.I1EN = 1; + ECanShadow.CANGIM.bit.GIL = 1; + ECanRegs->CANGIM.all = ECanShadow.CANGIM.all; + + PieVectTable.ECAN0INTA = &CANa_handler; + PieCtrlRegs.PIEIER9.bit.INTx5=1; // PIE Group 9, INT6 + PieVectTable.ECAN1INTA = &CANa_reset_err; + PieCtrlRegs.PIEIER9.bit.INTx6=1; // PIE Group 9, INT6 + + IER |= M_INT9; // Enable CPU INT + EDIS; + +// çàâåðøèëè íàñòðîéêó CAN àùèêîâ + + MessageReceivedCount = 0; + ErrorCount = 0; + CanTimeOutErrorTR=0; + MessageTransivedCount=0; +} + +void CAN_send(int Port, int data[], int Addr) +{ + unsigned long hiword,loword; + volatile struct ECAN_REGS * ECanRegs; + volatile struct ECAN_MBOXES * ECanMboxes; + + ECanRegs = &ECanaRegs; + ECanMboxes = &ECanaMboxes; + + if(wait) + if(!(ECanRegs->CANTA.all & 1)) + if(!(ECanRegs->CANAA.all & 1)) + return; + + ECanRegs->CANTA.all = 1; + ECanRegs->CANAA.all = 1; + + hiword= ((((Uint32) Addr ) & 0xffff)<<16)| 0xE0000000 | + ((((Uint32)data[Addr ]) & 0xffff) ); + loword= ((((Uint32)data[Addr+1]) & 0xffff)<<16)| + ((((Uint32)data[Addr+2]) & 0xffff) ); + + ECanMboxes->MBOX0.MDH.all = hiword; + ECanMboxes->MBOX0.MDL.all = loword; + + EALLOW; + ECanRegs->CANTSC = 0; // clear time-out counter + EDIS; + + ECanRegs->CANTRS.all = 1; // çàïóñòèòü ïåðåäà÷ó + + wait=1; + led1_toggle(); +} + + +void Handlai(volatile struct ECAN_MBOXES * ECanMboxes) +{ + unsigned int adr; + unsigned int bit[3]; + unsigned long hiword,loword; + int Data[3]; + + Lonely=0; + + hiword = ECanMboxes->MBOX1.MDH.all; + loword = ECanMboxes->MBOX1.MDL.all; + + adr = (hiword >> 16); + + bit[0] = adr & 0x8000; + bit[1] = adr & 0x4000; + bit[2] = adr & 0x2000; + + adr &= 0x1fff; + + Data[0] = (hiword ) & 0xffff; + Data[1] = (loword>>16) & 0xffff; + Data[2] = (loword ) & 0xffff; + + if(bit[0]) if(adr < ANSWER_LEN) modbus[adr] = Data[0]; adr++; + if(bit[1]) if(adr < ANSWER_LEN) modbus[adr] = Data[1]; adr++; + if(bit[2]) if(adr < ANSWER_LEN) modbus[adr] = Data[2]; + + led2_toggle(); +} + +interrupt void CANa_handler(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + Handlai(&ECanaMboxes); + + ECanaRegs.CANRMP.all = 2; + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +interrupt void CANa_reset_err(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + EINT; + + ECanaRegs.CANTRR.all = 1; + CanTimeOutErrorTR++; + + PieCtrlRegs.PIEACK.bit.ACK9 |= 1; + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; +} + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/Source/Internal/filter_bat2.c b/Source/Internal/filter_bat2.c new file mode 100644 index 0000000..a577836 --- /dev/null +++ b/Source/Internal/filter_bat2.c @@ -0,0 +1,19 @@ +#include "filter_bat2.h" + +float filterbat(FILTERBAT *b, float InpVarCurr) +{ + float y; + + y = (b->k_0 * (InpVarCurr + (b->i_0*2) + b->i_1)) + + (b->k_1 * b->u_0) + (b->k_2 * b->u_1); + + b->u_1=b->u_0; + b->u_0=y; + b->i_1=b->i_0; + b->i_0=InpVarCurr; + + return y; +} + + + diff --git a/Source/Internal/kanal.c b/Source/Internal/kanal.c new file mode 100644 index 0000000..c719f08 --- /dev/null +++ b/Source/Internal/kanal.c @@ -0,0 +1,183 @@ +#include "DSP2833x_Device.h" // DSP281x Headerfile Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" +#include "filter_bat2.h" +#include "measure.h" + +#include "RS485.h" +#include "message.h" +#include "kanal.h" +#include "pulto.h" +#include "package.h" +#include "tools.h" + +#include "peripher.h" + +int digits[16] = {63,6,91,79,102,109,125,7,127,111,64,0,0,0,121,0}; +int readr[5] = {0x08,0x0C,0x10,0x00,0x04}; + +void DCLK(int x) +{ + if(x) GpioDataRegs.GPASET.bit.GPIO6=1; + else GpioDataRegs.GPACLEAR.bit.GPIO6=1; +} + +void DOUT(int x) +{ + if(x) GpioDataRegs.GPASET.bit.GPIO8=1; + else GpioDataRegs.GPACLEAR.bit.GPIO8=1; +} + +#if CLKMULT==1 +#define POWS0 0L +#define POWS1 10L +#endif +#if CLKMULT==2 +#define POWS0 0L +#define POWS1 30L +#endif +#if CLKMULT==3 +#define POWS0 1L +#define POWS1 50L +#endif +#if CLKMULT==4 +#define POWS0 2L +#define POWS1 60L +#endif +#if CLKMULT==5 +#define POWS0 4L +#define POWS1 80L +#endif + +void RESET() +{ + DCLK(0); +#if POWS1>0 + DSP28x_usDelay(POWS1); +#endif + DOUT(1); +#if POWS1>0 + DSP28x_usDelay(POWS1); +#endif + DOUT(0); +#if POWS1>0 + DSP28x_usDelay(POWS1); +#endif +} + +void SENDBIT(int x) +{ + DOUT(x); DCLK(1); +#if POWS0>0 + DSP28x_usDelay(POWS0); +#endif + DOUT(0); + DSP28x_usDelay(POWS0+1); + DCLK(0); +#if POWS1>0 + DSP28x_usDelay(POWS1); +#endif +} + +void kanal_Send(int adr, long dat, int dot) +{ + long Word,data,aliq_part,dg[4]; + int i,j,bit,byt,addr,sgn=0,punkt=0,aliq_len=0,full_len, isdot=0; + + if(adr>1) // Ëàìïî÷êè + { + Word =dat; + } + + else + + { + if(dat<0) sgn=1; + data = labs(dat); + + if(dot>=0 && dot<4) isdot = 1; + else dot=0; + + aliq_part = data; + for(i=0;i0) + { + aliq_len++; dat/=10; + } + + dat = data; + + full_len = aliq_len+sgn; + if(full_len==0) full_len=1; + full_len += dot; + + for(i=0; i<(full_len-4);i++) + { + dot--; dat/=10; + } + if(dot<0) dot=0; + punkt = 1<0;i--) + { + if((dg[i]==0)&&(i!=dot)) + dg[i]=0xF; // Ýòî çíà÷èò ïóñòî + else break; + } + + if(sgn) + for(i=1;i<4;i++) + { + if( (dg[i]==0xF)||(i==3)) + { + dg[i]=0xA; // Ýòî çíà÷èò ìèíóñ + break; + } } + + for(i=0;i<4;i++) + { + dg[i] = digits[dg[i]]; + if((punkt>>i)&1) dg[i]+= 128; + + } + + Word = ((dg[0] ) & 0x000000FF) | ((dg[1]<<8 ) & 0x0000FF00) | + ((dg[2]<<16) & 0x00FF0000) | ((dg[3]<<24) & 0xFF000000); + } + + addr = readr[adr]; + + for (i=0;i<4;i++) + { + if(addr>0x10) break; + + for (j=0;j<8;j++) + { + bit = Word & 1; Word >>= 1; + SENDBIT(bit); + } + + byt = addr; + for (j=0;j<6;j++) + { + bit = byt & 1; byt >>= 1; + SENDBIT(bit); + } + addr++; + + RESET(); + } +} diff --git a/Source/Internal/log_to_mem.c b/Source/Internal/log_to_mem.c new file mode 100644 index 0000000..1b0a255 --- /dev/null +++ b/Source/Internal/log_to_mem.c @@ -0,0 +1,34 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */ +/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2001ã. */ +/****************************************************************/ +/* log_to_mem.c + **************************************************************** + * Çàïèñü ëîãîâ â ïàìyòü * + ****************************************************************/ + +#include "log_to_mem.h" + +int no_write = 0, + never_write = 0; // Ôëàãè, ÷òîáû íå ïèñàòü (åñëè ÷òî) + +#pragma DATA_SECTION(logs_block,".logg"); +unsigned int logs_block[0xFA00]; + +LOG Log; +unsigned int flog=0; + +// Î÷èùåíèå ïàìàòè, ãäå ëîãè ëåæàò +void clear_mem() +{ + unsigned long i; + + Log.Start = LOG_PAGE_START; + Log.Finis = LOG_PAGE_START + LOG_PAGE_LEN; + Log.Adres = Log.Start; + Log.Circl = 0; + + for (i=Log.Start; i=Owncount) + { + rscount=0; + SendCommandModbus4(&rs_b); + } + + for(i=0;i<2;i++) + if(++cancount[i] >= Cancount[i]) + if(Cancount[i] && cancount[0]) + { + cancount[i] = 0; + + while(1) + { + if(cancell[i] >= 0x80) cancell[i]=0; + mask = Maska[i][cancell[i]/16] >> (cancell[i]%16); + if(!mask) cancell[i] = (cancell[i] + 0x10) & 0xFFF0; + else + { + while(!(mask & 1)) + { + cancell[i]++; mask >>= 1; + } + break; + } } + CAN_send(0,modbus,cancell[i]); + cancell[i]+=3; + } } + + if(cDefParam) + { + cDefParam=0; + Default_params(); + } + + if(cSaveParam) + { + cSaveParam=0; + Save_params(); + } + + if(cLoadParam) + { + cLoadParam=0; + Load_params(); + } + + if(cKoefCalc) + { + cKoefCalc=0; + calc_sensor_koef(); + } + + get_Buttons(); + + if(Desk==dsk_COMM) + { + if(!bTermoCal & presbyt) cSaveParam=1; + presbyt = bTermoCal; + } + + if(Desk==dsk_LOAD) + { + if(cUMPstart & !preCstart) + { + set_START_DPTB(); set_RES_OUT_2(); + IMPowse = READY_FREQ; + } + preCstart = cUMPstart; + + if(cUMPreset & !preCstop) + { + set_STOP_DPTB(); clear_RES_OUT_2(); + IMPowse = READY_FREQ; + } + preCstop = cUMPreset; + + if(!IMPowse) { clear_START_DPTB(); clear_STOP_DPTB(); } + } + + for(i=0;i<2;i++) + { + if(i) rs = &rs_a; + else rs = &rs_b; + + j = get_command(rs); + + if(j!=-1) + { + Lonely=0; + led2_toggle(); + switch(j) + { + case CMD_INIT: init(rs); break; // íà÷àëüíûå óñòàíîâêè + case CMD_INITLOAD: initload(rs); break; // íàñòðîéêà çàãðóçêè + case CMD_RUN: run(rs); break; // çàãðóçèòü áëîê + case CMD_LOAD: load(rs); break; // çàãðóçèòü áëîê + case CMD_PEEK: peek(rs); break; // ïðî÷èòàòü à÷åéêó ïàìàòè + case CMD_POKE: poke(rs); break; // çàïèñàòü â à÷åéêó ïàìàòè + case CMD_UPLOAD: upload(rs); break; // ïåðåäàòü áëîê ïàìàòè + case CMD_EXTEND: extendbios(rs); break; // ðàñøèðåííûå êîìàíäû äëà áèîñà + + case CMD_TFLASH: tflash(rs); break; // ïðîøèòü TMS + + case CMD_MODBUS_3: ReceiveCommandModbus3(rs); break; + case CMD_MODBUS_6: ReceiveCommandModbus6(rs); break; + case ANS_MODBUS_4: ReceiveAnswerModbus4(rs); break; + + + default: break; +} } } } } + diff --git a/Source/Internal/measure.c b/Source/Internal/measure.c new file mode 100644 index 0000000..ddb0f47 --- /dev/null +++ b/Source/Internal/measure.c @@ -0,0 +1,841 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" +#include "filter_bat2.h" +#include "package.h" + +#include "measure.h" +#include "package.h" + +#include "peripher.h" +#include "ADC.h" +#include "DAC.h" + +#include "RS485.h" +#include "message.h" +#include "log_to_mem.h" + +#include // Ýòî ÷òîáû ìåðèòü àìïëèòóäó! sqrt áåç ýòîãî áóäåò êðèâ!!! + +unsigned int CanPowse=CANPOWSE,CanGO=0; + +unsigned int Maska[2][8]; + +int READY=0; // Âñå çàãðóçèëîñ + +int TPL_CANS=0; // Êîëè÷åñòâî òåìïåðàòóðíûõ êàíàëîâ +int tpl_cans=0; // Êîëè÷åñòâî òåìïåðàòóðíûõ äàò÷èêîâ +int cal_addr=0; // Íà÷àëî êàëèáðîâî÷íûõ äàò÷èêîâ +int pow_addr=0; // Íà÷àëî äàò÷èêîâ íàïðàæåíèà\òîêà + +int period_ready, period_blink; + +FLAG chk,sig; +unsigned int time_1_5sec, time_5msec, time_3sec, time_5sec; + +unsigned int low_count[2] = {0,0}; +unsigned int err_count[6]; +int lev_count[6]; +float lev_quadr[6]; +float zer_count[4]; + +int sens_type[24]; +int sens_pair[24]; +unsigned int din_count[32]; + +int ext_temp[8]; +int ext_diag[8]; + +unsigned int Caliber_time = 0; +int Curr_Edge; +ERROR okay; + +float powK[] = +{ + 0.127, // ïèòàíèå 380 + 0.127, // ïèòàíèå 380 + + 1.000, // òîê + 1.000, // íàïðàæåíèå + + 0.0076, // ïèòàíèå 31 + 0.0076, // ïèòàíèå 24 + 0.0076, // ïèòàíèå 24 + 0.0076, // ïèòàíèå 15 + 1.0000, // òåðìîäàò÷èê ìåëêîñõåìà +}; + +FILTERBAT def_FILTERBAT = DEF_FILTERBAT; +FILTERBAT adc_filter[20+4]; // ìàêñ.TPL*2 + 4 êàëèáð +FILTERBAT out_filter[20+4]; // ìàêñ.TPL*2 + 4 íàïðàæ +FILTERBAT zer_filter[4]; // 4 íàïðàæ + +long sens_count[24+4]; + +float K100,K_50; +float K_T1,K_T2; + +interrupt void cpu_timer1_isr_SENS(void); + +/********************************************************************/ +/* Ðàñ÷åò ìîäóëà òîêà èç ïîêàçàíèé äâóõ ôàç */ +/********************************************************************/ +float im_calc(float ia,float ib) +{ + float isa,isb; + + isa = - 1.5 * (ia + ib); + isb = COSPi6 * (ia - ib); + return (2*sqrt(isa*isa+isb*isb)/3); +} + +void calc_sensor_koef() +{ + int i; + float K; + + if(TermoRS) + { + K100 = 129.0/(K150_D - K100_D); + K_50 = 261.8/(K150_D - K100_D); + K_T1 = 129.0/(K150_1 - K100_1); + K_T2 = 129.0/(K150_2 - K100_2); + } + + if(TermoAD) + { + K_T1 = 100.0/(K400_1 - K300_1); + K_T2 = 100.0/(K400_2 - K300_2); + } + +// if(Kurrent) + for(i=0;i<4;i++) + { + K = Caliber[i]; + if(sens_type[i]==CURRENT) K/=1000.0; + else K/=10000.0; + powK[i] = K; +} } + +interrupt void cpu_timer1_isr_SENS(void) +{ + static unsigned int + count_blink=0, count_bright=0, count_mode, + blink_over, blink_alarm, work_lamp, heat_lamp, power_lamp; + static int preTest; + + int TST; + +#define err_lamp work_lamp // ýòî äëà øêàïà, +#define alm_lamp heat_lamp // ÷òîá áûëî ïîíàòíåå + + EALLOW; + CpuTimer1.InterruptCount++; + IER |= M_INT13; // Set "global" priority + IER &= MINT13; // Set "global" priority + EINT; + EDIS; // This is needed to disable write to EALLOW protected registers + + if(!cReset) ServiceDog(); + + if(++CanPowse >= CANPOWSE) + { + CanPowse = 0; + CanGO = 1; + } + + TST = cTestLamp|bTestLamp; + + if(!sig.bit.Error|TST) toggle_READY(); + else clear_READY(); + + if(Desk==dsk_LOAD) + { + Load_runner(); + return; + } + + if(++count_bright == maximum_bright) + { + count_bright = 0 ; + + if( ((Desk==dsk_SHKF) && power_lamp) || + ((Desk==dsk_COMM) && heat_lamp) ) set_RES_OUT_1(); + else clear_RES_OUT_1(); + + if(work_lamp) set_LED_OUT_1(); // Îíà æå err_lamp äëà øêàïà + else clear_LED_OUT_1(); + if(heat_lamp) set_LED_OUT_2(); // Îíà æå alm_lamp äëà øêàïà + else clear_LED_OUT_2(); + } + + if(!TST) + if(count_bright == Brightness) + { + clear_LED_OUT_1(); + clear_LED_OUT_2(); + clear_RES_OUT_1(); + } + + if(TST & !preTest) + { + count_blink = BLINK_TIME; + count_mode = 0; + } + preTest = TST; + + if(++count_blink >= BLINK_TIME) + { + count_blink=0; + count_mode++; + blink_over = (count_mode & 1)?1:0; + blink_alarm = (count_mode & 7)?1:0; + + if(TST) + { + heat_lamp = blink_over; + work_lamp = blink_over; + power_lamp= blink_over; + } + else + { + if(Mode==adr_SHKF) + { + power_lamp= 1; + if(sig.bit.Alarm){// power_lamp= blink_alarm; + alm_lamp = blink_over; } + else alm_lamp = 0; + + if(sig.bit.Error){ power_lamp= blink_over; + err_lamp = blink_over; } + else err_lamp = 0; + } + else + { +// if(sig.bit.Error) work_lamp = blink_over; +// else if(sig.bit.Alarm) work_lamp = blink_alarm; +// else + work_lamp = 1; + + if(bSecretBt|cSecretBt) work_lamp = blink_alarm; + + if(sig.bit.OverHeat) heat_lamp = 1; + else if(sig.bit.SubHeat) heat_lamp = blink_over; + else if(sig.bit.OutHeat) heat_lamp = !blink_alarm; + else heat_lamp = 0; +} } } } + +void Init_sensors() +{ + int i; + + TPL_CANS = tpl_cans = cal_addr = 0; + + switch(Mode) + { + case adr_TRN1: + case adr_TRN2: + TPL_CANS = TPL_TRN; tpl_cans = TPL_TRN*2; cal_addr = tpl_cans; break; + case adr_POW1: + case adr_POW2: + TPL_CANS = TPL_POW; tpl_cans = TPL_POW*2; cal_addr = tpl_cans; break; + + case adr_ENG1: + TPL_CANS = TPL_ENG; tpl_cans = TPL_ENG; cal_addr = tpl_cans; break; + + + case adr_SHKF: tpl_cans = TPL_SHK; cal_addr = tpl_cans-2; break; + } + + pow_addr = tpl_cans + Owen; + + for(i=0;i<24;i++) + { + sens_type[i]=0; + sens_pair[i]=i; + + adc_filter[i] = def_FILTERBAT; + out_filter[i] = def_FILTERBAT; + } + + if(TermoSW) + for(i=0;i=edge) return 1; + (*count)++; return pre; + } + if( (*count) == 0 ) return 0; + (*count)--; return pre; +} + +void reset_errs(int sens, ERROR err) +{ + ERROR set; + + set.all = (sens_error[sens].all & NOER) | err.all; + chk.bit.Error|= set.bit.Stop; + set.bit.Ready = !set.bit.Stop; + sens_error[sens] = set; +} + +void Current_count(int chan) +{ + float Numb,Zer,Current,Level; + static float aCurrent,Amplitude; + int sens, pair, ist, thrd, fazz, feed; + + ERROR error; + + if(Desk == dsk_LOAD) + if(!chan) + { + sig.all = chk.all; + chk.all = 0; + } + + sens = pow_addr + chan; + pair = sens_pair[chan]; + ist = !(chan & 1); + feed = (chan >>1); + fazz = feed*3; + thrd = feed+4; + + if(sens_error[sens].bit.Bypas) + { + sens_error[sens].all = 0; + sens_error[sens].bit.Bypas = 1; + sens_data[sens] = 0; + return; + } + + Numb = adc_table_lem[chan]; + + modbus[0x64+chan] = Numb; + +// Ñðåäíèé (îí æå íóëåâîé) óðîâåíü ïîêàçàíèé ÀÖÏ + zer_count[chan] += (Numb-zer_count[chan])/(5.0 * ADC_FREQ); + Zer = (int)(filterbat(&zer_filter[chan],zer_count[chan])); + if(WAKE < (WAKE_TIME /2)) Zero_lev[chan] = Zer; +/* +Test_mem_limit(12); +Log_to_mem((int)adc_table_lem[chan]); +Log_to_mem((int)zer_count[chan]); +Log_to_mem((int)Zero_lev[chan]); +*/ +// Ìãíîâåííîå çíà÷åíèå ôàçû + Current = (Numb - Zero_lev[chan]) * powK[chan]; + +// Äåéñòâóþùåå (ñðåäíåêâàäðàòè÷íîå) çíà÷åíèå ôàçû + lev_quadr[chan] += ((Current*Current)-lev_quadr[chan])/(1.0 * ADC_FREQ); + lev_count[chan] = sqrt(lev_quadr[chan]); + +// Çàïîìíèì + if(ist) + { + if(Desk==dsk_COMM) aCurrent =-Current; + else aCurrent = Current; // Çàïîìíèëè ìãíîâåííîå çíà÷åíèå - äëà àìïëèòóäû + } + else + { +// Âû÷èñëåíèå àìïëèòóäû + Amplitude = filterbat(&out_filter[sens], im_calc(Current,aCurrent)); + + if(sens_type[sens]==VOLTAGE) + if(Amplitude<20) Amplitude = 0; + + if(sens_type[sens]==CURRENT) + if(Amplitude<75) Amplitude = 0; + + Level = Amplitude / RADIX2; + + if(!WAKE) + { + sens_data[sens ] = Amplitude; + sens_data[sens-1] = Level; + } + +// Äåéñòâóþùåå (ñðåäíåêâàäðàòè÷íîå) çíà÷åíèå òðåòüåé ôàçû + Numb =-Current-aCurrent; + lev_quadr[thrd] += (Numb*Numb-lev_quadr[thrd])/(1.0 * ADC_FREQ); + lev_count[thrd] = sqrt(lev_quadr[thrd]); +/* +if(!no_write) +{ +Test_mem_limit(8); + +Log_to_mem(Current); +Log_to_mem(aCurrent); +Log_to_mem(Numb); + +Log_to_mem(lev_count[chan]); +Log_to_mem(lev_count[pair]); +Log_to_mem(lev_count[thrd]); + +Log_to_mem(Amplitude); +Log_to_mem(Level); +} +*/ +modbus[0x68+fazz ] = lev_count[pair]; +modbus[0x68+fazz+1] = lev_count[chan]; +modbus[0x68+fazz+2] = lev_count[thrd]; + } + +// Ýòî ìàêñèìàëüíîå + Numb = lev_count[chan]; + if(Numb 0.3) && (Numb>Curr_Edge), + &err_count[chan],time_3sec,0)) + { + error.bit.Wry = 1; + error.bit.Stop = 1; + } + + if(er_anal( ((Numb-lev_count[thrd])/Numb > 0.3) && (Numb>Curr_Edge), + &err_count[thrd],time_3sec,0)) + { + error.bit.Wry = 1; + error.bit.Stop = 1; + } + + if(Desk == dsk_LOAD) + if(!ist) + { + if(Level > sens_hi_edge[sens]) + { + error.bit.Hyper = 1; + error.bit.Stop = 1; + } + + if(sens_type[sens]==VOLTAGE) + + if(er_anal( (Level < sens_lo_edge[sens]), + &low_count[feed],time_3sec,0)) + { + error.bit.Out = 1; + error.bit.Stop = 1; + } + + if(sens_type[sens]==CURRENT) + if(Level > sens_lo_edge[sens]) + { + error.bit.Over = 1; + } } +/* +if((chan==1)||(chan==3)) +if(error.all) +if(!no_write) +{ +Test_mem_limit(12); +Log_to_mem(Current); +Log_to_mem(aCurrent); +Log_to_mem(Numb); +Log_to_mem(lev_count[chan]); +Log_to_mem(lev_count[pair]); +Log_to_mem(lev_count[thrd]); +Log_to_mem(Amplitude); +Log_to_mem(Level); +Log_to_mem(Zero_lev[chan]); +Log_to_mem(Curr_Edge); +Log_to_mem(error.all); +Log_to_mem(WAKE); +} +*/ + fin: + reset_errs(sens,error); +} + +void Temper_count(int chan, int own) +{ + float Numb; + static int Temper; + int i,j, kun; + long s; + ERROR error; + int ovn; + + if(!chan) + { + sig.all = chk.all; + chk.all = 0; + } + + if(sens_error[chan].bit.Bypas) + if(chan2200) kun|=2; + + if(kun>=0) + { + TCaliber[kun] = Numb; + calc_sensor_koef(); + return; + } } + + if(chan>=tpl_cans) return; + +// Kun èìåííî ÷òîá ñêîìïåíñèðîâàòü íå÷åòíîñòü + if(kun&1) Numb = (Numb-K300_2)*K_T2+ZERO; + else Numb = (Numb-K300_1)*K_T1+ZERO; + } + + if(TermoRS) + { + if(kun>=0) + { + if(WAKE) out_filter[chan] = adc_filter[chan]; + else + { +// Êàëèáðîâêó îòôèëüòðóåì âòîðûì ñëîåì + Numb = filterbat(&out_filter[chan],Numb); + + TCaliber[kun] = Numb; + calc_sensor_koef(); + } + return; + } + + if(Desk==dsk_BKSD) + { +sens_data[chan+8] = ADC_table[chan]; + if(chan<6) Numb = (Numb-K100_D)*K100; + else Numb = (Numb-K100_D)*K_50; + } + else + { + if(chan&1) Numb = (Numb-K100_2)*K_T2; + else Numb = (Numb-K100_1)*K_T1; + } } + + if(Numb < -20) Numb = -20; + if(Numb > 200) Numb = 200; + + if(bSecretBt|cSecretBt) Numb = 40.0; + + sens_data[chan] = Numb*10; + + Temper = Numb; + + error.all = 0; + if(WAKE || sens_error[chan].bit.Ignor) goto fin; + +// Îáðûâ èëè íåèñïðàâíîñòü + if(Temper<=-20 || Temper>=200) + { + error.bit.Tear = 1; + chk.bit.OutHeat = 1; + } + else + +// Ïåðåãðåâ + if(((Temper>sens_hi_edge[chan]-Cooling) && (sens_error[chan].bit.Hyper)) || + (Temper>sens_hi_edge[chan]) ) + { + error.bit.Hyper = 1; + error.bit.Stop = 1; + chk.bit.OverHeat= 1; + } + else + +// Ïðåäóïðåæäåíèå ïî òåìïåðàòóðå + if(Temper>sens_lo_edge[chan]) + { + error.bit.Over = 1; + chk.bit.SubHeat = 1; + } + + fin: + reset_errs(chan,error); +} + +void Power_count(int chan) +{ + float Numb; + int Power,bitt; + ERROR error; + + if(!chan) + { + sig.all = chk.all; + chk.all = 0; + } + + if(sens_error[chan].bit.Bypas) + { + sens_error[chan].all = 0; + sens_error[chan].bit.Bypas = 1; + sens_data[chan] = 0; + return; + } + + Numb = ADC_table[chan]; + + if(cRawMeat) + { + sens_data[chan] = Numb; + return; + } + + Power = Numb * powK[sens_type[chan]]; + + sens_data[chan] = Power; + + error.all = 0; + + if(WAKE || sens_error[chan].bit.Ignor) goto fin; + +// Äèñêðåòíûå êàíàëû + bitt = chan*2; + if(chan!=7) + { + error.bit.Discr1 = er_anal(((DigErr.all>>bitt)&1), &din_count[bitt], 1000, 0); bitt++; + error.bit.Discr2 = er_anal(((DigErr.all>>bitt)&1), &din_count[bitt], 1000, 0); bitt++; + } + if(chan==6) + { + error.bit.Discr3 = er_anal(((DigErr.all>>bitt)&1), &din_count[bitt], 1000, 0); bitt++; + error.bit.Discr4 = er_anal(((DigErr.all>>bitt)&1), &din_count[bitt], 1000, 0); bitt++; + } + error.bit.Contr = error.bit.Discr1 | error.bit.Discr2 | error.bit.Discr3 | error.bit.Discr4; + +// Ïîíèæåííîå íàïðàæåíèå + if(Power sens_hi_edge[chan]) + { + error.bit.Hyper = 1; + error.bit.Stop = 1; + } +*/ + if(error.all) + chk.bit.Alarm = 1; + + fin: + reset_errs(chan,error); +} diff --git a/Source/Internal/message.c b/Source/Internal/message.c new file mode 100644 index 0000000..8c15358 --- /dev/null +++ b/Source/Internal/message.c @@ -0,0 +1,294 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "package.h" +#include "RS485.h" +#include "crc16.h" +#include "cntrl_adr.h" +#include "bios_dsp.h" +#include "message.h" +#include "filter_bat2.h" +#include "measure.h" + + +#include "ADC.h" +#include "peripher.h" + +#include "ecan.h" +#include "pulto.h" +#include "spise2p.h" + +#include "caliber.h" + +int modbus[ANSWER_LEN+1]; +unsigned int param[ANSWER_LEN+1]; + +void Default_params() +{ + unsigned int i,def; + + int shkf_lo_edge[] = {300, // 380 + 300, // 38O + 0, // 0 + 0, // 0 + 15, // 31 + 22, // 27 + 20, // 24 + 10, // 15 + 60}; // AD + + int bright[] = {10,8,6,8,6,8}; + + for(i=0;iadr_PULT) def--; +#else + def = Mode-3; + if(Mode==adr_SHKF) def=4; +#endif + for(i=0;i<8;i++) Caliber[i] = def_cal[def][i]; + } + + if(Desk == dsk_COMM) + { + for(i=0;iRS_Header[2] << 8) |*/ rs_arr->RS_Header[3]; + +// ïîëó÷èëè êîëè÷åñòâî ñëîâ äàííûõ + Length_MB = (rs_arr->RS_Header[4] << 8) | rs_arr->RS_Header[5]; + + ///////////////////////////////////////////////// + // Îòñûëêà + /* Ïîñ÷èòàëè êîíòðîëüíóþ ñóììó ïåðåä ñàìîé ïîñûëêîé */ + + rs_arr->buffer[0] = CNTRL_ADDR; + rs_arr->buffer[1] = CMD_MODBUS_3; + rs_arr->buffer[2] = Length_MB*2; + + for (i=0;ibuffer[3+i*2 ]=(Modbus[Address_MB+i].byt.byte_hi); + rs_arr->buffer[3+i*2+1]=(Modbus[Address_MB+i].byt.byte_lo); + } + + crc = 0xffff; + crc = get_crc_16(crc, rs_arr->buffer, Length_MB*2+3); + + rs_arr->buffer[Length_MB*2+3] = LOBYTE(crc); + rs_arr->buffer[Length_MB*2+4] = HIBYTE(crc); + + rs_arr->buffer[Length_MB*2+5] = 0; + rs_arr->buffer[Length_MB*2+6] = 0; + rs_arr->buffer[Length_MB*2+7] = 0; + rs_arr->buffer[Length_MB*2+8] = 0; + + rs_arr->flag_TIMEOUT_to_Send=true; + RS_Send(rs_arr, rs_arr->buffer, Length_MB*2+8); + + return; +} + +void ReceiveCommandModbus6(RS_DATA *rs_arr) +{ + unsigned int Address_MB, Data_MB, i; + + ///////////////////////////////////////////////// + // Îòñûëêà + /* Îòïðàâëàåì íàçàä òî æå ñàìîå */ + + for (i=0;i<8;i++) + rs_arr->buffer[i] = rs_arr->RS_Header[i]; + + +// ïîëó÷èëè íà÷àëüíûé àäðåñ çàïèñè + Address_MB = (/*(rs_arr->RS_Header[2] << 8) | */rs_arr->RS_Header[3]); + +// ïîëó÷èëè ñëîâî äàííûõ + Data_MB = (rs_arr->RS_Header[4] << 8) | rs_arr->RS_Header[5]; + + Modbus[Address_MB].all = Data_MB; + + rs_arr->flag_TIMEOUT_to_Send=true; + RS_Send(rs_arr, rs_arr->buffer, 10); +} + +void SendCommandModbus4(RS_DATA *rs_arr) +{ + unsigned int crc; + + ///////////////////////////////////////////////// + // Îòñûëêà + + rs_arr->buffer[0] = 16; + rs_arr->buffer[1] = 4; + rs_arr->buffer[2] = 0; + rs_arr->buffer[3] = 0; + rs_arr->buffer[4] = 0; + rs_arr->buffer[5] = 48; + + crc = 0xffff; + crc = get_crc_16(crc, rs_arr->buffer, 6); + + rs_arr->buffer[6] = LOBYTE(crc); + rs_arr->buffer[7] = HIBYTE(crc); + +//rs_arr->buffer[8] = 0; +//rs_arr->buffer[9] = 0; +//rs_arr->buffer[10] = 0; + + rs_arr->flag_TIMEOUT_to_Send=true; + RS_Send(rs_arr, rs_arr->buffer, 8); +} + +void ReceiveAnswerModbus4(RS_DATA *rs_arr) +{ + unsigned int i; + + ///////////////////////////////////////////////// + // Îòñûëêà + + for (i=0;i<8;i++) + { + ext_temp[i] = ( rs_arr->RS_Header[5+i*12] << 8) + + rs_arr->RS_Header[6+i*12]; + + ext_diag[i] = ( rs_arr->RS_Header[7+i*12] | + rs_arr->RS_Header[8+i*12] ) != 0; +} } + + diff --git a/Source/Internal/peripher.c b/Source/Internal/peripher.c new file mode 100644 index 0000000..bba30e2 --- /dev/null +++ b/Source/Internal/peripher.c @@ -0,0 +1,291 @@ +#include "DSP2833x_Device.h" // DSP281x Headerfile Include File +#include "filter_bat2.h" +#include "measure.h" +#include "RS485.h" +#include "message.h" + +#include "package.h" +#include "pulto.h" + +#include "peripher.h" +#include "GPIO_table.h" + +int Mode,Desk,TermoAD=0,TermoRS=0,TermoSW=0,Kurrent=0,Kalibro=0,Owen=0; +unsigned int INcount0=0,INcount1=0; +LONGE DigErr; + +int MUX_GPIO32,MUX_GPIO48,DIR_GPIO32,DIR_GPIO48; + +void setup_leds_line() +{ + MUX_GPIO32 = GpioCtrlRegs.GPBMUX1.bit.GPIO32; + MUX_GPIO48 = GpioCtrlRegs.GPBMUX2.bit.GPIO48; + DIR_GPIO32 = GpioCtrlRegs.GPBDIR.bit.GPIO32; + DIR_GPIO48 = GpioCtrlRegs.GPBDIR.bit.GPIO48; + + EALLOW; + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0; + GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 0; + GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1; + GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1; + EDIS; +} + +void unsetup_leds_line() +{ + EALLOW; + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = MUX_GPIO32; + GpioCtrlRegs.GPBMUX2.bit.GPIO48 = MUX_GPIO48; + GpioCtrlRegs.GPBDIR.bit.GPIO32 = DIR_GPIO32; + GpioCtrlRegs.GPBDIR.bit.GPIO48 = DIR_GPIO48; + EDIS; +} + +void get_Mode() +{ + EALLOW; + + GpioCtrlRegs.GPAMUX1.all &= 0xFF000000; // 00—11 + GpioCtrlRegs.GPAMUX2.all &= 0xFF00003F; // 19—27 + GpioCtrlRegs.GPBMUX1.all &= 0xFFFFFFC0; // 32—34 + GpioCtrlRegs.GPBMUX2.all &= 0x000FF000; // 48—53, 58—63 + + GpioCtrlRegs.GPADIR.bit.GPIO20 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO21 = 0; + GpioCtrlRegs.GPADIR.bit.GPIO22 = 0; + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 0; + + EDIS; + + Mode = 1; + Mode += 1 * !GpioDataRegs.GPADAT.bit.GPIO21; + Mode += 2 * !GpioDataRegs.GPADAT.bit.GPIO20; + Mode += 4 * !GpioDataRegs.GPADAT.bit.GPIO22; + Mode += 8 * !GpioDataRegs.GPBDAT.bit.GPIO51; + + if( (Mode==adr_POW1)||(Mode==adr_POW2)) Desk = dsk_COMM; + if( (Mode==adr_TRN1)||(Mode==adr_TRN2)) Desk = dsk_BKST; + if( (Mode==adr_LOA1)||(Mode==adr_LOA2)) Desk = dsk_LOAD; + if (Mode==adr_ENG1) Desk = dsk_BKSD; + if (Mode==adr_PULT) Desk = dsk_EPLT; + if (Mode==adr_SHKF) Desk = dsk_SHKF; + + if( (Desk==dsk_COMM)||(Desk==dsk_LOAD)) Kurrent = 1; + if( (Desk==dsk_BKSD)||(Desk==dsk_BKST)) TermoRS = 1; + if( (Desk==dsk_COMM)||(Desk==dsk_SHKF)) TermoAD = 1; + if( (Desk==dsk_COMM)||(Desk==dsk_BKST)) TermoSW = 2; + if (Desk==dsk_BKSD) TermoSW = 1; + +#ifdef CALIB_RS + if (Desk!=dsk_EPLT) Kalibro = 1; +#else + if( (Desk==dsk_COMM)||(Desk==dsk_SHKF)|| + (Desk==dsk_LOAD) ) Kalibro = 1; +#endif + +#ifdef OWEN + if (Desk==dsk_COMM) Owen = OWEN_DT; +#endif + + clear_LED_OUT_1(); + clear_LED_OUT_2(); + clear_RES_OUT_1(); + clear_RES_OUT_2(); + + EALLOW; + switch(Desk) + { + case dsk_COMM: GpioCtrlRegs.GPADIR.all = COMM_GPADIR; + GpioCtrlRegs.GPBDIR.all = COMM_GPBDIR; break; + + case dsk_BKSD: GpioCtrlRegs.GPADIR.all = BKSD_GPADIR; + GpioCtrlRegs.GPBDIR.all = BKSD_GPBDIR; break; + + case dsk_BKST: GpioCtrlRegs.GPADIR.all = BKST_GPADIR; + GpioCtrlRegs.GPBDIR.all = BKST_GPBDIR; break; + + case dsk_EPLT: GpioCtrlRegs.GPADIR.all = PLT2_GPADIR; + GpioCtrlRegs.GPBDIR.all = PLT2_GPBDIR; break; + + case dsk_LOAD: GpioCtrlRegs.GPADIR.all = LOAD_GPADIR; + GpioCtrlRegs.GPBDIR.all = LOAD_GPBDIR; + GpioDataRegs.GPASET.bit.GPIO3=1; break; + + case dsk_SHKF: GpioCtrlRegs.GPADIR.all = SHKF_GPADIR; + GpioCtrlRegs.GPBDIR.all = SHKF_GPBDIR; break; + } + EDIS; +} + +void select_tpl_255(void) +{ + if(Desk==dsk_BKSD) + { +#define BKSD_A_tpl_255 ((1L<<11) + (1L<<9) + (1L<<7) + (1L<<3)) + + GpioDataRegs.GPACLEAR.all = BKSD_A_tpl_255; + } + + if(Desk==dsk_COMM) + { +#define COMM_A_tpl_255 ((1L<<27) + (1L<<24) + (1L<<25)) +#define COMM_B_tpl_255 ((1L<<(49-32)) + (1L<<(52-32))) + + GpioDataRegs.GPASET.all = COMM_A_tpl_255; + GpioDataRegs.GPBSET.all = COMM_B_tpl_255; + } + + if(Desk==dsk_BKST) + { +#define BKST_A_tpl_zero ((1L<<11) + (1L<<9) + (1L<<7) + (1L<<3) + (1L<<1) + (1L<<8) + (1L<<6) + (1L<<0) + (1L<<27) + (1L<<24)) +#define BKST_B_tpl_zero ((1L<<(53-32)) + (1L<<(50-32))) + + GpioDataRegs.GPASET.all = BKST_A_tpl_zero; + GpioDataRegs.GPBSET.all = BKST_B_tpl_zero; +} } + +void select_tpl_canal(int n_tpl) +{ + unsigned long GPIO_A_tpl_set = 0; + unsigned long GPIO_B_tpl_set = 0; + + if(Desk==dsk_BKSD) + { + if(!(n_tpl&0x01)) GPIO_A_tpl_set|=(1L<<11); + if(!(n_tpl&0x02)) GPIO_A_tpl_set|=(1L<<9); + if(!(n_tpl&0x04)) GPIO_A_tpl_set|=(1L<<7); + if(!(n_tpl&0x08)) GPIO_A_tpl_set|=(1L<<3); + + GpioDataRegs.GPASET.all = GPIO_A_tpl_set; + } + + if(Desk==dsk_BKST) + { + if(n_tpl==0) GpioDataRegs.GPACLEAR.bit.GPIO11=1; + if(n_tpl==1) GpioDataRegs.GPACLEAR.bit.GPIO9=1; + if(n_tpl==2) GpioDataRegs.GPACLEAR.bit.GPIO7=1; + if(n_tpl==3) GpioDataRegs.GPACLEAR.bit.GPIO3=1; + if(n_tpl==4) GpioDataRegs.GPACLEAR.bit.GPIO1=1; + if(n_tpl==5) GpioDataRegs.GPACLEAR.bit.GPIO8=1; + if(n_tpl==6) GpioDataRegs.GPACLEAR.bit.GPIO6=1; + if(n_tpl==7) GpioDataRegs.GPACLEAR.bit.GPIO0=1; + if(n_tpl==8) GpioDataRegs.GPACLEAR.bit.GPIO27=1; + if(n_tpl==9) GpioDataRegs.GPACLEAR.bit.GPIO24=1; + if(n_tpl==10) GpioDataRegs.GPBCLEAR.bit.GPIO53=1; + if(n_tpl==11) GpioDataRegs.GPBCLEAR.bit.GPIO50=1; + } + + if(Desk==dsk_COMM) + { + if(!(n_tpl&0x01)) GPIO_A_tpl_set|=(1L<<27); + if(!(n_tpl&0x02)) GPIO_A_tpl_set|=(1L<<24); + if(!(n_tpl&0x04)) GPIO_A_tpl_set|=(1L<<25); + if(!(n_tpl&0x08)) GPIO_B_tpl_set|=(1L<<(49-32)); + if(!(n_tpl&0x10)) GPIO_B_tpl_set|=(1L<<(52-32)); + + GpioDataRegs.GPACLEAR.all = GPIO_A_tpl_set; + GpioDataRegs.GPBCLEAR.all = GPIO_B_tpl_set; +} } + +void get_Buttons() +{ + unsigned long butt =0; + unsigned long fluf =0; + + if(Desk==dsk_BKSD) + { + bTestLamp = !GpioDataRegs.GPBDAT.bit.GPIO50; + bSecretBt = !GpioDataRegs.GPBDAT.bit.GPIO49; + + InputRep0 = bTestLamp; + InputRep1 = bSecretBt; + + if(GpioDataRegs.GPADAT.bit.GPIO0) butt +=0x0001; + if(GpioDataRegs.GPADAT.bit.GPIO2) butt +=0x0002; + if(GpioDataRegs.GPADAT.bit.GPIO10)butt +=0x0004; + if(GpioDataRegs.GPADAT.bit.GPIO4) butt +=0x0008; + + Inputs.all = butt; + } + +/* Íè÷åãî òàêîãî â äåéñòâèòåëüíîñòè íåò + if(Desk==dsk_BKST) + { bSecretBt = !GpioDataRegs.GPBDAT.bit.GPIO63; + InputRep1 = bSecretBt; + return; + } */ + + if(Desk==dsk_COMM) + { + bSecretBt = !GpioDataRegs.GPBDAT.bit.GPIO53; + bTermoCal = er_anal(!GpioDataRegs.GPBDAT.bit.GPIO50, &INcount0, 0xFFFF, 0); + + InputRep1 = bSecretBt; + InputRep2 = bTermoCal; + } + + if(Desk==dsk_EPLT) + { + bTestLamp = er_anal(GpioDataRegs.GPADAT.bit.GPIO26, &INcount0, 1000, 0); + + if(GpioDataRegs.GPADAT.bit.GPIO27) butt +=0x0001; + if(GpioDataRegs.GPADAT.bit.GPIO24) butt +=0x0002; + if(GpioDataRegs.GPBDAT.bit.GPIO53) butt +=0x0004; + if(GpioDataRegs.GPBDAT.bit.GPIO50) butt +=0x0008; + + if(GpioDataRegs.GPADAT.bit.GPIO26) butt +=0x0010; + if(GpioDataRegs.GPADAT.bit.GPIO23) butt +=0x0020; + if(GpioDataRegs.GPBDAT.bit.GPIO52) butt +=0x0040; + if(GpioDataRegs.GPADAT.bit.GPIO4 ) butt +=0x0080; + + if(GpioDataRegs.GPADAT.bit.GPIO25) butt +=0x0100; + if(GpioDataRegs.GPBDAT.bit.GPIO49) butt +=0x0200; + if(GpioDataRegs.GPADAT.bit.GPIO11) butt +=0x0400; + if(GpioDataRegs.GPADAT.bit.GPIO5 ) butt +=0x0800; + + if(GpioDataRegs.GPBDAT.bit.GPIO48) butt +=0x1000; + if(GpioDataRegs.GPADAT.bit.GPIO10) butt +=0x2000; // Ñåêðåòíûé âõîä + + Inputs.all = butt; + } + + if(Desk==dsk_LOAD) + { + if(!GpioDataRegs.GPADAT.bit.GPIO6) butt +=0x0001; // OMEGA + if(!GpioDataRegs.GPADAT.bit.GPIO8) butt +=0x0002; // Start_1 + if(!GpioDataRegs.GPADAT.bit.GPIO11) butt +=0x0004; // Res_in + + Inputs.all = butt; + } + + if(Desk==dsk_SHKF) + { + + if(GpioDataRegs.GPBDAT.bit.GPIO53) fluf += 0x0000010; else butt += 0x0001; + if(GpioDataRegs.GPBDAT.bit.GPIO52) fluf += 0x0000040; else butt += 0x0002; + + if(GpioDataRegs.GPADAT.bit.GPIO2) fluf += 0x0001000; else butt += 0x0004; + if(GpioDataRegs.GPADAT.bit.GPIO4) fluf += 0x0002000; else butt += 0x0008; + if(GpioDataRegs.GPADAT.bit.GPIO6) fluf += 0x0004000; else butt += 0x0010; + if(GpioDataRegs.GPADAT.bit.GPIO0) fluf += 0x0008000; else butt += 0x0020; + + if(GpioDataRegs.GPADAT.bit.GPIO8) fluf += 0x0010000; else butt += 0x0040; + if(GpioDataRegs.GPADAT.bit.GPIO10) fluf += 0x0020000; else butt += 0x0080; + if(GpioDataRegs.GPADAT.bit.GPIO3) fluf += 0x0040000; else butt += 0x0100; + if(GpioDataRegs.GPADAT.bit.GPIO5) fluf += 0x0080000; else butt += 0x0200; + if(GpioDataRegs.GPADAT.bit.GPIO7) fluf += 0x0100000; else butt += 0x0400; + if(GpioDataRegs.GPADAT.bit.GPIO1) fluf += 0x0200000; else butt += 0x0800; + if(GpioDataRegs.GPADAT.bit.GPIO11) fluf += 0x0400000; else butt += 0x1000; + if(GpioDataRegs.GPADAT.bit.GPIO9) fluf += 0x0800000; else butt += 0x2000; + + DigErr.all = fluf; + Inputs.all = butt; + } + + butt = 1 * !GpioDataRegs.GPADAT.bit.GPIO21; + butt += 2 * !GpioDataRegs.GPADAT.bit.GPIO20; + butt += 4 * !GpioDataRegs.GPADAT.bit.GPIO22; + butt += 8 * !GpioDataRegs.GPBDAT.bit.GPIO51; + + Jumpers = butt; +} diff --git a/Source/Internal/pulto.c b/Source/Internal/pulto.c new file mode 100644 index 0000000..2efd425 --- /dev/null +++ b/Source/Internal/pulto.c @@ -0,0 +1,107 @@ +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_SWPrioritizedIsrLevels.h" + +#include "RS485.h" +#include "message.h" +#include "filter_bat2.h" +#include "measure.h" +#include "package.h" +#include "pulto.h" +#include "kanal.h" +#include "peripher.h" + +unsigned long isMask; +int isNumb; + +int quaLamp = 6; + +unsigned long Lonely=0; + +void what_is() +{ + static unsigned int count_blink; + static int numb=0; + + if(++count_blink >= BLINK_TIME) + { + count_blink=0; + + numb++; if(numb==10) numb=0; + isNumb = numb*1000 + numb*100 + numb*10 +numb; + + if(isMask) isMask = 0; + else isMask = 0xFFFFFFFF; +} } + +interrupt void cpu_timer1_isr_PULT(void) +{ + static int cownt=0,count_bright; + unsigned int light=0, i; + unsigned int Alone = 20*READY_FREQ; + + EALLOW; + CpuTimer1.InterruptCount++; + IER |= MINT13; // Set "global" priority + EINT; + EDIS; // This is needed to disable write to EALLOW protected registers + + if(!cReset) ServiceDog(); + + if(++CanPowse >= CANPOWSE) + { + CanPowse = 0; + CanGO = 1; + } + + toggle_ONLINE(); // ñòðîá äëà ÏËÈÑ + toggle_RES_OUT_1(); // òèïà ýòî ãîòîâíîñòü + toggle_RES_OUT_2(); // íà âñàêèé + + if(++Lonely > Alone) Lonely = Alone; + + if(++count_bright >= maximum_bright) count_bright = 0 ; + + for(i=0; i2) cownt=0; + + if(cTestLamp|bTestLamp) + { + what_is(); + + if(cownt == 0) kanal_Send(0,isNumb,4); + if(cownt == 1) kanal_Send(1,isNumb,4); + kanal_Send(2,isMask,0); + if(cownt == 2) kanal_Send(3,isMask,0); + } + else + if(cLiteFire) + { + if(cownt == 0) kanal_Send(0,8888,1); + if(cownt == 1) kanal_Send(1,8888,1); + kanal_Send(2,0xFFFF & light,0); + if(cownt == 2) kanal_Send(3,0xFFFF,0); + } + else + if((Lonely >= Alone)) + { + if(cownt == 0) kanal_Send(0,0,0); + if(cownt == 1) kanal_Send(1,0,0); + kanal_Send(2,0,0); + if(cownt == 2) kanal_Send(3,0,0); + } + else + { +#if OBOROT == STRAIGHT + if(cownt == 0) kanal_Send(0,modbus[0],1); + if(cownt == 1) kanal_Send(1,modbus[1],1); +#else + if(cownt == 0) kanal_Send(0,modbus[1],1); + if(cownt == 1) kanal_Send(1,modbus[0],1); +#endif + kanal_Send(2,modbus[2] & light,0); + if(cownt == 2) kanal_Send(3,modbus[3],0); +} } diff --git a/Source/Internal/spise2p.c b/Source/Internal/spise2p.c new file mode 100644 index 0000000..4c7cca8 --- /dev/null +++ b/Source/Internal/spise2p.c @@ -0,0 +1,463 @@ +/*================================================================= +File name : SPISE2PD.C + +Originator : Settu Duraisamy + C2000 Applications Team + Texas Instruments + +Description : This file contains the SPI bus Serial EEPROM driver + implemented using Virtual SPI driver + +Date : 6/30/2003 (DD/MM/YYYY) +====================================================================*/ + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File + +#include "spise2p.h" + + +/* Instance the SPI bus serial EEPROM driver */ +static SPISE2P_DRV se2p=SPISE2P_DRV_DEFAULTS; + +/* Instance serial EEPROm data transfer structure */ +static SE2P_DATA writeData, readData; + +// Prototype statements for functions found within this file. +interrupt void PRD_TICK(void); +interrupt void cpu_timer2_isr(void); + +int ccc=0; + +/********************************************************************/ +/******* SPI bus Serial EEPROM driver Initialization routine ********/ +/********************************************************************/ + +void Seeprom_write( unsigned int adres, + unsigned int buf[], + unsigned int size) +{ + unsigned int len; + + CpuTimer2.InterruptCount=0; + CpuTimer2Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0 + + while(!spiSe2pFree(&se2p)); + + size = (size / WORD_LEN) + (size % WORD_LEN); + while(size) + { + len = PAGE_LEN - (adres % PAGE_LEN); + if(len > size) len=size; + + writeData.dataPtr = buf; + writeData.nrData = len; + writeData.se2pAddr = adres * WORD_LEN; + + spiSe2pWrite(&se2p, &writeData); + while(!spiSe2pFree(&se2p)); + + buf += len; + adres += len; + size -= len; + } + CpuTimer2Regs.TCR.all = 0x4010; // Use write-only instruction to set TSS bit = 1 +} + +void Seeprom_read( unsigned int adres, + unsigned int buf[], + unsigned int size) +{ + unsigned int len; + + CpuTimer2.InterruptCount=0; + CpuTimer2Regs.TCR.all = 0x4020; // Use write-only instruction to set TSS bit = 0 + + while(!spiSe2pFree(&se2p)); + + size = (size / WORD_LEN) + (size % WORD_LEN); + while(size) + { + len = PAGE_LEN - (adres % PAGE_LEN); + if(len > size) len=size; + + readData.dataPtr = buf; + readData.nrData = len; + readData.se2pAddr = adres * WORD_LEN; + + spiSe2pRead(&se2p, &readData); + while(!spiSe2pFree(&se2p)); + + buf += len; + adres += len; + size -= len; + } + CpuTimer2Regs.TCR.all = 0x4010; // Use write-only instruction to set TSS bit = 1 +} + +void InitSeeprom() +{ + se2p.init(&se2p); + + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.TINT2 = &cpu_timer2_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + InitCpuTimers(); // For this example, only initialize the Cpu Timers + ConfigCpuTimer(&CpuTimer2, (SYSCLKOUT/1000000), 100); + + IER |= M_INT14; +} + +void SPISE2P_DRV_init(SPISE2P_DRV *eeprom) +{ +/* Configure SPI-A pins using GPIO regs*/ +// This specifies which of the possible GPIO pins will be SPI functional pins. +// Comment out other unwanted lines. + EALLOW; + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // General purpose I/O 19 (default) (I/O) + GpioCtrlRegs.GPADIR.bit.GPIO19 = 1; // Configures the GPIO pin as an output + GpioDataRegs.GPADAT.bit.GPIO19 = 0; + EDIS; + + /* Configure the SPI: 8-bit, Rising edge with delay */ + SpiaRegs.SPICCR.all=0x0007; + SpiaRegs.SPICTL.all=0x001F; + SpiaRegs.SPISTS.all=0x00; + + SpiaRegs.SPIBRR = CLKMULT * 6 + 1; + + SpiaRegs.SPIFFTX.all=0x8000; + SpiaRegs.SPIFFRX.all=0x0000; + SpiaRegs.SPIFFCT.all=0x00; + SpiaRegs.SPIPRI.all=0x0010; + + /* Disable Chip Select of Serial EEPROM */ + eeprom->csr=0; + eeprom->msgPtr=0; + + SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SCI +} + +void SPISE2P_DRV_csset() +{ + GpioDataRegs.GPADAT.bit.GPIO19 = 1; +} + +void SPISE2P_DRV_csclr() +{ + GpioDataRegs.GPADAT.bit.GPIO19 = 0; +} + +unsigned int spiSe2pFree(SPISE2P_DRV *se2p) +{ + if(se2p->csr&0x3) return(0); + else return(1); +} + +void spiSe2pWrite(SPISE2P_DRV *se2p, SE2P_DATA *msgPtr) +{ + se2p->msgPtr=msgPtr; + se2p->csr|=0x1; +} + +void spiSe2pRead(SPISE2P_DRV *se2p, SE2P_DATA *msgPtr) +{ + se2p->msgPtr=msgPtr; + se2p->csr|=0x2; +} + +/********************************************************************/ +/******* SPI bus Serial EEPROM driver Tick function *****************/ +/********************************************************************/ + +interrupt void cpu_timer2_isr(void) +{ EALLOW; + CpuTimer2.InterruptCount++; + + se2p.tick(&se2p); + + // The CPU acknowledges the interrupt. + EDIS; +} + +void SPISE2P_DRV_tick(SPISE2P_DRV *eeprom) +{ + static unsigned int step=0; + static unsigned int dataCount=0; + static volatile unsigned int dummy=0; + + switch(step) + { + case 0: + /* If write request is SET, then trigger the Write operation + If read request is SET, then trigger the Read operation + If Read request is also not SET, then continue to poll */ + + if(eeprom->csr&SPISE2P_WRRQ) + { step=1; + eeprom->csr|=SPISE2P_WRIP; /* Set Write in progress*/ + eeprom->csclr(); + } + + if(eeprom->csr&SPISE2P_RDRQ) + { step=13; + eeprom->csr|=SPISE2P_RDIP; /* Set Read in progress */ + eeprom->csclr(); + } + break; + + case 1: + /************************************************************ + *********** SPI bus EEPROM Write Starts from here *********** + ************************************************************* + Prier to any attempt to write data to SPI serial EEPROM + Write Enable Latch must be set by issuing the WREN command */ + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_WREN_CMD; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; + step=2; + break; + + case 2: + /* Wait for VSPI State machine to send the WREN command and + serial EEPROM Chip Select must be brought to HIGH to set + the WREN latch */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { + dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + eeprom->csset(); + + step=3; + } + break; + + case 3: + /* Assert CS of Serial EEPROM and send WRITE command */ + + eeprom->csclr(); + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_WRITE_CMD; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; + step=4; + break; + + case 4: + /* Wait for VSPI State machine to send the WRITE command */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=5; + } + break; + + case 5: + /* Send Address */ + + #if(SPISE2P_ADDR_WIDTH==SIXTEEN_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT; + SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr; + #endif + #if(SPISE2P_ADDR_WIDTH==EIGHT_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr<<8; + #endif + + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=6; + break; + + case 6: + /* Wait for VSPI State machine to send the Address */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=7; + } + break; + + case 7: + /* Send Data */ + + #if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT) + SpiaRegs.SPICCR.all=SPISE2P_TFR16BIT; + SpiaRegs.SPITXBUF=*(eeprom->msgPtr->dataPtr+dataCount); + #endif + + #if(SPISE2P_DATA_WIDTH==EIGHT_BIT) + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=*(eeprom->msgPtr->dataPtr+dataCount)<<8; + #endif + + dataCount++; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=8; + break; + + case 8: + /* Wait for VSPI State machine to send the Data. + If all the data are sent, then set the CS pin to HIGH + to program or write the data in EEPROM array */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + + if (dataCount==eeprom->msgPtr->nrData) + { eeprom->csset(); + step=9;} + else + step=7; /* Write next data */ + } + break; + + + case 9: + /* Read the EEPROM status register to check whether the + data sent are indeed programmed to the EEPROM array. + Hence, send RDSR command to EEPROM to read status reg. */ + + eeprom->csclr(); + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_RDSR_CMD; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=10; + break; + + case 10: + /* Wait for VSPI State machine to send RDSR command */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=11; + } + break; + + case 11: + /* Send dummy Data to read Status reg. */ + + SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=12; + break; + + case 12: + /* Wait for VSPI State machine to clock out status reg. + Check, whether the data are written to the EEPROM array, + If written, then reset the WRIP(write in progress) and + WRRQ(Write request bit) and go back to STATE0 */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { eeprom->csset(); + + if (SpiaRegs.SPIRXBUF & SPISE2P_BUSY_MASK ) + step=9; + else + { eeprom->csr&=(~SPISE2P_WRIP); + eeprom->csr&=(~SPISE2P_WRRQ); + step=0; + dataCount=0; + } + } + break; + + case 13: + /************************************************************ + *********** SPI bus EEPROM Read Starts from here *********** + ************************************************************* + Send READ Command to SPI bus serail EEPROM */ + + SpiaRegs.SPICCR.all=SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_READ_CMD; + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=14; + break; + + case 14: + /* Wait for VSPI State machine to send READ command */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=15; + } + break; + + case 15: + /* Send Address */ + + #if(SPISE2P_ADDR_WIDTH==SIXTEEN_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT; + SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr; + #endif + #if(SPISE2P_ADDR_WIDTH==EIGHT_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=eeprom->msgPtr->se2pAddr<<8; + #endif + + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=16; + break; + + case 16: + /* Wait for VSPI State machine to send Address */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { dummy=SpiaRegs.SPIRXBUF; /* Reset SPI INT FLAG */ + step=17; + } + break; + + case 17: + /* Send Dummy value to clock out data from serial EEPROM */ + + #if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR16BIT; + SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA; + #endif + + #if(SPISE2P_DATA_WIDTH==EIGHT_BIT) + SpiaRegs.SPICCR.all= SPISE2P_TFR8BIT; + SpiaRegs.SPITXBUF=SPISE2P_DUMMY_DATA<<8; + #endif + + SpiaRegs.SPISTS.bit.BUFFULL_FLAG=1; /* Set TXBUF FULL FLAG */ + step=18; + break; + + case 18: + /* Wait for VSPI State machine to clk out data from EEPROM */ + + if(SpiaRegs.SPISTS.bit.INT_FLAG) /* Check SPI INT FLAG */ + { + #if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT) + *(eeprom->msgPtr->dataPtr+dataCount)=SpiaRegs.SPIRXBUF; + #endif + + #if(SPISE2P_DATA_WIDTH==EIGHT_BIT) + *(eeprom->msgPtr->dataPtr+dataCount)=SpiaRegs.SPIRXBUF&0xFF; + #endif + dataCount++; + step=19; + } + break; + + case 19: + /* If all the data are read, terminate the read operation by + rising the CS. Then reset the RDIP (Read in progress) bit + and reset the RDRQ(Read request) bit and go back to STATE0 */ + + if (dataCount==eeprom->msgPtr->nrData) + { eeprom->csset(); + step=0; + dataCount=0; + eeprom->csr&=(~SPISE2P_RDIP); + eeprom->csr&=(~SPISE2P_RDRQ); + } + else + step=17; + break; + } +} + diff --git a/Source/Internal/tools.c b/Source/Internal/tools.c new file mode 100644 index 0000000..382de8b --- /dev/null +++ b/Source/Internal/tools.c @@ -0,0 +1,68 @@ +#include "DSP2833x_Device.h" // DSP281x Headerfile Include File + +// Configure the timing paramaters for Zone 7. +// Notes: +// This function should not be executed from XINTF +// Adjust the timing based on the data manual and +// external device requirements. +void init_zone7(void) +{ + + // Make sure the XINTF clock is enabled + SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; + + // Configure the GPIO for XINTF with a 16-bit data bus + // This function is in DSP2833x_Xintf.c + InitXintf16Gpio(); + EALLOW; + // All Zones--------------------------------- + // Timing for all zones based on XTIMCLK = SYSCLKOUT + XintfRegs.XINTCNF2.bit.XTIMCLK = 0; + // Buffer up to 3 writes + XintfRegs.XINTCNF2.bit.WRBUFF = 3; + // XCLKOUT is enabled + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + // XCLKOUT = XTIMCLK + XintfRegs.XINTCNF2.bit.CLKMODE = 0; + + // Zone 7------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING7.bit.XWRLEAD = 1; + XintfRegs.XTIMING7.bit.XWRACTIVE = 2; + XintfRegs.XTIMING7.bit.XWRTRAIL = 1; + // Zone read timing + XintfRegs.XTIMING7.bit.XRDLEAD = 1; + XintfRegs.XTIMING7.bit.XRDACTIVE = 3; + XintfRegs.XTIMING7.bit.XRDTRAIL = 0; + + // don't double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING7.bit.X2TIMING = 0; + + // Zone will not sample XREADY signal + XintfRegs.XTIMING7.bit.USEREADY = 0; + XintfRegs.XTIMING7.bit.READYMODE = 0; + + // 1,1 = x16 data bus + // 0,1 = x32 data bus + // other values are reserved + XintfRegs.XTIMING7.bit.XSIZE = 3; + EDIS; + + //Force a pipeline flush to ensure that the write to + //the last register configured occurs before returning. + asm(" RPT #7 || NOP"); +} + +void pause_us(unsigned long t) +{ + unsigned long i; + + t = t >> 1; + + for (i = 0; i < t; i++) + { + DSP28x_usDelay(CLKMULT*8L); +} } + diff --git a/UKSSTMS320F28335.map b/UKSSTMS320F28335.map new file mode 100644 index 0000000..624e41a --- /dev/null +++ b/UKSSTMS320F28335.map @@ -0,0 +1,1209 @@ +****************************************************************************** + TMS320C2000 Linker PC v5.2.15 +****************************************************************************** +>> Linked Wed Jul 22 12:55:54 2026 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00" address: 0000b8fa + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- +PAGE 0: + ZONE0 00004000 00001000 00000000 00001000 RWIX + RAML0 00008000 00004000 00003d13 000002ed RWIX + RAML4 0000c000 00001000 00000180 00000e80 RWIX + ZONE6 00100000 00100000 00000000 00100000 RWIX + FLASHH 00300000 00008000 00000000 00008000 RWIX + FLASHG 00308000 00008000 00000000 00008000 RWIX + FLASHF 00310000 00008000 00000000 00008000 RWIX + FLASHE 00318000 00008000 00000000 00008000 RWIX + FLASHD 00320000 00008000 00000000 00008000 RWIX + FLASHC 00328000 00008000 00000000 00008000 RWIX + FLASHA 00338000 00007f80 00000000 00007f80 RWIX + CSM_RSVD 0033ff80 00000076 00000000 00000076 RWIX + BEGIN 0033fff6 00000002 00000000 00000002 RWIX + CSM_PWL 0033fff8 00000008 00000000 00000008 RWIX + ADC_CAL 00380080 00000009 00000007 00000002 RWIX + OTP 00380400 00000400 00000000 00000400 RWIX + IQTABLES 003fe000 00000b50 00000000 00000b50 RWIX + IQTABLES2 003feb50 0000008c 00000000 0000008c RWIX + FPUTABLES 003febdc 000006a0 00000000 000006a0 RWIX + ROM 003ff27c 00000d44 00000000 00000d44 RWIX + RESET 003fffc0 00000002 00000000 00000002 RWIX + VECTORS 003fffc2 0000003e 00000000 0000003e RWIX + +PAGE 1: + BOOT_RSVD 00000000 00000050 00000000 00000050 RWIX + RAMM0 00000050 000003b0 00000000 000003b0 RWIX + RAMM1 00000400 00000400 000003f0 00000010 RWIX + DEV_EMU 00000880 00000180 000000d0 000000b0 RWIX + FLASH_REGS 00000a80 00000060 00000008 00000058 RWIX + CSM 00000ae0 00000010 00000010 00000000 RWIX + ADC_MIRROR 00000b00 00000010 00000010 00000000 RWIX + XINTF 00000b20 00000020 0000001e 00000002 RWIX + CPU_TIMER0 00000c00 00000008 00000008 00000000 RWIX + CPU_TIMER1 00000c08 00000008 00000008 00000000 RWIX + CPU_TIMER2 00000c10 00000008 00000008 00000000 RWIX + PIE_CTRL 00000ce0 00000020 0000001a 00000006 RWIX + PIE_VECT 00000d00 00000100 00000100 00000000 RWIX + DMA 00001000 00000200 000000e0 00000120 RWIX + MCBSPA 00005000 00000040 00000025 0000001b RWIX + MCBSPB 00005040 00000040 00000025 0000001b RWIX + ECANA 00006000 00000040 00000034 0000000c RWIX + ECANA_LAM 00006040 00000040 00000040 00000000 RWIX + ECANA_MOTS 00006080 00000040 00000040 00000000 RWIX + ECANA_MOTO 000060c0 00000040 00000040 00000000 RWIX + ECANA_MBOX 00006100 00000100 00000100 00000000 RWIX + ECANB 00006200 00000040 00000034 0000000c RWIX + ECANB_LAM 00006240 00000040 00000040 00000000 RWIX + ECANB_MOTS 00006280 00000040 00000040 00000000 RWIX + ECANB_MOTO 000062c0 00000040 00000040 00000000 RWIX + ECANB_MBOX 00006300 00000100 00000100 00000000 RWIX + EPWM1 00006800 00000022 00000022 00000000 RWIX + EPWM2 00006840 00000022 00000022 00000000 RWIX + EPWM3 00006880 00000022 00000022 00000000 RWIX + EPWM4 000068c0 00000022 00000022 00000000 RWIX + EPWM5 00006900 00000022 00000022 00000000 RWIX + EPWM6 00006940 00000022 00000022 00000000 RWIX + ECAP1 00006a00 00000020 00000020 00000000 RWIX + ECAP2 00006a20 00000020 00000020 00000000 RWIX + ECAP3 00006a40 00000020 00000020 00000000 RWIX + ECAP4 00006a60 00000020 00000020 00000000 RWIX + ECAP5 00006a80 00000020 00000020 00000000 RWIX + ECAP6 00006aa0 00000020 00000020 00000000 RWIX + EQEP1 00006b00 00000040 00000040 00000000 RWIX + EQEP2 00006b40 00000040 00000040 00000000 RWIX + GPIOCTRL 00006f80 00000040 0000002e 00000012 RWIX + GPIODAT 00006fc0 00000020 00000020 00000000 RWIX + GPIOINT 00006fe0 00000020 0000000a 00000016 RWIX + SYSTEM 00007010 00000020 00000020 00000000 RWIX + SPIA 00007040 00000010 00000010 00000000 RWIX + SCIA 00007050 00000010 00000010 00000000 RWIX + XINTRUPT 00007070 00000010 00000010 00000000 RWIX + ADC 00007100 00000020 0000001e 00000002 RWIX + SCIB 00007750 00000010 00000010 00000000 RWIX + SCIC 00007770 00000010 00000010 00000000 RWIX + I2CA 00007900 00000040 00000022 0000001e RWIX + RAML5 0000d000 00003000 00000fb0 00002050 RWIX + ZONE7A 00200000 0000fc00 0000fa00 00000200 RWIX + ZONE7B 0020fc00 00000400 00000000 00000400 RWIX + FLASHB 00330000 00008000 00000000 00008000 RWIX + CSM_PWL 0033fff8 00000008 00000008 00000000 RWIX + PARTID 00380090 00000001 00000001 00000000 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.pinit 0 00008000 00000000 UNINITIALIZED + +.text 0 00008000 00003a94 + 00008000 00000bb9 measure.obj (.text) + 00008bb9 0000088f DSP2833x_SWPrioritizedDefaultIsr.obj (.text) + 00009448 000004f2 RS485.obj (.text) + 0000993a 00000497 peripher.obj (.text) + 00009dd1 00000461 ADC.obj (.text) + 0000a232 0000031e spise2p.obj (.text) + 0000a550 000002de bios.obj (.text) + 0000a82e 0000025f message.obj (.text) + 0000aa8d 0000025d main.obj (.text) + 0000acea 000001e7 ecan.obj (.text) + 0000aed1 000001cc DSP2833x_SysCtrl.obj (.text) + 0000b09d 000001a7 pulto.obj (.text) + 0000b244 000001a6 DSP2833x_Xintf.obj (.text) + 0000b3ea 00000178 kanal.obj (.text) + 0000b562 0000015a DAC.obj (.text) + 0000b6bc 00000088 rts2800_fpu32.lib : fs_div.obj (.text) + 0000b744 00000082 crc16.obj (.text) + 0000b7c6 0000006d DSP2833x_CpuTimers.obj (.text) + 0000b833 0000006d tools.obj (.text) + 0000b8a0 0000005a DSP2833x_PieCtrl.obj (.text) + 0000b8fa 00000046 rts2800_fpu32.lib : boot.obj (.text) + 0000b940 00000034 filter_bat2.obj (.text) + 0000b974 0000002a rts2800_fpu32.lib : l_div.obj (.text) + 0000b99e 00000022 : i_div.obj (.text) + 0000b9c0 00000021 : memcpy_ff.obj (.text) + 0000b9e1 00000001 --HOLE-- [fill = 0] + 0000b9e2 00000020 : sqrt.obj (.text) + 0000ba02 0000001f log_to_mem.obj (.text) + 0000ba21 0000001d DSP2833x_Adc.obj (.text) + 0000ba3e 0000001b rts2800_fpu32.lib : args_main.obj (.text) + 0000ba59 00000019 : exit.obj (.text) + 0000ba72 0000000e DSP2833x_SWPrioritizedPieVect.obj (.text) + 0000ba80 00000009 rts2800_fpu32.lib : _lock.obj (.text) + 0000ba89 00000007 cntrl_adr.obj (.text) + 0000ba90 00000004 DSP2833x_usDelay.obj (.text) + +.cinit 0 0000ba94 0000027f + 0000ba94 00000103 crc16.obj (.cinit) + 0000bb97 00000057 measure.obj (.cinit) + 0000bbee 00000043 message.obj (.cinit) + 0000bc31 00000020 peripher.obj (.cinit) + 0000bc51 0000001f spise2p.obj (.cinit) + 0000bc70 0000001c ecan.obj (.cinit) + 0000bc8c 0000001b kanal.obj (.cinit) + 0000bca7 00000011 pulto.obj (.cinit) + 0000bcb8 0000000d ADC.obj (.cinit) + 0000bcc5 0000000c DAC.obj (.cinit) + 0000bcd1 0000000c log_to_mem.obj (.cinit) + 0000bcdd 0000000a rts2800_fpu32.lib : _lock.obj (.cinit) + 0000bce7 0000000a : exit.obj (.cinit) + 0000bcf1 00000008 RS485.obj (.cinit) + 0000bcf9 00000008 cntrl_adr.obj (.cinit) + 0000bd01 00000008 main.obj (.cinit) + 0000bd09 00000004 bios.obj (.cinit) + 0000bd0d 00000004 rts2800_fpu32.lib : errno.obj (.cinit) + 0000bd11 00000002 --HOLE-- [fill = 0] + +.econst 0 0000c000 00000112 + 0000c000 00000100 DSP2833x_SWPrioritizedPieVect.obj (.econst) + 0000c100 00000009 message.obj (.econst:_$P$T0$1) + 0000c109 00000006 message.obj (.econst:_$P$T1$2) + 0000c10f 00000003 cntrl_adr.obj (.econst) + +.switch 0 0000c112 00000028 + 0000c112 00000028 spise2p.obj (.switch) + +ramfuncs 0 0000c15d 00000023 RUN ADDR = 0000c13a + 0000c15d 00000023 DSP2833x_SysCtrl.obj (ramfuncs) + +.adc_cal 0 00380080 00000007 NOLOAD SECTION + 00380080 00000007 DSP2833x_ADC_cal.obj (.adc_cal) + +.reset 0 003fffc0 00000002 DSECT + 003fffc0 00000002 rts2800_fpu32.lib : boot.obj (.reset) + +vectors 0 003fffc2 00000000 DSECT + +.stack 1 00000400 000003f0 UNINITIALIZED + 00000400 000003f0 --HOLE-- + +DevEmuRegsFile +* 1 00000880 000000d0 UNINITIALIZED + 00000880 000000d0 DSP2833x_GlobalVariableDefs.obj (DevEmuRegsFile) + +FlashRegsFile +* 1 00000a80 00000008 UNINITIALIZED + 00000a80 00000008 DSP2833x_GlobalVariableDefs.obj (FlashRegsFile) + +CsmRegsFile +* 1 00000ae0 00000010 UNINITIALIZED + 00000ae0 00000010 DSP2833x_GlobalVariableDefs.obj (CsmRegsFile) + +AdcMirrorFile +* 1 00000b00 00000010 UNINITIALIZED + 00000b00 00000010 DSP2833x_GlobalVariableDefs.obj (AdcMirrorFile) + +XintfRegsFile +* 1 00000b20 0000001e UNINITIALIZED + 00000b20 0000001e DSP2833x_GlobalVariableDefs.obj (XintfRegsFile) + +CpuTimer0RegsFile +* 1 00000c00 00000008 UNINITIALIZED + 00000c00 00000008 DSP2833x_GlobalVariableDefs.obj (CpuTimer0RegsFile) + +CpuTimer1RegsFile +* 1 00000c08 00000008 UNINITIALIZED + 00000c08 00000008 DSP2833x_GlobalVariableDefs.obj (CpuTimer1RegsFile) + +CpuTimer2RegsFile +* 1 00000c10 00000008 UNINITIALIZED + 00000c10 00000008 DSP2833x_GlobalVariableDefs.obj (CpuTimer2RegsFile) + +PieCtrlRegsFile +* 1 00000ce0 0000001a UNINITIALIZED + 00000ce0 0000001a DSP2833x_GlobalVariableDefs.obj (PieCtrlRegsFile) + +PieVectTableFile +* 1 00000d00 00000100 UNINITIALIZED + 00000d00 00000100 DSP2833x_GlobalVariableDefs.obj (PieVectTableFile) + +DmaRegsFile +* 1 00001000 000000e0 UNINITIALIZED + 00001000 000000e0 DSP2833x_GlobalVariableDefs.obj (DmaRegsFile) + +McbspaRegsFile +* 1 00005000 00000025 UNINITIALIZED + 00005000 00000025 DSP2833x_GlobalVariableDefs.obj (McbspaRegsFile) + +McbspbRegsFile +* 1 00005040 00000025 UNINITIALIZED + 00005040 00000025 DSP2833x_GlobalVariableDefs.obj (McbspbRegsFile) + +ECanaRegsFile +* 1 00006000 00000034 UNINITIALIZED + 00006000 00000034 DSP2833x_GlobalVariableDefs.obj (ECanaRegsFile) + +ECanaLAMRegsFile +* 1 00006040 00000040 UNINITIALIZED + 00006040 00000040 DSP2833x_GlobalVariableDefs.obj (ECanaLAMRegsFile) + +ECanaMOTSRegsFile +* 1 00006080 00000040 UNINITIALIZED + 00006080 00000040 DSP2833x_GlobalVariableDefs.obj (ECanaMOTSRegsFile) + +ECanaMOTORegsFile +* 1 000060c0 00000040 UNINITIALIZED + 000060c0 00000040 DSP2833x_GlobalVariableDefs.obj (ECanaMOTORegsFile) + +ECanaMboxesFile +* 1 00006100 00000100 UNINITIALIZED + 00006100 00000100 DSP2833x_GlobalVariableDefs.obj (ECanaMboxesFile) + +ECanbRegsFile +* 1 00006200 00000034 UNINITIALIZED + 00006200 00000034 DSP2833x_GlobalVariableDefs.obj (ECanbRegsFile) + +ECanbLAMRegsFile +* 1 00006240 00000040 UNINITIALIZED + 00006240 00000040 DSP2833x_GlobalVariableDefs.obj (ECanbLAMRegsFile) + +ECanbMOTSRegsFile +* 1 00006280 00000040 UNINITIALIZED + 00006280 00000040 DSP2833x_GlobalVariableDefs.obj (ECanbMOTSRegsFile) + +ECanbMOTORegsFile +* 1 000062c0 00000040 UNINITIALIZED + 000062c0 00000040 DSP2833x_GlobalVariableDefs.obj (ECanbMOTORegsFile) + +ECanbMboxesFile +* 1 00006300 00000100 UNINITIALIZED + 00006300 00000100 DSP2833x_GlobalVariableDefs.obj (ECanbMboxesFile) + +EPwm1RegsFile +* 1 00006800 00000022 UNINITIALIZED + 00006800 00000022 DSP2833x_GlobalVariableDefs.obj (EPwm1RegsFile) + +EPwm2RegsFile +* 1 00006840 00000022 UNINITIALIZED + 00006840 00000022 DSP2833x_GlobalVariableDefs.obj (EPwm2RegsFile) + +EPwm3RegsFile +* 1 00006880 00000022 UNINITIALIZED + 00006880 00000022 DSP2833x_GlobalVariableDefs.obj (EPwm3RegsFile) + +EPwm4RegsFile +* 1 000068c0 00000022 UNINITIALIZED + 000068c0 00000022 DSP2833x_GlobalVariableDefs.obj (EPwm4RegsFile) + +EPwm5RegsFile +* 1 00006900 00000022 UNINITIALIZED + 00006900 00000022 DSP2833x_GlobalVariableDefs.obj (EPwm5RegsFile) + +EPwm6RegsFile +* 1 00006940 00000022 UNINITIALIZED + 00006940 00000022 DSP2833x_GlobalVariableDefs.obj (EPwm6RegsFile) + +ECap1RegsFile +* 1 00006a00 00000020 UNINITIALIZED + 00006a00 00000020 DSP2833x_GlobalVariableDefs.obj (ECap1RegsFile) + +ECap2RegsFile +* 1 00006a20 00000020 UNINITIALIZED + 00006a20 00000020 DSP2833x_GlobalVariableDefs.obj (ECap2RegsFile) + +ECap3RegsFile +* 1 00006a40 00000020 UNINITIALIZED + 00006a40 00000020 DSP2833x_GlobalVariableDefs.obj (ECap3RegsFile) + +ECap4RegsFile +* 1 00006a60 00000020 UNINITIALIZED + 00006a60 00000020 DSP2833x_GlobalVariableDefs.obj (ECap4RegsFile) + +ECap5RegsFile +* 1 00006a80 00000020 UNINITIALIZED + 00006a80 00000020 DSP2833x_GlobalVariableDefs.obj (ECap5RegsFile) + +ECap6RegsFile +* 1 00006aa0 00000020 UNINITIALIZED + 00006aa0 00000020 DSP2833x_GlobalVariableDefs.obj (ECap6RegsFile) + +EQep1RegsFile +* 1 00006b00 00000040 UNINITIALIZED + 00006b00 00000040 DSP2833x_GlobalVariableDefs.obj (EQep1RegsFile) + +EQep2RegsFile +* 1 00006b40 00000040 UNINITIALIZED + 00006b40 00000040 DSP2833x_GlobalVariableDefs.obj (EQep2RegsFile) + +GpioCtrlRegsFile +* 1 00006f80 0000002e UNINITIALIZED + 00006f80 0000002e DSP2833x_GlobalVariableDefs.obj (GpioCtrlRegsFile) + +GpioDataRegsFile +* 1 00006fc0 00000020 UNINITIALIZED + 00006fc0 00000020 DSP2833x_GlobalVariableDefs.obj (GpioDataRegsFile) + +GpioIntRegsFile +* 1 00006fe0 0000000a UNINITIALIZED + 00006fe0 0000000a DSP2833x_GlobalVariableDefs.obj (GpioIntRegsFile) + +SysCtrlRegsFile +* 1 00007010 00000020 UNINITIALIZED + 00007010 00000020 DSP2833x_GlobalVariableDefs.obj (SysCtrlRegsFile) + +SpiaRegsFile +* 1 00007040 00000010 UNINITIALIZED + 00007040 00000010 DSP2833x_GlobalVariableDefs.obj (SpiaRegsFile) + +SciaRegsFile +* 1 00007050 00000010 UNINITIALIZED + 00007050 00000010 DSP2833x_GlobalVariableDefs.obj (SciaRegsFile) + +XIntruptRegsFile +* 1 00007070 00000010 UNINITIALIZED + 00007070 00000010 DSP2833x_GlobalVariableDefs.obj (XIntruptRegsFile) + +AdcRegsFile +* 1 00007100 0000001e UNINITIALIZED + 00007100 0000001e DSP2833x_GlobalVariableDefs.obj (AdcRegsFile) + +ScibRegsFile +* 1 00007750 00000010 UNINITIALIZED + 00007750 00000010 DSP2833x_GlobalVariableDefs.obj (ScibRegsFile) + +ScicRegsFile +* 1 00007770 00000010 UNINITIALIZED + 00007770 00000010 DSP2833x_GlobalVariableDefs.obj (ScicRegsFile) + +I2caRegsFile +* 1 00007900 00000022 UNINITIALIZED + 00007900 00000022 DSP2833x_GlobalVariableDefs.obj (I2caRegsFile) + +.ebss 1 0000d000 00000fb0 UNINITIALIZED + 0000d000 00000746 RS485.obj (.ebss) + 0000d746 0000001c spise2p.obj (.ebss) + 0000d762 00000018 DSP2833x_CpuTimers.obj (.ebss) + 0000d77a 00000006 DSP2833x_SysCtrl.obj (.ebss) + 0000d780 00000500 measure.obj (.ebss) + 0000dc80 00000181 message.obj (.ebss) + 0000de01 00000015 kanal.obj (.ebss) + 0000de16 00000010 peripher.obj (.ebss) + 0000de26 0000000e ecan.obj (.ebss) + 0000de34 0000000b log_to_mem.obj (.ebss) + 0000de3f 00000001 bios.obj (.ebss) + 0000de40 00000100 crc16.obj (.ebss) + 0000df40 00000049 ADC.obj (.ebss) + 0000df89 00000001 rts2800_fpu32.lib : errno.obj (.ebss) + 0000df8a 0000000a pulto.obj (.ebss) + 0000df94 00000009 DAC.obj (.ebss) + 0000df9d 00000007 main.obj (.ebss) + 0000dfa4 00000004 cntrl_adr.obj (.ebss) + 0000dfa8 00000004 rts2800_fpu32.lib : _lock.obj (.ebss) + 0000dfac 00000004 : exit.obj (.ebss) + +.logg 1 00200000 0000fa00 UNINITIALIZED + 00200000 0000fa00 log_to_mem.obj (.logg) + +CsmPwlFile +* 1 0033fff8 00000008 UNINITIALIZED + 0033fff8 00000008 DSP2833x_GlobalVariableDefs.obj (CsmPwlFile) + +PartIdRegsFile +* 1 00380090 00000001 UNINITIALIZED + 00380090 00000001 DSP2833x_GlobalVariableDefs.obj (PartIdRegsFile) + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +-------- ---- +00008000 .text +0000ba59 C$$EXIT +0000b6bc FS$$DIV +0000b99e I$$DIV +0000b9af I$$MOD +0000b974 L$$DIV +0000b983 L$$MOD +0000b991 UL$$DIV +0000b998 UL$$MOD +00008d14 _ADCINT_ISR +00380080 _ADC_cal +0000df44 _ADC_table +0000c10f _ADDR_ANSWER +0000dfa4 _ADDR_FOR_ALL +0000c110 _ADDR_TERMINAL +00000b00 _AdcMirror +00007100 _AdcRegs +0000b5cc _Anal_output +0000a5af _Answer +0000adbc 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_ECAN1INTA_ISR +0000931e _ECAN1INTB_ISR +00008f0d _ECAP1_INT_ISR +00008f2e _ECAP2_INT_ISR +00008f51 _ECAP3_INT_ISR +00008f72 _ECAP4_INT_ISR +00008f93 _ECAP5_INT_ISR +00008fb4 _ECAP6_INT_ISR +00006040 _ECanaLAMRegs +000060c0 _ECanaMOTORegs +00006080 _ECanaMOTSRegs +00006100 _ECanaMboxes +00006000 _ECanaRegs +00006240 _ECanbLAMRegs +000062c0 _ECanbMOTORegs +00006280 _ECanbMOTSRegs +00006300 _ECanbMboxes +00006200 _ECanbRegs +00006a00 _ECap1Regs +00006a20 _ECap2Regs +00006a40 _ECap3Regs +00006a60 _ECap4Regs +00006a80 _ECap5Regs +00006aa0 _ECap6Regs +00008bed _EMUINT_ISR +00008e41 _EPWM1_INT_ISR +00008d79 _EPWM1_TZINT_ISR +00008e62 _EPWM2_INT_ISR +00008d9a _EPWM2_TZINT_ISR +00008e85 _EPWM3_INT_ISR +00008dbb _EPWM3_TZINT_ISR +00008ea8 _EPWM4_INT_ISR +00008ddc _EPWM4_TZINT_ISR +00008ec9 _EPWM5_INT_ISR +00008dff _EPWM5_TZINT_ISR +00008eea _EPWM6_INT_ISR +00008e20 _EPWM6_TZINT_ISR +00006800 _EPwm1Regs +00006840 _EPwm2Regs +00006880 _EPwm3Regs +000068c0 _EPwm4Regs +00006900 _EPwm5Regs +00006940 _EPwm6Regs +00008fd5 _EQEP1_INT_ISR +00008ff6 _EQEP2_INT_ISR +00006b00 _EQep1Regs +00006b40 _EQep2Regs +0000b8ef _EnableInterrupts +0000de26 _ErrorCount +0000df7f _FILTER_CLIP +00000a80 _FlashRegs +00006f80 _GpioCtrlRegs +00006fc0 _GpioDataRegs +00006fe0 _GpioIntRegs +0000d77e _HSPCLK +0000ae10 _Handlai +000091ab _I2CINT1A_ISR +000091ce _I2CINT2A_ISR +00007900 _I2caRegs +00008c03 _ILLEGAL_ISR +0000df96 _IMPowse +00008bb9 _INT13_ISR +00008bc6 _INT14_ISR +00009434 _INT_NOTUSED_ISR +0000de1e _INcount0 +0000de1f _INcount1 +0000ba21 _InitAdc +0000acea _InitCan +0000b7c6 _InitCpuTimers +0000c13a _InitFlash +0000af87 _InitPeripheralClocks +0000b8a0 _InitPieCtrl +0000ba72 _InitPieVectTable +0000aef9 _InitPll +0000a2e0 _InitSeeprom +0000aed1 _InitSysCtrl +0000b244 _InitXintf +0000b355 _InitXintf16Gpio +0000b2cf _InitXintf32Gpio +0000b5b0 _Init_DAC +0000851a _Init_packMask +000082f3 _Init_sensors +000084a9 _Init_sensors_more +0000d7be _K100 +0000d83a _K_50 +0000d83c _K_T1 +0000d83e _K_T2 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_USER2_ISR +00008c24 _USER3_ISR +00008c2f _USER4_ISR +00008c3a _USER5_ISR +00008c45 _USER6_ISR +00008c50 _USER7_ISR +00008c5b _USER8_ISR +00008c66 _USER9_ISR +00008c71 _USER10_ISR +00008c7c _USER11_ISR +00008c87 _USER12_ISR +00008c92 _SEQ1INT_ISR +00008cb3 _SEQ2INT_ISR +00008cd4 _XINT1_ISR +00008cf5 _XINT2_ISR +00008d14 _ADCINT_ISR +00008d35 _TINT0_ISR +00008d58 _WAKEINT_ISR +00008d79 _EPWM1_TZINT_ISR +00008d9a _EPWM2_TZINT_ISR +00008dbb _EPWM3_TZINT_ISR +00008ddc _EPWM4_TZINT_ISR +00008dff _EPWM5_TZINT_ISR +00008e20 _EPWM6_TZINT_ISR +00008e41 _EPWM1_INT_ISR +00008e62 _EPWM2_INT_ISR +00008e85 _EPWM3_INT_ISR +00008ea8 _EPWM4_INT_ISR +00008ec9 _EPWM5_INT_ISR +00008eea _EPWM6_INT_ISR +00008f0d _ECAP1_INT_ISR +00008f2e _ECAP2_INT_ISR +00008f51 _ECAP3_INT_ISR +00008f72 _ECAP4_INT_ISR +00008f93 _ECAP5_INT_ISR +00008fb4 _ECAP6_INT_ISR +00008fd5 _EQEP1_INT_ISR +00008ff6 _EQEP2_INT_ISR +00009019 _SPIRXINTA_ISR +0000903a _SPITXINTA_ISR +0000905d _MRINTB_ISR +0000907e _MXINTB_ISR +0000909f _MRINTA_ISR +000090c0 _MXINTA_ISR +000090e3 _DINTCH1_ISR +00009104 _DINTCH2_ISR +00009125 _DINTCH3_ISR +00009146 _DINTCH4_ISR +00009167 _DINTCH5_ISR +00009188 _DINTCH6_ISR +000091ab _I2CINT1A_ISR +000091ce _I2CINT2A_ISR +000091ef _SCIRXINTC_ISR +00009210 _SCITXINTC_ISR +00009231 _SCIRXINTA_ISR +00009254 _SCITXINTA_ISR +00009275 _SCIRXINTB_ISR +00009296 _SCITXINTB_ISR +000092b7 _ECAN0INTA_ISR +000092da _ECAN1INTA_ISR +000092fd _ECAN0INTB_ISR +0000931e _ECAN1INTB_ISR +0000933f _XINT3_ISR +00009360 _XINT4_ISR +00009381 _XINT5_ISR +000093a2 _XINT6_ISR +000093c3 _XINT7_ISR +000093e6 _LVF_ISR +00009407 _LUF_ISR +0000942a _PIE_RESERVED +00009434 _INT_NOTUSED_ISR +0000943e _rsvd_ISR +00009448 _RSA_RX_Handler +00009497 _RSB_RX_Handler +000094e4 _RSA_TX_Handler +00009531 _RSB_TX_Handler +0000957e _RS_RX_Handler +000096c9 _RS_TX_Handler +0000973e _setup_arr_cmd_length +00009784 _RS_SetBitMode +000097a3 _RS_Send +000097f5 _RS_BSend +00009822 _RS_SetLineSpeed +00009842 _create_uart_vars +0000984e _setup_uart +00009907 _RS_SetLineMode +00009934 _clear_timer_rs_live +00009939 _test_rs_live +0000993a _setup_leds_line +00009968 _unsetup_leds_line +0000999a _get_Mode +00009b10 _select_tpl_255 +00009b36 _select_tpl_canal +00009bca _get_Buttons +00009dd1 _setup_adc +0000a002 _adc_isr +0000a232 _Seeprom_write +0000a289 _Seeprom_read +0000a2e0 _InitSeeprom +0000a309 _SPISE2P_DRV_init +0000a355 _SPISE2P_DRV_csset +0000a35a _SPISE2P_DRV_csclr +0000a35f _spiSe2pFree +0000a365 _spiSe2pWrite +0000a369 _spiSe2pRead +0000a36d _cpu_timer2_isr +0000a3a5 _SPISE2P_DRV_tick +0000a550 _read_memory +0000a553 _write_memory +0000a556 _get_command +0000a5af _Answer +0000a5f0 _init +0000a5f1 _initload +0000a634 _load +0000a67b _run +0000a67c _peek +0000a6e2 _poke +0000a71d _upload +0000a7bb _xflash +0000a7bc _tflash +0000a7bd _extendbios +0000a82e _Default_params +0000a940 _Load_params +0000a97e _Save_params +0000a9a5 _ReceiveCommandModbus3 +0000aa17 _ReceiveCommandModbus6 +0000aa3d _SendCommandModbus4 +0000aa67 _ReceiveAnswerModbus4 +0000aa8d _timer_Init +0000aaba _main +0000acea _InitCan +0000adbc _CAN_send +0000ae10 _Handlai +0000ae4e _CANa_handler +0000ae9f _CANa_reset_err +0000aed1 _InitSysCtrl +0000aeda _ServiceDog +0000aef1 _DisableDog +0000aef9 _InitPll +0000af87 _InitPeripheralClocks +0000b052 _CsmUnlock +0000b09d _what_is +0000b0ca _cpu_timer1_isr_PULT +0000b244 _InitXintf +0000b2cf _InitXintf32Gpio +0000b355 _InitXintf16Gpio +0000b3ea _DCLK +0000b3f6 _DOUT +0000b402 _RESET +0000b415 _SENDBIT +0000b427 _kanal_Send +0000b562 _Setup_DAC_time +0000b570 _dOUT +0000b57c _wast +0000b581 _dSEND +0000b5b0 _Init_DAC +0000b5cc _Anal_output +0000b618 _Load_runner +0000b6bc FS$$DIV +0000b744 _get_crc_16 +0000b757 _get_crc_16b +0000b782 _get_crc16 +0000b7c6 _InitCpuTimers +0000b811 _ConfigCpuTimer +0000b833 _init_zone7 +0000b88d _pause_us +0000b8a0 _InitPieCtrl +0000b8ef _EnableInterrupts +0000b8fa _c_int00 +0000b940 _filterbat +0000b974 L$$DIV +0000b983 L$$MOD +0000b991 UL$$DIV +0000b998 UL$$MOD +0000b99e I$$DIV +0000b9af I$$MOD +0000b9c0 ___memcpy_ff +0000b9e2 _sqrt +0000ba02 _clear_mem +0000ba21 _InitAdc +0000ba3e __args_main +0000ba59 C$$EXIT +0000ba59 _abort +0000ba5b _exit +0000ba72 _InitPieVectTable +0000ba80 __register_unlock +0000ba84 __register_lock +0000ba88 __nop +0000ba89 _set_cntrl_addr +0000ba90 _DSP28x_usDelay +0000ba94 ___cinit__ +0000ba94 ___etext__ +0000ba94 cinit +0000ba94 etext +0000c000 _PieVectTableInit +0000c10f _ADDR_ANSWER +0000c110 _ADDR_TERMINAL +0000c111 _CNTRL_ADDR_UNIVERSAL +0000c13a _InitFlash +0000c13a _RamfuncsRunStart +0000c15d _RamfuncsLoadStart +0000c180 _RamfuncsLoadEnd +0000d000 _rs_a +0000d380 _rs_b +0000d700 _RS_Len +0000d75e _ccc +0000d762 _CpuTimer0 +0000d76a _CpuTimer1 +0000d772 _CpuTimer2 +0000d77a _SYSCLKOUT +0000d77c _LSPCLK +0000d77e _HSPCLK +0000d780 _CanPowse +0000d781 _CanGO +0000d782 _Maska +0000d792 _READY +0000d793 _TPL_CANS +0000d794 _tpl_cans +0000d795 _cal_addr +0000d796 _pow_addr +0000d797 _period_ready +0000d798 _period_blink +0000d799 _chk +0000d79a _sig +0000d79b _time_1_5sec +0000d79c _time_5msec +0000d79d _time_3sec +0000d79e _time_5sec +0000d79f _low_count +0000d7a1 _err_count +0000d7a7 _lev_count +0000d7ae _lev_quadr +0000d7ba _Caliber_time +0000d7bb _Curr_Edge +0000d7bc _okay +0000d7be _K100 +0000d7c0 _zer_count +0000d7c8 _sens_type +0000d7e0 _sens_pair +0000d7f8 _ext_temp +0000d800 _din_count +0000d820 _ext_diag +0000d828 _powK +0000d83a _K_50 +0000d83c _K_T1 +0000d83e _K_T2 +0000d840 _def_FILTERBAT +0000d880 _adc_filter +0000da40 _out_filter +0000dc00 _zer_filter +0000dc48 _sens_count +0000dc80 _def_cal +0000dcc0 _modbus +0000dd80 _param +0000de01 _digits +0000de11 _readr +0000de16 _Mode +0000de17 _Desk +0000de18 _TermoAD +0000de19 _TermoRS +0000de1a _TermoSW +0000de1b _Kurrent +0000de1c _Kalibro +0000de1d _Owen +0000de1e _INcount0 +0000de1f _INcount1 +0000de20 _DigErr +0000de22 _MUX_GPIO32 +0000de23 _MUX_GPIO48 +0000de24 _DIR_GPIO32 +0000de25 _DIR_GPIO48 +0000de26 _ErrorCount +0000de28 _MessageReceivedCount +0000de2a _MessageTransivedCount +0000de2c _TestMbox1 +0000de2e _TestMbox2 +0000de30 _TestMbox3 +0000de32 _CanTimeOutErrorTR +0000de33 _wait +0000de34 _no_write +0000de35 _never_write +0000de36 _Log +0000de3e _flog +0000de3f _flag_DEBUG +0000de40 _crc_16_tab +0000df40 _adc_table_lem +0000df44 _ADC_table +0000df60 _prev_ok +0000df7c _COUNT_ONE_CANAL +0000df7d _COUNT_DISCHARGE +0000df7e _COUNT_TRANSICIA +0000df7f _FILTER_CLIP +0000df80 _WAKE +0000df82 _WAKE_TIME +0000df89 _errno +0000df8a _isMask +0000df8c _isNumb +0000df8d _quaLamp +0000df8e _Lonely +0000df94 _WAKEpowse +0000df96 _IMPowse +0000df98 _period_dac +0000df99 _time_dac +0000dfa4 _ADDR_FOR_ALL +0000dfa5 _CNTRL_ADDR +0000dfa6 _cntr_addr_c +0000dfa7 _cntr_addr_c_all +0000dfa8 __unlock +0000dfaa __lock +0000dfac __cleanup_ptr +0000dfae __dtors_ptr +00200000 _logs_block +0033fff8 _CsmPwl +00380080 _ADC_cal +00380090 _PartIdRegs +ffffffff ___binit__ +ffffffff ___c_args__ +ffffffff ___pinit__ +ffffffff binit +ffffffff pinit + +[393 symbols] diff --git a/UKSSTMS320F28335.paf2 b/UKSSTMS320F28335.paf2 new file mode 100644 index 0000000..f4edacc Binary files /dev/null and b/UKSSTMS320F28335.paf2 differ diff --git a/UKSSTMS320F28335.pjt b/UKSSTMS320F28335.pjt new file mode 100644 index 0000000..55bb6f4 --- /dev/null +++ b/UKSSTMS320F28335.pjt @@ -0,0 +1,73 @@ +; Code Composer Project File, Version 2.0 (do not modify or remove this line) + +[Project Settings] +ProjectDir="D:\project12\Balsam_167\" +ProjectType=Executable +CPUFamily=TMS320C28XX +Tool="Compiler" +Tool="CustomBuilder" +Tool="DspBiosBuilder" +Tool="Linker" +Config="Debug" +Config="Release" + +[Source Files] +Source="Libraries\rts2800_fpu32.lib" +Source="Source\External\v120\DSP2833x_common\source\DSP2833x_Adc.c" +Source="Source\External\v120\DSP2833x_common\source\DSP2833x_ADC_cal.asm" +Source="Source\External\v120\DSP2833x_common\source\DSP2833x_CpuTimers.c" +Source="Source\External\v120\DSP2833x_common\source\DSP2833x_PieCtrl.c" +Source="Source\External\v120\DSP2833x_common\source\DSP2833x_SWPrioritizedDefaultIsr.c" +Source="Source\External\v120\DSP2833x_common\source\DSP2833x_SWPrioritizedPieVect.c" +Source="Source\External\v120\DSP2833x_common\source\DSP2833x_SysCtrl.c" +Source="Source\External\v120\DSP2833x_common\source\DSP2833x_usDelay.asm" +Source="Source\External\v120\DSP2833x_common\source\DSP2833x_Xintf.c" +Source="Source\External\v120\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c" +Source="Source\Internal\ADC.c" +Source="Source\Internal\bios.c" +Source="Source\Internal\cntrl_adr.c" +Source="Source\Internal\crc16.c" +Source="Source\Internal\DAC.c" +Source="Source\Internal\ecan.c" +Source="Source\Internal\filter_bat2.c" +Source="Source\Internal\kanal.c" +Source="Source\Internal\log_to_mem.c" +Source="Source\Internal\main.c" +Source="Source\Internal\measure.c" +Source="Source\Internal\message.c" +Source="Source\Internal\peripher.c" +Source="Source\Internal\pulto.c" +Source="Source\Internal\RS485.c" +Source="Source\Internal\spise2p.c" +Source="Source\Internal\tools.c" +Source="F28335.cmd" +Source="Source\External\v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" + +["Debug" Settings] +FinalBuildCmd=$(Proj_dir)\bin\hex2000.exe $(Proj_dir)\bin\UKSSTMS320F28335.out -boot -sci8 -map $(Proj_dir)\bin\UKSSTMS320F28335.map -o $(Proj_dir)\bin\UKSSTMS320F28335.hex -i +FinalBuildCmd=$(Proj_dir)\bin\hex2000.exe $(Proj_dir)\bin\UKSSTMS320F28335.out -boot -sci8 -map $(Proj_dir)\bin\UKSSTMS320F28335.map -o $(Proj_dir)\bin\UKSSTMS320F28335.bin -b + +["Compiler" Settings: "Debug"] +Options=-g -pdsw225 -o1 -fr"$(Proj_dir)\Debug" -fs"$(Proj_dir)\Asm" -i"$(Proj_dir)\Source\External\v120\DSP2833x_headers\include" -i"$(Proj_dir)\Source\Internal\Include" -i"$(Proj_dir)\Source\External\v120\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 + +["Compiler" Settings: "Release"] +Options=-pdsw225 -o3 -fr"$(Proj_dir)\Release" -d"LARGE_MODEL" -ml -v28 + +["Linker" Settings: "Debug"] +Options=-c -e_c_int00 -m"$(Proj_dir)\UKSSTMS320F28335.map" -o"$(Proj_dir)\bin\UKSSTMS320F28335.out" -stack0x3f0 -w -x -l"rts2800_fpu32.lib" + +["Linker" Settings: "Release"] +Options=-c -m"$(Proj_dir)\Release\UKSSTMS320F28335.map" -o"$(Proj_dir)\Release\UKSSTMS320F28335.out" -w -x + +["F28335.cmd" Settings: "Debug"] +LinkOrder=1 + +["F28335.cmd" Settings: "Release"] +LinkOrder=1 + +["Source\External\v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Debug"] +LinkOrder=2 + +["Source\External\v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd" Settings: "Release"] +LinkOrder=1 + diff --git a/UKSSTMS320F28335.sbl b/UKSSTMS320F28335.sbl new file mode 100644 index 0000000..a68e5bf Binary files /dev/null and b/UKSSTMS320F28335.sbl differ diff --git a/UKSSTMS320F28335/.ccsproject b/UKSSTMS320F28335/.ccsproject new file mode 100644 index 0000000..269c339 --- /dev/null +++ b/UKSSTMS320F28335/.ccsproject @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/UKSSTMS320F28335/.cproject b/UKSSTMS320F28335/.cproject new file mode 100644 index 0000000..e7b4248 --- /dev/null +++ b/UKSSTMS320F28335/.cproject @@ -0,0 +1,373 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/UKSSTMS320F28335/.gitignore b/UKSSTMS320F28335/.gitignore new file mode 100644 index 0000000..6d4a3d8 --- /dev/null +++ b/UKSSTMS320F28335/.gitignore @@ -0,0 +1,5 @@ +/Debug/ +/Source/ +/.launches/ +/targetConfigs/ +/project.log diff --git a/UKSSTMS320F28335/.project b/UKSSTMS320F28335/.project new file mode 100644 index 0000000..c139f70 --- /dev/null +++ b/UKSSTMS320F28335/.project @@ -0,0 +1,195 @@ + + + UKSSTMS320F28335 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + F28335.cmd + 1 + SRC_ROOT/F28335.cmd + + + UKSSTMS320F28335.pjt + 1 + SRC_ROOT/UKSSTMS320F28335.pjt + + + Debug/UKSSTMS320F28335.out + 1 + EXTERNAL_BUILD_ARTIFACT + + + Libraries/rts2800_fpu32.lib + 1 + SRC_ROOT/Libraries/rts2800_fpu32.lib + + + Source/Internal/ADC.c + 1 + SRC_ROOT/Source/Internal/ADC.c + + + Source/Internal/DAC.c + 1 + SRC_ROOT/Source/Internal/DAC.c + + + Source/Internal/RS485.c + 1 + SRC_ROOT/Source/Internal/RS485.c + + + Source/Internal/bios.c + 1 + SRC_ROOT/Source/Internal/bios.c + + + Source/Internal/cntrl_adr.c + 1 + SRC_ROOT/Source/Internal/cntrl_adr.c + + + Source/Internal/crc16.c + 1 + SRC_ROOT/Source/Internal/crc16.c + + + Source/Internal/ecan.c + 1 + SRC_ROOT/Source/Internal/ecan.c + + + Source/Internal/filter_bat2.c + 1 + SRC_ROOT/Source/Internal/filter_bat2.c + + + Source/Internal/kanal.c + 1 + SRC_ROOT/Source/Internal/kanal.c + + + Source/Internal/log_to_mem.c + 1 + SRC_ROOT/Source/Internal/log_to_mem.c + + + Source/Internal/main.c + 1 + SRC_ROOT/Source/Internal/main.c + + + Source/Internal/measure.c + 1 + SRC_ROOT/Source/Internal/measure.c + + + Source/Internal/message.c + 1 + SRC_ROOT/Source/Internal/message.c + + + Source/Internal/peripher.c + 1 + SRC_ROOT/Source/Internal/peripher.c + + + Source/Internal/pulto.c + 1 + SRC_ROOT/Source/Internal/pulto.c + + + Source/Internal/spise2p.c + 1 + SRC_ROOT/Source/Internal/spise2p.c + + + Source/Internal/tools.c + 1 + SRC_ROOT/Source/Internal/tools.c + + + Source/External/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm + 1 + SRC_ROOT/Source/External/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm + + + Source/External/v120/DSP2833x_common/source/DSP2833x_Adc.c + 1 + SRC_ROOT/Source/External/v120/DSP2833x_common/source/DSP2833x_Adc.c + + + Source/External/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c + 1 + SRC_ROOT/Source/External/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c + + + Source/External/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c + 1 + SRC_ROOT/Source/External/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c + + + Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c + 1 + SRC_ROOT/Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c + + + Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c + 1 + SRC_ROOT/Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c + + + Source/External/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c + 1 + SRC_ROOT/Source/External/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c + + + Source/External/v120/DSP2833x_common/source/DSP2833x_Xintf.c + 1 + SRC_ROOT/Source/External/v120/DSP2833x_common/source/DSP2833x_Xintf.c + + + Source/External/v120/DSP2833x_common/source/DSP2833x_usDelay.asm + 1 + SRC_ROOT/Source/External/v120/DSP2833x_common/source/DSP2833x_usDelay.asm + + + Source/External/v120/DSP2833x_headers/cmd/DSP2833x_Headers_nonBIOS.cmd + 1 + SRC_ROOT/Source/External/v120/DSP2833x_headers/cmd/DSP2833x_Headers_nonBIOS.cmd + + + Source/External/v120/DSP2833x_headers/source/DSP2833x_GlobalVariableDefs.c + 1 + SRC_ROOT/Source/External/v120/DSP2833x_headers/source/DSP2833x_GlobalVariableDefs.c + + + + + SRC_ROOT + $%7BPARENT-1-PROJECT_LOC%7D + + + diff --git a/UKSSTMS320F28335/.settings/com.ti.ccstudio.project.core.prefs b/UKSSTMS320F28335/.settings/com.ti.ccstudio.project.core.prefs new file mode 100644 index 0000000..76e251e --- /dev/null +++ b/UKSSTMS320F28335/.settings/com.ti.ccstudio.project.core.prefs @@ -0,0 +1,4 @@ +ccsVersionValidationPolicy=warning +compilerVersionValidationPolicy=flexible +eclipse.preferences.version=1 +productVersionsValidationPolicy=flexible diff --git a/UKSSTMS320F28335/.settings/org.eclipse.cdt.codan.core.prefs b/UKSSTMS320F28335/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..f653028 --- /dev/null +++ b/UKSSTMS320F28335/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/UKSSTMS320F28335/.settings/org.eclipse.cdt.debug.core.prefs b/UKSSTMS320F28335/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 0000000..2adc7b1 --- /dev/null +++ b/UKSSTMS320F28335/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/UKSSTMS320F28335/.settings/org.eclipse.core.resources.prefs b/UKSSTMS320F28335/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..5dbaf64 --- /dev/null +++ b/UKSSTMS320F28335/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,16 @@ +eclipse.preferences.version=1 +encoding//Debug/Libraries/subdir_rules.mk=UTF-8 +encoding//Debug/Libraries/subdir_vars.mk=UTF-8 +encoding//Debug/Source/External/v120/DSP2833x_common/source/subdir_rules.mk=UTF-8 +encoding//Debug/Source/External/v120/DSP2833x_common/source/subdir_vars.mk=UTF-8 +encoding//Debug/Source/External/v120/DSP2833x_headers/cmd/subdir_rules.mk=UTF-8 +encoding//Debug/Source/External/v120/DSP2833x_headers/cmd/subdir_vars.mk=UTF-8 +encoding//Debug/Source/External/v120/DSP2833x_headers/source/subdir_rules.mk=UTF-8 +encoding//Debug/Source/External/v120/DSP2833x_headers/source/subdir_vars.mk=UTF-8 +encoding//Debug/Source/Internal/subdir_rules.mk=UTF-8 +encoding//Debug/Source/Internal/subdir_vars.mk=UTF-8 +encoding//Debug/makefile=UTF-8 +encoding//Debug/objects.mk=UTF-8 +encoding//Debug/sources.mk=UTF-8 +encoding//Debug/subdir_rules.mk=UTF-8 +encoding//Debug/subdir_vars.mk=UTF-8 diff --git a/UKSSTMS320F28335/28335_RAM_lnk.cmd b/UKSSTMS320F28335/28335_RAM_lnk.cmd new file mode 100644 index 0000000..0db663f --- /dev/null +++ b/UKSSTMS320F28335/28335_RAM_lnk.cmd @@ -0,0 +1,184 @@ +/* +// TI File $Revision: /main/11 $ +// Checkin $Date: April 15, 2009 09:57:28 $ +//########################################################################### +// +// FILE: 28335_RAM_lnk.cmd +// +// TITLE: Linker Command File For 28335 examples that run out of RAM +// +// This ONLY includes all SARAM blocks on the 28335 device. +// This does not include flash or OTP. +// +// Keep in mind that L0 and L1 are protected by the code +// security module. +// +// What this means is in most cases you will want to move to +// another memory map file which has more memory defined. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +//########################################################################### +*/ + +/* ====================================================== +// For Code Composer Studio V2.2 and later +// --------------------------------------- +// In addition to this memory linker command file, +// add the header linker command file directly to the project. +// The header linker command file is required to link the +// peripheral structures to the proper locations within +// the memory map. +// +// The header linker files are found in \DSP2833x_Headers\cmd +// +// For BIOS applications add: DSP2833x_Headers_BIOS.cmd +// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd +========================================================= */ + +/* ====================================================== +// For Code Composer Studio prior to V2.2 +// -------------------------------------- +// 1) Use one of the following -l statements to include the +// header linker command file in the project. The header linker +// file is required to link the peripheral structures to the proper +// locations within the memory map */ + +/* Uncomment this line to include file only for non-BIOS applications */ +/* -l DSP2833x_Headers_nonBIOS.cmd */ + +/* Uncomment this line to include file only for BIOS applications */ +/* -l DSP2833x_Headers_BIOS.cmd */ + +/* 2) In your project add the path to \DSP2833x_headers\cmd to the + library search path under project->build options, linker tab, + library search path (-i). +/*========================================================= */ + +/* Define the memory block start/length for the F28335 + PAGE 0 will be used to organize program sections + PAGE 1 will be used to organize data sections + + Notes: + Memory blocks on F28335 are uniform (ie same + physical memory) in both PAGE 0 and PAGE 1. + That is the same memory region should not be + defined for both PAGE 0 and PAGE 1. + Doing so will result in corruption of program + and/or data. + + L0/L1/L2 and L3 memory blocks are mirrored - that is + they can be accessed in high memory or low memory. + For simplicity only one instance is used in this + linker file. + + Contiguous SARAM memory blocks can be combined + if required to create a larger memory block. +*/ + + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */ + RAMM0 : origin = 0x000050, length = 0x0003B0 + RAML0 : origin = 0x008000, length = 0x001000 + RAML1 : origin = 0x009000, length = 0x001000 + RAML2 : origin = 0x00A000, length = 0x001000 + RAML3 : origin = 0x00B000, length = 0x001000 + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 + RESET : origin = 0x3FFFC0, length = 0x000002 + IQTABLES : origin = 0x3FE000, length = 0x000b50 + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 + BOOTROM : origin = 0x3FF27C, length = 0x000D44 + + +PAGE 1 : + /* BOOT_RSVD is used by the boot ROM for stack. */ + /* This section is only reserved to keep the BOOT ROM from */ + /* corrupting this area during the debug process */ + + BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAML4 : origin = 0x00C000, length = 0x001000 + RAML5 : origin = 0x00D000, length = 0x001000 + RAML6 : origin = 0x00E000, length = 0x001000 + RAML7 : origin = 0x00F000, length = 0x001000 + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ +} + + +SECTIONS +{ + /* Setup for "boot to SARAM" mode: + The codestart section (found in DSP28_CodeStartBranch.asm) + re-directs execution to the start of user code. */ + codestart : > BEGIN, PAGE = 0 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAML0, PAGE = 0 + #else + ramfuncs : > RAML0, PAGE = 0 + #endif +#endif + + .text : > RAML1, PAGE = 0 + .cinit : > RAML0, PAGE = 0 + .pinit : > RAML0, PAGE = 0 + .switch : > RAML0, PAGE = 0 + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAML4, PAGE = 1 + .econst : > RAML5, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + IQmath : > RAML1, PAGE = 0 + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + + /* Uncomment the section below if calling the IQNexp() or IQexp() + functions from the IQMath.lib library in order to utilize the + relevant IQ Math table in Boot ROM (This saves space and Boot ROM + is 1 wait-state). If this section is not uncommented, IQmathTables2 + will be loaded into other memory (SARAM, Flash, etc.) and will take + up space, but 0 wait-state is possible. + */ + /* + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + { + + IQmath.lib (IQmathTablesRam) + + } + */ + + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + ZONE7DATA : > ZONE7B, PAGE = 1 + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */ + csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */ + + /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ \ No newline at end of file diff --git a/UKSSTMS320F28335/postBuildStep_Debug.bat b/UKSSTMS320F28335/postBuildStep_Debug.bat new file mode 100644 index 0000000..a054feb --- /dev/null +++ b/UKSSTMS320F28335/postBuildStep_Debug.bat @@ -0,0 +1,34 @@ +@echo off +setlocal + +for %%I in ("%~dp0..") do set "SRC_ROOT=%%~fI" + +:process_arg +if "%1"=="" goto end_process_arg +set name=%1 +set value= + +:process_arg_value +if NOT "%value%"=="" set value=%value% %2 +if "%value%"=="" set value=%2 +shift +if "%2"=="!" goto set_arg +if "%2"=="" goto set_arg +goto process_arg_value + +:set_arg +set %name%=%value% +shift +shift +goto process_arg +:end_process_arg + +echo. > temp_postBuildStep_Debug.bat + +echo "%SRC_ROOT%\Bin\hex2000.exe" "%SRC_ROOT%\Bin\UKSSTMS320F28335.out" -boot -sci8 -map "%SRC_ROOT%\Bin\UKSSTMS320F28335.map" -o "%SRC_ROOT%\Bin\UKSSTMS320F28335.hex" -i >> temp_postBuildStep_Debug.bat +echo "%SRC_ROOT%\Bin\hex2000.exe" "%SRC_ROOT%\Bin\UKSSTMS320F28335.out" -boot -sci8 -map "%SRC_ROOT%\Bin\UKSSTMS320F28335.map" -o "%SRC_ROOT%\Bin\UKSSTMS320F28335.bin" -b >> temp_postBuildStep_Debug.bat + +call temp_postBuildStep_Debug.bat +del temp_postBuildStep_Debug.bat + +endlocal diff --git a/UKSSTMS320F28335/postBuildStep_Debug.old b/UKSSTMS320F28335/postBuildStep_Debug.old new file mode 100644 index 0000000..d7027dd --- /dev/null +++ b/UKSSTMS320F28335/postBuildStep_Debug.old @@ -0,0 +1,35 @@ +@echo off +pushd ..\..\ +setlocal + +:process_arg +if "%1"=="" goto end_process_arg +set name=%1 +set value= + +:process_arg_value +if NOT "%value%"=="" set value=%value% %2 +if "%value%"=="" set value=%2 +shift +if "%2"=="!" goto set_arg +if "%2"=="" goto set_arg +goto process_arg_value + +:set_arg +set %name%=%value% +shift +shift +goto process_arg +:end_process_arg + +echo. > temp_postBuildStep_Debug.bat + +echo E:\workspace\setcorp\set506\git_project\ukssDimaCccs12\Bin\hex2000.exe E:\workspace\setcorp\set506\git_project\ukssDimaCccs12\Bin\UKSSTMS320F28335.out -boot -sci8 -map E:\workspace\setcorp\set506\git_project\ukssDimaCccs12\Bin\UKSSTMS320F28335.map -o E:\workspace\setcorp\set506\git_project\ukssDimaCccs12\Bin\UKSSTMS320F28335.hex -i >> temp_postBuildStep_Debug.bat +echo E:\workspace\setcorp\set506\git_project\ukssDimaCccs12\Bin\hex2000.exe E:\workspace\setcorp\set506\git_project\ukssDimaCccs12\Bin\UKSSTMS320F28335.out -boot -sci8 -map E:\workspace\setcorp\set506\git_project\ukssDimaCccs12\Bin\UKSSTMS320F28335.map -o E:\workspace\setcorp\set506\git_project\ukssDimaCccs12\Bin\UKSSTMS320F28335.bin -b >> temp_postBuildStep_Debug.bat + +call temp_postBuildStep_Debug.bat +del temp_postBuildStep_Debug.bat +PAUSE + +endlocal +popd diff --git a/cc_build_Debug.log b/cc_build_Debug.log new file mode 100644 index 0000000..1cd25db --- /dev/null +++ b/cc_build_Debug.log @@ -0,0 +1,77 @@ +------------------------ UKSSTMS320F28335.pjt - Debug ------------------------ +[DSP2833x_Adc.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../../../../Debug.lkf" "DSP2833x_Adc.c" + +[DSP2833x_ADC_cal.asm] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../../../../Debug.lkf" "DSP2833x_ADC_cal.asm" + +[DSP2833x_CpuTimers.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../../../../Debug.lkf" "DSP2833x_CpuTimers.c" + +[DSP2833x_PieCtrl.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../../../../Debug.lkf" "DSP2833x_PieCtrl.c" + +[DSP2833x_SWPrioritizedDefaultIsr.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../../../../Debug.lkf" "DSP2833x_SWPrioritizedDefaultIsr.c" + +[DSP2833x_SWPrioritizedPieVect.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../../../../Debug.lkf" "DSP2833x_SWPrioritizedPieVect.c" + +[DSP2833x_SysCtrl.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../../../../Debug.lkf" "DSP2833x_SysCtrl.c" + +[DSP2833x_usDelay.asm] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../../../../Debug.lkf" "DSP2833x_usDelay.asm" + +[DSP2833x_Xintf.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../../../../Debug.lkf" "DSP2833x_Xintf.c" + +[DSP2833x_GlobalVariableDefs.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../../../../Debug.lkf" "DSP2833x_GlobalVariableDefs.c" + +[ADC.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "ADC.c" + +[bios.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "bios.c" + +[cntrl_adr.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "cntrl_adr.c" + +[crc16.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "crc16.c" + +[DAC.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "DAC.c" + +[ecan.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "ecan.c" + +[filter_bat2.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "filter_bat2.c" + +[kanal.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "kanal.c" + +[log_to_mem.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "log_to_mem.c" + +[main.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "main.c" + +[measure.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "measure.c" + +[message.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "message.c" + +[peripher.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "peripher.c" + +[pulto.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "pulto.c" + +[RS485.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "RS485.c" + +[spise2p.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "spise2p.c" + +[tools.c] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -g -pdsw225 -o1 -fr"D:/project12/Balsam_167/Debug" -fs"D:/project12/Balsam_167/Asm" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_headers/include" -i"D:/project12/Balsam_167/Source/Internal/Include" -i"D:/project12/Balsam_167/Source/External/v120/DSP2833x_common/include" -d"_DEBUG" -d"LARGE_MODEL" -md -ml -v28 --float_support=fpu32 -@"../../Debug.lkf" "tools.c" + +[Linking...] "D:\ti\cgt\C2000 Code Generation Tools 5.2.15\bin\cl2000" -@"Debug.lkf" + + +D:\project12\Balsam_167\bin\hex2000.exe D:\project12\Balsam_167\bin\UKSSTMS320F28335.out -boot -sci8 -map D:\project12\Balsam_167\bin\UKSSTMS320F28335.map -o D:\project12\Balsam_167\bin\UKSSTMS320F28335.hex -i +Translating to Intel format... + "D:\project12\Balsam_167\bin\UKSSTMS320F28335.out" ==> .cinit (BOOT LOAD) + "D:\project12\Balsam_167\bin\UKSSTMS320F28335.out" ==> .text (BOOT LOAD) + "D:\project12\Balsam_167\bin\UKSSTMS320F28335.out" ==> ramfuncs (BOOT LOAD) + "D:\project12\Balsam_167\bin\UKSSTMS320F28335.out" ==> .econst (BOOT LOAD) + "D:\project12\Balsam_167\bin\UKSSTMS320F28335.out" ==> .switch (BOOT LOAD) + +D:\project12\Balsam_167\bin\hex2000.exe D:\project12\Balsam_167\bin\UKSSTMS320F28335.out -boot -sci8 -map D:\project12\Balsam_167\bin\UKSSTMS320F28335.map -o D:\project12\Balsam_167\bin\UKSSTMS320F28335.bin -b +Translating to Binary format... + "D:\project12\Balsam_167\bin\UKSSTMS320F28335.out" ==> .cinit (BOOT LOAD) + "D:\project12\Balsam_167\bin\UKSSTMS320F28335.out" ==> .text (BOOT LOAD) + "D:\project12\Balsam_167\bin\UKSSTMS320F28335.out" ==> ramfuncs (BOOT LOAD) + "D:\project12\Balsam_167\bin\UKSSTMS320F28335.out" ==> .econst (BOOT LOAD) + "D:\project12\Balsam_167\bin\UKSSTMS320F28335.out" ==> .switch (BOOT LOAD) + +Build Complete, + 0 Errors, 0 Warnings, 0 Remarks. + Please view the build output for errors and warnings for any custom steps. diff --git a/fixya.bat b/fixya.bat new file mode 100644 index 0000000..9f8c871 --- /dev/null +++ b/fixya.bat @@ -0,0 +1,3 @@ +fuckya.exe *.c +fuckya.exe *.h +