andrey
eb2ff79932
Фронты START/STOP обрабатываются при принятии командного слова CAN/RS, а окончание импульса обслуживается таймером. STOP имеет приоритет, перекрытие выходов исключено, сохранена защита от самопуска при включении. Загрузка параметров больше не подменяет живые команды нагрузки. Добавлены подробные русские комментарии во все собственные C-модули и основные заголовки, описание поведения и host-тест автомата. Обновлены файлы прошивки. Полная сборка TI 22.6.1.LTS и тесты пройдены; проверка на физической плате не выполнялась.
264 lines
8.1 KiB
C
264 lines
8.1 KiB
C
/* Íàñòðîéêà ÀÖÏ è îáðàáîòêà àíàëîãîâûõ âûáîðîê. adc_isr îáíîâëÿåò
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* adc_table_lem[0..3] èç ADCRESULT2..5 >> 4 è âûçûâàåò ðàñ÷¸ò èçìåðåíèé.
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* READY â 166 ÿâëÿåòñÿ ñ÷¸ò÷èêîì äî íóëÿ, íå ôëàãîì ãîòîâíîñòè.
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* WAKE çàäà¸ò îòäåëüíîå âðåìÿ óñòàíîâëåíèÿ èçìåðèòåëüíûõ öåïåé.
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* Íå äîáàâëÿòü îæèäàíèÿ EEPROM/UART â îáðàáîò÷èê âûáîðîê.
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*/
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#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
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#include "DSP2833x_Examples.h" // DSP281x Examples Include File
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#include "DSP2833x_SWPrioritizedIsrLevels.h"
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#include "ADC.h"
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#include "log_to_mem.h"
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#include "RS485.h"
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#include "filter_bat2.h"
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#include "measure.h"
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#include "message.h"
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#include "package.h"
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#include "peripher.h"
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Uint16 adc_table_lem[4];
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Uint16 adc_table_tpl[28]; // Ïîòîìó ÷òî +4 êàëèáð
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unsigned long COUNT_WAIT_ONE_CANAL;
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// Prototype statements for functions found within this file.
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interrupt void adc_isr(void);
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void setup_adc()
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{
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long CLKdiv,HSPCLKdiv,Rate;
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#if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT
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#define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz
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#endif
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#if (CPU_FRQ_100MHZ)
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#define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz
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#endif
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// Specific clock setting for this example:
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// EALLOW;
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// SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK
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// EDIS;
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// Interrupts that are used in this example are re-mapped to
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// ISR functions found within this file.
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EALLOW; // This is needed to write to EALLOW protected register
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PieVectTable.ADCINT = &adc_isr;
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EDIS; // This is needed to disable write to EALLOW protected registers
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InitAdc(); // For this example, init the ADC
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// Enable ADCINT in PIE
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PieCtrlRegs.PIEIER1.bit.INTx6 = 1;
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IER |= M_INT1; // Enable CPU Interrupt 1
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// EINT; // Enable Global interrupt INTM
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// ERTM; // Enable Global realtime interrupt DBGM
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// Configure ADC
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if(Desk==dsk_LOAD)
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{
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AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x0005; // Setup 2 conv's on SEQ1
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AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x3; // òåìïåðàòóðà (êîòîðîé íåò)
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AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // îìåãà
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AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x5; // íàïðóãà 1
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AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x4; // íàïðóãà 2
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AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x7; // òîê 1
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AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x2; // òîê 2
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}
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if(Desk==dsk_BKST)
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{
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AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x0002; // Setup 2 conv's on SEQ1
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AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; //0x5;//0x7; // Setup ADCINA3 as 1st SEQ1 conv.
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AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; //0x4;// Setup ADCINA2 as 2nd SEQ1 conv.
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AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; //0x4;// Setup ADCINA2 as 2nd SEQ1 conv.
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}
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if(Desk==dsk_COMM)
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{
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AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x0006; // Setup 2 conv's on SEQ1
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AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x5; // ñíà÷àëà òîæå áóäóò òåìïåðàòóðû
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AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x4; // Setup ADCINA2 as 2nd SEQ1 conv.
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AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x7; // Setup ADCINA2 as 2nd SEQ1 conv.
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AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x2; // Setup ADCINA2 as 2nd SEQ1 conv.
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AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x3; // Setup ADCINA2 as 2nd SEQ1 conv.
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AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x6; // Setup ADCINA2 as 2nd SEQ1 conv.
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AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x1; // Setup ADCINA2 as 2nd SEQ1 conv.
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}
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if(Desk==dsk_BKSD)
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{
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AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x0000; // Setup 2 conv's on SEQ1
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AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup ADCINA3 as 1st SEQ1 conv.
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}
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if(Desk==dsk_SHKF)
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{
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AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x000F; // Setup 2 conv's on SEQ1
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AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x2; // 380Â Ô1
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AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x3; // 380Â Ô2
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AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x6; // 31Â Ô1
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AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0xC; // 31Â Ô2 ?
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AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0xA; // 31Â UC1
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AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0xB; // 31Â UC2
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AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x7; // 24Â ÏÓ
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AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x4; // 24Â ÏÓ
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AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x5; // 24Â ÏÊ áûëî 5
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AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x1; // 15Â Äð
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AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xE; // +24Â Äò
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AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0x0; // +24Â Äò
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AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0x8; // -24Â Äò áûëî 8
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AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xF;//0xF; // ÄÒ° 1
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AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0xD;//0xD; // ÄÒ° 2
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AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0x9;//0x9;
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}
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AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1
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AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS)
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AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit
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AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode
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AdcRegs.ADCTRL1.bit.CONT_RUN=0;
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AdcRegs.ADCTRL1.bit.ACQ_PS = 15;
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//AdcRegs.ADCTRL1.bit.CPS=1;
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AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
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// Assumes ePWM1 clock is already enabled in InitSysCtrl();
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EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
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EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount
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EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
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EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value
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EPwm1Regs.TBCTL.bit.HSPCLKDIV = CLKMULT;
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EPwm1Regs.TBCTL.bit.CLKDIV=2;
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CLKdiv = 1<<EPwm1Regs.TBCTL.bit.CLKDIV;
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if(EPwm1Regs.TBCTL.bit.HSPCLKDIV) HSPCLKdiv = 2*EPwm1Regs.TBCTL.bit.HSPCLKDIV;
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else HSPCLKdiv = 1;
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Rate = (SYSCLKOUT/(HSPCLKdiv*CLKdiv))/ADC_FREQ;
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EPwm1Regs.TBPRD = Rate; // Set period for ePWM1
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EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start
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if(Desk==dsk_BKSD) COUNT_WAIT_ONE_CANAL = (ADC_FREQ/100);
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else COUNT_WAIT_ONE_CANAL = (ADC_FREQ/20);
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}
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interrupt void adc_isr(void)
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{
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static int count_run_one_canal=0;
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static int cownt_cans=0;
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int code_tpl_canal=0;
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float Temper;
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int i;
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// Set interrupt priority:
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volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
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IER |= M_INT1;
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IER &= MINT1; // Set "global" priority
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PieCtrlRegs.PIEIER1.all &= MG11;//16; // Set "group" priority
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PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
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EINT;
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if(WAKE) WAKE--;
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if(READY) READY--;
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else
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{
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if(Caliber_time)
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{
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if(!--Caliber_time)
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{
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cTermoCal = 0;
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cSaveParam = 1;
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} }
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if(Kurrent)
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{
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for(i=0;i<4;i++)
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{
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adc_table_lem[i] = *((&AdcRegs.ADCRESULT0)+i+2) >>4; Current_count(i);
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} }
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if(Desk==dsk_LOAD)
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{
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Temper = AdcRegs.ADCRESULT1 >> 4;
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modbus[0x63] = Temper;
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Temper = filterbat(&adc_filter[0],Temper);
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modbus[0x1D] = (Temper-DAC_04)/(DAC_20-DAC_04)*(200-40)+40;
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}
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if(Desk==dsk_SHKF)
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{
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for(i=0;i<CLKMULT*3;)
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{
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if (++cownt_cans>=tpl_cans) cownt_cans=0;
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// Èìåííî çäåñü íåò äûð
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// if(sens_type[cownt_cans])
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{
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i++;
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Temper= *(&AdcRegs.ADCRESULT0 + cownt_cans) >>4;
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adc_table_tpl[cownt_cans]=filterbat(&adc_filter[cownt_cans],Temper);
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if(sens_type[cownt_cans]==TERMO_AD) Temper_count(cownt_cans);
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else Power_count(cownt_cans);
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} } }
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if(TermoSW)
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{
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if (count_run_one_canal>COUNT_WAIT_ONE_CANAL/2)
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{
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for(i=0;i<TermoSW;i++)
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{
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Temper = *(&AdcRegs.ADCRESULT0 + i) >>4;
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Temper = filterbat(&adc_filter[TermoSW*cownt_cans+i],Temper);
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adc_table_tpl[TermoSW*cownt_cans+i]=(int)Temper;
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} }
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if (count_run_one_canal++ >= COUNT_WAIT_ONE_CANAL)
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{
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count_run_one_canal=0;
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for(i=0;i<TermoSW;i++)
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Temper_count(TermoSW*cownt_cans+i);
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if (++cownt_cans >= TPL_CANS+2)
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{
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cownt_cans=0;
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}
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code_tpl_canal = cownt_cans;
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if(TermoAD)
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{
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if(cownt_cans == TPL_CANS ) code_tpl_canal = TERMOPAIR-1;
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if(cownt_cans == TPL_CANS+1) code_tpl_canal = TERMOPAIR-2; // ïîòîìó ÷òî 300 è 400 íàîáîðîò
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}
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select_tpl_canal(code_tpl_canal);
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} } }
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// Reinitialize for next ADC sequence
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AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1
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AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
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// Restore registers saved:
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DINT;
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PieCtrlRegs.PIEIER1.all = TempPIEIER;
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return;
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}
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