TMS_STM_Peripher/Balsam_165
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Dimas
2021-10-05 15:55:45 +03:00
commit e7b5a84588
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7
Source/Internal/Include/ADC.h Normal file
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extern Uint16 adc_table_lem[];
extern Uint16 adc_table_tpl[];
void setup_adc(void);

7
Source/Internal/Include/DAC.h Normal file
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//void dSEND_A(unsigned int word);
//void dSEND_B(unsigned int word);
void Anal_output(long vrot, long maxx);
void Init_DAC(void);

443
Source/Internal/Include/GPIO_table.h Normal file
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#define COMM_gpio00_dir 0L
#define COMM_gpio01_dir 0L
#define COMM_gpio02_dir 0L
#define COMM_gpio03_dir 0L
#define COMM_gpio04_dir 0L
#define COMM_gpio05_dir 0L
#define COMM_gpio06_dir 0L
#define COMM_gpio07_dir 0L
#define COMM_gpio08_dir 0L
#define COMM_gpio09_dir 0L
#define COMM_gpio10_dir 0L
#define COMM_gpio11_dir 0L
#define COMM_gpio19_dir 1L // 63 — SPI
#define COMM_gpio20_dir 0L // 64 2:9B mode 2
#define COMM_gpio21_dir 0L // 65 2:9A mode 4
#define COMM_gpio22_dir 0L // 66 2:12C mode 1
#define COMM_gpio23_dir 0L
#define COMM_gpio24_dir 1L // 68 2:12A select
#define COMM_gpio25_dir 1L // 69 2:11C select
#define COMM_gpio26_dir 0L
#define COMM_gpio27_dir 1L // 73 2:11A select
#define COMM_gpio32_dir 1L // 74 2:10B DIOD green
#define COMM_gpio33_dir 0L
#define COMM_gpio34_dir 1L // 142 — SCI
#define COMM_gpio48_dir 1L // 88 2:14C DIOD red
#define COMM_gpio49_dir 1L // 89 2:14B select
#define COMM_gpio50_dir 0L // 90 2:14A input 2
#define COMM_gpio51_dir 0L // 91 2:13C mode !8
#define COMM_gpio52_dir 1L // 94 2:13B select
#define COMM_gpio53_dir 0L // 95 2:13A input 1
#define COMM_gpio58_dir 1L // 100 1:13C rez 1
#define COMM_gpio59_dir 1L // 110 1:13B gotov
#define COMM_gpio60_dir 1L // 111 1:13A led 1
#define COMM_gpio61_dir 1L // 112 1:14C rez 2
#define COMM_gpio62_dir 0L
#define COMM_gpio63_dir 1L // 114 1:14A led 2
//===========================================================================
#define BKSD_gpio00_dir 0L // 5 2:7A oil
#define BKSD_gpio01_dir 1L // 6 2:4A select
#define BKSD_gpio02_dir 0L // 7 2:7B oil
#define BKSD_gpio03_dir 1L // 10 2:4B select
#define BKSD_gpio04_dir 0L // 11 2:7C oil
#define BKSD_gpio05_dir 0L
#define BKSD_gpio06_dir 0L
#define BKSD_gpio07_dir 1L // 16 2:3A select
#define BKSD_gpio08_dir 1L // 17 2:6B select
#define BKSD_gpio09_dir 1L // 18 2:3B select
#define BKSD_gpio10_dir 0L // 19 2:6C oil
#define BKSD_gpio11_dir 1L // 20 2:3C select
#define BKSD_gpio19_dir 1L // 63 — SPI
#define BKSD_gpio20_dir 0L // 64 2:9B mode 2
#define BKSD_gpio21_dir 0L // 65 2:9A mode 4
#define BKSD_gpio22_dir 0L // 66 2:12C mode 1
#define BKSD_gpio23_dir 0L
#define BKSD_gpio24_dir 0L
#define BKSD_gpio25_dir 0L
#define BKSD_gpio26_dir 0L
#define BKSD_gpio27_dir 0L
#define BKSD_gpio32_dir 1L // 74 2:10B DIOD green
#define BKSD_gpio33_dir 0L
#define BKSD_gpio34_dir 1L // 142 — SCI
#define BKSD_gpio48_dir 1L // 88 2:14C DIOD red
#define BKSD_gpio49_dir 0L // 89 2:14B input 2
#define BKSD_gpio50_dir 0L // 90 2:14A input 1
#define BKSD_gpio51_dir 0L // 91 2:13C mode !8
#define BKSD_gpio52_dir 0L
#define BKSD_gpio53_dir 0L
#define BKSD_gpio58_dir 0L
#define BKSD_gpio59_dir 1L // 110 1:13B gotov
#define BKSD_gpio60_dir 1L // 111 1:13A led 1
#define BKSD_gpio61_dir 1L // 112 1:14C rez 2
#define BKSD_gpio62_dir 1L // 113 1:14B rez 1
#define BKSD_gpio63_dir 1L // 114 1:14A led 2
//===========================================================================
#define BKST_gpio00_dir 1L // 5 2:7A select
#define BKST_gpio01_dir 1L // 6 2:4A select
#define BKST_gpio02_dir 0L
#define BKST_gpio03_dir 1L // 10 2:4B select
#define BKST_gpio04_dir 0L
#define BKST_gpio05_dir 0L
#define BKST_gpio06_dir 1L // 13 2:6A select
#define BKST_gpio07_dir 1L // 16 2:3A select
#define BKST_gpio08_dir 1L // 17 2:6B select
#define BKST_gpio09_dir 1L // 18 2:3B select
#define BKST_gpio10_dir 0L
#define BKST_gpio11_dir 1L // 20 2:3C select
#define BKST_gpio19_dir 1L // 63 — SPI
#define BKST_gpio20_dir 0L // 64 2:9B mode 2
#define BKST_gpio21_dir 0L // 65 2:9A mode 4
#define BKST_gpio22_dir 0L // 66 2:12C mode 1
#define BKST_gpio23_dir 0L
#define BKST_gpio24_dir 1L // 68 2:12A select
#define BKST_gpio25_dir 0L
#define BKST_gpio26_dir 0L
#define BKST_gpio27_dir 1L // 73 2:11A select
#define BKST_gpio32_dir 1L // 74 2:10B DIOD green
#define BKST_gpio33_dir 0L
#define BKST_gpio34_dir 1L // 142 — SCI
#define BKST_gpio48_dir 1L // 88 2:14C DIOD red
#define BKST_gpio49_dir 0L
#define BKST_gpio50_dir 1L // 90 2:14A select
#define BKST_gpio51_dir 0L // 91 2:13C mode !8
#define BKST_gpio52_dir 0L
#define BKST_gpio53_dir 1L // 95 2:13A select
#define BKST_gpio58_dir 1L // 100 1:13C rez 1
#define BKST_gpio59_dir 1L // 110 1:13B gotov
#define BKST_gpio60_dir 1L // 111 1:13A led 1
#define BKST_gpio61_dir 1L // 112 1:14C rez 2
#define BKST_gpio62_dir 1L // 113 1:14B led 2
#define BKST_gpio63_dir 0L // 114 1:14A input
//===========================================================================
#define PULT_gpio00_dir 1L // 5 2:7A gotov
#define PULT_gpio01_dir 0L
#define PULT_gpio02_dir 1L // 7 2:7B ro 1
#define PULT_gpio03_dir 0L
#define PULT_gpio04_dir 0L
#define PULT_gpio05_dir 0L
#define PULT_gpio06_dir 1L // 13 2:6A kanal
#define PULT_gpio07_dir 0L
#define PULT_gpio08_dir 1L // 17 2:6B kanal
#define PULT_gpio09_dir 0L
#define PULT_gpio10_dir 0L
#define PULT_gpio11_dir 0L
#define PULT_gpio19_dir 1L // 63 — SPI
#define PULT_gpio20_dir 0L // 64 2:9B mode 2
#define PULT_gpio21_dir 0L // 65 2:9A mode 4
#define PULT_gpio22_dir 0L // 66 2:12C mode 1
#define PULT_gpio23_dir 0L // 67 2:12B button
#define PULT_gpio24_dir 0L // 68 2:12A button
#define PULT_gpio25_dir 0L
#define PULT_gpio26_dir 0L // 72 2:11B button
#define PULT_gpio27_dir 0L // 73 2:11A button
#define PULT_gpio32_dir 1L // 74 2:10B DIOD green
#define PULT_gpio33_dir 0L
#define PULT_gpio34_dir 1L // 142 — SCI
#define PULT_gpio48_dir 1L // 88 2:14C DIOD red
#define PULT_gpio49_dir 0L // 89 2:14B button
#define PULT_gpio50_dir 0L // 90 2:14A button
#define PULT_gpio51_dir 0L // 91 2:13C mode !8
#define PULT_gpio52_dir 0L // 94 2:13B button
#define PULT_gpio53_dir 0L // 95 2:13A button
#define PULT_gpio58_dir 0L
#define PULT_gpio59_dir 0L
#define PULT_gpio60_dir 0L
#define PULT_gpio61_dir 0L
#define PULT_gpio62_dir 0L
#define PULT_gpio63_dir 0L
//===========================================================================
#define PLT2_gpio00_dir 0L
#define PLT2_gpio01_dir 0L
#define PLT2_gpio02_dir 0L
#define PLT2_gpio03_dir 1L // 10 2:4B res_pb
#define PLT2_gpio04_dir 0L // 11 2:7C button
#define PLT2_gpio05_dir 0L // 12 2:4C button
#define PLT2_gpio06_dir 1L // 13 2:6A kanal
#define PLT2_gpio07_dir 0L
#define PLT2_gpio08_dir 1L // 17 2:6B kanal
#define PLT2_gpio09_dir 1L // 18 2:3B res_lb
#define PLT2_gpio10_dir 0L
#define PLT2_gpio11_dir 0L
#define PLT2_gpio19_dir 1L // 63 × SPI
#define PLT2_gpio20_dir 0L // 64 2:9B mode 2
#define PLT2_gpio21_dir 0L // 65 2:9A mode 4
#define PLT2_gpio22_dir 0L // 66 2:12C mode 1
#define PLT2_gpio23_dir 0L // 67 2:12B button
#define PLT2_gpio24_dir 0L // 68 2:12A button
#define PLT2_gpio25_dir 0L // 69 2:11C button
#define PLT2_gpio26_dir 0L // 72 2:11B button
#define PLT2_gpio27_dir 0L // 73 2:11A button
#define PLT2_gpio32_dir 1L // 74 2:10B DIOD green
#define PLT2_gpio33_dir 0L // 75 2:10C button
#define PLT2_gpio34_dir 1L // 142 × SCI
#define PLT2_gpio48_dir 0L // 88 2:14C button
#define PLT2_gpio49_dir 0L // 89 2:14B button
#define PLT2_gpio50_dir 0L // 90 2:14A button
#define PLT2_gpio51_dir 0L // 91 2:13C mode !8
#define PLT2_gpio52_dir 0L // 94 2:13B button
#define PLT2_gpio53_dir 0L // 95 2:13A button
#define PLT2_gpio58_dir 0L
#define PLT2_gpio59_dir 0L
#define PLT2_gpio60_dir 0L
#define PLT2_gpio61_dir 0L
#define PLT2_gpio62_dir 0L
#define PLT2_gpio63_dir 0L
//===========================================================================
#define SHKF_gpio00_dir 0L // 5 2:7A input
#define SHKF_gpio01_dir 0L // 6 2:4A input
#define SHKF_gpio02_dir 0L // 7 2:7B input
#define SHKF_gpio03_dir 0L // 10 2:4B input
#define SHKF_gpio04_dir 0L // 11 2:7C input
#define SHKF_gpio05_dir 0L // 12 2:4C input
#define SHKF_gpio06_dir 0L // 13 2:6A input
#define SHKF_gpio07_dir 0L // 16 2:3A input
#define SHKF_gpio08_dir 0L // 17 2:6B input
#define SHKF_gpio09_dir 0L // 18 2:3B input
#define SHKF_gpio10_dir 0L // 19 2:6C input
#define SHKF_gpio11_dir 0L // 20 2:3C input
#define SHKF_gpio19_dir 1L // 63 — SPI
#define SHKF_gpio20_dir 0L // 64 2:9B mode 2
#define SHKF_gpio21_dir 0L // 65 2:9A mode 4
#define SHKF_gpio22_dir 0L // 66 2:12C mode 1
#define SHKF_gpio23_dir 0L // 67 2:12B input
#define SHKF_gpio24_dir 0L // 68 2:12A input
#define SHKF_gpio25_dir 0L // 69 2:11C input
#define SHKF_gpio26_dir 0L // 72 2:11B input
#define SHKF_gpio27_dir 0L // 73 2:11A input
#define SHKF_gpio32_dir 0L // 74 2:10B input
#define SHKF_gpio33_dir 0L // 75 2:10C input
#define SHKF_gpio34_dir 1L // 142 — SCI
#define SHKF_gpio48_dir 1L // 88 2:14C DIOD red
#define SHKF_gpio49_dir 0L // 89 2:14B input
#define SHKF_gpio50_dir 0L // 90 2:14A input
#define SHKF_gpio51_dir 0L // 91 2:13C mode !8
#define SHKF_gpio52_dir 0L // 94 2:13B input
#define SHKF_gpio53_dir 0L // 95 2:13A input
#define SHKF_gpio58_dir 1L // 100 1:13C rez 1
#define SHKF_gpio59_dir 1L // 110 1:13B gotov
#define SHKF_gpio60_dir 1L // 111 1:13A led 1
#define SHKF_gpio61_dir 1L // 112 1:14C rez 2
#define SHKF_gpio62_dir 0L
#define SHKF_gpio63_dir 1L // 114 1:14A led 2
//===========================================================================
#define LOAD_gpio00_dir 0L
#define LOAD_gpio01_dir 1L // 6 2:4A led 2
#define LOAD_gpio02_dir 0L
#define LOAD_gpio03_dir 1L // 10 2:4B res_out 2
#define LOAD_gpio04_dir 0L
#define LOAD_gpio05_dir 0L
#define LOAD_gpio06_dir 0L // 13 2:6A omega d
#define LOAD_gpio07_dir 1L // 16 2:3A led 1
#define LOAD_gpio08_dir 0L // 17 2:6B start 1
#define LOAD_gpio09_dir 1L // 18 2:3B res_out 1
#define LOAD_gpio10_dir 0L
#define LOAD_gpio11_dir 0L // 20 2:3C res_in 0
#define LOAD_gpio19_dir 1L // 63 — SPI
#define LOAD_gpio20_dir 0L // 64 2:9B mode 2
#define LOAD_gpio21_dir 0L // 65 2:9A mode 4
#define LOAD_gpio22_dir 0L // 66 2:12C mode 1
#define LOAD_gpio23_dir 0L
#define LOAD_gpio24_dir 0L
#define LOAD_gpio25_dir 0L
#define LOAD_gpio26_dir 0L
#define LOAD_gpio27_dir 0L
#define LOAD_gpio32_dir 1L // 74 2:10B DIOD green
#define LOAD_gpio33_dir 0L
#define LOAD_gpio34_dir 1L // 142 — SCI
#define LOAD_gpio48_dir 1L // 88 2:14C DIOD red
#define LOAD_gpio49_dir 0L
#define LOAD_gpio50_dir 0L
#define LOAD_gpio51_dir 0L // 91 2:13C mode !8
#define LOAD_gpio52_dir 0L
#define LOAD_gpio53_dir 0L
#define LOAD_gpio58_dir 1L // 100 1:13C stop_dptb
#define LOAD_gpio59_dir 1L // 110 1:13B csdac
#define LOAD_gpio60_dir 1L // 111 1:13A didac
#define LOAD_gpio61_dir 1L // 112 1:14C gotov
#define LOAD_gpio62_dir 1L // 113 1:14B start_dptb
#define LOAD_gpio63_dir 1L // 114 1:14A clkdac
//===========================================================================
#define DSTR_gpio00_dir 1L // 5 2:7A gotov pb
#define DSTR_gpio01_dir 1L // 6 2:4A led 2
#define DSTR_gpio02_dir 0L
#define DSTR_gpio03_dir 1L // 10 2:4B res pb
#define DSTR_gpio04_dir 0L
#define DSTR_gpio05_dir 1L // 12 2:4C led 6
#define DSTR_gpio06_dir 1L // 13 2:6A gotov lb
#define DSTR_gpio07_dir 1L // 16 2:3A led 1
#define DSTR_gpio08_dir 0L
#define DSTR_gpio09_dir 1L // 18 2:3B res lb
#define DSTR_gpio10_dir 0L
#define DSTR_gpio11_dir 1L // 20 2:3C led 5
#define DSTR_gpio19_dir 1L // 63 — SPI
#define DSTR_gpio20_dir 0L // 64 2:9B mode 2
#define DSTR_gpio21_dir 0L // 65 2:9A mode 4
#define DSTR_gpio22_dir 0L // 66 2:12C mode 1
#define DSTR_gpio23_dir 0L // 67 2:12B qg 4
#define DSTR_gpio24_dir 0L // 68 2:12A qg 2
#define DSTR_gpio25_dir 0L // 69 2:11C 110% 2
#define DSTR_gpio26_dir 0L // 72 2:11B qg3
#define DSTR_gpio27_dir 0L // 73 2:11A qg1
#define DSTR_gpio32_dir 1L // 74 2:10B DIOD green / red 3
#define DSTR_gpio33_dir 0L // 75 2:10C input
#define DSTR_gpio34_dir 1L // 142 — SCI
#define DSTR_gpio48_dir 1L // 88 2:14C DIOD red / led 4
#define DSTR_gpio49_dir 0L // 89 2:14B 90% 2
#define DSTR_gpio50_dir 0L // 90 2:14A 110% 1
#define DSTR_gpio51_dir 0L // 91 2:13C mode !8
#define DSTR_gpio52_dir 0L // 94 2:13B qg 5
#define DSTR_gpio53_dir 0L // 95 2:13A 90% 1
#define DSTR_gpio58_dir 0L // 100 1:13C +24 lb
#define DSTR_gpio59_dir 0L // 110 1:13B res cslb
#define DSTR_gpio60_dir 0L // 111 1:13A res lb
#define DSTR_gpio61_dir 0L // 112 1:14C +24 pb
#define DSTR_gpio62_dir 0L // 113 1:14B res cspb
#define DSTR_gpio63_dir 0L // 114 1:14A res pb
//===========================================================================
#define COMM_GPADIR (COMM_gpio00_dir ) + (COMM_gpio01_dir<<1) + (COMM_gpio02_dir<<2) + (COMM_gpio03_dir<<3) + \
(COMM_gpio04_dir<<4) + (COMM_gpio05_dir<<5) + (COMM_gpio06_dir<<6) + (COMM_gpio07_dir<<7) + \
(COMM_gpio08_dir<<8) + (COMM_gpio09_dir<<9) + (COMM_gpio10_dir<<10)+ (COMM_gpio11_dir<<11)+ \
(COMM_gpio19_dir<<19)+ \
(COMM_gpio20_dir<<20)+ (COMM_gpio21_dir<<21)+ (COMM_gpio22_dir<<22)+ (COMM_gpio23_dir<<23)+ \
(COMM_gpio24_dir<<24)+ (COMM_gpio25_dir<<25)+ (COMM_gpio26_dir<<26)+ (COMM_gpio27_dir<<27);
#define COMM_GPBDIR (COMM_gpio32_dir )+ (COMM_gpio33_dir<<1) + (COMM_gpio34_dir<<2 )+ \
(COMM_gpio48_dir<<16)+ (COMM_gpio49_dir<<17)+ (COMM_gpio50_dir<<18)+ (COMM_gpio51_dir<<19)+ \
(COMM_gpio52_dir<<20)+ (COMM_gpio53_dir<<21)+ \
(COMM_gpio58_dir<<26)+ (COMM_gpio59_dir<<27)+ \
(COMM_gpio60_dir<<28)+ (COMM_gpio61_dir<<29)+ (COMM_gpio62_dir<<30)+ (COMM_gpio63_dir<<31);
#define BKSD_GPADIR (BKSD_gpio00_dir ) + (BKSD_gpio01_dir<<1) + (BKSD_gpio02_dir<<2) + (BKSD_gpio03_dir<<3) + \
(BKSD_gpio04_dir<<4) + (BKSD_gpio05_dir<<5) + (BKSD_gpio06_dir<<6) + (BKSD_gpio07_dir<<7) + \
(BKSD_gpio08_dir<<8) + (BKSD_gpio09_dir<<9) + (BKSD_gpio10_dir<<10)+ (BKSD_gpio11_dir<<11)+ \
(BKSD_gpio19_dir<<19)+ \
(BKSD_gpio20_dir<<20)+ (BKSD_gpio21_dir<<21)+ (BKSD_gpio22_dir<<22)+ (BKSD_gpio23_dir<<23)+ \
(BKSD_gpio24_dir<<24)+ (BKSD_gpio25_dir<<25)+ (BKSD_gpio26_dir<<26)+ (BKSD_gpio27_dir<<27);
#define BKSD_GPBDIR (BKSD_gpio32_dir )+ (BKSD_gpio33_dir<<1) + (BKSD_gpio34_dir<<2 )+ \
(BKSD_gpio48_dir<<16)+ (BKSD_gpio49_dir<<17)+ (BKSD_gpio50_dir<<18)+ (BKSD_gpio51_dir<<19)+ \
(BKSD_gpio52_dir<<20)+ (BKSD_gpio53_dir<<21)+ \
(BKSD_gpio58_dir<<26)+ (BKSD_gpio59_dir<<27)+ \
(BKSD_gpio60_dir<<28)+ (BKSD_gpio61_dir<<29)+ (BKSD_gpio62_dir<<30)+ (BKSD_gpio63_dir<<31);
#define BKST_GPADIR (BKST_gpio00_dir ) + (BKST_gpio01_dir<<1) + (BKST_gpio02_dir<<2) + (BKST_gpio03_dir<<3) + \
(BKST_gpio04_dir<<4) + (BKST_gpio05_dir<<5) + (BKST_gpio06_dir<<6) + (BKST_gpio07_dir<<7) + \
(BKST_gpio08_dir<<8) + (BKST_gpio09_dir<<9) + (BKST_gpio10_dir<<10)+ (BKST_gpio11_dir<<11)+ \
(BKST_gpio19_dir<<19)+ \
(BKST_gpio20_dir<<20)+ (BKST_gpio21_dir<<21)+ (BKST_gpio22_dir<<22)+ (BKST_gpio23_dir<<23)+ \
(BKST_gpio24_dir<<24)+ (BKST_gpio25_dir<<25)+ (BKST_gpio26_dir<<26)+ (BKST_gpio27_dir<<27);
#define BKST_GPBDIR (BKST_gpio32_dir )+ (BKST_gpio33_dir<<1) + (BKST_gpio34_dir<<2 )+ \
(BKST_gpio48_dir<<16)+ (BKST_gpio49_dir<<17)+ (BKST_gpio50_dir<<18)+ (BKST_gpio51_dir<<19)+ \
(BKST_gpio52_dir<<20)+ (BKST_gpio53_dir<<21)+ \
(BKST_gpio58_dir<<26)+ (BKST_gpio59_dir<<27)+ \
(BKST_gpio60_dir<<28)+ (BKST_gpio61_dir<<29)+ (BKST_gpio62_dir<<30)+ (BKST_gpio63_dir<<31);
#define PULT_GPADIR (PULT_gpio00_dir ) + (PULT_gpio01_dir<<1) + (PULT_gpio02_dir<<2) + (PULT_gpio03_dir<<3) + \
(PULT_gpio04_dir<<4) + (PULT_gpio05_dir<<5) + (PULT_gpio06_dir<<6) + (PULT_gpio07_dir<<7) + \
(PULT_gpio08_dir<<8) + (PULT_gpio09_dir<<9) + (PULT_gpio10_dir<<10)+ (PULT_gpio11_dir<<11)+ \
(PULT_gpio19_dir<<19)+ \
(PULT_gpio20_dir<<20)+ (PULT_gpio21_dir<<21)+ (PULT_gpio22_dir<<22)+ (PULT_gpio23_dir<<23)+ \
(PULT_gpio24_dir<<24)+ (PULT_gpio25_dir<<25)+ (PULT_gpio26_dir<<26)+ (PULT_gpio27_dir<<27);
#define PULT_GPBDIR (PULT_gpio32_dir )+ (PULT_gpio33_dir<<1) + (PULT_gpio34_dir<<2 )+ \
(PULT_gpio48_dir<<16)+ (PULT_gpio49_dir<<17)+ (PULT_gpio50_dir<<18)+ (PULT_gpio51_dir<<19)+ \
(PULT_gpio52_dir<<20)+ (PULT_gpio53_dir<<21)+ \
(PULT_gpio58_dir<<26)+ (PULT_gpio59_dir<<27)+ \
(PULT_gpio60_dir<<28)+ (PULT_gpio61_dir<<29)+ (PULT_gpio62_dir<<30)+ (PULT_gpio63_dir<<31);
#define PLT2_GPADIR (PLT2_gpio00_dir ) + (PLT2_gpio01_dir<<1) + (PLT2_gpio02_dir<<2) + (PLT2_gpio03_dir<<3) + \
(PLT2_gpio04_dir<<4) + (PLT2_gpio05_dir<<5) + (PLT2_gpio06_dir<<6) + (PLT2_gpio07_dir<<7) + \
(PLT2_gpio08_dir<<8) + (PLT2_gpio09_dir<<9) + (PLT2_gpio10_dir<<10)+ (PLT2_gpio11_dir<<11)+ \
(PLT2_gpio19_dir<<19)+ \
(PLT2_gpio20_dir<<20)+ (PLT2_gpio21_dir<<21)+ (PLT2_gpio22_dir<<22)+ (PLT2_gpio23_dir<<23)+ \
(PLT2_gpio24_dir<<24)+ (PLT2_gpio25_dir<<25)+ (PLT2_gpio26_dir<<26)+ (PLT2_gpio27_dir<<27);
#define PLT2_GPBDIR (PLT2_gpio32_dir )+ (PLT2_gpio33_dir<<1) + (PLT2_gpio34_dir<<2 )+ \
(PLT2_gpio48_dir<<16)+ (PLT2_gpio49_dir<<17)+ (PLT2_gpio50_dir<<18)+ (PLT2_gpio51_dir<<19)+ \
(PLT2_gpio52_dir<<20)+ (PLT2_gpio53_dir<<21)+ \
(PLT2_gpio58_dir<<26)+ (PLT2_gpio59_dir<<27)+ \
(PLT2_gpio60_dir<<28)+ (PLT2_gpio61_dir<<29)+ (PLT2_gpio62_dir<<30)+ (PLT2_gpio63_dir<<31);
#define SHKF_GPADIR (SHKF_gpio00_dir ) + (SHKF_gpio01_dir<<1) + (SHKF_gpio02_dir<<2) + (SHKF_gpio03_dir<<3) + \
(SHKF_gpio04_dir<<4) + (SHKF_gpio05_dir<<5) + (SHKF_gpio06_dir<<6) + (SHKF_gpio07_dir<<7) + \
(SHKF_gpio08_dir<<8) + (SHKF_gpio09_dir<<9) + (SHKF_gpio10_dir<<10)+ (SHKF_gpio11_dir<<11)+ \
(SHKF_gpio19_dir<<19)+ \
(SHKF_gpio20_dir<<20)+ (SHKF_gpio21_dir<<21)+ (SHKF_gpio22_dir<<22)+ (SHKF_gpio23_dir<<23)+ \
(SHKF_gpio24_dir<<24)+ (SHKF_gpio25_dir<<25)+ (SHKF_gpio26_dir<<26)+ (SHKF_gpio27_dir<<27);
#define SHKF_GPBDIR (SHKF_gpio32_dir )+ (SHKF_gpio33_dir<<1) + (SHKF_gpio34_dir<<2 )+ \
(SHKF_gpio48_dir<<16)+ (SHKF_gpio49_dir<<17)+ (SHKF_gpio50_dir<<18)+ (SHKF_gpio51_dir<<19)+ \
(SHKF_gpio52_dir<<20)+ (SHKF_gpio53_dir<<21)+ \
(SHKF_gpio58_dir<<26)+ (SHKF_gpio59_dir<<27)+ \
(SHKF_gpio60_dir<<28)+ (SHKF_gpio61_dir<<29)+ (SHKF_gpio62_dir<<30)+ (SHKF_gpio63_dir<<31);
#define LOAD_GPADIR (LOAD_gpio00_dir ) + (LOAD_gpio01_dir<<1) + (LOAD_gpio02_dir<<2) + (LOAD_gpio03_dir<<3) + \
(LOAD_gpio04_dir<<4) + (LOAD_gpio05_dir<<5) + (LOAD_gpio06_dir<<6) + (LOAD_gpio07_dir<<7) + \
(LOAD_gpio08_dir<<8) + (LOAD_gpio09_dir<<9) + (LOAD_gpio10_dir<<10)+ (LOAD_gpio11_dir<<11)+ \
(LOAD_gpio19_dir<<19)+ \
(LOAD_gpio20_dir<<20)+ (LOAD_gpio21_dir<<21)+ (LOAD_gpio22_dir<<22)+ (LOAD_gpio23_dir<<23)+ \
(LOAD_gpio24_dir<<24)+ (LOAD_gpio25_dir<<25)+ (LOAD_gpio26_dir<<26)+ (LOAD_gpio27_dir<<27);
#define LOAD_GPBDIR (LOAD_gpio32_dir )+ (LOAD_gpio33_dir<<1) + (LOAD_gpio34_dir<<2 )+ \
(LOAD_gpio48_dir<<16)+ (LOAD_gpio49_dir<<17)+ (LOAD_gpio50_dir<<18)+ (LOAD_gpio51_dir<<19)+ \
(LOAD_gpio52_dir<<20)+ (LOAD_gpio53_dir<<21)+ \
(LOAD_gpio58_dir<<26)+ (LOAD_gpio59_dir<<27)+ \
(LOAD_gpio60_dir<<28)+ (LOAD_gpio61_dir<<29)+ (LOAD_gpio62_dir<<30)+ (LOAD_gpio63_dir<<31);
#define DSTR_GPADIR (DSTR_gpio00_dir ) + (DSTR_gpio01_dir<<1) + (DSTR_gpio02_dir<<2) + (DSTR_gpio03_dir<<3) + \
(DSTR_gpio04_dir<<4) + (DSTR_gpio05_dir<<5) + (DSTR_gpio06_dir<<6) + (DSTR_gpio07_dir<<7) + \
(DSTR_gpio08_dir<<8) + (DSTR_gpio09_dir<<9) + (DSTR_gpio10_dir<<10)+ (DSTR_gpio11_dir<<11)+ \
(DSTR_gpio19_dir<<19)+ \
(DSTR_gpio20_dir<<20)+ (DSTR_gpio21_dir<<21)+ (DSTR_gpio22_dir<<22)+ (DSTR_gpio23_dir<<23)+ \
(DSTR_gpio24_dir<<24)+ (DSTR_gpio25_dir<<25)+ (DSTR_gpio26_dir<<26)+ (DSTR_gpio27_dir<<27);
#define DSTR_GPBDIR (DSTR_gpio32_dir )+ (DSTR_gpio33_dir<<1) + (DSTR_gpio34_dir<<2 )+ \
(DSTR_gpio48_dir<<16)+ (DSTR_gpio49_dir<<17)+ (DSTR_gpio50_dir<<18)+ (DSTR_gpio51_dir<<19)+ \
(DSTR_gpio52_dir<<20)+ (DSTR_gpio53_dir<<21)+ \
(DSTR_gpio58_dir<<26)+ (DSTR_gpio59_dir<<27)+ \
(DSTR_gpio60_dir<<28)+ (DSTR_gpio61_dir<<29)+ (DSTR_gpio62_dir<<30)+ (DSTR_gpio63_dir<<31);
//===========================================================================
// No more.
//===========================================================================

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/****************************************************************/
/* TMS320C32 */
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */
/****************************************************************
RS485.h
****************************************************************
* Ïðîöåäóðû ðàáîòû ñ UART *
****************************************************************/
#ifndef _RS485
#define _RS485
#ifdef __cplusplus
extern "C" {
#endif
//#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
//#include "DSP2833x_Sci.h"
//#include "cntrl_adr.h"
//#include "params.h"
#define COM_1 1
#define COM_2 2
#define MAX_RECEIVE_LENGTH 400 // 80 //150
#define MAX_SEND_LENGTH 400 //150
#define TIME_WAIT_RS_BYTE_OUT 1000
#define TIME_WAIT_RS_LOST_BYTE 100
#define RS_TIME_OUT (SECOND*10)
#define Rec_Bloc_Begin 0x200000
#define Rec_Bloc_End 0x2F0000
#define Rec_Bloc_Length (Rec_Bloc_End-Rec_Bloc_Begin)
/* Message RS declaration */
typedef struct
{
volatile struct SCI_REGS *SciRegs;
unsigned int commnumber; // Íîìåð ïîðòà
unsigned long RS_Length; // Äëèíà ïàêåòà
unsigned int *pRS_RecvPtr; // Áóôåð ïðèåìà
unsigned int *pRS_SendPtr; // Áóôåð ïîñûëêè
unsigned int *pRecvPtr;
unsigned int RS_PrevCmd; // Ïðåäûäóùàà êîììàíäà
unsigned int RS_Cmd; // Òåêóùàà êîììàíäà
unsigned int RS_Header[MAX_RECEIVE_LENGTH]; // Çàãîëîâîê
unsigned int flag_TIMEOUT_to_Send; // Ôëàã îæèäàíèà òàéìàóòà íà îòñûëêó
unsigned int flag_TIMEOUT_to_Receive; // Ôëàã îæèäàíèà òàéìàóòà íà ïðèåì
unsigned int RS_DataReady; // Ôëàã ãîòîâíîñòè RS äàííûõ
unsigned int buffer[MAX_SEND_LENGTH]; // Áóôåð äëà îòñûëêè ïî RS
unsigned int addr_answer; // àäðåñ êóäà îòâå÷àòü â ðåæèìå âåäóùåãî
unsigned int addr_recive; // àäðåñ ïî êîòîðîìó íàñ çàïðîñèëè
unsigned int flag_LEADING; // Ôëàã ðåæèìà êîíòðîëëåðà (ïî óìîë÷àíèþ âåäîìûé)
unsigned long RS_RecvLen;
unsigned long RS_SLength; // Äëèíà ïàêåòà äëà ïîñûëêè
unsigned long RS_SendLen; // Êîëè÷åñòâî áàéò óæå ïåðåäàëè
char RS_SendBlockMode; // Ðåæèì ïåðåäà÷è
char RS_Flag9bit; // äëà RS485????????
int BS_LoadOK; // Ôëàã óñïåøíîñòè ïðèåìà áëîêà
int RS_FlagBegin;
int RS_HeaderCnt;
int RS_FlagSkiping;
unsigned long curr_baud;
unsigned long time_wait_rs_out;
} RS_DATA;
extern RS_DATA rs_a,rs_b;
extern unsigned int
RS_Len[70]; /* Äåéñòâèòåëüíàà äëèíà êîìàíäû (îòëàäî÷íîé) + 1 */
interrupt void RSA_RX_Handler(void);
interrupt void RSA_TX_Handler(void);
interrupt void RSB_RX_Handler(void);
interrupt void RSB_TX_Handler(void);
/* èíèöèëèçàöèà ïåðåìåííûõ rs_a,rs_b*/
void create_uart_vars(char size_cmd15);
/** Ïîâòîðíàà èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà, èñïîëüçóåòñà ïîñëå ïîäâèñà */
/** Íàñòðîéêà ðåæèìà ïðèåìà/ïåðåäà÷è */
void RS_SetBitMode(RS_DATA *rs_arr, int n);
/** Ïîñûëêà áëîêà áàéòîâ.
Ïîñûëàåò ìàññèâà 32-áèòíûõ öåëûõ ÷èñåë ñòàðøèå áèòû äîëæíû áûòü 0.
@precondition Ðàáîòà ô-öèè çàâèñèò îò ìàêðî RS_TRANSMIT_INTR
@param buf àäðåñ ìàññèâà
@param len êîëè÷åñòâî áàéò
@see RS_BSend, RS_TRANSMIT_INTR
*/
int RS_Send(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len);
/** Ïîñûëêà áëîêà óïàêîâàííûõ áàéòîâ.
@precondition Ðàáîòà ô-öèè çàâèñèò îò ìàêðî RS_TRANSMIT_INTR
@param buf àäðåñ ìàññèâà
@param len êîëè÷åñòâî 8-áèòíûõ áàéò
@see RS_Send, RS_TRANSMIT_INTR
*/
int RS_BSend(RS_DATA *rs_arr,unsigned int *pBuf, unsigned long len);
/** Èíèöèàëèçàöèà ïîñëåäîâàòåëüíîãî ïîðòà */
void setup_uart(char commnumber,unsigned long speed_baud); /* speed_baud - ñêîðîñòü ëèíèè â áîäàõ */
void RS_SetLineMode(RS_DATA *rs_arr, int bit, char parity, int stop);
void RS_SetLineSpeed(RS_DATA *rs_arr, unsigned long speed);
// Transmit a character from the SCI'
#define SCI_send(x,y) x->SciRegs->SCITXBUF=(unsigned char)(y)
// Îæèäàíèå çàâåðøåíèà ïåðåäà÷è UART
// wait for TRDY =1 for empty state
#define RS_Wait4OK(x) while(!(x->SciRegs->SCICTL2.bit.TXEMPTY))
/** Ïåðåêëþ÷åíèå ëèíèè íà ïðèåì */
#define RS_Line_to_receive(x) if(x->commnumber==COM_2) GpioDataRegs.GPBDAT.bit.GPIO34 = 1;
/** Ïåðåêëþ÷åíèå ëèíèè íà ïåðåäà÷ó */
#define RS_Line_to_send(x) if(x->commnumber==COM_2) GpioDataRegs.GPBDAT.bit.GPIO34 = 0;
/** Ðàçðåøåíèå ïðåðûâàíèé ïî ïîëó÷åíèþ ñèìâîëà è îøèáêàì îò UART */
#define enableUARTInt(x) x->SciRegs->SCICTL2.all=2
#define enableUARTIntW(x) x->SciRegs->SCICTL2.all=1
void clear_timer_rs_live(RS_DATA *rs_arr);
void test_rs_live(RS_DATA *rs_arr);
#ifdef __cplusplus
}
#endif
#endif /* _RS485 */

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/****************************************************************/
/* TMS320C32 */
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */
/****************************************************************/
/* Bios_dsp.h */
/****************************************************************/
/* Îñíîâíûå êîììàíäû BIOS */
/****************************************************************/
#ifndef _BIOS_DSP
#define _BIOS_DSP
#ifdef __cplusplus
extern "C" {
#endif
#define BM_PACKED 1
#define BM_CHAR32 0
#define CHIEF 1
#define SLAVE 0
#define ADR_FOR_SPECIAL 0x100
#define CMD_MODBUS_3 3
#define ANS_MODBUS_3 4
#define CMD_MODBUS_15 5
#define CMD_MODBUS_6 6
#define ANS_MODBUS_6 7
#define CMD_MODBUS_16 16
/*
CMD_MODBUS_3 = 3,
ANS_MODBUS_3 = 4,
CMD_MODBUS_15 = 5,
CMD_MODBUS_6 = 6,
ANS_MODBUS_6 = 7,
CMD_MODBUS_16 = 16,
*/
enum {
CMD_LOAD=51, CMD_UPLOAD, CMD_RUN, CMD_XFLASH, CMD_TFLASH,
CMD_PEEK, CMD_POKE, CMD_INITLOAD, CMD_INIT,CMD_EXTEND,
CMD_VECTOR=61,
CMD_IMPULSE,
/* ñòàíäàðòíûå êîìàíäû */
CMD_STD=65, CMD_STD_ANS
};
enum {false=0, true};
/** Âîçâðàùàåò íîìåð êîììàíäû, åñëè åñòü èëè -1 åñëè òðàíçàêöèé íå áûëî */
int get_command(RS_DATA *rs_arr);
/** Ñòàíäàðòíûé îòâåò, áåç ïàðàìåòðîâ */
void Answer(RS_DATA *rs_arr,int n);
/* íà÷àëüíûå óñòàíîâêè (íå ðàáîòàåò)*/
void init(RS_DATA *rs_arr);
/**@name Êîììàíäû
* Êîììàíäû, âûçûâàåìûå ÷åðåç ïîñëåäîâàòåëüíûé êàíàë*/
//@{
/** Èíèöèèðîâàòü çàãðóçêó áëîêà.
Íàñòðàèâàåò ïðèåì áëîêà äàííûõ */
void initload(RS_DATA *rs_arr);
/** Çàãðóçêà áëîêà.
Âûçûâàåòñà ïîñëå çàãðóçêè áëîêà ÷åðåç RS */
void load(RS_DATA *rs_arr);
/** Âûïîëíèòü ïðîãðàììó â ôîðìàòå Serial Boot.
@precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà
Àäðåñ ïðîãðàììû áåðåòñà èç çàãîëîâêà è
ñðàâíèâàåòñà ñ ïåðåìåííîé RecvPtr, çàïîëíàåìîé â ô-öèè load
@see load */
void run (RS_DATA *rs_arr);
/** Ïðî÷èòàòü à÷åéêó ïàìàòè */
void peek(RS_DATA *rs_arr);
/** Çàïèñàòü â à÷åéêó ïàìàòè */
void poke(RS_DATA *rs_arr);
/** Ïåðåäàòü áëîê ïàìàòè */
void upload(RS_DATA *rs_arr);
/** Ïðîøèòü XILINX.
@precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà
Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è
ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load,
òàê æå ñìîòðèò ìàãè÷åñêîå ñëîâî â íà÷àëå ïðîøèâêè
@see load */
void xflash(RS_DATA *rs_arr);
/** Ïðîøèòü TMS.
@precondition Äîëæíà áûòü ïðîèçâåäåíà çàãðóçêà áëîêà
Àäðåñ è äëèíà ïðîøèâêè áåðåòñà èç çàãîëîâêà è
ñðàâíèâàåòñà ñ ïåðåìåííûìè RecvPtr è Length, çàïîëíàåìûìè â ô-öèè load
@see load */
void tflash(RS_DATA *rs_arr);
/* ðàñøèðåííûå êîìàíäû äëà áèîñà */
void extendbios(RS_DATA *rs_arr);
void write_memory(unsigned long addr, unsigned int data);
unsigned int read_memory(unsigned long addr);
//@}
#ifdef __cplusplus
}
#endif
#endif/* _BIOS_DSP */

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/****************************************************************/
/* TMS320C32 */
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2000 ã. */
/****************************************************************
cntrl_adr.h
****************************************************************
* Àäðåñ êîíòðîëëåðà *
****************************************************************/
#ifndef _CNTRL_ADR
#define _CNTRL_ADR
#ifdef __cplusplus
extern "C" {
#endif
/** àäðåñ êîíòðîëëåðà äëà ïîñûëêè âñåì ÀÈÍàì */
extern int ADDR_FOR_ALL;
/** àäðåñ êîíòðîëëåðà äëà ïîñûëêè îòâåòà */
extern const int ADDR_ANSWER;
/** àäðåñà òåðìèíàëà äëà ïîñûëêè îòâåòà */
extern const int ADDR_TERMINAL;
/* Àäðåñ êîíòðîëëåðà */
extern int CNTRL_ADDR;
/* Óíèâåðñàëüíûé àäðåñ êîíòðîëëåðà */
extern const int CNTRL_ADDR_UNIVERSAL;
/** Óñòàíîâêà àäðåñà êîíòðîëëåðà äëà ïðîøèâêè */
void set_cntrl_addr (int cntrl_addr,int cntrl_addr_for_all);
extern int cntr_addr_c;
extern int cntr_addr_c_all;
#ifdef __cplusplus
}
#endif
#endif /* _CNTRL_ADR */

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typedef unsigned short WORD;
typedef unsigned char byte;
unsigned int get_crc_ccitt(unsigned int crc, unsigned int *buf, unsigned long size );
unsigned int get_crc_16(unsigned int crc,unsigned int *buf,unsigned long size );
unsigned int get_crc_16b(unsigned int crc,unsigned int *buf,unsigned long size );
int get_crc16(unsigned int *buf, int size );

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void InitCan(int Port, int DevNum);
void CAN_send(int Port, int data[], int Addr);
extern int CAN_input_data[];

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#ifndef _FILTER_BAT2
#define _FILTER_BAT2
#ifdef __cplusplus
extern "C" {
#endif
#define K1_FILTER_BATTER2_1HZ 0.0000096
#define K2_FILTER_BATTER2_1HZ 1.94468056
#define K3_FILTER_BATTER2_1HZ -0.94471895
#define K1_FILTER_BATTER2_3HZ 0.00008766
#define K2_FILTER_BATTER2_3HZ 1.97347532
#define K3_FILTER_BATTER2_3HZ -0.97382594
#define K1_FILTER_BATTER2_5HZ 0.00024135
#define K2_FILTER_BATTER2_5HZ 1.95581276
#define K3_FILTER_BATTER2_5HZ -0.95677816
#define K1_FILTER_BATTER2_10HZ 0.00094411
#define K2_FILTER_BATTER2_10HZ 1.91126422
#define K3_FILTER_BATTER2_10HZ -0.91504065
typedef struct { float k_0;
float k_1;
float k_2;
float i_0;
float i_1;
float i_2;
float u_0;
float u_1;
float u_2;
} FILTERBAT;
#define DEF_FILTERBAT { K1_FILTER_BATTER2_5HZ, \
K2_FILTER_BATTER2_5HZ, \
K3_FILTER_BATTER2_5HZ, \
0,0,0,0,0,0}
float filterbat(FILTERBAT *b, float InpVarCurr);
#ifdef __cplusplus
}
#endif
#endif /* _FILTER_BAT2 */

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void kanal_Send(int adr, long dat, int dot);

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/****************************************************************/
/* TMS320C32 */
/* ====== BIOS, ÊËÀÈÍ, ÊËÂÑÏ ====== */
/* ÖÍÈÈ ÑÝÒ (ñ) 1998-2001ã. */
/****************************************************************/
/* log_to_mem.h
****************************************************************
* Çàïèñü ëîãîâ â ïàìyòü *
****************************************************************/
#ifndef _LOG_TO_MEM
#define _LOG_TO_MEM
#ifdef __cplusplus
extern "C" {
#endif
/* Îïðåäåëåíèa äëa ðàáîòû ëîããåðà */
#define LOG_PAGE_START 0x0200000
#define LOG_PAGE_LEN 0xF000
extern int no_write, never_write; // Ôëàãè, ÷òîáû íå ïèñàòü (åñëè ÷òî)
typedef struct
{
unsigned long Start;
unsigned long Finis;
unsigned long Adres;
unsigned int Circl;
} LOG;
extern LOG Log;
/* Çàïèñü ñëîâa â ïàìàòü, ãäå ëîãè ëåæàò */
#define Log_to_mem(x) *(int *)(Log.Adres++) = x
/* Ïðîâåðêà ãðàíèöû ïàìàòè äëà ëîãîâ */
#define Test_mem_limit(x) if(Log.Adres > (Log.Finis - x)) Log.Adres = Log.Start
/* Î÷èñòêà ïàìàòè (îáíóëåíèå) */
void clear_mem();
#ifdef __cplusplus
}
#endif
#endif /* _LOG_TO_MEM */

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// âãâ
#ifndef _MEASURE
#define _MEASURE
interrupt void cpu_timer1_isr_SENS(void);
void Init_sensors(void);
void Init_packMask(void);
void measure_all(void);
void Temper_count(int chan);
void Current_count(int chan);
void Power_count(int chan);
void Init_sensors_more(void);
int er_anal(int term, long * count, int edge, int pre);
typedef union
{
struct
{
unsigned int Tear :1;
unsigned int res1 :1;
unsigned int Wry :1;
unsigned int Out :1;
unsigned int Over :1;
unsigned int Hyper :1;
unsigned int Contr :1;
unsigned int res2 :1;
unsigned int Stop :1;
unsigned int Ready :1;
unsigned int Discr1 :1;
unsigned int Discr2 :1;
unsigned int Discr3 :1;
unsigned int Discr4 :1;
unsigned int Ignor :1;
unsigned int Bypas :1;
} bit;
unsigned int all;
} ERROR;
typedef union
{
struct
{
unsigned int Error :1;
unsigned int Alarm :1;
unsigned int OverHeat :1;
unsigned int SubHeat :1;
unsigned int OutHeat :1;
unsigned int Test_lamp :1;
} bit;
unsigned int all;
} FLAG;
#define NOER 0xC000
#define EROR 0x01FF
#define READY_FREQ (500.0 * 2)// Ãö
#define BLINK_FREQ 2 // Ãö
#define BLINK_TIME (READY_FREQ / BLINK_FREQ)
#define CANPOWSE 20
#define ADC_FREQ 5000//3885//777//2000//20000 //777 //3885 // Ãö (777*5)
#define DAC_FREQ 300//5 // Ãö
#define LOAD_TIME 30//15 // sec
extern unsigned int Caliber_time;
#define SENS_ERR_WAIT 10
#define maximum_bright 10
#define Pi 3.1415926535897932384626433832795
#define Pi_2 1.5707963267948966192313216916398
#define tmp_T_0 84.31 // 68Om
#define tmp_T_1 234.19 // 100Om
#define tmp_A1_0 540.0 // êàíàë 1 68Îì
#define tmp_A2_0 500.0 // êàíàë 1 100Îì
#define tmp_A1_1 1055.0 // êàíàë 2 68Îì
#define tmp_A2_1 1060.0 // êàíàë 2 100Îì
#define ZERO 27
#define mka300 2040
#define mka400 2700
#define C100 1540
#define C150 2310
#define Cooling 5 // (°Ñ) Ãèñòåðåçèñ ïî ñíàòèþ ïåðåãðåâà
#define COSPi6 0.86602540378443864676372317075294
#define RADIX2 1.4142135623730950488016887242097
#define POWER_380 1 // ïèòàíèå 380Â
#define POWER_38O 2 // ïèòàíèå 380Â
#define POWER_31 3 // ïèòàíèå 31Â
#define POWER_27 4 // ïèòàíèå 24Â
#define POWER_24 5 // ïèòàíèå 24Â
#define POWER_15 6 // ïèòàíèå 15Â
#define TERMO_AD 7 // òåðìîäàò÷èê ìåëêîñõåìà
#define CURRENT 0 // òîê
#define VOLTAGE 1 // íàïðàæåíèå
extern int TPL_CANS,tpl_cans;
extern int READY;
extern FILTERBAT filter[];
extern FILTERBAT adc_filter[];
extern FILTERBAT out_filter[];
extern int sens_type[];
extern ERROR * sens_error;
extern int * sens_hi_edge;
extern int * sens_lo_edge;
extern unsigned long WAKEpowse;
extern unsigned long STOPpowse;
extern float tmpK1,tmpK2;
extern float tmpK1_50,tmpK2_50;
extern unsigned long Lonely;
extern unsigned int CanPowse,CanGO;
extern unsigned int Maska[][8];
#endif //_MEASURE

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#ifndef MESSAGE_H
#define MESSAGE_H
typedef unsigned char CHAR;
#define ANSWER_LEN 0x80 //70 // 16+16+16+16+6
#define REPLY_LEN 0x19
#define byte_hi byte_1
#define byte_lo byte_0
typedef struct
{
unsigned char Address; // Àäðåñ êîíòðîëëåðà
unsigned char Number; // Íîìåð êîìàíäû
BAITE byte0;
BAITE byte1;
BAITE byte2;
BAITE byte3;
BAITE byte4;
BAITE byte5;
BAITE byte6;
BAITE byte7;
unsigned char crc_lo;
unsigned char crc_hi;
unsigned char add_byte;
} CMD_TO_TMS;
extern WORDE* Modbus;
extern int modbus[];
extern LONGE* outputs;
extern int DataAnalog1,DataAnalog2;
void ReceiveCommandModbus3(RS_DATA *rs_arr);
void ReceiveCommandModbus6(RS_DATA *rs_arr);
void Save_params(void);
void Load_params(void);
void Default_params(void);
void calc_temper_koef(void);
#endif //MESSAGE_H

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#ifndef PACKAGE
#define PACKAGE
#define BALSAM
#define DIODES
#define NEWPULT
#define NEWBKSS
#define ONBOARDCALIBER
#define TERMOPAIR 14
#define CURRENTOS (TERMOPAIR*2)
#define DATASTART 24
//-----------------------------------------------
#ifdef BALSAM
#define adr_TRN1 1
#define adr_TRN2 2
#define adr_POW1 3
#define adr_POW2 4
#define adr_LOA1 5
#define adr_LOA2 6
#define adr_ENG1 7
#define adr_PLT3 8
#define adr_SHKF 9
//-------------------
#define adr_REC1 0xff
#define adr_REC2 0xff
#define adr_INV1 0xff
#define adr_INV2 0xff
#define adr_BRK1 0xff
#define adr_BRK2 0xff
#define adr_ENG2 0xff
#define adr_PLT1 0xff
#define adr_PLT2 0xff
#define adr_DSTR 0xff
#endif
//-----------------------------------------------
#define dsk_COMM 1
#define dsk_BKSD 2
#define dsk_BKST 3
#define dsk_PULT 4
#define dsk_EPLT 5
#define dsk_SHKF 6
#define dsk_LOAD 7
#define dsk_DSTR 8
//-----------------------------------------------
//-----------------------------------------------
#define TPL_TRN 10
#define TPL_POW 8
#define TPL_BRK 12
#define TPL_ENG 8
//-----------------------------------------------
#define start_sens_error 0
#define start_sens_hi_edge 48
#define start_sens_lo_edge 72
#define InputRep0 Modbus[0].bit.bitA
#define InputRep1 Modbus[0].bit.bitB
#define InputRep2 Modbus[0].bit.bitC
#define Inputs Modbus[0x10]
#define bTestLamp KeyPressed.bit.bit00
#define bSecretBt KeyPressed.bit.bit01
#define bTermoCal KeyPressed.bit.bit02
#define bDoor_One KeyPressed.bit.bit03
#define bDoor_Two KeyPressed.bit.bit04
#define Cancount (modbus+0x60) // ïàóçà ìåæäó I ïîñûëêàìè CAN
#define Bright (modbus+0x62) // àðêîñòü ñèãíàëüíûõ ëàìïî÷åê
#define Brightness modbus[0x62] // àðêîñòü ñèãíàëüíûõ ëàìïî÷åê
#define m_FAST 0
#define m_SLOW 1
#define Zero_lev (modbus+0x70)
#define DAC_max() modbus[0x78] // 751//0x0000 804
#define DAC_min() modbus[0x79] // 2162//0x0FFF 2373
#define DAC_cal() modbus[0x7A]
#define Caliber (modbus+0x78) // ïàóçà ìåæäó I ïîñûëêàìè CAN
#define K300_1 Caliber[0]
#define K300_2 Caliber[1]
#define K400_1 Caliber[2]
#define K400_2 Caliber[3]
#define K100_D Caliber[0]
#define K150_D Caliber[1]
#define K100_1 Caliber[0]
#define K100_2 Caliber[1]
#define K150_1 Caliber[2]
#define K150_2 Caliber[3]
#define K380_1 Caliber[4]
#define K380_2 Caliber[5]
#define LastMode Modbus[126].all
#define Commands Modbus[127].all
#define cTestLamp Modbus[127].bit.bit0
#define cDefParam Modbus[127].bit.bit1
#define cSaveParam Modbus[127].bit.bit2
#define cLoadParam Modbus[127].bit.bit3
#define cTermoCal Modbus[127].bit.bit4
#define cKoefCalc Modbus[127].bit.bit5
#define cSecretBt Modbus[127].bit.bit6
#define cUMPreset Modbus[127].bit.bit6
#define cUMPstart Modbus[127].bit.bit7
#define cInitDac Modbus[127].bit.bit8
#define cCalibrDac Modbus[127].bit.bit9
/*
#define cUMPstart Modbus[127].bit.bit8
#define cUMPreset Modbus[127].bit.bit9
#define cInitDac Modbus[127].bit.bitA
#define cCalibrDac Modbus[127].bit.bitB
*/
#define cReset Modbus[127].bit.bitF
#endif //PACKAGE

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#include "DSP2833x_Device.h" // DSP281x Headerfile Include File
extern int Mode,Desk,TermoAD,TermoRS,TermoSW,Currentoz;
// READY ---------------------------------------------------------
static inline void dat_READY(int x)
{ if(Desk==dsk_LOAD) GpioDataRegs.GPBDAT.bit.GPIO61=!x; else
GpioDataRegs.GPBDAT.bit.GPIO59=!x; }
static inline void set_READY(void)
{ if(Desk==dsk_LOAD) GpioDataRegs.GPBCLEAR.bit.GPIO61=1; else
GpioDataRegs.GPBCLEAR.bit.GPIO59=1; }
static inline void clear_READY(void)
{ if(Desk==dsk_LOAD) GpioDataRegs.GPBSET.bit.GPIO61=1; else
GpioDataRegs.GPBSET.bit.GPIO59=1; }
static inline void toggle_READY(void)
{ if(Desk==dsk_LOAD) GpioDataRegs.GPBTOGGLE.bit.GPIO61=1;else
GpioDataRegs.GPBTOGGLE.bit.GPIO59=1;}
// LED OUT 1 -----------------------------------------------------
static inline void dat_LED_OUT_1(int x)
{ if(Desk==dsk_BKST || Desk==dsk_COMM)
GpioDataRegs.GPBDAT.bit.GPIO60=!x; else
if(Desk==dsk_LOAD) GpioDataRegs.GPADAT.bit.GPIO7=!x; else
GpioDataRegs.GPBDAT.bit.GPIO60=x; }
static inline void set_LED_OUT_1(void)
{ if(Desk==dsk_BKST || Desk==dsk_COMM)
GpioDataRegs.GPBCLEAR.bit.GPIO60=1; else
if(Desk==dsk_LOAD) GpioDataRegs.GPACLEAR.bit.GPIO7=1; else
GpioDataRegs.GPBSET.bit.GPIO60=1; }
static inline void clear_LED_OUT_1(void)
{ if(Desk==dsk_BKST || Desk==dsk_COMM)
GpioDataRegs.GPBSET.bit.GPIO60=1; else
if(Desk==dsk_LOAD) GpioDataRegs.GPASET.bit.GPIO7=1; else
GpioDataRegs.GPBCLEAR.bit.GPIO60=1; }
static inline void toggle_LED_OUT_1(void)
{ if(Desk==dsk_LOAD) GpioDataRegs.GPATOGGLE.bit.GPIO7=1; else
GpioDataRegs.GPBTOGGLE.bit.GPIO60=1;}
// LED OUT 2 -----------------------------------------------------
static inline void dat_LED_OUT_2(int x)
{ if(Desk==dsk_LOAD) GpioDataRegs.GPADAT.bit.GPIO1=!x; else
if(Desk==dsk_BKST) GpioDataRegs.GPBDAT.bit.GPIO62=!x; else
if(Desk==dsk_COMM) GpioDataRegs.GPBDAT.bit.GPIO63=!x; else
GpioDataRegs.GPBDAT.bit.GPIO63=x; }
static inline void set_LED_OUT_2(void)
{ if(Desk==dsk_LOAD) GpioDataRegs.GPACLEAR.bit.GPIO1=1; else
if(Desk==dsk_BKST) GpioDataRegs.GPBCLEAR.bit.GPIO62=1; else
if(Desk==dsk_COMM) GpioDataRegs.GPBCLEAR.bit.GPIO63=1; else
GpioDataRegs.GPBSET.bit.GPIO63=1; }
static inline void clear_LED_OUT_2(void)
{ if(Desk==dsk_LOAD) GpioDataRegs.GPASET.bit.GPIO7=1; else
if(Desk==dsk_BKST) GpioDataRegs.GPBSET.bit.GPIO62=1; else
if(Desk==dsk_COMM) GpioDataRegs.GPBSET.bit.GPIO63=1; else
GpioDataRegs.GPBCLEAR.bit.GPIO63=1; }
static inline void toggle_LED_OUT_2(void)
{ if(Desk==dsk_LOAD) GpioDataRegs.GPATOGGLE.bit.GPIO1=1; else
if(Desk==dsk_BKST) GpioDataRegs.GPBTOGGLE.bit.GPIO62=1;else
GpioDataRegs.GPBTOGGLE.bit.GPIO63=1;}
// RES OUT 1 -----------------------------------------------------
static inline void dat_RES_OUT_1(int x)
{
if(Desk==dsk_LOAD || Desk==dsk_EPLT)
GpioDataRegs.GPADAT.bit.GPIO9=!x; else
if(Desk==dsk_BKSD) GpioDataRegs.GPBDAT.bit.GPIO62=!x; else
GpioDataRegs.GPBDAT.bit.GPIO58=!x; }
static inline void set_RES_OUT_1(void)
{
if(Desk==dsk_LOAD || Desk==dsk_EPLT)
GpioDataRegs.GPACLEAR.bit.GPIO9=1; else
if(Desk==dsk_BKSD) GpioDataRegs.GPBCLEAR.bit.GPIO62=1; else
GpioDataRegs.GPBCLEAR.bit.GPIO58=1; }
static inline void clear_RES_OUT_1(void)
{
if(Desk==dsk_LOAD || Desk==dsk_EPLT)
GpioDataRegs.GPASET.bit.GPIO9=1; else
if(Desk==dsk_BKSD) GpioDataRegs.GPBSET.bit.GPIO62=1; else
GpioDataRegs.GPBSET.bit.GPIO58=1; }
static inline void toggle_RES_OUT_1(void)
{
if(Desk==dsk_LOAD || Desk==dsk_EPLT)
GpioDataRegs.GPATOGGLE.bit.GPIO9=1; else
if(Desk==dsk_BKSD) GpioDataRegs.GPBTOGGLE.bit.GPIO62=1;else
GpioDataRegs.GPBTOGGLE.bit.GPIO58=1;}
// RES OUT 2 -----------------------------------------------------
static inline void dat_RES_OUT_2(int x)
{ if(Desk==dsk_LOAD || Desk==dsk_EPLT)
GpioDataRegs.GPADAT.bit.GPIO3=!x; else
GpioDataRegs.GPBDAT.bit.GPIO61=x; }
static inline void set_RES_OUT_2(void)
{ if(Desk==dsk_LOAD || Desk==dsk_EPLT)
GpioDataRegs.GPACLEAR.bit.GPIO3=1; else
GpioDataRegs.GPBCLEAR.bit.GPIO61=1; }
static inline void clear_RES_OUT_2(void)
{ if(Desk==dsk_LOAD || Desk==dsk_EPLT)
GpioDataRegs.GPASET.bit.GPIO3=1; else
GpioDataRegs.GPBSET.bit.GPIO61=1; }
static inline void toggle_RES_OUT_2(void)
{ if(Desk==dsk_LOAD || Desk==dsk_EPLT)
GpioDataRegs.GPATOGGLE.bit.GPIO3=1; else
GpioDataRegs.GPBTOGGLE.bit.GPIO61=1;}
// START DPTB -----------------------------------------------------
static inline void dat_START_DPTB(int x)
{ GpioDataRegs.GPBDAT.bit.GPIO62=x; }
static inline void set_START_DPTB(void)
{ GpioDataRegs.GPBSET.bit.GPIO62=1; }
static inline void clear_START_DPTB(void)
{ GpioDataRegs.GPBCLEAR.bit.GPIO62=1; }
static inline void toggle_START_DPTB(void)
{ GpioDataRegs.GPBTOGGLE.bit.GPIO62=1;}
// STOP DPTB -----------------------------------------------------
static inline void dat_STOP_DPTB(int x)
{ GpioDataRegs.GPBDAT.bit.GPIO58=x; }
static inline void set_STOP_DPTB(void)
{ GpioDataRegs.GPBSET.bit.GPIO58=1; }
static inline void clear_STOP_DPTB(void)
{ GpioDataRegs.GPBCLEAR.bit.GPIO58=1; }
static inline void toggle_STOP_DPTB(void)
{ GpioDataRegs.GPBTOGGLE.bit.GPIO58=1;}
extern LONGE KeyPressed;
void select_tpl_canal(int n_tpl);
void get_Mode(void);
void get_Buttons(void);

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//void what_is(void);
interrupt void cpu_timer1_isr_PULT(void);

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/*=====================================================================
File name : SPISE2P.H
Originator : Settu Duraisamy
C2000 Applications Team
Texas Instruments
Description :
Header file containing object definitions, proto type
declaration and default object initializers for
SPI Serial EEPROM driver using VSPI
Date : 30/6/2003 (DD/MM/YYYY)
=======================================================================*/
#ifndef __SPISE2P_H__
#define __SPISE2P_H__
// ¨ìêîñòü ïàìàòè â áàéòàõ
#define SEEPROM_LEN 0x10000
#define NULL 0
#define SIXTEEN_BIT 15
#define EIGHT_BIT 07
/***************************************************************/
/* Configurable Parameter for SPI bus Serial EEPROM */
/***************************************************************/
#define SPISE2P_DATA_WIDTH SIXTEEN_BIT//EIGHT_BIT
#define SPISE2P_ADDR_WIDTH SIXTEEN_BIT
#define SPIBAUD_REG_VAL 1//12
#define SPICLK_PHASE 1
#define SPICLK_POLARITY 0
#define SPIBAUD_RATE 100000
//10000000
/**************************************************************/
/**************************************************************/
/* Serial EEPROM Command words, left justified */
#define SPISE2P_READ_CMD 0x0300
#define SPISE2P_WRITE_CMD 0x0200
#define SPISE2P_WRDI_CMD 0x0400
#define SPISE2P_WREN_CMD 0x0600
#define SPISE2P_RDSR_CMD 0x0500
#define SPISE2P_WRSR_CMD 0x0100
#define SPISE2P_RDID_CMD 0x0A00
#define SPISE2P_DUMMY_DATA 0x0000
#define SPISE2P_BUSY_MASK 0x01
/* Symbolic constant for SPICCR to transfer 8bit or 16 bit value*/
#define SPISE2P_TFR16BIT 0x80|(SPICLK_POLARITY<<6)|SIXTEEN_BIT
#define SPISE2P_TFR8BIT 0x80|(SPICLK_POLARITY<<6)|EIGHT_BIT
/* Status valus */
#define SPISE2P_WRRQ 1 /* Write Requset */
#define SPISE2P_RDRQ 2 /* Read request */
#define SPISE2P_WRIP 4 /* Write in progress */
#define SPISE2P_RDIP 8 /* Read in progress */
/* Message declaration */
typedef struct {
unsigned int *dataPtr; /* Data pointer */
unsigned long nrData; /* number of data */
unsigned long se2pAddr; /* se2pAddr */
}SE2P_DATA;
/* Object declaration */
typedef struct {
SE2P_DATA *msgPtr;
unsigned int csr; /* control/status register */
void (*init)(void *);
void (*tick)(void *);
void (*csset)(void);
void (*csclr)(void);
}SPISE2P_DRV;
#define SPISE2P_DRV_DEFAULTS { NULL,\
0,\
(void (*)(void *))SPISE2P_DRV_init,\
(void (*)(void *))SPISE2P_DRV_tick,\
(void (*)(void))SPISE2P_DRV_csset,\
(void (*)(void))SPISE2P_DRV_csclr}
typedef SPISE2P_DRV *SPISE2P_DRV_handle;
void SPISE2P_DRV_init(SPISE2P_DRV * );
void SPISE2P_DRV_tick(SPISE2P_DRV *);
void SPISE2P_DRV_csset(void);
void SPISE2P_DRV_csclr(void);
unsigned int spiSe2pFree(SPISE2P_DRV *se2p);
void spiSe2pWrite(SPISE2P_DRV *se2p, SE2P_DATA *data);
void spiSe2pRead(SPISE2P_DRV *se2p, SE2P_DATA *data);
#if(SPISE2P_DATA_WIDTH==SIXTEEN_BIT)
#define PROM_LEN 0x8000
#define PAGE_LEN 0x20
#define WORD_LEN 2
#else
#define PROM_LEN 0x4000
#define PAGE_LEN 0x40
#define WORD_LEN 1
#endif
/* Óñòàíîâêà äðàéâåðà ñåðèàëüíîé EEPROM. **
** Èíèöèàëèçàöèà SPI è ïðî÷. Òàêæå íàñòðîéêà òàéìåðà. **
** Äðàéâåð ðàáîòàåò íà ïðåðûâàíèàõ îò òàéìåðà 2! */
void InitSeeprom(void);
/* Çàïèñü áëîêà â SEEPROM. Ïàðàìåòðû òàêîâû: **
** adres - àäðåñ â åïðîìêå, êóäà ïèñàòü. **
** adres = 0..0x8000, åñëè äëèíà ñëîâà 8 áèò **
** adres = 0..0x4000, åñëè äëèíà ñëîâà 16 áèò **
** buf - óêàçàòåëü íà ïàìàòü, îòêóäà ïèñàòü. **
** size - äëèíà áëîêà â áàéòàõ. Ïî-ëþáîìó â áàéòàõ! */
void Seeprom_write(unsigned int adres, unsigned int buf[], unsigned int size);
/* ×òåíèå áëîêà èç SEEPROM. Ïàðàìåòðû òàêîâû: **
** adres - àäðåñ â åïðîìêå, îòêóäà ÷èòàòü. **
** adres = 0..0x8000, åñëè äëèíà ñëîâà 8 áèò **
** adres = 0..0x4000, åñëè äëèíà ñëîâà 16 áèò **
** buf - óêàçàòåëü íà ïàìàòü, êóäà ÷èòàòü. **
** size - äëèíà áëîêà â áàéòàõ. Ïî-ëþáîìó â áàéòàõ! */
void Seeprom_read(unsigned int adres, unsigned int buf[], unsigned int size);
#endif

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#ifndef TOOLS_H
#define TOOLS_H
void init_zone7(void);
void setup_leds_line(void);
void pause_us(unsigned long t);
#define led1_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO32=1
#define led2_toggle() GpioDataRegs.GPBTOGGLE.bit.GPIO48=1
#define led1_off() GpioDataRegs.GPBSET.bit.GPIO32=1
#define led2_off() GpioDataRegs.GPBSET.bit.GPIO48=1
#define led1_on() GpioDataRegs.GPBCLEAR.bit.GPIO32=1
#define led2_on() GpioDataRegs.GPBCLEAR.bit.GPIO48=1
#endif //TOOLS_H