250 lines
8.6 KiB
VHDL
250 lines
8.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity RAM9X8_ParallelBusMaster is
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generic(
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REG_ADDR_FIRST_FREE_LOWER_BYTE : integer := 6;
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REG_ADDR_FIRST_FREE_UPPER_BYTE : integer := 7;
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REG_ADDR_CMD_LOWER_BYTE : integer := 8;
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REG_ADDR_CMD_UPPER_BYTE : integer := 9;
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REG_ADDR_FILL_ADDRESS_SPACE_LOWER_BYTE : integer := 10;
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REG_ADDR_FILL_ADDRESS_SPACE_UPPER_BYTE : integer := 11;
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REG_ADDR_CONTROL_LOWER_BYTE : integer := 12;
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REG_ADDR_CONTROL_UPPER_BYTE : integer := 13;
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ARRAY_LENGTH : integer := 256;
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DATA_BUS_WIDTH : integer := 8;
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ADDRESS_BUS_WIDTH : integer := 9
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);
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port(
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clk : in std_logic;
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data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
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we : in std_logic;
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oe : in std_logic;
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ce : in std_logic;
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pbclk : out std_logic := '1';
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pbce : out std_logic := '1';
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pbdir : out std_logic_vector(1 downto 0) := (others => '1');
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pbdata : inout std_logic_vector(15 downto 0) := (others => 'Z');
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pback : in std_logic
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);
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end entity;
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architecture behavorial of RAM9X8_ParallelBusMaster is
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type mem is array (ARRAY_LENGTH - 1 downto 0) of std_logic_vector(7 downto 0);
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signal memoryAddress : mem;
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signal memoryData : mem;
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signal firstFreeBuf : std_logic_vector(15 downto 0) := (others => '0');
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signal cmdBuf : std_logic_vector(15 downto 0) := (others => '0');
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signal fasBuf : std_logic_vector(15 downto 0) := (others => '0');
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signal controlBuf : std_logic_vector(7 downto 0) := (others => '0');
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signal errorBuf : std_logic_vector(7 downto 0) := x"00";
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signal addrTemp : std_logic_vector(7 downto 0) := x"00";
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signal dataTemp : std_logic_vector(15 downto 0) := x"0000";
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type CommunicationState_start is (Waiting, TransmiteAddress, TransmiteCheck, PreparingToReceiveData, ReceiveData, ReceiveCheck, Timeout, ReceiveCheckTimeout);
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signal CommunicationState : CommunicationState_start := Waiting ;
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signal lineBusy : std_logic := '1';
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signal start : std_logic := '0';
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signal startPrev : std_logic := '0';
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begin
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process (we, oe, ce)
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variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
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variable position : integer range 0 to ARRAY_LENGTH - 1 := 0;
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begin
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if (ce = '0') then -- Если микросхема выбрана
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addr := conv_integer(address);
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if (addr = REG_ADDR_FIRST_FREE_UPPER_BYTE or addr = REG_ADDR_FIRST_FREE_LOWER_BYTE or addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE
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or addr = REG_ADDR_FILL_ADDRESS_SPACE_UPPER_BYTE or addr = REG_ADDR_FILL_ADDRESS_SPACE_LOWER_BYTE or addr = REG_ADDR_CONTROL_UPPER_BYTE or addr = REG_ADDR_CONTROL_LOWER_BYTE) then
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if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
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case addr is
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when REG_ADDR_FIRST_FREE_UPPER_BYTE =>
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data <= firstFreeBuf(15 downto 8);
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when REG_ADDR_FIRST_FREE_LOWER_BYTE =>
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data <= firstFreeBuf(7 downto 0);
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when REG_ADDR_CMD_UPPER_BYTE =>
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data <= cmdBuf(15 downto 8);
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when REG_ADDR_CMD_LOWER_BYTE =>
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data <= cmdBuf(7 downto 0);
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when REG_ADDR_FILL_ADDRESS_SPACE_UPPER_BYTE =>
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data <= fasBuf(15 downto 8);
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when REG_ADDR_FILL_ADDRESS_SPACE_LOWER_BYTE =>
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data <= fasBuf(7 downto 0);
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when REG_ADDR_CONTROL_UPPER_BYTE =>
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data <= errorBuf;
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when REG_ADDR_CONTROL_LOWER_BYTE =>
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data <= controlBuf(7 downto 0);
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when others =>
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data <= (others => 'Z'); -- Запретить запись на шину
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end case;
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elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
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case addr is
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when REG_ADDR_FIRST_FREE_UPPER_BYTE =>
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firstFreeBuf(15 downto 8) <= data;
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when REG_ADDR_FIRST_FREE_LOWER_BYTE =>
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firstFreeBuf(7 downto 0) <= data;
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when REG_ADDR_CMD_UPPER_BYTE =>
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cmdBuf(15 downto 8) <= data;
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when REG_ADDR_CMD_LOWER_BYTE =>
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cmdBuf(7 downto 0) <= data;
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when REG_ADDR_FILL_ADDRESS_SPACE_UPPER_BYTE =>
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fasBuf(15 downto 8) <= data;
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when REG_ADDR_FILL_ADDRESS_SPACE_LOWER_BYTE =>
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fasBuf(7 downto 0) <= data;
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position := conv_integer(data);
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memoryAddress(position) <= fasBuf(15 downto 8);
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when others =>
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data <= (others => 'Z'); -- Запретить запись на шину
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end case;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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elsif (addr >= conv_integer(firstFreeBuf) and addr <= conv_integer(firstFreeBuf) + conv_integer(cmdBuf(7 downto 0))) then
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if (oe = '0') then -- Если сигнал чтения активен
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data <= memoryData(addr - conv_integer(firstFreeBuf));
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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end process;
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process(clk) is
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variable count : integer range 0 to 255 := 0;
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variable countValue : integer range 0 to 255 := 63;
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variable errorCount : integer range 0 to 15 := 0;
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variable position : integer range 0 to ARRAY_LENGTH - 1 := 0;
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begin
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if(rising_edge (clk)) then
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if cmdBuf(15) = '1' then
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case CommunicationState is
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when Waiting =>
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if errorCount < conv_integer(cmdBuf(11 downto 8)) then
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addrTemp <= memoryAddress(position);
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CommunicationState <= TransmiteAddress;
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else
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errorBuf(7 downto 4) <= conv_std_logic_vector(errorCount, 4);
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end if;
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pbclk <= '1';
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pbce <= '1';
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pbdata <= (others =>'Z');
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pbdir <= b"11";
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countValue := 7;
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count := 0;
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when TransmiteAddress =>
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if count < countValue then
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if count = 0 then
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pbdata(15 downto 8) <= addrTemp;
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pbdata(7 downto 0) <= not addrTemp;
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end if;
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count := count + 1;
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else
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pbce <= '0';
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CommunicationState <= TransmiteCheck;
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count := 0;
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countValue := 15;
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end if;
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when TransmiteCheck =>
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if pback = '0' then
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count := 0;
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countValue := 1;
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pbdata <= (others => 'Z');
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CommunicationState <= PreparingToReceiveData;
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else
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if count < countValue then
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count := count + 1;
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else
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CommunicationState <= Waiting;
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errorBuf(0) <= '1';
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end if;
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end if;
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when PreparingToReceiveData =>
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if count < countValue then
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count := count + 1;
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else
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pbdir <= b"00";
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pbclk <= '0';
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count := 0;
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countValue := 15;
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CommunicationState <= ReceiveData;
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end if;
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when ReceiveData =>
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if pback = '1' then
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pbclk <= '1';
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dataTemp <= pbdata;
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CommunicationState <= ReceiveCheck;
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count := 0;
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countValue := 15;
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else
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if count < countValue then
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count := count + 1;
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else
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CommunicationState <= Waiting;
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errorBuf(1) <= '1';
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end if;
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end if;
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when ReceiveCheck =>
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if pback = '0' then
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if pbdata = not dataTemp then
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memoryData(position) <= dataTemp(15 downto 8);
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memoryData(position + 1) <= dataTemp(7 downto 0);
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controlBuf <= memoryAddress(position);
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CommunicationState <= Timeout;
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count := 0;
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pbce <= '1';
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countValue := 5;
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if position + 1 < conv_integer(cmdBuf(7 downto 0)) then
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position := position + 2;
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else
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position := 0;
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end if;
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else
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CommunicationState <= Waiting;
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errorBuf(2) <= '1';
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end if;
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else
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if count < countValue then
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count := count + 1;
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else
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CommunicationState <= Waiting;
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errorBuf(3) <= '1';
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end if;
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end if;
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when Timeout =>
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if count < countValue then
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count := count + 1;
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else
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CommunicationState <= Waiting;
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end if;
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when others => CommunicationState <= Waiting;
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end case;
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else
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pbclk <= '1';
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pbce <= '1';
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pbdata <= (others =>'Z');
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pbdir <= b"11";
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position := 0;
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errorCount := 0;
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errorBuf <= (others => '0');
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end if;
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end if;
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end process;
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end behavorial; |