298 lines
10 KiB
VHDL
298 lines
10 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity RAM9X8_OpticalBusMaster is
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generic(
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REG_ADDR_CMD_LOWER_BYTE : integer := 54;
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REG_ADDR_CMD_UPPER_BYTE : integer := 55;
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REG_ADDR_WORD_8_LOWER_BYTE : integer := 56;
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REG_ADDR_WORD_8_UPPER_BYTE : integer := 57;
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REG_ADDR_WORD_7_LOWER_BYTE : integer := 58;
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REG_ADDR_WORD_7_UPPER_BYTE : integer := 59;
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REG_ADDR_WORD_6_LOWER_BYTE : integer := 60;
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REG_ADDR_WORD_6_UPPER_BYTE : integer := 61;
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REG_ADDR_WORD_5_LOWER_BYTE : integer := 62;
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REG_ADDR_WORD_5_UPPER_BYTE : integer := 63;
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REG_ADDR_WORD_4_LOWER_BYTE : integer := 64;
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REG_ADDR_WORD_4_UPPER_BYTE : integer := 65;
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REG_ADDR_WORD_3_LOWER_BYTE : integer := 66;
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REG_ADDR_WORD_3_UPPER_BYTE : integer := 67;
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REG_ADDR_WORD_2_LOWER_BYTE : integer := 68;
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REG_ADDR_WORD_2_UPPER_BYTE : integer := 69;
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REG_ADDR_WORD_1_LOWER_BYTE : integer := 70;
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REG_ADDR_WORD_1_UPPER_BYTE : integer := 71;
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DATA_BUS_WIDTH : integer := 8;
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ADDRESS_BUS_WIDTH : integer := 9
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);
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port(
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clk : in std_logic;
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data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
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we : in std_logic;
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oe : in std_logic;
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ce : in std_logic;
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obclk : out std_logic := '1';
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obdata : out std_logic := '1'
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);
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end entity;
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architecture behavorial of RAM9X8_OpticalBusMaster is
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signal dataBuf : std_logic_vector(127 downto 0) := (others => '0');
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signal dataToSend : std_logic_vector(127 downto 0) := (others => '0');
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signal cmdBuf : std_logic_vector(15 downto 0) := x"0004";
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type CommunicationState_start is (Waiting, DataSending, CRCSending);
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signal CommunicationState : CommunicationState_start := Waiting ;
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signal resetCRC : std_logic := '1';
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signal CRC : std_logic_vector(3 downto 0) := x"0";
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signal bufCRC : std_logic_vector(3 downto 0) := x"0";
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signal dataCRC : std_logic_vector(127 downto 0) := (others => '0'); -- переключает
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signal readyCRC : std_logic := '0'; -- готовность контрольной суммы
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signal lineBusy : std_logic := '1';
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signal start : std_logic := '0';
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signal startPrev : std_logic := '0';
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begin
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process (we, oe, ce)
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variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
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begin
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if (ce = '0') then -- Если микросхема выбрана
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addr := conv_integer(address);
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if (addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE
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or addr = REG_ADDR_WORD_8_UPPER_BYTE or addr = REG_ADDR_WORD_8_LOWER_BYTE
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or addr = REG_ADDR_WORD_7_UPPER_BYTE or addr = REG_ADDR_WORD_7_LOWER_BYTE
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or addr = REG_ADDR_WORD_6_UPPER_BYTE or addr = REG_ADDR_WORD_6_LOWER_BYTE
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or addr = REG_ADDR_WORD_5_UPPER_BYTE or addr = REG_ADDR_WORD_5_LOWER_BYTE
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or addr = REG_ADDR_WORD_4_UPPER_BYTE or addr = REG_ADDR_WORD_4_LOWER_BYTE
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or addr = REG_ADDR_WORD_3_UPPER_BYTE or addr = REG_ADDR_WORD_3_LOWER_BYTE
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or addr = REG_ADDR_WORD_2_UPPER_BYTE or addr = REG_ADDR_WORD_2_LOWER_BYTE
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or addr = REG_ADDR_WORD_1_UPPER_BYTE or addr = REG_ADDR_WORD_1_LOWER_BYTE) then
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if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
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case addr is
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when REG_ADDR_CMD_UPPER_BYTE =>
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data <= cmdBuf(15 downto 8);
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when REG_ADDR_CMD_LOWER_BYTE =>
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data <= cmdBuf(7 downto 0);
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when REG_ADDR_WORD_8_UPPER_BYTE =>
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data <= dataBuf(127 downto 120);
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when REG_ADDR_WORD_8_LOWER_BYTE =>
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data <= dataBuf(119 downto 112);
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when REG_ADDR_WORD_7_UPPER_BYTE =>
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data <= dataBuf(111 downto 104);
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when REG_ADDR_WORD_7_LOWER_BYTE =>
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data <= dataBuf(103 downto 96);
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when REG_ADDR_WORD_6_UPPER_BYTE =>
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data <= dataBuf(95 downto 88);
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when REG_ADDR_WORD_6_LOWER_BYTE =>
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data <= dataBuf(87 downto 80);
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when REG_ADDR_WORD_5_UPPER_BYTE =>
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data <= dataBuf(79 downto 72);
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when REG_ADDR_WORD_5_LOWER_BYTE =>
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data <= dataBuf(71 downto 64);
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when REG_ADDR_WORD_4_UPPER_BYTE =>
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data <= dataBuf(63 downto 56);
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when REG_ADDR_WORD_4_LOWER_BYTE =>
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data <= dataBuf(55 downto 48);
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when REG_ADDR_WORD_3_UPPER_BYTE =>
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data <= dataBuf(47 downto 40);
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when REG_ADDR_WORD_3_LOWER_BYTE =>
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data <= dataBuf(39 downto 32);
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when REG_ADDR_WORD_2_UPPER_BYTE =>
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data <= dataBuf(31 downto 24);
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when REG_ADDR_WORD_2_LOWER_BYTE =>
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data <= dataBuf(23 downto 16);
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when REG_ADDR_WORD_1_UPPER_BYTE =>
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data <= dataBuf(15 downto 8);
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when REG_ADDR_WORD_1_LOWER_BYTE =>
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data <= dataBuf(7 downto 0);
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when others =>
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data <= (others => 'Z'); -- Запретить запись на шину
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end case;
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elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
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case addr is
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when REG_ADDR_CMD_UPPER_BYTE =>
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cmdBuf(15 downto 8) <= data;
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when REG_ADDR_CMD_LOWER_BYTE =>
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cmdBuf(7 downto 0) <= data;
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when REG_ADDR_WORD_8_UPPER_BYTE =>
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dataBuf(127 downto 120) <= data;
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when REG_ADDR_WORD_8_LOWER_BYTE =>
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dataBuf(119 downto 112) <= data;
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when REG_ADDR_WORD_7_UPPER_BYTE =>
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dataBuf(111 downto 104) <= data;
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when REG_ADDR_WORD_7_LOWER_BYTE =>
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dataBuf(103 downto 96) <= data;
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when REG_ADDR_WORD_6_UPPER_BYTE =>
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dataBuf(95 downto 88) <= data;
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when REG_ADDR_WORD_6_LOWER_BYTE =>
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dataBuf(87 downto 80) <= data;
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when REG_ADDR_WORD_5_UPPER_BYTE =>
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dataBuf(79 downto 72) <= data;
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when REG_ADDR_WORD_5_LOWER_BYTE =>
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dataBuf(71 downto 64) <= data;
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when REG_ADDR_WORD_4_UPPER_BYTE =>
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dataBuf(63 downto 56) <= data;
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when REG_ADDR_WORD_4_LOWER_BYTE =>
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dataBuf(55 downto 48) <= data;
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when REG_ADDR_WORD_3_UPPER_BYTE =>
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dataBuf(47 downto 40) <= data;
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when REG_ADDR_WORD_3_LOWER_BYTE =>
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dataBuf(39 downto 32) <= data;
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when REG_ADDR_WORD_2_UPPER_BYTE =>
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dataBuf(31 downto 24) <= data;
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when REG_ADDR_WORD_2_LOWER_BYTE =>
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dataBuf(23 downto 16) <= data;
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when REG_ADDR_WORD_1_UPPER_BYTE =>
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dataBuf(15 downto 8) <= data;
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when REG_ADDR_WORD_1_LOWER_BYTE =>
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dataBuf(7 downto 0) <= data;
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when others =>
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data <= (others => 'Z'); -- Запретить запись на шину
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end case;
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if (addr = REG_ADDR_WORD_1_UPPER_BYTE) then
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start <= '1';
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else
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start <= '0';
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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end process;
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process(clk) is
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variable count : integer range 0 to 31 := 0;
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variable countValue : integer range 0 to 31 := 25;
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variable state : integer range 0 to 1 := 0;
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variable bitCnt : integer range 0 to 127 := 0;
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begin
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if(rising_edge (clk)) then
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case CommunicationState is
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when Waiting =>
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obclk <= '1';
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obdata <= '1';
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resetCRC <= '1';
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count := 0;
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state := 0;
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if start = '1' and startPrev = '0' then
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dataToSend <= dataBuf;
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dataCRC <= dataBuf;
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if conv_integer(cmdBuf(3 downto 0)) < 9 and conv_integer(cmdBuf(3 downto 0)) > 0 then
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bitCnt := (conv_integer(cmdBuf(3 downto 0)) * 16) - 1;
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else
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bitCnt := 63;
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end if;
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CommunicationState <= DataSending;
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resetCRC <= '0';
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end if;
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when DataSending =>
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if count < countValue and state = 0 then
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if count = 0 then
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obdata <= dataToSend(bitCnt);
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end if;
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count := count + 1;
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elsif count = countValue and state = 0 then
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obclk <= '0';
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count := 0;
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state := 1;
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elsif count < countValue and state = 1 then
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count := count + 1;
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elsif count = countValue and state = 1 then
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obclk <= '1';
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count := 0;
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state := 0;
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if bitCnt > 0 then
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bitCnt := bitCnt - 1;
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else
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bitCnt := 3;
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CommunicationState <= CRCSending;
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end if;
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end if;
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when CRCSending =>
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if count < countValue and state = 0 then
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if count = 0 then
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obdata <= CRC(bitCnt);
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end if;
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count := count + 1;
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elsif count = countValue and state = 0 then
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obclk <= '0';
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count := 0;
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state := 1;
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elsif count < countValue and state = 1 then
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count := count + 1;
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elsif count = countValue and state = 1 then
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obclk <= '1';
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count := 0;
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state := 0;
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if bitCnt > 0 then
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bitCnt := bitCnt - 1;
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else
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CommunicationState <= Waiting;
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end if;
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end if;
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when others =>
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CommunicationState <= Waiting;
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end case;
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startPrev <= start;
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end if;
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end process;
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process(clk)
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variable lacth : integer range 0 to 1 := 0;
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variable bitCnt : integer range -1 to 127 := 0;
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begin
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if rising_edge(clk) then
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if resetCRC = '1' then
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if conv_integer(cmdBuf(3 downto 0)) < 9 and conv_integer(cmdBuf(3 downto 0)) > 0 then
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bitCnt := (conv_integer(cmdBuf(3 downto 0)) * 16) - 1;
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else
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bitCnt := 63;
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end if;
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CRC <= x"0";
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lacth := 0;
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readyCRC <= '0';
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else
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if readyCRC = '0' then
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if lacth = 0 then
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if bitCnt /= -1 then
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CRC(3) <= CRC(2) xor CRC(3);
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CRC(2) <= CRC(1) xor CRC(0);
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CRC(1) <= CRC(0);
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CRC(0) <= dataCRC(bitCnt) xor CRC(1);
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bitCnt := bitCnt - 1;
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else
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bitCnt := 3;
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lacth := 1;
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end if;
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else
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if bitCnt /= -1 then
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CRC(3) <= CRC(2) xor CRC(3);
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CRC(2) <= CRC(1) xor CRC(0);
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CRC(1) <= CRC(0);
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CRC(0) <= '1' xor CRC(1);
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bitCnt := bitCnt - 1;
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else
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readyCRC <= '1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end behavorial; |