291 lines
7.3 KiB
VHDL
291 lines
7.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity RAM9X8_LedController is
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generic(
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REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE : integer := 38;
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REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE : integer := 39;
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REG_ADDR_TEST_UPPER_BYTE : integer := 40;
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REG_ADDR_TEST_LOWER_BYTE : integer := 41;
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DATA_BUS_WIDTH : integer := 8;
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ADDRESS_BUS_WIDTH : integer := 9
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);
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port(
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clk : in std_logic;
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data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
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we : in std_logic;
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oe : in std_logic;
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ce : in std_logic;
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asyncline : out std_logic := '1';
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divclk : out std_logic := '1';
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error : in std_logic;
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init : out std_logic := '0'
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);
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end entity;
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architecture behavorial of RAM9X8_LedController is
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signal activeDeviceBuf : std_logic_vector(15 downto 0) := (others => '0');
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signal testBuf : std_logic_vector(15 downto 0) := (others => '0');
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signal initBuf : std_logic := '0';
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signal divClkBuf : std_logic := '0';
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signal divClkBufPWM : std_logic := '0';
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signal addrBuf : std_logic_vector(3 downto 0) := (others => '0');
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signal ledBuf : std_logic := '0';
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signal LedState : std_logic_vector(1 downto 0) := (others => '0');
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type BusSt is (Waiting, A3, A2, A1, A0, Dt, Finish);
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signal BusState : BusSt := Waiting;
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signal countBuf : std_logic_vector(3 downto 0) := (others => '0');
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signal countBufPWM : std_logic_vector(3 downto 0) := (others => '0');
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begin
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process (we, oe, ce)
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variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
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begin
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if (ce = '0') then -- Если микросхема выбрана
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addr := conv_integer(address);
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if (addr = REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE or addr = REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE
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or addr = REG_ADDR_TEST_UPPER_BYTE or addr = REG_ADDR_TEST_LOWER_BYTE) then
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if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
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case addr is
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when REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE =>
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data <= activeDeviceBuf(15 downto 8);
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when REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE =>
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data <= activeDeviceBuf(7 downto 0);
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when REG_ADDR_TEST_UPPER_BYTE =>
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data <= not testBuf(15 downto 8);
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when REG_ADDR_TEST_LOWER_BYTE =>
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data <= not testBuf(7 downto 0);
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when others =>
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data <= (others => 'Z'); -- Запретить запись на шину
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end case;
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elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
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case addr is
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when REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE =>
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activeDeviceBuf(15 downto 8) <= data;
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when REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE =>
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activeDeviceBuf(7 downto 0) <= data;
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when REG_ADDR_TEST_UPPER_BYTE =>
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testBuf(15 downto 8) <= data;
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when REG_ADDR_TEST_LOWER_BYTE =>
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testBuf(7 downto 0) <= data;
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when others =>
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data <= (others => 'Z'); -- Запретить запись на шину
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end case;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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end process;
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process(clk) is
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begin
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if rising_edge(clk) then
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if testBuf = x"5AA5" then
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initBuf <= '1';
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end if;
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end if;
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end process;
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init <= initBuf;
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process(clk) is
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variable count50000 : integer range 0 to 50000 := 0;
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variable count50 : integer range 0 to 50 := 0;
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begin
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if rising_edge(clk) then
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if count50000 < 50000 then
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count50000 := count50000 + 1;
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else
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divClkBufPWM <= not divClkBufPWM;
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count50000 := 0;
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if count50 < 50 then
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count50 := count50 + 1;
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else
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count50 := 0;
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divClkBuf <= not divClkBuf;
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end if;
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end if;
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end if;
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end process;
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process(divClkBufPWM) is
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begin
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if conv_integer(countBufPWM) < 15 then
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countBufPWM <= conv_std_logic_vector(conv_integer(countBufPWM) + 1, 4);
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else
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countBufPWM <= (others => '0');
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end if;
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end process;
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process(divClkBuf) is
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variable direction : integer range 0 to 1 := 0;
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begin
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if direction = 0 then
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if conv_integer(countBuf) < 15 then
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countBuf <= conv_std_logic_vector(conv_integer(countBuf) + 1, 4);
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else
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direction := 1;
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end if;
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else
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if conv_integer(countBuf) > 0 then
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countBuf <= conv_std_logic_vector(conv_integer(countBuf) - 1, 4);
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else
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direction := 0;
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end if;
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end if;
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end process;
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process(divClkBuf) is
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variable count15 : integer range 0 to 15 := 0;
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begin
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case LedState is
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when b"00" =>
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if count15 < 15 then
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count15 := count15 + 1;
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else
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count15 := 0;
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LedState <= b"01";
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end if;
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divclk <= '0';
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when b"01" =>
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if count15 < 7 then
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count15 := count15 + 1;
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else
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count15 := 0;
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LedState <= b"10";
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end if;
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divclk <= '1';
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when b"10" =>
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if count15 < 15 then
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count15 := count15 + 1;
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else
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count15 := 0;
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LedState <= b"11";
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end if;
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divclk <= '0';
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when b"11" =>
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if count15 < 4 then
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count15 := count15 + 1;
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else
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count15 := 0;
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LedState <= b"00";
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end if;
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divclk <= '1';
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when others =>
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LedState <= b"00";
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end case;
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end process;
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process(clk) is
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variable count50 : integer range 0 to 50 := 0;
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variable count15 : integer range 0 to 15 := 15;
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begin
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if rising_edge(clk) then
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if initBuf = '0' then
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case BusState is
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when Waiting =>
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if count50 < 38 then
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count50 := count50 + 1;
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else
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if count15 < 15 then
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count15 := count15 + 1;
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else
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count15 := 0;
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end if;
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if activeDeviceBuf(count15) = '1' then
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addrBuf <= conv_std_logic_vector(count15, 4);
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asyncline <= '0';
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count50 := 0;
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BusState <= A3;
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end if;
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end if;
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when A3 =>
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if count50 < 18 then
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count50 := count50 + 1;
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else
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count50 := 0;
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asyncline <= addrBuf(3);
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BusState <= A2;
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end if;
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when A2 =>
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if count50 < 38 then
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count50 := count50 + 1;
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else
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count50 := 0;
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asyncline <= addrBuf(2);
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BusState <= A1;
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end if;
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when A1 =>
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if count50 < 38 then
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count50 := count50 + 1;
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else
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count50 := 0;
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asyncline <= addrBuf(1);
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BusState <= A0;
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end if;
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when A0 =>
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if count50 < 38 then
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count50 := count50 + 1;
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else
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count50 := 0;
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asyncline <= addrBuf(0);
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BusState <= Dt;
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end if;
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when Dt =>
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if count50 < 38 then
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count50 := count50 + 1;
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else
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count50 := 0;
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asyncline <= divClkBuf;
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BusState <= Finish;
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end if;
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when Finish =>
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if count50 < 38 then
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count50 := count50 + 1;
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else
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count50 := 0;
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asyncline <= '1';
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BusState <= Finish;
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end if;
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when others =>
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BusState <= Waiting;
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count50 := 0;
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count15 :=15;
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end case;
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else
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BusState <= Waiting;
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count50 := 0;
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count15 := 15;
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if error = '0' then
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if countBuf < countBufPWM then
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asyncline <= '1';
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else
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asyncline <= '0';
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end if;
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else
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asyncline <= '1';
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end if;
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end if;
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end if;
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end process;
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end behavorial; |