116 lines
3.2 KiB
VHDL
116 lines
3.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity RAM9X8 is
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port(
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-- clk : in std_logic;
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data : inout std_logic_vector(7 downto 0);
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address : in std_logic_vector(8 downto 0);
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we : in std_logic;
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oe : in std_logic;
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ce : in std_logic
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);
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end entity;
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architecture behavorial of RAM9X8 is
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type mem is array (511 downto 0) of std_logic_vector(7 downto 0);
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signal memory : mem;
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--signal cePrev : std_logic := '0';
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--type MemoryMachine is (Waiting, ReadingAddress, WritingData, ReadingData);
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--signal stateMM : MemoryMachine := Waiting;
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begin
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-- process (CLK_FPGA, nCS, nOE, bWE, A)
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-- begin
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-- -- Фильтрация и синхронизация сигналов от процессора
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-- if rising_edge(CLK_FPGA) then
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-- -- Пример фильтрации сигналов nCS, nOE и bWE
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-- filtered_we <= we;
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-- filtered_oe <= oe;
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-- filtered_ce <= ce;
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--
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-- -- Пример фильтрации и синхронизации сигнала адреса A
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-- --filtered_A <= A;
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-- end if;
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-- end process;
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--
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process (we, oe, ce, address)
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variable addr : integer range 0 to 511 := 0;
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begin
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if (ce = '0') then -- Если микросхема выбрана
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if (oe = '0') then -- Если сигнал чтения активен
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addr := conv_integer(address);
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case addr is
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when 0 => data <= x"AA";
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when 1 => data <= x"BB";
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when 2 => data <= x"CC";
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when 3 => data <= x"DD";
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when 4 => data <= x"EE";
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when 5 => data <= x"FF";
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when 6 => data <= x"01";
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when 7 => data <= x"23";
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when 8 => data <= x"45";
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when 9 => data <= x"67";
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when others => data <= (others => 'Z'); -- Для остальных адресов разрешить чтение
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end case;
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elsif (we = '0') then -- Если сигнал записи активен
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addr := conv_integer(address);
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memory(addr) <= data;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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end process;
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-- process(clk)
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-- variable addr : integer range 0 to 511 := 0;
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-- begin
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-- if rising_edge(clk) then
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-- case stateMM is
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-- when Waiting =>
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-- if ce = '0' and cePrev = '1' then
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-- stateMM <= ReadingAddress;
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-- end if;
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-- data <= (others => 'Z');
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-- when ReadingAddress =>
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-- addr := conv_integer(address);
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-- if oe = '0' then
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-- stateMM <= ReadingData;
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-- data <= (others => '0');
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-- elsif we = '0' then
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-- stateMM <= WritingData;
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-- elsif ce = '1' then
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-- stateMM <= Waiting;
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-- end if;
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-- when ReadingData =>
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-- data <= memory(addr);
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-- if ce = '1' then
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-- stateMM <= Waiting;
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-- end if;
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-- when WritingData =>
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-- memory(addr) <= data;
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-- stateMM <= Waiting;
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-- when others =>
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-- end case;
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-- memory(0) <= x"AA";
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-- memory(1) <= x"BB";
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-- memory(2) <= x"CC";
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-- memory(3) <= x"DD";
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-- memory(4) <= x"EE";
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-- memory(5) <= x"FF";
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-- memory(6) <= x"01";
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-- memory(7) <= x"23";
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-- memory(8) <= x"45";
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-- memory(9) <= memory(9) + 1;
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-- end if;
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-- end process;
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end behavorial; |