31 lines
501 B
VHDL
31 lines
501 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity LedBlink is
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Port (
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clk : in STD_LOGIC;
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led : out STD_LOGIC
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);
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end LedBlink;
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architecture Behavioral of LedBlink is
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signal counter : natural range 0 to 16666667 := 0;
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signal ledBuf : STD_LOGIC := '1';
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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if counter < 16666667 then
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counter <= counter + 1;
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else
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counter <= 0;
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ledBuf <= not ledBuf;
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end if;
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end if;
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end process;
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led <= ledBuf;
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end Behavioral; |