121 lines
3.7 KiB
VHDL
121 lines
3.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity RAM9X8_Service is
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generic(
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SRV_BASE_ADDRESS : integer := 74;
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DATA_BUS_WIDTH : integer := 8;
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ADDRESS_BUS_WIDTH : integer := 9
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);
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port(
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clk : in std_logic;
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data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
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we : in std_logic;
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oe : in std_logic;
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ce : in std_logic;
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er0_in : in std_logic;
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leds : out std_logic_vector(3 downto 0);
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er0_out : out std_logic;
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init : out std_logic;
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sres : out std_logic
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);
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end entity;
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architecture behavorial of RAM9X8_Service is
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signal SRV_CONTROL_LOWER : integer := SRV_BASE_ADDRESS;
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signal SRV_CONTROL_UPPER : integer := SRV_BASE_ADDRESS + 1;
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signal SRV_LEDS_LOWER : integer := SRV_BASE_ADDRESS + 2;
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signal SRV_LEDS_UPPER : integer := SRV_BASE_ADDRESS + 3;
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signal SRV_INIT_LOWER : integer := SRV_BASE_ADDRESS + 4;
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signal SRV_INIT_UPPER : integer := SRV_BASE_ADDRESS + 5;
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signal SRV_VERSION_LOWER : integer := SRV_BASE_ADDRESS + 6;
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signal SRV_VERSION_UPPER : integer := SRV_BASE_ADDRESS + 7;
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signal ledsBuf : std_logic_vector(15 downto 0) := (others => '0');
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signal initBuf : std_logic_vector(15 downto 0) := (others => '0');
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signal versionBuf : std_logic_vector(15 downto 0) := x"0004";
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begin
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process (we, oe, ce)
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variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
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begin
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if (ce = '0') then -- Если микросхема выбрана
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addr := conv_integer(address);
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if (addr = SRV_CONTROL_UPPER or addr = SRV_CONTROL_LOWER
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or addr = SRV_LEDS_LOWER or addr = SRV_LEDS_UPPER
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or addr = SRV_INIT_LOWER or addr = SRV_INIT_UPPER
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or addr = SRV_VERSION_LOWER or addr = SRV_VERSION_UPPER) then
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if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
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case addr is
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when SRV_CONTROL_UPPER =>
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data <= (others => '0');
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when SRV_CONTROL_LOWER =>
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data(7 downto 1) <= (others => '0');
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data(0) <= er0_in;
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when SRV_LEDS_UPPER =>
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data <= ledsBuf(15 downto 8);
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when SRV_LEDS_LOWER =>
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data <= ledsBuf(7 downto 0);
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when SRV_INIT_UPPER =>
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data <= not initBuf(15 downto 8);
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when SRV_INIT_LOWER =>
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data <= not initBuf(7 downto 0);
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when SRV_VERSION_UPPER =>
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data <= versionBuf(15 downto 8);
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when SRV_VERSION_LOWER =>
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data <= versionBuf(7 downto 0);
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when others =>
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data <= (others => 'Z'); -- Запретить запись на шину
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end case;
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elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
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case addr is
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when SRV_LEDS_UPPER =>
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ledsBuf(15 downto 8) <= data;
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when SRV_LEDS_LOWER =>
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ledsBuf(7 downto 0) <= data;
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when SRV_INIT_UPPER =>
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initBuf(15 downto 8) <= data;
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when SRV_INIT_LOWER =>
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initBuf(7 downto 0) <= data;
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when others =>
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data <= (others => 'Z'); -- Запретить запись на шину
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end case;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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end process;
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process(clk) is
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begin
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if rising_edge(clk) then
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if initBuf = x"5AA5" then
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init <= '1';
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end if;
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end if;
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end process;
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process(clk)
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begin
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if rising_edge(clk) then
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leds <= ledsBuf(3 downto 0);
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er0_out <= ledsBuf(15);
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sres <= ledsBuf(14);
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end if;
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end process;
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end behavorial; |