45 lines
1.2 KiB
VHDL
45 lines
1.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity RAM is
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generic(
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DATA_BUS_WIDTH : integer := 8;
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ADDRESS_BUS_WIDTH : integer := 9
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);
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port(
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data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
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we : in std_logic;
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oe : in std_logic;
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ce : in std_logic
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);
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end entity;
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architecture behavorial of RAM is
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type mem is array (2**ADDRESS_BUS_WIDTH - 1 downto 0) of std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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signal memory : mem;
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begin
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process (we, oe, ce)
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variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
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begin
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if (ce = '0') then -- Если микросхема выбрана
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addr := conv_integer(address);
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if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
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data <= memory(addr);
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elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
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memory(addr) <= data;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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end process;
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end behavorial; |