library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DigitalInversion is
	 port(
		 clk : in STD_LOGIC;
		 input : in STD_LOGIC;
		 ce : in STD_LOGIC;
		 output : out STD_LOGIC;
		 noutput : out STD_LOGIC
	     );
end DigitalInversion;

architecture Behavioral of DigitalInversion is

begin	
	
	process(clk)		
	begin		
		if rising_edge(clk) then 
			if (ce = '1') then
				if input = '1' then	
					output <= '1';
					noutput <= '0';	
				else
					output <= '0';
					noutput <= '1';	
				end if;
			else
				output <= 'Z';
				noutput <= 'Z';
			end if;	
		end if;
	end process;
	
end Behavioral;