EDA Netlist Writer report for MainController Tue Mar 12 17:46:57 2024 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. EDA Netlist Writer Summary 3. Simulation Settings 4. Simulation Generated Files 5. EDA Netlist Writer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ ; EDA Netlist Writer Status ; Successful - Tue Mar 12 17:46:57 2024 ; ; Revision Name ; MainController ; ; Top-level Entity Name ; MainController ; ; Family ; Cyclone III ; ; Simulation Files Creation ; Successful ; +---------------------------+---------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------+ ; Simulation Settings ; +---------------------------------------------------------------------------------------------------+------------------------+ ; Option ; Setting ; +---------------------------------------------------------------------------------------------------+------------------------+ ; Tool Name ; ModelSim-Altera (VHDL) ; ; Generate netlist for functional simulation only ; Off ; ; Time scale ; 1 ps ; ; Truncate long hierarchy paths ; Off ; ; Map illegal HDL characters ; Off ; ; Flatten buses into individual nodes ; Off ; ; Maintain hierarchy ; Off ; ; Bring out device-wide set/reset signals as ports ; Off ; ; Enable glitch filtering ; Off ; ; Do not write top level VHDL entity ; Off ; ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; ; Architecture name in VHDL output netlist ; structure ; ; Generate third-party EDA tool command script for RTL functional simulation ; Off ; ; Generate third-party EDA tool command script for gate-level simulation ; Off ; +---------------------------------------------------------------------------------------------------+------------------------+ +----------------------------------------------------------------------------------------------+ ; Simulation Generated Files ; +----------------------------------------------------------------------------------------------+ ; Generated Files ; +----------------------------------------------------------------------------------------------+ ; D:/GITEA/altera/MainController/simulation/modelsim/MainController_8_1200mv_85c_slow.vho ; ; D:/GITEA/altera/MainController/simulation/modelsim/MainController_8_1200mv_0c_slow.vho ; ; D:/GITEA/altera/MainController/simulation/modelsim/MainController_min_1200mv_0c_fast.vho ; ; D:/GITEA/altera/MainController/simulation/modelsim/MainController.vho ; ; D:/GITEA/altera/MainController/simulation/modelsim/MainController_8_1200mv_85c_vhd_slow.sdo ; ; D:/GITEA/altera/MainController/simulation/modelsim/MainController_8_1200mv_0c_vhd_slow.sdo ; ; D:/GITEA/altera/MainController/simulation/modelsim/MainController_min_1200mv_0c_vhd_fast.sdo ; ; D:/GITEA/altera/MainController/simulation/modelsim/MainController_vhd.sdo ; +----------------------------------------------------------------------------------------------+ +-----------------------------+ ; EDA Netlist Writer Messages ; +-----------------------------+ Info: ******************************************************************* Info: Running Quartus II 64-Bit EDA Netlist Writer Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version Info: Processing started: Tue Mar 12 17:46:56 2024 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off MainController -c MainController Info (204019): Generated file MainController_8_1200mv_85c_slow.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file MainController_8_1200mv_0c_slow.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file MainController_min_1200mv_0c_fast.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file MainController.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file MainController_8_1200mv_85c_vhd_slow.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file MainController_8_1200mv_0c_vhd_slow.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file MainController_min_1200mv_0c_vhd_fast.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file MainController_vhd.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4577 megabytes Info: Processing ended: Tue Mar 12 17:46:57 2024 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01