vendor_name = ModelSim
source_file = 1, D:/GITEA/altera/MainController/MainController.bdf
source_file = 1, D:/GITEA/altera/MainController/AlteraPLL.qip
source_file = 1, D:/GITEA/altera/MainController/AlteraPLL.vhd
source_file = 1, D:/GITEA/altera/MainController/RAM.vhd
source_file = 1, D:/GITEA/altera/MainController/LedBlink.vhd
source_file = 1, D:/GITEA/altera/MainController/db/MainController.cbx.xml
source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/timing_b.vhd
source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/timing_p.vhd
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altpll.tdf
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/aglobal131.inc
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_pll.inc
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/stratixii_pll.inc
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/cbx.lst
source_file = 1, D:/GITEA/altera/MainController/db/alterapll_altpll.v
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altsyncram.tdf
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/lpm_mux.inc
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/lpm_decode.inc
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/a_rdenreg.inc
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altrom.inc
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altram.inc
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altdpram.inc
source_file = 1, D:/GITEA/altera/MainController/db/altsyncram_lkc1.tdf
source_file = 1, D:/GITEA/altera/MainController/db/altsyncram_8bi1.tdf
design_name = MainController
instance = comp, \FPGA_LED_1~output\, FPGA_LED_1~output, MainController, 1
instance = comp, \FPGA_LED_2~output\, FPGA_LED_2~output, MainController, 1
instance = comp, \FPGA_LED_3~output\, FPGA_LED_3~output, MainController, 1
instance = comp, \Data[7]~output\, Data[7]~output, MainController, 1
instance = comp, \Data[6]~output\, Data[6]~output, MainController, 1
instance = comp, \Data[5]~output\, Data[5]~output, MainController, 1
instance = comp, \Data[4]~output\, Data[4]~output, MainController, 1
instance = comp, \Data[3]~output\, Data[3]~output, MainController, 1
instance = comp, \Data[2]~output\, Data[2]~output, MainController, 1
instance = comp, \Data[1]~output\, Data[1]~output, MainController, 1
instance = comp, \Data[0]~output\, Data[0]~output, MainController, 1
instance = comp, \FPGA_CLK~input\, FPGA_CLK~input, MainController, 1
instance = comp, \FPGA_CLK~inputclkctrl\, FPGA_CLK~inputclkctrl, MainController, 1
instance = comp, \nCE~input\, nCE~input, MainController, 1
instance = comp, \Address[5]~input\, Address[5]~input, MainController, 1
instance = comp, \inst3|ce0Prev\, inst3|ce0Prev, MainController, 1
instance = comp, \inst3|addr~5\, inst3|addr~5, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[12]~feeder\, inst3|memory_rtl_0_bypass[12]~feeder, MainController, 1
instance = comp, \nWE~input\, nWE~input, MainController, 1
instance = comp, \inst3|we0Prev\, inst3|we0Prev, MainController, 1
instance = comp, \nOE~input\, nOE~input, MainController, 1
instance = comp, \inst3|Selector3~3\, inst3|Selector3~3, MainController, 1
instance = comp, \inst3|Selector3~2\, inst3|Selector3~2, MainController, 1
instance = comp, \inst3|stateMM0.Writing\, inst3|stateMM0.Writing, MainController, 1
instance = comp, \inst3|memory~48\, inst3|memory~48, MainController, 1
instance = comp, \inst3|oe0Prev\, inst3|oe0Prev, MainController, 1
instance = comp, \inst3|Selector3~0\, inst3|Selector3~0, MainController, 1
instance = comp, \inst3|Selector3~1\, inst3|Selector3~1, MainController, 1
instance = comp, \inst3|Selector2~0\, inst3|Selector2~0, MainController, 1
instance = comp, \inst3|stateMM0.Waiting\, inst3|stateMM0.Waiting, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[12]\, inst3|memory_rtl_0_bypass[12], MainController, 1
instance = comp, \inst3|addr[5]\, inst3|addr[5], MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[11]~feeder\, inst3|memory_rtl_0_bypass[11]~feeder, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[11]\, inst3|memory_rtl_0_bypass[11], MainController, 1
instance = comp, \Address[4]~input\, Address[4]~input, MainController, 1
instance = comp, \inst3|addr~4\, inst3|addr~4, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[10]\, inst3|memory_rtl_0_bypass[10], MainController, 1
instance = comp, \inst3|addr[4]\, inst3|addr[4], MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[9]\, inst3|memory_rtl_0_bypass[9], MainController, 1
instance = comp, \inst3|memory~37\, inst3|memory~37, MainController, 1
instance = comp, \Address[2]~input\, Address[2]~input, MainController, 1
instance = comp, \inst3|addr~2\, inst3|addr~2, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[6]~feeder\, inst3|memory_rtl_0_bypass[6]~feeder, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[6]\, inst3|memory_rtl_0_bypass[6], MainController, 1
instance = comp, \Address[3]~input\, Address[3]~input, MainController, 1
instance = comp, \inst3|addr~3\, inst3|addr~3, MainController, 1
instance = comp, \inst3|addr[3]\, inst3|addr[3], MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[7]\, inst3|memory_rtl_0_bypass[7], MainController, 1
instance = comp, \inst3|addr[2]\, inst3|addr[2], MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[5]\, inst3|memory_rtl_0_bypass[5], MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[8]\, inst3|memory_rtl_0_bypass[8], MainController, 1
instance = comp, \inst3|memory~35\, inst3|memory~35, MainController, 1
instance = comp, \Address[0]~input\, Address[0]~input, MainController, 1
instance = comp, \inst3|addr~0\, inst3|addr~0, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[2]~feeder\, inst3|memory_rtl_0_bypass[2]~feeder, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[2]\, inst3|memory_rtl_0_bypass[2], MainController, 1
instance = comp, \Address[1]~input\, Address[1]~input, MainController, 1
instance = comp, \inst3|addr~1\, inst3|addr~1, MainController, 1
instance = comp, \inst3|addr[1]\, inst3|addr[1], MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[3]\, inst3|memory_rtl_0_bypass[3], MainController, 1
instance = comp, \inst3|addr[0]\, inst3|addr[0], MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[1]\, inst3|memory_rtl_0_bypass[1], MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[4]~feeder\, inst3|memory_rtl_0_bypass[4]~feeder, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[4]\, inst3|memory_rtl_0_bypass[4], MainController, 1
instance = comp, \inst3|memory~34\, inst3|memory~34, MainController, 1
instance = comp, \inst3|memory~36\, inst3|memory~36, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[0]\, inst3|memory_rtl_0_bypass[0], MainController, 1
instance = comp, \Address[7]~input\, Address[7]~input, MainController, 1
instance = comp, \inst3|addr~7\, inst3|addr~7, MainController, 1
instance = comp, \inst3|addr[7]\, inst3|addr[7], MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[15]\, inst3|memory_rtl_0_bypass[15], MainController, 1
instance = comp, \Address[6]~input\, Address[6]~input, MainController, 1
instance = comp, \inst3|addr~6\, inst3|addr~6, MainController, 1
instance = comp, \inst3|addr[6]\, inst3|addr[6], MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[13]~feeder\, inst3|memory_rtl_0_bypass[13]~feeder, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[13]\, inst3|memory_rtl_0_bypass[13], MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[14]\, inst3|memory_rtl_0_bypass[14], MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[16]~feeder\, inst3|memory_rtl_0_bypass[16]~feeder, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[16]\, inst3|memory_rtl_0_bypass[16], MainController, 1
instance = comp, \inst3|memory~38\, inst3|memory~38, MainController, 1
instance = comp, \inst3|memory~39\, inst3|memory~39, MainController, 1
instance = comp, \inst3|stateMM0.Waiting~_wirecell\, inst3|stateMM0.Waiting~_wirecell, MainController, 1
instance = comp, \Data[0]~input\, Data[0]~input, MainController, 1
instance = comp, \Data[1]~input\, Data[1]~input, MainController, 1
instance = comp, \Data[2]~input\, Data[2]~input, MainController, 1
instance = comp, \Data[3]~input\, Data[3]~input, MainController, 1
instance = comp, \Data[4]~input\, Data[4]~input, MainController, 1
instance = comp, \Data[5]~input\, Data[5]~input, MainController, 1
instance = comp, \Data[6]~input\, Data[6]~input, MainController, 1
instance = comp, \Data[7]~input\, Data[7]~input, MainController, 1
instance = comp, \inst3|memory_rtl_0|auto_generated|ram_block1a0\, inst3|memory_rtl_0|auto_generated|ram_block1a0, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[24]~feeder\, inst3|memory_rtl_0_bypass[24]~feeder, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[24]\, inst3|memory_rtl_0_bypass[24], MainController, 1
instance = comp, \inst3|memory~40\, inst3|memory~40, MainController, 1
instance = comp, \inst3|Selector4~0\, inst3|Selector4~0, MainController, 1
instance = comp, \inst3|stateMM0.Reading\, inst3|stateMM0.Reading, MainController, 1
instance = comp, \inst3|Selector74~0\, inst3|Selector74~0, MainController, 1
instance = comp, \inst3|data0[7]~reg0\, inst3|data0[7]~reg0, MainController, 1
instance = comp, \inst3|data0[7]~enfeeder\, inst3|data0[7]~enfeeder, MainController, 1
instance = comp, \inst3|data0[7]~en\, inst3|data0[7]~en, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[23]~feeder\, inst3|memory_rtl_0_bypass[23]~feeder, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[23]\, inst3|memory_rtl_0_bypass[23], MainController, 1
instance = comp, \inst3|memory~41\, inst3|memory~41, MainController, 1
instance = comp, \inst3|data0[6]~reg0\, inst3|data0[6]~reg0, MainController, 1
instance = comp, \inst3|data0[6]~enfeeder\, inst3|data0[6]~enfeeder, MainController, 1
instance = comp, \inst3|data0[6]~en\, inst3|data0[6]~en, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[22]~feeder\, inst3|memory_rtl_0_bypass[22]~feeder, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[22]\, inst3|memory_rtl_0_bypass[22], MainController, 1
instance = comp, \inst3|memory~42\, inst3|memory~42, MainController, 1
instance = comp, \inst3|data0[5]~reg0\, inst3|data0[5]~reg0, MainController, 1
instance = comp, \inst3|data0[5]~enfeeder\, inst3|data0[5]~enfeeder, MainController, 1
instance = comp, \inst3|data0[5]~en\, inst3|data0[5]~en, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[21]~feeder\, inst3|memory_rtl_0_bypass[21]~feeder, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[21]\, inst3|memory_rtl_0_bypass[21], MainController, 1
instance = comp, \inst3|memory~43\, inst3|memory~43, MainController, 1
instance = comp, \inst3|data0[4]~reg0\, inst3|data0[4]~reg0, MainController, 1
instance = comp, \inst3|data0[4]~enfeeder\, inst3|data0[4]~enfeeder, MainController, 1
instance = comp, \inst3|data0[4]~en\, inst3|data0[4]~en, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[20]\, inst3|memory_rtl_0_bypass[20], MainController, 1
instance = comp, \inst3|memory~44\, inst3|memory~44, MainController, 1
instance = comp, \inst3|data0[3]~reg0\, inst3|data0[3]~reg0, MainController, 1
instance = comp, \inst3|data0[3]~enfeeder\, inst3|data0[3]~enfeeder, MainController, 1
instance = comp, \inst3|data0[3]~en\, inst3|data0[3]~en, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[19]\, inst3|memory_rtl_0_bypass[19], MainController, 1
instance = comp, \inst3|memory~45\, inst3|memory~45, MainController, 1
instance = comp, \inst3|data0[2]~reg0\, inst3|data0[2]~reg0, MainController, 1
instance = comp, \inst3|data0[2]~enfeeder\, inst3|data0[2]~enfeeder, MainController, 1
instance = comp, \inst3|data0[2]~en\, inst3|data0[2]~en, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[18]\, inst3|memory_rtl_0_bypass[18], MainController, 1
instance = comp, \inst3|memory~46\, inst3|memory~46, MainController, 1
instance = comp, \inst3|data0[1]~reg0\, inst3|data0[1]~reg0, MainController, 1
instance = comp, \inst3|data0[1]~enfeeder\, inst3|data0[1]~enfeeder, MainController, 1
instance = comp, \inst3|data0[1]~en\, inst3|data0[1]~en, MainController, 1
instance = comp, \inst3|memory_rtl_0_bypass[17]\, inst3|memory_rtl_0_bypass[17], MainController, 1
instance = comp, \inst3|memory~47\, inst3|memory~47, MainController, 1
instance = comp, \inst3|data0[0]~reg0\, inst3|data0[0]~reg0, MainController, 1
instance = comp, \inst3|data0[0]~enfeeder\, inst3|data0[0]~enfeeder, MainController, 1
instance = comp, \inst3|data0[0]~en\, inst3|data0[0]~en, MainController, 1
instance = comp, \inst2|counter[0]~24\, inst2|counter[0]~24, MainController, 1
instance = comp, \inst2|counter[13]~50\, inst2|counter[13]~50, MainController, 1
instance = comp, \inst2|counter[14]~52\, inst2|counter[14]~52, MainController, 1
instance = comp, \inst2|counter[14]\, inst2|counter[14], MainController, 1
instance = comp, \inst2|counter[15]~54\, inst2|counter[15]~54, MainController, 1
instance = comp, \inst2|counter[15]\, inst2|counter[15], MainController, 1
instance = comp, \inst2|counter[16]~56\, inst2|counter[16]~56, MainController, 1
instance = comp, \inst2|counter[16]\, inst2|counter[16], MainController, 1
instance = comp, \inst2|counter[17]~58\, inst2|counter[17]~58, MainController, 1
instance = comp, \inst2|counter[17]\, inst2|counter[17], MainController, 1
instance = comp, \inst2|counter[18]~60\, inst2|counter[18]~60, MainController, 1
instance = comp, \inst2|counter[18]\, inst2|counter[18], MainController, 1
instance = comp, \inst2|counter[19]~62\, inst2|counter[19]~62, MainController, 1
instance = comp, \inst2|counter[19]\, inst2|counter[19], MainController, 1
instance = comp, \inst2|counter[20]~64\, inst2|counter[20]~64, MainController, 1
instance = comp, \inst2|counter[20]\, inst2|counter[20], MainController, 1
instance = comp, \inst2|counter[21]~66\, inst2|counter[21]~66, MainController, 1
instance = comp, \inst2|counter[21]\, inst2|counter[21], MainController, 1
instance = comp, \inst2|LessThan0~8\, inst2|LessThan0~8, MainController, 1
instance = comp, \inst2|counter[22]~68\, inst2|counter[22]~68, MainController, 1
instance = comp, \inst2|counter[22]\, inst2|counter[22], MainController, 1
instance = comp, \inst2|counter[23]~70\, inst2|counter[23]~70, MainController, 1
instance = comp, \inst2|counter[23]\, inst2|counter[23], MainController, 1
instance = comp, \inst2|LessThan0~9\, inst2|LessThan0~9, MainController, 1
instance = comp, \inst2|LessThan0~2\, inst2|LessThan0~2, MainController, 1
instance = comp, \inst2|LessThan0~3\, inst2|LessThan0~3, MainController, 1
instance = comp, \inst2|LessThan0~0\, inst2|LessThan0~0, MainController, 1
instance = comp, \inst2|LessThan0~1\, inst2|LessThan0~1, MainController, 1
instance = comp, \inst2|LessThan0~4\, inst2|LessThan0~4, MainController, 1
instance = comp, \inst2|LessThan0~6\, inst2|LessThan0~6, MainController, 1
instance = comp, \inst2|LessThan0~10\, inst2|LessThan0~10, MainController, 1
instance = comp, \inst2|counter[0]\, inst2|counter[0], MainController, 1
instance = comp, \inst2|counter[1]~26\, inst2|counter[1]~26, MainController, 1
instance = comp, \inst2|counter[1]\, inst2|counter[1], MainController, 1
instance = comp, \inst2|counter[2]~28\, inst2|counter[2]~28, MainController, 1
instance = comp, \inst2|counter[2]\, inst2|counter[2], MainController, 1
instance = comp, \inst2|counter[3]~30\, inst2|counter[3]~30, MainController, 1
instance = comp, \inst2|counter[3]\, inst2|counter[3], MainController, 1
instance = comp, \inst2|counter[4]~32\, inst2|counter[4]~32, MainController, 1
instance = comp, \inst2|counter[4]\, inst2|counter[4], MainController, 1
instance = comp, \inst2|counter[5]~34\, inst2|counter[5]~34, MainController, 1
instance = comp, \inst2|counter[5]\, inst2|counter[5], MainController, 1
instance = comp, \inst2|counter[6]~36\, inst2|counter[6]~36, MainController, 1
instance = comp, \inst2|counter[6]\, inst2|counter[6], MainController, 1
instance = comp, \inst2|counter[7]~38\, inst2|counter[7]~38, MainController, 1
instance = comp, \inst2|counter[7]\, inst2|counter[7], MainController, 1
instance = comp, \inst2|counter[8]~40\, inst2|counter[8]~40, MainController, 1
instance = comp, \inst2|counter[8]\, inst2|counter[8], MainController, 1
instance = comp, \inst2|counter[9]~42\, inst2|counter[9]~42, MainController, 1
instance = comp, \inst2|counter[9]\, inst2|counter[9], MainController, 1
instance = comp, \inst2|counter[10]~44\, inst2|counter[10]~44, MainController, 1
instance = comp, \inst2|counter[10]\, inst2|counter[10], MainController, 1
instance = comp, \inst2|counter[11]~46\, inst2|counter[11]~46, MainController, 1
instance = comp, \inst2|counter[11]\, inst2|counter[11], MainController, 1
instance = comp, \inst2|counter[12]~48\, inst2|counter[12]~48, MainController, 1
instance = comp, \inst2|counter[12]\, inst2|counter[12], MainController, 1
instance = comp, \inst2|counter[13]\, inst2|counter[13], MainController, 1
instance = comp, \inst2|LessThan0~5\, inst2|LessThan0~5, MainController, 1
instance = comp, \inst2|LessThan0~7\, inst2|LessThan0~7, MainController, 1
instance = comp, \inst2|ledBuf~0\, inst2|ledBuf~0, MainController, 1
instance = comp, \inst2|ledBuf\, inst2|ledBuf, MainController, 1
instance = comp, \inst|altpll_component|auto_generated|pll1\, inst|altpll_component|auto_generated|pll1, MainController, 1
instance = comp, \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl\, inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, MainController, 1
instance = comp, \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl\, inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl, MainController, 1