library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity LedBlink is

Port ( 
	clk : in STD_LOGIC;
	led : out STD_LOGIC
	);
end LedBlink;

architecture Behavioral of LedBlink is
	signal counter : natural range 0 to 16666667 := 0;
	signal ledBuf : STD_LOGIC := '1';
begin		

	process(clk)
	begin
		if rising_edge(clk) then
			if counter < 16666667 then
				counter <= counter + 1;
			else
				counter <= 0;
				ledBuf <= not ledBuf;				
			end if;
		end if;	
	end process;
	
	led <= ledBuf;
	
end Behavioral;