# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.1.0 Build 162 10/23/2013 SJ Full Version # Date created = 14:32:32 March 04, 2024 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # MainController_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone III" set_global_assignment -name DEVICE EP3C25Q240C8 set_global_assignment -name TOP_LEVEL_ENTITY MainController set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:32:32 MARCH 04, 2024" set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation set_global_assignment -name BDF_FILE MainController.bdf set_global_assignment -name QIP_FILE AlteraPLL.qip set_global_assignment -name VHDL_FILE RAM.vhd set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name VHDL_FILE LedBlink.vhd set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_location_assignment PIN_166 -to FPGA_LED_1 set_location_assignment PIN_224 -to Data[5] set_location_assignment PIN_223 -to Data[6] set_location_assignment PIN_226 -to Data[4] set_location_assignment PIN_230 -to Address[6] set_location_assignment PIN_231 -to Address[1] set_location_assignment PIN_232 -to Address[4] set_location_assignment PIN_233 -to Address[3] set_location_assignment PIN_234 -to Address[2] set_location_assignment PIN_235 -to Address[5] set_location_assignment PIN_221 -to Data[7] set_location_assignment PIN_196 -to Address[0] set_location_assignment PIN_195 -to Address[7] set_location_assignment PIN_194 -to Data[0] set_location_assignment PIN_189 -to Data[1] set_location_assignment PIN_188 -to Data[2] set_location_assignment PIN_187 -to Data[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[7] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[4] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[7] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[4] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_LED_1 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nCE set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nOE set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nWE set_location_assignment PIN_217 -to nOE set_location_assignment PIN_218 -to nWE set_location_assignment PIN_219 -to nCE set_location_assignment PIN_31 -to FPGA_CLK set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top