/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.1")) (symbol (rect 16 16 160 128) (text "DigitalInversion" (rect 5 0 64 12)(font "Arial" )) (text "inst" (rect 8 96 20 108)(font "Arial" )) (port (pt 0 32) (input) (text "clk" (rect 0 0 10 12)(font "Arial" )) (text "clk" (rect 21 27 31 39)(font "Arial" )) (line (pt 0 32)(pt 16 32)(line_width 1)) ) (port (pt 0 48) (input) (text "input" (rect 0 0 17 12)(font "Arial" )) (text "input" (rect 21 43 38 55)(font "Arial" )) (line (pt 0 48)(pt 16 48)(line_width 1)) ) (port (pt 0 64) (input) (text "ce" (rect 0 0 9 12)(font "Arial" )) (text "ce" (rect 21 59 30 71)(font "Arial" )) (line (pt 0 64)(pt 16 64)(line_width 1)) ) (port (pt 144 32) (output) (text "output" (rect 0 0 23 12)(font "Arial" )) (text "output" (rect 100 27 123 39)(font "Arial" )) (line (pt 144 32)(pt 128 32)(line_width 1)) ) (port (pt 144 48) (output) (text "noutput" (rect 0 0 28 12)(font "Arial" )) (text "noutput" (rect 95 43 123 55)(font "Arial" )) (line (pt 144 48)(pt 128 48)(line_width 1)) ) (drawing (rectangle (rect 16 16 128 96)(line_width 1)) ) )