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Добавил блок SerialBusMaster. Описание адресного пространства https://docs.google.com/spreadsheets/d/1YiDgJD9m-7imFdXdC5MSfWhiwEYSqdSyA5iGffnVPWk/edit#gid=159505595.

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sokolovstanislav 2024-03-26 14:29:23 +03:00
parent 2a0c20ebc0
commit fdccda960f
3 changed files with 198 additions and 188 deletions
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335
MainController/MainController.bdf
View File

@ -136,11 +136,11 @@ applicable agreement for further details.
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(pin (pin
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(text "FPGA_LED_1" (rect 90 0 158 12)(font "Arial" )) (text "FPGA_LED_1" (rect 90 0 158 12)(font "Arial" ))
(pt 0 8) (pt 0 8)
@ -153,11 +153,11 @@ applicable agreement for further details.
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(pin (pin
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(text "FPGA_LED_2" (rect 90 0 158 12)(font "Arial" )) (text "FPGA_LED_2" (rect 90 0 158 12)(font "Arial" ))
(pt 0 8) (pt 0 8)
@ -170,11 +170,11 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12)) (line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8)) (line (pt 78 12)(pt 82 8))
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(annotation_block (location)(rect 1512 112 1568 128)) (annotation_block (location)(rect 2016 112 2072 128))
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(pin (pin
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(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "FPGA_LED_3" (rect 90 0 158 12)(font "Arial" )) (text "FPGA_LED_3" (rect 90 0 158 12)(font "Arial" ))
(pt 0 8) (pt 0 8)
@ -187,7 +187,7 @@ applicable agreement for further details.
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@ -204,7 +204,7 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12)) (line (pt 82 8)(pt 78 12))
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@ -221,26 +221,25 @@ applicable agreement for further details.
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(pt 176 8) (pt 0 8)
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@ -324,6 +323,131 @@ applicable agreement for further details.
(line (pt 8 8)(pt 24 8)) (line (pt 8 8)(pt 24 8))
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) )
(symbol
(rect 1040 256 1368 368)
(text "RAM" (rect 5 0 28 12)(font "Arial" ))
(text "inst1" (rect 8 96 31 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "address[address_bus_width-1..0]" (rect 0 0 161 12)(font "Arial" ))
(text "address[address_bus_width-1..0]" (rect 21 27 182 39)(font "Arial" ))
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(line (pt 328 32)(pt 312 32)(line_width 3))
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(parameter
"DATA_BUS_WIDTH"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"ADDRESS_BUS_WIDTH"
"9"
""
(type "PARAMETER_SIGNED_DEC") )
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(text "clk" (rect 21 27 36 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
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(drawing
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)
(symbol (symbol
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(text "RAM9X8_SerialBusMaster" (rect 5 0 131 12)(font "Arial" )) (text "RAM9X8_SerialBusMaster" (rect 5 0 131 12)(font "Arial" ))
@ -411,6 +535,16 @@ applicable agreement for further details.
"3" "3"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CONTROL_UPPER_BYTE"
"4"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CONTROL_LOWER_BYTE"
"5"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"DATA_BUS_WIDTH" "DATA_BUS_WIDTH"
"8" "8"
@ -424,132 +558,7 @@ applicable agreement for further details.
(drawing (drawing
(rectangle (rect 16 16 312 128)) (rectangle (rect 16 16 312 128))
) )
(annotation_block (parameter)(rect 1040 432 1333 530)) (annotation_block (parameter)(rect 1040 416 1360 544))
)
(symbol
(rect 1040 256 1368 368)
(text "RAM" (rect 5 0 28 12)(font "Arial" ))
(text "inst1" (rect 8 96 31 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "address[address_bus_width-1..0]" (rect 0 0 161 12)(font "Arial" ))
(text "address[address_bus_width-1..0]" (rect 21 27 182 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
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(text "we" (rect 21 43 33 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
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(line (pt 0 64)(pt 16 64))
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(port
(pt 0 80)
(input)
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(text "ce" (rect 21 75 32 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80))
)
(port
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(bidir)
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(text "data[data_bus_width-1..0]" (rect 208 27 334 39)(font "Arial" ))
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"DATA_BUS_WIDTH"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"ADDRESS_BUS_WIDTH"
"9"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 312 96))
)
(annotation_block (parameter)(rect 1040 208 1280 256))
)
(symbol
(rect 704 208 936 336)
(text "DigitalFilterBlock" (rect 5 0 95 14)(font "Arial" (font_size 8)))
(text "inst3" (rect 8 112 31 124)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "clk" (rect 21 27 36 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
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(port
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(line (pt 0 48)(pt 16 48))
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(input)
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(input)
(text "addressin[8..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
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(line (pt 232 32)(pt 216 32))
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(port
(pt 232 48)
(output)
(text "oeout" (rect 0 0 31 14)(font "Arial" (font_size 8)))
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(line (pt 232 48)(pt 216 48))
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(port
(pt 232 64)
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(text "weout" (rect 0 0 36 14)(font "Arial" (font_size 8)))
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(line (pt 232 64)(pt 216 64))
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(port
(pt 232 80)
(output)
(text "addressout[8..0]" (rect 0 0 93 14)(font "Arial" (font_size 8)))
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(line (pt 232 80)(pt 216 80)(line_width 3))
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(drawing
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(connector (connector
(pt 560 32) (pt 560 32)
@ -659,11 +668,6 @@ applicable agreement for further details.
(pt 704 240) (pt 704 240)
(pt 680 240) (pt 680 240)
) )
(connector
(pt 544 408)
(pt 1440 408)
(bus)
)
(connector (connector
(pt 952 240) (pt 952 240)
(pt 952 336) (pt 952 336)
@ -680,10 +684,6 @@ applicable agreement for further details.
(pt 680 -16) (pt 680 -16)
(pt 936 -16) (pt 936 -16)
) )
(connector
(pt 824 32)
(pt 1336 32)
)
(connector (connector
(pt 608 32) (pt 608 32)
(pt 608 136) (pt 608 136)
@ -713,16 +713,6 @@ applicable agreement for further details.
(pt 1040 640) (pt 1040 640)
(pt 952 640) (pt 952 640)
) )
(connector
(pt 1440 288)
(pt 1440 408)
(bus)
)
(connector
(pt 1368 288)
(pt 1440 288)
(bus)
)
(connector (connector
(pt 856 136) (pt 856 136)
(pt 936 136) (pt 936 136)
@ -731,6 +721,15 @@ applicable agreement for further details.
(pt 936 -16) (pt 936 -16)
(pt 936 136) (pt 936 136)
) )
(connector
(pt 824 32)
(pt 1840 32)
)
(connector
(pt 1840 288)
(pt 1368 288)
(bus)
)
(junction (pt 608 32)) (junction (pt 608 32))
(junction (pt 1000 288)) (junction (pt 1000 288))
(junction (pt 984 304)) (junction (pt 984 304))

10
MainController/RAM9X8_SerialBusMaster.bsf
View File

@ -106,6 +106,16 @@ applicable agreement for further details.
"3" "3"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CONTROL_UPPER_BYTE"
"4"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CONTROL_LOWER_BYTE"
"5"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"DATA_BUS_WIDTH" "DATA_BUS_WIDTH"
"8" "8"

41
MainController/RAM9X8_SerialBusMaster.vhd
View File

@ -8,6 +8,8 @@ entity RAM9X8_SerialBusMaster is
REG_ADDR_DATA_LOWER_BYTE : integer := 1; REG_ADDR_DATA_LOWER_BYTE : integer := 1;
REG_ADDR_CMD_UPPER_BYTE : integer := 2; REG_ADDR_CMD_UPPER_BYTE : integer := 2;
REG_ADDR_CMD_LOWER_BYTE : integer := 3; REG_ADDR_CMD_LOWER_BYTE : integer := 3;
REG_ADDR_CONTROL_UPPER_BYTE : integer := 4;
REG_ADDR_CONTROL_LOWER_BYTE : integer := 5;
DATA_BUS_WIDTH : integer := 8; DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9 ADDRESS_BUS_WIDTH : integer := 9
@ -30,9 +32,10 @@ end entity;
architecture behavorial of RAM9X8_SerialBusMaster is architecture behavorial of RAM9X8_SerialBusMaster is
signal dataBufIn : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0); signal dataBufIn : std_logic_vector(15 downto 0) := (others => '0');
signal dataBufOut : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0); signal dataBufOut : std_logic_vector(15 downto 0) := (others => '0');
signal cmdBuf : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0); signal cmdBuf : std_logic_vector(15 downto 0) := (others => '0');
signal controlBuf : std_logic_vector(15 downto 0) := (others => '0');
signal direction : std_logic := '0'; signal direction : std_logic := '0';
signal addressToTransmit : std_logic_vector(7 downto 0) := x"00"; signal addressToTransmit : std_logic_vector(7 downto 0) := x"00";
@ -55,11 +58,12 @@ signal startPrev : std_logic := '0';
begin begin
process (we, oe, ce) process (we, oe, ce)
variable addr : integer range 0 to 511 := 0; variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
begin begin
if (ce = '0') then -- Если микросхема выбрана if (ce = '0') then -- Если микросхема выбрана
addr := conv_integer(address); addr := conv_integer(address);
if (addr = REG_ADDR_DATA_UPPER_BYTE or addr = REG_ADDR_DATA_LOWER_BYTE or addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE) then if (addr = REG_ADDR_DATA_UPPER_BYTE or addr = REG_ADDR_DATA_LOWER_BYTE or addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE
or addr = REG_ADDR_CONTROL_UPPER_BYTE or addr = REG_ADDR_CONTROL_LOWER_BYTE) then
if (oe = '0') then -- Если сигнал чтения активен if (oe = '0') then -- Если сигнал чтения активен
case addr is case addr is
when REG_ADDR_DATA_UPPER_BYTE => when REG_ADDR_DATA_UPPER_BYTE =>
@ -70,6 +74,10 @@ begin
data <= cmdBuf(15 downto 8); data <= cmdBuf(15 downto 8);
when REG_ADDR_CMD_LOWER_BYTE => when REG_ADDR_CMD_LOWER_BYTE =>
data <= cmdBuf(7 downto 0); data <= cmdBuf(7 downto 0);
when REG_ADDR_CONTROL_UPPER_BYTE =>
data <= controlBuf(15 downto 8);
when REG_ADDR_CONTROL_UPPER_BYTE =>
data <= controlBuf(7 downto 0);
when others => when others =>
data <= (others => 'Z'); -- Запретить запись на шину data <= (others => 'Z'); -- Запретить запись на шину
end case; end case;
@ -125,6 +133,7 @@ begin
dataCRC(15 downto 0) <= dataBufIn; dataCRC(15 downto 0) <= dataBufIn;
CommunicationState <= TransmitAddress; CommunicationState <= TransmitAddress;
lineBusy <= '1'; lineBusy <= '1';
controlBuf <= (others => '0');
end if; end if;
when TransmitAddress => when TransmitAddress =>
if bitCnt = -1 then if bitCnt = -1 then
@ -182,7 +191,6 @@ begin
if readyCRC = '1' then if readyCRC = '1' then
if bitCnt = -1 then if bitCnt = -1 then
CommunicationState <= TransmitCheck; CommunicationState <= TransmitCheck;
--errors(1) <= '0';
else else
if count < count and state = 1 then if count < count and state = 1 then
sbdataout <= CRC(bitCnt); sbdataout <= CRC(bitCnt);
@ -202,8 +210,7 @@ begin
end if; end if;
else else
CommunicationState <= Waiting; CommunicationState <= Waiting;
--errors(1) <= '1'; controlBuf(15) <= '1';
--countError1 <= countError1 + 1;
end if; end if;
when TransmitCheck => when TransmitCheck =>
if count < countValue and state = 1 then if count < countValue and state = 1 then
@ -213,11 +220,9 @@ begin
count := 0; count := 0;
state := 0; state := 0;
if sbdatain = '0' then if sbdatain = '0' then
--countSuccessfulTransmite <= countSuccessfulTransmite + 1; controlBuf(0) <= '1';
--errors(0) <= '0';
else else
--errors(0) <= '1'; controlBuf(14) <= '1';
--countError0 <= countError0 + 1;
end if; end if;
CommunicationState <= Waiting; CommunicationState <= Waiting;
end if; end if;
@ -271,17 +276,13 @@ begin
when ReceiveCheck => when ReceiveCheck =>
if readyCRC = '1' then if readyCRC = '1' then
if bufCRC = CRC then if bufCRC = CRC then
--countSuccessfulReceive <= countSuccessfulReceive + 1;
dataBufOut <= dataFromDevices; dataBufOut <= dataFromDevices;
--errors(3) <= '0'; controlBuf(0) <= '1';
else else
--errors(3) <= '1'; controlBuf(13) <= '1';
--countError3 <= countError3 + 1; end if;
end if;
--errors(2) <= '0';
else else
--errors(2) <= '1'; controlBuf(12) <= '1';
--countError2 <= countError2 + 1;
end if; end if;
CommunicationState <= Waiting; CommunicationState <= Waiting;
when others => when others =>