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Ввели фазовый сдвиг на 4 такта для сигнала WE, так как в режиме записи не успевали выставляться данные на шину данных и ПЛИС зачитывала нули по всем битам. Это помогло стабилизировать запись. Чтение работает хорошо. Полный цикл записи или чтения бвух байт равен примерно 200нс.

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sokolovstanislav 2024-03-19 18:39:41 +03:00
parent b1038bfc75
commit f3a7b565e4
7 changed files with 262 additions and 233 deletions
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50
MainController/DigitalFilter3.bsf Normal file
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@ -0,0 +1,50 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 160 96)
(text "DigitalFilter3" (rect 5 0 51 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 27 31 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "input" (rect 0 0 17 12)(font "Arial" ))
(text "input" (rect 21 43 38 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 32)
(output)
(text "output" (rect 0 0 23 12)(font "Arial" ))
(text "output" (rect 100 27 123 39)(font "Arial" ))
(line (pt 144 32)(pt 128 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 128 64)(line_width 1))
)
)

48
MainController/DigitalFilter3.vhd Normal file
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@ -0,0 +1,48 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DigitalFilter3 is
port(
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC
);
end DigitalFilter3;
architecture Behavioral of DigitalFilter3 is
signal count : natural range 0 to 3 := 0;
signal latch : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if input = '1' then
if latch = '0' then
latch <= '1';
count <= 0;
else
if count < 3 then
count <= count + 1;
else
output <= '1';
count <= 0;
end if;
end if;
else
if latch = '1' then
latch <= '0';
count <= 0;
else
if count < 3 then
count <= count + 1;
else
output <= '0';
count <= 0;
end if;
end if;
end if;
end if;
end process;
end Behavioral;

14
MainController/DigitalFilterBlock.bdf
View File

@ -23,7 +23,7 @@ applicable agreement for further details.
(input) (input)
(rect 416 -80 584 -64) (rect 416 -80 584 -64)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "clk" (rect 5 0 20 12)(font "Arial" )) (text "clk" (rect 5 0 19 12)(font "Arial" ))
(pt 168 8) (pt 168 8)
(drawing (drawing
(line (pt 84 12)(pt 109 12)) (line (pt 84 12)(pt 109 12))
@ -39,7 +39,7 @@ applicable agreement for further details.
(input) (input)
(rect 416 -48 584 -32) (rect 416 -48 584 -32)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "cein" (rect 5 0 26 12)(font "Arial" )) (text "cein" (rect 5 0 25 12)(font "Arial" ))
(pt 168 8) (pt 168 8)
(drawing (drawing
(line (pt 84 12)(pt 109 12)) (line (pt 84 12)(pt 109 12))
@ -55,7 +55,7 @@ applicable agreement for further details.
(input) (input)
(rect 416 40 584 56) (rect 416 40 584 56)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "oein" (rect 5 0 26 12)(font "Arial" )) (text "oein" (rect 5 0 25 12)(font "Arial" ))
(pt 168 8) (pt 168 8)
(drawing (drawing
(line (pt 84 12)(pt 109 12)) (line (pt 84 12)(pt 109 12))
@ -71,7 +71,7 @@ applicable agreement for further details.
(input) (input)
(rect 416 128 584 144) (rect 416 128 584 144)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "wein" (rect 5 0 27 12)(font "Arial" )) (text "wein" (rect 5 0 26 12)(font "Arial" ))
(pt 168 8) (pt 168 8)
(drawing (drawing
(line (pt 84 12)(pt 109 12)) (line (pt 84 12)(pt 109 12))
@ -87,7 +87,7 @@ applicable agreement for further details.
(input) (input)
(rect 416 216 584 232) (rect 416 216 584 232)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "addressin[8..0]" (rect 5 0 79 12)(font "Arial" )) (text "addressin[8..0]" (rect 5 0 78 12)(font "Arial" ))
(pt 168 8) (pt 168 8)
(drawing (drawing
(line (pt 84 12)(pt 109 12)) (line (pt 84 12)(pt 109 12))
@ -484,8 +484,8 @@ applicable agreement for further details.
) )
(symbol (symbol
(rect 792 88 936 168) (rect 792 88 936 168)
(text "DigitalFilter2" (rect 5 0 66 12)(font "Arial" )) (text "DigitalFilter3" (rect 5 0 66 12)(font "Arial" ))
(text "inst11" (rect 8 64 37 76)(font "Arial" )) (text "inst" (rect 8 64 25 76)(font "Arial" ))
(port (port
(pt 0 32) (pt 0 32)
(input) (input)

195
MainController/MainController.bdf
View File

@ -327,7 +327,7 @@ applicable agreement for further details.
(symbol (symbol
(rect 704 208 936 336) (rect 704 208 936 336)
(text "DigitalFilterBlock" (rect 5 0 95 14)(font "Arial" (font_size 8))) (text "DigitalFilterBlock" (rect 5 0 95 14)(font "Arial" (font_size 8)))
(text "inst7" (rect 8 112 31 124)(font "Arial" )) (text "inst12" (rect 8 112 37 124)(font "Arial" ))
(port (port
(pt 0 32) (pt 0 32)
(input) (input)
@ -395,10 +395,53 @@ applicable agreement for further details.
(rectangle (rect 16 16 216 112)) (rectangle (rect 16 16 216 112))
) )
) )
(symbol
(rect 1040 256 1232 368)
(text "RAM9X8" (rect 5 0 46 12)(font "Arial" ))
(text "inst13" (rect 8 96 37 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "address[8..0]" (rect 0 0 64 12)(font "Arial" ))
(text "address[8..0]" (rect 21 27 85 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "we" (rect 0 0 12 12)(font "Arial" ))
(text "we" (rect 21 43 33 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "oe" (rect 0 0 11 12)(font "Arial" ))
(text "oe" (rect 21 59 32 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "ce" (rect 0 0 11 12)(font "Arial" ))
(text "ce" (rect 21 75 32 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 192 32)
(bidir)
(text "data[7..0]" (rect 0 0 47 12)(font "Arial" ))
(text "data[7..0]" (rect 135 27 182 39)(font "Arial" ))
(line (pt 192 32)(pt 176 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 176 96))
)
)
(symbol (symbol
(rect 1040 544 1368 688) (rect 1040 544 1368 688)
(text "RAM9X8_SerialBusMaster" (rect 5 0 131 12)(font "Arial" )) (text "RAM9X8_SerialBusMaster" (rect 5 0 131 12)(font "Arial" ))
(text "inst11" (rect 8 128 37 140)(font "Arial" )) (text "inst4" (rect 8 128 31 140)(font "Arial" ))
(port (port
(pt 0 32) (pt 0 32)
(input) (input)
@ -495,50 +538,7 @@ applicable agreement for further details.
(drawing (drawing
(rectangle (rect 16 16 312 128)) (rectangle (rect 16 16 312 128))
) )
(annotation_block (parameter)(rect 1056 688 1352 792)) (annotation_block (parameter)(rect 1040 432 1333 530))
)
(symbol
(rect 1040 256 1232 368)
(text "RAM9X8" (rect 5 0 46 12)(font "Arial" ))
(text "inst3" (rect 8 96 31 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "address[8..0]" (rect 0 0 64 12)(font "Arial" ))
(text "address[8..0]" (rect 21 27 85 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "we" (rect 0 0 12 12)(font "Arial" ))
(text "we" (rect 21 43 33 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "oe" (rect 0 0 11 12)(font "Arial" ))
(text "oe" (rect 21 59 32 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "ce" (rect 0 0 11 12)(font "Arial" ))
(text "ce" (rect 21 75 32 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 192 32)
(bidir)
(text "data[7..0]" (rect 0 0 47 12)(font "Arial" ))
(text "data[7..0]" (rect 135 27 182 39)(font "Arial" ))
(line (pt 192 32)(pt 176 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 176 96))
)
) )
(connector (connector
(pt 560 32) (pt 560 32)
@ -577,10 +577,6 @@ applicable agreement for further details.
(pt 544 304) (pt 544 304)
(bus) (bus)
) )
(connector
(pt 608 32)
(pt 608 136)
)
(connector (connector
(pt 1040 336) (pt 1040 336)
(pt 952 336) (pt 952 336)
@ -652,59 +648,86 @@ applicable agreement for further details.
(pt 704 240) (pt 704 240)
(pt 680 240) (pt 680 240)
) )
(connector
(pt 680 240)
(pt 680 576)
)
(connector
(pt 680 576)
(pt 1016 576)
)
(connector (connector
(pt 544 408) (pt 544 408)
(pt 1440 408) (pt 1440 408)
(bus) (bus)
) )
(connector
(pt 952 32)
(pt 1336 32)
)
(connector
(pt 952 32)
(pt 952 240)
)
(connector (connector
(pt 952 240) (pt 952 240)
(pt 952 336) (pt 952 336)
) )
(connector
(pt 968 136)
(pt 1336 136)
)
(connector
(pt 968 136)
(pt 968 256)
)
(connector (connector
(pt 968 256) (pt 968 256)
(pt 968 320) (pt 968 320)
) )
(connector (connector
(pt 856 120) (pt 1232 288)
(pt 1016 120)
)
(connector
(pt 1016 120)
(pt 1016 576)
)
(connector
(pt 1440 408)
(pt 1440 288) (pt 1440 288)
(bus) (bus)
) )
(connector (connector
(pt 1232 288) (pt 680 240)
(pt 680 -16)
)
(connector
(pt 680 -16)
(pt 936 -16)
)
(connector
(pt 824 32)
(pt 1336 32)
)
(connector
(pt 856 120)
(pt 936 120)
)
(connector
(pt 936 -16)
(pt 936 120)
)
(connector
(pt 608 32)
(pt 608 136)
)
(connector
(pt 1040 576)
(pt 608 576)
)
(connector
(pt 608 136)
(pt 608 576)
)
(connector
(pt 1000 592)
(pt 1040 592)
(bus)
)
(connector
(pt 1040 608)
(pt 984 608)
)
(connector
(pt 1040 624)
(pt 968 624)
)
(connector
(pt 1040 640)
(pt 952 640)
)
(connector
(pt 1368 576)
(pt 1440 576)
(bus)
)
(connector
(pt 1440 288) (pt 1440 288)
(pt 1440 408)
(bus)
)
(connector
(pt 1440 408)
(pt 1440 576)
(bus) (bus)
) )
(junction (pt 608 32)) (junction (pt 608 32))
@ -712,5 +735,5 @@ applicable agreement for further details.
(junction (pt 984 304)) (junction (pt 984 304))
(junction (pt 968 320)) (junction (pt 968 320))
(junction (pt 952 336)) (junction (pt 952 336))
(junction (pt 952 240)) (junction (pt 608 136))
(junction (pt 968 256)) (junction (pt 1440 408))

2
MainController/MainController.qsf
View File

@ -120,4 +120,6 @@ set_location_assignment PIN_18 -to SBclk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBclk set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBclk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBdatain set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBdatain
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBdataout set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBdataout
set_global_assignment -name VHDL_FILE DigitalFilter3.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[8]

71
MainController/RAM9X8.vhd
View File

@ -4,8 +4,6 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8 is entity RAM9X8 is
port( port(
-- clk : in std_logic;
data : inout std_logic_vector(7 downto 0); data : inout std_logic_vector(7 downto 0);
address : in std_logic_vector(8 downto 0); address : in std_logic_vector(8 downto 0);
we : in std_logic; we : in std_logic;
@ -19,33 +17,14 @@ architecture behavorial of RAM9X8 is
type mem is array (511 downto 0) of std_logic_vector(7 downto 0); type mem is array (511 downto 0) of std_logic_vector(7 downto 0);
signal memory : mem; signal memory : mem;
--signal cePrev : std_logic := '0';
--type MemoryMachine is (Waiting, ReadingAddress, WritingData, ReadingData);
--signal stateMM : MemoryMachine := Waiting;
begin begin
-- process (CLK_FPGA, nCS, nOE, bWE, A) process (we, oe, ce)
-- begin
-- -- Фильтрация и синхронизация сигналов от процессора
-- if rising_edge(CLK_FPGA) then
-- -- Пример фильтрации сигналов nCS, nOE и bWE
-- filtered_we <= we;
-- filtered_oe <= oe;
-- filtered_ce <= ce;
--
-- -- Пример фильтрации и синхронизации сигнала адреса A
-- --filtered_A <= A;
-- end if;
-- end process;
--
process (we, oe, ce, address)
variable addr : integer range 0 to 511 := 0; variable addr : integer range 0 to 511 := 0;
begin begin
if (ce = '0') then -- Если микросхема выбрана if (ce = '0') then -- Если микросхема выбрана
if (oe = '0') then -- Если сигнал чтения активен
addr := conv_integer(address); addr := conv_integer(address);
if (oe = '0') then -- Если сигнал чтения активен
case addr is case addr is
when 0 => data <= x"AA"; when 0 => data <= x"AA";
when 1 => data <= x"BB"; when 1 => data <= x"BB";
@ -57,10 +36,9 @@ begin
when 7 => data <= x"23"; when 7 => data <= x"23";
when 8 => data <= x"45"; when 8 => data <= x"45";
when 9 => data <= x"67"; when 9 => data <= x"67";
when others => data <= (others => 'Z'); -- Для остальных адресов разрешить чтение when others => data <= not memory(addr);
end case; end case;
elsif (we = '0') then -- Если сигнал записи активен elsif (we = '0') then -- Если сигнал записи активен
addr := conv_integer(address);
memory(addr) <= data; memory(addr) <= data;
else else
data <= (others => 'Z'); -- Запретить запись на шину data <= (others => 'Z'); -- Запретить запись на шину
@ -70,47 +48,4 @@ begin
end if; end if;
end process; end process;
-- process(clk)
-- variable addr : integer range 0 to 511 := 0;
-- begin
-- if rising_edge(clk) then
-- case stateMM is
-- when Waiting =>
-- if ce = '0' and cePrev = '1' then
-- stateMM <= ReadingAddress;
-- end if;
-- data <= (others => 'Z');
-- when ReadingAddress =>
-- addr := conv_integer(address);
-- if oe = '0' then
-- stateMM <= ReadingData;
-- data <= (others => '0');
-- elsif we = '0' then
-- stateMM <= WritingData;
-- elsif ce = '1' then
-- stateMM <= Waiting;
-- end if;
-- when ReadingData =>
-- data <= memory(addr);
-- if ce = '1' then
-- stateMM <= Waiting;
-- end if;
-- when WritingData =>
-- memory(addr) <= data;
-- stateMM <= Waiting;
-- when others =>
-- end case;
-- memory(0) <= x"AA";
-- memory(1) <= x"BB";
-- memory(2) <= x"CC";
-- memory(3) <= x"DD";
-- memory(4) <= x"EE";
-- memory(5) <= x"FF";
-- memory(6) <= x"01";
-- memory(7) <= x"23";
-- memory(8) <= x"45";
-- memory(9) <= memory(9) + 1;
-- end if;
-- end process;
end behavorial; end behavorial;

55
MainController/RAM9X8_SerialBusMaster.vhd
View File

@ -30,16 +30,6 @@ end entity;
architecture behavorial of RAM9X8_SerialBusMaster is architecture behavorial of RAM9X8_SerialBusMaster is
type mem is array (511 downto 0) of std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
signal memory : mem;
signal wePrev : std_logic := '0';
signal oePrev : std_logic := '0';
signal cePrev : std_logic := '0';
type MemoryMachine is (Waiting, Writing, Reading);
signal stateMM : MemoryMachine := Waiting;
signal dataBufIn : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0); signal dataBufIn : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0);
signal dataBufOut : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0); signal dataBufOut : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0);
signal cmdBuf : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0); signal cmdBuf : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0);
@ -64,26 +54,13 @@ signal startPrev : std_logic := '0';
begin begin
process(clk) process (we, oe, ce)
variable addr : integer range 0 to 511 := 0; variable addr : integer range 0 to 511 := 0;
begin begin
if rising_edge(clk) then if (ce = '0') then -- Если микросхема выбрана
case stateMM is
when Waiting =>
if ce = '0' and cePrev = '1' then
addr := conv_integer(address); addr := conv_integer(address);
if (addr = REG_ADDR_DATA_UPPER_BYTE or addr = REG_ADDR_DATA_LOWER_BYTE or addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE) then if (addr = REG_ADDR_DATA_UPPER_BYTE or addr = REG_ADDR_DATA_LOWER_BYTE or addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE) then
if oe = '0' then if (oe = '0') then -- Если сигнал чтения активен
stateMM <= Reading;
else
stateMM <= Writing;
end if;
end if;
else
start <= '0';
data <= (others => 'Z');
end if;
when Reading =>
case addr is case addr is
when REG_ADDR_DATA_UPPER_BYTE => when REG_ADDR_DATA_UPPER_BYTE =>
data <= dataBufOut(15 downto 8); data <= dataBufOut(15 downto 8);
@ -94,14 +71,9 @@ begin
when REG_ADDR_CMD_LOWER_BYTE => when REG_ADDR_CMD_LOWER_BYTE =>
data <= cmdBuf(7 downto 0); data <= cmdBuf(7 downto 0);
when others => when others =>
data <= (others => 'Z'); -- Запретить запись на шину
end case; end case;
if oe = '1' and oePrev = '0' then elsif (we = '0') then -- Если сигнал записи активен
stateMM <= Waiting;
elsif ce = '1' then
stateMM <= Waiting;
end if;
when Writing =>
if we = '0' and wePrev = '1' then
case addr is case addr is
when REG_ADDR_DATA_UPPER_BYTE => when REG_ADDR_DATA_UPPER_BYTE =>
dataBufIn(15 downto 8) <= data; dataBufIn(15 downto 8) <= data;
@ -113,17 +85,16 @@ begin
cmdBuf(7 downto 0) <= data; cmdBuf(7 downto 0) <= data;
start <= '1'; start <= '1';
when others => when others =>
data <= (others => 'Z'); -- Запретить запись на шину
end case; end case;
stateMM <= Waiting; else
elsif ce = '1' then data <= (others => 'Z'); -- Запретить запись на шину
stateMM <= Waiting;
end if; end if;
when others => else
end case; data <= (others => 'Z'); -- Запретить запись на шину
end if;
oePrev <= oe; else
cePrev <= ce; data <= (others => 'Z'); -- Запретить запись на шину
wePrev <= we;
end if; end if;
end process; end process;