From b1038bfc7511fb3cdda319ebf59ef9162f3e9117 Mon Sep 17 00:00:00 2001 From: sokolovstanislav Date: Tue, 19 Mar 2024 11:40:31 +0300 Subject: [PATCH] =?UTF-8?q?=D0=A3=D0=B1=D1=80=D0=B0=D0=BB=D0=B8=20=D0=BA?= =?UTF-8?q?=D0=BE=D0=BD=D0=B5=D1=87=D0=BD=D1=8B=D0=B9=20=D0=B0=D0=B2=D1=82?= =?UTF-8?q?=D0=BE=D0=BC=D0=B0=D1=82=20=D0=B8=D0=B7=20=D1=80=D0=B0=D0=B1?= =?UTF-8?q?=D0=BE=D1=82=D1=8B=20RAM9X8,=20=D1=88=D0=B8=D0=BD=D0=B0=20?= =?UTF-8?q?=D0=B7=D0=B0=D1=80=D0=B0=D0=B1=D0=BE=D1=82=D0=B0=D0=BB=D0=B0=20?= =?UTF-8?q?=D1=81=20=D1=81=D0=B8=D0=BD=D1=85=D1=80=D0=BE=D0=BA=D0=BB=D0=BE?= =?UTF-8?q?=D0=BA=D0=BE=D0=BC=20100=D0=9C=D0=93=D1=86.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- MainController/MainController.bdf | 178 ++++++++++++------------------ MainController/RAM9X8.bsf | 33 +++--- MainController/RAM9X8.vhd | 133 ++++++++++++---------- 3 files changed, 153 insertions(+), 191 deletions(-) diff --git a/MainController/MainController.bdf b/MainController/MainController.bdf index 761f1a7..4893a3a 100644 --- a/MainController/MainController.bdf +++ b/MainController/MainController.bdf @@ -89,7 +89,7 @@ applicable agreement for further details. ) (pin (input) - (rect 376 480 544 496) + (rect 376 584 544 600) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) (text "nBL[1..0]" (rect 5 0 49 12)(font "Arial" )) (pt 168 8) @@ -102,7 +102,7 @@ applicable agreement for further details. (line (pt 109 12)(pt 113 8)) ) (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 296 496 352 528)) + (annotation_block (location)(rect 296 600 352 632)) ) (pin (input) @@ -125,7 +125,7 @@ applicable agreement for further details. (input) (rect 376 648 544 664) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) - (text "SBdatain" (rect 5 0 49 12)(font "Arial" )) + (text "SBdatain" (rect 5 0 48 12)(font "Arial" )) (pt 168 8) (drawing (line (pt 84 12)(pt 109 12)) @@ -225,7 +225,7 @@ applicable agreement for further details. ) (pin (bidir) - (rect 368 312 544 328) + (rect 368 400 544 416) (text "BIDIR" (rect 151 0 175 10)(font "Arial" (font_size 6))) (text "Data[7..0]" (rect 5 0 54 12)(font "Arial" )) (pt 176 8) @@ -240,7 +240,7 @@ applicable agreement for further details. ) (flipy) (text "VCC" (rect 152 7 172 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 296 328 352 440)) + (annotation_block (location)(rect 296 416 352 528)) ) (symbol (rect 704 88 856 200) @@ -498,43 +498,36 @@ applicable agreement for further details. (annotation_block (parameter)(rect 1056 688 1352 792)) ) (symbol - (rect 1040 240 1232 384) + (rect 1040 256 1232 368) (text "RAM9X8" (rect 5 0 46 12)(font "Arial" )) - (text "inst15" (rect 8 128 37 140)(font "Arial" )) + (text "inst3" (rect 8 96 31 108)(font "Arial" )) (port (pt 0 32) (input) - (text "clk" (rect 0 0 14 12)(font "Arial" )) - (text "clk" (rect 21 27 35 39)(font "Arial" )) - (line (pt 0 32)(pt 16 32)) + (text "address[8..0]" (rect 0 0 64 12)(font "Arial" )) + (text "address[8..0]" (rect 21 27 85 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) ) (port (pt 0 48) (input) - (text "address[8..0]" (rect 0 0 64 12)(font "Arial" )) - (text "address[8..0]" (rect 21 43 85 55)(font "Arial" )) - (line (pt 0 48)(pt 16 48)(line_width 3)) + (text "we" (rect 0 0 12 12)(font "Arial" )) + (text "we" (rect 21 43 33 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) - (text "we" (rect 0 0 12 12)(font "Arial" )) - (text "we" (rect 21 59 33 71)(font "Arial" )) + (text "oe" (rect 0 0 11 12)(font "Arial" )) + (text "oe" (rect 21 59 32 71)(font "Arial" )) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) - (text "oe" (rect 0 0 11 12)(font "Arial" )) - (text "oe" (rect 21 75 32 87)(font "Arial" )) - (line (pt 0 80)(pt 16 80)) - ) - (port - (pt 0 96) - (input) (text "ce" (rect 0 0 11 12)(font "Arial" )) - (text "ce" (rect 21 91 32 103)(font "Arial" )) - (line (pt 0 96)(pt 16 96)) + (text "ce" (rect 21 75 32 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)) ) (port (pt 192 32) @@ -544,7 +537,7 @@ applicable agreement for further details. (line (pt 192 32)(pt 176 32)(line_width 3)) ) (drawing - (rectangle (rect 16 16 176 128)) + (rectangle (rect 16 16 176 96)) ) ) (connector @@ -567,14 +560,6 @@ applicable agreement for further details. (pt 608 136) (pt 704 136) ) -(connector - (pt 704 240) - (pt 608 240) -) -(connector - (pt 608 136) - (pt 608 240) -) (connector (pt 544 256) (pt 704 256) @@ -592,44 +577,10 @@ applicable agreement for further details. (pt 544 304) (bus) ) -(connector - (pt 608 -8) - (pt 608 32) -) (connector (pt 608 32) (pt 608 136) ) -(connector - (pt 680 408) - (pt 680 320) - (bus) -) -(connector - (pt 544 320) - (pt 680 320) - (bus) -) -(connector - (pt 608 -8) - (pt 1016 -8) -) -(connector - (pt 1016 272) - (pt 1040 272) -) -(connector - (pt 1040 576) - (pt 1016 576) -) -(connector - (pt 1016 -8) - (pt 1016 272) -) -(connector - (pt 1016 272) - (pt 1016 576) -) (connector (pt 1040 336) (pt 952 336) @@ -654,11 +605,6 @@ applicable agreement for further details. (pt 1040 304) (pt 984 304) ) -(connector - (pt 1040 592) - (pt 1000 592) - (bus) -) (connector (pt 1000 592) (pt 1000 288) @@ -674,10 +620,6 @@ applicable agreement for further details. (pt 1040 288) (bus) ) -(connector - (pt 1040 608) - (pt 984 608) -) (connector (pt 984 272) (pt 984 304) @@ -686,40 +628,14 @@ applicable agreement for further details. (pt 984 304) (pt 984 608) ) -(connector - (pt 1040 624) - (pt 968 624) -) -(connector - (pt 968 256) - (pt 968 320) -) (connector (pt 968 320) (pt 968 624) ) -(connector - (pt 1040 640) - (pt 952 640) -) -(connector - (pt 952 240) - (pt 952 336) -) (connector (pt 952 336) (pt 952 640) ) -(connector - (pt 680 408) - (pt 1440 408) - (bus) -) -(connector - (pt 1232 272) - (pt 1440 272) - (bus) -) (connector (pt 1368 592) (pt 1848 592) @@ -733,26 +649,68 @@ applicable agreement for further details. (pt 544 656) ) (connector - (pt 1440 272) + (pt 704 240) + (pt 680 240) +) +(connector + (pt 680 240) + (pt 680 576) +) +(connector + (pt 680 576) + (pt 1016 576) +) +(connector + (pt 544 408) (pt 1440 408) (bus) ) (connector - (pt 856 136) + (pt 952 32) + (pt 1336 32) +) +(connector + (pt 952 32) + (pt 952 240) +) +(connector + (pt 952 240) + (pt 952 336) +) +(connector + (pt 968 136) (pt 1336 136) ) (connector - (pt 856 120) - (pt 1336 120) + (pt 968 136) + (pt 968 256) ) (connector - (pt 824 32) - (pt 1336 32) + (pt 968 256) + (pt 968 320) +) +(connector + (pt 856 120) + (pt 1016 120) +) +(connector + (pt 1016 120) + (pt 1016 576) +) +(connector + (pt 1440 408) + (pt 1440 288) + (bus) +) +(connector + (pt 1232 288) + (pt 1440 288) + (bus) ) -(junction (pt 608 136)) (junction (pt 608 32)) -(junction (pt 1016 272)) (junction (pt 1000 288)) (junction (pt 984 304)) (junction (pt 968 320)) (junction (pt 952 336)) +(junction (pt 952 240)) +(junction (pt 968 256)) diff --git a/MainController/RAM9X8.bsf b/MainController/RAM9X8.bsf index bdd0615..59f02c2 100644 --- a/MainController/RAM9X8.bsf +++ b/MainController/RAM9X8.bsf @@ -20,43 +20,36 @@ applicable agreement for further details. */ (header "symbol" (version "1.1")) (symbol - (rect 16 16 208 160) + (rect 16 16 208 128) (text "RAM9X8" (rect 5 0 45 12)(font "Arial" )) - (text "inst" (rect 8 128 20 140)(font "Arial" )) + (text "inst" (rect 8 96 20 108)(font "Arial" )) (port (pt 0 32) (input) - (text "clk" (rect 0 0 10 12)(font "Arial" )) - (text "clk" (rect 21 27 31 39)(font "Arial" )) - (line (pt 0 32)(pt 16 32)(line_width 1)) + (text "address[8..0]" (rect 0 0 51 12)(font "Arial" )) + (text "address[8..0]" (rect 21 27 72 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) ) (port (pt 0 48) (input) - (text "address[8..0]" (rect 0 0 51 12)(font "Arial" )) - (text "address[8..0]" (rect 21 43 72 55)(font "Arial" )) - (line (pt 0 48)(pt 16 48)(line_width 3)) + (text "we" (rect 0 0 10 12)(font "Arial" )) + (text "we" (rect 21 43 31 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) ) (port (pt 0 64) (input) - (text "we" (rect 0 0 10 12)(font "Arial" )) - (text "we" (rect 21 59 31 71)(font "Arial" )) + (text "oe" (rect 0 0 9 12)(font "Arial" )) + (text "oe" (rect 21 59 30 71)(font "Arial" )) (line (pt 0 64)(pt 16 64)(line_width 1)) ) (port (pt 0 80) (input) - (text "oe" (rect 0 0 9 12)(font "Arial" )) - (text "oe" (rect 21 75 30 87)(font "Arial" )) - (line (pt 0 80)(pt 16 80)(line_width 1)) - ) - (port - (pt 0 96) - (input) (text "ce" (rect 0 0 9 12)(font "Arial" )) - (text "ce" (rect 21 91 30 103)(font "Arial" )) - (line (pt 0 96)(pt 16 96)(line_width 1)) + (text "ce" (rect 21 75 30 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 1)) ) (port (pt 192 32) @@ -66,6 +59,6 @@ applicable agreement for further details. (line (pt 192 32)(pt 176 32)(line_width 3)) ) (drawing - (rectangle (rect 16 16 176 128)(line_width 1)) + (rectangle (rect 16 16 176 96)(line_width 1)) ) ) diff --git a/MainController/RAM9X8.vhd b/MainController/RAM9X8.vhd index 9629c49..0f04ab4 100644 --- a/MainController/RAM9X8.vhd +++ b/MainController/RAM9X8.vhd @@ -4,7 +4,7 @@ use ieee.std_logic_unsigned.all; entity RAM9X8 is port( - clk : in std_logic; + -- clk : in std_logic; data : inout std_logic_vector(7 downto 0); address : in std_logic_vector(8 downto 0); @@ -19,10 +19,10 @@ architecture behavorial of RAM9X8 is type mem is array (511 downto 0) of std_logic_vector(7 downto 0); signal memory : mem; -signal cePrev : std_logic := '0'; +--signal cePrev : std_logic := '0'; -type MemoryMachine is (Waiting, ReadingAddress, WritingData, ReadingData); -signal stateMM : MemoryMachine := Waiting; +--type MemoryMachine is (Waiting, ReadingAddress, WritingData, ReadingData); +--signal stateMM : MemoryMachine := Waiting; begin @@ -40,66 +40,77 @@ begin -- end if; -- end process; -- --- process (filtered_nCS, filtered_nOE, filtered_bWE, filtered_A) --- begin --- if (filtered_nCS = '0') then -- Если микросхема выбрана --- if (filtered_nOE = '0') then -- Если сигнал чтения активен --- D <= (others => 'Z'); -- Запретить запись на шину --- elsif (filtered_bWE = '1') then -- Если сигнал записи активен --- case filtered_A is --- when "00000000" => D <= (others => '0'); -- Адрес 0x00, запись нулей --- when "00000001" => D <= (others => '1'); -- Адрес 0x01, запись единиц --- when others => D <= (others => 'Z'); -- Для остальных адресов разрешить чтение --- end case; --- else --- D <= (others => 'Z'); -- Запретить запись на шину --- end if; --- else --- D <= (others => 'Z'); -- Запретить запись на шину --- end if; --- end process; - - process(clk) + process (we, oe, ce, address) variable addr : integer range 0 to 511 := 0; begin - if rising_edge(clk) then - case stateMM is - when Waiting => - if ce = '0' and cePrev = '1' then - stateMM <= ReadingAddress; - end if; - data <= (others => 'Z'); - when ReadingAddress => - addr := conv_integer(address); - if oe = '0' then - stateMM <= ReadingData; - data <= (others => '0'); - elsif we = '0' then - stateMM <= WritingData; - elsif ce = '1' then - stateMM <= Waiting; - end if; - when ReadingData => - data <= memory(addr); - if ce = '1' then - stateMM <= Waiting; - end if; - when WritingData => - memory(addr) <= data; - stateMM <= Waiting; - when others => - end case; - memory(0) <= x"AA"; - memory(1) <= x"BB"; - memory(2) <= x"CC"; - memory(3) <= x"DD"; - memory(4) <= x"EE"; - memory(5) <= x"FF"; - memory(6) <= x"01"; - memory(7) <= x"23"; - memory(8) <= x"45"; - memory(9) <= memory(9) + 1; + if (ce = '0') then -- Если микросхема выбрана + if (oe = '0') then -- Если сигнал чтения активен + addr := conv_integer(address); + case addr is + when 0 => data <= x"AA"; + when 1 => data <= x"BB"; + when 2 => data <= x"CC"; + when 3 => data <= x"DD"; + when 4 => data <= x"EE"; + when 5 => data <= x"FF"; + when 6 => data <= x"01"; + when 7 => data <= x"23"; + when 8 => data <= x"45"; + when 9 => data <= x"67"; + when others => data <= (others => 'Z'); -- Для остальных адресов разрешить чтение + end case; + elsif (we = '0') then -- Если сигнал записи активен + addr := conv_integer(address); + memory(addr) <= data; + else + data <= (others => 'Z'); -- Запретить запись на шину + end if; + else + data <= (others => 'Z'); -- Запретить запись на шину end if; end process; + +-- process(clk) +-- variable addr : integer range 0 to 511 := 0; +-- begin +-- if rising_edge(clk) then +-- case stateMM is +-- when Waiting => +-- if ce = '0' and cePrev = '1' then +-- stateMM <= ReadingAddress; +-- end if; +-- data <= (others => 'Z'); +-- when ReadingAddress => +-- addr := conv_integer(address); +-- if oe = '0' then +-- stateMM <= ReadingData; +-- data <= (others => '0'); +-- elsif we = '0' then +-- stateMM <= WritingData; +-- elsif ce = '1' then +-- stateMM <= Waiting; +-- end if; +-- when ReadingData => +-- data <= memory(addr); +-- if ce = '1' then +-- stateMM <= Waiting; +-- end if; +-- when WritingData => +-- memory(addr) <= data; +-- stateMM <= Waiting; +-- when others => +-- end case; +-- memory(0) <= x"AA"; +-- memory(1) <= x"BB"; +-- memory(2) <= x"CC"; +-- memory(3) <= x"DD"; +-- memory(4) <= x"EE"; +-- memory(5) <= x"FF"; +-- memory(6) <= x"01"; +-- memory(7) <= x"23"; +-- memory(8) <= x"45"; +-- memory(9) <= memory(9) + 1; +-- end if; +-- end process; end behavorial; \ No newline at end of file