diff --git a/MainController/DigitalFilterBlock.bdf b/MainController/DigitalFilterBlock.bdf new file mode 100644 index 0000000..f483296 --- /dev/null +++ b/MainController/DigitalFilterBlock.bdf @@ -0,0 +1,851 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 416 -80 584 -64) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "clk" (rect 5 0 20 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 416 -48 584 -32) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "cein" (rect 5 0 26 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 416 40 584 56) + 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(pt 1024 472)) +(junction (pt 1024 560)) +(junction (pt 1024 648)) +(junction (pt 1024 736)) +(junction (pt 1024 824)) +(junction (pt 672 224)) +(junction (pt 696 208)) +(junction (pt 696 32)) +(junction (pt 696 120)) +(junction (pt 696 -56)) diff --git a/MainController/DigitalFilterBlock.bsf b/MainController/DigitalFilterBlock.bsf new file mode 100644 index 0000000..949364d --- /dev/null +++ b/MainController/DigitalFilterBlock.bsf @@ -0,0 +1,92 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 248 144) + (text "DigitalFilterBlock" (rect 5 0 95 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 112 25 124)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8))) + (text "clk" (rect 21 27 36 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "cein" (rect 0 0 23 14)(font "Arial" (font_size 8))) + (text "cein" (rect 21 43 44 57)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "oein" (rect 0 0 23 14)(font "Arial" (font_size 8))) + (text "oein" (rect 21 59 44 73)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 0 80) + (input) + (text "wein" (rect 0 0 28 14)(font "Arial" (font_size 8))) + (text "wein" (rect 21 75 49 89)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 16 80)) + ) + (port + (pt 0 96) + (input) + (text "addressin[8..0]" (rect 0 0 84 14)(font "Arial" (font_size 8))) + (text "addressin[8..0]" (rect 21 91 105 105)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 3)) + ) + (port + (pt 232 32) + (output) + (text "ceout" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "ceout" (rect 180 27 211 41)(font "Arial" (font_size 8))) + (line (pt 232 32)(pt 216 32)) + ) + (port + (pt 232 48) + (output) + (text "oeout" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "oeout" (rect 180 43 211 57)(font "Arial" (font_size 8))) + (line (pt 232 48)(pt 216 48)) + ) + (port + (pt 232 64) + (output) + (text "weout" (rect 0 0 36 14)(font "Arial" (font_size 8))) + (text "weout" (rect 175 59 211 73)(font "Arial" (font_size 8))) + (line (pt 232 64)(pt 216 64)) + ) + (port + (pt 232 80) + (output) + (text "addressout[8..0]" (rect 0 0 93 14)(font "Arial" (font_size 8))) + (text "addressout[8..0]" (rect 118 75 211 89)(font "Arial" (font_size 8))) + (line (pt 232 80)(pt 216 80)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 216 112)) + ) +) diff --git a/MainController/MainController.bdf b/MainController/MainController.bdf index 9096d09..761f1a7 100644 --- a/MainController/MainController.bdf +++ b/MainController/MainController.bdf @@ -38,7 +38,7 @@ applicable agreement for further details. ) (pin (input) - (rect 376 288 544 304) + (rect 376 264 544 280) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) (text "nOE" (rect 5 0 26 12)(font "Arial" )) (pt 168 8) @@ -51,11 +51,11 @@ applicable agreement for further details. (line (pt 109 12)(pt 113 8)) ) (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 320 288 376 304)) + (annotation_block (location)(rect 320 264 376 280)) ) (pin (input) - (rect 376 376 544 392) + (rect 376 280 544 296) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) (text "nWE" (rect 5 0 28 12)(font "Arial" )) (pt 168 8) @@ -68,11 +68,11 @@ applicable agreement for further details. (line (pt 109 12)(pt 113 8)) ) (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 320 376 376 392)) + (annotation_block (location)(rect 320 280 376 296)) ) (pin (input) - (rect 376 464 544 480) + (rect 376 248 544 264) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) (text "nCE" (rect 5 0 26 12)(font "Arial" )) (pt 168 8) @@ -85,7 +85,7 @@ applicable agreement for further details. (line (pt 109 12)(pt 113 8)) ) (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 320 464 376 480)) + (annotation_block (location)(rect 320 248 376 264)) ) (pin (input) @@ -102,11 +102,11 @@ applicable agreement for further details. (line (pt 109 12)(pt 113 8)) ) (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 248 496 304 528)) + (annotation_block (location)(rect 296 496 352 528)) ) (pin (input) - (rect 376 216 544 232) + (rect 376 296 544 312) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) (text "Address[8..0]" (rect 5 0 71 12)(font "Arial" )) (pt 168 8) @@ -119,11 +119,28 @@ applicable agreement for further details. (line (pt 109 12)(pt 113 8)) ) (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 320 88 376 216)) + (annotation_block (location)(rect 224 312 280 440)) +) +(pin + (input) + (rect 376 648 544 664) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "SBdatain" (rect 5 0 49 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 328 664 376 680)) ) (pin (output) - (rect 1144 24 1320 40) + (rect 1336 24 1512 40) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "FPGA_LED_1" (rect 90 0 158 12)(font "Arial" )) (pt 0 8) @@ -136,11 +153,11 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 1320 24 1376 40)) + (annotation_block (location)(rect 1512 24 1568 40)) ) (pin (output) - (rect 1144 112 1320 128) + (rect 1336 112 1512 128) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "FPGA_LED_2" (rect 90 0 158 12)(font "Arial" )) (pt 0 8) @@ -153,11 +170,11 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 1320 112 1376 128)) + (annotation_block (location)(rect 1512 112 1568 128)) ) (pin (output) - (rect 1144 128 1320 144) + (rect 1336 128 1512 144) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "FPGA_LED_3" (rect 90 0 158 12)(font "Arial" )) (pt 0 8) @@ -170,11 +187,45 @@ applicable agreement for further details. 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(pt 856 160) - (bus) -) -(connector - (pt 544 240) - (pt 576 240) - (bus) -) -(connector - (pt 576 240) - (pt 856 240) - (bus) -) -(connector - (pt 608 208) - (pt 952 208) -) -(connector - (pt 1168 160) - (pt 1168 208) - (bus) -) -(connector - (pt 608 136) - (pt 608 208) -) -(connector - (pt 544 224) - (pt 592 224) - (bus) -) -(connector - (pt 592 224) - (pt 952 224) - (bus) -) -(connector - (pt 1144 208) - (pt 1168 208) - (bus) -) -(connector - (pt 632 120) - (pt 488 120) + (pt 704 32) ) (connector (pt 488 136) (pt 488 120) ) (connector - (pt 560 624) - (pt 560 296) + (pt 488 120) + (pt 704 120) ) (connector - (pt 632 280) - (pt 608 280) + (pt 608 136) + (pt 704 136) ) (connector - (pt 608 208) - (pt 608 280) + (pt 704 240) + (pt 608 240) ) (connector - (pt 544 296) - (pt 560 296) + (pt 608 136) + (pt 608 240) ) (connector - (pt 560 296) - (pt 632 296) + (pt 544 256) + (pt 704 256) ) (connector - (pt 776 280) - (pt 872 280) + (pt 544 272) + (pt 704 272) ) (connector - (pt 872 280) - (pt 872 256) + (pt 544 288) + (pt 704 288) ) (connector - (pt 952 256) - (pt 872 256) + (pt 704 304) + (pt 544 304) + (bus) ) (connector - (pt 544 384) - (pt 632 384) + (pt 608 -8) + (pt 608 32) ) (connector - (pt 632 368) - (pt 608 368) + (pt 608 32) + (pt 608 136) ) (connector - (pt 608 280) - (pt 608 368) + (pt 680 408) + (pt 680 320) + (bus) ) (connector - (pt 776 368) - (pt 888 368) + (pt 544 320) + (pt 680 320) + (bus) ) (connector - (pt 888 368) - (pt 888 240) + (pt 608 -8) + (pt 1016 -8) +) +(connector + (pt 1016 272) + (pt 1040 272) +) +(connector + (pt 1040 576) + (pt 1016 576) +) +(connector + (pt 1016 -8) + (pt 1016 272) +) +(connector + (pt 1016 272) + (pt 1016 576) +) +(connector + (pt 1040 336) + (pt 952 336) +) +(connector + (pt 936 240) + (pt 952 240) +) +(connector + (pt 936 256) + (pt 968 256) +) +(connector + (pt 1040 320) + (pt 968 320) +) +(connector + (pt 936 272) + (pt 984 272) +) +(connector + (pt 1040 304) + (pt 984 304) +) +(connector + (pt 1040 592) + (pt 1000 592) + (bus) +) +(connector + (pt 1000 592) + (pt 1000 288) + (bus) +) +(connector + (pt 936 288) + (pt 1000 288) + (bus) +) +(connector + (pt 1000 288) + (pt 1040 288) + (bus) +) +(connector + (pt 1040 608) + (pt 984 608) +) +(connector + (pt 984 272) + (pt 984 304) +) +(connector + (pt 984 304) + (pt 984 608) +) +(connector + (pt 1040 624) + (pt 968 624) +) +(connector + (pt 968 256) + (pt 968 320) +) +(connector + (pt 968 320) + (pt 968 624) +) +(connector + (pt 1040 640) + (pt 952 640) ) (connector (pt 952 240) - (pt 888 240) + (pt 952 336) ) (connector - (pt 776 456) - (pt 904 456) + (pt 952 336) + (pt 952 640) ) (connector - (pt 904 456) - (pt 904 272) + (pt 680 408) + (pt 1440 408) + (bus) ) (connector - (pt 952 272) - (pt 904 272) + (pt 1232 272) + (pt 1440 272) + (bus) ) (connector - (pt 632 472) - (pt 544 472) + (pt 1368 592) + (pt 1848 592) ) (connector - (pt 632 456) - (pt 608 456) + (pt 1368 608) + (pt 1848 608) ) (connector - (pt 608 368) - (pt 608 456) + (pt 1040 656) + (pt 544 656) ) (connector - (pt 608 456) - (pt 608 624) + (pt 1440 272) + (pt 1440 408) + (bus) +) +(connector + (pt 856 136) + (pt 1336 136) +) +(connector + (pt 856 120) + (pt 1336 120) +) +(connector + (pt 824 32) + (pt 1336 32) ) -(junction (pt 592 224)) -(junction (pt 576 240)) (junction (pt 608 136)) (junction (pt 608 32)) -(junction (pt 608 208)) -(junction (pt 608 280)) -(junction (pt 560 296)) -(junction (pt 608 368)) -(junction (pt 608 456)) +(junction (pt 1016 272)) +(junction (pt 1000 288)) +(junction (pt 984 304)) +(junction (pt 968 320)) +(junction (pt 952 336)) diff --git a/MainController/MainController.qsf b/MainController/MainController.qsf index 7977875..243531c 100644 --- a/MainController/MainController.qsf +++ b/MainController/MainController.qsf @@ -112,7 +112,12 @@ set_location_assignment PIN_195 -to Address[8] set_global_assignment -name VHDL_FILE DigitalFilter8.vhd set_global_assignment -name VHDL_FILE DigitalFilter16.vhd set_global_assignment -name VHDL_FILE RAM9X8_SerialBusMaster.vhd -set_location_assignment PIN_46 -to SerialBusIn -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SerialBusIn set_global_assignment -name VHDL_FILE DigitalFilter2.vhd +set_global_assignment -name BDF_FILE DigitalFilterBlock.bdf +set_location_assignment PIN_13 -to SBdataout +set_location_assignment PIN_37 -to SBdatain +set_location_assignment PIN_18 -to SBclk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBclk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBdatain +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBdataout set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/MainController/RAM9X8.vhd b/MainController/RAM9X8.vhd index d52dfe8..9629c49 100644 --- a/MainController/RAM9X8.vhd +++ b/MainController/RAM9X8.vhd @@ -10,7 +10,7 @@ entity RAM9X8 is address : in std_logic_vector(8 downto 0); we : in std_logic; oe : in std_logic; - ce : in std_logic + ce : in std_logic ); end entity; @@ -19,18 +19,48 @@ architecture behavorial of RAM9X8 is type mem is array (511 downto 0) of std_logic_vector(7 downto 0); signal memory : mem; -signal wePrev : std_logic := '0'; -signal oePrev : std_logic := '0'; signal cePrev : std_logic := '0'; type MemoryMachine is (Waiting, ReadingAddress, WritingData, ReadingData); signal stateMM : MemoryMachine := Waiting; -begin +begin + +-- process (CLK_FPGA, nCS, nOE, bWE, A) +-- begin +-- -- Фильтрация и синхронизация сигналов от процессора +-- if rising_edge(CLK_FPGA) then +-- -- Пример фильтрации сигналов nCS, nOE и bWE +-- filtered_we <= we; +-- filtered_oe <= oe; +-- filtered_ce <= ce; +-- +-- -- Пример фильтрации и синхронизации сигнала адреса A +-- --filtered_A <= A; +-- end if; +-- end process; +-- +-- process (filtered_nCS, filtered_nOE, filtered_bWE, filtered_A) +-- begin +-- if (filtered_nCS = '0') then -- Если микросхема выбрана +-- if (filtered_nOE = '0') then -- Если сигнал чтения активен +-- D <= (others => 'Z'); -- Запретить запись на шину +-- elsif (filtered_bWE = '1') then -- Если сигнал записи активен +-- case filtered_A is +-- when "00000000" => D <= (others => '0'); -- Адрес 0x00, запись нулей +-- when "00000001" => D <= (others => '1'); -- Адрес 0x01, запись единиц +-- when others => D <= (others => 'Z'); -- Для остальных адресов разрешить чтение +-- end case; +-- else +-- D <= (others => 'Z'); -- Запретить запись на шину +-- end if; +-- else +-- D <= (others => 'Z'); -- Запретить запись на шину +-- end if; +-- end process; process(clk) variable addr : integer range 0 to 511 := 0; - variable count : integer range 0 to 2 := 0; begin if rising_edge(clk) then case stateMM is @@ -38,46 +68,27 @@ begin if ce = '0' and cePrev = '1' then stateMM <= ReadingAddress; end if; - count := 0; data <= (others => 'Z'); - when ReadingAddress => - --if ce = '0' then - if count < 2 then - count := count + 1; - else - count := 0; - addr := conv_integer(address); - if oe = '0' then - stateMM <= ReadingData; - data <= (others => '0'); - else - stateMM <= WritingData; - end if; - end if; - --else - --stateMM <= Waiting; - --end if; + when ReadingAddress => + addr := conv_integer(address); + if oe = '0' then + stateMM <= ReadingData; + data <= (others => '0'); + elsif we = '0' then + stateMM <= WritingData; + elsif ce = '1' then + stateMM <= Waiting; + end if; when ReadingData => data <= memory(addr); - if oe = '1' and oePrev = '0' then + if ce = '1' then stateMM <= Waiting; - elsif ce = '1' then - stateMM <= Waiting; - end if; + end if; when WritingData => - if we = '0' and wePrev = '1' then - memory(addr) <= data; - stateMM <= Waiting; - elsif ce = '1' then - stateMM <= Waiting; - end if; + memory(addr) <= data; + stateMM <= Waiting; when others => - end case; - - oePrev <= oe; - cePrev <= ce; - wePrev <= we; - + end case; memory(0) <= x"AA"; memory(1) <= x"BB"; memory(2) <= x"CC"; diff --git a/MainController/RAM9X8_SerialBusMaster.bsf b/MainController/RAM9X8_SerialBusMaster.bsf new file mode 100644 index 0000000..f86a7c4 --- /dev/null +++ b/MainController/RAM9X8_SerialBusMaster.bsf @@ -0,0 +1,123 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 344 160) + (text "RAM9X8_SerialBusMaster" (rect 5 0 115 12)(font "Arial" )) + (text "inst" (rect 8 128 20 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "address[address_bus_width-1..0]" (rect 0 0 129 12)(font "Arial" )) + (text "address[address_bus_width-1..0]" (rect 21 43 150 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "we" (rect 0 0 10 12)(font "Arial" )) + (text "we" (rect 21 59 31 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "oe" (rect 0 0 9 12)(font "Arial" )) + (text "oe" (rect 21 75 30 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "ce" (rect 0 0 9 12)(font "Arial" )) + (text "ce" (rect 21 91 30 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "sbdatain" (rect 0 0 31 12)(font "Arial" )) + (text "sbdatain" (rect 21 107 52 119)(font "Arial" )) + (line (pt 0 112)(pt 16 112)(line_width 1)) + ) + (port + (pt 328 48) + (output) + (text "sbclk" (rect 0 0 20 12)(font "Arial" )) + (text "sbclk" (rect 287 43 307 55)(font "Arial" )) + (line (pt 328 48)(pt 312 48)(line_width 1)) + ) + (port + (pt 328 64) + (output) + (text "sbdataout" (rect 0 0 37 12)(font "Arial" )) + (text "sbdataout" (rect 270 59 307 71)(font "Arial" )) + (line (pt 328 64)(pt 312 64)(line_width 1)) + ) + (port + (pt 328 32) + (bidir) + (text "data[data_bus_width-1..0]" (rect 0 0 99 12)(font "Arial" )) + (text "data[data_bus_width-1..0]" (rect 208 27 307 39)(font "Arial" )) + (line (pt 328 32)(pt 312 32)(line_width 3)) + ) + (parameter + "REG_ADDR_DATA_UPPER_BYTE" + "0" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "REG_ADDR_DATA_LOWER_BYTE" + "1" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "REG_ADDR_CMD_UPPER_BYTE" + "2" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "REG_ADDR_CMD_LOWER_BYTE" + "3" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "DATA_BUS_WIDTH" + "8" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "ADDRESS_BUS_WIDTH" + "9" + "" + (type "PARAMETER_SIGNED_DEC") ) + (drawing + (rectangle (rect 16 16 312 128)(line_width 1)) + ) + (annotation_block (parameter)(rect 344 -64 444 16)) +) diff --git a/MainController/RAM9X8_SerialBusMaster.vhd b/MainController/RAM9X8_SerialBusMaster.vhd index 4316e8a..99e79ed 100644 --- a/MainController/RAM9X8_SerialBusMaster.vhd +++ b/MainController/RAM9X8_SerialBusMaster.vhd @@ -24,7 +24,7 @@ entity RAM9X8_SerialBusMaster is sbclk : out std_logic := '0'; sbdataout : out std_logic := '0'; - sbdatain : in std_logic; + sbdatain : in std_logic ); end entity; @@ -40,16 +40,16 @@ signal cePrev : std_logic := '0'; type MemoryMachine is (Waiting, Writing, Reading); signal stateMM : MemoryMachine := Waiting; -signal dataBufIn : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downro 0); -signal dataBufOut : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downro 0); -signal cmdBuf : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downro 0); +signal dataBufIn : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0); +signal dataBufOut : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0); +signal cmdBuf : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0); signal direction : std_logic := '0'; signal addressToTransmit : std_logic_vector(7 downto 0) := x"00"; signal dataToTransmit : std_logic_vector(15 downto 0) := x"0000"; signal dataFromDevices : std_logic_vector(15 downto 0) := x"0000"; -type CommunicationState_start is (Waiting, TransmiteAddress, TransmiteData, TransmiteCRC, TransmiteCheck, ReceiveData, ReceiveCRC, ReceiveCheck); +type CommunicationState_start is (Waiting, TransmitAddress, TransmitData, TransmitCRC, TransmitCheck, ReceiveData, ReceiveCRC, ReceiveCheck); signal CommunicationState : CommunicationState_start := Waiting ; signal resetCRC : std_logic := '1'; @@ -59,18 +59,20 @@ signal dataCRC : std_logic_vector(31 downto 0) := x"00000000"; signal readyCRC : std_logic := '0'; -- готовность контрольной суммы signal lineBusy : std_logic := '1'; +signal start : std_logic := '0'; +signal startPrev : std_logic := '0'; begin process(clk) - variable addr : integer range 0 to 2^ADDRESS_BUS_WIDTH := 0; + variable addr : integer range 0 to 511 := 0; begin if rising_edge(clk) then case stateMM is when Waiting => if ce = '0' and cePrev = '1' then addr := conv_integer(address); - if (addr == REG_ADDR_DATA_UPPER_BYTE or addr == REG_ADDR_DATA_LOWER_BYTE or addr == REG_ADDR_CMD_UPPER_BYTE or addr == REG_ADDR_CMD_LOWER_BYTE) then + if (addr = REG_ADDR_DATA_UPPER_BYTE or addr = REG_ADDR_DATA_LOWER_BYTE or addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE) then if oe = '0' then stateMM <= Reading; else @@ -171,14 +173,14 @@ begin end if; sbclk <= '0'; count := count + 1; - elsif count = countValue and state = '1' then + elsif count = countValue and state = 1 then latch := 1; count := 0; state := 0; - elsif count < countValue and state = '0' then + elsif count < countValue and state = 0 then sbclk <= '1'; count := count + 1; - elsif count = countValue and state = '0' then + elsif count = countValue and state = 0 then count := 0; state := 1; bitCnt := bitCnt - 1; @@ -200,7 +202,7 @@ begin sbclk <= '1'; count := count + 1; elsif count = countValue and state = 0 then - count := 0;; + count := 0; state := 1; bitCnt := bitCnt - 1; end if; @@ -209,7 +211,7 @@ begin if readyCRC = '1' then if bitCnt = -1 then CommunicationState <= TransmitCheck; - errors(1) <= '0'; + --errors(1) <= '0'; else if count < count and state = 1 then sbdataout <= CRC(bitCnt); @@ -229,8 +231,8 @@ begin end if; else CommunicationState <= Waiting; - errors(1) <= '1'; - countError1 <= countError1 + 1; + --errors(1) <= '1'; + --countError1 <= countError1 + 1; end if; when TransmitCheck => if count < countValue and state = 1 then @@ -240,18 +242,18 @@ begin count := 0; state := 0; if sbdatain = '0' then - countSuccessfulTransmite <= countSuccessfulTransmite + 1; - errors(0) <= '0'; + --countSuccessfulTransmite <= countSuccessfulTransmite + 1; + --errors(0) <= '0'; else - errors(0) <= '1'; - countError0 <= countError0 + 1; + --errors(0) <= '1'; + --countError0 <= countError0 + 1; end if; CommunicationState <= Waiting; end if; when ReceiveData => if bitCnt = -1 then CommunicationState <= ReceiveCRC; - bitCnt <= 3; + bitCnt := 3; else if count < countValue and state = 1 then sbclk <= '0'; @@ -263,7 +265,7 @@ begin elsif count < countValue and state = 0 then sbclk <= '1'; count := count + 1; - elsif count = countValue and state = '0' then + elsif count = countValue and state = 0 then count := 0; state := 1; bitCnt := bitCnt - 1; @@ -298,17 +300,17 @@ begin when ReceiveCheck => if readyCRC = '1' then if bufCRC = CRC then - countSuccessfulReceive <= countSuccessfulReceive + 1; + --countSuccessfulReceive <= countSuccessfulReceive + 1; dataBufOut <= dataFromDevices; - errors(3) <= '0'; + --errors(3) <= '0'; else - errors(3) <= '1'; - countError3 <= countError3 + 1; + --errors(3) <= '1'; + --countError3 <= countError3 + 1; end if; - errors(2) <= '0'; + --errors(2) <= '0'; else - errors(2) <= '1'; - countError2 <= countError2 + 1; + --errors(2) <= '1'; + --countError2 <= countError2 + 1; end if; CommunicationState <= Waiting; when others => @@ -349,7 +351,7 @@ begin bitCnt := bitCnt - 1; else readyCRC <= '1'; - countreadyCRC <= countreadyCRC + 1; + --countreadyCRC <= countreadyCRC + 1; end if; end if; end if;