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Исправили в соответствии с описанием адресного пространства блок ParallelBusMaster в части счетчика ошибок. Убрали из проекта библиотечные элементы фильтров, оставили один. Добавили синхронный блок инверсии сигналов для работы SerialBus. Настроили буферы на 96 ногой шине в соотвтествии с режимом работы NOT LOAD. Чтобы исправить назначение ног, предназначенных по умолчанию только для конфигурации, необходимо было в Assigments > Device > Device & Pin options > Dual Purpose Pins > двойным кликом на интересующих пинах выбрать regular I/O.

Browse Source 
Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 12 (Здесь у нас nSBclk);
Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 14 (LoadMode);
Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 23 (остается только для конфигурации);
Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 24 (остается только для конфигурации);
Info (169125): Pin ~ALTERA_nCEO~ is reserved at location 162 (ТК4);
This commit is contained in:
sokolovstanislav 2024-03-28 15:54:34 +03:00
parent 5370ab4575
commit 845f3fd223
12 changed files with 507 additions and 434 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
MainController/DigitalFilter16.vhd
View File

@ -1,48 +0,0 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DigitalFilter16 is
port(
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC
);
end DigitalFilter16;
architecture Behavioral of DigitalFilter16 is
signal count : natural range 0 to 15 := 0;
signal latch : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if input = '1' then
if latch = '0' then
latch <= '1';
count <= 0;
else
if count < 15 then
count <= count + 1;
else
output <= '1';
count <= 0;
end if;
end if;
else
if latch = '1' then
latch <= '0';
count <= 0;
else
if count < 15 then
count <= count + 1;
else
output <= '0';
count <= 0;
end if;
end if;
end if;
end if;
end process;
end Behavioral;

50
MainController/DigitalFilter2.bsf
View File

@ -1,50 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 160 96)
(text "DigitalFilter2" (rect 5 0 51 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 27 31 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "input" (rect 0 0 17 12)(font "Arial" ))
(text "input" (rect 21 43 38 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 32)
(output)
(text "output" (rect 0 0 23 12)(font "Arial" ))
(text "output" (rect 100 27 123 39)(font "Arial" ))
(line (pt 144 32)(pt 128 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 128 64)(line_width 1))
)
)

48
MainController/DigitalFilter2.vhd
View File

@ -1,48 +0,0 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DigitalFilter2 is
port(
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC
);
end DigitalFilter2;
architecture Behavioral of DigitalFilter2 is
signal count : natural range 0 to 1 := 0;
signal latch : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if input = '1' then
if latch = '0' then
latch <= '1';
count <= 0;
else
if count < 1 then
count <= count + 1;
else
output <= '1';
count <= 0;
end if;
end if;
else
if latch = '1' then
latch <= '0';
count <= 0;
else
if count < 1 then
count <= count + 1;
else
output <= '0';
count <= 0;
end if;
end if;
end if;
end if;
end process;
end Behavioral;

50
MainController/DigitalFilter3.bsf
View File

@ -1,50 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 160 96)
(text "DigitalFilter3" (rect 5 0 51 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 27 31 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "input" (rect 0 0 17 12)(font "Arial" ))
(text "input" (rect 21 43 38 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 32)
(output)
(text "output" (rect 0 0 23 12)(font "Arial" ))
(text "output" (rect 100 27 123 39)(font "Arial" ))
(line (pt 144 32)(pt 128 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 128 64)(line_width 1))
)
)

48
MainController/DigitalFilter3.vhd
View File

@ -1,48 +0,0 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DigitalFilter3 is
port(
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC
);
end DigitalFilter3;
architecture Behavioral of DigitalFilter3 is
signal count : natural range 0 to 3 := 0;
signal latch : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if input = '1' then
if latch = '0' then
latch <= '1';
count <= 0;
else
if count < 3 then
count <= count + 1;
else
output <= '1';
count <= 0;
end if;
end if;
else
if latch = '1' then
latch <= '0';
count <= 0;
else
if count < 3 then
count <= count + 1;
else
output <= '0';
count <= 0;
end if;
end if;
end if;
end if;
end process;
end Behavioral;

50
MainController/DigitalFilter8.bsf
View File

@ -1,50 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 160 96)
(text "DigitalFilter8" (rect 5 0 51 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 27 31 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "input" (rect 0 0 17 12)(font "Arial" ))
(text "input" (rect 21 43 38 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 32)
(output)
(text "output" (rect 0 0 23 12)(font "Arial" ))
(text "output" (rect 100 27 123 39)(font "Arial" ))
(line (pt 144 32)(pt 128 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 128 64)(line_width 1))
)
)

48
MainController/DigitalFilter8.vhd
View File

@ -1,48 +0,0 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DigitalFilter8 is
port(
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC
);
end DigitalFilter8;
architecture Behavioral of DigitalFilter8 is
signal count : natural range 0 to 7 := 0;
signal latch : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if input = '1' then
if latch = '0' then
latch <= '1';
count <= 0;
else
if count < 7 then
count <= count + 1;
else
output <= '1';
count <= 0;
end if;
end if;
else
if latch = '1' then
latch <= '0';
count <= 0;
else
if count < 7 then
count <= count + 1;
else
output <= '0';
count <= 0;
end if;
end if;
end if;
end if;
end process;
end Behavioral;

22
MainController/DigitalFilter16.bsf → MainController/DigitalInversion.bsf
View File

@ -20,9 +20,9 @@ applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 160 96)
(text "DigitalFilter16" (rect 5 0 54 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(rect 16 16 160 128)
(text "DigitalInversion" (rect 5 0 64 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
(port
(pt 0 32)
(input)
@ -37,6 +37,13 @@ applicable agreement for further details.
(text "input" (rect 21 43 38 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "ce" (rect 0 0 9 12)(font "Arial" ))
(text "ce" (rect 21 59 30 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 144 32)
(output)
@ -44,7 +51,14 @@ applicable agreement for further details.
(text "output" (rect 100 27 123 39)(font "Arial" ))
(line (pt 144 32)(pt 128 32)(line_width 1))
)
(port
(pt 144 48)
(output)
(text "noutput" (rect 0 0 28 12)(font "Arial" ))
(text "noutput" (rect 95 43 123 55)(font "Arial" ))
(line (pt 144 48)(pt 128 48)(line_width 1))
)
(drawing
(rectangle (rect 16 16 128 64)(line_width 1))
(rectangle (rect 16 16 128 96)(line_width 1))
)
)

36
MainController/DigitalInversion.vhd Normal file
View File

@ -0,0 +1,36 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DigitalInversion is
port(
clk : in STD_LOGIC;
input : in STD_LOGIC;
ce : in STD_LOGIC;
output : out STD_LOGIC;
noutput : out STD_LOGIC
);
end DigitalInversion;
architecture Behavioral of DigitalInversion is
begin
process(clk)
begin
if rising_edge(clk) then
if (ce = '1') then
if input = '1' then
output <= '1';
noutput <= '0';
else
output <= '0';
noutput <= '1';
end if;
else
output <= 'Z';
noutput <= 'Z';
end if;
end if;
end process;
end Behavioral;

500
MainController/MainController.bdf
View File

@ -34,7 +34,7 @@ applicable agreement for further details.
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 344 24 392 40))
(annotation_block (location)(rect 336 24 384 40))
)
(pin
(input)
@ -51,7 +51,7 @@ applicable agreement for further details.
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 320 264 376 280))
(annotation_block (location)(rect 312 264 368 280))
)
(pin
(input)
@ -68,7 +68,7 @@ applicable agreement for further details.
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 320 280 376 296))
(annotation_block (location)(rect 312 280 368 296))
)
(pin
(input)
@ -85,7 +85,7 @@ applicable agreement for further details.
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 320 248 376 264))
(annotation_block (location)(rect 312 248 368 264))
)
(pin
(input)
@ -102,7 +102,7 @@ applicable agreement for further details.
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 296 600 352 632))
(annotation_block (location)(rect 312 584 368 616))
)
(pin
(input)
@ -136,7 +136,7 @@ applicable agreement for further details.
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 328 664 376 680))
(annotation_block (location)(rect 320 664 368 680))
)
(pin
(input)
@ -153,7 +153,7 @@ applicable agreement for further details.
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 320 1000 368 1016))
(annotation_block (location)(rect 312 984 360 1000))
)
(pin
(output)
@ -170,7 +170,7 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 2016 24 2072 40))
(annotation_block (location)(rect 2024 24 2080 40))
)
(pin
(output)
@ -187,7 +187,7 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 2016 112 2072 128))
(annotation_block (location)(rect 2024 112 2080 128))
)
(pin
(output)
@ -204,41 +204,7 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 2016 128 2072 144))
)
(pin
(output)
(rect 1848 584 2024 600)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "SBclk" (rect 90 0 118 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 2024 584 2072 600))
)
(pin
(output)
(rect 1848 600 2024 616)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "SBdataout" (rect 90 0 140 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 2024 600 2072 616))
(annotation_block (location)(rect 2024 128 2080 144))
)
(pin
(output)
@ -272,7 +238,7 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 2024 904 2072 920))
(annotation_block (location)(rect 2032 904 2080 920))
)
(pin
(output)
@ -289,11 +255,11 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 2024 920 2072 936))
(annotation_block (location)(rect 2032 920 2080 936))
)
(pin
(output)
(rect 1840 40 2016 56)
(rect 1840 56 2016 72)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "DIRen" (rect 90 0 121 12)(font "Arial" ))
(pt 0 8)
@ -306,7 +272,143 @@ applicable agreement for further details.
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 2016 56 2064 72))
(annotation_block (location)(rect 2024 56 2072 72))
)
(pin
(output)
(rect 1840 -24 2016 -8)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "TKdir[3..0]" (rect 90 0 140 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
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(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 2024 -80 2080 -24))
)
(pin
(output)
(rect 1848 480 2024 496)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "nSBclk" (rect 90 0 124 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
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(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 2032 480 2080 496))
)
(pin
(output)
(rect 1848 464 2024 480)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "SBclk" (rect 90 0 118 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
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(line (pt 78 4)(pt 82 8))
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)
(annotation_block (location)(rect 2032 464 2080 480))
)
(pin
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(rect 1848 600 2024 616)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "nSBdataout" (rect 90 0 146 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 2032 600 2080 616))
)
(pin
(output)
(rect 1848 584 2024 600)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "SBdataout" (rect 90 0 140 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 2032 584 2080 600))
)
(pin
(output)
(rect 1840 -8 2016 8)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "DIR7" (rect 90 0 115 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
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(line (pt 82 8)(pt 78 12))
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)
(annotation_block (location)(rect 2024 -8 2072 8))
)
(pin
(output)
(rect 1840 40 2016 56)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "DIR9" (rect 90 0 115 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 2024 40 2072 56))
)
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(rect 1840 8 2016 24)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "DIR8" (rect 90 0 115 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
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(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 2024 8 2072 24))
)
(pin
(bidir)
@ -875,7 +977,7 @@ applicable agreement for further details.
(annotation_block (parameter)(rect 1024 696 1408 864))
)
(symbol
(rect 1728 72 1760 104)
(rect 1696 80 1728 112)
(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
(text "inst9" (rect 3 21 26 33)(font "Arial" )(invisible))
(port
@ -891,6 +993,137 @@ applicable agreement for further details.
(line (pt 8 8)(pt 24 8))
)
)
(symbol
(rect 1728 -136 1760 -120)
(text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6)))
(text "inst10" (rect 3 5 32 17)(font "Arial" )(invisible))
(port
(pt 16 16)
(output)
(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
(line (pt 16 16)(pt 16 8))
)
(drawing
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)
)
(symbol
(rect 1592 440 1736 552)
(text "DigitalInversion" (rect 5 0 81 12)(font "Arial" ))
(text "inst11" (rect 8 96 37 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
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(text "input" (rect 0 0 23 12)(font "Arial" ))
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)
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(pt 0 64)
(input)
(text "ce" (rect 0 0 11 12)(font "Arial" ))
(text "ce" (rect 21 59 32 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 144 32)
(output)
(text "output" (rect 0 0 30 12)(font "Arial" ))
(text "output" (rect 98 27 128 39)(font "Arial" ))
(line (pt 144 32)(pt 128 32))
)
(port
(pt 144 48)
(output)
(text "noutput" (rect 0 0 36 12)(font "Arial" ))
(text "noutput" (rect 93 43 129 55)(font "Arial" ))
(line (pt 144 48)(pt 128 48))
)
(drawing
(rectangle (rect 16 16 128 96))
)
)
(symbol
(rect 1592 560 1736 672)
(text "DigitalInversion" (rect 5 0 81 12)(font "Arial" ))
(text "inst12" (rect 8 96 37 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "input" (rect 0 0 23 12)(font "Arial" ))
(text "input" (rect 21 43 44 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "ce" (rect 0 0 11 12)(font "Arial" ))
(text "ce" (rect 21 59 32 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 144 32)
(output)
(text "output" (rect 0 0 30 12)(font "Arial" ))
(text "output" (rect 98 27 128 39)(font "Arial" ))
(line (pt 144 32)(pt 128 32))
)
(port
(pt 144 48)
(output)
(text "noutput" (rect 0 0 36 12)(font "Arial" ))
(text "noutput" (rect 93 43 129 55)(font "Arial" ))
(line (pt 144 48)(pt 128 48))
)
(drawing
(rectangle (rect 16 16 128 96))
)
)
(symbol
(rect 1552 408 1584 424)
(text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6)))
(text "inst13" (rect 3 5 32 17)(font "Arial" )(invisible))
(port
(pt 16 16)
(output)
(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
(line (pt 16 16)(pt 16 8))
)
(drawing
(line (pt 8 8)(pt 24 8))
)
)
(symbol
(rect 1696 -136 1728 -120)
(text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6)))
(text "inst14" (rect 3 5 32 17)(font "Arial" )(invisible))
(port
(pt 16 16)
(output)
(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
(line (pt 16 16)(pt 16 8))
)
(drawing
(line (pt 8 8)(pt 24 8))
)
)
(connector
(pt 560 32)
(pt 608 32)
@ -962,14 +1195,6 @@ applicable agreement for further details.
(pt 984 272)
(pt 984 304)
)
(connector
(pt 1368 592)
(pt 1848 592)
)
(connector
(pt 1368 608)
(pt 1848 608)
)
(connector
(pt 704 240)
(pt 680 240)
@ -1028,10 +1253,6 @@ applicable agreement for further details.
(pt 712 656)
(pt 608 656)
)
(connector
(pt 608 136)
(pt 608 576)
)
(connector
(pt 544 672)
(pt 712 672)
@ -1052,6 +1273,18 @@ applicable agreement for further details.
(pt 608 576)
(pt 608 656)
)
(connector
(pt 712 992)
(pt 536 992)
)
(connector
(pt 856 136)
(pt 936 136)
)
(connector
(pt 936 -16)
(pt 936 136)
)
(connector
(pt 1000 912)
(pt 1040 912)
@ -1073,10 +1306,36 @@ applicable agreement for further details.
(pt 608 896)
(pt 1040 896)
)
(connector
(pt 1848 912)
(pt 1368 912)
)
(connector
(pt 1848 928)
(pt 1368 928)
)
(connector
(pt 1848 944)
(pt 1368 944)
(bus)
)
(connector
(pt 1848 960)
(pt 1368 960)
(bus)
)
(connector
(pt 856 976)
(pt 1040 976)
)
(connector
(pt 608 656)
(pt 608 896)
)
(connector
(pt 608 896)
(pt 608 976)
)
(connector
(pt 1000 288)
(pt 1000 592)
@ -1112,50 +1371,122 @@ applicable agreement for further details.
(pt 952 960)
)
(connector
(pt 608 656)
(pt 608 896)
(pt 1368 608)
(pt 1592 608)
)
(connector
(pt 608 896)
(pt 608 976)
(pt 1592 504)
(pt 1568 504)
)
(connector
(pt 712 992)
(pt 536 992)
(pt 1592 624)
(pt 1568 624)
)
(connector
(pt 1368 912)
(pt 1848 912)
(pt 1568 424)
(pt 1568 504)
)
(connector
(pt 1368 928)
(pt 1848 928)
(pt 1568 504)
(pt 1568 624)
)
(connector
(pt 1368 944)
(pt 1848 944)
(pt 1592 592)
(pt 1544 592)
)
(connector
(pt 1592 472)
(pt 1544 472)
)
(connector
(pt 1544 408)
(pt 1544 472)
)
(connector
(pt 1544 472)
(pt 1544 592)
)
(connector
(pt 608 408)
(pt 1544 408)
)
(connector
(pt 608 136)
(pt 608 408)
)
(connector
(pt 608 408)
(pt 608 576)
)
(connector
(pt 1592 488)
(pt 1520 488)
)
(connector
(pt 1368 592)
(pt 1520 592)
)
(connector
(pt 1520 592)
(pt 1520 488)
)
(connector
(pt 1736 592)
(pt 1848 592)
)
(connector
(pt 1736 608)
(pt 1848 608)
)
(connector
(pt 1736 472)
(pt 1848 472)
)
(connector
(pt 1736 488)
(pt 1848 488)
)
(connector
(pt 1744 -16)
(pt 1840 -16)
(bus)
)
(connector
(pt 1368 960)
(pt 1848 960)
(pt 1744 -120)
(pt 1744 -16)
(bus)
)
(connector
(pt 856 136)
(pt 936 136)
(pt 1712 0)
(pt 1840 0)
)
(connector
(pt 936 -16)
(pt 936 136)
(pt 1840 16)
(pt 1712 16)
)
(connector
(pt 1712 -120)
(pt 1712 0)
)
(connector
(pt 1712 0)
(pt 1712 16)
)
(connector
(pt 1840 48)
(pt 1744 48)
(pt 1712 48)
)
(connector
(pt 1744 48)
(pt 1744 72)
(pt 1712 64)
(pt 1840 64)
)
(connector
(pt 1712 48)
(pt 1712 64)
)
(connector
(pt 1712 64)
(pt 1712 80)
)
(junction (pt 608 32))
(junction (pt 1000 288))
@ -1170,3 +1501,8 @@ applicable agreement for further details.
(junction (pt 968 624))
(junction (pt 952 640))
(junction (pt 608 896))
(junction (pt 1568 504))
(junction (pt 1544 472))
(junction (pt 608 408))
(junction (pt 1712 0))
(junction (pt 1712 64))

32
MainController/MainController.qsf
View File

@ -46,7 +46,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name BDF_FILE MainController.bdf
@ -168,4 +167,35 @@ set_location_assignment PIN_98 -to DIRen
set_location_assignment PIN_95 -to PBdir[1]
set_location_assignment PIN_72 -to PBdir[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DIRen
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TKdir[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TKdir[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TKdir[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TKdir[0]
set_location_assignment PIN_126 -to TKdir[3]
set_location_assignment PIN_110 -to TKdir[2]
set_location_assignment PIN_148 -to TKdir[1]
set_location_assignment PIN_127 -to TKdir[0]
set_global_assignment -name VHDL_FILE DigitalInversion.vhd
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nSBclk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nSBdataout
set_location_assignment PIN_14 -to nSBclk
set_location_assignment PIN_21 -to nSBdataout
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DIR7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DIR8
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DIR9
set_location_assignment PIN_55 -to DIR9
set_location_assignment PIN_57 -to DIR7
set_location_assignment PIN_71 -to DIR8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

9
MainController/RAM9X8_ParallelBusMaster.vhd
View File

@ -45,11 +45,10 @@ signal memoryData : mem;
signal firstFreeBuf : std_logic_vector(15 downto 0) := (others => '0');
signal cmdBuf : std_logic_vector(15 downto 0) := (others => '0');
signal fasBuf : std_logic_vector(15 downto 0) := (others => '0');
signal controlBuf : std_logic_vector(15 downto 0) := (others => '0');
signal updatedAddress : std_logic_vector(7 downto 0) := (others => '0');
signal controlBuf : std_logic_vector(7 downto 0) := (others => '0');
signal errorBuf : std_logic_vector(7 downto 0) := x"00";
signal addrTemp : std_logic_vector(7 downto 0) := x"00";
signal dataTemp : std_logic_vector(15 downto 0) := x"0000";
@ -113,7 +112,7 @@ begin
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;
elsif (addr >= firstFreeBuf and addr <= firstFreeBuf + cmdBuf(7 downto 0)) then
elsif (addr >= conv_integer(firstFreeBuf) and addr <= conv_integer(firstFreeBuf) + conv_integer(cmdBuf(7 downto 0))) then
if (oe = '0') then -- Если сигнал чтения активен
data <= memoryData(addr - conv_integer(firstFreeBuf));
else
@ -206,12 +205,12 @@ begin
if pbdata = not dataTemp then
memoryData(position) <= dataTemp(15 downto 8);
memoryData(position + 1) <= dataTemp(7 downto 0);
controlBuf <= memoryAddress(position);
CommunicationState <= Timeout;
count := 0;
pbce <= '1';
countValue := 5;
if position + 1 < conv_integer(cmdBuf(7 downto 0)) then
updatedAddress <= conv_std_logic_vector(position, 8);
position := position + 2;
else
position := 0;