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Начали тестирование последовательной шины. S_RES (ножка 30С управляется из сервисного регистра SRV_LEDS(14)). Синхросигнал инвертирован в SB. Данные от периферийных устройств неверно заходили в фильтр (исправлено). ПО проходит тесты, пока не работает.

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sokolovstanislav 2024-06-07 10:50:55 +03:00
parent f72d466925
commit 6b28fad4b1
21 changed files with 2524 additions and 1350 deletions
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1912062031_XILINX-XC6SLX9-2TQG144I_C415799.pdf Normal file
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MainController/MainController.bdf
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@ -0,0 +1,337 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 240 592)
(text "MainController" (rect 5 0 85 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 560 25 572)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "HWPdatain[1..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "HWPdatain[1..0]" (rect 21 27 110 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "Error0In" (rect 0 0 44 14)(font "Arial" (font_size 8)))
(text "Error0In" (rect 21 43 65 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "FPGA_CLK" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "FPGA_CLK" (rect 21 59 84 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "nCE" (rect 0 0 22 14)(font "Arial" (font_size 8)))
(text "nCE" (rect 21 75 43 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "nOE" (rect 0 0 23 14)(font "Arial" (font_size 8)))
(text "nOE" (rect 21 91 44 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 0 112)
(input)
(text "nWE" (rect 0 0 25 14)(font "Arial" (font_size 8)))
(text "nWE" (rect 21 107 46 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112))
)
(port
(pt 0 128)
(input)
(text "Address[8..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "Address[8..0]" (rect 21 123 98 137)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128)(line_width 3))
)
(port
(pt 0 144)
(input)
(text "nBL[1..0]" (rect 0 0 50 14)(font "Arial" (font_size 8)))
(text "nBL[1..0]" (rect 21 139 71 153)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144)(line_width 3))
)
(port
(pt 0 160)
(input)
(text "SBdatain" (rect 0 0 50 14)(font "Arial" (font_size 8)))
(text "SBdatain" (rect 21 155 71 169)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 16 160))
)
(port
(pt 0 176)
(input)
(text "PBack" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "PBack" (rect 21 171 56 185)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 16 176))
)
(port
(pt 0 192)
(input)
(text "PWM[5..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
(text "PWM[5..0]" (rect 21 187 77 201)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 16 192)(line_width 3))
)
(port
(pt 224 32)
(output)
(text "FPGA_LED_1" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "FPGA_LED_1" (rect 127 27 203 41)(font "Arial" (font_size 8)))
(line (pt 224 32)(pt 208 32))
)
(port
(pt 224 48)
(output)
(text "AddrDevice_2" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "AddrDevice_2" (rect 122 43 203 57)(font "Arial" (font_size 8)))
(line (pt 224 48)(pt 208 48))
)
(port
(pt 224 64)
(output)
(text "AddrDevice_1" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "AddrDevice_1" (rect 122 59 203 73)(font "Arial" (font_size 8)))
(line (pt 224 64)(pt 208 64))
)
(port
(pt 224 80)
(output)
(text "HWPDATA" (rect 0 0 61 14)(font "Arial" (font_size 8)))
(text "HWPDATA" (rect 142 75 203 89)(font "Arial" (font_size 8)))
(line (pt 224 80)(pt 208 80))
)
(port
(pt 224 96)
(output)
(text "HWPCLK" (rect 0 0 50 14)(font "Arial" (font_size 8)))
(text "HWPCLK" (rect 153 91 203 105)(font "Arial" (font_size 8)))
(line (pt 224 96)(pt 208 96))
)
(port
(pt 224 112)
(output)
(text "RW" (rect 0 0 20 14)(font "Arial" (font_size 8)))
(text "RW" (rect 183 107 203 121)(font "Arial" (font_size 8)))
(line (pt 224 112)(pt 208 112))
)
(port
(pt 224 128)
(output)
(text "Reset" (rect 0 0 33 14)(font "Arial" (font_size 8)))
(text "Reset" (rect 170 123 203 137)(font "Arial" (font_size 8)))
(line (pt 224 128)(pt 208 128))
)
(port
(pt 224 144)
(output)
(text "Error0Out" (rect 0 0 55 14)(font "Arial" (font_size 8)))
(text "Error0Out" (rect 148 139 203 153)(font "Arial" (font_size 8)))
(line (pt 224 144)(pt 208 144))
)
(port
(pt 224 160)
(output)
(text "LoadMode" (rect 0 0 59 14)(font "Arial" (font_size 8)))
(text "LoadMode" (rect 144 155 203 169)(font "Arial" (font_size 8)))
(line (pt 224 160)(pt 208 160))
)
(port
(pt 224 176)
(output)
(text "TKdir[3..0]" (rect 0 0 57 14)(font "Arial" (font_size 8)))
(text "TKdir[3..0]" (rect 146 171 203 185)(font "Arial" (font_size 8)))
(line (pt 224 176)(pt 208 176)(line_width 3))
)
(port
(pt 224 192)
(output)
(text "DIR7" (rect 0 0 25 14)(font "Arial" (font_size 8)))
(text "DIR7" (rect 178 187 203 201)(font "Arial" (font_size 8)))
(line (pt 224 192)(pt 208 192))
)
(port
(pt 224 208)
(output)
(text "DIR8" (rect 0 0 25 14)(font "Arial" (font_size 8)))
(text "DIR8" (rect 178 203 203 217)(font "Arial" (font_size 8)))
(line (pt 224 208)(pt 208 208))
)
(port
(pt 224 224)
(output)
(text "DIR9" (rect 0 0 25 14)(font "Arial" (font_size 8)))
(text "DIR9" (rect 178 219 203 233)(font "Arial" (font_size 8)))
(line (pt 224 224)(pt 208 224))
)
(port
(pt 224 240)
(output)
(text "DIRen" (rect 0 0 33 14)(font "Arial" (font_size 8)))
(text "DIRen" (rect 170 235 203 249)(font "Arial" (font_size 8)))
(line (pt 224 240)(pt 208 240))
)
(port
(pt 224 256)
(output)
(text "AsyncLine" (rect 0 0 61 14)(font "Arial" (font_size 8)))
(text "AsyncLine" (rect 142 251 203 265)(font "Arial" (font_size 8)))
(line (pt 224 256)(pt 208 256))
)
(port
(pt 224 272)
(output)
(text "DivClk" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "DivClk" (rect 169 267 203 281)(font "Arial" (font_size 8)))
(line (pt 224 272)(pt 208 272))
)
(port
(pt 224 288)
(output)
(text "SBclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "SBclk" (rect 172 283 203 297)(font "Arial" (font_size 8)))
(line (pt 224 288)(pt 208 288))
)
(port
(pt 224 304)
(output)
(text "nSBclk" (rect 0 0 38 14)(font "Arial" (font_size 8)))
(text "nSBclk" (rect 165 299 203 313)(font "Arial" (font_size 8)))
(line (pt 224 304)(pt 208 304))
)
(port
(pt 224 320)
(output)
(text "SBdataout" (rect 0 0 59 14)(font "Arial" (font_size 8)))
(text "SBdataout" (rect 144 315 203 329)(font "Arial" (font_size 8)))
(line (pt 224 320)(pt 208 320))
)
(port
(pt 224 336)
(output)
(text "nSBdataout" (rect 0 0 66 14)(font "Arial" (font_size 8)))
(text "nSBdataout" (rect 137 331 203 345)(font "Arial" (font_size 8)))
(line (pt 224 336)(pt 208 336))
)
(port
(pt 224 352)
(output)
(text "PBclk" (rect 0 0 30 14)(font "Arial" (font_size 8)))
(text "PBclk" (rect 173 347 203 361)(font "Arial" (font_size 8)))
(line (pt 224 352)(pt 208 352))
)
(port
(pt 224 368)
(output)
(text "PBce" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "PBce" (rect 174 363 203 377)(font "Arial" (font_size 8)))
(line (pt 224 368)(pt 208 368))
)
(port
(pt 224 384)
(output)
(text "PBdir[1..0]" (rect 0 0 57 14)(font "Arial" (font_size 8)))
(text "PBdir[1..0]" (rect 146 379 203 393)(font "Arial" (font_size 8)))
(line (pt 224 384)(pt 208 384)(line_width 3))
)
(port
(pt 224 416)
(output)
(text "TK[31..0]" (rect 0 0 50 14)(font "Arial" (font_size 8)))
(text "TK[31..0]" (rect 153 411 203 425)(font "Arial" (font_size 8)))
(line (pt 224 416)(pt 208 416)(line_width 3))
)
(port
(pt 224 432)
(output)
(text "Interrupt" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "Interrupt" (rect 156 427 203 441)(font "Arial" (font_size 8)))
(line (pt 224 432)(pt 208 432))
)
(port
(pt 224 448)
(output)
(text "OBclk" (rect 0 0 33 14)(font "Arial" (font_size 8)))
(text "OBclk" (rect 170 443 203 457)(font "Arial" (font_size 8)))
(line (pt 224 448)(pt 208 448))
)
(port
(pt 224 464)
(output)
(text "OBdata" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "OBdata" (rect 161 459 203 473)(font "Arial" (font_size 8)))
(line (pt 224 464)(pt 208 464))
)
(port
(pt 224 496)
(output)
(text "FPGA_LED_2" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "FPGA_LED_2" (rect 127 491 203 505)(font "Arial" (font_size 8)))
(line (pt 224 496)(pt 208 496))
)
(port
(pt 224 512)
(output)
(text "FPGA_LED_3" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "FPGA_LED_3" (rect 127 507 203 521)(font "Arial" (font_size 8)))
(line (pt 224 512)(pt 208 512))
)
(port
(pt 224 528)
(output)
(text "FPGA_LED_4" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "FPGA_LED_4" (rect 127 523 203 537)(font "Arial" (font_size 8)))
(line (pt 224 528)(pt 208 528))
)
(port
(pt 224 544)
(output)
(text "FPGA_LED_5" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "FPGA_LED_5" (rect 127 539 203 553)(font "Arial" (font_size 8)))
(line (pt 224 544)(pt 208 544))
)
(port
(pt 224 400)
(bidir)
(text "PBdata[15..0]" (rect 0 0 75 14)(font "Arial" (font_size 8)))
(text "PBdata[15..0]" (rect 128 395 203 409)(font "Arial" (font_size 8)))
(line (pt 224 400)(pt 208 400)(line_width 3))
)
(port
(pt 224 480)
(bidir)
(text "Data[7..0]" (rect 0 0 54 14)(font "Arial" (font_size 8)))
(text "Data[7..0]" (rect 149 475 203 489)(font "Arial" (font_size 8)))
(line (pt 224 480)(pt 208 480)(line_width 3))
)
(drawing
(rectangle (rect 16 16 208 560))
)
)

4
MainController/MainController.qsf
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@ -318,4 +318,8 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_LED_4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_LED_5 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_LED_5
set_location_assignment PIN_169 -to FPGA_LED_4 set_location_assignment PIN_169 -to FPGA_LED_4
set_location_assignment PIN_171 -to FPGA_LED_5 set_location_assignment PIN_171 -to FPGA_LED_5
set_global_assignment -name VHDL_FILE RAM9X8_Peripheral.vhd
set_global_assignment -name VHDL_FILE RAM9X8_Service.vhd
set_location_assignment PIN_43 -to S_RES
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to S_RES
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

16
MainController/RAM9X8_HWPBusMaster.bsf
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@ -87,42 +87,42 @@ applicable agreement for further details.
(line (pt 328 32)(pt 312 32)(line_width 3)) (line (pt 328 32)(pt 312 32)(line_width 3))
) )
(parameter (parameter
"REG_ADDR_CMD_2_LOWER_BYTE" "HWP_CMD_2_LOWER"
"46" "46"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CMD_2_UPPER_BYTE" "HWP_CMD_2_UPPER"
"47" "47"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CMD_1_LOWER_BYTE" "HWP_CMD_1_LOWER"
"48" "48"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CMD_1_UPPER_BYTE" "HWP_CMD_1_UPPER"
"49" "49"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_DATA_2_LOWER_BYTE" "HWP_DATA_2_LOWER"
"50" "50"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_DATA_2_UPPER_BYTE" "HWP_DATA_2_UPPER"
"51" "51"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_DATA_1_LOWER_BYTE" "HWP_DATA_1_LOWER"
"52" "52"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_DATA_1_UPPER_BYTE" "HWP_DATA_1_UPPER"
"53" "53"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )

52
MainController/RAM9X8_HWPBusMaster.vhd
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@ -5,14 +5,14 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8_HWPBusMaster is entity RAM9X8_HWPBusMaster is
generic( generic(
REG_ADDR_CMD_2_LOWER_BYTE : integer := 46; HWP_CMD_2_LOWER : integer := 46;
REG_ADDR_CMD_2_UPPER_BYTE : integer := 47; HWP_CMD_2_UPPER : integer := 47;
REG_ADDR_CMD_1_LOWER_BYTE : integer := 48; HWP_CMD_1_LOWER : integer := 48;
REG_ADDR_CMD_1_UPPER_BYTE : integer := 49; HWP_CMD_1_UPPER : integer := 49;
REG_ADDR_DATA_2_LOWER_BYTE : integer := 50; HWP_DATA_2_LOWER : integer := 50;
REG_ADDR_DATA_2_UPPER_BYTE : integer := 51; HWP_DATA_2_UPPER : integer := 51;
REG_ADDR_DATA_1_LOWER_BYTE : integer := 52; HWP_DATA_1_LOWER : integer := 52;
REG_ADDR_DATA_1_UPPER_BYTE : integer := 53; HWP_DATA_1_UPPER : integer := 53;
DATA_BUS_WIDTH : integer := 8; DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9 ADDRESS_BUS_WIDTH : integer := 9
@ -52,26 +52,26 @@ begin
begin begin
if (ce = '0') then -- Если микросхема выбрана if (ce = '0') then -- Если микросхема выбрана
addr := conv_integer(address); addr := conv_integer(address);
if (addr = REG_ADDR_CMD_2_UPPER_BYTE or addr = REG_ADDR_CMD_2_LOWER_BYTE or addr = REG_ADDR_CMD_1_UPPER_BYTE or addr = REG_ADDR_CMD_1_LOWER_BYTE if (addr = HWP_CMD_2_UPPER or addr = HWP_CMD_2_LOWER or addr = HWP_CMD_1_UPPER or addr = HWP_CMD_1_LOWER
or addr = REG_ADDR_DATA_2_UPPER_BYTE or addr = REG_ADDR_DATA_2_LOWER_BYTE or addr = REG_ADDR_DATA_1_UPPER_BYTE or addr = REG_ADDR_DATA_1_LOWER_BYTE) then or addr = HWP_DATA_2_UPPER or addr = HWP_DATA_2_LOWER or addr = HWP_DATA_1_UPPER or addr = HWP_DATA_1_LOWER) then
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
case addr is case addr is
when REG_ADDR_CMD_2_UPPER_BYTE => when HWP_CMD_2_UPPER =>
data <= cmdBuf(31 downto 24); data <= cmdBuf(31 downto 24);
when REG_ADDR_CMD_2_LOWER_BYTE => when HWP_CMD_2_LOWER =>
data <= cmdBuf(23 downto 16); data <= cmdBuf(23 downto 16);
when REG_ADDR_CMD_1_UPPER_BYTE => when HWP_CMD_1_UPPER =>
data <= cmdBuf(15 downto 8); data <= cmdBuf(15 downto 8);
when REG_ADDR_CMD_1_LOWER_BYTE => when HWP_CMD_1_LOWER =>
data(7 downto 1) <= cmdBuf(7 downto 1); data(7 downto 1) <= cmdBuf(7 downto 1);
data(0) <= done; data(0) <= done;
when REG_ADDR_DATA_2_UPPER_BYTE => when HWP_DATA_2_UPPER =>
data <= tempBuf(29 downto 22); data <= tempBuf(29 downto 22);
when REG_ADDR_DATA_2_LOWER_BYTE => when HWP_DATA_2_LOWER =>
data <= tempBuf(21 downto 14); data <= tempBuf(21 downto 14);
when REG_ADDR_DATA_1_UPPER_BYTE => when HWP_DATA_1_UPPER =>
data <= tempBuf(13 downto 6); data <= tempBuf(13 downto 6);
when REG_ADDR_DATA_1_LOWER_BYTE => when HWP_DATA_1_LOWER =>
data(7 downto 2) <= tempBuf(5 downto 0); data(7 downto 2) <= tempBuf(5 downto 0);
data(1 downto 0) <= (others => '0'); data(1 downto 0) <= (others => '0');
when others => when others =>
@ -79,21 +79,21 @@ begin
end case; end case;
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
case addr is case addr is
when REG_ADDR_CMD_2_UPPER_BYTE => when HWP_CMD_2_UPPER =>
cmdBuf(31 downto 24) <= data; cmdBuf(31 downto 24) <= data;
when REG_ADDR_CMD_2_LOWER_BYTE => when HWP_CMD_2_LOWER =>
cmdBuf(23 downto 16) <= data; cmdBuf(23 downto 16) <= data;
when REG_ADDR_CMD_1_UPPER_BYTE => when HWP_CMD_1_UPPER =>
cmdBuf(15 downto 8) <= data; cmdBuf(15 downto 8) <= data;
when REG_ADDR_CMD_1_LOWER_BYTE => when HWP_CMD_1_LOWER =>
cmdBuf(7 downto 0) <= data; cmdBuf(7 downto 0) <= data;
when REG_ADDR_DATA_2_UPPER_BYTE => when HWP_DATA_2_UPPER =>
dataBuf(31 downto 24) <= data; dataBuf(31 downto 24) <= data;
when REG_ADDR_DATA_2_LOWER_BYTE => when HWP_DATA_2_LOWER =>
dataBuf(23 downto 16) <= data; dataBuf(23 downto 16) <= data;
when REG_ADDR_DATA_1_UPPER_BYTE => when HWP_DATA_1_UPPER =>
dataBuf(15 downto 8) <= data; dataBuf(15 downto 8) <= data;
when REG_ADDR_DATA_1_LOWER_BYTE => when HWP_DATA_1_LOWER =>
dataBuf(7 downto 0) <= data; dataBuf(7 downto 0) <= data;
when others => when others =>
data <= (others => 'Z'); -- Запретить запись на шину data <= (others => 'Z'); -- Запретить запись на шину

4
MainController/RAM9X8_Loader.bsf
View File

@ -143,12 +143,12 @@ applicable agreement for further details.
(line (pt 328 32)(pt 312 32)(line_width 3)) (line (pt 328 32)(pt 312 32)(line_width 3))
) )
(parameter (parameter
"REG_ADDR_LOADER_LOWER_BYTE" "LD_LOADER_LOWER"
"44" "44"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_LOADER_UPPER_BYTE" "LD_LOADER_UPPER"
"45" "45"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )

14
MainController/RAM9X8_Loader.vhd
View File

@ -5,8 +5,8 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8_Loader is entity RAM9X8_Loader is
generic( generic(
REG_ADDR_LOADER_LOWER_BYTE : integer := 44; LD_LOADER_LOWER : integer := 44;
REG_ADDR_LOADER_UPPER_BYTE : integer := 45; LD_LOADER_UPPER : integer := 45;
DATA_BUS_WIDTH : integer := 8; DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9 ADDRESS_BUS_WIDTH : integer := 9
@ -48,22 +48,22 @@ begin
begin begin
if (ce = '0') then -- Если микросхема выбрана if (ce = '0') then -- Если микросхема выбрана
addr := conv_integer(address); addr := conv_integer(address);
if (addr = REG_ADDR_LOADER_UPPER_BYTE or addr = REG_ADDR_LOADER_LOWER_BYTE) then if (addr = LD_LOADER_UPPER or addr = LD_LOADER_LOWER) then
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
case addr is case addr is
when REG_ADDR_LOADER_UPPER_BYTE => when LD_LOADER_UPPER =>
data(7) <= dataInLoader; data(7) <= dataInLoader;
data(6 downto 0) <= loaderBuf(14 downto 8); data(6 downto 0) <= loaderBuf(14 downto 8);
when REG_ADDR_LOADER_LOWER_BYTE => when LD_LOADER_LOWER =>
data <= loaderBuf(7 downto 0); data <= loaderBuf(7 downto 0);
when others => when others =>
data <= (others => 'Z'); -- Запретить запись на шину data <= (others => 'Z'); -- Запретить запись на шину
end case; end case;
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
case addr is case addr is
when REG_ADDR_LOADER_UPPER_BYTE => when LD_LOADER_UPPER =>
loaderBuf(15 downto 8) <= data; loaderBuf(15 downto 8) <= data;
when REG_ADDR_LOADER_LOWER_BYTE => when LD_LOADER_LOWER =>
loaderBuf(7 downto 0) <= data; loaderBuf(7 downto 0) <= data;
when others => when others =>
data <= (others => 'Z'); -- Запретить запись на шину data <= (others => 'Z'); -- Запретить запись на шину

36
MainController/RAM9X8_OpticalBusMaster.bsf
View File

@ -80,92 +80,92 @@ applicable agreement for further details.
(line (pt 328 32)(pt 312 32)(line_width 3)) (line (pt 328 32)(pt 312 32)(line_width 3))
) )
(parameter (parameter
"REG_ADDR_CMD_LOWER_BYTE" "OB_CMD_LOWER"
"54" "54"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CMD_UPPER_BYTE" "OB_CMD_UPPER"
"55" "55"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_8_LOWER_BYTE" "OB_WORD_8_LOWER"
"56" "56"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_8_UPPER_BYTE" "OB_WORD_8_UPPER"
"57" "57"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_7_LOWER_BYTE" "OB_WORD_7_LOWER"
"58" "58"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_7_UPPER_BYTE" "OB_WORD_7_UPPER"
"59" "59"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_6_LOWER_BYTE" "OB_WORD_6_LOWER"
"60" "60"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_6_UPPER_BYTE" "OB_WORD_6_UPPER"
"61" "61"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_5_LOWER_BYTE" "OB_WORD_5_LOWER"
"62" "62"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_5_UPPER_BYTE" "OB_WORD_5_UPPER"
"63" "63"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_4_LOWER_BYTE" "OB_WORD_4_LOWER"
"64" "64"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_4_UPPER_BYTE" "OB_WORD_4_UPPER"
"65" "65"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_3_LOWER_BYTE" "OB_WORD_3_LOWER"
"66" "66"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_3_UPPER_BYTE" "OB_WORD_3_UPPER"
"67" "67"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_2_LOWER_BYTE" "OB_WORD_2_LOWER"
"68" "68"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_2_UPPER_BYTE" "OB_WORD_2_UPPER"
"69" "69"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_1_LOWER_BYTE" "OB_WORD_1_LOWER"
"70" "70"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_WORD_1_UPPER_BYTE" "OB_WORD_1_UPPER"
"71" "71"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )

128
MainController/RAM9X8_OpticalBusMaster.vhd
View File

@ -5,24 +5,24 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8_OpticalBusMaster is entity RAM9X8_OpticalBusMaster is
generic( generic(
REG_ADDR_CMD_LOWER_BYTE : integer := 54; OB_CMD_LOWER : integer := 54;
REG_ADDR_CMD_UPPER_BYTE : integer := 55; OB_CMD_UPPER : integer := 55;
REG_ADDR_WORD_8_LOWER_BYTE : integer := 56; OB_WORD_8_LOWER : integer := 56;
REG_ADDR_WORD_8_UPPER_BYTE : integer := 57; OB_WORD_8_UPPER : integer := 57;
REG_ADDR_WORD_7_LOWER_BYTE : integer := 58; OB_WORD_7_LOWER : integer := 58;
REG_ADDR_WORD_7_UPPER_BYTE : integer := 59; OB_WORD_7_UPPER : integer := 59;
REG_ADDR_WORD_6_LOWER_BYTE : integer := 60; OB_WORD_6_LOWER : integer := 60;
REG_ADDR_WORD_6_UPPER_BYTE : integer := 61; OB_WORD_6_UPPER : integer := 61;
REG_ADDR_WORD_5_LOWER_BYTE : integer := 62; OB_WORD_5_LOWER : integer := 62;
REG_ADDR_WORD_5_UPPER_BYTE : integer := 63; OB_WORD_5_UPPER : integer := 63;
REG_ADDR_WORD_4_LOWER_BYTE : integer := 64; OB_WORD_4_LOWER : integer := 64;
REG_ADDR_WORD_4_UPPER_BYTE : integer := 65; OB_WORD_4_UPPER : integer := 65;
REG_ADDR_WORD_3_LOWER_BYTE : integer := 66; OB_WORD_3_LOWER : integer := 66;
REG_ADDR_WORD_3_UPPER_BYTE : integer := 67; OB_WORD_3_UPPER : integer := 67;
REG_ADDR_WORD_2_LOWER_BYTE : integer := 68; OB_WORD_2_LOWER : integer := 68;
REG_ADDR_WORD_2_UPPER_BYTE : integer := 69; OB_WORD_2_UPPER : integer := 69;
REG_ADDR_WORD_1_LOWER_BYTE : integer := 70; OB_WORD_1_LOWER : integer := 70;
REG_ADDR_WORD_1_UPPER_BYTE : integer := 71; OB_WORD_1_UPPER : integer := 71;
DATA_BUS_WIDTH : integer := 8; DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9 ADDRESS_BUS_WIDTH : integer := 9
@ -68,98 +68,98 @@ begin
begin begin
if (ce = '0') then -- Если микросхема выбрана if (ce = '0') then -- Если микросхема выбрана
addr := conv_integer(address); addr := conv_integer(address);
if (addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE if (addr = OB_CMD_UPPER or addr = OB_CMD_LOWER
or addr = REG_ADDR_WORD_8_UPPER_BYTE or addr = REG_ADDR_WORD_8_LOWER_BYTE or addr = OB_WORD_8_UPPER or addr = OB_WORD_8_LOWER
or addr = REG_ADDR_WORD_7_UPPER_BYTE or addr = REG_ADDR_WORD_7_LOWER_BYTE or addr = OB_WORD_7_UPPER or addr = OB_WORD_7_LOWER
or addr = REG_ADDR_WORD_6_UPPER_BYTE or addr = REG_ADDR_WORD_6_LOWER_BYTE or addr = OB_WORD_6_UPPER or addr = OB_WORD_6_LOWER
or addr = REG_ADDR_WORD_5_UPPER_BYTE or addr = REG_ADDR_WORD_5_LOWER_BYTE or addr = OB_WORD_5_UPPER or addr = OB_WORD_5_LOWER
or addr = REG_ADDR_WORD_4_UPPER_BYTE or addr = REG_ADDR_WORD_4_LOWER_BYTE or addr = OB_WORD_4_UPPER or addr = OB_WORD_4_LOWER
or addr = REG_ADDR_WORD_3_UPPER_BYTE or addr = REG_ADDR_WORD_3_LOWER_BYTE or addr = OB_WORD_3_UPPER or addr = OB_WORD_3_LOWER
or addr = REG_ADDR_WORD_2_UPPER_BYTE or addr = REG_ADDR_WORD_2_LOWER_BYTE or addr = OB_WORD_2_UPPER or addr = OB_WORD_2_LOWER
or addr = REG_ADDR_WORD_1_UPPER_BYTE or addr = REG_ADDR_WORD_1_LOWER_BYTE) then or addr = OB_WORD_1_UPPER or addr = OB_WORD_1_LOWER) then
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
case addr is case addr is
when REG_ADDR_CMD_UPPER_BYTE => when OB_CMD_UPPER =>
data <= cmdBuf(15 downto 8); data <= cmdBuf(15 downto 8);
when REG_ADDR_CMD_LOWER_BYTE => when OB_CMD_LOWER =>
data <= cmdBuf(7 downto 0); data <= cmdBuf(7 downto 0);
when REG_ADDR_WORD_8_UPPER_BYTE => when OB_WORD_8_UPPER =>
data <= dataBuf(127 downto 120); data <= dataBuf(127 downto 120);
when REG_ADDR_WORD_8_LOWER_BYTE => when OB_WORD_8_LOWER =>
data <= dataBuf(119 downto 112); data <= dataBuf(119 downto 112);
when REG_ADDR_WORD_7_UPPER_BYTE => when OB_WORD_7_UPPER =>
data <= dataBuf(111 downto 104); data <= dataBuf(111 downto 104);
when REG_ADDR_WORD_7_LOWER_BYTE => when OB_WORD_7_LOWER =>
data <= dataBuf(103 downto 96); data <= dataBuf(103 downto 96);
when REG_ADDR_WORD_6_UPPER_BYTE => when OB_WORD_6_UPPER =>
data <= dataBuf(95 downto 88); data <= dataBuf(95 downto 88);
when REG_ADDR_WORD_6_LOWER_BYTE => when OB_WORD_6_LOWER =>
data <= dataBuf(87 downto 80); data <= dataBuf(87 downto 80);
when REG_ADDR_WORD_5_UPPER_BYTE => when OB_WORD_5_UPPER =>
data <= dataBuf(79 downto 72); data <= dataBuf(79 downto 72);
when REG_ADDR_WORD_5_LOWER_BYTE => when OB_WORD_5_LOWER =>
data <= dataBuf(71 downto 64); data <= dataBuf(71 downto 64);
when REG_ADDR_WORD_4_UPPER_BYTE => when OB_WORD_4_UPPER =>
data <= dataBuf(63 downto 56); data <= dataBuf(63 downto 56);
when REG_ADDR_WORD_4_LOWER_BYTE => when OB_WORD_4_LOWER =>
data <= dataBuf(55 downto 48); data <= dataBuf(55 downto 48);
when REG_ADDR_WORD_3_UPPER_BYTE => when OB_WORD_3_UPPER =>
data <= dataBuf(47 downto 40); data <= dataBuf(47 downto 40);
when REG_ADDR_WORD_3_LOWER_BYTE => when OB_WORD_3_LOWER =>
data <= dataBuf(39 downto 32); data <= dataBuf(39 downto 32);
when REG_ADDR_WORD_2_UPPER_BYTE => when OB_WORD_2_UPPER =>
data <= dataBuf(31 downto 24); data <= dataBuf(31 downto 24);
when REG_ADDR_WORD_2_LOWER_BYTE => when OB_WORD_2_LOWER =>
data <= dataBuf(23 downto 16); data <= dataBuf(23 downto 16);
when REG_ADDR_WORD_1_UPPER_BYTE => when OB_WORD_1_UPPER =>
data <= dataBuf(15 downto 8); data <= dataBuf(15 downto 8);
when REG_ADDR_WORD_1_LOWER_BYTE => when OB_WORD_1_LOWER =>
data <= dataBuf(7 downto 0); data <= dataBuf(7 downto 0);
when others => when others =>
data <= (others => 'Z'); -- Запретить запись на шину data <= (others => 'Z'); -- Запретить запись на шину
end case; end case;
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
case addr is case addr is
when REG_ADDR_CMD_UPPER_BYTE => when OB_CMD_UPPER =>
cmdBuf(15 downto 8) <= data; cmdBuf(15 downto 8) <= data;
when REG_ADDR_CMD_LOWER_BYTE => when OB_CMD_LOWER =>
cmdBuf(7 downto 0) <= data; cmdBuf(7 downto 0) <= data;
when REG_ADDR_WORD_8_UPPER_BYTE => when OB_WORD_8_UPPER =>
dataBuf(127 downto 120) <= data; dataBuf(127 downto 120) <= data;
when REG_ADDR_WORD_8_LOWER_BYTE => when OB_WORD_8_LOWER =>
dataBuf(119 downto 112) <= data; dataBuf(119 downto 112) <= data;
when REG_ADDR_WORD_7_UPPER_BYTE => when OB_WORD_7_UPPER =>
dataBuf(111 downto 104) <= data; dataBuf(111 downto 104) <= data;
when REG_ADDR_WORD_7_LOWER_BYTE => when OB_WORD_7_LOWER =>
dataBuf(103 downto 96) <= data; dataBuf(103 downto 96) <= data;
when REG_ADDR_WORD_6_UPPER_BYTE => when OB_WORD_6_UPPER =>
dataBuf(95 downto 88) <= data; dataBuf(95 downto 88) <= data;
when REG_ADDR_WORD_6_LOWER_BYTE => when OB_WORD_6_LOWER =>
dataBuf(87 downto 80) <= data; dataBuf(87 downto 80) <= data;
when REG_ADDR_WORD_5_UPPER_BYTE => when OB_WORD_5_UPPER =>
dataBuf(79 downto 72) <= data; dataBuf(79 downto 72) <= data;
when REG_ADDR_WORD_5_LOWER_BYTE => when OB_WORD_5_LOWER =>
dataBuf(71 downto 64) <= data; dataBuf(71 downto 64) <= data;
when REG_ADDR_WORD_4_UPPER_BYTE => when OB_WORD_4_UPPER =>
dataBuf(63 downto 56) <= data; dataBuf(63 downto 56) <= data;
when REG_ADDR_WORD_4_LOWER_BYTE => when OB_WORD_4_LOWER =>
dataBuf(55 downto 48) <= data; dataBuf(55 downto 48) <= data;
when REG_ADDR_WORD_3_UPPER_BYTE => when OB_WORD_3_UPPER =>
dataBuf(47 downto 40) <= data; dataBuf(47 downto 40) <= data;
when REG_ADDR_WORD_3_LOWER_BYTE => when OB_WORD_3_LOWER =>
dataBuf(39 downto 32) <= data; dataBuf(39 downto 32) <= data;
when REG_ADDR_WORD_2_UPPER_BYTE => when OB_WORD_2_UPPER =>
dataBuf(31 downto 24) <= data; dataBuf(31 downto 24) <= data;
when REG_ADDR_WORD_2_LOWER_BYTE => when OB_WORD_2_LOWER =>
dataBuf(23 downto 16) <= data; dataBuf(23 downto 16) <= data;
when REG_ADDR_WORD_1_UPPER_BYTE => when OB_WORD_1_UPPER =>
dataBuf(15 downto 8) <= data; dataBuf(15 downto 8) <= data;
when REG_ADDR_WORD_1_LOWER_BYTE => when OB_WORD_1_LOWER =>
dataBuf(7 downto 0) <= data; dataBuf(7 downto 0) <= data;
when others => when others =>
data <= (others => 'Z'); -- Запретить запись на шину data <= (others => 'Z'); -- Запретить запись на шину
end case; end case;
if (addr = REG_ADDR_WORD_1_UPPER_BYTE) then if (addr = OB_WORD_1_UPPER) then
start <= '1'; start <= '1';
else else
start <= '0'; start <= '0';

48
MainController/RAM9X8_PWM.bsf
View File

@ -94,122 +94,122 @@ applicable agreement for further details.
(line (pt 328 32)(pt 312 32)(line_width 3)) (line (pt 328 32)(pt 312 32)(line_width 3))
) )
(parameter (parameter
"REG_ADDR_MODE_CONTROL_LOWER_BYTE" "PWM_MODE_CONTROL_LOWER"
"14" "14"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_MODE_CONTROL_UPPER_BYTE" "PWM_MODE_CONTROL_UPPER"
"15" "15"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_MASK_2_LOWER_BYTE" "PWM_MASK_2_LOWER"
"16" "16"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_MASK_2_UPPER_BYTE" "PWM_MASK_2_UPPER"
"17" "17"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_MASK_1_LOWER_BYTE" "PWM_MASK_1_LOWER"
"18" "18"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_MASK_1_UPPER_BYTE" "PWM_MASK_1_UPPER"
"19" "19"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_DIRECT_CONTROL_2_LOWER_BYTE" "PWM_DIRECT_CONTROL_2_LOWER"
"20" "20"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_DIRECT_CONTROL_2_UPPER_BYTE" "PWM_DIRECT_CONTROL_2_UPPER"
"21" "21"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_DIRECT_CONTROL_1_LOWER_BYTE" "PWM_DIRECT_CONTROL_1_LOWER"
"22" "22"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_DIRECT_CONTROL_1_UPPER_BYTE" "PWM_DIRECT_CONTROL_1_UPPER"
"23" "23"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_PERIOD_LOWER_BYTE" "PWM_PERIOD_LOWER"
"24" "24"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_PERIOD_UPPER_BYTE" "PWM_PERIOD_UPPER"
"25" "25"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_DIRECTION_2_LOWER_BYTE" "PWM_DIRECTION_2_LOWER"
"26" "26"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_DIRECTION_2_UPPER_BYTE" "PWM_DIRECTION_2_UPPER"
"27" "27"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_DIRECTION_1_LOWER_BYTE" "PWM_DIRECTION_1_LOWER"
"28" "28"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_DIRECTION_1_UPPER_BYTE" "PWM_DIRECTION_1_UPPER"
"29" "29"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CHANNEL_LOWER_BYTE" "PWM_CHANNEL_LOWER"
"30" "30"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CHANNEL_UPPER_BYTE" "PWM_CHANNEL_UPPER"
"31" "31"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_TIMING_LOWER_BYTE" "PWM_TIMING_LOWER"
"32" "32"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_TIMING_UPPER_BYTE" "PWM_TIMING_UPPER"
"33" "33"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CMD_LOWER_BYTE" "PWM_CMD_LOWER"
"34" "34"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CMD_UPPER_BYTE" "PWM_CMD_UPPER"
"35" "35"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CONTROL_LOWER_BYTE" "PWM_CONTROL_LOWER"
"36" "36"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CONTROL_UPPER_BYTE" "PWM_CONTROL_UPPER"
"37" "37"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )

160
MainController/RAM9X8_PWM.vhd
View File

@ -5,30 +5,30 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8_PWM is entity RAM9X8_PWM is
generic( generic(
REG_ADDR_MODE_CONTROL_LOWER_BYTE : integer := 14; PWM_MODE_CONTROL_LOWER : integer := 14;
REG_ADDR_MODE_CONTROL_UPPER_BYTE : integer := 15; PWM_MODE_CONTROL_UPPER : integer := 15;
REG_ADDR_MASK_2_LOWER_BYTE : integer := 16; PWM_MASK_2_LOWER : integer := 16;
REG_ADDR_MASK_2_UPPER_BYTE : integer := 17; PWM_MASK_2_UPPER : integer := 17;
REG_ADDR_MASK_1_LOWER_BYTE : integer := 18; PWM_MASK_1_LOWER : integer := 18;
REG_ADDR_MASK_1_UPPER_BYTE : integer := 19; PWM_MASK_1_UPPER : integer := 19;
REG_ADDR_DIRECT_CONTROL_2_LOWER_BYTE : integer := 20; PWM_DIRECT_CONTROL_2_LOWER : integer := 20;
REG_ADDR_DIRECT_CONTROL_2_UPPER_BYTE : integer := 21; PWM_DIRECT_CONTROL_2_UPPER : integer := 21;
REG_ADDR_DIRECT_CONTROL_1_LOWER_BYTE : integer := 22; PWM_DIRECT_CONTROL_1_LOWER : integer := 22;
REG_ADDR_DIRECT_CONTROL_1_UPPER_BYTE : integer := 23; PWM_DIRECT_CONTROL_1_UPPER : integer := 23;
REG_ADDR_PERIOD_LOWER_BYTE : integer := 24; PWM_PERIOD_LOWER : integer := 24;
REG_ADDR_PERIOD_UPPER_BYTE : integer := 25; PWM_PERIOD_UPPER : integer := 25;
REG_ADDR_DIRECTION_2_LOWER_BYTE : integer := 26; PWM_DIRECTION_2_LOWER : integer := 26;
REG_ADDR_DIRECTION_2_UPPER_BYTE : integer := 27; PWM_DIRECTION_2_UPPER : integer := 27;
REG_ADDR_DIRECTION_1_LOWER_BYTE : integer := 28; PWM_DIRECTION_1_LOWER : integer := 28;
REG_ADDR_DIRECTION_1_UPPER_BYTE : integer := 29; PWM_DIRECTION_1_UPPER : integer := 29;
REG_ADDR_CHANNEL_LOWER_BYTE : integer := 30; PWM_CHANNEL_LOWER : integer := 30;
REG_ADDR_CHANNEL_UPPER_BYTE : integer := 31; PWM_CHANNEL_UPPER : integer := 31;
REG_ADDR_TIMING_LOWER_BYTE : integer := 32; PWM_TIMING_LOWER : integer := 32;
REG_ADDR_TIMING_UPPER_BYTE : integer := 33; PWM_TIMING_UPPER : integer := 33;
REG_ADDR_CMD_LOWER_BYTE : integer := 34; PWM_CMD_LOWER : integer := 34;
REG_ADDR_CMD_UPPER_BYTE : integer := 35; PWM_CMD_UPPER : integer := 35;
REG_ADDR_CONTROL_LOWER_BYTE : integer := 36; PWM_CONTROL_LOWER : integer := 36;
REG_ADDR_CONTROL_UPPER_BYTE : integer := 37; PWM_CONTROL_UPPER : integer := 37;
DATA_BUS_WIDTH : integer := 8; DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9 ADDRESS_BUS_WIDTH : integer := 9
@ -83,121 +83,121 @@ begin
begin begin
if (ce = '0') then -- Если микросхема выбрана if (ce = '0') then -- Если микросхема выбрана
addr := conv_integer(address); addr := conv_integer(address);
if (addr = REG_ADDR_MODE_CONTROL_UPPER_BYTE or addr = REG_ADDR_MODE_CONTROL_LOWER_BYTE if (addr = PWM_MODE_CONTROL_UPPER or addr = PWM_MODE_CONTROL_LOWER
or addr = REG_ADDR_MASK_2_UPPER_BYTE or addr = REG_ADDR_MASK_2_LOWER_BYTE or addr = REG_ADDR_MASK_1_UPPER_BYTE or addr = REG_ADDR_MASK_1_LOWER_BYTE or addr = PWM_MASK_2_UPPER or addr = PWM_MASK_2_LOWER or addr = PWM_MASK_1_UPPER or addr = PWM_MASK_1_LOWER
or addr = REG_ADDR_DIRECT_CONTROL_2_UPPER_BYTE or addr = REG_ADDR_DIRECT_CONTROL_2_LOWER_BYTE or addr = REG_ADDR_DIRECT_CONTROL_1_UPPER_BYTE or addr = REG_ADDR_DIRECT_CONTROL_1_LOWER_BYTE or addr = PWM_DIRECT_CONTROL_2_UPPER or addr = PWM_DIRECT_CONTROL_2_LOWER or addr = PWM_DIRECT_CONTROL_1_UPPER or addr = PWM_DIRECT_CONTROL_1_LOWER
or addr = REG_ADDR_PERIOD_UPPER_BYTE or addr = REG_ADDR_PERIOD_LOWER_BYTE or addr = PWM_PERIOD_UPPER or addr = PWM_PERIOD_LOWER
or addr = REG_ADDR_DIRECTION_2_UPPER_BYTE or addr = REG_ADDR_DIRECTION_2_LOWER_BYTE or addr = REG_ADDR_DIRECTION_1_UPPER_BYTE or addr = REG_ADDR_DIRECTION_1_LOWER_BYTE or addr = PWM_DIRECTION_2_UPPER or addr = PWM_DIRECTION_2_LOWER or addr = PWM_DIRECTION_1_UPPER or addr = PWM_DIRECTION_1_LOWER
or addr = REG_ADDR_CHANNEL_UPPER_BYTE or addr = REG_ADDR_CHANNEL_LOWER_BYTE or addr = REG_ADDR_TIMING_UPPER_BYTE or addr = REG_ADDR_TIMING_LOWER_BYTE or addr = PWM_CHANNEL_UPPER or addr = PWM_CHANNEL_LOWER or addr = PWM_TIMING_UPPER or addr = PWM_TIMING_LOWER
or addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE or addr = REG_ADDR_CONTROL_UPPER_BYTE or addr = REG_ADDR_CONTROL_LOWER_BYTE) then or addr = PWM_CMD_UPPER or addr = PWM_CMD_LOWER or addr = PWM_CONTROL_UPPER or addr = PWM_CONTROL_LOWER) then
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
case addr is case addr is
when REG_ADDR_MODE_CONTROL_UPPER_BYTE => when PWM_MODE_CONTROL_UPPER =>
data <= modeBuf(15 downto 8); data <= modeBuf(15 downto 8);
when REG_ADDR_MODE_CONTROL_LOWER_BYTE => when PWM_MODE_CONTROL_LOWER =>
data <= modeBuf(7 downto 0); data <= modeBuf(7 downto 0);
when REG_ADDR_MASK_2_UPPER_BYTE => when PWM_MASK_2_UPPER =>
data <= maskBuf(31 downto 24); data <= maskBuf(31 downto 24);
when REG_ADDR_MASK_2_LOWER_BYTE => when PWM_MASK_2_LOWER =>
data <= maskBuf(23 downto 16); data <= maskBuf(23 downto 16);
when REG_ADDR_MASK_1_UPPER_BYTE => when PWM_MASK_1_UPPER =>
data <= maskBuf(15 downto 8); data <= maskBuf(15 downto 8);
when REG_ADDR_MASK_1_LOWER_BYTE => when PWM_MASK_1_LOWER =>
data <= maskBuf(7 downto 0); data <= maskBuf(7 downto 0);
when REG_ADDR_DIRECT_CONTROL_2_UPPER_BYTE => when PWM_DIRECT_CONTROL_2_UPPER =>
data <= directControlBuf(31 downto 24); data <= directControlBuf(31 downto 24);
when REG_ADDR_DIRECT_CONTROL_2_LOWER_BYTE => when PWM_DIRECT_CONTROL_2_LOWER =>
data <= directControlBuf(23 downto 16); data <= directControlBuf(23 downto 16);
when REG_ADDR_DIRECT_CONTROL_1_UPPER_BYTE => when PWM_DIRECT_CONTROL_1_UPPER =>
data <= directControlBuf(15 downto 8); data <= directControlBuf(15 downto 8);
when REG_ADDR_DIRECT_CONTROL_1_LOWER_BYTE => when PWM_DIRECT_CONTROL_1_LOWER =>
data <= directControlBuf(7 downto 0); data <= directControlBuf(7 downto 0);
when REG_ADDR_PERIOD_UPPER_BYTE => when PWM_PERIOD_UPPER =>
data <= periodBuf(15 downto 8); data <= periodBuf(15 downto 8);
when REG_ADDR_PERIOD_LOWER_BYTE => when PWM_PERIOD_LOWER =>
data <= periodBuf(7 downto 0); data <= periodBuf(7 downto 0);
when REG_ADDR_DIRECTION_2_UPPER_BYTE => when PWM_DIRECTION_2_UPPER =>
data <= directionBuf(31 downto 24); data <= directionBuf(31 downto 24);
when REG_ADDR_DIRECTION_2_LOWER_BYTE => when PWM_DIRECTION_2_LOWER =>
data <= directionBuf(23 downto 16); data <= directionBuf(23 downto 16);
when REG_ADDR_DIRECTION_1_UPPER_BYTE => when PWM_DIRECTION_1_UPPER =>
data <= directionBuf(15 downto 8); data <= directionBuf(15 downto 8);
when REG_ADDR_DIRECTION_1_LOWER_BYTE => when PWM_DIRECTION_1_LOWER =>
data <= directionBuf(7 downto 0); data <= directionBuf(7 downto 0);
when REG_ADDR_CHANNEL_UPPER_BYTE => when PWM_CHANNEL_UPPER =>
data <= channelBuf(15 downto 8); data <= channelBuf(15 downto 8);
when REG_ADDR_CHANNEL_LOWER_BYTE => when PWM_CHANNEL_LOWER =>
data <= channelBuf(7 downto 0); data <= channelBuf(7 downto 0);
when REG_ADDR_TIMING_UPPER_BYTE => when PWM_TIMING_UPPER =>
data <= memory(conv_integer(channelBuf))(15 downto 8); data <= memory(conv_integer(channelBuf))(15 downto 8);
when REG_ADDR_TIMING_LOWER_BYTE => when PWM_TIMING_LOWER =>
data <= memory(conv_integer(channelBuf))(7 downto 0); data <= memory(conv_integer(channelBuf))(7 downto 0);
when REG_ADDR_CMD_UPPER_BYTE => when PWM_CMD_UPPER =>
data <= cmdBuf(15 downto 8); data <= cmdBuf(15 downto 8);
when REG_ADDR_CMD_LOWER_BYTE => when PWM_CMD_LOWER =>
data <= cmdBuf(7 downto 0); data <= cmdBuf(7 downto 0);
when REG_ADDR_CONTROL_UPPER_BYTE => when PWM_CONTROL_UPPER =>
data <= controlBuf(15 downto 8); data <= controlBuf(15 downto 8);
when REG_ADDR_CONTROL_LOWER_BYTE => when PWM_CONTROL_LOWER =>
data <= controlBuf(7 downto 0); data <= controlBuf(7 downto 0);
when others => when others =>
data <= (others => 'Z'); -- Запретить запись на шину data <= (others => 'Z'); -- Запретить запись на шину
end case; end case;
if addr /= REG_ADDR_CONTROL_LOWER_BYTE then if addr /= PWM_CONTROL_LOWER then
enableWriteControlBuf <= '1'; enableWriteControlBuf <= '1';
else else
enableWriteControlBuf <= '0'; enableWriteControlBuf <= '0';
end if; end if;
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
case addr is case addr is
when REG_ADDR_MODE_CONTROL_UPPER_BYTE => when PWM_MODE_CONTROL_UPPER =>
modeBuf(15 downto 8) <= data; modeBuf(15 downto 8) <= data;
when REG_ADDR_MODE_CONTROL_LOWER_BYTE => when PWM_MODE_CONTROL_LOWER =>
modeBuf(7 downto 0) <= data; modeBuf(7 downto 0) <= data;
when REG_ADDR_MASK_2_UPPER_BYTE => when PWM_MASK_2_UPPER =>
maskBuf(31 downto 24) <= data; maskBuf(31 downto 24) <= data;
when REG_ADDR_MASK_2_LOWER_BYTE => when PWM_MASK_2_LOWER =>
maskBuf(23 downto 16) <= data; maskBuf(23 downto 16) <= data;
when REG_ADDR_MASK_1_UPPER_BYTE => when PWM_MASK_1_UPPER =>
maskBuf(15 downto 8) <= data; maskBuf(15 downto 8) <= data;
when REG_ADDR_MASK_1_LOWER_BYTE => when PWM_MASK_1_LOWER =>
maskBuf(7 downto 0) <= data; maskBuf(7 downto 0) <= data;
when REG_ADDR_DIRECT_CONTROL_2_UPPER_BYTE => when PWM_DIRECT_CONTROL_2_UPPER =>
directControlBuf(31 downto 24) <= data; directControlBuf(31 downto 24) <= data;
when REG_ADDR_DIRECT_CONTROL_2_LOWER_BYTE => when PWM_DIRECT_CONTROL_2_LOWER =>
directControlBuf(23 downto 16) <= data; directControlBuf(23 downto 16) <= data;
when REG_ADDR_DIRECT_CONTROL_1_UPPER_BYTE => when PWM_DIRECT_CONTROL_1_UPPER =>
directControlBuf(15 downto 8) <= data; directControlBuf(15 downto 8) <= data;
when REG_ADDR_DIRECT_CONTROL_1_LOWER_BYTE => when PWM_DIRECT_CONTROL_1_LOWER =>
directControlBuf(7 downto 0) <= data; directControlBuf(7 downto 0) <= data;
when REG_ADDR_PERIOD_UPPER_BYTE => when PWM_PERIOD_UPPER =>
periodBuf(15 downto 8) <= data; periodBuf(15 downto 8) <= data;
when REG_ADDR_PERIOD_LOWER_BYTE => when PWM_PERIOD_LOWER =>
periodBuf(7 downto 0) <= data; periodBuf(7 downto 0) <= data;
when REG_ADDR_DIRECTION_2_UPPER_BYTE => when PWM_DIRECTION_2_UPPER =>
directionBuf(31 downto 24) <= data; directionBuf(31 downto 24) <= data;
when REG_ADDR_DIRECTION_2_LOWER_BYTE => when PWM_DIRECTION_2_LOWER =>
directionBuf(23 downto 16) <= data; directionBuf(23 downto 16) <= data;
when REG_ADDR_DIRECTION_1_UPPER_BYTE => when PWM_DIRECTION_1_UPPER =>
directionBuf(15 downto 8) <= data; directionBuf(15 downto 8) <= data;
when REG_ADDR_DIRECTION_1_LOWER_BYTE => when PWM_DIRECTION_1_LOWER =>
directionBuf(7 downto 0) <= data; directionBuf(7 downto 0) <= data;
when REG_ADDR_CHANNEL_UPPER_BYTE => when PWM_CHANNEL_UPPER =>
channelBuf(15 downto 8) <= data; channelBuf(15 downto 8) <= data;
when REG_ADDR_CHANNEL_LOWER_BYTE => when PWM_CHANNEL_LOWER =>
channelBuf(7 downto 0) <= data; channelBuf(7 downto 0) <= data;
when REG_ADDR_TIMING_UPPER_BYTE => when PWM_TIMING_UPPER =>
memory(conv_integer(channelBuf))(15 downto 8) <= data; memory(conv_integer(channelBuf))(15 downto 8) <= data;
when REG_ADDR_TIMING_LOWER_BYTE => when PWM_TIMING_LOWER =>
memory(conv_integer(channelBuf))(7 downto 0) <= data; memory(conv_integer(channelBuf))(7 downto 0) <= data;
when REG_ADDR_CMD_UPPER_BYTE => when PWM_CMD_UPPER =>
cmdBuf(15 downto 8) <= data; cmdBuf(15 downto 8) <= data;
when REG_ADDR_CMD_LOWER_BYTE => when PWM_CMD_LOWER =>
cmdBuf(7 downto 0) <= data; cmdBuf(7 downto 0) <= data;
-- when REG_ADDR_CONTROL_UPPER_BYTE => -- when PWM_CONTROL_UPPER =>
-- controlBuf(15 downto 8) <= data; -- controlBuf(15 downto 8) <= data;
-- when REG_ADDR_CONTROL_LOWER_BYTE => -- when PWM_CONTROL_LOWER =>
-- controlBuf(7 downto 0) <= data; -- controlBuf(7 downto 0) <= data;
when others => when others =>
data <= (others => 'Z'); -- Запретить запись на шину data <= (others => 'Z'); -- Запретить запись на шину

16
MainController/RAM9X8_ParallelBusMaster.bsf
View File

@ -101,42 +101,42 @@ applicable agreement for further details.
(line (pt 328 96)(pt 312 96)(line_width 3)) (line (pt 328 96)(pt 312 96)(line_width 3))
) )
(parameter (parameter
"REG_ADDR_FIRST_FREE_LOWER_BYTE" "PB_FIRST_FREE_LOWER"
"6" "6"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_FIRST_FREE_UPPER_BYTE" "PB_FIRST_FREE_UPPER"
"7" "7"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CMD_LOWER_BYTE" "PB_CMD_LOWER"
"8" "8"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CMD_UPPER_BYTE" "PB_CMD_UPPER"
"9" "9"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_FILL_ADDRESS_SPACE_LOWER_BYTE" "PB_FILL_ADDRESS_SPACE_LOWER"
"10" "10"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_FILL_ADDRESS_SPACE_UPPER_BYTE" "PB_FILL_ADDRESS_SPACE_UPPER"
"11" "11"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CONTROL_LOWER_BYTE" "PB_CONTROL_LOWER"
"12" "12"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CONTROL_UPPER_BYTE" "PB_CONTROL_UPPER"
"13" "13"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )

48
MainController/RAM9X8_ParallelBusMaster.vhd
View File

@ -5,14 +5,14 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8_ParallelBusMaster is entity RAM9X8_ParallelBusMaster is
generic( generic(
REG_ADDR_FIRST_FREE_LOWER_BYTE : integer := 6; PB_FIRST_FREE_LOWER : integer := 6;
REG_ADDR_FIRST_FREE_UPPER_BYTE : integer := 7; PB_FIRST_FREE_UPPER : integer := 7;
REG_ADDR_CMD_LOWER_BYTE : integer := 8; PB_CMD_LOWER : integer := 8;
REG_ADDR_CMD_UPPER_BYTE : integer := 9; PB_CMD_UPPER : integer := 9;
REG_ADDR_FILL_ADDRESS_SPACE_LOWER_BYTE : integer := 10; PB_FILL_ADDRESS_SPACE_LOWER : integer := 10;
REG_ADDR_FILL_ADDRESS_SPACE_UPPER_BYTE : integer := 11; PB_FILL_ADDRESS_SPACE_UPPER : integer := 11;
REG_ADDR_CONTROL_LOWER_BYTE : integer := 12; PB_CONTROL_LOWER : integer := 12;
REG_ADDR_CONTROL_UPPER_BYTE : integer := 13; PB_CONTROL_UPPER : integer := 13;
ARRAY_LENGTH : integer := 256; ARRAY_LENGTH : integer := 256;
DATA_BUS_WIDTH : integer := 8; DATA_BUS_WIDTH : integer := 8;
@ -67,42 +67,42 @@ begin
begin begin
if (ce = '0') then -- Если микросхема выбрана if (ce = '0') then -- Если микросхема выбрана
addr := conv_integer(address); addr := conv_integer(address);
if (addr = REG_ADDR_FIRST_FREE_UPPER_BYTE or addr = REG_ADDR_FIRST_FREE_LOWER_BYTE or addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE if (addr = PB_FIRST_FREE_UPPER or addr = PB_FIRST_FREE_LOWER or addr = PB_CMD_UPPER or addr = PB_CMD_LOWER
or addr = REG_ADDR_FILL_ADDRESS_SPACE_UPPER_BYTE or addr = REG_ADDR_FILL_ADDRESS_SPACE_LOWER_BYTE or addr = REG_ADDR_CONTROL_UPPER_BYTE or addr = REG_ADDR_CONTROL_LOWER_BYTE) then or addr = PB_FILL_ADDRESS_SPACE_UPPER or addr = PB_FILL_ADDRESS_SPACE_LOWER or addr = PB_CONTROL_UPPER or addr = PB_CONTROL_LOWER) then
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
case addr is case addr is
when REG_ADDR_FIRST_FREE_UPPER_BYTE => when PB_FIRST_FREE_UPPER =>
data <= firstFreeBuf(15 downto 8); data <= firstFreeBuf(15 downto 8);
when REG_ADDR_FIRST_FREE_LOWER_BYTE => when PB_FIRST_FREE_LOWER =>
data <= firstFreeBuf(7 downto 0); data <= firstFreeBuf(7 downto 0);
when REG_ADDR_CMD_UPPER_BYTE => when PB_CMD_UPPER =>
data <= cmdBuf(15 downto 8); data <= cmdBuf(15 downto 8);
when REG_ADDR_CMD_LOWER_BYTE => when PB_CMD_LOWER =>
data <= cmdBuf(7 downto 0); data <= cmdBuf(7 downto 0);
when REG_ADDR_FILL_ADDRESS_SPACE_UPPER_BYTE => when PB_FILL_ADDRESS_SPACE_UPPER =>
data <= fasBuf(15 downto 8); data <= fasBuf(15 downto 8);
when REG_ADDR_FILL_ADDRESS_SPACE_LOWER_BYTE => when PB_FILL_ADDRESS_SPACE_LOWER =>
data <= fasBuf(7 downto 0); data <= fasBuf(7 downto 0);
when REG_ADDR_CONTROL_UPPER_BYTE => when PB_CONTROL_UPPER =>
data <= errorBuf; data <= errorBuf;
when REG_ADDR_CONTROL_LOWER_BYTE => when PB_CONTROL_LOWER =>
data <= controlBuf(7 downto 0); data <= controlBuf(7 downto 0);
when others => when others =>
data <= (others => 'Z'); -- Запретить запись на шину data <= (others => 'Z'); -- Запретить запись на шину
end case; end case;
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
case addr is case addr is
when REG_ADDR_FIRST_FREE_UPPER_BYTE => when PB_FIRST_FREE_UPPER =>
firstFreeBuf(15 downto 8) <= data; firstFreeBuf(15 downto 8) <= data;
when REG_ADDR_FIRST_FREE_LOWER_BYTE => when PB_FIRST_FREE_LOWER =>
firstFreeBuf(7 downto 0) <= data; firstFreeBuf(7 downto 0) <= data;
when REG_ADDR_CMD_UPPER_BYTE => when PB_CMD_UPPER =>
cmdBuf(15 downto 8) <= data; cmdBuf(15 downto 8) <= data;
when REG_ADDR_CMD_LOWER_BYTE => when PB_CMD_LOWER =>
cmdBuf(7 downto 0) <= data; cmdBuf(7 downto 0) <= data;
when REG_ADDR_FILL_ADDRESS_SPACE_UPPER_BYTE => when PB_FILL_ADDRESS_SPACE_UPPER =>
fasBuf(15 downto 8) <= data; fasBuf(15 downto 8) <= data;
when REG_ADDR_FILL_ADDRESS_SPACE_LOWER_BYTE => when PB_FILL_ADDRESS_SPACE_LOWER =>
fasBuf(7 downto 0) <= data; fasBuf(7 downto 0) <= data;
position := conv_integer(data); position := conv_integer(data);
memoryAddress(position) <= fasBuf(15 downto 8); memoryAddress(position) <= fasBuf(15 downto 8);

140
MainController/RAM9X8_Peripheral.bsf Normal file
View File

@ -0,0 +1,140 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 344 192)
(text "RAM9X8_Peripheral" (rect 5 0 89 12)(font "Arial" ))
(text "inst" (rect 8 160 20 172)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 27 31 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "address[address_bus_width-1..0]" (rect 0 0 129 12)(font "Arial" ))
(text "address[address_bus_width-1..0]" (rect 21 43 150 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "we" (rect 0 0 10 12)(font "Arial" ))
(text "we" (rect 21 59 31 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "oe" (rect 0 0 9 12)(font "Arial" ))
(text "oe" (rect 21 75 30 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "ce" (rect 0 0 9 12)(font "Arial" ))
(text "ce" (rect 21 91 30 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "error" (rect 0 0 20 12)(font "Arial" ))
(text "error" (rect 21 107 41 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 1))
)
(port
(pt 0 128)
(input)
(text "init" (rect 0 0 9 12)(font "Arial" ))
(text "init" (rect 21 123 30 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128)(line_width 1))
)
(port
(pt 328 48)
(output)
(text "asyncline" (rect 0 0 36 12)(font "Arial" ))
(text "asyncline" (rect 271 43 307 55)(font "Arial" ))
(line (pt 328 48)(pt 312 48)(line_width 1))
)
(port
(pt 328 64)
(output)
(text "divclk" (rect 0 0 22 12)(font "Arial" ))
(text "divclk" (rect 285 59 307 71)(font "Arial" ))
(line (pt 328 64)(pt 312 64)(line_width 1))
)
(port
(pt 328 32)
(bidir)
(text "data[data_bus_width-1..0]" (rect 0 0 99 12)(font "Arial" ))
(text "data[data_bus_width-1..0]" (rect 208 27 307 39)(font "Arial" ))
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"PER_ACTIVE_DEVICE_LOWER"
"38"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PER_ACTIVE_DEVICE_UPPER"
"39"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PER_REZERVED_1_LOWER"
"40"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PER_REZERVED_1_UPPER"
"41"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PER_REZERVED_2_LOWER"
"42"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PER_REZERVED_2_UPPER"
"43"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DATA_BUS_WIDTH"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"ADDRESS_BUS_WIDTH"
"9"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 312 160)(line_width 1))
)
(annotation_block (parameter)(rect 344 -64 444 16))
)

290
MainController/RAM9X8_Peripheral.vhd Normal file
View File

@ -0,0 +1,290 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RAM9X8_Peripheral is
generic(
PER_ACTIVE_DEVICE_LOWER : integer := 38;
PER_ACTIVE_DEVICE_UPPER : integer := 39;
PER_REZERVED_1_LOWER : integer := 40;
PER_REZERVED_1_UPPER : integer := 41;
PER_REZERVED_2_LOWER : integer := 42;
PER_REZERVED_2_UPPER : integer := 43;
DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9
);
port(
clk : in std_logic;
data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
we : in std_logic;
oe : in std_logic;
ce : in std_logic;
asyncline : out std_logic := '1';
divclk : out std_logic := '1';
error : in std_logic;
init : in std_logic
);
end entity;
architecture behavorial of RAM9X8_Peripheral is
signal activeDeviceBuf : std_logic_vector(15 downto 0) := (others => '0');
signal rezerved1Buf : std_logic_vector(15 downto 0) := (others => '0');
signal rezerved2Buf : std_logic_vector(15 downto 0) := (others => '0');
signal divClkBuf : std_logic := '0';
signal divClkBufPWM : std_logic := '0';
signal addrBuf : std_logic_vector(3 downto 0) := (others => '0');
signal LedState : std_logic_vector(1 downto 0) := (others => '0');
type BusSt is (Waiting, A3, A2, A1, A0, Dt, Finish);
signal BusState : BusSt := Waiting;
signal countBuf : std_logic_vector(3 downto 0) := (others => '0');
signal countBufPWM : std_logic_vector(3 downto 0) := (others => '0');
begin
process (we, oe, ce)
variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
begin
if (ce = '0') then -- Если микросхема выбрана
addr := conv_integer(address);
if (addr = PER_ACTIVE_DEVICE_UPPER or addr = PER_ACTIVE_DEVICE_LOWER
or addr = PER_REZERVED_1_UPPER or addr = PER_REZERVED_1_LOWER
or addr = PER_REZERVED_2_UPPER or addr = PER_REZERVED_2_LOWER) then
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
case addr is
when PER_ACTIVE_DEVICE_UPPER =>
data <= activeDeviceBuf(15 downto 8);
when PER_ACTIVE_DEVICE_LOWER =>
data <= activeDeviceBuf(7 downto 0);
when PER_REZERVED_1_UPPER =>
data <= rezerved1Buf(15 downto 8);
when PER_REZERVED_1_LOWER =>
data <= rezerved1Buf(7 downto 0);
when PER_REZERVED_2_UPPER =>
data <= rezerved2Buf(15 downto 8);
when PER_REZERVED_2_LOWER =>
data <= rezerved2Buf(7 downto 0);
when others =>
data <= (others => 'Z'); -- Запретить запись на шину
end case;
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
case addr is
when PER_ACTIVE_DEVICE_UPPER =>
activeDeviceBuf(15 downto 8) <= data;
when PER_ACTIVE_DEVICE_LOWER =>
activeDeviceBuf(7 downto 0) <= data;
when PER_REZERVED_1_UPPER =>
rezerved1Buf(15 downto 8) <= data;
when PER_REZERVED_1_LOWER =>
rezerved1Buf(7 downto 0) <= data;
when PER_REZERVED_2_UPPER =>
rezerved2Buf(15 downto 8) <= data;
when PER_REZERVED_2_LOWER =>
rezerved2Buf(7 downto 0) <= data;
when others =>
data <= (others => 'Z'); -- Запретить запись на шину
end case;
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;
end process;
process(clk) is
variable count50000 : integer range 0 to 50000 := 0;
variable count50 : integer range 0 to 50 := 0;
begin
if rising_edge(clk) then
if count50000 < 50000 then
count50000 := count50000 + 1;
else
divClkBufPWM <= not divClkBufPWM;
count50000 := 0;
if count50 < 50 then
count50 := count50 + 1;
else
count50 := 0;
divClkBuf <= not divClkBuf;
end if;
end if;
end if;
end process;
process(divClkBufPWM) is
begin
if conv_integer(countBufPWM) < 15 then
countBufPWM <= conv_std_logic_vector(conv_integer(countBufPWM) + 1, 4);
else
countBufPWM <= (others => '0');
end if;
end process;
process(divClkBuf) is
variable direction : integer range 0 to 1 := 0;
begin
if direction = 0 then
if conv_integer(countBuf) < 15 then
countBuf <= conv_std_logic_vector(conv_integer(countBuf) + 1, 4);
else
direction := 1;
end if;
else
if conv_integer(countBuf) > 0 then
countBuf <= conv_std_logic_vector(conv_integer(countBuf) - 1, 4);
else
direction := 0;
end if;
end if;
end process;
process(divClkBuf) is
variable count15 : integer range 0 to 15 := 0;
begin
case LedState is
when b"00" =>
if count15 < 15 then
count15 := count15 + 1;
else
count15 := 0;
LedState <= b"01";
end if;
divclk <= '0';
when b"01" =>
if count15 < 7 then
count15 := count15 + 1;
else
count15 := 0;
LedState <= b"10";
end if;
divclk <= '1';
when b"10" =>
if count15 < 15 then
count15 := count15 + 1;
else
count15 := 0;
LedState <= b"11";
end if;
divclk <= '0';
when b"11" =>
if count15 < 4 then
count15 := count15 + 1;
else
count15 := 0;
LedState <= b"00";
end if;
divclk <= '1';
when others =>
LedState <= b"00";
end case;
end process;
process(clk) is
variable count50 : integer range 0 to 50 := 0;
variable count15 : integer range 0 to 15 := 15;
begin
if rising_edge(clk) then
if init = '0' then
case BusState is
when Waiting =>
if count50 < 38 then
count50 := count50 + 1;
else
if count15 < 15 then
count15 := count15 + 1;
else
count15 := 0;
end if;
if activeDeviceBuf(count15) = '1' then
addrBuf <= conv_std_logic_vector(count15, 4);
asyncline <= '0';
count50 := 0;
BusState <= A3;
end if;
end if;
when A3 =>
if count50 < 18 then
count50 := count50 + 1;
else
count50 := 0;
asyncline <= addrBuf(3);
BusState <= A2;
end if;
when A2 =>
if count50 < 38 then
count50 := count50 + 1;
else
count50 := 0;
asyncline <= addrBuf(2);
BusState <= A1;
end if;
when A1 =>
if count50 < 38 then
count50 := count50 + 1;
else
count50 := 0;
asyncline <= addrBuf(1);
BusState <= A0;
end if;
when A0 =>
if count50 < 38 then
count50 := count50 + 1;
else
count50 := 0;
asyncline <= addrBuf(0);
BusState <= Dt;
end if;
when Dt =>
if count50 < 38 then
count50 := count50 + 1;
else
count50 := 0;
asyncline <= divClkBuf;
BusState <= Finish;
end if;
when Finish =>
if count50 < 38 then
count50 := count50 + 1;
else
count50 := 0;
asyncline <= '1';
BusState <= Finish;
end if;
when others =>
BusState <= Waiting;
count50 := 0;
count15 :=15;
end case;
else
BusState <= Waiting;
count50 := 0;
count15 := 15;
if error = '0' then
if countBuf < countBufPWM then
asyncline <= '1';
else
asyncline <= '0';
end if;
else
asyncline <= '1';
end if;
end if;
end if;
end process;
end behavorial;

12
MainController/RAM9X8_SerialBusMaster.bsf
View File

@ -87,32 +87,32 @@ applicable agreement for further details.
(line (pt 328 32)(pt 312 32)(line_width 3)) (line (pt 328 32)(pt 312 32)(line_width 3))
) )
(parameter (parameter
"REG_ADDR_DATA_LOWER_BYTE" "SB_DATA_LOWER"
"0" "0"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_DATA_UPPER_BYTE" "SB_DATA_UPPER"
"1" "1"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CMD_LOWER_BYTE" "SB_CMD_LOWER"
"2" "2"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CMD_UPPER_BYTE" "SB_CMD_UPPER"
"3" "3"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CONTROL_LOWER_BYTE" "SB_CONTROL_LOWER"
"4" "4"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_CONTROL_UPPER_BYTE" "SB_CONTROL_UPPER"
"5" "5"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )

38
MainController/RAM9X8_SerialBusMaster.vhd
View File

@ -5,12 +5,12 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8_SerialBusMaster is entity RAM9X8_SerialBusMaster is
generic( generic(
REG_ADDR_DATA_LOWER_BYTE : integer := 0; SB_DATA_LOWER : integer := 0;
REG_ADDR_DATA_UPPER_BYTE : integer := 1; SB_DATA_UPPER : integer := 1;
REG_ADDR_CMD_LOWER_BYTE : integer := 2; SB_CMD_LOWER : integer := 2;
REG_ADDR_CMD_UPPER_BYTE : integer := 3; SB_CMD_UPPER : integer := 3;
REG_ADDR_CONTROL_LOWER_BYTE : integer := 4; SB_CONTROL_LOWER : integer := 4;
REG_ADDR_CONTROL_UPPER_BYTE : integer := 5; SB_CONTROL_UPPER : integer := 5;
DATA_BUS_WIDTH : integer := 8; DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9 ADDRESS_BUS_WIDTH : integer := 9
@ -63,36 +63,36 @@ begin
begin begin
if (ce = '0') then -- Если микросхема выбрана if (ce = '0') then -- Если микросхема выбрана
addr := conv_integer(address); addr := conv_integer(address);
if (addr = REG_ADDR_DATA_UPPER_BYTE or addr = REG_ADDR_DATA_LOWER_BYTE or addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE if (addr = SB_DATA_UPPER or addr = SB_DATA_LOWER or addr = SB_CMD_UPPER or addr = SB_CMD_LOWER
or addr = REG_ADDR_CONTROL_UPPER_BYTE or addr = REG_ADDR_CONTROL_LOWER_BYTE) then or addr = SB_CONTROL_UPPER or addr = SB_CONTROL_LOWER) then
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
case addr is case addr is
when REG_ADDR_DATA_UPPER_BYTE => when SB_DATA_UPPER =>
data <= dataBufOut(15 downto 8); data <= dataBufOut(15 downto 8);
when REG_ADDR_DATA_LOWER_BYTE => when SB_DATA_LOWER =>
data <= dataBufOut(7 downto 0); data <= dataBufOut(7 downto 0);
when REG_ADDR_CMD_UPPER_BYTE => when SB_CMD_UPPER =>
data <= cmdBuf(15 downto 8); data <= cmdBuf(15 downto 8);
when REG_ADDR_CMD_LOWER_BYTE => when SB_CMD_LOWER =>
data <= cmdBuf(7 downto 0); data <= cmdBuf(7 downto 0);
when REG_ADDR_CONTROL_UPPER_BYTE => when SB_CONTROL_UPPER =>
data <= controlBuf(15 downto 8); data <= controlBuf(15 downto 8);
start <= '0'; start <= '0';
when REG_ADDR_CONTROL_LOWER_BYTE => when SB_CONTROL_LOWER =>
data <= controlBuf(7 downto 0); data <= controlBuf(7 downto 0);
when others => when others =>
data <= (others => 'Z'); -- Запретить запись на шину data <= (others => 'Z'); -- Запретить запись на шину
end case; end case;
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
case addr is case addr is
when REG_ADDR_DATA_UPPER_BYTE => when SB_DATA_UPPER =>
dataBufIn(15 downto 8) <= data; dataBufIn(15 downto 8) <= data;
when REG_ADDR_DATA_LOWER_BYTE => when SB_DATA_LOWER =>
dataBufIn(7 downto 0) <= data; dataBufIn(7 downto 0) <= data;
when REG_ADDR_CMD_UPPER_BYTE => when SB_CMD_UPPER =>
cmdBuf(15 downto 8) <= data; cmdBuf(15 downto 8) <= data;
start <= '1'; start <= '1';
when REG_ADDR_CMD_LOWER_BYTE => when SB_CMD_LOWER =>
cmdBuf(7 downto 0) <= data; cmdBuf(7 downto 0) <= data;
when others => when others =>
data <= (others => 'Z'); -- Запретить запись на шину data <= (others => 'Z'); -- Запретить запись на шину
@ -110,7 +110,7 @@ begin
process(clk) is process(clk) is
variable count : integer range 0 to 255 := 0; variable count : integer range 0 to 255 := 0;
variable countValue : integer range 0 to 255 := 63; variable countValue : integer range 0 to 255 := 50;
variable state : integer range 0 to 1 := 1; variable state : integer range 0 to 1 := 1;
variable bitCnt : integer range -1 to 31 := 0; variable bitCnt : integer range -1 to 31 := 0;
variable latch : integer range 0 to 1 := 0; variable latch : integer range 0 to 1 := 0;

157
MainController/RAM9X8_Service.bsf Normal file
View File

@ -0,0 +1,157 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 344 160)
(text "RAM9X8_Service" (rect 5 0 81 12)(font "Arial" ))
(text "inst" (rect 8 128 20 140)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 27 31 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "address[address_bus_width-1..0]" (rect 0 0 129 12)(font "Arial" ))
(text "address[address_bus_width-1..0]" (rect 21 43 150 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "we" (rect 0 0 10 12)(font "Arial" ))
(text "we" (rect 21 59 31 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "oe" (rect 0 0 9 12)(font "Arial" ))
(text "oe" (rect 21 75 30 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "ce" (rect 0 0 9 12)(font "Arial" ))
(text "ce" (rect 21 91 30 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "er0_in" (rect 0 0 24 12)(font "Arial" ))
(text "er0_in" (rect 21 107 45 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 1))
)
(port
(pt 328 48)
(output)
(text "leds[3..0]" (rect 0 0 35 12)(font "Arial" ))
(text "leds[3..0]" (rect 272 43 307 55)(font "Arial" ))
(line (pt 328 48)(pt 312 48)(line_width 3))
)
(port
(pt 328 64)
(output)
(text "er0_out" (rect 0 0 30 12)(font "Arial" ))
(text "er0_out" (rect 277 59 307 71)(font "Arial" ))
(line (pt 328 64)(pt 312 64)(line_width 1))
)
(port
(pt 328 80)
(output)
(text "init" (rect 0 0 9 12)(font "Arial" ))
(text "init" (rect 298 75 307 87)(font "Arial" ))
(line (pt 328 80)(pt 312 80)(line_width 1))
)
(port
(pt 328 96)
(output)
(text "sres" (rect 0 0 17 12)(font "Arial" ))
(text "sres" (rect 290 91 307 103)(font "Arial" ))
(line (pt 328 96)(pt 312 96)(line_width 1))
)
(port
(pt 328 32)
(bidir)
(text "data[data_bus_width-1..0]" (rect 0 0 99 12)(font "Arial" ))
(text "data[data_bus_width-1..0]" (rect 208 27 307 39)(font "Arial" ))
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"SRV_CONTROL_LOWER"
"72"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SRV_CONTROL_UPPER"
"73"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SRV_LEDS_LOWER"
"74"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SRV_LEDS_UPPER"
"75"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SRV_INIT_LOWER"
"76"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SRV_INIT_UPPER"
"77"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SRV_VERSION_LOWER"
"78"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SRV_VERSION_UPPER"
"79"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DATA_BUS_WIDTH"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"ADDRESS_BUS_WIDTH"
"9"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 312 128)(line_width 1))
)
(annotation_block (parameter)(rect 344 -64 444 16))
)

119
MainController/RAM9X8_Service.vhd Normal file
View File

@ -0,0 +1,119 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RAM9X8_Service is
generic(
SRV_CONTROL_LOWER : integer := 72;
SRV_CONTROL_UPPER : integer := 73;
SRV_LEDS_LOWER : integer := 74;
SRV_LEDS_UPPER : integer := 75;
SRV_INIT_LOWER : integer := 76;
SRV_INIT_UPPER : integer := 77;
SRV_VERSION_LOWER : integer := 78;
SRV_VERSION_UPPER : integer := 79;
DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9
);
port(
clk : in std_logic;
data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
we : in std_logic;
oe : in std_logic;
ce : in std_logic;
er0_in : in std_logic;
leds : out std_logic_vector(3 downto 0);
er0_out : out std_logic;
init : out std_logic;
sres : out std_logic
);
end entity;
architecture behavorial of RAM9X8_Service is
signal ledsBuf : std_logic_vector(15 downto 0) := (others => '0');
signal initBuf : std_logic_vector(15 downto 0) := (others => '0');
signal versionBuf : std_logic_vector(15 downto 0) := x"0004";
begin
process (we, oe, ce)
variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
begin
if (ce = '0') then -- Если микросхема выбрана
addr := conv_integer(address);
if (addr = SRV_CONTROL_UPPER or addr = SRV_CONTROL_LOWER
or addr = SRV_LEDS_LOWER or addr = SRV_LEDS_UPPER
or addr = SRV_INIT_LOWER or addr = SRV_INIT_UPPER
or addr = SRV_VERSION_LOWER or addr = SRV_VERSION_UPPER) then
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
case addr is
when SRV_CONTROL_UPPER =>
data <= (others => '0');
when SRV_CONTROL_LOWER =>
data(7 downto 1) <= (others => '0');
data(0) <= er0_in;
when SRV_LEDS_UPPER =>
data <= ledsBuf(15 downto 8);
when SRV_LEDS_LOWER =>
data <= ledsBuf(7 downto 0);
when SRV_INIT_UPPER =>
data <= not initBuf(15 downto 8);
when SRV_INIT_LOWER =>
data <= not initBuf(7 downto 0);
when SRV_VERSION_UPPER =>
data <= versionBuf(15 downto 8);
when SRV_VERSION_LOWER =>
data <= versionBuf(7 downto 0);
when others =>
data <= (others => 'Z'); -- Запретить запись на шину
end case;
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
case addr is
when SRV_LEDS_UPPER =>
ledsBuf(15 downto 8) <= data;
when SRV_LEDS_LOWER =>
ledsBuf(7 downto 0) <= data;
when SRV_INIT_UPPER =>
initBuf(15 downto 8) <= data;
when SRV_INIT_LOWER =>
initBuf(7 downto 0) <= data;
when others =>
data <= (others => 'Z'); -- Запретить запись на шину
end case;
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;
end process;
process(clk) is
begin
if rising_edge(clk) then
if initBuf = x"5AA5" then
init <= '1';
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
leds <= ledsBuf(3 downto 0);
er0_out <= ledsBuf(15);
sres <= ledsBuf(14);
end if;
end process;
end behavorial;

BIN
Xilinx Spartan 2E.pdf Normal file
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