Заменил RAM9X8 на расширяемый с помощью параметров RAM.
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@ -395,49 +395,6 @@ applicable agreement for further details.
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(rectangle (rect 16 16 216 112))
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)
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)
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(symbol
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(rect 1040 256 1232 368)
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(text "RAM9X8" (rect 5 0 46 12)(font "Arial" ))
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(text "inst13" (rect 8 96 37 108)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "address[8..0]" (rect 0 0 64 12)(font "Arial" ))
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(text "address[8..0]" (rect 21 27 85 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 3))
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)
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(port
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(pt 0 48)
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(input)
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(text "we" (rect 0 0 12 12)(font "Arial" ))
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(text "we" (rect 21 43 33 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48))
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)
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(port
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(pt 0 64)
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(input)
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(text "oe" (rect 0 0 11 12)(font "Arial" ))
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(text "oe" (rect 21 59 32 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64))
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)
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(port
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(pt 0 80)
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(input)
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(text "ce" (rect 0 0 11 12)(font "Arial" ))
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(text "ce" (rect 21 75 32 87)(font "Arial" ))
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(line (pt 0 80)(pt 16 80))
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)
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(port
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(pt 192 32)
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(bidir)
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(text "data[7..0]" (rect 0 0 47 12)(font "Arial" ))
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(text "data[7..0]" (rect 135 27 182 39)(font "Arial" ))
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(line (pt 192 32)(pt 176 32)(line_width 3))
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)
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(drawing
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(rectangle (rect 16 16 176 96))
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)
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)
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(symbol
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(rect 1040 544 1368 688)
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(text "RAM9X8_SerialBusMaster" (rect 5 0 131 12)(font "Arial" ))
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@ -540,6 +497,60 @@ applicable agreement for further details.
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)
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(annotation_block (parameter)(rect 1040 432 1333 530))
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)
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(symbol
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(rect 1040 256 1368 368)
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(text "RAM" (rect 5 0 28 12)(font "Arial" ))
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(text "inst1" (rect 8 96 31 108)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "address[address_bus_width-1..0]" (rect 0 0 161 12)(font "Arial" ))
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(text "address[address_bus_width-1..0]" (rect 21 27 182 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 3))
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)
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(port
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(pt 0 48)
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(input)
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(text "we" (rect 0 0 12 12)(font "Arial" ))
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(text "we" (rect 21 43 33 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48))
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)
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(port
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(pt 0 64)
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(input)
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(text "oe" (rect 0 0 11 12)(font "Arial" ))
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(text "oe" (rect 21 59 32 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64))
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)
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(port
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(pt 0 80)
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(input)
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(text "ce" (rect 0 0 11 12)(font "Arial" ))
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(text "ce" (rect 21 75 32 87)(font "Arial" ))
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(line (pt 0 80)(pt 16 80))
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)
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(port
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(pt 328 32)
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(bidir)
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(text "data[data_bus_width-1..0]" (rect 0 0 126 12)(font "Arial" ))
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(text "data[data_bus_width-1..0]" (rect 208 27 334 39)(font "Arial" ))
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(line (pt 328 32)(pt 312 32)(line_width 3))
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)
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(parameter
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"DATA_BUS_WIDTH"
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"8"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"ADDRESS_BUS_WIDTH"
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"9"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(drawing
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(rectangle (rect 16 16 312 96))
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)
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(annotation_block (parameter)(rect 1040 208 1280 256))
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)
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(connector
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(pt 560 32)
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(pt 608 32)
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@ -661,11 +672,6 @@ applicable agreement for further details.
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(pt 968 256)
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(pt 968 320)
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)
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(connector
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(pt 1232 288)
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(pt 1440 288)
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(bus)
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)
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(connector
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(pt 680 240)
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(pt 680 -16)
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@ -715,19 +721,14 @@ applicable agreement for further details.
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(pt 1040 640)
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(pt 952 640)
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)
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(connector
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(pt 1368 576)
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(pt 1440 576)
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(bus)
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)
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(connector
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(pt 1440 288)
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(pt 1440 408)
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(bus)
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)
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(connector
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(pt 1440 408)
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(pt 1440 576)
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(pt 1368 288)
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(pt 1440 288)
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(bus)
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)
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(junction (pt 608 32))
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@ -736,4 +737,3 @@ applicable agreement for further details.
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(junction (pt 968 320))
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(junction (pt 952 336))
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(junction (pt 608 136))
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(junction (pt 1440 408))
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@ -121,5 +121,5 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBclk
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBdatain
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBdataout
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set_global_assignment -name VHDL_FILE DigitalFilter3.vhd
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[8]
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -20,110 +20,56 @@ applicable agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 216 224)
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(rect 16 16 344 128)
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(text "RAM" (rect 5 0 29 12)(font "Arial" ))
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(text "inst" (rect 8 192 20 204)(font "Arial" ))
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(text "inst" (rect 8 96 20 108)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "clk" (rect 0 0 10 12)(font "Arial" ))
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(text "clk" (rect 21 27 31 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 1))
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(text "address[address_bus_width-1..0]" (rect 0 0 129 12)(font "Arial" ))
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(text "address[address_bus_width-1..0]" (rect 21 27 150 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 3))
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)
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(port
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(pt 0 48)
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(input)
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(text "address0[7..0]" (rect 0 0 56 12)(font "Arial" ))
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(text "address0[7..0]" (rect 21 43 77 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 3))
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(text "we" (rect 0 0 10 12)(font "Arial" ))
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(text "we" (rect 21 43 31 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 1))
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)
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(port
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(pt 0 64)
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(input)
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(text "we0" (rect 0 0 15 12)(font "Arial" ))
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(text "we0" (rect 21 59 36 71)(font "Arial" ))
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(text "oe" (rect 0 0 9 12)(font "Arial" ))
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(text "oe" (rect 21 59 30 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64)(line_width 1))
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)
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(port
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(pt 0 80)
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(input)
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(text "oe0" (rect 0 0 14 12)(font "Arial" ))
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(text "oe0" (rect 21 75 35 87)(font "Arial" ))
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(text "ce" (rect 0 0 9 12)(font "Arial" ))
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(text "ce" (rect 21 75 30 87)(font "Arial" ))
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(line (pt 0 80)(pt 16 80)(line_width 1))
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)
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(port
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(pt 0 96)
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(input)
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(text "ce0" (rect 0 0 14 12)(font "Arial" ))
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(text "ce0" (rect 21 91 35 103)(font "Arial" ))
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(line (pt 0 96)(pt 16 96)(line_width 1))
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)
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(port
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(pt 0 112)
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(input)
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(text "bl0[1..0]" (rect 0 0 29 12)(font "Arial" ))
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(text "bl0[1..0]" (rect 21 107 50 119)(font "Arial" ))
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(line (pt 0 112)(pt 16 112)(line_width 3))
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)
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(port
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(pt 0 128)
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(input)
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(text "address1[7..0]" (rect 0 0 55 12)(font "Arial" ))
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(text "address1[7..0]" (rect 21 123 76 135)(font "Arial" ))
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(line (pt 0 128)(pt 16 128)(line_width 3))
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)
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(port
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(pt 0 144)
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(input)
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(text "we1" (rect 0 0 14 12)(font "Arial" ))
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(text "we1" (rect 21 139 35 151)(font "Arial" ))
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(line (pt 0 144)(pt 16 144)(line_width 1))
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)
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(port
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(pt 0 160)
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(input)
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(text "oe1" (rect 0 0 12 12)(font "Arial" ))
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(text "oe1" (rect 21 155 33 167)(font "Arial" ))
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(line (pt 0 160)(pt 16 160)(line_width 1))
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)
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(port
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(pt 0 176)
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(input)
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(text "ce1" (rect 0 0 12 12)(font "Arial" ))
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(text "ce1" (rect 21 171 33 183)(font "Arial" ))
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(line (pt 0 176)(pt 16 176)(line_width 1))
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)
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(port
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(pt 200 32)
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(pt 328 32)
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(bidir)
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(text "data0[7..0]" (rect 0 0 41 12)(font "Arial" ))
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(text "data0[7..0]" (rect 138 27 179 39)(font "Arial" ))
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(line (pt 200 32)(pt 184 32)(line_width 3))
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)
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(port
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(pt 200 48)
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(bidir)
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(text "data1[31..0]" (rect 0 0 43 12)(font "Arial" ))
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(text "data1[31..0]" (rect 136 43 179 55)(font "Arial" ))
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(line (pt 200 48)(pt 184 48)(line_width 3))
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(text "data[data_bus_width-1..0]" (rect 0 0 99 12)(font "Arial" ))
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(text "data[data_bus_width-1..0]" (rect 208 27 307 39)(font "Arial" ))
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(line (pt 328 32)(pt 312 32)(line_width 3))
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)
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(parameter
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"REG_ADDR_FIRST"
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"0"
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"DATA_BUS_WIDTH"
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"8"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"REG_ADDR_LAST"
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"16"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"TEST"
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"5"
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"ADDRESS_BUS_WIDTH"
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"9"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(drawing
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(rectangle (rect 16 16 184 192)(line_width 1))
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(rectangle (rect 16 16 312 96)(line_width 1))
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)
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(annotation_block (parameter)(rect 216 -64 316 16))
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(annotation_block (parameter)(rect 344 -64 444 16))
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)
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@ -2,178 +2,44 @@ library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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-- Блок памяти (8х32) способен принимать данные с двух устройств одновременно;
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-- Со стороны контроллера - постфикс "0" - данные грузятся в ячейку памяти четырьмя транзакциями, поскольку шина данных здесь всего 8 бит;
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-- Со стороны ПЛИС - постфикс "1" - данные грузятся за одну транзакцию (шина данных 32х разрядная);
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-- Для работы с контроллером дополнительно введены два бита BL для определения с какой частью ячейки памяти работаем;
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-- Когда в комментариях говорю "со стороны ПЛИС" - это значит, что есть IP блок диспетчеризации,
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-- который получает свежайшие данные от остальных IP блоков на ПЛИС, создает приоритетную очередь и грузит эти данные в ячейки памяти;
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entity RAM is
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generic(
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REG_ADDR_FIRST : integer := 0;
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REG_ADDR_LAST : integer := 16;
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TEST : integer := 5
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);
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DATA_BUS_WIDTH : integer := 8;
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ADDRESS_BUS_WIDTH : integer := 9
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);
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port(
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clk : in std_logic;
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data0 : inout std_logic_vector(7 downto 0);
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address0 : in std_logic_vector(7 downto 0);
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we0 : in std_logic;
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oe0 : in std_logic;
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ce0 : in std_logic;
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bl0 : in std_logic_vector(1 downto 0);
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data1 : inout std_logic_vector(31 downto 0);
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address1 : in std_logic_vector(7 downto 0);
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we1 : in std_logic;
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oe1 : in std_logic;
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ce1 : in std_logic
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data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
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we : in std_logic;
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oe : in std_logic;
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ce : in std_logic
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);
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end entity;
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architecture behavorial of RAM is
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type mem is array (255 downto 0) of std_logic_vector(31 downto 0);
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type mem is array (2**ADDRESS_BUS_WIDTH - 1 downto 0) of std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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signal memory : mem;
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signal we0Prev : std_logic := '0';
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signal oe0Prev : std_logic := '0';
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signal ce0Prev : std_logic := '0';
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signal we1Prev : std_logic := '0';
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signal oe1Prev : std_logic := '0';
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signal ce1Prev : std_logic := '0';
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type MemoryMachine is (Waiting, Writing, Reading);
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signal stateMM0 : MemoryMachine := Waiting;
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signal stateMM1 : MemoryMachine := Waiting;
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begin
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process(clk)
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variable addr0 : integer range 0 to 255 := 0;
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variable part0 : integer range 0 to 3 := 0;
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variable addr1 : integer range 0 to 255 := 0;
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process (we, oe, ce)
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variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
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begin
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if rising_edge(clk) then
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case stateMM0 is
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when Waiting =>
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if ce0 = '0' and ce0Prev = '1' then
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addr0 := conv_integer(address0);
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part0 := conv_integer(bl0);
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if oe0 = '0' then -- этот if можно перенести на следующий такт, чтобы успела установиться ножка output enable
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stateMM0 <= Reading;
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else
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stateMM0 <= Writing;
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end if;
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else
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data0 <= (others => 'Z');
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end if;
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when Reading =>
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data0 <= memory(addr0)(7 + part0*8 downto part0*8);
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if oe0 = '1' and oe0Prev = '0' then
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stateMM0 <= Waiting;
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elsif ce0 = '1' then
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stateMM0 <= Waiting;
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end if;
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when Writing =>
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if we0 = '0' and we0Prev = '1' then
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memory(addr0)(7 + part0*8 downto part0*8) <= data0;
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stateMM0 <= Waiting;
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elsif ce0 = '1' then
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stateMM0 <= Waiting;
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end if;
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when others =>
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end case;
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oe0Prev <= oe0;
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ce0Prev <= ce0;
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we0Prev <= we0;
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case stateMM1 is
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when Waiting =>
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if ce1 = '0' and ce1Prev = '1' then
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addr1 := conv_integer(address1);
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if oe1 = '0' then -- этот if можно перенести на следующий такт, чтобы успела установиться ножка output enable
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stateMM1 <= Reading;
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else
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stateMM1 <= Writing;
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end if;
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else
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data1 <= (others => 'Z');
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end if;
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when Reading =>
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data1 <= memory(addr1);
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if oe1 = '1' and oe1Prev = '0' then
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stateMM1 <= Waiting;
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elsif ce0 = '1' then
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stateMM1 <= Waiting;
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end if;
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when Writing =>
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if we1 = '0' and we1Prev = '1' then
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memory(addr1) <= data1;
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stateMM1 <= Waiting;
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elsif ce0 = '1' then
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stateMM1 <= Waiting;
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end if;
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when others =>
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end case;
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oe1Prev <= oe1;
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ce1Prev <= ce1;
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we1Prev <= we1;
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memory(0) <= x"AABBCCDD";
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memory(1) <= x"EEFF0011";
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memory(2) <= x"22334455";
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memory(3) <= x"66778899";
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memory(4) <= x"EEFF0011";
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memory(5) <= x"AAAAAAAA";
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memory(6) <= x"55555555";
|
||||
memory(7) <= x"BBBBBBBB";
|
||||
memory(8) <= x"66666666";
|
||||
memory(9) <= memory(9) + 1;
|
||||
if (ce = '0') then -- Если микросхема выбрана
|
||||
addr := conv_integer(address);
|
||||
if (oe = '0') then -- Если сигнал чтения активен
|
||||
data <= memory(addr);
|
||||
elsif (we = '0') then -- Если сигнал записи активен
|
||||
memory(addr) <= data;
|
||||
else
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end if;
|
||||
else
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- process(clk)
|
||||
-- variable addr : integer range 0 to 255;
|
||||
-- begin
|
||||
-- if rising_edge(clk) then
|
||||
-- if clk = '1' and clkPrev = '0' then
|
||||
-- addr := conv_integer(address1); -- переменной addr1 присваивается новое значение сразу. Удобно для преобразования типов.
|
||||
-- if (wr1 = '0') then
|
||||
-- memory(addr1) <= data1; -- тут уже новое значение переменной addr1
|
||||
-- else
|
||||
-- data1 <= memory(addr1);
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- if clk1 = '0' and clk1Prev = '1' then
|
||||
-- data1 <= (others => 'Z');
|
||||
-- end if;
|
||||
--
|
||||
-- clk1Prev <= clk1;
|
||||
--
|
||||
-- if clk0 = '1' and clk0Prev = '0' then
|
||||
-- addr0 := conv_integer(address0); -- переменной addr0 присваивается новое значение сразу. Удобно для преобразования типов.
|
||||
-- if (wr0 = '0') then
|
||||
-- memory(addr0) <= data0; -- тут уже новое значение переменной addr0
|
||||
-- else
|
||||
-- data0 <= memory(addr0);
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- if clk0 = '0' and clk0Prev = '1' then
|
||||
-- data0 <= (others => 'Z');
|
||||
-- end if;
|
||||
--
|
||||
-- clk0Prev <= clk0;
|
||||
--
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
end behavorial;
|
||||
Loading…
Reference in New Issue
Block a user