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Заменил RAM9X8 на расширяемый с помощью параметров RAM.

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sokolovstanislav 2024-03-26 10:23:20 +03:00
parent f3a7b565e4
commit 5fba6ce8b4
4 changed files with 108 additions and 296 deletions
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112
MainController/MainController.bdf
View File

@ -395,49 +395,6 @@ applicable agreement for further details.
(rectangle (rect 16 16 216 112)) (rectangle (rect 16 16 216 112))
) )
) )
(symbol
(rect 1040 256 1232 368)
(text "RAM9X8" (rect 5 0 46 12)(font "Arial" ))
(text "inst13" (rect 8 96 37 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "address[8..0]" (rect 0 0 64 12)(font "Arial" ))
(text "address[8..0]" (rect 21 27 85 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "we" (rect 0 0 12 12)(font "Arial" ))
(text "we" (rect 21 43 33 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "oe" (rect 0 0 11 12)(font "Arial" ))
(text "oe" (rect 21 59 32 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "ce" (rect 0 0 11 12)(font "Arial" ))
(text "ce" (rect 21 75 32 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 192 32)
(bidir)
(text "data[7..0]" (rect 0 0 47 12)(font "Arial" ))
(text "data[7..0]" (rect 135 27 182 39)(font "Arial" ))
(line (pt 192 32)(pt 176 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 176 96))
)
)
(symbol (symbol
(rect 1040 544 1368 688) (rect 1040 544 1368 688)
(text "RAM9X8_SerialBusMaster" (rect 5 0 131 12)(font "Arial" )) (text "RAM9X8_SerialBusMaster" (rect 5 0 131 12)(font "Arial" ))
@ -540,6 +497,60 @@ applicable agreement for further details.
) )
(annotation_block (parameter)(rect 1040 432 1333 530)) (annotation_block (parameter)(rect 1040 432 1333 530))
) )
(symbol
(rect 1040 256 1368 368)
(text "RAM" (rect 5 0 28 12)(font "Arial" ))
(text "inst1" (rect 8 96 31 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "address[address_bus_width-1..0]" (rect 0 0 161 12)(font "Arial" ))
(text "address[address_bus_width-1..0]" (rect 21 27 182 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "we" (rect 0 0 12 12)(font "Arial" ))
(text "we" (rect 21 43 33 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "oe" (rect 0 0 11 12)(font "Arial" ))
(text "oe" (rect 21 59 32 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "ce" (rect 0 0 11 12)(font "Arial" ))
(text "ce" (rect 21 75 32 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 328 32)
(bidir)
(text "data[data_bus_width-1..0]" (rect 0 0 126 12)(font "Arial" ))
(text "data[data_bus_width-1..0]" (rect 208 27 334 39)(font "Arial" ))
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"DATA_BUS_WIDTH"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"ADDRESS_BUS_WIDTH"
"9"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 312 96))
)
(annotation_block (parameter)(rect 1040 208 1280 256))
)
(connector (connector
(pt 560 32) (pt 560 32)
(pt 608 32) (pt 608 32)
@ -661,11 +672,6 @@ applicable agreement for further details.
(pt 968 256) (pt 968 256)
(pt 968 320) (pt 968 320)
) )
(connector
(pt 1232 288)
(pt 1440 288)
(bus)
)
(connector (connector
(pt 680 240) (pt 680 240)
(pt 680 -16) (pt 680 -16)
@ -715,19 +721,14 @@ applicable agreement for further details.
(pt 1040 640) (pt 1040 640)
(pt 952 640) (pt 952 640)
) )
(connector
(pt 1368 576)
(pt 1440 576)
(bus)
)
(connector (connector
(pt 1440 288) (pt 1440 288)
(pt 1440 408) (pt 1440 408)
(bus) (bus)
) )
(connector (connector
(pt 1440 408) (pt 1368 288)
(pt 1440 576) (pt 1440 288)
(bus) (bus)
) )
(junction (pt 608 32)) (junction (pt 608 32))
@ -736,4 +737,3 @@ applicable agreement for further details.
(junction (pt 968 320)) (junction (pt 968 320))
(junction (pt 952 336)) (junction (pt 952 336))
(junction (pt 608 136)) (junction (pt 608 136))
(junction (pt 1440 408))

2
MainController/MainController.qsf
View File

@ -121,5 +121,5 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBclk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBdatain set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBdatain
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBdataout set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBdataout
set_global_assignment -name VHDL_FILE DigitalFilter3.vhd set_global_assignment -name VHDL_FILE DigitalFilter3.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[8] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[8]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

98
MainController/RAM.bsf
View File

@ -20,110 +20,56 @@ applicable agreement for further details.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.1"))
(symbol (symbol
(rect 16 16 216 224) (rect 16 16 344 128)
(text "RAM" (rect 5 0 29 12)(font "Arial" )) (text "RAM" (rect 5 0 29 12)(font "Arial" ))
(text "inst" (rect 8 192 20 204)(font "Arial" )) (text "inst" (rect 8 96 20 108)(font "Arial" ))
(port (port
(pt 0 32) (pt 0 32)
(input) (input)
(text "clk" (rect 0 0 10 12)(font "Arial" )) (text "address[address_bus_width-1..0]" (rect 0 0 129 12)(font "Arial" ))
(text "clk" (rect 21 27 31 39)(font "Arial" )) (text "address[address_bus_width-1..0]" (rect 21 27 150 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1)) (line (pt 0 32)(pt 16 32)(line_width 3))
) )
(port (port
(pt 0 48) (pt 0 48)
(input) (input)
(text "address0[7..0]" (rect 0 0 56 12)(font "Arial" )) (text "we" (rect 0 0 10 12)(font "Arial" ))
(text "address0[7..0]" (rect 21 43 77 55)(font "Arial" )) (text "we" (rect 21 43 31 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3)) (line (pt 0 48)(pt 16 48)(line_width 1))
) )
(port (port
(pt 0 64) (pt 0 64)
(input) (input)
(text "we0" (rect 0 0 15 12)(font "Arial" )) (text "oe" (rect 0 0 9 12)(font "Arial" ))
(text "we0" (rect 21 59 36 71)(font "Arial" )) (text "oe" (rect 21 59 30 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1)) (line (pt 0 64)(pt 16 64)(line_width 1))
) )
(port (port
(pt 0 80) (pt 0 80)
(input) (input)
(text "oe0" (rect 0 0 14 12)(font "Arial" )) (text "ce" (rect 0 0 9 12)(font "Arial" ))
(text "oe0" (rect 21 75 35 87)(font "Arial" )) (text "ce" (rect 21 75 30 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1)) (line (pt 0 80)(pt 16 80)(line_width 1))
) )
(port (port
(pt 0 96) (pt 328 32)
(input)
(text "ce0" (rect 0 0 14 12)(font "Arial" ))
(text "ce0" (rect 21 91 35 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "bl0[1..0]" (rect 0 0 29 12)(font "Arial" ))
(text "bl0[1..0]" (rect 21 107 50 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 3))
)
(port
(pt 0 128)
(input)
(text "address1[7..0]" (rect 0 0 55 12)(font "Arial" ))
(text "address1[7..0]" (rect 21 123 76 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128)(line_width 3))
)
(port
(pt 0 144)
(input)
(text "we1" (rect 0 0 14 12)(font "Arial" ))
(text "we1" (rect 21 139 35 151)(font "Arial" ))
(line (pt 0 144)(pt 16 144)(line_width 1))
)
(port
(pt 0 160)
(input)
(text "oe1" (rect 0 0 12 12)(font "Arial" ))
(text "oe1" (rect 21 155 33 167)(font "Arial" ))
(line (pt 0 160)(pt 16 160)(line_width 1))
)
(port
(pt 0 176)
(input)
(text "ce1" (rect 0 0 12 12)(font "Arial" ))
(text "ce1" (rect 21 171 33 183)(font "Arial" ))
(line (pt 0 176)(pt 16 176)(line_width 1))
)
(port
(pt 200 32)
(bidir) (bidir)
(text "data0[7..0]" (rect 0 0 41 12)(font "Arial" )) (text "data[data_bus_width-1..0]" (rect 0 0 99 12)(font "Arial" ))
(text "data0[7..0]" (rect 138 27 179 39)(font "Arial" )) (text "data[data_bus_width-1..0]" (rect 208 27 307 39)(font "Arial" ))
(line (pt 200 32)(pt 184 32)(line_width 3)) (line (pt 328 32)(pt 312 32)(line_width 3))
)
(port
(pt 200 48)
(bidir)
(text "data1[31..0]" (rect 0 0 43 12)(font "Arial" ))
(text "data1[31..0]" (rect 136 43 179 55)(font "Arial" ))
(line (pt 200 48)(pt 184 48)(line_width 3))
) )
(parameter (parameter
"REG_ADDR_FIRST" "DATA_BUS_WIDTH"
"0" "8"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter
"REG_ADDR_LAST" "ADDRESS_BUS_WIDTH"
"16" "9"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"TEST"
"5"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(drawing (drawing
(rectangle (rect 16 16 184 192)(line_width 1)) (rectangle (rect 16 16 312 96)(line_width 1))
) )
(annotation_block (parameter)(rect 216 -64 316 16)) (annotation_block (parameter)(rect 344 -64 444 16))
) )

172
MainController/RAM.vhd
View File

@ -2,178 +2,44 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;
-- Блок памяти (8х32) способен принимать данные с двух устройств одновременно;
-- Со стороны контроллера - постфикс "0" - данные грузятся в ячейку памяти четырьмя транзакциями, поскольку шина данных здесь всего 8 бит;
-- Со стороны ПЛИС - постфикс "1" - данные грузятся за одну транзакцию (шина данных 32х разрядная);
-- Для работы с контроллером дополнительно введены два бита BL для определения с какой частью ячейки памяти работаем;
-- Когда в комментариях говорю "со стороны ПЛИС" - это значит, что есть IP блок диспетчеризации,
-- который получает свежайшие данные от остальных IP блоков на ПЛИС, создает приоритетную очередь и грузит эти данные в ячейки памяти;
entity RAM is entity RAM is
generic( generic(
REG_ADDR_FIRST : integer := 0; DATA_BUS_WIDTH : integer := 8;
REG_ADDR_LAST : integer := 16; ADDRESS_BUS_WIDTH : integer := 9
TEST : integer := 5
); );
port( port(
clk : in std_logic; data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
data0 : inout std_logic_vector(7 downto 0); we : in std_logic;
address0 : in std_logic_vector(7 downto 0); oe : in std_logic;
we0 : in std_logic; ce : in std_logic
oe0 : in std_logic;
ce0 : in std_logic;
bl0 : in std_logic_vector(1 downto 0);
data1 : inout std_logic_vector(31 downto 0);
address1 : in std_logic_vector(7 downto 0);
we1 : in std_logic;
oe1 : in std_logic;
ce1 : in std_logic
); );
end entity; end entity;
architecture behavorial of RAM is architecture behavorial of RAM is
type mem is array (255 downto 0) of std_logic_vector(31 downto 0); type mem is array (2**ADDRESS_BUS_WIDTH - 1 downto 0) of std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
signal memory : mem; signal memory : mem;
signal we0Prev : std_logic := '0';
signal oe0Prev : std_logic := '0';
signal ce0Prev : std_logic := '0';
signal we1Prev : std_logic := '0';
signal oe1Prev : std_logic := '0';
signal ce1Prev : std_logic := '0';
type MemoryMachine is (Waiting, Writing, Reading);
signal stateMM0 : MemoryMachine := Waiting;
signal stateMM1 : MemoryMachine := Waiting;
begin begin
process(clk) process (we, oe, ce)
variable addr0 : integer range 0 to 255 := 0; variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
variable part0 : integer range 0 to 3 := 0;
variable addr1 : integer range 0 to 255 := 0;
begin begin
if rising_edge(clk) then if (ce = '0') then -- Если микросхема выбрана
case stateMM0 is addr := conv_integer(address);
when Waiting => if (oe = '0') then -- Если сигнал чтения активен
if ce0 = '0' and ce0Prev = '1' then data <= memory(addr);
addr0 := conv_integer(address0); elsif (we = '0') then -- Если сигнал записи активен
part0 := conv_integer(bl0); memory(addr) <= data;
if oe0 = '0' then -- этот if можно перенести на следующий такт, чтобы успела установиться ножка output enable
stateMM0 <= Reading;
else else
stateMM0 <= Writing; data <= (others => 'Z'); -- Запретить запись на шину
end if; end if;
else else
data0 <= (others => 'Z'); data <= (others => 'Z'); -- Запретить запись на шину
end if;
when Reading =>
data0 <= memory(addr0)(7 + part0*8 downto part0*8);
if oe0 = '1' and oe0Prev = '0' then
stateMM0 <= Waiting;
elsif ce0 = '1' then
stateMM0 <= Waiting;
end if;
when Writing =>
if we0 = '0' and we0Prev = '1' then
memory(addr0)(7 + part0*8 downto part0*8) <= data0;
stateMM0 <= Waiting;
elsif ce0 = '1' then
stateMM0 <= Waiting;
end if;
when others =>
end case;
oe0Prev <= oe0;
ce0Prev <= ce0;
we0Prev <= we0;
case stateMM1 is
when Waiting =>
if ce1 = '0' and ce1Prev = '1' then
addr1 := conv_integer(address1);
if oe1 = '0' then -- этот if можно перенести на следующий такт, чтобы успела установиться ножка output enable
stateMM1 <= Reading;
else
stateMM1 <= Writing;
end if;
else
data1 <= (others => 'Z');
end if;
when Reading =>
data1 <= memory(addr1);
if oe1 = '1' and oe1Prev = '0' then
stateMM1 <= Waiting;
elsif ce0 = '1' then
stateMM1 <= Waiting;
end if;
when Writing =>
if we1 = '0' and we1Prev = '1' then
memory(addr1) <= data1;
stateMM1 <= Waiting;
elsif ce0 = '1' then
stateMM1 <= Waiting;
end if;
when others =>
end case;
oe1Prev <= oe1;
ce1Prev <= ce1;
we1Prev <= we1;
memory(0) <= x"AABBCCDD";
memory(1) <= x"EEFF0011";
memory(2) <= x"22334455";
memory(3) <= x"66778899";
memory(4) <= x"EEFF0011";
memory(5) <= x"AAAAAAAA";
memory(6) <= x"55555555";
memory(7) <= x"BBBBBBBB";
memory(8) <= x"66666666";
memory(9) <= memory(9) + 1;
end if; end if;
end process; end process;
-- process(clk)
-- variable addr : integer range 0 to 255;
-- begin
-- if rising_edge(clk) then
-- if clk = '1' and clkPrev = '0' then
-- addr := conv_integer(address1); -- переменной addr1 присваивается новое значение сразу. Удобно для преобразования типов.
-- if (wr1 = '0') then
-- memory(addr1) <= data1; -- тут уже новое значение переменной addr1
-- else
-- data1 <= memory(addr1);
-- end if;
-- end if;
-- if clk1 = '0' and clk1Prev = '1' then
-- data1 <= (others => 'Z');
-- end if;
--
-- clk1Prev <= clk1;
--
-- if clk0 = '1' and clk0Prev = '0' then
-- addr0 := conv_integer(address0); -- переменной addr0 присваивается новое значение сразу. Удобно для преобразования типов.
-- if (wr0 = '0') then
-- memory(addr0) <= data0; -- тут уже новое значение переменной addr0
-- else
-- data0 <= memory(addr0);
-- end if;
-- end if;
-- if clk0 = '0' and clk0Prev = '1' then
-- data0 <= (others => 'Z');
-- end if;
--
-- clk0Prev <= clk0;
--
-- end if;
-- end process;
end behavorial; end behavorial;