Тактовый сигнал, который распространяется по всему проекту, берется с блока PLL. Он умножен на 4 от значения частоты на соответствующей ножке ПЛИС и теперь все модули внутри ПЛИС работают на частоте 100МГц . Так гарантировано получаем один и тот же синхросигнал во всей схеме. Из книжки ПЛИС Xilinx Тарасова И. Е.;

This commit is contained in:
sokolovstanislav 2024-10-21 18:27:29 +03:00
parent dfe22a8ab2
commit 5de2386bb5

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@ -21,7 +21,7 @@ applicable agreement for further details.
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@ -34,7 +34,7 @@ applicable agreement for further details.
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@ -2796,10 +2796,6 @@ applicable agreement for further details.
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@ -2816,18 +2812,6 @@ applicable agreement for further details.
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@ -3064,18 +3048,6 @@ applicable agreement for further details.
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@ -3112,6 +3084,34 @@ applicable agreement for further details.
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