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Начали тестирование параллельной шины. Для контроля счетчика полного круга работы с адресным пространством шины добавили новый регистр. Проект при этом изменился - теперь в каждом блоке есть базовый регистр, от которого начинаем считать остальные.

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This commit is contained in:
sokolovstanislav 2024-06-11 16:21:14 +03:00
parent cd65199ea6
commit 0b80c8a3d2
16 changed files with 131 additions and 458 deletions
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37
MainController/RAM9X8_HWPBusMaster.bsf
View File

@ -87,45 +87,10 @@ applicable agreement for further details.
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"HWP_CMD_2_LOWER"
"46"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"HWP_CMD_2_UPPER"
"47"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"HWP_CMD_1_LOWER"
"HWP_BASE_ADDRESS"
"48"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"HWP_CMD_1_UPPER"
"49"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"HWP_DATA_2_LOWER"
"50"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"HWP_DATA_2_UPPER"
"51"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"HWP_DATA_1_LOWER"
"52"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"HWP_DATA_1_UPPER"
"53"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DATA_BUS_WIDTH"
"8"

18
MainController/RAM9X8_HWPBusMaster.vhd
View File

@ -5,14 +5,7 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8_HWPBusMaster is
generic(
HWP_CMD_2_LOWER : integer := 46;
HWP_CMD_2_UPPER : integer := 47;
HWP_CMD_1_LOWER : integer := 48;
HWP_CMD_1_UPPER : integer := 49;
HWP_DATA_2_LOWER : integer := 50;
HWP_DATA_2_UPPER : integer := 51;
HWP_DATA_1_LOWER : integer := 52;
HWP_DATA_1_UPPER : integer := 53;
HWP_BASE_ADDRESS : integer := 48;
DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9
@ -35,6 +28,15 @@ end entity;
architecture behavorial of RAM9X8_HWPBusMaster is
signal HWP_CMD_2_LOWER : integer := HWP_BASE_ADDRESS;
signal HWP_CMD_2_UPPER : integer := HWP_BASE_ADDRESS + 1;
signal HWP_CMD_1_LOWER : integer := HWP_BASE_ADDRESS + 2;
signal HWP_CMD_1_UPPER : integer := HWP_BASE_ADDRESS + 3;
signal HWP_DATA_2_LOWER : integer := HWP_BASE_ADDRESS + 4;
signal HWP_DATA_2_UPPER : integer := HWP_BASE_ADDRESS + 5;
signal HWP_DATA_1_LOWER : integer := HWP_BASE_ADDRESS + 6;
signal HWP_DATA_1_UPPER : integer := HWP_BASE_ADDRESS + 7;
signal cmdBuf : std_logic_vector(31 downto 0) := (others => '0');
signal dataBuf : std_logic_vector(31 downto 0) := (others => '0');
signal tempBuf : std_logic_vector(31 downto 0) := (others => '0');

9
MainController/RAM9X8_Loader.bsf
View File

@ -143,13 +143,8 @@ applicable agreement for further details.
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"LD_LOADER_LOWER"
"44"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"LD_LOADER_UPPER"
"45"
"LD_BASE_ADDRESS"
"46"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter

6
MainController/RAM9X8_Loader.vhd
View File

@ -5,8 +5,7 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8_Loader is
generic(
LD_LOADER_LOWER : integer := 44;
LD_LOADER_UPPER : integer := 45;
LD_BASE_ADDRESS : integer := 46;
DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9
@ -38,6 +37,9 @@ end entity;
architecture behavorial of RAM9X8_Loader is
signal LD_LOADER_LOWER : integer := LD_BASE_ADDRESS;
signal LD_LOADER_UPPER : integer := LD_BASE_ADDRESS + 1;
signal loaderBuf : std_logic_vector(15 downto 0) := (others => '1');
signal sel : std_logic := '0';

87
MainController/RAM9X8_OpticalBusMaster.bsf
View File

@ -80,95 +80,10 @@ applicable agreement for further details.
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"OB_CMD_LOWER"
"54"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_CMD_UPPER"
"55"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_8_LOWER"
"OB_BASE_ADDRESS"
"56"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_8_UPPER"
"57"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_7_LOWER"
"58"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_7_UPPER"
"59"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_6_LOWER"
"60"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_6_UPPER"
"61"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_5_LOWER"
"62"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_5_UPPER"
"63"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_4_LOWER"
"64"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_4_UPPER"
"65"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_3_LOWER"
"66"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_3_UPPER"
"67"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_2_LOWER"
"68"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_2_UPPER"
"69"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_1_LOWER"
"70"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"OB_WORD_1_UPPER"
"71"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DATA_BUS_WIDTH"
"8"

38
MainController/RAM9X8_OpticalBusMaster.vhd
View File

@ -5,24 +5,7 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8_OpticalBusMaster is
generic(
OB_CMD_LOWER : integer := 54;
OB_CMD_UPPER : integer := 55;
OB_WORD_8_LOWER : integer := 56;
OB_WORD_8_UPPER : integer := 57;
OB_WORD_7_LOWER : integer := 58;
OB_WORD_7_UPPER : integer := 59;
OB_WORD_6_LOWER : integer := 60;
OB_WORD_6_UPPER : integer := 61;
OB_WORD_5_LOWER : integer := 62;
OB_WORD_5_UPPER : integer := 63;
OB_WORD_4_LOWER : integer := 64;
OB_WORD_4_UPPER : integer := 65;
OB_WORD_3_LOWER : integer := 66;
OB_WORD_3_UPPER : integer := 67;
OB_WORD_2_LOWER : integer := 68;
OB_WORD_2_UPPER : integer := 69;
OB_WORD_1_LOWER : integer := 70;
OB_WORD_1_UPPER : integer := 71;
OB_BASE_ADDRESS : integer := 56;
DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9
@ -44,6 +27,25 @@ end entity;
architecture behavorial of RAM9X8_OpticalBusMaster is
signal OB_CMD_LOWER : integer := OB_BASE_ADDRESS;
signal OB_CMD_UPPER : integer := OB_BASE_ADDRESS + 1;
signal OB_WORD_8_LOWER : integer := OB_BASE_ADDRESS + 2;
signal OB_WORD_8_UPPER : integer := OB_BASE_ADDRESS + 3;
signal OB_WORD_7_LOWER : integer := OB_BASE_ADDRESS + 4;
signal OB_WORD_7_UPPER : integer := OB_BASE_ADDRESS + 5;
signal OB_WORD_6_LOWER : integer := OB_BASE_ADDRESS + 6;
signal OB_WORD_6_UPPER : integer := OB_BASE_ADDRESS + 7;
signal OB_WORD_5_LOWER : integer := OB_BASE_ADDRESS + 8;
signal OB_WORD_5_UPPER : integer := OB_BASE_ADDRESS + 9;
signal OB_WORD_4_LOWER : integer := OB_BASE_ADDRESS + 10;
signal OB_WORD_4_UPPER : integer := OB_BASE_ADDRESS + 11;
signal OB_WORD_3_LOWER : integer := OB_BASE_ADDRESS + 12;
signal OB_WORD_3_UPPER : integer := OB_BASE_ADDRESS + 13;
signal OB_WORD_2_LOWER : integer := OB_BASE_ADDRESS + 14;
signal OB_WORD_2_UPPER : integer := OB_BASE_ADDRESS + 15;
signal OB_WORD_1_LOWER : integer := OB_BASE_ADDRESS + 16;
signal OB_WORD_1_UPPER : integer := OB_BASE_ADDRESS + 17;
signal dataBuf : std_logic_vector(127 downto 0) := (others => '0');
signal dataToSend : std_logic_vector(127 downto 0) := (others => '0');
signal cmdBuf : std_logic_vector(15 downto 0) := x"0004";

117
MainController/RAM9X8_PWM.bsf
View File

@ -94,125 +94,10 @@ applicable agreement for further details.
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"PWM_MODE_CONTROL_LOWER"
"14"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_MODE_CONTROL_UPPER"
"15"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_MASK_2_LOWER"
"PWM_BASE_ADDRESS"
"16"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_MASK_2_UPPER"
"17"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_MASK_1_LOWER"
"18"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_MASK_1_UPPER"
"19"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_DIRECT_CONTROL_2_LOWER"
"20"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_DIRECT_CONTROL_2_UPPER"
"21"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_DIRECT_CONTROL_1_LOWER"
"22"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_DIRECT_CONTROL_1_UPPER"
"23"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_PERIOD_LOWER"
"24"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_PERIOD_UPPER"
"25"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_DIRECTION_2_LOWER"
"26"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_DIRECTION_2_UPPER"
"27"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_DIRECTION_1_LOWER"
"28"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_DIRECTION_1_UPPER"
"29"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_CHANNEL_LOWER"
"30"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_CHANNEL_UPPER"
"31"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_TIMING_LOWER"
"32"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_TIMING_UPPER"
"33"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_CMD_LOWER"
"34"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_CMD_UPPER"
"35"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_CONTROL_LOWER"
"36"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PWM_CONTROL_UPPER"
"37"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DATA_BUS_WIDTH"
"8"

50
MainController/RAM9X8_PWM.vhd
View File

@ -5,30 +5,7 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8_PWM is
generic(
PWM_MODE_CONTROL_LOWER : integer := 14;
PWM_MODE_CONTROL_UPPER : integer := 15;
PWM_MASK_2_LOWER : integer := 16;
PWM_MASK_2_UPPER : integer := 17;
PWM_MASK_1_LOWER : integer := 18;
PWM_MASK_1_UPPER : integer := 19;
PWM_DIRECT_CONTROL_2_LOWER : integer := 20;
PWM_DIRECT_CONTROL_2_UPPER : integer := 21;
PWM_DIRECT_CONTROL_1_LOWER : integer := 22;
PWM_DIRECT_CONTROL_1_UPPER : integer := 23;
PWM_PERIOD_LOWER : integer := 24;
PWM_PERIOD_UPPER : integer := 25;
PWM_DIRECTION_2_LOWER : integer := 26;
PWM_DIRECTION_2_UPPER : integer := 27;
PWM_DIRECTION_1_LOWER : integer := 28;
PWM_DIRECTION_1_UPPER : integer := 29;
PWM_CHANNEL_LOWER : integer := 30;
PWM_CHANNEL_UPPER : integer := 31;
PWM_TIMING_LOWER : integer := 32;
PWM_TIMING_UPPER : integer := 33;
PWM_CMD_LOWER : integer := 34;
PWM_CMD_UPPER : integer := 35;
PWM_CONTROL_LOWER : integer := 36;
PWM_CONTROL_UPPER : integer := 37;
PWM_BASE_ADDRESS : integer := 16;
DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9
@ -52,6 +29,31 @@ end entity;
architecture behavorial of RAM9X8_PWM is
signal PWM_MODE_CONTROL_LOWER : integer := PWM_BASE_ADDRESS;
signal PWM_MODE_CONTROL_UPPER : integer := PWM_BASE_ADDRESS + 1;
signal PWM_MASK_2_LOWER : integer := PWM_BASE_ADDRESS + 2;
signal PWM_MASK_2_UPPER : integer := PWM_BASE_ADDRESS + 3;
signal PWM_MASK_1_LOWER : integer := PWM_BASE_ADDRESS + 4;
signal PWM_MASK_1_UPPER : integer := PWM_BASE_ADDRESS + 5;
signal PWM_DIRECT_CONTROL_2_LOWER : integer := PWM_BASE_ADDRESS + 6;
signal PWM_DIRECT_CONTROL_2_UPPER : integer := PWM_BASE_ADDRESS + 7;
signal PWM_DIRECT_CONTROL_1_LOWER : integer := PWM_BASE_ADDRESS + 8;
signal PWM_DIRECT_CONTROL_1_UPPER : integer := PWM_BASE_ADDRESS + 9;
signal PWM_PERIOD_LOWER : integer := PWM_BASE_ADDRESS + 10;
signal PWM_PERIOD_UPPER : integer := PWM_BASE_ADDRESS + 11;
signal PWM_DIRECTION_2_LOWER : integer := PWM_BASE_ADDRESS + 12;
signal PWM_DIRECTION_2_UPPER : integer := PWM_BASE_ADDRESS + 13;
signal PWM_DIRECTION_1_LOWER : integer := PWM_BASE_ADDRESS + 14;
signal PWM_DIRECTION_1_UPPER : integer := PWM_BASE_ADDRESS + 15;
signal PWM_CHANNEL_LOWER : integer := PWM_BASE_ADDRESS + 16;
signal PWM_CHANNEL_UPPER : integer := PWM_BASE_ADDRESS + 17;
signal PWM_TIMING_LOWER : integer := PWM_BASE_ADDRESS + 18;
signal PWM_TIMING_UPPER : integer := PWM_BASE_ADDRESS + 19;
signal PWM_CMD_LOWER : integer := PWM_BASE_ADDRESS + 20;
signal PWM_CMD_UPPER : integer := PWM_BASE_ADDRESS + 21;
signal PWM_CONTROL_LOWER : integer := PWM_BASE_ADDRESS + 22;
signal PWM_CONTROL_UPPER : integer := PWM_BASE_ADDRESS + 23;
signal modeBuf : std_logic_vector(15 downto 0) := (others => '0');
signal maskBuf : std_logic_vector(31 downto 0) := (others => '1');
signal directControlBuf : std_logic_vector(31 downto 0) := (others => '1');

37
MainController/RAM9X8_ParallelBusMaster.bsf
View File

@ -101,45 +101,10 @@ applicable agreement for further details.
(line (pt 328 96)(pt 312 96)(line_width 3))
)
(parameter
"PB_FIRST_FREE_LOWER"
"PB_BASE_ADDRESS"
"6"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PB_FIRST_FREE_UPPER"
"7"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PB_CMD_LOWER"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PB_CMD_UPPER"
"9"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PB_FILL_ADDRESS_SPACE_LOWER"
"10"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PB_FILL_ADDRESS_SPACE_UPPER"
"11"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PB_CONTROL_LOWER"
"12"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PB_CONTROL_UPPER"
"13"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"ARRAY_LENGTH"
"256"

41
MainController/RAM9X8_ParallelBusMaster.vhd
View File

@ -5,14 +5,7 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8_ParallelBusMaster is
generic(
PB_FIRST_FREE_LOWER : integer := 6;
PB_FIRST_FREE_UPPER : integer := 7;
PB_CMD_LOWER : integer := 8;
PB_CMD_UPPER : integer := 9;
PB_FILL_ADDRESS_SPACE_LOWER : integer := 10;
PB_FILL_ADDRESS_SPACE_UPPER : integer := 11;
PB_CONTROL_LOWER : integer := 12;
PB_CONTROL_UPPER : integer := 13;
PB_BASE_ADDRESS : integer := 6;
ARRAY_LENGTH : integer := 256;
DATA_BUS_WIDTH : integer := 8;
@ -38,6 +31,17 @@ end entity;
architecture behavorial of RAM9X8_ParallelBusMaster is
signal PB_FIRST_FREE_LOWER : integer := PB_BASE_ADDRESS;
signal PB_FIRST_FREE_UPPER : integer := PB_BASE_ADDRESS + 1;
signal PB_CMD_LOWER : integer := PB_BASE_ADDRESS + 2;
signal PB_CMD_UPPER : integer := PB_BASE_ADDRESS + 3;
signal PB_FILL_ADDRESS_SPACE_LOWER : integer := PB_BASE_ADDRESS + 4;
signal PB_FILL_ADDRESS_SPACE_UPPER : integer := PB_BASE_ADDRESS + 5;
signal PB_CONTROL_2_LOWER : integer := PB_BASE_ADDRESS + 6;
signal PB_CONTROL_2_UPPER : integer := PB_BASE_ADDRESS + 7;
signal PB_CONTROL_1_LOWER : integer := PB_BASE_ADDRESS + 8;
signal PB_CONTROL_1_UPPER : integer := PB_BASE_ADDRESS + 9;
type mem is array (ARRAY_LENGTH - 1 downto 0) of std_logic_vector(7 downto 0);
signal memoryAddress : mem;
signal memoryData : mem;
@ -52,6 +56,8 @@ signal errorBuf : std_logic_vector(7 downto 0) := x"00";
signal addrTemp : std_logic_vector(7 downto 0) := x"00";
signal dataTemp : std_logic_vector(15 downto 0) := x"0000";
signal circleCounterBuf : std_logic_vector(7 downto 0) := x"00";
type CommunicationState_start is (Waiting, TransmiteAddress, TransmiteCheck, PreparingToReceiveData, ReceiveData, ReceiveCheck, Timeout, ReceiveCheckTimeout);
signal CommunicationState : CommunicationState_start := Waiting ;
@ -68,7 +74,8 @@ begin
if (ce = '0') then -- Если микросхема выбрана
addr := conv_integer(address);
if (addr = PB_FIRST_FREE_UPPER or addr = PB_FIRST_FREE_LOWER or addr = PB_CMD_UPPER or addr = PB_CMD_LOWER
or addr = PB_FILL_ADDRESS_SPACE_UPPER or addr = PB_FILL_ADDRESS_SPACE_LOWER or addr = PB_CONTROL_UPPER or addr = PB_CONTROL_LOWER) then
or addr = PB_FILL_ADDRESS_SPACE_UPPER or addr = PB_FILL_ADDRESS_SPACE_LOWER or addr = PB_CONTROL_2_UPPER or addr = PB_CONTROL_2_LOWER
or addr = PB_CONTROL_1_UPPER or addr = PB_CONTROL_1_LOWER) then
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
case addr is
when PB_FIRST_FREE_UPPER =>
@ -83,9 +90,13 @@ begin
data <= fasBuf(15 downto 8);
when PB_FILL_ADDRESS_SPACE_LOWER =>
data <= fasBuf(7 downto 0);
when PB_CONTROL_UPPER =>
when PB_CONTROL_2_UPPER =>
data <= (others => '0');
when PB_CONTROL_2_LOWER =>
data <= circleCounterBuf;
when PB_CONTROL_1_UPPER =>
data <= errorBuf;
when PB_CONTROL_LOWER =>
when PB_CONTROL_1_LOWER =>
data <= controlBuf(7 downto 0);
when others =>
data <= (others => 'Z'); -- Запретить запись на шину
@ -131,6 +142,7 @@ begin
variable countValue : integer range 0 to 255 := 63;
variable errorCount : integer range 0 to 15 := 0;
variable position : integer range 0 to ARRAY_LENGTH - 1 := 0;
variable circleCounter : integer range 0 to 255 := 0;
begin
if(rising_edge (clk)) then
if cmdBuf(15) = '1' then
@ -148,6 +160,7 @@ begin
pbdir <= b"11";
countValue := 7;
count := 0;
circleCounterBuf <= conv_std_logic_vector(circleCounter, 8);
when TransmiteAddress =>
if count < countValue then
if count = 0 then
@ -172,6 +185,7 @@ begin
count := count + 1;
else
CommunicationState <= Waiting;
errorCount := errorCount + 1;
errorBuf(0) <= '1';
end if;
end if;
@ -197,6 +211,7 @@ begin
count := count + 1;
else
CommunicationState <= Waiting;
errorCount := errorCount + 1;
errorBuf(1) <= '1';
end if;
end if;
@ -214,9 +229,11 @@ begin
position := position + 2;
else
position := 0;
circleCounter := circleCounter + 1;
end if;
else
CommunicationState <= Waiting;
errorCount := errorCount + 1;
errorBuf(2) <= '1';
end if;
else
@ -224,6 +241,7 @@ begin
count := count + 1;
else
CommunicationState <= Waiting;
errorCount := errorCount + 1;
errorBuf(3) <= '1';
end if;
end if;
@ -243,6 +261,7 @@ begin
position := 0;
errorCount := 0;
errorBuf <= (others => '0');
CommunicationState <= Waiting;
end if;
end if;
end process;

27
MainController/RAM9X8_Peripheral.bsf
View File

@ -94,35 +94,10 @@ applicable agreement for further details.
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"PER_ACTIVE_DEVICE_LOWER"
"38"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PER_ACTIVE_DEVICE_UPPER"
"39"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PER_REZERVED_1_LOWER"
"PER_BASE_ADDRESS"
"40"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PER_REZERVED_1_UPPER"
"41"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PER_REZERVED_2_LOWER"
"42"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"PER_REZERVED_2_UPPER"
"43"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DATA_BUS_WIDTH"
"8"

14
MainController/RAM9X8_Peripheral.vhd
View File

@ -5,12 +5,7 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8_Peripheral is
generic(
PER_ACTIVE_DEVICE_LOWER : integer := 38;
PER_ACTIVE_DEVICE_UPPER : integer := 39;
PER_REZERVED_1_LOWER : integer := 40;
PER_REZERVED_1_UPPER : integer := 41;
PER_REZERVED_2_LOWER : integer := 42;
PER_REZERVED_2_UPPER : integer := 43;
PER_BASE_ADDRESS : integer := 40;
DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9
@ -34,6 +29,13 @@ end entity;
architecture behavorial of RAM9X8_Peripheral is
signal PER_ACTIVE_DEVICE_LOWER : integer := PER_BASE_ADDRESS;
signal PER_ACTIVE_DEVICE_UPPER : integer := PER_BASE_ADDRESS + 1;
signal PER_REZERVED_1_LOWER : integer := PER_BASE_ADDRESS + 2;
signal PER_REZERVED_1_UPPER : integer := PER_BASE_ADDRESS + 3;
signal PER_REZERVED_2_LOWER : integer := PER_BASE_ADDRESS + 4;
signal PER_REZERVED_2_UPPER : integer := PER_BASE_ADDRESS + 5;
signal activeDeviceBuf : std_logic_vector(15 downto 0) := (others => '0');
signal rezerved1Buf : std_logic_vector(15 downto 0) := (others => '0');
signal rezerved2Buf : std_logic_vector(15 downto 0) := (others => '0');

27
MainController/RAM9X8_SerialBusMaster.bsf
View File

@ -87,35 +87,10 @@ applicable agreement for further details.
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"SB_DATA_LOWER"
"SB_BASE_ADDRESS"
"0"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SB_DATA_UPPER"
"1"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SB_CMD_LOWER"
"2"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SB_CMD_UPPER"
"3"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SB_CONTROL_LOWER"
"4"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SB_CONTROL_UPPER"
"5"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DATA_BUS_WIDTH"
"8"

14
MainController/RAM9X8_SerialBusMaster.vhd
View File

@ -5,12 +5,7 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8_SerialBusMaster is
generic(
SB_DATA_LOWER : integer := 0;
SB_DATA_UPPER : integer := 1;
SB_CMD_LOWER : integer := 2;
SB_CMD_UPPER : integer := 3;
SB_CONTROL_LOWER : integer := 4;
SB_CONTROL_UPPER : integer := 5;
SB_BASE_ADDRESS : integer := 0;
DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9
@ -33,6 +28,13 @@ end entity;
architecture behavorial of RAM9X8_SerialBusMaster is
signal SB_DATA_LOWER : integer := SB_BASE_ADDRESS;
signal SB_DATA_UPPER : integer := SB_BASE_ADDRESS + 1;
signal SB_CMD_LOWER : integer := SB_BASE_ADDRESS + 2;
signal SB_CMD_UPPER : integer := SB_BASE_ADDRESS + 3;
signal SB_CONTROL_LOWER : integer := SB_BASE_ADDRESS + 4;
signal SB_CONTROL_UPPER : integer := SB_BASE_ADDRESS + 5;
signal dataBufIn : std_logic_vector(15 downto 0) := (others => '0');
signal dataBufOut : std_logic_vector(15 downto 0) := (others => '0');
signal cmdBuf : std_logic_vector(15 downto 0) := (others => '0');

37
MainController/RAM9X8_Service.bsf
View File

@ -101,45 +101,10 @@ applicable agreement for further details.
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"SRV_CONTROL_LOWER"
"72"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SRV_CONTROL_UPPER"
"73"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SRV_LEDS_LOWER"
"SRV_BASE_ADDRESS"
"74"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SRV_LEDS_UPPER"
"75"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SRV_INIT_LOWER"
"76"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SRV_INIT_UPPER"
"77"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SRV_VERSION_LOWER"
"78"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SRV_VERSION_UPPER"
"79"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DATA_BUS_WIDTH"
"8"

18
MainController/RAM9X8_Service.vhd
View File

@ -5,14 +5,7 @@ use ieee.std_logic_unsigned.all;
entity RAM9X8_Service is
generic(
SRV_CONTROL_LOWER : integer := 72;
SRV_CONTROL_UPPER : integer := 73;
SRV_LEDS_LOWER : integer := 74;
SRV_LEDS_UPPER : integer := 75;
SRV_INIT_LOWER : integer := 76;
SRV_INIT_UPPER : integer := 77;
SRV_VERSION_LOWER : integer := 78;
SRV_VERSION_UPPER : integer := 79;
SRV_BASE_ADDRESS : integer := 74;
DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9
@ -37,6 +30,15 @@ end entity;
architecture behavorial of RAM9X8_Service is
signal SRV_CONTROL_LOWER : integer := SRV_BASE_ADDRESS;
signal SRV_CONTROL_UPPER : integer := SRV_BASE_ADDRESS + 1;
signal SRV_LEDS_LOWER : integer := SRV_BASE_ADDRESS + 2;
signal SRV_LEDS_UPPER : integer := SRV_BASE_ADDRESS + 3;
signal SRV_INIT_LOWER : integer := SRV_BASE_ADDRESS + 4;
signal SRV_INIT_UPPER : integer := SRV_BASE_ADDRESS + 5;
signal SRV_VERSION_LOWER : integer := SRV_BASE_ADDRESS + 6;
signal SRV_VERSION_UPPER : integer := SRV_BASE_ADDRESS + 7;
signal ledsBuf : std_logic_vector(15 downto 0) := (others => '0');
signal initBuf : std_logic_vector(15 downto 0) := (others => '0');
signal versionBuf : std_logic_vector(15 downto 0) := x"0004";