altera/MainController/RAM9X8_Service.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
  
entity RAM9X8_Service is	
	generic(
		SRV_BASE_ADDRESS : integer := 74;
		
		DATA_BUS_WIDTH : integer := 8;
		ADDRESS_BUS_WIDTH : integer := 9
	);	
	
	port(
		clk : in std_logic;
		
		data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
		address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
		we : in std_logic;
		oe : in std_logic;
		ce : in std_logic;
		
		er0_in : in std_logic;
		leds : out std_logic_vector(3 downto 0);
		er0_out : out std_logic;
		init : out std_logic;
		sres : out std_logic
	); 
end entity;

architecture behavorial of RAM9X8_Service is

signal SRV_CONTROL_LOWER : integer := SRV_BASE_ADDRESS;
signal SRV_CONTROL_UPPER : integer := SRV_BASE_ADDRESS + 1;
signal SRV_LEDS_LOWER : integer := SRV_BASE_ADDRESS + 2;
signal SRV_LEDS_UPPER : integer := SRV_BASE_ADDRESS + 3;
signal SRV_INIT_LOWER : integer := SRV_BASE_ADDRESS + 4;
signal SRV_INIT_UPPER : integer := SRV_BASE_ADDRESS + 5;
signal SRV_VERSION_LOWER : integer := SRV_BASE_ADDRESS + 6;
signal SRV_VERSION_UPPER : integer := SRV_BASE_ADDRESS + 7;

signal ledsBuf : std_logic_vector(15 downto 0) := (others => '0');
signal initBuf : std_logic_vector(15 downto 0) := (others => '0');
signal versionBuf : std_logic_vector(15 downto 0) := x"0004";

begin	

	process (we, oe, ce)
		variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
	begin
		if (ce = '0') then  -- Если микросхема выбрана
			addr := conv_integer(address);
			if (addr = SRV_CONTROL_UPPER or addr = SRV_CONTROL_LOWER
				or addr = SRV_LEDS_LOWER or addr = SRV_LEDS_UPPER
				or addr = SRV_INIT_LOWER or addr = SRV_INIT_UPPER
				or addr = SRV_VERSION_LOWER or addr = SRV_VERSION_UPPER) then
				if (oe = '0' and we = '1') then  -- Если сигнал чтения активен, а записи нет	
					case addr is
						when SRV_CONTROL_UPPER =>
							data <= (others => '0');
						when SRV_CONTROL_LOWER =>
							data(7 downto 1) <= (others => '0');
							data(0) <= er0_in;
						when SRV_LEDS_UPPER =>
							data <= ledsBuf(15 downto 8);
						when SRV_LEDS_LOWER =>
							data <= ledsBuf(7 downto 0);
						when SRV_INIT_UPPER =>
							data <= not initBuf(15 downto 8);
						when SRV_INIT_LOWER =>
							data <= not initBuf(7 downto 0);
						when SRV_VERSION_UPPER =>
							data <= versionBuf(15 downto 8);
						when SRV_VERSION_LOWER =>
							data <= versionBuf(7 downto 0);		
						when others => 
							data <= (others => 'Z');  -- Запретить запись на шину
					end case;				
				elsif (oe = '1' and we = '0') then  -- Если сигнал записи активен, а чтения нет
					case addr is
						when SRV_LEDS_UPPER =>
							ledsBuf(15 downto 8) <= data;
						when SRV_LEDS_LOWER =>	
							ledsBuf(7 downto 0) <= data;
						when SRV_INIT_UPPER =>
							initBuf(15 downto 8) <= data;
						when SRV_INIT_LOWER =>	
							initBuf(7 downto 0) <= data;							
						when others =>
							data <= (others => 'Z');  -- Запретить запись на шину
					end case;
				else
					data <= (others => 'Z');  -- Запретить запись на шину
				end if;
			else 
				data <= (others => 'Z');  -- Запретить запись на шину
			end if;	
		else
			data <= (others => 'Z');  -- Запретить запись на шину
		end if;
	end process;
	
	process(clk) is
	begin
		if rising_edge(clk) then
			if initBuf = x"5AA5" then
				init <= '1';
			end if;	
		end if;	
	end process;
	
	process(clk)
	begin
		if rising_edge(clk) then	
			leds <= ledsBuf(3 downto 0);
			er0_out <= ledsBuf(15);
			sres <= ledsBuf(14);
		end if;
	end process;
	
end behavorial;