360 lines
11 KiB
VHDL
360 lines
11 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity RAM9X8_SerialBusMaster is
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generic(
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REG_ADDR_DATA_UPPER_BYTE : integer := 0;
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REG_ADDR_DATA_LOWER_BYTE : integer := 1;
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REG_ADDR_CMD_UPPER_BYTE : integer := 2;
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REG_ADDR_CMD_LOWER_BYTE : integer := 3;
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DATA_BUS_WIDTH : integer := 8;
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ADDRESS_BUS_WIDTH : integer := 9
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);
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port(
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clk : in std_logic;
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data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
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we : in std_logic;
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oe : in std_logic;
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ce : in std_logic;
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sbclk : out std_logic := '0';
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sbdataout : out std_logic := '0';
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sbdatain : in std_logic;
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);
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end entity;
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architecture behavorial of RAM9X8_SerialBusMaster is
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type mem is array (511 downto 0) of std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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signal memory : mem;
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signal wePrev : std_logic := '0';
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signal oePrev : std_logic := '0';
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signal cePrev : std_logic := '0';
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type MemoryMachine is (Waiting, Writing, Reading);
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signal stateMM : MemoryMachine := Waiting;
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signal dataBufIn : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downro 0);
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signal dataBufOut : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downro 0);
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signal cmdBuf : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downro 0);
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signal direction : std_logic := '0';
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signal addressToTransmit : std_logic_vector(7 downto 0) := x"00";
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signal dataToTransmit : std_logic_vector(15 downto 0) := x"0000";
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signal dataFromDevices : std_logic_vector(15 downto 0) := x"0000";
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type CommunicationState_start is (Waiting, TransmiteAddress, TransmiteData, TransmiteCRC, TransmiteCheck, ReceiveData, ReceiveCRC, ReceiveCheck);
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signal CommunicationState : CommunicationState_start := Waiting ;
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signal resetCRC : std_logic := '1';
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signal CRC : std_logic_vector(3 downto 0) := x"0";
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signal bufCRC : std_logic_vector(3 downto 0) := x"0";
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signal dataCRC : std_logic_vector(31 downto 0) := x"00000000"; -- переключает
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signal readyCRC : std_logic := '0'; -- готовность контрольной суммы
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signal lineBusy : std_logic := '1';
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begin
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process(clk)
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variable addr : integer range 0 to 2^ADDRESS_BUS_WIDTH := 0;
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begin
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if rising_edge(clk) then
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case stateMM is
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when Waiting =>
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if ce = '0' and cePrev = '1' then
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addr := conv_integer(address);
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if (addr == REG_ADDR_DATA_UPPER_BYTE or addr == REG_ADDR_DATA_LOWER_BYTE or addr == REG_ADDR_CMD_UPPER_BYTE or addr == REG_ADDR_CMD_LOWER_BYTE) then
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if oe = '0' then
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stateMM <= Reading;
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else
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stateMM <= Writing;
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end if;
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end if;
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else
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start <= '0';
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data <= (others => 'Z');
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end if;
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when Reading =>
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case addr is
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when REG_ADDR_DATA_UPPER_BYTE =>
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data <= dataBufOut(15 downto 8);
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when REG_ADDR_DATA_LOWER_BYTE =>
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data <= dataBufOut(7 downto 0);
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when REG_ADDR_CMD_UPPER_BYTE =>
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data <= cmdBuf(15 downto 8);
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when REG_ADDR_CMD_LOWER_BYTE =>
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data <= cmdBuf(7 downto 0);
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when others =>
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end case;
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if oe = '1' and oePrev = '0' then
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stateMM <= Waiting;
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elsif ce = '1' then
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stateMM <= Waiting;
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end if;
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when Writing =>
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if we = '0' and wePrev = '1' then
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case addr is
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when REG_ADDR_DATA_UPPER_BYTE =>
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dataBufIn(15 downto 8) <= data;
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when REG_ADDR_DATA_LOWER_BYTE =>
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dataBufIn(7 downto 0) <= data;
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when REG_ADDR_CMD_UPPER_BYTE =>
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cmdBuf(15 downto 8) <= data;
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when REG_ADDR_CMD_LOWER_BYTE =>
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cmdBuf(7 downto 0) <= data;
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start <= '1';
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when others =>
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end case;
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stateMM <= Waiting;
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elsif ce = '1' then
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stateMM <= Waiting;
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end if;
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when others =>
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end case;
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oePrev <= oe;
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cePrev <= ce;
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wePrev <= we;
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end if;
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end process;
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process(clk) is
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variable count : integer range 0 to 255 := 0;
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variable countValue : integer range 0 to 255 := 63;
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variable state : integer range 0 to 1 := 1;
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variable bitCnt : integer range -1 to 31 := 0;
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variable latch : integer range 0 to 1 := 0;
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begin
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if(rising_edge (clk)) then
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case CommunicationState is
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when Waiting =>
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sbclk <= '0';
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bitCnt := 8;
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latch := 0;
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resetCRC <= '1';
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sbdataout <= '0';
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lineBusy <= '0';
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count := 0;
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state := 1;
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if start = '1' and startPrev = '0' then
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direction <= cmdBuf(15);
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dataCRC(24) <= cmdBuf(15);
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addressToTransmit(7 downto 0) <= cmdBuf(7 downto 0);
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dataCRC(23 downto 16) <= cmdBuf(7 downto 0);
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dataToTransmit <= dataBufIn;
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dataCRC(15 downto 0) <= dataBufIn;
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CommunicationState <= TransmitAddress;
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lineBusy <= '1';
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end if;
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when TransmitAddress =>
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if bitCnt = -1 then
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if direction = '1' then
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CommunicationState <= TransmitData;
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resetCRC <= '0';
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else
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CommunicationState <= ReceiveData;
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end if;
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bitCnt := 15;
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else
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if count < countValue and state = 1 then
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if latch = 0 then
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sbdataout <= direction;
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else
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sbdataout <= addressToTransmit(bitCnt);
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end if;
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sbclk <= '0';
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count := count + 1;
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elsif count = countValue and state = '1' then
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latch := 1;
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count := 0;
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state := 0;
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elsif count < countValue and state = '0' then
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sbclk <= '1';
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count := count + 1;
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elsif count = countValue and state = '0' then
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count := 0;
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state := 1;
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bitCnt := bitCnt - 1;
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end if;
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end if;
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when TransmitData =>
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if bitCnt = -1 then
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CommunicationState <= TransmitCRC;
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bitCnt := 3;
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else
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if count < countValue and state = 1 then
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sbdataout <= data(bitCnt);
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sbclk <= '0';
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count := count + 1;
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elsif count = countValue and state = 1 then
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count := 0;
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state := 0;
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elsif count < countValue and state = 0 then
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sbclk <= '1';
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count := count + 1;
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elsif count = countValue and state = 0 then
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count := 0;;
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state := 1;
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bitCnt := bitCnt - 1;
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end if;
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end if;
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when TransmitCRC =>
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if readyCRC = '1' then
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if bitCnt = -1 then
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CommunicationState <= TransmitCheck;
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errors(1) <= '0';
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else
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if count < count and state = 1 then
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sbdataout <= CRC(bitCnt);
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sbclk <= '0';
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count := count + 1;
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elsif count = countValue and state = 1 then
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count := 0;
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state := 0;
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elsif count < countValue and state = 0 then
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sbclk <= '1';
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count := count + 1;
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elsif count = countValue and state = 0 then
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count := 0;
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state := 1;
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bitCnt := bitCnt - 1;
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end if;
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end if;
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else
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CommunicationState <= Waiting;
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errors(1) <= '1';
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countError1 <= countError1 + 1;
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end if;
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when TransmitCheck =>
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if count < countValue and state = 1 then
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sbclk <= '0';
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count := count + 1;
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else
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count := 0;
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state := 0;
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if sbdatain = '0' then
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countSuccessfulTransmite <= countSuccessfulTransmite + 1;
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errors(0) <= '0';
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else
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errors(0) <= '1';
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countError0 <= countError0 + 1;
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end if;
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CommunicationState <= Waiting;
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end if;
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when ReceiveData =>
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if bitCnt = -1 then
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CommunicationState <= ReceiveCRC;
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bitCnt <= 3;
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else
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if count < countValue and state = 1 then
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sbclk <= '0';
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count := count + 1;
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elsif count = countValue and state = 1 then
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dataFromDevices(bitCnt) <= sbdatain;
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count := 0;
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state := 0;
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elsif count < countValue and state = 0 then
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sbclk <= '1';
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count := count + 1;
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elsif count = countValue and state = '0' then
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count := 0;
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state := 1;
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bitCnt := bitCnt - 1;
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end if;
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end if;
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when ReceiveCRC =>
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if bitCnt = -1 then
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CommunicationState <= ReceiveCheck;
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else
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if count < countValue and state = 1 then
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sbclk <= '0';
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count := count + 1;
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elsif count = countValue and state = 1 then
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bufCRC(BitCnt) <= sbdatain;
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count := 0;
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state := 0;
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if bitCnt = 0 then
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dataCRC(24) <= direction;
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dataCRC(23 downto 16) <= addressToTransmit;
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dataCRC(15 downto 0) <= dataFromDevices(15 downto 0);
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resetCRC <= '0';
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end if;
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elsif count < countValue and state = 0 then
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sbclk <= '1';
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count := count + 1;
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elsif count = countValue and state = 0 then
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count := 0;
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state := 1;
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bitCnt := bitCnt - 1;
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end if;
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end if;
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when ReceiveCheck =>
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if readyCRC = '1' then
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if bufCRC = CRC then
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countSuccessfulReceive <= countSuccessfulReceive + 1;
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dataBufOut <= dataFromDevices;
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errors(3) <= '0';
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else
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errors(3) <= '1';
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countError3 <= countError3 + 1;
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end if;
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errors(2) <= '0';
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else
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errors(2) <= '1';
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countError2 <= countError2 + 1;
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end if;
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CommunicationState <= Waiting;
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when others =>
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end case;
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startPrev <= start;
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end if;
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end process;
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process(clk)
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variable lacth : integer range 0 to 1 := 0;
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variable bitCnt : integer range -1 to 24 := 0;
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begin
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if rising_edge(clk) then
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if resetCRC = '1' then
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bitCnt := 24;
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CRC <= x"0";
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lacth := 0;
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readyCRC <= '0';
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else
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if readyCRC = '0' then
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if lacth = 0 then
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if bitCnt /= -1 then
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CRC(3) <= CRC(2) xor CRC(3);
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CRC(2) <= CRC(1) xor CRC(0);
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CRC(1) <= CRC(0);
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CRC(0) <= dataCRC(bitCnt) xor CRC(1);
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bitCnt := bitCnt - 1;
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else
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bitCnt := 3;
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lacth := 1;
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end if;
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else
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if bitCnt /= -1 then
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CRC(3) <= CRC(2) xor CRC(3);
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CRC(2) <= CRC(1) xor CRC(0);
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CRC(1) <= CRC(0);
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CRC(0) <= '1' xor CRC(1);
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bitCnt := bitCnt - 1;
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else
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readyCRC <= '1';
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countreadyCRC <= countreadyCRC + 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end behavorial;
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