207 lines
6.6 KiB
VHDL
207 lines
6.6 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity RAM9X8_HWPBusMaster is
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generic(
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REG_ADDR_CMD_2_UPPER_BYTE : integer := 44;
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REG_ADDR_CMD_2_LOWER_BYTE : integer := 45;
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REG_ADDR_CMD_1_UPPER_BYTE : integer := 46;
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REG_ADDR_CMD_1_LOWER_BYTE : integer := 47;
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REG_ADDR_DATA_2_UPPER_BYTE : integer := 48;
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REG_ADDR_DATA_2_LOWER_BYTE : integer := 49;
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REG_ADDR_DATA_1_UPPER_BYTE : integer := 50;
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REG_ADDR_DATA_1_LOWER_BYTE : integer := 51;
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DATA_BUS_WIDTH : integer := 8;
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ADDRESS_BUS_WIDTH : integer := 9
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);
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port(
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clk : in std_logic;
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data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
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we : in std_logic;
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oe : in std_logic;
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ce : in std_logic;
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hwpdataout : out std_logic;
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hwpclk : out std_logic;
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hwpdatain : in std_logic_vector(1 downto 0)
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);
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end entity;
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architecture behavorial of RAM9X8_HWPBusMaster is
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signal cmdBuf : std_logic_vector(31 downto 0) := (others => '0');
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signal dataBuf : std_logic_vector(31 downto 0) := (others => '0');
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signal tempBuf : std_logic_vector(31 downto 0) := (others => '0');
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signal dataToSend : std_logic_vector(33 downto 0) := (others => '0');
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signal cmdBuf_0_prev : std_logic := '0';
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signal done : std_logic := '1';
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type HWPSt is (Waiting, SendingData, ReceivingData, Checking);
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signal HWPState : HWPSt := Waiting;
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begin
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process (we, oe, ce)
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variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
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begin
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if (ce = '0') then -- Если микросхема выбрана
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addr := conv_integer(address);
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if (addr = REG_ADDR_CMD_2_UPPER_BYTE or addr = REG_ADDR_CMD_2_LOWER_BYTE or addr = REG_ADDR_CMD_1_UPPER_BYTE or addr = REG_ADDR_CMD_1_LOWER_BYTE
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or addr = REG_ADDR_DATA_2_UPPER_BYTE or addr = REG_ADDR_DATA_2_LOWER_BYTE or addr = REG_ADDR_DATA_1_UPPER_BYTE or addr = REG_ADDR_DATA_1_LOWER_BYTE) then
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if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
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case addr is
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when REG_ADDR_CMD_2_UPPER_BYTE =>
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data <= cmdBuf(31 downto 24);
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when REG_ADDR_CMD_2_LOWER_BYTE =>
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data <= cmdBuf(23 downto 16);
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when REG_ADDR_CMD_1_UPPER_BYTE =>
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data <= cmdBuf(15 downto 8);
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when REG_ADDR_CMD_1_LOWER_BYTE =>
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data(7 downto 1) <= cmdBuf(7 downto 1);
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data(0) <= done;
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when REG_ADDR_DATA_2_UPPER_BYTE =>
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data <= tempBuf(29 downto 22);
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when REG_ADDR_DATA_2_LOWER_BYTE =>
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data <= tempBuf(21 downto 14);
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when REG_ADDR_DATA_1_UPPER_BYTE =>
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data <= tempBuf(13 downto 6);
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when REG_ADDR_DATA_1_LOWER_BYTE =>
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data(7 downto 2) <= tempBuf(5 downto 0);
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data(1 downto 0) <= (others => '0');
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when others =>
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data <= (others => 'Z'); -- Запретить запись на шину
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end case;
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elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
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case addr is
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when REG_ADDR_CMD_2_UPPER_BYTE =>
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cmdBuf(31 downto 24) <= data;
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when REG_ADDR_CMD_2_LOWER_BYTE =>
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cmdBuf(23 downto 16) <= data;
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when REG_ADDR_CMD_1_UPPER_BYTE =>
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cmdBuf(15 downto 8) <= data;
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when REG_ADDR_CMD_1_LOWER_BYTE =>
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cmdBuf(7 downto 0) <= data;
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when REG_ADDR_DATA_2_UPPER_BYTE =>
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dataBuf(31 downto 24) <= data;
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when REG_ADDR_DATA_2_LOWER_BYTE =>
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dataBuf(23 downto 16) <= data;
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when REG_ADDR_DATA_1_UPPER_BYTE =>
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dataBuf(15 downto 8) <= data;
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when REG_ADDR_DATA_1_LOWER_BYTE =>
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dataBuf(7 downto 0) <= data;
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when others =>
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data <= (others => 'Z'); -- Запретить запись на шину
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end case;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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end process;
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process(clk) is
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variable count : integer range 0 to 511 := 0;
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variable state : integer range 0 to 1 := 0;
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variable countBit : integer range 0 to 32 := 0;
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begin
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if rising_edge(clk) then
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case HWPState is
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when Waiting =>
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if cmdBuf(0) = '1' and cmdBuf_0_prev = '0' then
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done <= '1';
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if cmdBuf(14) = '0' then
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if cmdBuf(13) = '0' then
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dataToSend(33 downto 22) <= (others => '0');
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dataToSend(21 downto 16) <= cmdBuf(15 downto 10);
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dataToSend(15 downto 0) <= cmdBuf(31 downto 16);
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countBit := 21;
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else
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dataToSend(33) <= '0';
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dataToSend(32 downto 30) <= cmdBuf(15 downto 13);
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dataToSend(29 downto 0) <= dataBuf(31 downto 2);
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countBit := 32;
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end if;
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else
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dataToSend(33) <= '1';
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dataToSend(32 downto 2) <= (others => '0');
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dataToSend(1 downto 0) <= cmdBuf(15 downto 14);
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countBit := 1;
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end if;
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HWPState <= SendingData;
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count := 0;
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state := 0;
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end if;
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when SendingData =>
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if count < 511 and state = 0 then
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if count = 0 then
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hwpdataout <= dataToSend(countBit);
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end if;
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count := count + 1;
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elsif count = 511 and state = 0 then
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hwpclk <= '0';
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count := 0;
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state := 1;
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elsif count < 511 and state = 1 then
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count := count + 1;
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elsif count = 511 and state = 1 then
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hwpclk <= '1';
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count := 0;
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state := 0;
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if countBit > 0 then
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countBit := countBit - 1;
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else
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if dataToSend(33) = '1' then
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HWPState <= ReceivingData;
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countBit := 29;
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else
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HWPState <= Checking;
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end if;
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end if;
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end if;
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when ReceivingData =>
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if count < 511 and state = 0 then
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count := count + 1;
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elsif count = 511 and state = 0 then
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hwpclk <= '0';
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count := 0;
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state := 1;
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if dataToSend(1) = '0' then
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tempBuf(countBit) <= hwpdatain(0);
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hwpdataout <= hwpdatain(0);
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else
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tempBuf(countBit) <= hwpdatain(1);
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hwpdataout <= hwpdatain(1);
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end if;
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elsif count < 511 and state = 1 then
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count := count + 1;
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elsif count = 511 and state = 1 then
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hwpclk <= '1';
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count := 0;
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state := 0;
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if countBit > 0 then
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countBit := countBit - 1;
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else
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HWPState <= Checking;
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end if;
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end if;
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when Checking =>
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done <= '0';
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HWPState <= Waiting;
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when others =>
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HWPState <= Waiting;
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end case;
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cmdBuf_0_prev <= cmdBuf(0);
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end if;
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end process;
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end behavorial;
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