109 lines
7.7 KiB
Plaintext
109 lines
7.7 KiB
Plaintext
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vendor_name = ModelSim
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source_file = 1, D:/GITEA/altera/MainController/MainController.bdf
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source_file = 1, D:/GITEA/altera/MainController/AlteraPLL.qip
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source_file = 1, D:/GITEA/altera/MainController/AlteraPLL.vhd
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source_file = 1, D:/GITEA/altera/MainController/RAM.vhd
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source_file = 1, D:/GITEA/altera/MainController/LedBlink.vhd
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source_file = 1, D:/GITEA/altera/MainController/db/MainController.cbx.xml
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source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
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source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
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source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/timing_b.vhd
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source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/timing_p.vhd
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source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altpll.tdf
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source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/aglobal131.inc
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source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_pll.inc
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source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/stratixii_pll.inc
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source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc
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source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/cbx.lst
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source_file = 1, D:/GITEA/altera/MainController/db/alterapll_altpll.v
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design_name = MainController
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instance = comp, \Data[7]~output\, Data[7]~output, MainController, 1
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instance = comp, \Data[6]~output\, Data[6]~output, MainController, 1
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instance = comp, \Data[5]~output\, Data[5]~output, MainController, 1
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instance = comp, \Data[4]~output\, Data[4]~output, MainController, 1
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instance = comp, \Data[3]~output\, Data[3]~output, MainController, 1
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instance = comp, \Data[2]~output\, Data[2]~output, MainController, 1
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instance = comp, \Data[1]~output\, Data[1]~output, MainController, 1
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instance = comp, \Data[0]~output\, Data[0]~output, MainController, 1
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instance = comp, \FPGA_LED_1~output\, FPGA_LED_1~output, MainController, 1
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instance = comp, \FPGA_CLK~input\, FPGA_CLK~input, MainController, 1
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instance = comp, \FPGA_CLK~inputclkctrl\, FPGA_CLK~inputclkctrl, MainController, 1
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instance = comp, \inst2|counter[0]~24\, inst2|counter[0]~24, MainController, 1
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instance = comp, \inst2|counter[0]\, inst2|counter[0], MainController, 1
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instance = comp, \inst2|counter[1]~26\, inst2|counter[1]~26, MainController, 1
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instance = comp, \inst2|counter[1]\, inst2|counter[1], MainController, 1
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instance = comp, \inst2|counter[2]~28\, inst2|counter[2]~28, MainController, 1
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instance = comp, \inst2|counter[2]\, inst2|counter[2], MainController, 1
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instance = comp, \inst2|counter[3]~30\, inst2|counter[3]~30, MainController, 1
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instance = comp, \inst2|counter[3]\, inst2|counter[3], MainController, 1
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instance = comp, \inst2|counter[4]~32\, inst2|counter[4]~32, MainController, 1
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instance = comp, \inst2|counter[4]\, inst2|counter[4], MainController, 1
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instance = comp, \inst2|counter[5]~34\, inst2|counter[5]~34, MainController, 1
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instance = comp, \inst2|counter[5]\, inst2|counter[5], MainController, 1
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instance = comp, \inst2|counter[6]~36\, inst2|counter[6]~36, MainController, 1
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instance = comp, \inst2|counter[6]\, inst2|counter[6], MainController, 1
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instance = comp, \inst2|counter[7]~38\, inst2|counter[7]~38, MainController, 1
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instance = comp, \inst2|counter[7]\, inst2|counter[7], MainController, 1
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instance = comp, \inst2|counter[8]~40\, inst2|counter[8]~40, MainController, 1
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instance = comp, \inst2|counter[8]\, inst2|counter[8], MainController, 1
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instance = comp, \inst2|counter[9]~42\, inst2|counter[9]~42, MainController, 1
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instance = comp, \inst2|counter[9]\, inst2|counter[9], MainController, 1
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instance = comp, \inst2|counter[10]~44\, inst2|counter[10]~44, MainController, 1
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instance = comp, \inst2|counter[10]\, inst2|counter[10], MainController, 1
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instance = comp, \inst2|counter[11]~46\, inst2|counter[11]~46, MainController, 1
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instance = comp, \inst2|counter[11]\, inst2|counter[11], MainController, 1
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instance = comp, \inst2|counter[12]~48\, inst2|counter[12]~48, MainController, 1
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instance = comp, \inst2|counter[12]\, inst2|counter[12], MainController, 1
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instance = comp, \inst2|counter[13]~50\, inst2|counter[13]~50, MainController, 1
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instance = comp, \inst2|counter[13]\, inst2|counter[13], MainController, 1
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instance = comp, \inst2|counter[14]~52\, inst2|counter[14]~52, MainController, 1
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instance = comp, \inst2|counter[14]\, inst2|counter[14], MainController, 1
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instance = comp, \inst2|counter[15]~54\, inst2|counter[15]~54, MainController, 1
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instance = comp, \inst2|counter[15]\, inst2|counter[15], MainController, 1
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instance = comp, \inst2|counter[16]~56\, inst2|counter[16]~56, MainController, 1
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instance = comp, \inst2|counter[16]\, inst2|counter[16], MainController, 1
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instance = comp, \inst2|counter[17]~58\, inst2|counter[17]~58, MainController, 1
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instance = comp, \inst2|counter[17]\, inst2|counter[17], MainController, 1
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instance = comp, \inst2|LessThan0~0\, inst2|LessThan0~0, MainController, 1
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instance = comp, \inst2|counter[18]~60\, inst2|counter[18]~60, MainController, 1
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instance = comp, \inst2|counter[18]\, inst2|counter[18], MainController, 1
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instance = comp, \inst2|counter[19]~62\, inst2|counter[19]~62, MainController, 1
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instance = comp, \inst2|counter[19]\, inst2|counter[19], MainController, 1
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instance = comp, \inst2|counter[20]~64\, inst2|counter[20]~64, MainController, 1
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instance = comp, \inst2|counter[20]\, inst2|counter[20], MainController, 1
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instance = comp, \inst2|counter[21]~66\, inst2|counter[21]~66, MainController, 1
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instance = comp, \inst2|counter[21]\, inst2|counter[21], MainController, 1
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instance = comp, \inst2|counter[22]~68\, inst2|counter[22]~68, MainController, 1
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instance = comp, \inst2|counter[22]\, inst2|counter[22], MainController, 1
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instance = comp, \inst2|counter[23]~70\, inst2|counter[23]~70, MainController, 1
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instance = comp, \inst2|counter[23]\, inst2|counter[23], MainController, 1
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instance = comp, \inst2|LessThan0~1\, inst2|LessThan0~1, MainController, 1
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instance = comp, \inst2|LessThan0~2\, inst2|LessThan0~2, MainController, 1
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instance = comp, \inst2|LessThan0~5\, inst2|LessThan0~5, MainController, 1
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instance = comp, \inst2|LessThan0~3\, inst2|LessThan0~3, MainController, 1
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instance = comp, \inst2|LessThan0~4\, inst2|LessThan0~4, MainController, 1
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instance = comp, \inst2|LessThan0~6\, inst2|LessThan0~6, MainController, 1
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instance = comp, \inst2|LessThan0~7\, inst2|LessThan0~7, MainController, 1
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instance = comp, \inst2|LessThan0~8\, inst2|LessThan0~8, MainController, 1
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instance = comp, \inst2|ledBuf~0\, inst2|ledBuf~0, MainController, 1
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instance = comp, \inst2|ledBuf\, inst2|ledBuf, MainController, 1
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instance = comp, \Address[7]~input\, Address[7]~input, MainController, 1
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instance = comp, \Address[6]~input\, Address[6]~input, MainController, 1
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instance = comp, \Address[5]~input\, Address[5]~input, MainController, 1
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instance = comp, \Address[4]~input\, Address[4]~input, MainController, 1
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instance = comp, \Address[3]~input\, Address[3]~input, MainController, 1
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instance = comp, \Address[2]~input\, Address[2]~input, MainController, 1
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instance = comp, \Address[1]~input\, Address[1]~input, MainController, 1
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instance = comp, \Address[0]~input\, Address[0]~input, MainController, 1
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instance = comp, \nOE~input\, nOE~input, MainController, 1
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instance = comp, \nWE~input\, nWE~input, MainController, 1
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instance = comp, \nCE~input\, nCE~input, MainController, 1
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instance = comp, \Data[7]~input\, Data[7]~input, MainController, 1
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instance = comp, \Data[6]~input\, Data[6]~input, MainController, 1
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instance = comp, \Data[5]~input\, Data[5]~input, MainController, 1
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instance = comp, \Data[4]~input\, Data[4]~input, MainController, 1
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instance = comp, \Data[3]~input\, Data[3]~input, MainController, 1
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instance = comp, \Data[2]~input\, Data[2]~input, MainController, 1
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instance = comp, \Data[1]~input\, Data[1]~input, MainController, 1
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instance = comp, \Data[0]~input\, Data[0]~input, MainController, 1
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