9 lines
167 B
VHDL
9 lines
167 B
VHDL
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AlteraPLL_inst : AlteraPLL PORT MAP (
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areset => areset_sig,
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inclk0 => inclk0_sig,
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c0 => c0_sig,
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c1 => c1_sig,
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c2 => c2_sig,
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locked => locked_sig
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);
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