altera/MainController/RAM9X8_Loader.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
  
entity RAM9X8_Loader is	
	generic(
		REG_ADDR_LOADER_LOWER_BYTE : integer := 44;
		REG_ADDR_LOADER_UPPER_BYTE : integer := 45;
		
		DATA_BUS_WIDTH : integer := 8;
		ADDRESS_BUS_WIDTH : integer := 9
	);
	
	port(
		clk : in std_logic;
		
		data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
		address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
		we : in std_logic;
		oe : in std_logic;
		ce : in std_logic;	
	
		addrDevice : out std_logic_vector(3 downto 0) := (others => '0');
		clkLoader : out std_logic := '0';
		rwLoader : out std_logic := '0';
		resetLoader : out std_logic := '0';
		dataOutLoader : out std_logic := '0';
		loadMode : out std_logic := '0';
		
      dataInLoader : in std_logic;
		error : in std_logic;
		hwpclk : in std_logic;
		hwpdata : in std_logic;
		pbclk : in std_logic
	); 
end entity;

architecture behavorial of RAM9X8_Loader is

signal loaderBuf : std_logic_vector(15 downto 0) := (others => '1');
signal sel : std_logic := '0';

begin	

	process (we, oe, ce)
		variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
	begin
		if (ce = '0') then  -- Если микросхема выбрана
			addr := conv_integer(address);
			if (addr = REG_ADDR_LOADER_UPPER_BYTE or addr = REG_ADDR_LOADER_LOWER_BYTE) then
				if (oe = '0' and we = '1') then  -- Если сигнал чтения активен, а записи нет	
					case addr is
						when REG_ADDR_LOADER_UPPER_BYTE =>
							data(7) <= dataInLoader;
							data(6 downto 0) <= loaderBuf(14 downto 8);
						when REG_ADDR_LOADER_LOWER_BYTE =>
							data <= loaderBuf(7 downto 0);
						when others => 
							data <= (others => 'Z');  -- Запретить запись на шину
					end case;				
				elsif (oe = '1' and we = '0') then  -- Если сигнал записи активен, а чтения нет
					case addr is
						when REG_ADDR_LOADER_UPPER_BYTE =>
							loaderBuf(15 downto 8) <= data;
						when REG_ADDR_LOADER_LOWER_BYTE =>
							loaderBuf(7 downto 0) <= data;	
						when others =>
							data <= (others => 'Z');  -- Запретить запись на шину
					end case;
				else
					data <= (others => 'Z');  -- Запретить запись на шину
				end if;
			else 
				data <= (others => 'Z');  -- Запретить запись на шину
			end if;	
		else
			data <= (others => 'Z');  -- Запретить запись на шину
		end if;
	end process;
	
	process(clk) is
	begin
		if rising_edge(clk) then
			loadMode <= loaderBuf(0);
			if loaderBuf(4) = '1' and loaderBuf(0) = '1' then
				sel <= '0';
			else 
				sel <= '1';
			end if;	
		end if;	
	end process;
	
	process(clk) is
	begin
		if rising_edge(clk) then
			case sel is
				when '0' => 
					addrDevice(3) <= pbclk;
					addrDevice(2) <= '1';
					addrDevice(1) <= '1';
					addrDevice(0) <= hwpdata;
					clkLoader <= hwpclk;
					dataOutLoader <= error;
					rwLoader <= '1';
					resetLoader <= '1';
				when '1' =>
					addrDevice <= loaderBuf(14 downto 11);
					clkLoader <= not loaderBuf(9);
					dataOutLoader <= not loaderBuf(7);			
					rwLoader <= loaderBuf(4);
					resetLoader <= loaderBuf(1);
				when others => 
			end case;	
		end if;	
	end process;
	
end behavorial;