15593 lines
4.6 MiB
15593 lines
4.6 MiB
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<li class="navelem"><a class="el" href="dir_9609623a411adcd586e91350a30aa9d5.html">MCU_STM32F4xx_Matlab</a></li><li class="navelem"><a class="el" href="dir_afe59ba76eea2f90e4e37233dbf4f6f2.html">Drivers</a></li><li class="navelem"><a class="el" href="dir_30f2d142c55236add84215456f0e2b1c.html">CMSIS</a></li> </ul>
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<div class="headertitle"><div class="title">stm32f407xx_matlab.h</div></div>
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<a href="stm32f407xx__matlab_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">/************************************************************************</span></div>
|
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<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span><span class="comment">Данный файл является копией stm32f407xx.h с некоторыми изменениями:</span></div>
|
||
<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">- добавлен кейловский stdint.h (через "", вместо <>) (~170)</span></div>
|
||
<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment">- добавлен cmsis_armcc_matlab.h с дефайнами из оригинального cmsis_armcc.h (~170)</span></div>
|
||
<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment">- добавлен core_cm4.h с дефайнами из оригинального core_cm4.h (~170)</span></div>
|
||
<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment">- добавлена структура имитирующая память МК (для работы дефайнов адресов регистров) (~950)</span></div>
|
||
<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment"> (надо допилить)</span></div>
|
||
<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span><span class="comment">Необходимо допилить поддержку всех дефайнов, которые объявляются в</span></div>
|
||
<div class="line"><a id="l00009" name="l00009"></a><span class="lineno"> 9</span><span class="comment">arm_acle.h, arm_compat.h, cmsis_armclang.h, cmsis_compiler.h, cmsis_version.h, </span></div>
|
||
<div class="line"><a id="l00010" name="l00010"></a><span class="lineno"> 10</span><span class="comment">core_cm4.h, mpu_armv7.h, stddef</span></div>
|
||
<div class="line"><a id="l00011" name="l00011"></a><span class="lineno"> 11</span><span class="comment">**************************************************************************/</span></div>
|
||
<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span><span class="preprocessor">#ifndef __STM32F407xx_H</span></div>
|
||
<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span><span class="preprocessor">#define __STM32F407xx_H</span></div>
|
||
<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"> 46</span> </div>
|
||
<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span><span class="preprocessor">#ifdef __cplusplus</span></div>
|
||
<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span> <span class="keyword">extern</span> <span class="stringliteral">"C"</span> {</div>
|
||
<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span><span class="preprocessor">#endif </span><span class="comment">/* __cplusplus */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span> </div>
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||
<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#ga45a97e4bb8b6ce7c334acc5f45ace3ba"> 58</a></span><span class="preprocessor">#define __CM4_REV 0x0001U </span></div>
|
||
<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#ga4127d1b31aaf336fab3d7329d117f448"> 59</a></span><span class="preprocessor">#define __MPU_PRESENT 1U </span></div>
|
||
<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460"> 60</a></span><span class="preprocessor">#define __NVIC_PRIO_BITS 4U </span></div>
|
||
<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gab58771b4ec03f9bdddc84770f7c95c68"> 61</a></span><span class="preprocessor">#define __Vendor_SysTickConfig 0U </span></div>
|
||
<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gac1ba8a48ca926bddc88be9bfd7d42641"> 62</a></span><span class="preprocessor">#define __FPU_PRESENT 1U </span></div>
|
||
<div class="foldopen" id="foldopen00076" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8"> 76</a></span><span class="keyword">typedef</span> <span class="keyword">enum</span></div>
|
||
<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span>{</div>
|
||
<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span><span class="comment">/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/</span></div>
|
||
<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30"> 79</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">NonMaskableInt_IRQn</a> = -14, </div>
|
||
<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa"> 80</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa">MemoryManagement_IRQn</a> = -12, </div>
|
||
<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af"> 81</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af">BusFault_IRQn</a> = -11, </div>
|
||
<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf"> 82</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf">UsageFault_IRQn</a> = -10, </div>
|
||
<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237"> 83</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237">SVCall_IRQn</a> = -5, </div>
|
||
<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c"> 84</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c">DebugMonitor_IRQn</a> = -4, </div>
|
||
<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2"> 85</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2">PendSV_IRQn</a> = -2, </div>
|
||
<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7"> 86</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a> = -1, </div>
|
||
<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span><span class="comment">/****** STM32 specific Interrupt Numbers **********************************************************************/</span></div>
|
||
<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a971089d7566ef902dfa0c80ac3a8fd52"> 88</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a971089d7566ef902dfa0c80ac3a8fd52">WWDG_IRQn</a> = 0, </div>
|
||
<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab0b51ffcc4dcf5661141b79c8e5bd924"> 89</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab0b51ffcc4dcf5661141b79c8e5bd924">PVD_IRQn</a> = 1, </div>
|
||
<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac127cca7ae48bcf93924209f04e5e5a1"> 90</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac127cca7ae48bcf93924209f04e5e5a1">TAMP_STAMP_IRQn</a> = 2, </div>
|
||
<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a173ccc3f31df1f7e43de2ddeab3d1777"> 91</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a173ccc3f31df1f7e43de2ddeab3d1777">RTC_WKUP_IRQn</a> = 3, </div>
|
||
<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a91b73963ce243a1d031576d49e137fab"> 92</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a91b73963ce243a1d031576d49e137fab">FLASH_IRQn</a> = 4, </div>
|
||
<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a5710b22392997bac63daa5c999730f77"> 93</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a5710b22392997bac63daa5c999730f77">RCC_IRQn</a> = 5, </div>
|
||
<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab6aa6f87d26bbc6cf99b067b8d75c2f7"> 94</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab6aa6f87d26bbc6cf99b067b8d75c2f7">EXTI0_IRQn</a> = 6, </div>
|
||
<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae4badcdecdb94eb10129c4c0577c5e19"> 95</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae4badcdecdb94eb10129c4c0577c5e19">EXTI1_IRQn</a> = 7, </div>
|
||
<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a082cb3f7839069a0715fd76c7eacbbc9"> 96</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a082cb3f7839069a0715fd76c7eacbbc9">EXTI2_IRQn</a> = 8, </div>
|
||
<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8add889c84ba5de466ced209069e05d602"> 97</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8add889c84ba5de466ced209069e05d602">EXTI3_IRQn</a> = 9, </div>
|
||
<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab70a40106ca4486770df5d2072d9ac0e"> 98</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab70a40106ca4486770df5d2072d9ac0e">EXTI4_IRQn</a> = 10, </div>
|
||
<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9ee33e72512c4cfb301b216f4fb9d68c"> 99</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9ee33e72512c4cfb301b216f4fb9d68c">DMA1_Stream0_IRQn</a> = 11, </div>
|
||
<div class="line"><a id="l00100" name="l00100"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa45ca2c955060e2c2a7cbbe1d6753285"> 100</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa45ca2c955060e2c2a7cbbe1d6753285">DMA1_Stream1_IRQn</a> = 12, </div>
|
||
<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0d9ec75e4478e70235b705d5a6b3efd8"> 101</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0d9ec75e4478e70235b705d5a6b3efd8">DMA1_Stream2_IRQn</a> = 13, </div>
|
||
<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af77770e080206a7558decf09344fb2e2"> 102</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af77770e080206a7558decf09344fb2e2">DMA1_Stream3_IRQn</a> = 14, </div>
|
||
<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aee2aaf365c6c297a63cee41ecae2301a"> 103</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aee2aaf365c6c297a63cee41ecae2301a">DMA1_Stream4_IRQn</a> = 15, </div>
|
||
<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac92efa72399fe58fa615d8bf8fd64a4e"> 104</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac92efa72399fe58fa615d8bf8fd64a4e">DMA1_Stream5_IRQn</a> = 16, </div>
|
||
<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aef5e2b68f62f6f1781fab894f0b8f486"> 105</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aef5e2b68f62f6f1781fab894f0b8f486">DMA1_Stream6_IRQn</a> = 17, </div>
|
||
<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4d69175258ae261dd545001e810421b3"> 106</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4d69175258ae261dd545001e810421b3">ADC_IRQn</a> = 18, </div>
|
||
<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9ceb5175f7c10cf436955173c2246877"> 107</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9ceb5175f7c10cf436955173c2246877">CAN1_TX_IRQn</a> = 19, </div>
|
||
<div class="line"><a id="l00108" name="l00108"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab6bf73ac43a9856b3f2759a59f3d25b5"> 108</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab6bf73ac43a9856b3f2759a59f3d25b5">CAN1_RX0_IRQn</a> = 20, </div>
|
||
<div class="line"><a id="l00109" name="l00109"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af71ef06c4f9ff0e1691c21ff3670acd4"> 109</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af71ef06c4f9ff0e1691c21ff3670acd4">CAN1_RX1_IRQn</a> = 21, </div>
|
||
<div class="line"><a id="l00110" name="l00110"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0f5f129d88a5606a378811e43039e274"> 110</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0f5f129d88a5606a378811e43039e274">CAN1_SCE_IRQn</a> = 22, </div>
|
||
<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa3aa50e0353871985facf62d055faa52"> 111</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa3aa50e0353871985facf62d055faa52">EXTI9_5_IRQn</a> = 23, </div>
|
||
<div class="line"><a id="l00112" name="l00112"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab35b4ce63cfb11453f84a3695c6df368"> 112</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab35b4ce63cfb11453f84a3695c6df368">TIM1_BRK_TIM9_IRQn</a> = 24, </div>
|
||
<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa3879e49013035601e17f83a51e0829f"> 113</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa3879e49013035601e17f83a51e0829f">TIM1_UP_TIM10_IRQn</a> = 25, </div>
|
||
<div class="line"><a id="l00114" name="l00114"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a744bdceb8eface6ff57dd036e608e"> 114</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a744bdceb8eface6ff57dd036e608e">TIM1_TRG_COM_TIM11_IRQn</a> = 26, </div>
|
||
<div class="line"><a id="l00115" name="l00115"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af312f0a21f600f9b286427e50c549ca9"> 115</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af312f0a21f600f9b286427e50c549ca9">TIM1_CC_IRQn</a> = 27, </div>
|
||
<div class="line"><a id="l00116" name="l00116"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3a4e2095a926e4095d3c846eb1c98afa"> 116</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3a4e2095a926e4095d3c846eb1c98afa">TIM2_IRQn</a> = 28, </div>
|
||
<div class="line"><a id="l00117" name="l00117"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a985574288f66e2a00e97387424a9a2d8"> 117</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a985574288f66e2a00e97387424a9a2d8">TIM3_IRQn</a> = 29, </div>
|
||
<div class="line"><a id="l00118" name="l00118"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a368b899ca740b9ae0d75841f3abf68c4"> 118</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a368b899ca740b9ae0d75841f3abf68c4">TIM4_IRQn</a> = 30, </div>
|
||
<div class="line"><a id="l00119" name="l00119"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9852dbbe8c014e716ce7e03a7b809751"> 119</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9852dbbe8c014e716ce7e03a7b809751">I2C1_EV_IRQn</a> = 31, </div>
|
||
<div class="line"><a id="l00120" name="l00120"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a2ec363869f4488782dc10a60abce3b34"> 120</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a2ec363869f4488782dc10a60abce3b34">I2C1_ER_IRQn</a> = 32, </div>
|
||
<div class="line"><a id="l00121" name="l00121"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3020193786527c47d2e4d8c92ceee804"> 121</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3020193786527c47d2e4d8c92ceee804">I2C2_EV_IRQn</a> = 33, </div>
|
||
<div class="line"><a id="l00122" name="l00122"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a60c35f2d48d512bd6818bc9fef7053d7"> 122</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a60c35f2d48d512bd6818bc9fef7053d7">I2C2_ER_IRQn</a> = 34, </div>
|
||
<div class="line"><a id="l00123" name="l00123"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aacdff1a9c42582ed663214cbe62c1174"> 123</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aacdff1a9c42582ed663214cbe62c1174">SPI1_IRQn</a> = 35, </div>
|
||
<div class="line"><a id="l00124" name="l00124"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a505fbd4ccf7c2a14c8b76dc9e58f7ede"> 124</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a505fbd4ccf7c2a14c8b76dc9e58f7ede">SPI2_IRQn</a> = 36, </div>
|
||
<div class="line"><a id="l00125" name="l00125"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ad97cb163e1f678367e37c50d54d161ab"> 125</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ad97cb163e1f678367e37c50d54d161ab">USART1_IRQn</a> = 37, </div>
|
||
<div class="line"><a id="l00126" name="l00126"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3f9c48714d0e5baaba6613343f0da68e"> 126</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3f9c48714d0e5baaba6613343f0da68e">USART2_IRQn</a> = 38, </div>
|
||
<div class="line"><a id="l00127" name="l00127"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8afb13802afc1f5fdf5c90e73ee99e5ff3"> 127</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8afb13802afc1f5fdf5c90e73ee99e5ff3">USART3_IRQn</a> = 39, </div>
|
||
<div class="line"><a id="l00128" name="l00128"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9fb0ad0c850234d1983fafdb17378e2f"> 128</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9fb0ad0c850234d1983fafdb17378e2f">EXTI15_10_IRQn</a> = 40, </div>
|
||
<div class="line"><a id="l00129" name="l00129"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8afe09d6563a21a1540f658163a76a3b37"> 129</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8afe09d6563a21a1540f658163a76a3b37">RTC_Alarm_IRQn</a> = 41, </div>
|
||
<div class="line"><a id="l00130" name="l00130"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa612f35c4440359c35acbaa3c1458c5f"> 130</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa612f35c4440359c35acbaa3c1458c5f">OTG_FS_WKUP_IRQn</a> = 42, </div>
|
||
<div class="line"><a id="l00131" name="l00131"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3e01328006d19f7d32354271b9f61dce"> 131</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3e01328006d19f7d32354271b9f61dce">TIM8_BRK_TIM12_IRQn</a> = 43, </div>
|
||
<div class="line"><a id="l00132" name="l00132"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa8d8f67a98f24de6f0b36ad6b1f29a7d"> 132</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa8d8f67a98f24de6f0b36ad6b1f29a7d">TIM8_UP_TIM13_IRQn</a> = 44, </div>
|
||
<div class="line"><a id="l00133" name="l00133"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae252b31c3a341acbe9a467e243137307"> 133</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae252b31c3a341acbe9a467e243137307">TIM8_TRG_COM_TIM14_IRQn</a> = 45, </div>
|
||
<div class="line"><a id="l00134" name="l00134"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a637750639eff4e2b4aae80ed6f3cf67f"> 134</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a637750639eff4e2b4aae80ed6f3cf67f">TIM8_CC_IRQn</a> = 46, </div>
|
||
<div class="line"><a id="l00135" name="l00135"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aedaa9c14e7e5fa9c0dcbb0c2455546e8"> 135</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aedaa9c14e7e5fa9c0dcbb0c2455546e8">DMA1_Stream7_IRQn</a> = 47, </div>
|
||
<div class="line"><a id="l00136" name="l00136"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a70450df88125476d5771f2ff3f562536"> 136</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a70450df88125476d5771f2ff3f562536">FSMC_IRQn</a> = 48, </div>
|
||
<div class="line"><a id="l00137" name="l00137"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a16fe70a39348f3f27906dc268b5654e3"> 137</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a16fe70a39348f3f27906dc268b5654e3">SDIO_IRQn</a> = 49, </div>
|
||
<div class="line"><a id="l00138" name="l00138"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aed2eb3f4bb721d55fcc1003125956645"> 138</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aed2eb3f4bb721d55fcc1003125956645">TIM5_IRQn</a> = 50, </div>
|
||
<div class="line"><a id="l00139" name="l00139"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4e9331739fb76a2ca7781fede070ae44"> 139</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4e9331739fb76a2ca7781fede070ae44">SPI3_IRQn</a> = 51, </div>
|
||
<div class="line"><a id="l00140" name="l00140"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aded5314b20c6e4e80cb6ab0668ffb8d5"> 140</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aded5314b20c6e4e80cb6ab0668ffb8d5">UART4_IRQn</a> = 52, </div>
|
||
<div class="line"><a id="l00141" name="l00141"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac55a11a64aae7432544d0ab0d4f7de09"> 141</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac55a11a64aae7432544d0ab0d4f7de09">UART5_IRQn</a> = 53, </div>
|
||
<div class="line"><a id="l00142" name="l00142"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a5f581e9aedfaccd9b1db9ec793804b45"> 142</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a5f581e9aedfaccd9b1db9ec793804b45">TIM6_DAC_IRQn</a> = 54, </div>
|
||
<div class="line"><a id="l00143" name="l00143"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a53cadc1e164ec85d0ea4cd143608e8e1"> 143</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a53cadc1e164ec85d0ea4cd143608e8e1">TIM7_IRQn</a> = 55, </div>
|
||
<div class="line"><a id="l00144" name="l00144"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a1e5055722630fd4b12aff421964c2ebb"> 144</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a1e5055722630fd4b12aff421964c2ebb">DMA2_Stream0_IRQn</a> = 56, </div>
|
||
<div class="line"><a id="l00145" name="l00145"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a98abb3f02c1feb3831706bc1b82307cb"> 145</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a98abb3f02c1feb3831706bc1b82307cb">DMA2_Stream1_IRQn</a> = 57, </div>
|
||
<div class="line"><a id="l00146" name="l00146"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8abf5e189f3ac7aad9f65e65ea5a0f3b36"> 146</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8abf5e189f3ac7aad9f65e65ea5a0f3b36">DMA2_Stream2_IRQn</a> = 58, </div>
|
||
<div class="line"><a id="l00147" name="l00147"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3ff8f3439f509e6e985eb960e63e1be4"> 147</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3ff8f3439f509e6e985eb960e63e1be4">DMA2_Stream3_IRQn</a> = 59, </div>
|
||
<div class="line"><a id="l00148" name="l00148"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae54eb8b30273b38a0576f75aba24eec0"> 148</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae54eb8b30273b38a0576f75aba24eec0">DMA2_Stream4_IRQn</a> = 60, </div>
|
||
<div class="line"><a id="l00149" name="l00149"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ad71328dd95461b7c55b568cf25966f6a"> 149</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ad71328dd95461b7c55b568cf25966f6a">ETH_IRQn</a> = 61, </div>
|
||
<div class="line"><a id="l00150" name="l00150"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0485578005e12c2e2c0fb253a844ec6f"> 150</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0485578005e12c2e2c0fb253a844ec6f">ETH_WKUP_IRQn</a> = 62, </div>
|
||
<div class="line"><a id="l00151" name="l00151"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af6b8fbc990ac71c8425647bb684788a4"> 151</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af6b8fbc990ac71c8425647bb684788a4">CAN2_TX_IRQn</a> = 63, </div>
|
||
<div class="line"><a id="l00152" name="l00152"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a851fd2f2ab1418710e7da80e1bdf348a"> 152</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a851fd2f2ab1418710e7da80e1bdf348a">CAN2_RX0_IRQn</a> = 64, </div>
|
||
<div class="line"><a id="l00153" name="l00153"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab5023ff845be31a488ab63a0b8cf2b7a"> 153</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab5023ff845be31a488ab63a0b8cf2b7a">CAN2_RX1_IRQn</a> = 65, </div>
|
||
<div class="line"><a id="l00154" name="l00154"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a56c0b5758f26f31494e74aab9273f9fd"> 154</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a56c0b5758f26f31494e74aab9273f9fd">CAN2_SCE_IRQn</a> = 66, </div>
|
||
<div class="line"><a id="l00155" name="l00155"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa60a30b7ef03446a46fd72e084911f7e"> 155</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa60a30b7ef03446a46fd72e084911f7e">OTG_FS_IRQn</a> = 67, </div>
|
||
<div class="line"><a id="l00156" name="l00156"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a933d4686213973abc01845a3da1c8a03"> 156</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a933d4686213973abc01845a3da1c8a03">DMA2_Stream5_IRQn</a> = 68, </div>
|
||
<div class="line"><a id="l00157" name="l00157"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a21570761ad0b5ed751adc831691b7800"> 157</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a21570761ad0b5ed751adc831691b7800">DMA2_Stream6_IRQn</a> = 69, </div>
|
||
<div class="line"><a id="l00158" name="l00158"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3d4cc0cd9b4d71e7ee002c4f8c1f8a77"> 158</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3d4cc0cd9b4d71e7ee002c4f8c1f8a77">DMA2_Stream7_IRQn</a> = 70, </div>
|
||
<div class="line"><a id="l00159" name="l00159"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa92bcb2bc3a87be869f05c5b07f04b8c"> 159</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa92bcb2bc3a87be869f05c5b07f04b8c">USART6_IRQn</a> = 71, </div>
|
||
<div class="line"><a id="l00160" name="l00160"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8326db2d570cb865ffa1d49fa29d562a"> 160</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8326db2d570cb865ffa1d49fa29d562a">I2C3_EV_IRQn</a> = 72, </div>
|
||
<div class="line"><a id="l00161" name="l00161"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6e954232d164a6942ebc7a6bd6f7736e"> 161</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6e954232d164a6942ebc7a6bd6f7736e">I2C3_ER_IRQn</a> = 73, </div>
|
||
<div class="line"><a id="l00162" name="l00162"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a60b6cc4b6dbeca39e29a475d26c9e080"> 162</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a60b6cc4b6dbeca39e29a475d26c9e080">OTG_HS_EP1_OUT_IRQn</a> = 74, </div>
|
||
<div class="line"><a id="l00163" name="l00163"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a1b040a7f76278a73cf5ea4c51f1be047"> 163</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a1b040a7f76278a73cf5ea4c51f1be047">OTG_HS_EP1_IN_IRQn</a> = 75, </div>
|
||
<div class="line"><a id="l00164" name="l00164"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9e5c9d81dd3985a88094f8158c0f0267"> 164</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9e5c9d81dd3985a88094f8158c0f0267">OTG_HS_WKUP_IRQn</a> = 76, </div>
|
||
<div class="line"><a id="l00165" name="l00165"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aad2d5e47d27fe3a02f7059b20bb729c0"> 165</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aad2d5e47d27fe3a02f7059b20bb729c0">OTG_HS_IRQn</a> = 77, </div>
|
||
<div class="line"><a id="l00166" name="l00166"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ace3c0fc2c4d05a7c02e3c987da5bc8e8"> 166</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ace3c0fc2c4d05a7c02e3c987da5bc8e8">DCMI_IRQn</a> = 78, </div>
|
||
<div class="line"><a id="l00167" name="l00167"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a90c4647e57cff99fac635c532802c4b5"> 167</a></span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a90c4647e57cff99fac635c532802c4b5">RNG_IRQn</a> = 80, </div>
|
||
<div class="line"><a id="l00168" name="l00168"></a><span class="lineno"> 168</span> <a class="code hl_enumvalue" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa6b8ff01b016a798c6e639728c179e4f">FPU_IRQn</a> = 81 </div>
|
||
<div class="line"><a id="l00169" name="l00169"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa6b8ff01b016a798c6e639728c179e4f"> 169</a></span>} <a class="code hl_enumeration" href="group___peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00170" name="l00170"></a><span class="lineno"> 170</span><span class="comment">/* Legacy define */</span></div>
|
||
<div class="line"><a id="l00171" name="l00171"></a><span class="lineno"><a class="line" href="group___peripheral__interrupt__number__definition.html#ga70479d84b2227bd03eca17d75ced09c1"> 171</a></span><span class="preprocessor">#define HASH_RNG_IRQn RNG_IRQn</span></div>
|
||
<div class="line"><a id="l00172" name="l00172"></a><span class="lineno"> 172</span> </div>
|
||
<div class="line"><a id="l00177" name="l00177"></a><span class="lineno"> 177</span><span class="preprocessor">#include "<a class="code" href="stdint_8h.html">stdint.h</a>"</span></div>
|
||
<div class="line"><a id="l00178" name="l00178"></a><span class="lineno"> 178</span><span class="preprocessor">#include "<a class="code" href="arm__defines_8h.html">arm_defines.h</a>"</span></div>
|
||
<div class="line"><a id="l00179" name="l00179"></a><span class="lineno"> 179</span><span class="preprocessor">#include "<a class="code" href="core__cm4__matlab_8h.html">core_cm4_matlab.h</a>"</span> <span class="comment">/* Cortex-M4 processor and core peripherals */</span></div>
|
||
<div class="line"><a id="l00180" name="l00180"></a><span class="lineno"> 180</span><span class="preprocessor">#include "<a class="code" href="system__stm32f4xx_8h.html">system_stm32f4xx.h</a>"</span></div>
|
||
<div class="line"><a id="l00181" name="l00181"></a><span class="lineno"> 181</span> </div>
|
||
<div class="foldopen" id="foldopen00190" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00190" name="l00190"></a><span class="lineno"><a class="line" href="struct_a_d_c___type_def.html"> 190</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00191" name="l00191"></a><span class="lineno"> 191</span>{</div>
|
||
<div class="line"><a id="l00192" name="l00192"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga081f4304e18753e5e8d0afd71ccca45e"> 192</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga081f4304e18753e5e8d0afd71ccca45e">SR</a>; </div>
|
||
<div class="line"><a id="l00193" name="l00193"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0"> 193</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0">CR1</a>; </div>
|
||
<div class="line"><a id="l00194" name="l00194"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586"> 194</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586">CR2</a>; </div>
|
||
<div class="line"><a id="l00195" name="l00195"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf9d6c604e365c7d9d7601bf4ef373498"> 195</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf9d6c604e365c7d9d7601bf4ef373498">SMPR1</a>; </div>
|
||
<div class="line"><a id="l00196" name="l00196"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6ac83fae8377c7b7fcae50fa4211b0e8"> 196</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6ac83fae8377c7b7fcae50fa4211b0e8">SMPR2</a>; </div>
|
||
<div class="line"><a id="l00197" name="l00197"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga427dda1678f254bd98b1f321d7194a3b"> 197</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga427dda1678f254bd98b1f321d7194a3b">JOFR1</a>; </div>
|
||
<div class="line"><a id="l00198" name="l00198"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga11e65074b9f06b48c17cdfa5bea9f125"> 198</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga11e65074b9f06b48c17cdfa5bea9f125">JOFR2</a>; </div>
|
||
<div class="line"><a id="l00199" name="l00199"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga613f6b76d20c1a513976b920ecd7f4f8"> 199</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga613f6b76d20c1a513976b920ecd7f4f8">JOFR3</a>; </div>
|
||
<div class="line"><a id="l00200" name="l00200"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2fd59854223e38158b4138ee8e913ab3"> 200</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2fd59854223e38158b4138ee8e913ab3">JOFR4</a>; </div>
|
||
<div class="line"><a id="l00201" name="l00201"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga24c3512abcc90ef75cf3e9145e5dbe9b"> 201</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga24c3512abcc90ef75cf3e9145e5dbe9b">HTR</a>; </div>
|
||
<div class="line"><a id="l00202" name="l00202"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9f8712dfef7125c0bb39db11f2b7416b"> 202</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9f8712dfef7125c0bb39db11f2b7416b">LTR</a>; </div>
|
||
<div class="line"><a id="l00203" name="l00203"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga3302e1bcfdfbbfeb58779d0761fb377c"> 203</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga3302e1bcfdfbbfeb58779d0761fb377c">SQR1</a>; </div>
|
||
<div class="line"><a id="l00204" name="l00204"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaab440b0ad8631f5666dd32768a89cf60"> 204</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaab440b0ad8631f5666dd32768a89cf60">SQR2</a>; </div>
|
||
<div class="line"><a id="l00205" name="l00205"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga97e40d9928fa25a5628d6442f0aa6c0f"> 205</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga97e40d9928fa25a5628d6442f0aa6c0f">SQR3</a>; </div>
|
||
<div class="line"><a id="l00206" name="l00206"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga75e0cc079831adcc051df456737d3ae4"> 206</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga75e0cc079831adcc051df456737d3ae4">JSQR</a>; </div>
|
||
<div class="line"><a id="l00207" name="l00207"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga22fa21352be442bd02f9c26a1013d598"> 207</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga22fa21352be442bd02f9c26a1013d598">JDR1</a>; </div>
|
||
<div class="line"><a id="l00208" name="l00208"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gae9156af81694b7a85923348be45a2167"> 208</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gae9156af81694b7a85923348be45a2167">JDR2</a>; </div>
|
||
<div class="line"><a id="l00209" name="l00209"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga3a54028253a75a470fccf841178cba46"> 209</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga3a54028253a75a470fccf841178cba46">JDR3</a>; </div>
|
||
<div class="line"><a id="l00210" name="l00210"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9274ceea3b2c6d5c1903d0a7abad91a1"> 210</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9274ceea3b2c6d5c1903d0a7abad91a1">JDR4</a>; </div>
|
||
<div class="line"><a id="l00211" name="l00211"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94"> 211</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94">DR</a>; </div>
|
||
<div class="line"><a id="l00212" name="l00212"></a><span class="lineno"> 212</span>} <a class="code hl_struct" href="struct_a_d_c___type_def.html">ADC_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00213" name="l00213"></a><span class="lineno"> 213</span> </div>
|
||
<div class="foldopen" id="foldopen00214" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00214" name="l00214"></a><span class="lineno"><a class="line" href="struct_a_d_c___common___type_def.html"> 214</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00215" name="l00215"></a><span class="lineno"> 215</span>{</div>
|
||
<div class="line"><a id="l00216" name="l00216"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga876dd0a8546697065f406b7543e27af2"> 216</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga876dd0a8546697065f406b7543e27af2">CSR</a>; </div>
|
||
<div class="line"><a id="l00217" name="l00217"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga5e1322e27c40bf91d172f9673f205c97"> 217</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga5e1322e27c40bf91d172f9673f205c97">CCR</a>; </div>
|
||
<div class="line"><a id="l00218" name="l00218"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga760f86a1a18dffffda54fc15a977979f"> 218</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga760f86a1a18dffffda54fc15a977979f">CDR</a>; </div>
|
||
<div class="line"><a id="l00220" name="l00220"></a><span class="lineno"> 220</span>} <a class="code hl_struct" href="struct_a_d_c___common___type_def.html">ADC_Common_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00221" name="l00221"></a><span class="lineno"> 221</span> </div>
|
||
<div class="line"><a id="l00222" name="l00222"></a><span class="lineno"> 222</span> </div>
|
||
<div class="foldopen" id="foldopen00227" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00227" name="l00227"></a><span class="lineno"><a class="line" href="struct_c_a_n___tx_mail_box___type_def.html"> 227</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00228" name="l00228"></a><span class="lineno"> 228</span>{</div>
|
||
<div class="line"><a id="l00229" name="l00229"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6921aa1c578a7d17c6e0eb33a73b6630"> 229</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6921aa1c578a7d17c6e0eb33a73b6630">TIR</a>; </div>
|
||
<div class="line"><a id="l00230" name="l00230"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaed87bed042dd9523ce086119a3bab0ea"> 230</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaed87bed042dd9523ce086119a3bab0ea">TDTR</a>; </div>
|
||
<div class="line"><a id="l00231" name="l00231"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaded1359e1a32512910bff534d57ade68"> 231</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaded1359e1a32512910bff534d57ade68">TDLR</a>; </div>
|
||
<div class="line"><a id="l00232" name="l00232"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga90f7c1cf22683459c632d6040366eddf"> 232</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga90f7c1cf22683459c632d6040366eddf">TDHR</a>; </div>
|
||
<div class="line"><a id="l00233" name="l00233"></a><span class="lineno"> 233</span>} <a class="code hl_struct" href="struct_c_a_n___tx_mail_box___type_def.html">CAN_TxMailBox_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00234" name="l00234"></a><span class="lineno"> 234</span> </div>
|
||
<div class="foldopen" id="foldopen00239" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00239" name="l00239"></a><span class="lineno"><a class="line" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html"> 239</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00240" name="l00240"></a><span class="lineno"> 240</span>{</div>
|
||
<div class="line"><a id="l00241" name="l00241"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga0acc8eb90b17bef5b9e03c7ddaacfb0b"> 241</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga0acc8eb90b17bef5b9e03c7ddaacfb0b">RIR</a>; </div>
|
||
<div class="line"><a id="l00242" name="l00242"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9563d8a88d0db403b8357331bea83a2e"> 242</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9563d8a88d0db403b8357331bea83a2e">RDTR</a>; </div>
|
||
<div class="line"><a id="l00243" name="l00243"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gae1c569688eedd49219cd505b9c22121b"> 243</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gae1c569688eedd49219cd505b9c22121b">RDLR</a>; </div>
|
||
<div class="line"><a id="l00244" name="l00244"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga7f11f42ba9d3bc5cd4a4f5ea0214608e"> 244</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga7f11f42ba9d3bc5cd4a4f5ea0214608e">RDHR</a>; </div>
|
||
<div class="line"><a id="l00245" name="l00245"></a><span class="lineno"> 245</span>} <a class="code hl_struct" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html">CAN_FIFOMailBox_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00246" name="l00246"></a><span class="lineno"> 246</span> </div>
|
||
<div class="foldopen" id="foldopen00251" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00251" name="l00251"></a><span class="lineno"><a class="line" href="struct_c_a_n___filter_register___type_def.html"> 251</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00252" name="l00252"></a><span class="lineno"> 252</span>{</div>
|
||
<div class="line"><a id="l00253" name="l00253"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga92036953ac673803fe001d843fea508b"> 253</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga92036953ac673803fe001d843fea508b">FR1</a>; </div>
|
||
<div class="line"><a id="l00254" name="l00254"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga7f7d80b45b7574463d7030fc8a464582"> 254</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga7f7d80b45b7574463d7030fc8a464582">FR2</a>; </div>
|
||
<div class="line"><a id="l00255" name="l00255"></a><span class="lineno"> 255</span>} <a class="code hl_struct" href="struct_c_a_n___filter_register___type_def.html">CAN_FilterRegister_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00256" name="l00256"></a><span class="lineno"> 256</span> </div>
|
||
<div class="foldopen" id="foldopen00261" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00261" name="l00261"></a><span class="lineno"><a class="line" href="struct_c_a_n___type_def.html"> 261</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00262" name="l00262"></a><span class="lineno"> 262</span>{</div>
|
||
<div class="line"><a id="l00263" name="l00263"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga27af4e9f888f0b7b1e8da7e002d98798"> 263</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga27af4e9f888f0b7b1e8da7e002d98798">MCR</a>; </div>
|
||
<div class="line"><a id="l00264" name="l00264"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gacdd4c1b5466be103fb2bb2a225b1d3a9"> 264</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gacdd4c1b5466be103fb2bb2a225b1d3a9">MSR</a>; </div>
|
||
<div class="line"><a id="l00265" name="l00265"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga87e3001757a0cd493785f1f3337dd0e8"> 265</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga87e3001757a0cd493785f1f3337dd0e8">TSR</a>; </div>
|
||
<div class="line"><a id="l00266" name="l00266"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaccf4141cee239380d0ad4634ee21dbf6"> 266</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaccf4141cee239380d0ad4634ee21dbf6">RF0R</a>; </div>
|
||
<div class="line"><a id="l00267" name="l00267"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga02b589bb589df4f39e549dca4d5abb08"> 267</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga02b589bb589df4f39e549dca4d5abb08">RF1R</a>; </div>
|
||
<div class="line"><a id="l00268" name="l00268"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6566f8cfbd1d8aa7e8db046aa35e77db"> 268</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6566f8cfbd1d8aa7e8db046aa35e77db">IER</a>; </div>
|
||
<div class="line"><a id="l00269" name="l00269"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2b39f943954e0e7d177b511d9074a0b7"> 269</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2b39f943954e0e7d177b511d9074a0b7">ESR</a>; </div>
|
||
<div class="line"><a id="l00270" name="l00270"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga5c0fcd3e7b4c59ab1dd68f6bd8f74e07"> 270</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga5c0fcd3e7b4c59ab1dd68f6bd8f74e07">BTR</a>; </div>
|
||
<div class="line"><a id="l00271" name="l00271"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaae28ab86a4ae57ed057ed1ea89a6d34b"> 271</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED0[88]; </div>
|
||
<div class="line"><a id="l00272" name="l00272"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gae37503ab1a7bbd29846f94cdadf0a9ef"> 272</a></span> <a class="code hl_struct" href="struct_c_a_n___tx_mail_box___type_def.html">CAN_TxMailBox_TypeDef</a> sTxMailBox[3]; </div>
|
||
<div class="line"><a id="l00273" name="l00273"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga21b030b34e131f7ef6ea273416449fe4"> 273</a></span> <a class="code hl_struct" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html">CAN_FIFOMailBox_TypeDef</a> sFIFOMailBox[2]; </div>
|
||
<div class="line"><a id="l00274" name="l00274"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga4bb07a7828fbd5fe86f6a5a3545c177d"> 274</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED1[12]; </div>
|
||
<div class="line"><a id="l00275" name="l00275"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1cb734df34f6520a7204c4c70634ebba"> 275</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1cb734df34f6520a7204c4c70634ebba">FMR</a>; </div>
|
||
<div class="line"><a id="l00276" name="l00276"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaaa6f4cf1f16aaa6d17ec6c410db76acf"> 276</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaaa6f4cf1f16aaa6d17ec6c410db76acf">FM1R</a>; </div>
|
||
<div class="line"><a id="l00277" name="l00277"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga4c9b972a304c0e08ca27cbe57627c496"> 277</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga4c9b972a304c0e08ca27cbe57627c496">RESERVED2</a>; </div>
|
||
<div class="line"><a id="l00278" name="l00278"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaae0256ae42106ee7f87fc7e5bdb779d4"> 278</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaae0256ae42106ee7f87fc7e5bdb779d4">FS1R</a>; </div>
|
||
<div class="line"><a id="l00279" name="l00279"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf2b40c5e36a5e861490988275499e158"> 279</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf2b40c5e36a5e861490988275499e158">RESERVED3</a>; </div>
|
||
<div class="line"><a id="l00280" name="l00280"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf1405e594e39e5b34f9499f680157a25"> 280</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf1405e594e39e5b34f9499f680157a25">FFA1R</a>; </div>
|
||
<div class="line"><a id="l00281" name="l00281"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac0018930ee9f18afda25b695b9a4ec16"> 281</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac0018930ee9f18afda25b695b9a4ec16">RESERVED4</a>; </div>
|
||
<div class="line"><a id="l00282" name="l00282"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaaf76271f4ab0b3deb3ceb6e2ac0d62d0"> 282</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaaf76271f4ab0b3deb3ceb6e2ac0d62d0">FA1R</a>; </div>
|
||
<div class="line"><a id="l00283" name="l00283"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga269f31b91d0f38a48061b76ecc346f55"> 283</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED5[8]; </div>
|
||
<div class="line"><a id="l00284" name="l00284"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga31bd74513e6e599319702ad34113bf59"> 284</a></span> <a class="code hl_struct" href="struct_c_a_n___filter_register___type_def.html">CAN_FilterRegister_TypeDef</a> sFilterRegister[28]; </div>
|
||
<div class="line"><a id="l00285" name="l00285"></a><span class="lineno"> 285</span>} <a class="code hl_struct" href="struct_c_a_n___type_def.html">CAN_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00286" name="l00286"></a><span class="lineno"> 286</span> </div>
|
||
<div class="foldopen" id="foldopen00291" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00291" name="l00291"></a><span class="lineno"><a class="line" href="struct_c_r_c___type_def.html"> 291</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00292" name="l00292"></a><span class="lineno"> 292</span>{</div>
|
||
<div class="line"><a id="l00293" name="l00293"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94"> 293</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94">DR</a>; </div>
|
||
<div class="line"><a id="l00294" name="l00294"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga601d7b0ba761c987db359b2d7173b7e0"> 294</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga601d7b0ba761c987db359b2d7173b7e0">IDR</a>; </div>
|
||
<div class="line"><a id="l00295" name="l00295"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaa7d2bd5481ee985778c410a7e5826b71"> 295</a></span> <a class="code hl_typedef" href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaa7d2bd5481ee985778c410a7e5826b71">RESERVED0</a>; </div>
|
||
<div class="line"><a id="l00296" name="l00296"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga8249a3955aace28d92109b391311eb30"> 296</a></span> <a class="code hl_typedef" href="stdint_8h.html#adf4d876453337156dde61095e1f20223">uint16_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga8249a3955aace28d92109b391311eb30">RESERVED1</a>; </div>
|
||
<div class="line"><a id="l00297" name="l00297"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a"> 297</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a">CR</a>; </div>
|
||
<div class="line"><a id="l00298" name="l00298"></a><span class="lineno"> 298</span>} <a class="code hl_struct" href="struct_c_r_c___type_def.html">CRC_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00299" name="l00299"></a><span class="lineno"> 299</span> </div>
|
||
<div class="foldopen" id="foldopen00304" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00304" name="l00304"></a><span class="lineno"><a class="line" href="struct_d_a_c___type_def.html"> 304</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00305" name="l00305"></a><span class="lineno"> 305</span>{</div>
|
||
<div class="line"><a id="l00306" name="l00306"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a"> 306</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a">CR</a>; </div>
|
||
<div class="line"><a id="l00307" name="l00307"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga896bbb7153af0b67ad772360feaceeb4"> 307</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga896bbb7153af0b67ad772360feaceeb4">SWTRIGR</a>; </div>
|
||
<div class="line"><a id="l00308" name="l00308"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac2bb55b037b800a25852736afdd7a258"> 308</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac2bb55b037b800a25852736afdd7a258">DHR12R1</a>; </div>
|
||
<div class="line"><a id="l00309" name="l00309"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gae9028b8bcb5118b7073165fb50fcd559"> 309</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gae9028b8bcb5118b7073165fb50fcd559">DHR12L1</a>; </div>
|
||
<div class="line"><a id="l00310" name="l00310"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gad0a200e12acad17a5c7d2059159ea7e1"> 310</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gad0a200e12acad17a5c7d2059159ea7e1">DHR8R1</a>; </div>
|
||
<div class="line"><a id="l00311" name="l00311"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga804c7e15dbb587c7ea25511f6a7809f7"> 311</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga804c7e15dbb587c7ea25511f6a7809f7">DHR12R2</a>; </div>
|
||
<div class="line"><a id="l00312" name="l00312"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2e45f9c9d67e384187b25334ba0a3e3d"> 312</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2e45f9c9d67e384187b25334ba0a3e3d">DHR12L2</a>; </div>
|
||
<div class="line"><a id="l00313" name="l00313"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga4c435f0e34ace4421241cd5c3ae87fc2"> 313</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga4c435f0e34ace4421241cd5c3ae87fc2">DHR8R2</a>; </div>
|
||
<div class="line"><a id="l00314" name="l00314"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1590b77e57f17e75193da259da72095e"> 314</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1590b77e57f17e75193da259da72095e">DHR12RD</a>; </div>
|
||
<div class="line"><a id="l00315" name="l00315"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gacc269320aff0a6482730224a4b641a59"> 315</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gacc269320aff0a6482730224a4b641a59">DHR12LD</a>; </div>
|
||
<div class="line"><a id="l00316" name="l00316"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9590269cba8412f1be96b0ddb846ef44"> 316</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9590269cba8412f1be96b0ddb846ef44">DHR8RD</a>; </div>
|
||
<div class="line"><a id="l00317" name="l00317"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaa710505be03a41981c35bacc7ce20746"> 317</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaa710505be03a41981c35bacc7ce20746">DOR1</a>; </div>
|
||
<div class="line"><a id="l00318" name="l00318"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaba9fb810b0cf6cbc1280c5c63be2418b"> 318</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaba9fb810b0cf6cbc1280c5c63be2418b">DOR2</a>; </div>
|
||
<div class="line"><a id="l00319" name="l00319"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360"> 319</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360">SR</a>; </div>
|
||
<div class="line"><a id="l00320" name="l00320"></a><span class="lineno"> 320</span>} <a class="code hl_struct" href="struct_d_a_c___type_def.html">DAC_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00321" name="l00321"></a><span class="lineno"> 321</span> </div>
|
||
<div class="foldopen" id="foldopen00326" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00326" name="l00326"></a><span class="lineno"><a class="line" href="struct_d_b_g_m_c_u___type_def.html"> 326</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00327" name="l00327"></a><span class="lineno"> 327</span>{</div>
|
||
<div class="line"><a id="l00328" name="l00328"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga24df28d0e440321b21f6f07b3bb93dea"> 328</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga24df28d0e440321b21f6f07b3bb93dea">IDCODE</a>; </div>
|
||
<div class="line"><a id="l00329" name="l00329"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a"> 329</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a">CR</a>; </div>
|
||
<div class="line"><a id="l00330" name="l00330"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga5eaefc557573ae7bdc632ef6b6d574b5"> 330</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga5eaefc557573ae7bdc632ef6b6d574b5">APB1FZ</a>; </div>
|
||
<div class="line"><a id="l00331" name="l00331"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga4628a8c32f97ef93b15b2b503ef90c75"> 331</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga4628a8c32f97ef93b15b2b503ef90c75">APB2FZ</a>; </div>
|
||
<div class="line"><a id="l00332" name="l00332"></a><span class="lineno"> 332</span>}<a class="code hl_struct" href="struct_d_b_g_m_c_u___type_def.html">DBGMCU_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00333" name="l00333"></a><span class="lineno"> 333</span> </div>
|
||
<div class="foldopen" id="foldopen00338" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00338" name="l00338"></a><span class="lineno"><a class="line" href="struct_d_c_m_i___type_def.html"> 338</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00339" name="l00339"></a><span class="lineno"> 339</span>{</div>
|
||
<div class="line"><a id="l00340" name="l00340"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a"> 340</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a">CR</a>; </div>
|
||
<div class="line"><a id="l00341" name="l00341"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360"> 341</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360">SR</a>; </div>
|
||
<div class="line"><a id="l00342" name="l00342"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaa196fddf0ba7d6e3ce29bdb04eb38b94"> 342</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaa196fddf0ba7d6e3ce29bdb04eb38b94">RISR</a>; </div>
|
||
<div class="line"><a id="l00343" name="l00343"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6566f8cfbd1d8aa7e8db046aa35e77db"> 343</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6566f8cfbd1d8aa7e8db046aa35e77db">IER</a>; </div>
|
||
<div class="line"><a id="l00344" name="l00344"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga524e134cec519206cb41d0545e382978"> 344</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga524e134cec519206cb41d0545e382978">MISR</a>; </div>
|
||
<div class="line"><a id="l00345" name="l00345"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga0a8c8230846fd8ff154b9fde8dfa0399"> 345</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga0a8c8230846fd8ff154b9fde8dfa0399">ICR</a>; </div>
|
||
<div class="line"><a id="l00346" name="l00346"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9cc4ec74be864c929261e0810f2fd7f0"> 346</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9cc4ec74be864c929261e0810f2fd7f0">ESCR</a>; </div>
|
||
<div class="line"><a id="l00347" name="l00347"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf751d49ef824c1636c78822ecae066f4"> 347</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf751d49ef824c1636c78822ecae066f4">ESUR</a>; </div>
|
||
<div class="line"><a id="l00348" name="l00348"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga919b70dd8762e44263a02dfbafc7b8ce"> 348</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga919b70dd8762e44263a02dfbafc7b8ce">CWSTRTR</a>; </div>
|
||
<div class="line"><a id="l00349" name="l00349"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaa3ccc5d081bbee3c61ae9aa5e0c83af9"> 349</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaa3ccc5d081bbee3c61ae9aa5e0c83af9">CWSIZER</a>; </div>
|
||
<div class="line"><a id="l00350" name="l00350"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94"> 350</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94">DR</a>; </div>
|
||
<div class="line"><a id="l00351" name="l00351"></a><span class="lineno"> 351</span>} <a class="code hl_struct" href="struct_d_c_m_i___type_def.html">DCMI_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00352" name="l00352"></a><span class="lineno"> 352</span> </div>
|
||
<div class="foldopen" id="foldopen00357" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00357" name="l00357"></a><span class="lineno"><a class="line" href="struct_d_m_a___stream___type_def.html"> 357</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00358" name="l00358"></a><span class="lineno"> 358</span>{</div>
|
||
<div class="line"><a id="l00359" name="l00359"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a"> 359</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a">CR</a>; </div>
|
||
<div class="line"><a id="l00360" name="l00360"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf60258ad5a25addc1e8969665d0c1731"> 360</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf60258ad5a25addc1e8969665d0c1731">NDTR</a>; </div>
|
||
<div class="line"><a id="l00361" name="l00361"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaef55be3d948c22dd32a97e8d4f8761fd"> 361</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaef55be3d948c22dd32a97e8d4f8761fd">PAR</a>; </div>
|
||
<div class="line"><a id="l00362" name="l00362"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga63b4d166f4ab5024db6b493a7ab7b640"> 362</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga63b4d166f4ab5024db6b493a7ab7b640">M0AR</a>; </div>
|
||
<div class="line"><a id="l00363" name="l00363"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaee7782244ceb4791d9a3891804ac47ac"> 363</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaee7782244ceb4791d9a3891804ac47ac">M1AR</a>; </div>
|
||
<div class="line"><a id="l00364" name="l00364"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga5d5cc7f32884945503dd29f8f6cbb415"> 364</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga5d5cc7f32884945503dd29f8f6cbb415">FCR</a>; </div>
|
||
<div class="line"><a id="l00365" name="l00365"></a><span class="lineno"> 365</span>} <a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00366" name="l00366"></a><span class="lineno"> 366</span> </div>
|
||
<div class="foldopen" id="foldopen00367" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00367" name="l00367"></a><span class="lineno"><a class="line" href="struct_d_m_a___type_def.html"> 367</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00368" name="l00368"></a><span class="lineno"> 368</span>{</div>
|
||
<div class="line"><a id="l00369" name="l00369"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga5cdef358e9e95b570358e1f6a3a7f492"> 369</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga5cdef358e9e95b570358e1f6a3a7f492">LISR</a>; </div>
|
||
<div class="line"><a id="l00370" name="l00370"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6fe40f7ac1a18c2726b328b5ec02b262"> 370</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6fe40f7ac1a18c2726b328b5ec02b262">HISR</a>; </div>
|
||
<div class="line"><a id="l00371" name="l00371"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac4f7bf4cb172024bfc940c00167cd04e"> 371</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac4f7bf4cb172024bfc940c00167cd04e">LIFCR</a>; </div>
|
||
<div class="line"><a id="l00372" name="l00372"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac55c27aeea4107813c1e7da3fcf46961"> 372</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac55c27aeea4107813c1e7da3fcf46961">HIFCR</a>; </div>
|
||
<div class="line"><a id="l00373" name="l00373"></a><span class="lineno"> 373</span>} <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00374" name="l00374"></a><span class="lineno"> 374</span> </div>
|
||
<div class="foldopen" id="foldopen00379" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00379" name="l00379"></a><span class="lineno"><a class="line" href="struct_e_t_h___type_def.html"> 379</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00380" name="l00380"></a><span class="lineno"> 380</span>{</div>
|
||
<div class="line"><a id="l00381" name="l00381"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga20acbcac1c35f66de94c9ff0e2ddc7b0"> 381</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga20acbcac1c35f66de94c9ff0e2ddc7b0">MACCR</a>;</div>
|
||
<div class="line"><a id="l00382" name="l00382"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga8ad4e3dbde1518ecde5d979c2a89a76a"> 382</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga8ad4e3dbde1518ecde5d979c2a89a76a">MACFFR</a>;</div>
|
||
<div class="line"><a id="l00383" name="l00383"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga121212bdb227106df681d24e5d896a4e"> 383</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga121212bdb227106df681d24e5d896a4e">MACHTHR</a>;</div>
|
||
<div class="line"><a id="l00384" name="l00384"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1d34ab8e5c2041c00ba9526b3958099d"> 384</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1d34ab8e5c2041c00ba9526b3958099d">MACHTLR</a>;</div>
|
||
<div class="line"><a id="l00385" name="l00385"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9ea1e1c6615eb3bd70eb328dba65fc87"> 385</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9ea1e1c6615eb3bd70eb328dba65fc87">MACMIIAR</a>;</div>
|
||
<div class="line"><a id="l00386" name="l00386"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga87c7687c35332bf5ee86473043652146"> 386</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga87c7687c35332bf5ee86473043652146">MACMIIDR</a>;</div>
|
||
<div class="line"><a id="l00387" name="l00387"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga12f62d3d3b9ee30c20c324b146e72795"> 387</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga12f62d3d3b9ee30c20c324b146e72795">MACFCR</a>;</div>
|
||
<div class="line"><a id="l00388" name="l00388"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga92ff1fe799bb33d13efbaa1195867781"> 388</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga92ff1fe799bb33d13efbaa1195867781">MACVLANTR</a>; <span class="comment">/* 8 */</span></div>
|
||
<div class="line"><a id="l00389" name="l00389"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga8be676577db129a84a9a2689519a8502"> 389</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED0[2];</div>
|
||
<div class="line"><a id="l00390" name="l00390"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga129dcc23d48588d5af7dd218b617933d"> 390</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga129dcc23d48588d5af7dd218b617933d">MACRWUFFR</a>; <span class="comment">/* 11 */</span></div>
|
||
<div class="line"><a id="l00391" name="l00391"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gabbb2f4f89e7d8c3242365b4506e43217"> 391</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gabbb2f4f89e7d8c3242365b4506e43217">MACPMTCSR</a>;</div>
|
||
<div class="line"><a id="l00392" name="l00392"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac4ac04e673b5b8320d53f7b0947db902"> 392</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac4ac04e673b5b8320d53f7b0947db902">RESERVED1</a>;</div>
|
||
<div class="line"><a id="l00393" name="l00393"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga8f35b3865c1f5fce934c1d48b9a63442"> 393</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga8f35b3865c1f5fce934c1d48b9a63442">MACDBGR</a>;</div>
|
||
<div class="line"><a id="l00394" name="l00394"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1173127526cca9128e409bc83c7729dc"> 394</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1173127526cca9128e409bc83c7729dc">MACSR</a>; <span class="comment">/* 15 */</span></div>
|
||
<div class="line"><a id="l00395" name="l00395"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac42b829c02429cb9363563f7eb9d58ed"> 395</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac42b829c02429cb9363563f7eb9d58ed">MACIMR</a>;</div>
|
||
<div class="line"><a id="l00396" name="l00396"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab8b4520c137846f0a128146144514419"> 396</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab8b4520c137846f0a128146144514419">MACA0HR</a>;</div>
|
||
<div class="line"><a id="l00397" name="l00397"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga45e8169adb601f00e411b840f9fbb5af"> 397</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga45e8169adb601f00e411b840f9fbb5af">MACA0LR</a>;</div>
|
||
<div class="line"><a id="l00398" name="l00398"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga3a6cc81e1024f9a93ec7653d32f12dcb"> 398</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga3a6cc81e1024f9a93ec7653d32f12dcb">MACA1HR</a>;</div>
|
||
<div class="line"><a id="l00399" name="l00399"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaadfb486dd07e2fd02fb491733deffd9b"> 399</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaadfb486dd07e2fd02fb491733deffd9b">MACA1LR</a>;</div>
|
||
<div class="line"><a id="l00400" name="l00400"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga38f1ce04678d5141e115cfd6f7b803d1"> 400</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga38f1ce04678d5141e115cfd6f7b803d1">MACA2HR</a>;</div>
|
||
<div class="line"><a id="l00401" name="l00401"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga423b12ab536a1c4fdb1ce63f645822a7"> 401</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga423b12ab536a1c4fdb1ce63f645822a7">MACA2LR</a>;</div>
|
||
<div class="line"><a id="l00402" name="l00402"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gad02ff09f7ce33f093ad04b84fee2bdec"> 402</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gad02ff09f7ce33f093ad04b84fee2bdec">MACA3HR</a>;</div>
|
||
<div class="line"><a id="l00403" name="l00403"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2ba9f73c7fa756305d54a8f80872c6df"> 403</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2ba9f73c7fa756305d54a8f80872c6df">MACA3LR</a>; <span class="comment">/* 24 */</span></div>
|
||
<div class="line"><a id="l00404" name="l00404"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1cf0d9299ef58b327f4e3d03da1c1aaf"> 404</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED2[40];</div>
|
||
<div class="line"><a id="l00405" name="l00405"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gad57490cb3a07132702f96d8b5d547c89"> 405</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gad57490cb3a07132702f96d8b5d547c89">MMCCR</a>; <span class="comment">/* 65 */</span></div>
|
||
<div class="line"><a id="l00406" name="l00406"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaea29ac183c979d0cb95ad3781fe9ed91"> 406</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaea29ac183c979d0cb95ad3781fe9ed91">MMCRIR</a>;</div>
|
||
<div class="line"><a id="l00407" name="l00407"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga614e0b81fce7cf218a357f8a0a3de7b8"> 407</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga614e0b81fce7cf218a357f8a0a3de7b8">MMCTIR</a>;</div>
|
||
<div class="line"><a id="l00408" name="l00408"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga63872a3017c14a869c647123573dd002"> 408</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga63872a3017c14a869c647123573dd002">MMCRIMR</a>;</div>
|
||
<div class="line"><a id="l00409" name="l00409"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga18e294dd2625a93ebf2aab9f2b3c4911"> 409</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga18e294dd2625a93ebf2aab9f2b3c4911">MMCTIMR</a>; <span class="comment">/* 69 */</span></div>
|
||
<div class="line"><a id="l00410" name="l00410"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf6446adf612691721c62fc68aff4fe39"> 410</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED3[14];</div>
|
||
<div class="line"><a id="l00411" name="l00411"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga23970354d69354ab78165e76afd6c2f7"> 411</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga23970354d69354ab78165e76afd6c2f7">MMCTGFSCCR</a>; <span class="comment">/* 84 */</span></div>
|
||
<div class="line"><a id="l00412" name="l00412"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga50c8425cf8d27268b3272ace0a224a94"> 412</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga50c8425cf8d27268b3272ace0a224a94">MMCTGFMSCCR</a>;</div>
|
||
<div class="line"><a id="l00413" name="l00413"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gabca175d3acfbc2a0806452fd57ea5fc4"> 413</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED4[5];</div>
|
||
<div class="line"><a id="l00414" name="l00414"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga71d932b554a5548e5d85ed81e58c1ed0"> 414</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga71d932b554a5548e5d85ed81e58c1ed0">MMCTGFCR</a>;</div>
|
||
<div class="line"><a id="l00415" name="l00415"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga3c1a316c73bb5f0eae7fbe66177cbca6"> 415</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED5[10];</div>
|
||
<div class="line"><a id="l00416" name="l00416"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaff6eeec1afa983f153ff0786c8902d43"> 416</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaff6eeec1afa983f153ff0786c8902d43">MMCRFCECR</a>;</div>
|
||
<div class="line"><a id="l00417" name="l00417"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga65bb525a3f4d3ee131f9a7ed899d5eef"> 417</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga65bb525a3f4d3ee131f9a7ed899d5eef">MMCRFAECR</a>;</div>
|
||
<div class="line"><a id="l00418" name="l00418"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga7e9a9bba62d1d98e3058b29a892b3877"> 418</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED6[10];</div>
|
||
<div class="line"><a id="l00419" name="l00419"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6ff264b60a3b40f40d136288e5ec5ba8"> 419</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6ff264b60a3b40f40d136288e5ec5ba8">MMCRGUFCR</a>;</div>
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||
<div class="line"><a id="l00420" name="l00420"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab1b7eacec3f164ed04001e9c806f73f9"> 420</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED7[334];</div>
|
||
<div class="line"><a id="l00421" name="l00421"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaa657aa42398bc8294976632d778b6db4"> 421</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaa657aa42398bc8294976632d778b6db4">PTPTSCR</a>;</div>
|
||
<div class="line"><a id="l00422" name="l00422"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf34b7e8815984e272daa3f089014af4e"> 422</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf34b7e8815984e272daa3f089014af4e">PTPSSIR</a>;</div>
|
||
<div class="line"><a id="l00423" name="l00423"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1ebbda0d742e80ca3d53edfa3a95f627"> 423</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1ebbda0d742e80ca3d53edfa3a95f627">PTPTSHR</a>;</div>
|
||
<div class="line"><a id="l00424" name="l00424"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga55c1058cd74dba0ed0cb8963684b9199"> 424</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga55c1058cd74dba0ed0cb8963684b9199">PTPTSLR</a>;</div>
|
||
<div class="line"><a id="l00425" name="l00425"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gae8e4ef158db1de28bfd759e40677ba4c"> 425</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gae8e4ef158db1de28bfd759e40677ba4c">PTPTSHUR</a>;</div>
|
||
<div class="line"><a id="l00426" name="l00426"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga646bf44e807d10a09f980ace333d33ab"> 426</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga646bf44e807d10a09f980ace333d33ab">PTPTSLUR</a>;</div>
|
||
<div class="line"><a id="l00427" name="l00427"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga8f47c0f21e22b98bbc2c9f3b6342fbb8"> 427</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga8f47c0f21e22b98bbc2c9f3b6342fbb8">PTPTSAR</a>;</div>
|
||
<div class="line"><a id="l00428" name="l00428"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf90723c7aee9c32113a2667b0a5c69f1"> 428</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf90723c7aee9c32113a2667b0a5c69f1">PTPTTHR</a>;</div>
|
||
<div class="line"><a id="l00429" name="l00429"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga28e7b0195ce457d20f585f6587fc1cb8"> 429</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga28e7b0195ce457d20f585f6587fc1cb8">PTPTTLR</a>;</div>
|
||
<div class="line"><a id="l00430" name="l00430"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2e60bc2eefc18398fb2459d1b44453e5"> 430</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2e60bc2eefc18398fb2459d1b44453e5">RESERVED8</a>;</div>
|
||
<div class="line"><a id="l00431" name="l00431"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gadca0624d09f2c72eee9807cea80a4d0c"> 431</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gadca0624d09f2c72eee9807cea80a4d0c">PTPTSSR</a>;</div>
|
||
<div class="line"><a id="l00432" name="l00432"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gae62fffd7d8f9f69b15edacdea4ba27f2"> 432</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED9[565];</div>
|
||
<div class="line"><a id="l00433" name="l00433"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gad1e11eb1200e64e0563e3576bf258194"> 433</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gad1e11eb1200e64e0563e3576bf258194">DMABMR</a>;</div>
|
||
<div class="line"><a id="l00434" name="l00434"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gacf0114902a52b7ffcc343e06484b3623"> 434</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gacf0114902a52b7ffcc343e06484b3623">DMATPDR</a>;</div>
|
||
<div class="line"><a id="l00435" name="l00435"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaad6309afe126da26921191697d7e5c43"> 435</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaad6309afe126da26921191697d7e5c43">DMARPDR</a>;</div>
|
||
<div class="line"><a id="l00436" name="l00436"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga581ce491c035ce46db723260377c2032"> 436</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga581ce491c035ce46db723260377c2032">DMARDLAR</a>;</div>
|
||
<div class="line"><a id="l00437" name="l00437"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga7dba9527df73350f35683140d73a5f8d"> 437</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga7dba9527df73350f35683140d73a5f8d">DMATDLAR</a>;</div>
|
||
<div class="line"><a id="l00438" name="l00438"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9e7c3d04e4dcf975939eeaac246b25d0"> 438</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9e7c3d04e4dcf975939eeaac246b25d0">DMASR</a>;</div>
|
||
<div class="line"><a id="l00439" name="l00439"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaa15b972f30ee47f5df0d3ebc8866509d"> 439</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaa15b972f30ee47f5df0d3ebc8866509d">DMAOMR</a>;</div>
|
||
<div class="line"><a id="l00440" name="l00440"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gadd56f3652fd065c6797411e80477a064"> 440</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gadd56f3652fd065c6797411e80477a064">DMAIER</a>;</div>
|
||
<div class="line"><a id="l00441" name="l00441"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga12eba1fc5d54aa50fdda201f7f9a84a3"> 441</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga12eba1fc5d54aa50fdda201f7f9a84a3">DMAMFBOCR</a>;</div>
|
||
<div class="line"><a id="l00442" name="l00442"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac6fe9e194ed9d08bf6bd28ceb80ac4b0"> 442</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac6fe9e194ed9d08bf6bd28ceb80ac4b0">DMARSWTR</a>;</div>
|
||
<div class="line"><a id="l00443" name="l00443"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga57d552323802fb4dd0bac95a02e814f0"> 443</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED10[8];</div>
|
||
<div class="line"><a id="l00444" name="l00444"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab5bb348210fdd9a5538eb57abc5a5673"> 444</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab5bb348210fdd9a5538eb57abc5a5673">DMACHTDR</a>;</div>
|
||
<div class="line"><a id="l00445" name="l00445"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9c49de2e699886d6604fd2b3d376a0e9"> 445</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9c49de2e699886d6604fd2b3d376a0e9">DMACHRDR</a>;</div>
|
||
<div class="line"><a id="l00446" name="l00446"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga900f9f888342fbdd8ee07e3ee1d4b73c"> 446</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga900f9f888342fbdd8ee07e3ee1d4b73c">DMACHTBAR</a>;</div>
|
||
<div class="line"><a id="l00447" name="l00447"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gacf3f7ecbf774d8d505655ac7f24761fc"> 447</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gacf3f7ecbf774d8d505655ac7f24761fc">DMACHRBAR</a>;</div>
|
||
<div class="line"><a id="l00448" name="l00448"></a><span class="lineno"> 448</span>} <a class="code hl_struct" href="struct_e_t_h___type_def.html">ETH_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00449" name="l00449"></a><span class="lineno"> 449</span> </div>
|
||
<div class="foldopen" id="foldopen00454" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00454" name="l00454"></a><span class="lineno"><a class="line" href="struct_e_x_t_i___type_def.html"> 454</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00455" name="l00455"></a><span class="lineno"> 455</span>{</div>
|
||
<div class="line"><a id="l00456" name="l00456"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gae845b86e973b4bf8a33c447c261633f6"> 456</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gae845b86e973b4bf8a33c447c261633f6">IMR</a>; </div>
|
||
<div class="line"><a id="l00457" name="l00457"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6034c7458d8e6030f6dacecf0f1a3a89"> 457</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6034c7458d8e6030f6dacecf0f1a3a89">EMR</a>; </div>
|
||
<div class="line"><a id="l00458" name="l00458"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga0d952a17455687d6e9053730d028fa1d"> 458</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga0d952a17455687d6e9053730d028fa1d">RTSR</a>; </div>
|
||
<div class="line"><a id="l00459" name="l00459"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaa0f7c828c46ae6f6bc9f66f11720bbe6"> 459</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaa0f7c828c46ae6f6bc9f66f11720bbe6">FTSR</a>; </div>
|
||
<div class="line"><a id="l00460" name="l00460"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9eae93b6cc13d4d25e12f2224e2369c9"> 460</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9eae93b6cc13d4d25e12f2224e2369c9">SWIER</a>; </div>
|
||
<div class="line"><a id="l00461" name="l00461"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf8d25514079514d38c104402f46470af"> 461</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf8d25514079514d38c104402f46470af">PR</a>; </div>
|
||
<div class="line"><a id="l00462" name="l00462"></a><span class="lineno"> 462</span>} <a class="code hl_struct" href="struct_e_x_t_i___type_def.html">EXTI_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00463" name="l00463"></a><span class="lineno"> 463</span> </div>
|
||
<div class="foldopen" id="foldopen00468" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00468" name="l00468"></a><span class="lineno"><a class="line" href="struct_f_l_a_s_h___type_def.html"> 468</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00469" name="l00469"></a><span class="lineno"> 469</span>{</div>
|
||
<div class="line"><a id="l00470" name="l00470"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9cb55206b29a8c16354747c556ab8bea"> 470</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9cb55206b29a8c16354747c556ab8bea">ACR</a>; </div>
|
||
<div class="line"><a id="l00471" name="l00471"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga84c491be6c66b1d5b6a2efd0740b3d0c"> 471</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga84c491be6c66b1d5b6a2efd0740b3d0c">KEYR</a>; </div>
|
||
<div class="line"><a id="l00472" name="l00472"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gafc4900646681dfe1ca43133d376c4423"> 472</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gafc4900646681dfe1ca43133d376c4423">OPTKEYR</a>; </div>
|
||
<div class="line"><a id="l00473" name="l00473"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360"> 473</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360">SR</a>; </div>
|
||
<div class="line"><a id="l00474" name="l00474"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a"> 474</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a">CR</a>; </div>
|
||
<div class="line"><a id="l00475" name="l00475"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gacfef9b6d7da4271943edc04d7dfdf595"> 475</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gacfef9b6d7da4271943edc04d7dfdf595">OPTCR</a>; </div>
|
||
<div class="line"><a id="l00476" name="l00476"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1dddf235f246a1d4e7e5084cd51e2dd0"> 476</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1dddf235f246a1d4e7e5084cd51e2dd0">OPTCR1</a>; </div>
|
||
<div class="line"><a id="l00477" name="l00477"></a><span class="lineno"> 477</span>} <a class="code hl_struct" href="struct_f_l_a_s_h___type_def.html">FLASH_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00478" name="l00478"></a><span class="lineno"> 478</span> </div>
|
||
<div class="line"><a id="l00479" name="l00479"></a><span class="lineno"> 479</span> </div>
|
||
<div class="line"><a id="l00480" name="l00480"></a><span class="lineno"> 480</span> </div>
|
||
<div class="foldopen" id="foldopen00485" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00485" name="l00485"></a><span class="lineno"><a class="line" href="struct_f_s_m_c___bank1___type_def.html"> 485</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00486" name="l00486"></a><span class="lineno"> 486</span>{</div>
|
||
<div class="line"><a id="l00487" name="l00487"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga80a6708b507f6eecbc10424fdb088b79"> 487</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> BTCR[8]; </div>
|
||
<div class="line"><a id="l00488" name="l00488"></a><span class="lineno"> 488</span>} <a class="code hl_struct" href="struct_f_s_m_c___bank1___type_def.html">FSMC_Bank1_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00489" name="l00489"></a><span class="lineno"> 489</span> </div>
|
||
<div class="foldopen" id="foldopen00494" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00494" name="l00494"></a><span class="lineno"><a class="line" href="struct_f_s_m_c___bank1_e___type_def.html"> 494</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00495" name="l00495"></a><span class="lineno"> 495</span>{</div>
|
||
<div class="line"><a id="l00496" name="l00496"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga20f13b79c0f8670af319af0c5ebd5c91"> 496</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> BWTR[7]; </div>
|
||
<div class="line"><a id="l00497" name="l00497"></a><span class="lineno"> 497</span>} <a class="code hl_struct" href="struct_f_s_m_c___bank1_e___type_def.html">FSMC_Bank1E_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00498" name="l00498"></a><span class="lineno"> 498</span> </div>
|
||
<div class="foldopen" id="foldopen00503" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00503" name="l00503"></a><span class="lineno"><a class="line" href="struct_f_s_m_c___bank2__3___type_def.html"> 503</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00504" name="l00504"></a><span class="lineno"> 504</span>{</div>
|
||
<div class="line"><a id="l00505" name="l00505"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab0cb1d704ee64c62ad5be55522a2683a"> 505</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab0cb1d704ee64c62ad5be55522a2683a">PCR2</a>; </div>
|
||
<div class="line"><a id="l00506" name="l00506"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga89623ee198737b29dc0a803310605a83"> 506</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga89623ee198737b29dc0a803310605a83">SR2</a>; </div>
|
||
<div class="line"><a id="l00507" name="l00507"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2e5a7a96de68a6612affa6df8c309c3d"> 507</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2e5a7a96de68a6612affa6df8c309c3d">PMEM2</a>; </div>
|
||
<div class="line"><a id="l00508" name="l00508"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9c1bc909ec5ed32df45444488ea6668b"> 508</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9c1bc909ec5ed32df45444488ea6668b">PATT2</a>; </div>
|
||
<div class="line"><a id="l00509" name="l00509"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf86c61a5d38a4fc9cef942a12744486b"> 509</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf86c61a5d38a4fc9cef942a12744486b">RESERVED0</a>; </div>
|
||
<div class="line"><a id="l00510" name="l00510"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga05a47a1664adc7a3db3fa3e83fe883b4"> 510</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga05a47a1664adc7a3db3fa3e83fe883b4">ECCR2</a>; </div>
|
||
<div class="line"><a id="l00511" name="l00511"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac4ac04e673b5b8320d53f7b0947db902"> 511</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac4ac04e673b5b8320d53f7b0947db902">RESERVED1</a>; </div>
|
||
<div class="line"><a id="l00512" name="l00512"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga4c9b972a304c0e08ca27cbe57627c496"> 512</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga4c9b972a304c0e08ca27cbe57627c496">RESERVED2</a>; </div>
|
||
<div class="line"><a id="l00513" name="l00513"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga73861fa74b83973fa1b5f92735c042ef"> 513</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga73861fa74b83973fa1b5f92735c042ef">PCR3</a>; </div>
|
||
<div class="line"><a id="l00514" name="l00514"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf30c34f7c606cb9416a413ec5fa36491"> 514</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf30c34f7c606cb9416a413ec5fa36491">SR3</a>; </div>
|
||
<div class="line"><a id="l00515" name="l00515"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaba8981e4f06cfb3db7d9959242052f80"> 515</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaba8981e4f06cfb3db7d9959242052f80">PMEM3</a>; </div>
|
||
<div class="line"><a id="l00516" name="l00516"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaba03fea9c1bb2242d963e29f1b94d25e"> 516</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaba03fea9c1bb2242d963e29f1b94d25e">PATT3</a>; </div>
|
||
<div class="line"><a id="l00517" name="l00517"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf2b40c5e36a5e861490988275499e158"> 517</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf2b40c5e36a5e861490988275499e158">RESERVED3</a>; </div>
|
||
<div class="line"><a id="l00518" name="l00518"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6062be7dc144c07e01c303cb49d69ce2"> 518</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6062be7dc144c07e01c303cb49d69ce2">ECCR3</a>; </div>
|
||
<div class="line"><a id="l00519" name="l00519"></a><span class="lineno"> 519</span>} <a class="code hl_struct" href="struct_f_s_m_c___bank2__3___type_def.html">FSMC_Bank2_3_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00520" name="l00520"></a><span class="lineno"> 520</span> </div>
|
||
<div class="foldopen" id="foldopen00525" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00525" name="l00525"></a><span class="lineno"><a class="line" href="struct_f_s_m_c___bank4___type_def.html"> 525</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00526" name="l00526"></a><span class="lineno"> 526</span>{</div>
|
||
<div class="line"><a id="l00527" name="l00527"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2f02e7acfbd7e549ede84633215eb6a1"> 527</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2f02e7acfbd7e549ede84633215eb6a1">PCR4</a>; </div>
|
||
<div class="line"><a id="l00528" name="l00528"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga8218d6e11dae5d4468c69303dec0b4fc"> 528</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga8218d6e11dae5d4468c69303dec0b4fc">SR4</a>; </div>
|
||
<div class="line"><a id="l00529" name="l00529"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga3f82cc749845fb0dd7dfa8121d96b663"> 529</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga3f82cc749845fb0dd7dfa8121d96b663">PMEM4</a>; </div>
|
||
<div class="line"><a id="l00530" name="l00530"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga955cad1aab7fb2d5b6e216cb29b5e7e2"> 530</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga955cad1aab7fb2d5b6e216cb29b5e7e2">PATT4</a>; </div>
|
||
<div class="line"><a id="l00531" name="l00531"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac53cd7a08093a4ae8f4de4bcff67a64f"> 531</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac53cd7a08093a4ae8f4de4bcff67a64f">PIO4</a>; </div>
|
||
<div class="line"><a id="l00532" name="l00532"></a><span class="lineno"> 532</span>} <a class="code hl_struct" href="struct_f_s_m_c___bank4___type_def.html">FSMC_Bank4_TypeDef</a>; </div>
|
||
</div>
|
||
<div class="line"><a id="l00533" name="l00533"></a><span class="lineno"> 533</span> </div>
|
||
<div class="foldopen" id="foldopen00538" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00538" name="l00538"></a><span class="lineno"><a class="line" href="struct_g_p_i_o___type_def.html"> 538</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00539" name="l00539"></a><span class="lineno"> 539</span>{</div>
|
||
<div class="line"><a id="l00540" name="l00540"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2b671a94c63a612f81e0e9de8152d01c"> 540</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2b671a94c63a612f81e0e9de8152d01c">MODER</a>; </div>
|
||
<div class="line"><a id="l00541" name="l00541"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9543592bda60cb5261075594bdeedac9"> 541</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9543592bda60cb5261075594bdeedac9">OTYPER</a>; </div>
|
||
<div class="line"><a id="l00542" name="l00542"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga328d16cc6213783ede54e4059ffd50a3"> 542</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga328d16cc6213783ede54e4059ffd50a3">OSPEEDR</a>; </div>
|
||
<div class="line"><a id="l00543" name="l00543"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gabeed38529bd7b8de082e490e5d4f1727"> 543</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gabeed38529bd7b8de082e490e5d4f1727">PUPDR</a>; </div>
|
||
<div class="line"><a id="l00544" name="l00544"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga328d2fe9ef1d513c3a97d30f98f0047c"> 544</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga328d2fe9ef1d513c3a97d30f98f0047c">IDR</a>; </div>
|
||
<div class="line"><a id="l00545" name="l00545"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gabff7fffd2b5a718715a130006590c75c"> 545</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gabff7fffd2b5a718715a130006590c75c">ODR</a>; </div>
|
||
<div class="line"><a id="l00546" name="l00546"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac25dd6b9e3d55e17589195b461c5ec80"> 546</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac25dd6b9e3d55e17589195b461c5ec80">BSRR</a>; </div>
|
||
<div class="line"><a id="l00547" name="l00547"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2612a0f4b3fbdbb6293f6dc70105e190"> 547</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2612a0f4b3fbdbb6293f6dc70105e190">LCKR</a>; </div>
|
||
<div class="line"><a id="l00548" name="l00548"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab67c1158c04450d19ad483dcd2192e43"> 548</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> AFR[2]; </div>
|
||
<div class="line"><a id="l00549" name="l00549"></a><span class="lineno"> 549</span>} <a class="code hl_struct" href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00550" name="l00550"></a><span class="lineno"> 550</span> </div>
|
||
<div class="foldopen" id="foldopen00555" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00555" name="l00555"></a><span class="lineno"><a class="line" href="struct_s_y_s_c_f_g___type_def.html"> 555</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00556" name="l00556"></a><span class="lineno"> 556</span>{</div>
|
||
<div class="line"><a id="l00557" name="l00557"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab36c409d0a009e3ce5a89ac55d3ff194"> 557</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab36c409d0a009e3ce5a89ac55d3ff194">MEMRMP</a>; </div>
|
||
<div class="line"><a id="l00558" name="l00558"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2130abf1fefb63ce4c4b138fd8c9822a"> 558</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2130abf1fefb63ce4c4b138fd8c9822a">PMC</a>; </div>
|
||
<div class="line"><a id="l00559" name="l00559"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga52f7bf8003ba69d66a4e86dea6eeab65"> 559</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> EXTICR[4]; </div>
|
||
<div class="line"><a id="l00560" name="l00560"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gafaf27b66c1edc60064db3fa6e693fb59"> 560</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED[2]; </div>
|
||
<div class="line"><a id="l00561" name="l00561"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga08ddbac546fa9928256654d31255c8c3"> 561</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga08ddbac546fa9928256654d31255c8c3">CMPCR</a>; </div>
|
||
<div class="line"><a id="l00562" name="l00562"></a><span class="lineno"> 562</span>} <a class="code hl_struct" href="struct_s_y_s_c_f_g___type_def.html">SYSCFG_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00563" name="l00563"></a><span class="lineno"> 563</span> </div>
|
||
<div class="foldopen" id="foldopen00568" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00568" name="l00568"></a><span class="lineno"><a class="line" href="struct_i2_c___type_def.html"> 568</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00569" name="l00569"></a><span class="lineno"> 569</span>{</div>
|
||
<div class="line"><a id="l00570" name="l00570"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0"> 570</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0">CR1</a>; </div>
|
||
<div class="line"><a id="l00571" name="l00571"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586"> 571</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586">CR2</a>; </div>
|
||
<div class="line"><a id="l00572" name="l00572"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga08b4be0d626a00f26bc295b379b3bba6"> 572</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga08b4be0d626a00f26bc295b379b3bba6">OAR1</a>; </div>
|
||
<div class="line"><a id="l00573" name="l00573"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab5c57ffed0351fa064038939a6c0bbf6"> 573</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab5c57ffed0351fa064038939a6c0bbf6">OAR2</a>; </div>
|
||
<div class="line"><a id="l00574" name="l00574"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94"> 574</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94">DR</a>; </div>
|
||
<div class="line"><a id="l00575" name="l00575"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gacefca4fd83c4b7846ae6d3cfe7bb8df9"> 575</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gacefca4fd83c4b7846ae6d3cfe7bb8df9">SR1</a>; </div>
|
||
<div class="line"><a id="l00576" name="l00576"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga89623ee198737b29dc0a803310605a83"> 576</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga89623ee198737b29dc0a803310605a83">SR2</a>; </div>
|
||
<div class="line"><a id="l00577" name="l00577"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga5e1322e27c40bf91d172f9673f205c97"> 577</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga5e1322e27c40bf91d172f9673f205c97">CCR</a>; </div>
|
||
<div class="line"><a id="l00578" name="l00578"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga5d5764c0ec44b661da957e6343f9e7b5"> 578</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga5d5764c0ec44b661da957e6343f9e7b5">TRISE</a>; </div>
|
||
<div class="line"><a id="l00579" name="l00579"></a><span class="lineno"> 579</span>} <a class="code hl_struct" href="struct_i2_c___type_def.html">I2C_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00580" name="l00580"></a><span class="lineno"> 580</span> </div>
|
||
<div class="foldopen" id="foldopen00585" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00585" name="l00585"></a><span class="lineno"><a class="line" href="struct_i_w_d_g___type_def.html"> 585</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00586" name="l00586"></a><span class="lineno"> 586</span>{</div>
|
||
<div class="line"><a id="l00587" name="l00587"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2f692354bde770f2a5e3e1b294ec064b"> 587</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2f692354bde770f2a5e3e1b294ec064b">KR</a>; </div>
|
||
<div class="line"><a id="l00588" name="l00588"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf8d25514079514d38c104402f46470af"> 588</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf8d25514079514d38c104402f46470af">PR</a>; </div>
|
||
<div class="line"><a id="l00589" name="l00589"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga7015e1046dbd3ea8783b33dc11a69e52"> 589</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga7015e1046dbd3ea8783b33dc11a69e52">RLR</a>; </div>
|
||
<div class="line"><a id="l00590" name="l00590"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360"> 590</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360">SR</a>; </div>
|
||
<div class="line"><a id="l00591" name="l00591"></a><span class="lineno"> 591</span>} <a class="code hl_struct" href="struct_i_w_d_g___type_def.html">IWDG_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00592" name="l00592"></a><span class="lineno"> 592</span> </div>
|
||
<div class="line"><a id="l00593" name="l00593"></a><span class="lineno"> 593</span> </div>
|
||
<div class="foldopen" id="foldopen00598" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00598" name="l00598"></a><span class="lineno"><a class="line" href="struct_p_w_r___type_def.html"> 598</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00599" name="l00599"></a><span class="lineno"> 599</span>{</div>
|
||
<div class="line"><a id="l00600" name="l00600"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a"> 600</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a">CR</a>; </div>
|
||
<div class="line"><a id="l00601" name="l00601"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga876dd0a8546697065f406b7543e27af2"> 601</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga876dd0a8546697065f406b7543e27af2">CSR</a>; </div>
|
||
<div class="line"><a id="l00602" name="l00602"></a><span class="lineno"> 602</span>} <a class="code hl_struct" href="struct_p_w_r___type_def.html">PWR_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00603" name="l00603"></a><span class="lineno"> 603</span> </div>
|
||
<div class="foldopen" id="foldopen00608" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00608" name="l00608"></a><span class="lineno"><a class="line" href="struct_r_c_c___type_def.html"> 608</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00609" name="l00609"></a><span class="lineno"> 609</span>{</div>
|
||
<div class="line"><a id="l00610" name="l00610"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a"> 610</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a">CR</a>; </div>
|
||
<div class="line"><a id="l00611" name="l00611"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gae6ff257862eba6b4b367feea786bf1fd"> 611</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gae6ff257862eba6b4b367feea786bf1fd">PLLCFGR</a>; </div>
|
||
<div class="line"><a id="l00612" name="l00612"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga26f1e746ccbf9c9f67e7c60e61085ec1"> 612</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga26f1e746ccbf9c9f67e7c60e61085ec1">CFGR</a>; </div>
|
||
<div class="line"><a id="l00613" name="l00613"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga907d8154c80b7e385478943f90b17a3b"> 613</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga907d8154c80b7e385478943f90b17a3b">CIR</a>; </div>
|
||
<div class="line"><a id="l00614" name="l00614"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga46c20c598e9e12f919f0ea47ebcbc90f"> 614</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga46c20c598e9e12f919f0ea47ebcbc90f">AHB1RSTR</a>; </div>
|
||
<div class="line"><a id="l00615" name="l00615"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga78a5aa9dd5694c48a7d8e66888a46450"> 615</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga78a5aa9dd5694c48a7d8e66888a46450">AHB2RSTR</a>; </div>
|
||
<div class="line"><a id="l00616" name="l00616"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga28560c5bfeb45326ea7f2019dba57bea"> 616</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga28560c5bfeb45326ea7f2019dba57bea">AHB3RSTR</a>; </div>
|
||
<div class="line"><a id="l00617" name="l00617"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf86c61a5d38a4fc9cef942a12744486b"> 617</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf86c61a5d38a4fc9cef942a12744486b">RESERVED0</a>; </div>
|
||
<div class="line"><a id="l00618" name="l00618"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga7da5d372374bc59e9b9af750b01d6a78"> 618</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga7da5d372374bc59e9b9af750b01d6a78">APB1RSTR</a>; </div>
|
||
<div class="line"><a id="l00619" name="l00619"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab2c5389c9ff4ac188cd498b8f7170968"> 619</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab2c5389c9ff4ac188cd498b8f7170968">APB2RSTR</a>; </div>
|
||
<div class="line"><a id="l00620" name="l00620"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga28d88d9a08aab1adbebea61c42ef901e"> 620</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED1[2]; </div>
|
||
<div class="line"><a id="l00621" name="l00621"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1e9c75b06c99d0611535f38c7b4aa845"> 621</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1e9c75b06c99d0611535f38c7b4aa845">AHB1ENR</a>; </div>
|
||
<div class="line"><a id="l00622" name="l00622"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga5e92ed32c33c92e7ebf6919400ad535b"> 622</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga5e92ed32c33c92e7ebf6919400ad535b">AHB2ENR</a>; </div>
|
||
<div class="line"><a id="l00623" name="l00623"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gacdaa650fcd63730825479f6e8f70d4c0"> 623</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gacdaa650fcd63730825479f6e8f70d4c0">AHB3ENR</a>; </div>
|
||
<div class="line"><a id="l00624" name="l00624"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga4c9b972a304c0e08ca27cbe57627c496"> 624</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga4c9b972a304c0e08ca27cbe57627c496">RESERVED2</a>; </div>
|
||
<div class="line"><a id="l00625" name="l00625"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac88901e2eb35079b7b58a185e6bf554c"> 625</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac88901e2eb35079b7b58a185e6bf554c">APB1ENR</a>; </div>
|
||
<div class="line"><a id="l00626" name="l00626"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gacc7bb47dddd2d94de124f74886d919be"> 626</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gacc7bb47dddd2d94de124f74886d919be">APB2ENR</a>; </div>
|
||
<div class="line"><a id="l00627" name="l00627"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab6f0f833dbe064708de75d95c68c32fd"> 627</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED3[2]; </div>
|
||
<div class="line"><a id="l00628" name="l00628"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaae70b1922167eb58d564cb82d39fd10b"> 628</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaae70b1922167eb58d564cb82d39fd10b">AHB1LPENR</a>; </div>
|
||
<div class="line"><a id="l00629" name="l00629"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2b30982547fae7d545d260312771b5c9"> 629</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2b30982547fae7d545d260312771b5c9">AHB2LPENR</a>; </div>
|
||
<div class="line"><a id="l00630" name="l00630"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2ff82b9bf0231645108965aa0febd766"> 630</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2ff82b9bf0231645108965aa0febd766">AHB3LPENR</a>; </div>
|
||
<div class="line"><a id="l00631" name="l00631"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac0018930ee9f18afda25b695b9a4ec16"> 631</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac0018930ee9f18afda25b695b9a4ec16">RESERVED4</a>; </div>
|
||
<div class="line"><a id="l00632" name="l00632"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gad85a9951a7be79fe08ffc90f796f071b"> 632</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gad85a9951a7be79fe08ffc90f796f071b">APB1LPENR</a>; </div>
|
||
<div class="line"><a id="l00633" name="l00633"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaba51c57f9506e14a6f5983526c78943b"> 633</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaba51c57f9506e14a6f5983526c78943b">APB2LPENR</a>; </div>
|
||
<div class="line"><a id="l00634" name="l00634"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac0eb05794aeee3b4ed69c8fe54c9be3b"> 634</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED5[2]; </div>
|
||
<div class="line"><a id="l00635" name="l00635"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga0b9a3ced775287c8585a6a61af4b40e9"> 635</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga0b9a3ced775287c8585a6a61af4b40e9">BDCR</a>; </div>
|
||
<div class="line"><a id="l00636" name="l00636"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga876dd0a8546697065f406b7543e27af2"> 636</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga876dd0a8546697065f406b7543e27af2">CSR</a>; </div>
|
||
<div class="line"><a id="l00637" name="l00637"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga10da398d74a1f88d5b42bd40718d9447"> 637</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED6[2]; </div>
|
||
<div class="line"><a id="l00638" name="l00638"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaaef3da59eaf7c6dfdf9a12fd60ce58a8"> 638</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaaef3da59eaf7c6dfdf9a12fd60ce58a8">SSCGR</a>; </div>
|
||
<div class="line"><a id="l00639" name="l00639"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2d08d5f995ed77228eb56741184a1bb6"> 639</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2d08d5f995ed77228eb56741184a1bb6">PLLI2SCFGR</a>; </div>
|
||
<div class="line"><a id="l00640" name="l00640"></a><span class="lineno"> 640</span>} <a class="code hl_struct" href="struct_r_c_c___type_def.html">RCC_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00641" name="l00641"></a><span class="lineno"> 641</span> </div>
|
||
<div class="foldopen" id="foldopen00646" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00646" name="l00646"></a><span class="lineno"><a class="line" href="struct_r_t_c___type_def.html"> 646</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00647" name="l00647"></a><span class="lineno"> 647</span>{</div>
|
||
<div class="line"><a id="l00648" name="l00648"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga63d179b7a36a715dce7203858d3be132"> 648</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga63d179b7a36a715dce7203858d3be132">TR</a>; </div>
|
||
<div class="line"><a id="l00649" name="l00649"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94"> 649</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94">DR</a>; </div>
|
||
<div class="line"><a id="l00650" name="l00650"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a"> 650</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a">CR</a>; </div>
|
||
<div class="line"><a id="l00651" name="l00651"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab3c49a96815fcbee63d95e1e74f20e75"> 651</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab3c49a96815fcbee63d95e1e74f20e75">ISR</a>; </div>
|
||
<div class="line"><a id="l00652" name="l00652"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac9b4c6c5b29f3461ce3f875eea69f35b"> 652</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac9b4c6c5b29f3461ce3f875eea69f35b">PRER</a>; </div>
|
||
<div class="line"><a id="l00653" name="l00653"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac5b3c8be61045a304d3076d4714d29f2"> 653</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac5b3c8be61045a304d3076d4714d29f2">WUTR</a>; </div>
|
||
<div class="line"><a id="l00654" name="l00654"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab97f3e9584dda705dc10a5f4c5f6e636"> 654</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab97f3e9584dda705dc10a5f4c5f6e636">CALIBR</a>; </div>
|
||
<div class="line"><a id="l00655" name="l00655"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac005b1a5bc52634d5a34578cc9d2c3f6"> 655</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac005b1a5bc52634d5a34578cc9d2c3f6">ALRMAR</a>; </div>
|
||
<div class="line"><a id="l00656" name="l00656"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga4e513deb9f58a138ad9f317cc5a3555d"> 656</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga4e513deb9f58a138ad9f317cc5a3555d">ALRMBR</a>; </div>
|
||
<div class="line"><a id="l00657" name="l00657"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6204786b050eb135fabb15784698e86e"> 657</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6204786b050eb135fabb15784698e86e">WPR</a>; </div>
|
||
<div class="line"><a id="l00658" name="l00658"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga8a868e5e76b52ced04c536be3dee08ec"> 658</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga8a868e5e76b52ced04c536be3dee08ec">SSR</a>; </div>
|
||
<div class="line"><a id="l00659" name="l00659"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2372c05a6c5508e0a9adada793f68b4f"> 659</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2372c05a6c5508e0a9adada793f68b4f">SHIFTR</a>; </div>
|
||
<div class="line"><a id="l00660" name="l00660"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga042059c8b4168681d6aecf30211dd7b8"> 660</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga042059c8b4168681d6aecf30211dd7b8">TSTR</a>; </div>
|
||
<div class="line"><a id="l00661" name="l00661"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gabeb6fb580a8fd128182aa9ba2738ac2c"> 661</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gabeb6fb580a8fd128182aa9ba2738ac2c">TSDR</a>; </div>
|
||
<div class="line"><a id="l00662" name="l00662"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1d6c2bc4c067d6a64ef30d16a5925796"> 662</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1d6c2bc4c067d6a64ef30d16a5925796">TSSSR</a>; </div>
|
||
<div class="line"><a id="l00663" name="l00663"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2ce7c3842792c506635bb87a21588b58"> 663</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2ce7c3842792c506635bb87a21588b58">CALR</a>; </div>
|
||
<div class="line"><a id="l00664" name="l00664"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga14d03244a7fda1d94b51ae9ed144ca12"> 664</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga14d03244a7fda1d94b51ae9ed144ca12">TAFCR</a>; </div>
|
||
<div class="line"><a id="l00665" name="l00665"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga61282fa74cede526af85fd9d20513646"> 665</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga61282fa74cede526af85fd9d20513646">ALRMASSR</a>;</div>
|
||
<div class="line"><a id="l00666" name="l00666"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga4ef7499da5d5beb1cfc81f7be057a7b2"> 666</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga4ef7499da5d5beb1cfc81f7be057a7b2">ALRMBSSR</a>;</div>
|
||
<div class="line"><a id="l00667" name="l00667"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6be3d40baea405ecaf6b38462357dac0"> 667</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6be3d40baea405ecaf6b38462357dac0">RESERVED7</a>; </div>
|
||
<div class="line"><a id="l00668" name="l00668"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga4808ec597e5a5fefd8a83a9127dd1aec"> 668</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga4808ec597e5a5fefd8a83a9127dd1aec">BKP0R</a>; </div>
|
||
<div class="line"><a id="l00669" name="l00669"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf85290529fb82acef7c9fcea3718346c"> 669</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf85290529fb82acef7c9fcea3718346c">BKP1R</a>; </div>
|
||
<div class="line"><a id="l00670" name="l00670"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaaa251a80daa57ad0bd7db75cb3b9cdec"> 670</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaaa251a80daa57ad0bd7db75cb3b9cdec">BKP2R</a>; </div>
|
||
<div class="line"><a id="l00671" name="l00671"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga0b1eeda834c3cfd4d2c67f242f7b2a1c"> 671</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga0b1eeda834c3cfd4d2c67f242f7b2a1c">BKP3R</a>; </div>
|
||
<div class="line"><a id="l00672" name="l00672"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab13e106cc2eca92d1f4022df3bfdbcd7"> 672</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab13e106cc2eca92d1f4022df3bfdbcd7">BKP4R</a>; </div>
|
||
<div class="line"><a id="l00673" name="l00673"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab6bed862c0d0476ff4f89f7b9bf3e130"> 673</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab6bed862c0d0476ff4f89f7b9bf3e130">BKP5R</a>; </div>
|
||
<div class="line"><a id="l00674" name="l00674"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1d854d2d7f0452f4c90035952b92d2ba"> 674</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1d854d2d7f0452f4c90035952b92d2ba">BKP6R</a>; </div>
|
||
<div class="line"><a id="l00675" name="l00675"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2ca54ce1a8d2fa9d1ba6d5987ed5e2cf"> 675</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2ca54ce1a8d2fa9d1ba6d5987ed5e2cf">BKP7R</a>; </div>
|
||
<div class="line"><a id="l00676" name="l00676"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac1085f6aae54b353c30871fe90c59851"> 676</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac1085f6aae54b353c30871fe90c59851">BKP8R</a>; </div>
|
||
<div class="line"><a id="l00677" name="l00677"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6c33564df6eaf97400e0457dde9b14ef"> 677</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6c33564df6eaf97400e0457dde9b14ef">BKP9R</a>; </div>
|
||
<div class="line"><a id="l00678" name="l00678"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaade2881a3e408bfd106b27f78bbbcfc9"> 678</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaade2881a3e408bfd106b27f78bbbcfc9">BKP10R</a>; </div>
|
||
<div class="line"><a id="l00679" name="l00679"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac66d5e2d3459cff89794c47dbc8f7228"> 679</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac66d5e2d3459cff89794c47dbc8f7228">BKP11R</a>; </div>
|
||
<div class="line"><a id="l00680" name="l00680"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6f7eee5ae8a32c07f9c8fe14281bdaf3"> 680</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6f7eee5ae8a32c07f9c8fe14281bdaf3">BKP12R</a>; </div>
|
||
<div class="line"><a id="l00681" name="l00681"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6ed4c3a0d4588a75078e9f8e376b4d06"> 681</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6ed4c3a0d4588a75078e9f8e376b4d06">BKP13R</a>; </div>
|
||
<div class="line"><a id="l00682" name="l00682"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac60f13e6619724747e61cfbff55b9fab"> 682</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac60f13e6619724747e61cfbff55b9fab">BKP14R</a>; </div>
|
||
<div class="line"><a id="l00683" name="l00683"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gafafaddc3a983eb71332b7526d82191ad"> 683</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gafafaddc3a983eb71332b7526d82191ad">BKP15R</a>; </div>
|
||
<div class="line"><a id="l00684" name="l00684"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gad2f2eb2fb4b93e21515b10e920e719b6"> 684</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gad2f2eb2fb4b93e21515b10e920e719b6">BKP16R</a>; </div>
|
||
<div class="line"><a id="l00685" name="l00685"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2842aa523df62f3508316eb3b2e08f4e"> 685</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2842aa523df62f3508316eb3b2e08f4e">BKP17R</a>; </div>
|
||
<div class="line"><a id="l00686" name="l00686"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga640ccb2ccfb6316b88c070362dc29339"> 686</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga640ccb2ccfb6316b88c070362dc29339">BKP18R</a>; </div>
|
||
<div class="line"><a id="l00687" name="l00687"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga4ec1dd54d976989b7c9e59fb14d974fb"> 687</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga4ec1dd54d976989b7c9e59fb14d974fb">BKP19R</a>; </div>
|
||
<div class="line"><a id="l00688" name="l00688"></a><span class="lineno"> 688</span>} <a class="code hl_struct" href="struct_r_t_c___type_def.html">RTC_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00689" name="l00689"></a><span class="lineno"> 689</span> </div>
|
||
<div class="foldopen" id="foldopen00694" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00694" name="l00694"></a><span class="lineno"><a class="line" href="struct_s_d_i_o___type_def.html"> 694</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00695" name="l00695"></a><span class="lineno"> 695</span>{</div>
|
||
<div class="line"><a id="l00696" name="l00696"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga65bff76f3af24c37708a1006d54720c7"> 696</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga65bff76f3af24c37708a1006d54720c7">POWER</a>; </div>
|
||
<div class="line"><a id="l00697" name="l00697"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaa94197378e20fc739d269be49d9c5d40"> 697</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaa94197378e20fc739d269be49d9c5d40">CLKCR</a>; </div>
|
||
<div class="line"><a id="l00698" name="l00698"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga07d4e63efcbde252c667e64a8d818aa9"> 698</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga07d4e63efcbde252c667e64a8d818aa9">ARG</a>; </div>
|
||
<div class="line"><a id="l00699" name="l00699"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gadcf812cbe5147d300507d59d4a55935d"> 699</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gadcf812cbe5147d300507d59d4a55935d">CMD</a>; </div>
|
||
<div class="line"><a id="l00700" name="l00700"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga195d1a8a6ae4f6072f4e4b62298051fe"> 700</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <span class="keyword">const</span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga195d1a8a6ae4f6072f4e4b62298051fe">RESPCMD</a>; </div>
|
||
<div class="line"><a id="l00701" name="l00701"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga7da778413f6db1f83ae25caed03382d4"> 701</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <span class="keyword">const</span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga7da778413f6db1f83ae25caed03382d4">RESP1</a>; </div>
|
||
<div class="line"><a id="l00702" name="l00702"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga44614d7422faffd14af83884e76b2d3e"> 702</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <span class="keyword">const</span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga44614d7422faffd14af83884e76b2d3e">RESP2</a>; </div>
|
||
<div class="line"><a id="l00703" name="l00703"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga270ee3c6e9f87e5851422ae0ef255fd4"> 703</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <span class="keyword">const</span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga270ee3c6e9f87e5851422ae0ef255fd4">RESP3</a>; </div>
|
||
<div class="line"><a id="l00704" name="l00704"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaa74faef460a0c655439bcf20caac1653"> 704</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <span class="keyword">const</span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaa74faef460a0c655439bcf20caac1653">RESP4</a>; </div>
|
||
<div class="line"><a id="l00705" name="l00705"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1dd219eaeee8d9def822da843028bd02"> 705</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1dd219eaeee8d9def822da843028bd02">DTIMER</a>; </div>
|
||
<div class="line"><a id="l00706" name="l00706"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga612edc78d2fa6288392f8ea32c36f7fb"> 706</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga612edc78d2fa6288392f8ea32c36f7fb">DLEN</a>; </div>
|
||
<div class="line"><a id="l00707" name="l00707"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga96a3d1a050982fccc23c2e6dbe0de068"> 707</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga96a3d1a050982fccc23c2e6dbe0de068">DCTRL</a>; </div>
|
||
<div class="line"><a id="l00708" name="l00708"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1c267db01a753d0b8a77afcaff6f9e13"> 708</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <span class="keyword">const</span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1c267db01a753d0b8a77afcaff6f9e13">DCOUNT</a>; </div>
|
||
<div class="line"><a id="l00709" name="l00709"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga0633c88accff51e7cc9d1e9c3db950d9"> 709</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <span class="keyword">const</span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga0633c88accff51e7cc9d1e9c3db950d9">STA</a>; </div>
|
||
<div class="line"><a id="l00710" name="l00710"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga0a8c8230846fd8ff154b9fde8dfa0399"> 710</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga0a8c8230846fd8ff154b9fde8dfa0399">ICR</a>; </div>
|
||
<div class="line"><a id="l00711" name="l00711"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga5c955643593b4aedbe9f84f054d26522"> 711</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga5c955643593b4aedbe9f84f054d26522">MASK</a>; </div>
|
||
<div class="line"><a id="l00712" name="l00712"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga8be676577db129a84a9a2689519a8502"> 712</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED0[2]; </div>
|
||
<div class="line"><a id="l00713" name="l00713"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga003c4c00f70bd77298fc66a449822651"> 713</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <span class="keyword">const</span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga003c4c00f70bd77298fc66a449822651">FIFOCNT</a>; </div>
|
||
<div class="line"><a id="l00714" name="l00714"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2d531df35272b1f3d787e5726ed5c52c"> 714</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> RESERVED1[13]; </div>
|
||
<div class="line"><a id="l00715" name="l00715"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga68bef1da5fd164cf0f884b4209670dc8"> 715</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga68bef1da5fd164cf0f884b4209670dc8">FIFO</a>; </div>
|
||
<div class="line"><a id="l00716" name="l00716"></a><span class="lineno"> 716</span>} <a class="code hl_struct" href="struct_s_d_i_o___type_def.html">SDIO_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00717" name="l00717"></a><span class="lineno"> 717</span> </div>
|
||
<div class="foldopen" id="foldopen00722" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00722" name="l00722"></a><span class="lineno"><a class="line" href="struct_s_p_i___type_def.html"> 722</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00723" name="l00723"></a><span class="lineno"> 723</span>{</div>
|
||
<div class="line"><a id="l00724" name="l00724"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0"> 724</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0">CR1</a>; </div>
|
||
<div class="line"><a id="l00725" name="l00725"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586"> 725</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586">CR2</a>; </div>
|
||
<div class="line"><a id="l00726" name="l00726"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360"> 726</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360">SR</a>; </div>
|
||
<div class="line"><a id="l00727" name="l00727"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94"> 727</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94">DR</a>; </div>
|
||
<div class="line"><a id="l00728" name="l00728"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gace450027b4b33f921dd8edd3425a717c"> 728</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gace450027b4b33f921dd8edd3425a717c">CRCPR</a>; </div>
|
||
<div class="line"><a id="l00729" name="l00729"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2cf9dcd9008924334f20f0dc6b57042e"> 729</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2cf9dcd9008924334f20f0dc6b57042e">RXCRCR</a>; </div>
|
||
<div class="line"><a id="l00730" name="l00730"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab4e4328504fd66285df8264d410deefd"> 730</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab4e4328504fd66285df8264d410deefd">TXCRCR</a>; </div>
|
||
<div class="line"><a id="l00731" name="l00731"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaa0c41c8883cb0812d6aaf956c393584b"> 731</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaa0c41c8883cb0812d6aaf956c393584b">I2SCFGR</a>; </div>
|
||
<div class="line"><a id="l00732" name="l00732"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab9be89a916ee5904381e10da10e5e8e9"> 732</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab9be89a916ee5904381e10da10e5e8e9">I2SPR</a>; </div>
|
||
<div class="line"><a id="l00733" name="l00733"></a><span class="lineno"> 733</span>} <a class="code hl_struct" href="struct_s_p_i___type_def.html">SPI_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00734" name="l00734"></a><span class="lineno"> 734</span> </div>
|
||
<div class="line"><a id="l00735" name="l00735"></a><span class="lineno"> 735</span> </div>
|
||
<div class="foldopen" id="foldopen00740" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00740" name="l00740"></a><span class="lineno"><a class="line" href="struct_t_i_m___type_def.html"> 740</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00741" name="l00741"></a><span class="lineno"> 741</span>{</div>
|
||
<div class="line"><a id="l00742" name="l00742"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0"> 742</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0">CR1</a>; </div>
|
||
<div class="line"><a id="l00743" name="l00743"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586"> 743</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586">CR2</a>; </div>
|
||
<div class="line"><a id="l00744" name="l00744"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2870732a4fc2ecd7bbecfbcbbf5528b7"> 744</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2870732a4fc2ecd7bbecfbcbbf5528b7">SMCR</a>; </div>
|
||
<div class="line"><a id="l00745" name="l00745"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga07fccbd85b91e6dca03ce333c1457fcb"> 745</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga07fccbd85b91e6dca03ce333c1457fcb">DIER</a>; </div>
|
||
<div class="line"><a id="l00746" name="l00746"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360"> 746</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360">SR</a>; </div>
|
||
<div class="line"><a id="l00747" name="l00747"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga196ebdaac12b21e90320c6175da78ef6"> 747</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga196ebdaac12b21e90320c6175da78ef6">EGR</a>; </div>
|
||
<div class="line"><a id="l00748" name="l00748"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gadb72f64492a75e780dd2294075c70fed"> 748</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gadb72f64492a75e780dd2294075c70fed">CCMR1</a>; </div>
|
||
<div class="line"><a id="l00749" name="l00749"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga091452256c9a16c33d891f4d32b395bf"> 749</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga091452256c9a16c33d891f4d32b395bf">CCMR2</a>; </div>
|
||
<div class="line"><a id="l00750" name="l00750"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga098110becfef10e1fd1b6a4f874da496"> 750</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga098110becfef10e1fd1b6a4f874da496">CCER</a>; </div>
|
||
<div class="line"><a id="l00751" name="l00751"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6095a27d764d06750fc0d642e08f8b2a"> 751</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6095a27d764d06750fc0d642e08f8b2a">CNT</a>; </div>
|
||
<div class="line"><a id="l00752" name="l00752"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9d4c753f09cbffdbe5c55008f0e8b180"> 752</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9d4c753f09cbffdbe5c55008f0e8b180">PSC</a>; </div>
|
||
<div class="line"><a id="l00753" name="l00753"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf17f19bb4aeea3cc14fa73dfa7772cb8"> 753</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf17f19bb4aeea3cc14fa73dfa7772cb8">ARR</a>; </div>
|
||
<div class="line"><a id="l00754" name="l00754"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaa1b1b7107fcf35abe39d20f5dfc230ee"> 754</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaa1b1b7107fcf35abe39d20f5dfc230ee">RCR</a>; </div>
|
||
<div class="line"><a id="l00755" name="l00755"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gadab1e24ef769bbcb3e3769feae192ffb"> 755</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gadab1e24ef769bbcb3e3769feae192ffb">CCR1</a>; </div>
|
||
<div class="line"><a id="l00756" name="l00756"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab90aa584f07eeeac364a67f5e05faa93"> 756</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab90aa584f07eeeac364a67f5e05faa93">CCR2</a>; </div>
|
||
<div class="line"><a id="l00757" name="l00757"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga27a478cc47a3dff478555ccb985b06a2"> 757</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga27a478cc47a3dff478555ccb985b06a2">CCR3</a>; </div>
|
||
<div class="line"><a id="l00758" name="l00758"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga85fdb75569bd7ea26fa48544786535be"> 758</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga85fdb75569bd7ea26fa48544786535be">CCR4</a>; </div>
|
||
<div class="line"><a id="l00759" name="l00759"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga476bae602205d6a49c7e71e2bda28c0a"> 759</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga476bae602205d6a49c7e71e2bda28c0a">BDTR</a>; </div>
|
||
<div class="line"><a id="l00760" name="l00760"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf6225cb8f4938f98204d11afaffd41c9"> 760</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf6225cb8f4938f98204d11afaffd41c9">DCR</a>; </div>
|
||
<div class="line"><a id="l00761" name="l00761"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab9087f2f31dd5edf59de6a59ae4e67ae"> 761</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab9087f2f31dd5edf59de6a59ae4e67ae">DMAR</a>; </div>
|
||
<div class="line"><a id="l00762" name="l00762"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga75ade4a9b3d40781fd80ce3e6589e98b"> 762</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga75ade4a9b3d40781fd80ce3e6589e98b">OR</a>; </div>
|
||
<div class="line"><a id="l00763" name="l00763"></a><span class="lineno"> 763</span>} <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00764" name="l00764"></a><span class="lineno"> 764</span> </div>
|
||
<div class="foldopen" id="foldopen00769" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00769" name="l00769"></a><span class="lineno"><a class="line" href="struct_u_s_a_r_t___type_def.html"> 769</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00770" name="l00770"></a><span class="lineno"> 770</span>{</div>
|
||
<div class="line"><a id="l00771" name="l00771"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360"> 771</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360">SR</a>; </div>
|
||
<div class="line"><a id="l00772" name="l00772"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94"> 772</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94">DR</a>; </div>
|
||
<div class="line"><a id="l00773" name="l00773"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga092e59d908b2ca112e31047e942340cb"> 773</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga092e59d908b2ca112e31047e942340cb">BRR</a>; </div>
|
||
<div class="line"><a id="l00774" name="l00774"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0"> 774</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0">CR1</a>; </div>
|
||
<div class="line"><a id="l00775" name="l00775"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586"> 775</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586">CR2</a>; </div>
|
||
<div class="line"><a id="l00776" name="l00776"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gadd5b8e29a64c55dcd65ca4201118e9d1"> 776</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gadd5b8e29a64c55dcd65ca4201118e9d1">CR3</a>; </div>
|
||
<div class="line"><a id="l00777" name="l00777"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga5dd0cb6c861eaf26470f56f451c1edbf"> 777</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga5dd0cb6c861eaf26470f56f451c1edbf">GTPR</a>; </div>
|
||
<div class="line"><a id="l00778" name="l00778"></a><span class="lineno"> 778</span>} <a class="code hl_struct" href="struct_u_s_a_r_t___type_def.html">USART_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00779" name="l00779"></a><span class="lineno"> 779</span> </div>
|
||
<div class="foldopen" id="foldopen00784" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00784" name="l00784"></a><span class="lineno"><a class="line" href="struct_w_w_d_g___type_def.html"> 784</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00785" name="l00785"></a><span class="lineno"> 785</span>{</div>
|
||
<div class="line"><a id="l00786" name="l00786"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a"> 786</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a">CR</a>; </div>
|
||
<div class="line"><a id="l00787" name="l00787"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac011ddcfe531f8e16787ea851c1f3667"> 787</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac011ddcfe531f8e16787ea851c1f3667">CFR</a>; </div>
|
||
<div class="line"><a id="l00788" name="l00788"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360"> 788</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360">SR</a>; </div>
|
||
<div class="line"><a id="l00789" name="l00789"></a><span class="lineno"> 789</span>} <a class="code hl_struct" href="struct_w_w_d_g___type_def.html">WWDG_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00790" name="l00790"></a><span class="lineno"> 790</span> </div>
|
||
<div class="foldopen" id="foldopen00795" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00795" name="l00795"></a><span class="lineno"><a class="line" href="struct_r_n_g___type_def.html"> 795</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span></div>
|
||
<div class="line"><a id="l00796" name="l00796"></a><span class="lineno"> 796</span>{</div>
|
||
<div class="line"><a id="l00797" name="l00797"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a"> 797</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a">CR</a>; </div>
|
||
<div class="line"><a id="l00798" name="l00798"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360"> 798</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360">SR</a>; </div>
|
||
<div class="line"><a id="l00799" name="l00799"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94"> 799</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94">DR</a>; </div>
|
||
<div class="line"><a id="l00800" name="l00800"></a><span class="lineno"> 800</span>} <a class="code hl_struct" href="struct_r_n_g___type_def.html">RNG_TypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00801" name="l00801"></a><span class="lineno"> 801</span> </div>
|
||
<div class="foldopen" id="foldopen00805" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00805" name="l00805"></a><span class="lineno"><a class="line" href="struct_u_s_b___o_t_g___global_type_def.html"> 805</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00806" name="l00806"></a><span class="lineno"> 806</span>{</div>
|
||
<div class="line"><a id="l00807" name="l00807"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga4f006a75f87074f02a532fbeb215bd24"> 807</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga4f006a75f87074f02a532fbeb215bd24">GOTGCTL</a>; </div>
|
||
<div class="line"><a id="l00808" name="l00808"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaef613e58417a7201da95b89b85931da9"> 808</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaef613e58417a7201da95b89b85931da9">GOTGINT</a>; </div>
|
||
<div class="line"><a id="l00809" name="l00809"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac38ac55e4148686564478e95f345b833"> 809</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac38ac55e4148686564478e95f345b833">GAHBCFG</a>; </div>
|
||
<div class="line"><a id="l00810" name="l00810"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga0633538b8b7a6f1372d38938851bba87"> 810</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga0633538b8b7a6f1372d38938851bba87">GUSBCFG</a>; </div>
|
||
<div class="line"><a id="l00811" name="l00811"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaecf297022669fda29294f6fe9818ebbd"> 811</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaecf297022669fda29294f6fe9818ebbd">GRSTCTL</a>; </div>
|
||
<div class="line"><a id="l00812" name="l00812"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9980c4a55080745a11528f8c7ffa1c66"> 812</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9980c4a55080745a11528f8c7ffa1c66">GINTSTS</a>; </div>
|
||
<div class="line"><a id="l00813" name="l00813"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga69d9432b4272331bffb34e196b57cbdf"> 813</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga69d9432b4272331bffb34e196b57cbdf">GINTMSK</a>; </div>
|
||
<div class="line"><a id="l00814" name="l00814"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9925d279a01c6e9713426315e2e44c87"> 814</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9925d279a01c6e9713426315e2e44c87">GRXSTSR</a>; </div>
|
||
<div class="line"><a id="l00815" name="l00815"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga026f1fea708d42ed74b0bd8a488bc55e"> 815</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga026f1fea708d42ed74b0bd8a488bc55e">GRXSTSP</a>; </div>
|
||
<div class="line"><a id="l00816" name="l00816"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1140b76ff103608f66c26ad0a3d595d0"> 816</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1140b76ff103608f66c26ad0a3d595d0">GRXFSIZ</a>; </div>
|
||
<div class="line"><a id="l00817" name="l00817"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga93412b352267d3faf0bd2dbac590b69e"> 817</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga93412b352267d3faf0bd2dbac590b69e">DIEPTXF0_HNPTXFSIZ</a>; </div>
|
||
<div class="line"><a id="l00818" name="l00818"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6ff3c8a6647ae7e5dfcd2ccfbfed4948"> 818</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6ff3c8a6647ae7e5dfcd2ccfbfed4948">HNPTXSTS</a>; </div>
|
||
<div class="line"><a id="l00819" name="l00819"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga577856159d58c037352ee10609b2a99c"> 819</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> Reserved30[2]; </div>
|
||
<div class="line"><a id="l00820" name="l00820"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaef85efc005db9a8e37d95644e92e9032"> 820</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaef85efc005db9a8e37d95644e92e9032">GCCFG</a>; </div>
|
||
<div class="line"><a id="l00821" name="l00821"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6eefd74b3acdc3c1a88b833fcf5e8d81"> 821</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6eefd74b3acdc3c1a88b833fcf5e8d81">CID</a>; </div>
|
||
<div class="line"><a id="l00822" name="l00822"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaea9d4b7970a55a4c87d8482ba1ed1b8b"> 822</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> Reserved40[48]; </div>
|
||
<div class="line"><a id="l00823" name="l00823"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga928fd38284165374eb5aa85ed8d4e6cb"> 823</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga928fd38284165374eb5aa85ed8d4e6cb">HPTXFSIZ</a>; </div>
|
||
<div class="line"><a id="l00824" name="l00824"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2b783e516da93a95c56adf3e52dcbe62"> 824</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> DIEPTXF[0x0F]; </div>
|
||
<div class="line"><a id="l00825" name="l00825"></a><span class="lineno"> 825</span>} <a class="code hl_struct" href="struct_u_s_b___o_t_g___global_type_def.html">USB_OTG_GlobalTypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00826" name="l00826"></a><span class="lineno"> 826</span> </div>
|
||
<div class="foldopen" id="foldopen00830" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00830" name="l00830"></a><span class="lineno"><a class="line" href="struct_u_s_b___o_t_g___device_type_def.html"> 830</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span></div>
|
||
<div class="line"><a id="l00831" name="l00831"></a><span class="lineno"> 831</span>{</div>
|
||
<div class="line"><a id="l00832" name="l00832"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9a163a0d5cfce7238b38067a1a53b324"> 832</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9a163a0d5cfce7238b38067a1a53b324">DCFG</a>; </div>
|
||
<div class="line"><a id="l00833" name="l00833"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gadc1bdc4e76749ccda09c92e885b164ad"> 833</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gadc1bdc4e76749ccda09c92e885b164ad">DCTL</a>; </div>
|
||
<div class="line"><a id="l00834" name="l00834"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga8371acd36203fa875cdea3f29b94d1fb"> 834</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga8371acd36203fa875cdea3f29b94d1fb">DSTS</a>; </div>
|
||
<div class="line"><a id="l00835" name="l00835"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1bcc039378b4ed4ac1261a0a758c3d1d"> 835</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1bcc039378b4ed4ac1261a0a758c3d1d">Reserved0C</a>; </div>
|
||
<div class="line"><a id="l00836" name="l00836"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga48647281e48d96a96f701cf5ae3f4f63"> 836</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga48647281e48d96a96f701cf5ae3f4f63">DIEPMSK</a>; </div>
|
||
<div class="line"><a id="l00837" name="l00837"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga11dbd3f7a82b3f3b91621321d3018e0a"> 837</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga11dbd3f7a82b3f3b91621321d3018e0a">DOEPMSK</a>; </div>
|
||
<div class="line"><a id="l00838" name="l00838"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga4e15c273373694f64b3f70226cb3ac35"> 838</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga4e15c273373694f64b3f70226cb3ac35">DAINT</a>; </div>
|
||
<div class="line"><a id="l00839" name="l00839"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga2c8f65655aa14ec9ba63c9d0655223ec"> 839</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga2c8f65655aa14ec9ba63c9d0655223ec">DAINTMSK</a>; </div>
|
||
<div class="line"><a id="l00840" name="l00840"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga17d14644b0d28710722b1c2c0149e472"> 840</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga17d14644b0d28710722b1c2c0149e472">Reserved20</a>; </div>
|
||
<div class="line"><a id="l00841" name="l00841"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga5dc05e38e6d591cd88f820b7a0b3f727"> 841</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga5dc05e38e6d591cd88f820b7a0b3f727">Reserved9</a>; </div>
|
||
<div class="line"><a id="l00842" name="l00842"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaef96b3719a70e62cb004b1e292b7a348"> 842</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaef96b3719a70e62cb004b1e292b7a348">DVBUSDIS</a>; </div>
|
||
<div class="line"><a id="l00843" name="l00843"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gacc968fd160f83749ad4176ad8cb36fe0"> 843</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gacc968fd160f83749ad4176ad8cb36fe0">DVBUSPULSE</a>; </div>
|
||
<div class="line"><a id="l00844" name="l00844"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac5d3a4bffd921da5d69f9a601263b573"> 844</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac5d3a4bffd921da5d69f9a601263b573">DTHRCTL</a>; </div>
|
||
<div class="line"><a id="l00845" name="l00845"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga99c6c50a3e3235c81b98a428ebd33d4c"> 845</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga99c6c50a3e3235c81b98a428ebd33d4c">DIEPEMPMSK</a>; </div>
|
||
<div class="line"><a id="l00846" name="l00846"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gae85e8a65a72f52a9daf3d2b66b77c2e2"> 846</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gae85e8a65a72f52a9daf3d2b66b77c2e2">DEACHINT</a>; </div>
|
||
<div class="line"><a id="l00847" name="l00847"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga0234d794aba7ddae31f3da3c02c8a673"> 847</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga0234d794aba7ddae31f3da3c02c8a673">DEACHMSK</a>; </div>
|
||
<div class="line"><a id="l00848" name="l00848"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9e0c029846e94bf08ac8edb35b30ecb2"> 848</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9e0c029846e94bf08ac8edb35b30ecb2">Reserved40</a>; </div>
|
||
<div class="line"><a id="l00849" name="l00849"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gab62b876c61e11199cf5c37aa944a5fed"> 849</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gab62b876c61e11199cf5c37aa944a5fed">DINEP1MSK</a>; </div>
|
||
<div class="line"><a id="l00850" name="l00850"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga8b1e044bd34b12074334270cfd18c931"> 850</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> Reserved44[15]; </div>
|
||
<div class="line"><a id="l00851" name="l00851"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga196e86fc15ba228188d47468349de69b"> 851</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga196e86fc15ba228188d47468349de69b">DOUTEP1MSK</a>; </div>
|
||
<div class="line"><a id="l00852" name="l00852"></a><span class="lineno"> 852</span>} <a class="code hl_struct" href="struct_u_s_b___o_t_g___device_type_def.html">USB_OTG_DeviceTypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00853" name="l00853"></a><span class="lineno"> 853</span> </div>
|
||
<div class="foldopen" id="foldopen00857" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00857" name="l00857"></a><span class="lineno"><a class="line" href="struct_u_s_b___o_t_g___i_n_endpoint_type_def.html"> 857</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span></div>
|
||
<div class="line"><a id="l00858" name="l00858"></a><span class="lineno"> 858</span>{</div>
|
||
<div class="line"><a id="l00859" name="l00859"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga840b32fa57faa544c3000ae1d08564c7"> 859</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga840b32fa57faa544c3000ae1d08564c7">DIEPCTL</a>; </div>
|
||
<div class="line"><a id="l00860" name="l00860"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gacfe7efaa61db86840767dff6d73f8695"> 860</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gacfe7efaa61db86840767dff6d73f8695">Reserved04</a>; </div>
|
||
<div class="line"><a id="l00861" name="l00861"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga65f69561c1cefe00ce608b7a3c2d8af5"> 861</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga65f69561c1cefe00ce608b7a3c2d8af5">DIEPINT</a>; </div>
|
||
<div class="line"><a id="l00862" name="l00862"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1bcc039378b4ed4ac1261a0a758c3d1d"> 862</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1bcc039378b4ed4ac1261a0a758c3d1d">Reserved0C</a>; </div>
|
||
<div class="line"><a id="l00863" name="l00863"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga19cf1f1798a062c2a19afe9224e3f938"> 863</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga19cf1f1798a062c2a19afe9224e3f938">DIEPTSIZ</a>; </div>
|
||
<div class="line"><a id="l00864" name="l00864"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga05fcc63652e936e715223e4423069959"> 864</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga05fcc63652e936e715223e4423069959">DIEPDMA</a>; </div>
|
||
<div class="line"><a id="l00865" name="l00865"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga44135a03aa87fb60abd479a09f71343d"> 865</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga44135a03aa87fb60abd479a09f71343d">DTXFSTS</a>; </div>
|
||
<div class="line"><a id="l00866" name="l00866"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga716e172ed03ae049eb501ad83207b4ed"> 866</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga716e172ed03ae049eb501ad83207b4ed">Reserved18</a>; </div>
|
||
<div class="line"><a id="l00867" name="l00867"></a><span class="lineno"> 867</span>} <a class="code hl_struct" href="struct_u_s_b___o_t_g___i_n_endpoint_type_def.html">USB_OTG_INEndpointTypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00868" name="l00868"></a><span class="lineno"> 868</span> </div>
|
||
<div class="foldopen" id="foldopen00872" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00872" name="l00872"></a><span class="lineno"><a class="line" href="struct_u_s_b___o_t_g___o_u_t_endpoint_type_def.html"> 872</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span></div>
|
||
<div class="line"><a id="l00873" name="l00873"></a><span class="lineno"> 873</span>{</div>
|
||
<div class="line"><a id="l00874" name="l00874"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga905a2b4ece4882eb67c710e0db10e960"> 874</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga905a2b4ece4882eb67c710e0db10e960">DOEPCTL</a>; </div>
|
||
<div class="line"><a id="l00875" name="l00875"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gacfe7efaa61db86840767dff6d73f8695"> 875</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gacfe7efaa61db86840767dff6d73f8695">Reserved04</a>; </div>
|
||
<div class="line"><a id="l00876" name="l00876"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaffd2c6f534c8f2c252f3a93d0cd04ea2"> 876</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaffd2c6f534c8f2c252f3a93d0cd04ea2">DOEPINT</a>; </div>
|
||
<div class="line"><a id="l00877" name="l00877"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga1bcc039378b4ed4ac1261a0a758c3d1d"> 877</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga1bcc039378b4ed4ac1261a0a758c3d1d">Reserved0C</a>; </div>
|
||
<div class="line"><a id="l00878" name="l00878"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga35b668314acbac2580b98caf8b9c5c10"> 878</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga35b668314acbac2580b98caf8b9c5c10">DOEPTSIZ</a>; </div>
|
||
<div class="line"><a id="l00879" name="l00879"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga78a4f036f29e552acad6a442fbb69420"> 879</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga78a4f036f29e552acad6a442fbb69420">DOEPDMA</a>; </div>
|
||
<div class="line"><a id="l00880" name="l00880"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga78fbe0aab076cfbf9df51dd6f67eaf82"> 880</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> Reserved18[2]; </div>
|
||
<div class="line"><a id="l00881" name="l00881"></a><span class="lineno"> 881</span>} <a class="code hl_struct" href="struct_u_s_b___o_t_g___o_u_t_endpoint_type_def.html">USB_OTG_OUTEndpointTypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00882" name="l00882"></a><span class="lineno"> 882</span> </div>
|
||
<div class="foldopen" id="foldopen00886" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00886" name="l00886"></a><span class="lineno"><a class="line" href="struct_u_s_b___o_t_g___host_type_def.html"> 886</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span></div>
|
||
<div class="line"><a id="l00887" name="l00887"></a><span class="lineno"> 887</span>{</div>
|
||
<div class="line"><a id="l00888" name="l00888"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaa15bc4ab9217b295560dbda2235c745a"> 888</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaa15bc4ab9217b295560dbda2235c745a">HCFG</a>; </div>
|
||
<div class="line"><a id="l00889" name="l00889"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga0a6f11662e44ad485cc869f49e5aa9c9"> 889</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga0a6f11662e44ad485cc869f49e5aa9c9">HFIR</a>; </div>
|
||
<div class="line"><a id="l00890" name="l00890"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga6a141fc0dab9ee8930465a2da604420f"> 890</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga6a141fc0dab9ee8930465a2da604420f">HFNUM</a>; </div>
|
||
<div class="line"><a id="l00891" name="l00891"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf66e42cdb83dc2eb156dfbbf42890f79"> 891</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf66e42cdb83dc2eb156dfbbf42890f79">Reserved40C</a>; </div>
|
||
<div class="line"><a id="l00892" name="l00892"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga3903a00940c32a9f09889e08881e7a6a"> 892</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga3903a00940c32a9f09889e08881e7a6a">HPTXSTS</a>; </div>
|
||
<div class="line"><a id="l00893" name="l00893"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9fb9e43255829e50b9e5416d58ae11be"> 893</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9fb9e43255829e50b9e5416d58ae11be">HAINT</a>; </div>
|
||
<div class="line"><a id="l00894" name="l00894"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga4d431ac4a59cbb89ed82a6c6cf9dfc39"> 894</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga4d431ac4a59cbb89ed82a6c6cf9dfc39">HAINTMSK</a>; </div>
|
||
<div class="line"><a id="l00895" name="l00895"></a><span class="lineno"> 895</span>} <a class="code hl_struct" href="struct_u_s_b___o_t_g___host_type_def.html">USB_OTG_HostTypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00896" name="l00896"></a><span class="lineno"> 896</span> </div>
|
||
<div class="foldopen" id="foldopen00900" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00900" name="l00900"></a><span class="lineno"><a class="line" href="struct_u_s_b___o_t_g___host_channel_type_def.html"> 900</a></span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||
<div class="line"><a id="l00901" name="l00901"></a><span class="lineno"> 901</span>{</div>
|
||
<div class="line"><a id="l00902" name="l00902"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac1d0619a44758dcaeeda5c0b9c22f784"> 902</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac1d0619a44758dcaeeda5c0b9c22f784">HCCHAR</a>; </div>
|
||
<div class="line"><a id="l00903" name="l00903"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gad715951248900b9a7c8c9ddb688bb3a0"> 903</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gad715951248900b9a7c8c9ddb688bb3a0">HCSPLT</a>; </div>
|
||
<div class="line"><a id="l00904" name="l00904"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga830a2b58d0eb53a7ec8f9816103e3bc1"> 904</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga830a2b58d0eb53a7ec8f9816103e3bc1">HCINT</a>; </div>
|
||
<div class="line"><a id="l00905" name="l00905"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gae69520f078c84fb1d33cd7551ff23342"> 905</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gae69520f078c84fb1d33cd7551ff23342">HCINTMSK</a>; </div>
|
||
<div class="line"><a id="l00906" name="l00906"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gadde42c516172a887c570545d965200cf"> 906</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gadde42c516172a887c570545d965200cf">HCTSIZ</a>; </div>
|
||
<div class="line"><a id="l00907" name="l00907"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaf294702e1d54fe06b43e7a3b4033dc2e"> 907</a></span> <a class="code hl_define" href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaf294702e1d54fe06b43e7a3b4033dc2e">HCDMA</a>; </div>
|
||
<div class="line"><a id="l00908" name="l00908"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gae930d94b6a3272fed7c42c1a02929924"> 908</a></span> <a class="code hl_typedef" href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a> Reserved[2]; </div>
|
||
<div class="line"><a id="l00909" name="l00909"></a><span class="lineno"> 909</span>} <a class="code hl_struct" href="struct_u_s_b___o_t_g___host_channel_type_def.html">USB_OTG_HostChannelTypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00910" name="l00910"></a><span class="lineno"> 910</span> </div>
|
||
<div class="line"><a id="l00918" name="l00918"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga4a1f7e664b3e091fee94976b33bbf7b9"> 918</a></span><span class="preprocessor">#define FLASH_BASE_SHIFT 0x08000000UL </span></div>
|
||
<div class="line"><a id="l00919" name="l00919"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga77155e7666b070a9653f0a43d11f2004"> 919</a></span><span class="preprocessor">#define FLASH_END_SHIFT 0x080FFFFFUL </span></div>
|
||
<div class="line"><a id="l00920" name="l00920"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga2d06a3566d8983055baf9e883e0198ef"> 920</a></span><span class="preprocessor">#define CCMDATARAM_BASE_SHIFT 0x10000000UL </span></div>
|
||
<div class="line"><a id="l00921" name="l00921"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga86d258a24d1cef85ee0333fcaf6398a8"> 921</a></span><span class="preprocessor">#define CCMDATARAM_END_SHIFT 0x1000FFFFUL </span></div>
|
||
<div class="line"><a id="l00922" name="l00922"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga1ea2ceeb2a729bb1072d98cf7c3ceb6e"> 922</a></span><span class="preprocessor">#define FLASH_OTP_BASE_SHIFT 0x1FFF7800UL </span></div>
|
||
<div class="line"><a id="l00923" name="l00923"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga46ebe9214ddc2503af753a11fd5ccb80"> 923</a></span><span class="preprocessor">#define FLASH_OTP_END_SHIFT 0x1FFF7A0FUL </span></div>
|
||
<div class="line"><a id="l00924" name="l00924"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gac53e3a39a0ebd3520aaa373ae44ff838"> 924</a></span><span class="preprocessor">#define SRAM1_BASE_SHIFT 0x20000000UL </span></div>
|
||
<div class="line"><a id="l00925" name="l00925"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaff8892343768799209d59c2c33848222"> 925</a></span><span class="preprocessor">#define SRAM2_BASE_SHIFT 0x2001C000UL </span></div>
|
||
<div class="line"><a id="l00926" name="l00926"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga9d4c99653d22992b3b4b1537ade15d21"> 926</a></span><span class="preprocessor">#define SRAM1_BB_BASE_SHIFT 0x22000000UL </span></div>
|
||
<div class="line"><a id="l00927" name="l00927"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga1654496a485d04270e2208afa8e4fd5c"> 927</a></span><span class="preprocessor">#define SRAM2_BB_BASE_SHIFT 0x22380000UL </span></div>
|
||
<div class="line"><a id="l00928" name="l00928"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga1294c8e27eb23b591c5195504e4dfd23"> 928</a></span><span class="preprocessor">#define PERIPH_BASE_SHIFT 0x40000000UL </span></div>
|
||
<div class="line"><a id="l00929" name="l00929"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gabac8d912551188d0039d016d16f7c0b0"> 929</a></span><span class="preprocessor">#define BKPSRAM_BASE_SHIFT 0x40024000UL </span></div>
|
||
<div class="line"><a id="l00930" name="l00930"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga33c4df718741b5cb60ca3fffe8969672"> 930</a></span><span class="preprocessor">#define PERIPH_BB_BASE_SHIFT 0x42000000UL </span></div>
|
||
<div class="line"><a id="l00931" name="l00931"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaa850b97b5338b2a9891acbf23788fd14"> 931</a></span><span class="preprocessor">#define BKPSRAM_BB_BASE_SHIFT 0x42480000UL </span></div>
|
||
<div class="line"><a id="l00932" name="l00932"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gae359dc044d8a99c9634a01abdbab704b"> 932</a></span><span class="preprocessor">#define FSMC_R_BASE_SHIFT 0xA0000000UL </span></div>
|
||
<div class="line"><a id="l00934" name="l00934"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga4ddc1e9172ba6fe724328595a3fadcf2"> 934</a></span><span class="preprocessor">#define MCU_MEM_END 0xA0000FFFUL </span></div>
|
||
<div class="line"><a id="l00936" name="l00936"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga71542ecbf91e5a2e4e7657ebf4743bb0"> 936</a></span><span class="preprocessor">#define CCMDATARAM_SIZE 0x10000UL </span><span class="comment">/* (64 KB) */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l00937" name="l00937"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gacf1c7f7eb345f8e1b617fd1b16320111"> 937</a></span><span class="preprocessor">#define SRAM1_SIZE 0x1C000UL </span><span class="comment">/* (112 KB) */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l00938" name="l00938"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gad89e757d25db6160b1aedeb58fcdac09"> 938</a></span><span class="preprocessor">#define SRAM2_SIZE 0x4000UL </span><span class="comment">/* (16 KB) */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l00939" name="l00939"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gafe7470549838cd29d6f2d7245f17176c"> 939</a></span><span class="preprocessor">#define BKPSRAM_SIZE 0x1000UL </span><span class="comment">/* (4 KB) */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l00940" name="l00940"></a><span class="lineno"> 940</span> </div>
|
||
<div class="line"><a id="l00941" name="l00941"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gae69620948dea1b76e0ab7843ab719db7"> 941</a></span><span class="preprocessor">#define FLASH_SIZE (CCMDATARAM_BASE_SHIFT - FLASH_BASE_SHIFT)</span></div>
|
||
<div class="line"><a id="l00942" name="l00942"></a><span class="lineno"> 942</span><span class="comment">//#define CCMDATARAM_SIZE (FLASH_OTP_BASE_SHIFT - CCMDATARAM_BASE_SHIFT)</span></div>
|
||
<div class="line"><a id="l00943" name="l00943"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gacb3e2951c91f038686e0cbcd4321814b"> 943</a></span><span class="preprocessor">#define FLASH_OTP_SIZE (SRAM1_BASE_SHIFT - FLASH_OTP_BASE_SHIFT)</span></div>
|
||
<div class="line"><a id="l00944" name="l00944"></a><span class="lineno"> 944</span><span class="comment">//#define SRAM1_SIZE (SRAM2_BASE_SHIFT - SRAM1_BASE_SHIFT)</span></div>
|
||
<div class="line"><a id="l00945" name="l00945"></a><span class="lineno"> 945</span><span class="comment">//#define SRAM2_SIZE (SRAM1_BB_BASE_SHIFT - SRAM2_BASE_SHIFT)</span></div>
|
||
<div class="line"><a id="l00946" name="l00946"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga4d759a2722aeeb47a81dd047d4e1790e"> 946</a></span><span class="preprocessor">#define SRAM1_BB_SIZE (SRAM2_BB_BASE_SHIFT - SRAM1_BB_BASE_SHIFT)</span></div>
|
||
<div class="line"><a id="l00947" name="l00947"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga146845582d93b1fa90c52f43f704c178"> 947</a></span><span class="preprocessor">#define SRAM2_BB_SIZE (PERIPH_BASE_SHIFT - SRAM2_BB_BASE_SHIFT)</span></div>
|
||
<div class="line"><a id="l00948" name="l00948"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaf91d23524f40a61d32fea568949043d0"> 948</a></span><span class="preprocessor">#define PERIPH_SIZE (BKPSRAM_BASE_SHIFT - PERIPH_BASE_SHIFT)</span></div>
|
||
<div class="line"><a id="l00949" name="l00949"></a><span class="lineno"> 949</span><span class="comment">//#define BKPSRAM_SIZE (PERIPH_BB_BASE_SHIFT - BKPSRAM_BASE_SHIFT)</span></div>
|
||
<div class="line"><a id="l00950" name="l00950"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga16c53e8ec3bcf87a7d170220d774956c"> 950</a></span><span class="preprocessor">#define PERIPH_BB_SIZE (BKPSRAM_BB_BASE_SHIFT - PERIPH_BB_BASE_SHIFT)</span></div>
|
||
<div class="line"><a id="l00951" name="l00951"></a><span class="lineno"> 951</span><span class="comment">//#define BKPSRAM_BB_SIZE (FSMC_R_BASE_SHIFT - BKPSRAM_BB_BASE_SHIFT)</span></div>
|
||
<div class="line"><a id="l00952" name="l00952"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga36147b9ef36c5be4745a45162cd85be4"> 952</a></span><span class="preprocessor">#define FSMC_R_SIZE (MCU_MEM_END - FSMC_R_BASE_SHIFT)</span></div>
|
||
<div class="line"><a id="l00953" name="l00953"></a><span class="lineno"> 953</span> </div>
|
||
<div class="line"><a id="l00954" name="l00954"></a><span class="lineno"> 954</span> </div>
|
||
<div class="foldopen" id="foldopen00955" data-start="{" data-end="};">
|
||
<div class="line"><a id="l00955" name="l00955"></a><span class="lineno"><a class="line" href="struct__memory.html"> 955</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code hl_struct" href="struct__memory.html">_memory</a></div>
|
||
<div class="line"><a id="l00956" name="l00956"></a><span class="lineno"> 956</span>{</div>
|
||
<div class="line"><a id="l00957" name="l00957"></a><span class="lineno"> 957</span> <span class="comment">//uint8_t RESERVED[FLASH_BASE_SHIFT];</span></div>
|
||
<div class="line"><a id="l00958" name="l00958"></a><span class="lineno"> 958</span> </div>
|
||
<div class="line"><a id="l00959" name="l00959"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga84303738f0e64d5303c027932c055d87"> 959</a></span> <a class="code hl_typedef" href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga84303738f0e64d5303c027932c055d87">FLASH_BASE</a>[<a class="code hl_define" href="group___peripheral__memory__map.html#gae69620948dea1b76e0ab7843ab719db7">FLASH_SIZE</a>];</div>
|
||
<div class="line"><a id="l00960" name="l00960"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gacd6db2394f2b493a873059464d5b0e18"> 960</a></span> <a class="code hl_typedef" href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gacd6db2394f2b493a873059464d5b0e18">CCMDATARAM_BASE</a>[<a class="code hl_define" href="group___peripheral__memory__map.html#ga71542ecbf91e5a2e4e7657ebf4743bb0">CCMDATARAM_SIZE</a>];</div>
|
||
<div class="line"><a id="l00961" name="l00961"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gace5daae0e2da2f05a6b63f3f68109284"> 961</a></span> <a class="code hl_typedef" href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gace5daae0e2da2f05a6b63f3f68109284">FLASH_OTP_BASE</a>[<a class="code hl_define" href="group___peripheral__memory__map.html#gacb3e2951c91f038686e0cbcd4321814b">FLASH_OTP_SIZE</a>];</div>
|
||
<div class="line"><a id="l00962" name="l00962"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac7c83f52956da4c75f4946348f7bfa1a"> 962</a></span> <a class="code hl_typedef" href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac7c83f52956da4c75f4946348f7bfa1a">SRAM1_BASE</a>[<a class="code hl_define" href="group___peripheral__memory__map.html#gacf1c7f7eb345f8e1b617fd1b16320111">SRAM1_SIZE</a>];</div>
|
||
<div class="line"><a id="l00963" name="l00963"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga57bfa1d7c82d97792cbb6c2d366dd48d"> 963</a></span> <a class="code hl_typedef" href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga57bfa1d7c82d97792cbb6c2d366dd48d">SRAM2_BASE</a>[<a class="code hl_define" href="group___peripheral__memory__map.html#gad89e757d25db6160b1aedeb58fcdac09">SRAM2_SIZE</a>];</div>
|
||
<div class="line"><a id="l00964" name="l00964"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gac88d0add27755615a9390fec8c64dafc"> 964</a></span> <a class="code hl_typedef" href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gac88d0add27755615a9390fec8c64dafc">SRAM1_BB_BASE</a>[<a class="code hl_define" href="group___peripheral__memory__map.html#gacf1c7f7eb345f8e1b617fd1b16320111">SRAM1_SIZE</a>];</div>
|
||
<div class="line"><a id="l00965" name="l00965"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga5db33a541cebb596c2976d4fc409a611"> 965</a></span> <a class="code hl_typedef" href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga5db33a541cebb596c2976d4fc409a611">SRAM2_BB_BASE</a>[<a class="code hl_define" href="group___peripheral__memory__map.html#gad89e757d25db6160b1aedeb58fcdac09">SRAM2_SIZE</a>];</div>
|
||
<div class="line"><a id="l00966" name="l00966"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga535f5001cfe9967fb7040cd5b081d944"> 966</a></span> <a class="code hl_typedef" href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga535f5001cfe9967fb7040cd5b081d944">PERIPH_BASE</a>[<a class="code hl_define" href="group___peripheral__memory__map.html#gaf91d23524f40a61d32fea568949043d0">PERIPH_SIZE</a>];</div>
|
||
<div class="line"><a id="l00967" name="l00967"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gae20eaf17d134d9c2136072bca05f36c0"> 967</a></span> <a class="code hl_typedef" href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gae20eaf17d134d9c2136072bca05f36c0">BKPSRAM_BASE</a>[<a class="code hl_define" href="group___peripheral__memory__map.html#gafe7470549838cd29d6f2d7245f17176c">BKPSRAM_SIZE</a>];</div>
|
||
<div class="line"><a id="l00968" name="l00968"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga9fbcd0d73c2b2229b9f95743f280382c"> 968</a></span> <a class="code hl_typedef" href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga9fbcd0d73c2b2229b9f95743f280382c">PERIPH_BB_BASE</a>[<a class="code hl_define" href="group___peripheral__memory__map.html#ga16c53e8ec3bcf87a7d170220d774956c">PERIPH_BB_SIZE</a>];</div>
|
||
<div class="line"><a id="l00969" name="l00969"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#ga90eb3fc2642288d3e7ca2416493bf8ae"> 969</a></span> <a class="code hl_typedef" href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#ga90eb3fc2642288d3e7ca2416493bf8ae">BKPSRAM_BB_BASE</a>[<a class="code hl_define" href="group___peripheral__memory__map.html#gafe7470549838cd29d6f2d7245f17176c">BKPSRAM_SIZE</a>];</div>
|
||
<div class="line"><a id="l00970" name="l00970"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___device.html#gaeb17f07e5976d0674b1afe60cffc79d4"> 970</a></span> <a class="code hl_typedef" href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code hl_variable" href="group___c_m_s_i_s___device.html#gaeb17f07e5976d0674b1afe60cffc79d4">FSMC_R_BASE</a>[<a class="code hl_define" href="group___peripheral__memory__map.html#ga36147b9ef36c5be4745a45162cd85be4">FSMC_R_SIZE</a>];</div>
|
||
<div class="line"><a id="l00971" name="l00971"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga304d35aeeebef1445af976d8a5248d57"> 971</a></span>}<a class="code hl_typedef" href="group___peripheral__memory__map.html#ga304d35aeeebef1445af976d8a5248d57">MCU_MemoryTypeDef</a>;</div>
|
||
</div>
|
||
<div class="line"><a id="l00972" name="l00972"></a><span class="lineno"> 972</span><span class="keyword">extern</span> <a class="code hl_struct" href="struct__memory.html">MCU_MemoryTypeDef</a> <a class="code hl_variable" href="group___peripheral__memory__map.html#gaf157a51d290d1383d493a6a2fe0241fc">MCU_MEM</a>;</div>
|
||
<div class="line"><a id="l00973" name="l00973"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga85a080726cb1ade56443b458fc49404b"> 973</a></span><a class="code hl_struct" href="struct_d_b_g_m_c_u___type_def.html">DBGMCU_TypeDef</a> <a class="code hl_variable" href="group___peripheral__memory__map.html#ga85a080726cb1ade56443b458fc49404b">DEBUG_MCU</a>;</div>
|
||
<div class="line"><a id="l00974" name="l00974"></a><span class="lineno"> 974</span> </div>
|
||
<div class="line"><a id="l00978" name="l00978"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga23a9099a5f8fc9c6e253c0eecb2be8db"> 978</a></span><span class="preprocessor">#define FLASH_BASE (MCU_MEM.CCMDATARAM_BASE) </span></div>
|
||
<div class="line"><a id="l00979" name="l00979"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gabea1f1810ebeac402164b42ab54bcdf9"> 979</a></span><span class="preprocessor">#define CCMDATARAM_BASE (MCU_MEM.CCMDATARAM_BASE) </span></div>
|
||
<div class="line"><a id="l00980" name="l00980"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga7d0fbfb8894012dbbb96754b95e562cd"> 980</a></span><span class="preprocessor">#define SRAM1_BASE (MCU_MEM.SRAM1_BASE) </span></div>
|
||
<div class="line"><a id="l00981" name="l00981"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gadbb42a3d0a8a90a79d2146e4014241b1"> 981</a></span><span class="preprocessor">#define SRAM2_BASE (MCU_MEM.SRAM2_BASE) </span></div>
|
||
<div class="line"><a id="l00982" name="l00982"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga9171f49478fa86d932f89e78e73b88b0"> 982</a></span><span class="preprocessor">#define PERIPH_BASE (MCU_MEM.PERIPH_BASE) </span></div>
|
||
<div class="line"><a id="l00983" name="l00983"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga52e57051bdf8909222b36e5408a48f32"> 983</a></span><span class="preprocessor">#define BKPSRAM_BASE (MCU_MEM.BKPSRAM_BASE) </span></div>
|
||
<div class="line"><a id="l00984" name="l00984"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaddf0e199dccba83272b20c9fb4d3aaed"> 984</a></span><span class="preprocessor">#define FSMC_R_BASE (MCU_MEM.FSMC_R_BASE) </span></div>
|
||
<div class="line"><a id="l00985" name="l00985"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gac4c4f61082e4b168f29d9cf97dc3ca5c"> 985</a></span><span class="preprocessor">#define SRAM1_BB_BASE (MCU_MEM.SRAM1_BB_BASE) </span></div>
|
||
<div class="line"><a id="l00986" name="l00986"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gac33cb6edadf184ab9860d77089503922"> 986</a></span><span class="preprocessor">#define SRAM2_BB_BASE (MCU_MEM.SRAM2_BB_BASE) </span></div>
|
||
<div class="line"><a id="l00987" name="l00987"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a"> 987</a></span><span class="preprocessor">#define PERIPH_BB_BASE (MCU_MEM.PERIPH_BB_BASE) </span></div>
|
||
<div class="line"><a id="l00988" name="l00988"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaee19a30c9fa326bb10b547e4eaf4e250"> 988</a></span><span class="preprocessor">#define BKPSRAM_BB_BASE (MCU_MEM.BKPSRAM_BB_BASE) </span></div>
|
||
<div class="line"><a id="l00989" name="l00989"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga8be554f354e5aa65370f6db63d4f3ee4"> 989</a></span><span class="preprocessor">#define FLASH_END (MCU_MEM.FLASH_END) </span></div>
|
||
<div class="line"><a id="l00990" name="l00990"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga91d296a67aec0da8f31c368cbc0eea94"> 990</a></span><span class="preprocessor">#define FLASH_OTP_BASE (MCU_MEM.FLASH_OTP_BASE) </span></div>
|
||
<div class="line"><a id="l00991" name="l00991"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga5bec9c5a91e312fca36f256f508ceee1"> 991</a></span><span class="preprocessor">#define FLASH_OTP_END (MCU_MEM.FLASH_OTP_END) </span></div>
|
||
<div class="line"><a id="l00992" name="l00992"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga9fbe263946209e6f09faf93512bd2f9a"> 992</a></span><span class="preprocessor">#define CCMDATARAM_END (MCU_MEM.CCMDATARAM_END) </span></div>
|
||
<div class="line"><a id="l00994" name="l00994"></a><span class="lineno"> 994</span> <span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l00995" name="l00995"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga05e8f3d2e5868754a7cd88614955aecc"> 995</a></span><span class="preprocessor">#define SRAM_BASE SRAM1_BASE</span></div>
|
||
<div class="line"><a id="l00996" name="l00996"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gad3548b6e2f017f39d399358f3ac98454"> 996</a></span><span class="preprocessor">#define SRAM_BB_BASE SRAM1_BB_BASE</span></div>
|
||
<div class="line"><a id="l00997" name="l00997"></a><span class="lineno"> 997</span> </div>
|
||
<div class="line"><a id="l00999" name="l00999"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb"> 999</a></span><span class="preprocessor">#define APB1PERIPH_BASE PERIPH_BASE</span></div>
|
||
<div class="line"><a id="l01000" name="l01000"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb"> 1000</a></span><span class="preprocessor">#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)</span></div>
|
||
<div class="line"><a id="l01001" name="l01001"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4"> 1001</a></span><span class="preprocessor">#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)</span></div>
|
||
<div class="line"><a id="l01002" name="l01002"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaeedaa71d22a1948492365e2cd26cfd46"> 1002</a></span><span class="preprocessor">#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)</span></div>
|
||
<div class="line"><a id="l01003" name="l01003"></a><span class="lineno"> 1003</span> </div>
|
||
<div class="line"><a id="l01005" name="l01005"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga00d0fe6ad532ab32f0f81cafca8d3aa5"> 1005</a></span><span class="preprocessor">#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)</span></div>
|
||
<div class="line"><a id="l01006" name="l01006"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaf0c34a518f87e1e505cd2332e989564a"> 1006</a></span><span class="preprocessor">#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)</span></div>
|
||
<div class="line"><a id="l01007" name="l01007"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga56e2d44b0002f316527b8913866a370d"> 1007</a></span><span class="preprocessor">#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)</span></div>
|
||
<div class="line"><a id="l01008" name="l01008"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga3e1671477190d065ba7c944558336d7e"> 1008</a></span><span class="preprocessor">#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)</span></div>
|
||
<div class="line"><a id="l01009" name="l01009"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga8268ec947929f192559f28c6bf7d1eac"> 1009</a></span><span class="preprocessor">#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)</span></div>
|
||
<div class="line"><a id="l01010" name="l01010"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga0ebf54364c6a2be6eb19ded6b18b6387"> 1010</a></span><span class="preprocessor">#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)</span></div>
|
||
<div class="line"><a id="l01011" name="l01011"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga33dea32fadbaecea161c2ef7927992fd"> 1011</a></span><span class="preprocessor">#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)</span></div>
|
||
<div class="line"><a id="l01012" name="l01012"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gad20f79948e9359125a40bbf6ed063590"> 1012</a></span><span class="preprocessor">#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)</span></div>
|
||
<div class="line"><a id="l01013" name="l01013"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga862855347d6e1d92730dfe17ee8e90b8"> 1013</a></span><span class="preprocessor">#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)</span></div>
|
||
<div class="line"><a id="l01014" name="l01014"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga4265e665d56225412e57a61d87417022"> 1014</a></span><span class="preprocessor">#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)</span></div>
|
||
<div class="line"><a id="l01015" name="l01015"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga9a5bf4728ab93dea5b569f5b972cbe62"> 1015</a></span><span class="preprocessor">#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)</span></div>
|
||
<div class="line"><a id="l01016" name="l01016"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga8543ee4997296af5536b007cd4748f55"> 1016</a></span><span class="preprocessor">#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)</span></div>
|
||
<div class="line"><a id="l01017" name="l01017"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaa5f7b241ed5b756decd835300c9e7bc9"> 1017</a></span><span class="preprocessor">#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)</span></div>
|
||
<div class="line"><a id="l01018" name="l01018"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gac3e357b4c25106ed375fb1affab6bb86"> 1018</a></span><span class="preprocessor">#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)</span></div>
|
||
<div class="line"><a id="l01019" name="l01019"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gae634fe8faa6922690e90fbec2fc86162"> 1019</a></span><span class="preprocessor">#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)</span></div>
|
||
<div class="line"><a id="l01020" name="l01020"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga89b61d6e6b09e94f3fccb7bef34e0263"> 1020</a></span><span class="preprocessor">#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)</span></div>
|
||
<div class="line"><a id="l01021" name="l01021"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gade83162a04bca0b15b39018a8e8ec090"> 1021</a></span><span class="preprocessor">#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)</span></div>
|
||
<div class="line"><a id="l01022" name="l01022"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gabe0d6539ac0026d598274ee7f45b0251"> 1022</a></span><span class="preprocessor">#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)</span></div>
|
||
<div class="line"><a id="l01023" name="l01023"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga94d92270bf587ccdc3a37a5bb5d20467"> 1023</a></span><span class="preprocessor">#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)</span></div>
|
||
<div class="line"><a id="l01024" name="l01024"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaa155689c0e206e6994951dc3cf31052a"> 1024</a></span><span class="preprocessor">#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)</span></div>
|
||
<div class="line"><a id="l01025" name="l01025"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gacd72dbffb1738ca87c838545c4eb85a3"> 1025</a></span><span class="preprocessor">#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)</span></div>
|
||
<div class="line"><a id="l01026" name="l01026"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga04bda70f25c795fb79f163b633ad4a5d"> 1026</a></span><span class="preprocessor">#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)</span></div>
|
||
<div class="line"><a id="l01027" name="l01027"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga4e8b9198748235a1729e1e8f8f24983b"> 1027</a></span><span class="preprocessor">#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)</span></div>
|
||
<div class="line"><a id="l01028" name="l01028"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gad8e45ea6c032d9fce1b0516fff9d8eaa"> 1028</a></span><span class="preprocessor">#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)</span></div>
|
||
<div class="line"><a id="l01029" name="l01029"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaf7b8267b0d439f8f3e82f86be4b9fba1"> 1029</a></span><span class="preprocessor">#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)</span></div>
|
||
<div class="line"><a id="l01030" name="l01030"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gac691ec23dace8b7a649a25acb110217a"> 1030</a></span><span class="preprocessor">#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)</span></div>
|
||
<div class="line"><a id="l01031" name="l01031"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gad18d0b914c7f68cecbee1a2d23a67d38"> 1031</a></span><span class="preprocessor">#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)</span></div>
|
||
<div class="line"><a id="l01032" name="l01032"></a><span class="lineno"> 1032</span> </div>
|
||
<div class="line"><a id="l01034" name="l01034"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaf8aa324ca5011b8173ab16585ed7324a"> 1034</a></span><span class="preprocessor">#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)</span></div>
|
||
<div class="line"><a id="l01035" name="l01035"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga5b72f698b7a048a6f9fcfe2efe5bc1db"> 1035</a></span><span class="preprocessor">#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)</span></div>
|
||
<div class="line"><a id="l01036" name="l01036"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga86162ab3f740db9026c1320d46938b4d"> 1036</a></span><span class="preprocessor">#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)</span></div>
|
||
<div class="line"><a id="l01037" name="l01037"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gade4d3907fd0387ee832f426f52d568bb"> 1037</a></span><span class="preprocessor">#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)</span></div>
|
||
<div class="line"><a id="l01038" name="l01038"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga695c9a2f892363a1c942405c8d351b91"> 1038</a></span><span class="preprocessor">#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)</span></div>
|
||
<div class="line"><a id="l01039" name="l01039"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga6544abc57f9759f610eee09a02442ae6"> 1039</a></span><span class="preprocessor">#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)</span></div>
|
||
<div class="line"><a id="l01040" name="l01040"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaca766f86c8e0b00a8e2b0224dcbb4c82"> 1040</a></span><span class="preprocessor">#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)</span></div>
|
||
<div class="line"><a id="l01041" name="l01041"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga58b9980508ab28022e3be7edc4eda72e"> 1041</a></span><span class="preprocessor">#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)</span></div>
|
||
<div class="line"><a id="l01042" name="l01042"></a><span class="lineno"> 1042</span><span class="comment">/* Legacy define */</span></div>
|
||
<div class="line"><a id="l01043" name="l01043"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gad06cb9e5985bd216a376f26f22303cd6"> 1043</a></span><span class="preprocessor">#define ADC_BASE ADC123_COMMON_BASE</span></div>
|
||
<div class="line"><a id="l01044" name="l01044"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga95dd0abbc6767893b4b02935fa846f52"> 1044</a></span><span class="preprocessor">#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)</span></div>
|
||
<div class="line"><a id="l01045" name="l01045"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga50cd8b47929f18b05efbd0f41253bf8d"> 1045</a></span><span class="preprocessor">#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)</span></div>
|
||
<div class="line"><a id="l01046" name="l01046"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga62246020bf3b34b6a4d8d0e84ec79d3d"> 1046</a></span><span class="preprocessor">#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)</span></div>
|
||
<div class="line"><a id="l01047" name="l01047"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga87371508b3bcdcd98cd1ec629be29061"> 1047</a></span><span class="preprocessor">#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)</span></div>
|
||
<div class="line"><a id="l01048" name="l01048"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga92ae902be7902560939223dd765ece08"> 1048</a></span><span class="preprocessor">#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)</span></div>
|
||
<div class="line"><a id="l01049" name="l01049"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga3eff32f3801db31fb4b61d5618cad54a"> 1049</a></span><span class="preprocessor">#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)</span></div>
|
||
<div class="line"><a id="l01050" name="l01050"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga3a4a06bb84c703084f0509e105ffaf1d"> 1050</a></span><span class="preprocessor">#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)</span></div>
|
||
<div class="line"><a id="l01051" name="l01051"></a><span class="lineno"> 1051</span> </div>
|
||
<div class="line"><a id="l01053" name="l01053"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gad7723846cc5db8e43a44d78cf21f6efa"> 1053</a></span><span class="preprocessor">#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)</span></div>
|
||
<div class="line"><a id="l01054" name="l01054"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gac944a89eb789000ece920c0f89cb6a68"> 1054</a></span><span class="preprocessor">#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)</span></div>
|
||
<div class="line"><a id="l01055" name="l01055"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga26f267dc35338eef219544c51f1e6b3f"> 1055</a></span><span class="preprocessor">#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)</span></div>
|
||
<div class="line"><a id="l01056" name="l01056"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga1a93ab27129f04064089616910c296ec"> 1056</a></span><span class="preprocessor">#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)</span></div>
|
||
<div class="line"><a id="l01057" name="l01057"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gab487b1983d936c4fee3e9e88b95aad9d"> 1057</a></span><span class="preprocessor">#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)</span></div>
|
||
<div class="line"><a id="l01058" name="l01058"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga7f9a3f4223a1a784af464a114978d26e"> 1058</a></span><span class="preprocessor">#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)</span></div>
|
||
<div class="line"><a id="l01059" name="l01059"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga5d8ca4020f2e8c00bde974e8e7c13cfe"> 1059</a></span><span class="preprocessor">#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)</span></div>
|
||
<div class="line"><a id="l01060" name="l01060"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaee4716389f3a1c727495375b76645608"> 1060</a></span><span class="preprocessor">#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)</span></div>
|
||
<div class="line"><a id="l01061" name="l01061"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga50acf918c2e1c4597d5ccfe25eb3ad3d"> 1061</a></span><span class="preprocessor">#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)</span></div>
|
||
<div class="line"><a id="l01062" name="l01062"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga656a447589e785594cbf2f45c835ad7e"> 1062</a></span><span class="preprocessor">#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)</span></div>
|
||
<div class="line"><a id="l01063" name="l01063"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga0e681b03f364532055d88f63fec0d99d"> 1063</a></span><span class="preprocessor">#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)</span></div>
|
||
<div class="line"><a id="l01064" name="l01064"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga8e21f4845015730c5731763169ec0e9b"> 1064</a></span><span class="preprocessor">#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)</span></div>
|
||
<div class="line"><a id="l01065" name="l01065"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gab2d8a917a0e4ea99a22ac6ebf279bc72"> 1065</a></span><span class="preprocessor">#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)</span></div>
|
||
<div class="line"><a id="l01066" name="l01066"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga0d3c52aa35dcc68f78b704dfde57ba95"> 1066</a></span><span class="preprocessor">#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)</span></div>
|
||
<div class="line"><a id="l01067" name="l01067"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga5b4152cef577e37eccc9311d8bdbf3c2"> 1067</a></span><span class="preprocessor">#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)</span></div>
|
||
<div class="line"><a id="l01068" name="l01068"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga48a551ee91d3f07dd74347fdb35c703d"> 1068</a></span><span class="preprocessor">#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)</span></div>
|
||
<div class="line"><a id="l01069" name="l01069"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gac51deb54ff7cfe1290dfcf517ae67127"> 1069</a></span><span class="preprocessor">#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)</span></div>
|
||
<div class="line"><a id="l01070" name="l01070"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga757a3c0d866c0fe68c6176156065a26b"> 1070</a></span><span class="preprocessor">#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)</span></div>
|
||
<div class="line"><a id="l01071" name="l01071"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga0ded7bed8969fe2e2d616e7f90eb7654"> 1071</a></span><span class="preprocessor">#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)</span></div>
|
||
<div class="line"><a id="l01072" name="l01072"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga58998ddc40adb6361704d6c9dad08125"> 1072</a></span><span class="preprocessor">#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)</span></div>
|
||
<div class="line"><a id="l01073" name="l01073"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga82186dd6d3f60995d428b34c041919d7"> 1073</a></span><span class="preprocessor">#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)</span></div>
|
||
<div class="line"><a id="l01074" name="l01074"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gab72a9ae145053ee13d1d491fb5c1df64"> 1074</a></span><span class="preprocessor">#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)</span></div>
|
||
<div class="line"><a id="l01075" name="l01075"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gac4c67b24726ba6b94d03adb351bcec4d"> 1075</a></span><span class="preprocessor">#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)</span></div>
|
||
<div class="line"><a id="l01076" name="l01076"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga35512bdc3f5e9df4557c2fbe7935d0b1"> 1076</a></span><span class="preprocessor">#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)</span></div>
|
||
<div class="line"><a id="l01077" name="l01077"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaed33a06f08188466f2ede06160984e9a"> 1077</a></span><span class="preprocessor">#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)</span></div>
|
||
<div class="line"><a id="l01078" name="l01078"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaf3a9480e08c6ae94f4482e0cdaebdd17"> 1078</a></span><span class="preprocessor">#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)</span></div>
|
||
<div class="line"><a id="l01079" name="l01079"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gad1e67740e6301233473f64638145dd1f"> 1079</a></span><span class="preprocessor">#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)</span></div>
|
||
<div class="line"><a id="l01080" name="l01080"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaed1460fdc407b6decfbffccb0260d0af"> 1080</a></span><span class="preprocessor">#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)</span></div>
|
||
<div class="line"><a id="l01081" name="l01081"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga5e81174c96fd204fa7c82c815e85c8e6"> 1081</a></span><span class="preprocessor">#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)</span></div>
|
||
<div class="line"><a id="l01082" name="l01082"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaa9faa708ad2440d24eb1064cba9bb06d"> 1082</a></span><span class="preprocessor">#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)</span></div>
|
||
<div class="line"><a id="l01083" name="l01083"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gad965a7b1106ece575ed3da10c45c65cc"> 1083</a></span><span class="preprocessor">#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)</span></div>
|
||
<div class="line"><a id="l01084" name="l01084"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga3cf7005808feb61bff1fee01e50a711a"> 1084</a></span><span class="preprocessor">#define ETH_MAC_BASE (ETH_BASE)</span></div>
|
||
<div class="line"><a id="l01085" name="l01085"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga4946f2b3b03f7998343ac1778fbcf725"> 1085</a></span><span class="preprocessor">#define ETH_MMC_BASE (ETH_BASE + 0x0100UL)</span></div>
|
||
<div class="line"><a id="l01086" name="l01086"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaa0f60b922aeb7275c785cbaa8f94ecf0"> 1086</a></span><span class="preprocessor">#define ETH_PTP_BASE (ETH_BASE + 0x0700UL)</span></div>
|
||
<div class="line"><a id="l01087" name="l01087"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gace2114e1b37c1ba88d60f3e831b67e93"> 1087</a></span><span class="preprocessor">#define ETH_DMA_BASE (ETH_BASE + 0x1000UL)</span></div>
|
||
<div class="line"><a id="l01088" name="l01088"></a><span class="lineno"> 1088</span> </div>
|
||
<div class="line"><a id="l01090" name="l01090"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga55b794507e021135486de57129a2505c"> 1090</a></span><span class="preprocessor">#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)</span></div>
|
||
<div class="line"><a id="l01091" name="l01091"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gab92662976cfe62457141e5b4f83d541c"> 1091</a></span><span class="preprocessor">#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)</span></div>
|
||
<div class="line"><a id="l01092" name="l01092"></a><span class="lineno"> 1092</span> </div>
|
||
<div class="line"><a id="l01094" name="l01094"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gad196fe6f5e4041b201d14f43508c06d2"> 1094</a></span><span class="preprocessor">#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL)</span></div>
|
||
<div class="line"><a id="l01095" name="l01095"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaea182589c84aee30b7f735474d8774e2"> 1095</a></span><span class="preprocessor">#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL)</span></div>
|
||
<div class="line"><a id="l01096" name="l01096"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga851707a200f63e03c336073706fdce1d"> 1096</a></span><span class="preprocessor">#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060UL)</span></div>
|
||
<div class="line"><a id="l01097" name="l01097"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaf9e5417133160b0bdd0498d982acec19"> 1097</a></span><span class="preprocessor">#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL)</span></div>
|
||
<div class="line"><a id="l01098" name="l01098"></a><span class="lineno"> 1098</span> </div>
|
||
<div class="line"><a id="l01099" name="l01099"></a><span class="lineno"> 1099</span> </div>
|
||
<div class="line"><a id="l01101" name="l01101"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga4adaf4fd82ccc3a538f1f27a70cdbbef"> 1101</a></span><span class="preprocessor">#define DBGMCU_BASE (&DEBUG_MCU)</span></div>
|
||
<div class="line"><a id="l01103" name="l01103"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaa405d2ebfd7e9394237b6639f16a5409"> 1103</a></span><span class="preprocessor">#define USB_OTG_HS_PERIPH_BASE 0x40040000UL</span></div>
|
||
<div class="line"><a id="l01104" name="l01104"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaa86d4c80849a74938924e73937b904e7"> 1104</a></span><span class="preprocessor">#define USB_OTG_FS_PERIPH_BASE 0x50000000UL</span></div>
|
||
<div class="line"><a id="l01105" name="l01105"></a><span class="lineno"> 1105</span> </div>
|
||
<div class="line"><a id="l01106" name="l01106"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga044aa4388e72d9d47a03f387fb8926fb"> 1106</a></span><span class="preprocessor">#define USB_OTG_GLOBAL_BASE 0x000UL</span></div>
|
||
<div class="line"><a id="l01107" name="l01107"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga4d74a337597a77b1fca978202b519a18"> 1107</a></span><span class="preprocessor">#define USB_OTG_DEVICE_BASE 0x800UL</span></div>
|
||
<div class="line"><a id="l01108" name="l01108"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gad8f69041452615aeb3948600e3882246"> 1108</a></span><span class="preprocessor">#define USB_OTG_IN_ENDPOINT_BASE 0x900UL</span></div>
|
||
<div class="line"><a id="l01109" name="l01109"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaf0e972b8f028ecf44a652029efbd4642"> 1109</a></span><span class="preprocessor">#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL</span></div>
|
||
<div class="line"><a id="l01110" name="l01110"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga6fdb7429ad88e2d69440d6ecc4f4199e"> 1110</a></span><span class="preprocessor">#define USB_OTG_EP_REG_SIZE 0x20UL</span></div>
|
||
<div class="line"><a id="l01111" name="l01111"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga3bb2dd6c82eefd8587b6146ba36ae071"> 1111</a></span><span class="preprocessor">#define USB_OTG_HOST_BASE 0x400UL</span></div>
|
||
<div class="line"><a id="l01112" name="l01112"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga42f433cb79ca69f09972e690fda6737a"> 1112</a></span><span class="preprocessor">#define USB_OTG_HOST_PORT_BASE 0x440UL</span></div>
|
||
<div class="line"><a id="l01113" name="l01113"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga942c8c5241b80fbcf638fea0fa18bebd"> 1113</a></span><span class="preprocessor">#define USB_OTG_HOST_CHANNEL_BASE 0x500UL</span></div>
|
||
<div class="line"><a id="l01114" name="l01114"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga266cb1dbb50faf447f9c15d2ee93a522"> 1114</a></span><span class="preprocessor">#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL</span></div>
|
||
<div class="line"><a id="l01115" name="l01115"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaa9766975aca084c257730879568bc7cf"> 1115</a></span><span class="preprocessor">#define USB_OTG_PCGCCTL_BASE 0xE00UL</span></div>
|
||
<div class="line"><a id="l01116" name="l01116"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gace340350802904868673f0e839c4fa04"> 1116</a></span><span class="preprocessor">#define USB_OTG_FIFO_BASE 0x1000UL</span></div>
|
||
<div class="line"><a id="l01117" name="l01117"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga8781c4b2406c740d9fe540737a6a0188"> 1117</a></span><span class="preprocessor">#define USB_OTG_FIFO_SIZE 0x1000UL</span></div>
|
||
<div class="line"><a id="l01118" name="l01118"></a><span class="lineno"> 1118</span> </div>
|
||
<div class="line"><a id="l01119" name="l01119"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga664eda42b83c919b153b07b23348be67"> 1119</a></span><span class="preprocessor">#define UID_BASE 0x1FFF7A10UL </span></div>
|
||
<div class="line"><a id="l01120" name="l01120"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga776d985f2d4d40b588ef6ca9d573af78"> 1120</a></span><span class="preprocessor">#define FLASHSIZE_BASE 0x1FFF7A22UL </span></div>
|
||
<div class="line"><a id="l01121" name="l01121"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga88fc8a2912bd1ac72c6eddb456f0b096"> 1121</a></span><span class="preprocessor">#define PACKAGE_BASE 0x1FFF7BF0UL </span></div>
|
||
<div class="line"><a id="l01129" name="l01129"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga3cfac9f2e43673f790f8668d48b4b92b"> 1129</a></span><span class="preprocessor">#define TIM2 ((TIM_TypeDef *) TIM2_BASE)</span></div>
|
||
<div class="line"><a id="l01130" name="l01130"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga61ee4c391385607d7af432b63905fcc9"> 1130</a></span><span class="preprocessor">#define TIM3 ((TIM_TypeDef *) TIM3_BASE)</span></div>
|
||
<div class="line"><a id="l01131" name="l01131"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga91a09bad8bdc7a1cb3d85cf49c94c8ec"> 1131</a></span><span class="preprocessor">#define TIM4 ((TIM_TypeDef *) TIM4_BASE)</span></div>
|
||
<div class="line"><a id="l01132" name="l01132"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga5125ff6a23a2ed66e2e19bd196128c14"> 1132</a></span><span class="preprocessor">#define TIM5 ((TIM_TypeDef *) TIM5_BASE)</span></div>
|
||
<div class="line"><a id="l01133" name="l01133"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gac7b4ed55f9201b498b38c962cca97314"> 1133</a></span><span class="preprocessor">#define TIM6 ((TIM_TypeDef *) TIM6_BASE)</span></div>
|
||
<div class="line"><a id="l01134" name="l01134"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga49267c49946fd61db6af8b49bcf16394"> 1134</a></span><span class="preprocessor">#define TIM7 ((TIM_TypeDef *) TIM7_BASE)</span></div>
|
||
<div class="line"><a id="l01135" name="l01135"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga2397f8a0f8e7aa10cf8e8c049e431e53"> 1135</a></span><span class="preprocessor">#define TIM12 ((TIM_TypeDef *) TIM12_BASE)</span></div>
|
||
<div class="line"><a id="l01136" name="l01136"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga5a959a833074d59bf6cc7fb437c65b18"> 1136</a></span><span class="preprocessor">#define TIM13 ((TIM_TypeDef *) TIM13_BASE)</span></div>
|
||
<div class="line"><a id="l01137" name="l01137"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga2dd30f46fad69dd73e1d8941a43daffe"> 1137</a></span><span class="preprocessor">#define TIM14 ((TIM_TypeDef *) TIM14_BASE)</span></div>
|
||
<div class="line"><a id="l01138" name="l01138"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga5359a088f5d8b20ce74d920e46059304"> 1138</a></span><span class="preprocessor">#define RTC ((RTC_TypeDef *) RTC_BASE)</span></div>
|
||
<div class="line"><a id="l01139" name="l01139"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga9821fd01757986612ddb8982e2fe27f1"> 1139</a></span><span class="preprocessor">#define WWDG ((WWDG_TypeDef *) WWDG_BASE)</span></div>
|
||
<div class="line"><a id="l01140" name="l01140"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gad16b79dd94ee85d261d08a8ee94187e7"> 1140</a></span><span class="preprocessor">#define IWDG ((IWDG_TypeDef *) IWDG_BASE)</span></div>
|
||
<div class="line"><a id="l01141" name="l01141"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga9efe6de71871a01dd38abcb229f30c02"> 1141</a></span><span class="preprocessor">#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)</span></div>
|
||
<div class="line"><a id="l01142" name="l01142"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gaf2c3d8ce359dcfbb2261e07ed42af72b"> 1142</a></span><span class="preprocessor">#define SPI2 ((SPI_TypeDef *) SPI2_BASE)</span></div>
|
||
<div class="line"><a id="l01143" name="l01143"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gab2339cbf25502bf562b19208b1b257fc"> 1143</a></span><span class="preprocessor">#define SPI3 ((SPI_TypeDef *) SPI3_BASE)</span></div>
|
||
<div class="line"><a id="l01144" name="l01144"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga15b3a03302ed53911099c5216da0b1cf"> 1144</a></span><span class="preprocessor">#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)</span></div>
|
||
<div class="line"><a id="l01145" name="l01145"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gaf114a9eab03ca08a6fb720e511595930"> 1145</a></span><span class="preprocessor">#define USART2 ((USART_TypeDef *) USART2_BASE)</span></div>
|
||
<div class="line"><a id="l01146" name="l01146"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga2350115553c1fe0a7bc14e6a7ec6a225"> 1146</a></span><span class="preprocessor">#define USART3 ((USART_TypeDef *) USART3_BASE)</span></div>
|
||
<div class="line"><a id="l01147" name="l01147"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga7c035f6f443c999fc043b2b7fb598800"> 1147</a></span><span class="preprocessor">#define UART4 ((USART_TypeDef *) UART4_BASE)</span></div>
|
||
<div class="line"><a id="l01148" name="l01148"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga9274e37cf5e8a174fc5dd627b98ec0fe"> 1148</a></span><span class="preprocessor">#define UART5 ((USART_TypeDef *) UART5_BASE)</span></div>
|
||
<div class="line"><a id="l01149" name="l01149"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gab45d257574da6fe1f091cc45b7eda6cc"> 1149</a></span><span class="preprocessor">#define I2C1 ((I2C_TypeDef *) I2C1_BASE)</span></div>
|
||
<div class="line"><a id="l01150" name="l01150"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gafa60ac20c1921ef1002083bb3e1f5d16"> 1150</a></span><span class="preprocessor">#define I2C2 ((I2C_TypeDef *) I2C2_BASE)</span></div>
|
||
<div class="line"><a id="l01151" name="l01151"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga1489b37ed2bca9d9c659119590583bda"> 1151</a></span><span class="preprocessor">#define I2C3 ((I2C_TypeDef *) I2C3_BASE)</span></div>
|
||
<div class="line"><a id="l01152" name="l01152"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga4964ecb6a5c689aaf8ee2832b8093aac"> 1152</a></span><span class="preprocessor">#define CAN1 ((CAN_TypeDef *) CAN1_BASE)</span></div>
|
||
<div class="line"><a id="l01153" name="l01153"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gac5e4c86ed487dc91418b156e24808033"> 1153</a></span><span class="preprocessor">#define CAN2 ((CAN_TypeDef *) CAN2_BASE)</span></div>
|
||
<div class="line"><a id="l01154" name="l01154"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga04651c526497822a859942b928e57f8e"> 1154</a></span><span class="preprocessor">#define PWR ((PWR_TypeDef *) PWR_BASE)</span></div>
|
||
<div class="line"><a id="l01155" name="l01155"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gaffb5ff8779fa698f3c7165a617d56e4f"> 1155</a></span><span class="preprocessor">#define DAC1 ((DAC_TypeDef *) DAC_BASE)</span></div>
|
||
<div class="line"><a id="l01156" name="l01156"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga4aa2a4ab86ce00c23035e5cee2e7fc7e"> 1156</a></span><span class="preprocessor">#define DAC ((DAC_TypeDef *) DAC_BASE) </span><span class="comment">/* Kept for legacy purpose */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l01157" name="l01157"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga2e87451fea8dc9380056d3cfc5ed81fb"> 1157</a></span><span class="preprocessor">#define TIM1 ((TIM_TypeDef *) TIM1_BASE)</span></div>
|
||
<div class="line"><a id="l01158" name="l01158"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga9a3660400b17735e91331f256095810e"> 1158</a></span><span class="preprocessor">#define TIM8 ((TIM_TypeDef *) TIM8_BASE)</span></div>
|
||
<div class="line"><a id="l01159" name="l01159"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga92871691058ff7ccffd7635930cb08da"> 1159</a></span><span class="preprocessor">#define USART1 ((USART_TypeDef *) USART1_BASE)</span></div>
|
||
<div class="line"><a id="l01160" name="l01160"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga2dab39a19ce3dd05fe360dcbb7b5dc84"> 1160</a></span><span class="preprocessor">#define USART6 ((USART_TypeDef *) USART6_BASE)</span></div>
|
||
<div class="line"><a id="l01161" name="l01161"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga90d2d5c526ce5c0a551f533eccbee71a"> 1161</a></span><span class="preprocessor">#define ADC1 ((ADC_TypeDef *) ADC1_BASE)</span></div>
|
||
<div class="line"><a id="l01162" name="l01162"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gac5503ae96c26b4475226f96715a1bf1e"> 1162</a></span><span class="preprocessor">#define ADC2 ((ADC_TypeDef *) ADC2_BASE)</span></div>
|
||
<div class="line"><a id="l01163" name="l01163"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gae917784606daf6b04c9b7b96b40c2f74"> 1163</a></span><span class="preprocessor">#define ADC3 ((ADC_TypeDef *) ADC3_BASE)</span></div>
|
||
<div class="line"><a id="l01164" name="l01164"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga813de18391e45c0854aafd470c2d547f"> 1164</a></span><span class="preprocessor">#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)</span></div>
|
||
<div class="line"><a id="l01165" name="l01165"></a><span class="lineno"> 1165</span> <span class="comment">/* Legacy define */</span></div>
|
||
<div class="line"><a id="l01166" name="l01166"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga54d148b91f3d356713f7e367a2243bea"> 1166</a></span><span class="preprocessor">#define ADC ADC123_COMMON</span></div>
|
||
<div class="line"><a id="l01167" name="l01167"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga8149aa2760fffac16bc75216d5fd9331"> 1167</a></span><span class="preprocessor">#define SDIO ((SDIO_TypeDef *) SDIO_BASE)</span></div>
|
||
<div class="line"><a id="l01168" name="l01168"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gad483be344a28ac800be8f03654a9612f"> 1168</a></span><span class="preprocessor">#define SPI1 ((SPI_TypeDef *) SPI1_BASE)</span></div>
|
||
<div class="line"><a id="l01169" name="l01169"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga3c833fe1c486cb62250ccbca32899cb8"> 1169</a></span><span class="preprocessor">#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)</span></div>
|
||
<div class="line"><a id="l01170" name="l01170"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga9189e770cd9b63dadd36683eb9843cac"> 1170</a></span><span class="preprocessor">#define EXTI ((EXTI_TypeDef *) EXTI_BASE)</span></div>
|
||
<div class="line"><a id="l01171" name="l01171"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gaf52b4b4c36110a0addfa98059f54a50e"> 1171</a></span><span class="preprocessor">#define TIM9 ((TIM_TypeDef *) TIM9_BASE)</span></div>
|
||
<div class="line"><a id="l01172" name="l01172"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga46b2ad3f5f506f0f8df0d2ec3e767267"> 1172</a></span><span class="preprocessor">#define TIM10 ((TIM_TypeDef *) TIM10_BASE)</span></div>
|
||
<div class="line"><a id="l01173" name="l01173"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gacfd11ef966c7165f57e2cebe0abc71ad"> 1173</a></span><span class="preprocessor">#define TIM11 ((TIM_TypeDef *) TIM11_BASE)</span></div>
|
||
<div class="line"><a id="l01174" name="l01174"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gac485358099728ddae050db37924dd6b7"> 1174</a></span><span class="preprocessor">#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)</span></div>
|
||
<div class="line"><a id="l01175" name="l01175"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga68b66ac73be4c836db878a42e1fea3cd"> 1175</a></span><span class="preprocessor">#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)</span></div>
|
||
<div class="line"><a id="l01176" name="l01176"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga2dca03332d620196ba943bc2346eaa08"> 1176</a></span><span class="preprocessor">#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)</span></div>
|
||
<div class="line"><a id="l01177" name="l01177"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga7580b1a929ea9df59725ba9c18eba6ac"> 1177</a></span><span class="preprocessor">#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)</span></div>
|
||
<div class="line"><a id="l01178" name="l01178"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gae04bdb5e8acc47cab1d0532e6b0d0763"> 1178</a></span><span class="preprocessor">#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)</span></div>
|
||
<div class="line"><a id="l01179" name="l01179"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga43c3022dede7c9db7a58d3c3409dbc8d"> 1179</a></span><span class="preprocessor">#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)</span></div>
|
||
<div class="line"><a id="l01180" name="l01180"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga02a2a23a32f9b02166a8c64012842414"> 1180</a></span><span class="preprocessor">#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)</span></div>
|
||
<div class="line"><a id="l01181" name="l01181"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gadeacbb43ae86c879945afe98c679b285"> 1181</a></span><span class="preprocessor">#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)</span></div>
|
||
<div class="line"><a id="l01182" name="l01182"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gad15f13545ecdbbabfccf43d5997e5ade"> 1182</a></span><span class="preprocessor">#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)</span></div>
|
||
<div class="line"><a id="l01183" name="l01183"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga4381bb54c2dbc34500521165aa7b89b1"> 1183</a></span><span class="preprocessor">#define CRC ((CRC_TypeDef *) CRC_BASE)</span></div>
|
||
<div class="line"><a id="l01184" name="l01184"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga74944438a086975793d26ae48d5882d4"> 1184</a></span><span class="preprocessor">#define RCC ((RCC_TypeDef *) RCC_BASE)</span></div>
|
||
<div class="line"><a id="l01185" name="l01185"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga844ea28ba1e0a5a0e497f16b61ea306b"> 1185</a></span><span class="preprocessor">#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)</span></div>
|
||
<div class="line"><a id="l01186" name="l01186"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gacc16d2a5937f7585320a98f7f6b578f9"> 1186</a></span><span class="preprocessor">#define DMA1 ((DMA_TypeDef *) DMA1_BASE)</span></div>
|
||
<div class="line"><a id="l01187" name="l01187"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga61247dd5d594289c404dd8774202dfd8"> 1187</a></span><span class="preprocessor">#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)</span></div>
|
||
<div class="line"><a id="l01188" name="l01188"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gaf7d82f110f19982d483eebc465d222b2"> 1188</a></span><span class="preprocessor">#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)</span></div>
|
||
<div class="line"><a id="l01189" name="l01189"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gad0e2140b8eeec3594035f1a7bf2a7250"> 1189</a></span><span class="preprocessor">#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)</span></div>
|
||
<div class="line"><a id="l01190" name="l01190"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga96ac1af7a92469fe86a9fbdec091f25d"> 1190</a></span><span class="preprocessor">#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)</span></div>
|
||
<div class="line"><a id="l01191" name="l01191"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga87df45f4b82e0b3a8c1b17f1a77aecdb"> 1191</a></span><span class="preprocessor">#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)</span></div>
|
||
<div class="line"><a id="l01192" name="l01192"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gac3abc20f80e25c19b02104ad34eae652"> 1192</a></span><span class="preprocessor">#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)</span></div>
|
||
<div class="line"><a id="l01193" name="l01193"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gac95127480470900755953f1cfe68567d"> 1193</a></span><span class="preprocessor">#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)</span></div>
|
||
<div class="line"><a id="l01194" name="l01194"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga8ecdeaf43d0f4207dab1fdb4d7bf8d26"> 1194</a></span><span class="preprocessor">#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)</span></div>
|
||
<div class="line"><a id="l01195" name="l01195"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga506520140eec1708bc7570c49bdf972d"> 1195</a></span><span class="preprocessor">#define DMA2 ((DMA_TypeDef *) DMA2_BASE)</span></div>
|
||
<div class="line"><a id="l01196" name="l01196"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga3a2efe5fd7a7a79be3b08a1670bbd016"> 1196</a></span><span class="preprocessor">#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)</span></div>
|
||
<div class="line"><a id="l01197" name="l01197"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gae96f15d34d3c41c16fce69bc2878151a"> 1197</a></span><span class="preprocessor">#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)</span></div>
|
||
<div class="line"><a id="l01198" name="l01198"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga71bb410664b861ff0520f08976e24ee1"> 1198</a></span><span class="preprocessor">#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)</span></div>
|
||
<div class="line"><a id="l01199" name="l01199"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gaa6ead6a5ca6b8df70b5505aaeec6fd2e"> 1199</a></span><span class="preprocessor">#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)</span></div>
|
||
<div class="line"><a id="l01200" name="l01200"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gae32674772021620800275dd3b6d62c2f"> 1200</a></span><span class="preprocessor">#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)</span></div>
|
||
<div class="line"><a id="l01201" name="l01201"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gac40f58718761251875b5a897287efd83"> 1201</a></span><span class="preprocessor">#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)</span></div>
|
||
<div class="line"><a id="l01202" name="l01202"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga11a00b283e0911cd427e277e5a314ccc"> 1202</a></span><span class="preprocessor">#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)</span></div>
|
||
<div class="line"><a id="l01203" name="l01203"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#gacc135dbca0eca67d5aa0abc555f053ce"> 1203</a></span><span class="preprocessor">#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)</span></div>
|
||
<div class="line"><a id="l01204" name="l01204"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga3a3f60de4318afbd0b3318e7a416aadc"> 1204</a></span><span class="preprocessor">#define ETH ((ETH_TypeDef *) ETH_BASE) </span></div>
|
||
<div class="line"><a id="l01205" name="l01205"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga049d9f61cb078d642e68f3c22bb6d90c"> 1205</a></span><span class="preprocessor">#define DCMI ((DCMI_TypeDef *) DCMI_BASE)</span></div>
|
||
<div class="line"><a id="l01206" name="l01206"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga5b0885b8b55bbc13691092b704d9309f"> 1206</a></span><span class="preprocessor">#define RNG ((RNG_TypeDef *) RNG_BASE)</span></div>
|
||
<div class="line"><a id="l01207" name="l01207"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga2a759bad07fe730c99f9e1490e646220"> 1207</a></span><span class="preprocessor">#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)</span></div>
|
||
<div class="line"><a id="l01208" name="l01208"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga422986101f42a8811ae89ac69deb2759"> 1208</a></span><span class="preprocessor">#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)</span></div>
|
||
<div class="line"><a id="l01209" name="l01209"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga37d7365ac249959b103d7b91d74e776d"> 1209</a></span><span class="preprocessor">#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)</span></div>
|
||
<div class="line"><a id="l01210" name="l01210"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga5aa00e4ac522693c6a21bc23ef5a96df"> 1210</a></span><span class="preprocessor">#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)</span></div>
|
||
<div class="line"><a id="l01211" name="l01211"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga92ec6d9ec2251fda7d4ce09748cd74b4"> 1211</a></span><span class="preprocessor">#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)</span></div>
|
||
<div class="line"><a id="l01212" name="l01212"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga9ebb053ee138fb47cdfede0e3371123d"> 1212</a></span><span class="preprocessor">#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)</span></div>
|
||
<div class="line"><a id="l01213" name="l01213"></a><span class="lineno"><a class="line" href="group___peripheral__declaration.html#ga820f5f7cb0a7af72a2444a1903fd83bc"> 1213</a></span><span class="preprocessor">#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)</span></div>
|
||
<div class="line"><a id="l01214" name="l01214"></a><span class="lineno"> 1214</span> </div>
|
||
<div class="line"><a id="l01226" name="l01226"></a><span class="lineno"><a class="line" href="group___hardware___constant___definition.html#gab9ea77371b070034ca2a56381a7e9de7"> 1226</a></span><span class="preprocessor">#define LSI_STARTUP_TIME 40U </span></div>
|
||
<div class="line"><a id="l01235" name="l01235"></a><span class="lineno"> 1235</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l01236" name="l01236"></a><span class="lineno"> 1236</span><span class="comment">/* Peripheral Registers_Bits_Definition */</span></div>
|
||
<div class="line"><a id="l01237" name="l01237"></a><span class="lineno"> 1237</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l01238" name="l01238"></a><span class="lineno"> 1238</span> </div>
|
||
<div class="line"><a id="l01239" name="l01239"></a><span class="lineno"> 1239</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l01240" name="l01240"></a><span class="lineno"> 1240</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l01241" name="l01241"></a><span class="lineno"> 1241</span><span class="comment">/* Analog to Digital Converter */</span></div>
|
||
<div class="line"><a id="l01242" name="l01242"></a><span class="lineno"> 1242</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l01243" name="l01243"></a><span class="lineno"> 1243</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l01244" name="l01244"></a><span class="lineno"> 1244</span><span class="comment">/*</span></div>
|
||
<div class="line"><a id="l01245" name="l01245"></a><span class="lineno"> 1245</span><span class="comment"> * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)</span></div>
|
||
<div class="line"><a id="l01246" name="l01246"></a><span class="lineno"> 1246</span><span class="comment"> */</span></div>
|
||
<div class="line"><a id="l01247" name="l01247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e2d417bccd8d576e16729c3e5a25cb8"> 1247</a></span><span class="preprocessor">#define ADC_MULTIMODE_SUPPORT </span></div>
|
||
<div class="line"><a id="l01249" name="l01249"></a><span class="lineno"> 1249</span><span class="comment">/******************** Bit definition for ADC_SR register ********************/</span></div>
|
||
<div class="line"><a id="l01250" name="l01250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1c2e0f2c5f57df27447e2c4055d1a3b"> 1250</a></span><span class="preprocessor">#define ADC_SR_AWD_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01251" name="l01251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1f5cef448ce47b4bf2e3d71ed7debf3"> 1251</a></span><span class="preprocessor">#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) </span></div>
|
||
<div class="line"><a id="l01252" name="l01252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b7f27694281e4cad956da567e5583b2"> 1252</a></span><span class="preprocessor">#define ADC_SR_AWD ADC_SR_AWD_Msk </span></div>
|
||
<div class="line"><a id="l01253" name="l01253"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a468d077f5722ce97ae2d5d907b6fc5"> 1253</a></span><span class="preprocessor">#define ADC_SR_EOC_Pos (1U) </span></div>
|
||
<div class="line"><a id="l01254" name="l01254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga370d791b736d2b691df00221dbd3041a"> 1254</a></span><span class="preprocessor">#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) </span></div>
|
||
<div class="line"><a id="l01255" name="l01255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3dc295c5253743aeb2cda582953b7b53"> 1255</a></span><span class="preprocessor">#define ADC_SR_EOC ADC_SR_EOC_Msk </span></div>
|
||
<div class="line"><a id="l01256" name="l01256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf45ea3ec6ba328fe2eb3d57cc061fcf6"> 1256</a></span><span class="preprocessor">#define ADC_SR_JEOC_Pos (2U) </span></div>
|
||
<div class="line"><a id="l01257" name="l01257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e5d245721d37e76b53660c9d2094000"> 1257</a></span><span class="preprocessor">#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) </span></div>
|
||
<div class="line"><a id="l01258" name="l01258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc9f07589bb1a4e398781df372389b56"> 1258</a></span><span class="preprocessor">#define ADC_SR_JEOC ADC_SR_JEOC_Msk </span></div>
|
||
<div class="line"><a id="l01259" name="l01259"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66b7ea4bf6dc5c2b0406d52f5c728716"> 1259</a></span><span class="preprocessor">#define ADC_SR_JSTRT_Pos (3U) </span></div>
|
||
<div class="line"><a id="l01260" name="l01260"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72dec61b0a9eaf8380b4ba19e8bd3750"> 1260</a></span><span class="preprocessor">#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) </span></div>
|
||
<div class="line"><a id="l01261" name="l01261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7340a01ffec051c06e80a037eee58a14"> 1261</a></span><span class="preprocessor">#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk </span></div>
|
||
<div class="line"><a id="l01262" name="l01262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21a6327becffbd34525a0960e7be990e"> 1262</a></span><span class="preprocessor">#define ADC_SR_STRT_Pos (4U) </span></div>
|
||
<div class="line"><a id="l01263" name="l01263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabffe4cd9e85d28f2e29d16acf305c48"> 1263</a></span><span class="preprocessor">#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) </span></div>
|
||
<div class="line"><a id="l01264" name="l01264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45eb11ad986d8220cde9fa47a91ed222"> 1264</a></span><span class="preprocessor">#define ADC_SR_STRT ADC_SR_STRT_Msk </span></div>
|
||
<div class="line"><a id="l01265" name="l01265"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50c7432adead5e587179e4c67713f193"> 1265</a></span><span class="preprocessor">#define ADC_SR_OVR_Pos (5U) </span></div>
|
||
<div class="line"><a id="l01266" name="l01266"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f963f57c46a01cd982b88b3a71574eb"> 1266</a></span><span class="preprocessor">#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) </span></div>
|
||
<div class="line"><a id="l01267" name="l01267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e5211d5e3e53cdedf4d9d6fe4ce2a45"> 1267</a></span><span class="preprocessor">#define ADC_SR_OVR ADC_SR_OVR_Msk </span></div>
|
||
<div class="line"><a id="l01269" name="l01269"></a><span class="lineno"> 1269</span><span class="comment">/******************* Bit definition for ADC_CR1 register ********************/</span></div>
|
||
<div class="line"><a id="l01270" name="l01270"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga593a52bc26648e0eceef061f5a8c32e0"> 1270</a></span><span class="preprocessor">#define ADC_CR1_AWDCH_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01271" name="l01271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cc3a347eb0150e7f476f67df64e2276"> 1271</a></span><span class="preprocessor">#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) </span></div>
|
||
<div class="line"><a id="l01272" name="l01272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8bb755c7059bb2d4f5e2e999d2a2677"> 1272</a></span><span class="preprocessor">#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk </span></div>
|
||
<div class="line"><a id="l01273" name="l01273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18725d77c35c173cdb5bdab658d9dace"> 1273</a></span><span class="preprocessor">#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) </span></div>
|
||
<div class="line"><a id="l01274" name="l01274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcd37244d74db7c9a34a4f08b94301ae"> 1274</a></span><span class="preprocessor">#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) </span></div>
|
||
<div class="line"><a id="l01275" name="l01275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga625eebdc95937325cad90a151853f5a0"> 1275</a></span><span class="preprocessor">#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) </span></div>
|
||
<div class="line"><a id="l01276" name="l01276"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb768d4aafbabc114d4650cf962392ec"> 1276</a></span><span class="preprocessor">#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) </span></div>
|
||
<div class="line"><a id="l01277" name="l01277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf37f3c0d7c72192803d0772e076cf8ee"> 1277</a></span><span class="preprocessor">#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) </span></div>
|
||
<div class="line"><a id="l01278" name="l01278"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac14738c525ee769e8971601f631ef594"> 1278</a></span><span class="preprocessor">#define ADC_CR1_EOCIE_Pos (5U) </span></div>
|
||
<div class="line"><a id="l01279" name="l01279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4cb8db4061b4ebb927dbf6bef84e9ae0"> 1279</a></span><span class="preprocessor">#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) </span></div>
|
||
<div class="line"><a id="l01280" name="l01280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa39fee2e812a7ca45998cccf32e90aea"> 1280</a></span><span class="preprocessor">#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk </span></div>
|
||
<div class="line"><a id="l01281" name="l01281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga553aa50487015ce07880bd3c62887698"> 1281</a></span><span class="preprocessor">#define ADC_CR1_AWDIE_Pos (6U) </span></div>
|
||
<div class="line"><a id="l01282" name="l01282"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34c5eb25f1b9dc807fabc06c90fe9df6"> 1282</a></span><span class="preprocessor">#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) </span></div>
|
||
<div class="line"><a id="l01283" name="l01283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd44f86b189696d5a3780342516de722"> 1283</a></span><span class="preprocessor">#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk </span></div>
|
||
<div class="line"><a id="l01284" name="l01284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89dc37165238a2b3a31bad4bf2241b12"> 1284</a></span><span class="preprocessor">#define ADC_CR1_JEOCIE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l01285" name="l01285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c41e259f643939c71619ce4f743554a"> 1285</a></span><span class="preprocessor">#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) </span></div>
|
||
<div class="line"><a id="l01286" name="l01286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c46fc1dc6c63acf88821f46a8f6d5e7"> 1286</a></span><span class="preprocessor">#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk </span></div>
|
||
<div class="line"><a id="l01287" name="l01287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dcc7aec82792bc0439ebf0eaa871d5c"> 1287</a></span><span class="preprocessor">#define ADC_CR1_SCAN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l01288" name="l01288"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ae87fc99e54856233fe19c05947821d"> 1288</a></span><span class="preprocessor">#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) </span></div>
|
||
<div class="line"><a id="l01289" name="l01289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaeab75ece0c73dd97e8f21911ed22d06"> 1289</a></span><span class="preprocessor">#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk </span></div>
|
||
<div class="line"><a id="l01290" name="l01290"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cc219fd4025d88bd77dfb2824e4a42b"> 1290</a></span><span class="preprocessor">#define ADC_CR1_AWDSGL_Pos (9U) </span></div>
|
||
<div class="line"><a id="l01291" name="l01291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a58382bba04769e4baef8f36390f648"> 1291</a></span><span class="preprocessor">#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) </span></div>
|
||
<div class="line"><a id="l01292" name="l01292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c9fc31f19c04033dfa98e982519c451"> 1292</a></span><span class="preprocessor">#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk </span></div>
|
||
<div class="line"><a id="l01293" name="l01293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac65ab808d9f67501a3e032f6e093baa7"> 1293</a></span><span class="preprocessor">#define ADC_CR1_JAUTO_Pos (10U) </span></div>
|
||
<div class="line"><a id="l01294" name="l01294"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cfa0d38cd6dfd5ed09673558ccadacf"> 1294</a></span><span class="preprocessor">#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) </span></div>
|
||
<div class="line"><a id="l01295" name="l01295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6353cb0d564410358b3a086dd0241f8c"> 1295</a></span><span class="preprocessor">#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk </span></div>
|
||
<div class="line"><a id="l01296" name="l01296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga394271f323587db3ea21731046b69004"> 1296</a></span><span class="preprocessor">#define ADC_CR1_DISCEN_Pos (11U) </span></div>
|
||
<div class="line"><a id="l01297" name="l01297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad69e1c5ba0421fe9b33109a3789be1a5"> 1297</a></span><span class="preprocessor">#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) </span></div>
|
||
<div class="line"><a id="l01298" name="l01298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd690297fc73fca40d797f4c90800b9a"> 1298</a></span><span class="preprocessor">#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk </span></div>
|
||
<div class="line"><a id="l01299" name="l01299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2e2019ed8fe62389fe06843f9bbc265"> 1299</a></span><span class="preprocessor">#define ADC_CR1_JDISCEN_Pos (12U) </span></div>
|
||
<div class="line"><a id="l01300" name="l01300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae5059f8684f70119fff571d8c79bbaf"> 1300</a></span><span class="preprocessor">#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) </span></div>
|
||
<div class="line"><a id="l01301" name="l01301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd06a2840346bf45ff335707db0b6e30"> 1301</a></span><span class="preprocessor">#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk </span></div>
|
||
<div class="line"><a id="l01302" name="l01302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga418d84715b6f383cea1ca241d0c76194"> 1302</a></span><span class="preprocessor">#define ADC_CR1_DISCNUM_Pos (13U) </span></div>
|
||
<div class="line"><a id="l01303" name="l01303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafee42b4ef0f4cb5b0ab45fc78f3e27f9"> 1303</a></span><span class="preprocessor">#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) </span></div>
|
||
<div class="line"><a id="l01304" name="l01304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeaa416a291023449ae82e7ef39844075"> 1304</a></span><span class="preprocessor">#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk </span></div>
|
||
<div class="line"><a id="l01305" name="l01305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59ff81db7def261f0e84d5dbb6cca1ce"> 1305</a></span><span class="preprocessor">#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) </span></div>
|
||
<div class="line"><a id="l01306" name="l01306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39940d3611126052f4f748934c629ebf"> 1306</a></span><span class="preprocessor">#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) </span></div>
|
||
<div class="line"><a id="l01307" name="l01307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab73d5fdf276f5ef3965afdda78ac9e1e"> 1307</a></span><span class="preprocessor">#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) </span></div>
|
||
<div class="line"><a id="l01308" name="l01308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78cb5899a747da3e5013ad44934b5c7d"> 1308</a></span><span class="preprocessor">#define ADC_CR1_JAWDEN_Pos (22U) </span></div>
|
||
<div class="line"><a id="l01309" name="l01309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29a30d56ef1ba75b52db631e367b13bb"> 1309</a></span><span class="preprocessor">#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) </span></div>
|
||
<div class="line"><a id="l01310" name="l01310"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4886de74bcd3a1e545094089f76fd0b3"> 1310</a></span><span class="preprocessor">#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk </span></div>
|
||
<div class="line"><a id="l01311" name="l01311"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4078327f9219b87d0627ad53f27e25a"> 1311</a></span><span class="preprocessor">#define ADC_CR1_AWDEN_Pos (23U) </span></div>
|
||
<div class="line"><a id="l01312" name="l01312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga815cfd0e3ad3eed4424caf312550da16"> 1312</a></span><span class="preprocessor">#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) </span></div>
|
||
<div class="line"><a id="l01313" name="l01313"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e006d43fcb9fe1306745c95a1bdd651"> 1313</a></span><span class="preprocessor">#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk </span></div>
|
||
<div class="line"><a id="l01314" name="l01314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacae7156287b4fc60bc71114529b7b868"> 1314</a></span><span class="preprocessor">#define ADC_CR1_RES_Pos (24U) </span></div>
|
||
<div class="line"><a id="l01315" name="l01315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5645a309568931b9f783dbca969ff487"> 1315</a></span><span class="preprocessor">#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) </span></div>
|
||
<div class="line"><a id="l01316" name="l01316"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71e4a4c233895a2e7b6dd3ca6ca849e5"> 1316</a></span><span class="preprocessor">#define ADC_CR1_RES ADC_CR1_RES_Msk </span></div>
|
||
<div class="line"><a id="l01317" name="l01317"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfc432ddbd2140a92d877f6d9dc52417"> 1317</a></span><span class="preprocessor">#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) </span></div>
|
||
<div class="line"><a id="l01318" name="l01318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga674904864f540043692a5b5ead9fae10"> 1318</a></span><span class="preprocessor">#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) </span></div>
|
||
<div class="line"><a id="l01319" name="l01319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c72d6e0c41f98ea9b378d8455de2f13"> 1319</a></span><span class="preprocessor">#define ADC_CR1_OVRIE_Pos (26U) </span></div>
|
||
<div class="line"><a id="l01320" name="l01320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada4ec8e732a43f37a4568049593aa146"> 1320</a></span><span class="preprocessor">#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) </span></div>
|
||
<div class="line"><a id="l01321" name="l01321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa892fda7c204bf18a33a059f28be0fba"> 1321</a></span><span class="preprocessor">#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk </span></div>
|
||
<div class="line"><a id="l01323" name="l01323"></a><span class="lineno"> 1323</span><span class="comment">/******************* Bit definition for ADC_CR2 register ********************/</span></div>
|
||
<div class="line"><a id="l01324" name="l01324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga234ecbd845e8f7b48fab4b3f1e12e788"> 1324</a></span><span class="preprocessor">#define ADC_CR2_ADON_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01325" name="l01325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga523c9c51b9eefe42cc33dec9dbcd7091"> 1325</a></span><span class="preprocessor">#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) </span></div>
|
||
<div class="line"><a id="l01326" name="l01326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89b646f092b052d8488d2016f6290f0e"> 1326</a></span><span class="preprocessor">#define ADC_CR2_ADON ADC_CR2_ADON_Msk </span></div>
|
||
<div class="line"><a id="l01327" name="l01327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4401869d89774c7f187aa72c3f9fae2"> 1327</a></span><span class="preprocessor">#define ADC_CR2_CONT_Pos (1U) </span></div>
|
||
<div class="line"><a id="l01328" name="l01328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69a1c4bf40a36bd05804f1083f745914"> 1328</a></span><span class="preprocessor">#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) </span></div>
|
||
<div class="line"><a id="l01329" name="l01329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49bb71a868c9d88a0f7bbe48918b2140"> 1329</a></span><span class="preprocessor">#define ADC_CR2_CONT ADC_CR2_CONT_Msk </span></div>
|
||
<div class="line"><a id="l01330" name="l01330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8edaebc5ec9c7cf465e7810189052ffd"> 1330</a></span><span class="preprocessor">#define ADC_CR2_DMA_Pos (8U) </span></div>
|
||
<div class="line"><a id="l01331" name="l01331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9bfa1dd15f4531ef79131a4a2810342"> 1331</a></span><span class="preprocessor">#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) </span></div>
|
||
<div class="line"><a id="l01332" name="l01332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga017309ac4b532bc8c607388f4e2cbbec"> 1332</a></span><span class="preprocessor">#define ADC_CR2_DMA ADC_CR2_DMA_Msk </span></div>
|
||
<div class="line"><a id="l01333" name="l01333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25e88283dda37ac8153f8f2d5aa8fd4b"> 1333</a></span><span class="preprocessor">#define ADC_CR2_DDS_Pos (9U) </span></div>
|
||
<div class="line"><a id="l01334" name="l01334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96fbc51781aa1e2cb18d72ac67e748fe"> 1334</a></span><span class="preprocessor">#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) </span></div>
|
||
<div class="line"><a id="l01335" name="l01335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d7d75f0c4c8fa190fbf9f86fbe6dfc8"> 1335</a></span><span class="preprocessor">#define ADC_CR2_DDS ADC_CR2_DDS_Msk </span></div>
|
||
<div class="line"><a id="l01336" name="l01336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga375e2be253b645381365c90ae8c4cb1f"> 1336</a></span><span class="preprocessor">#define ADC_CR2_EOCS_Pos (10U) </span></div>
|
||
<div class="line"><a id="l01337" name="l01337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacee54d4669ca3fd1c2e760cbe1a0dcbd"> 1337</a></span><span class="preprocessor">#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) </span></div>
|
||
<div class="line"><a id="l01338" name="l01338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9dac2004ab20295e04012060ab24aeb"> 1338</a></span><span class="preprocessor">#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk </span></div>
|
||
<div class="line"><a id="l01339" name="l01339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6422927e869ce87e289e796dcf0067c2"> 1339</a></span><span class="preprocessor">#define ADC_CR2_ALIGN_Pos (11U) </span></div>
|
||
<div class="line"><a id="l01340" name="l01340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada0bca3543546c0f5c893a4a99a4ddcc"> 1340</a></span><span class="preprocessor">#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) </span></div>
|
||
<div class="line"><a id="l01341" name="l01341"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5950b5a7438a447584f6dd86c343362"> 1341</a></span><span class="preprocessor">#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk </span></div>
|
||
<div class="line"><a id="l01342" name="l01342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d64811b8292d3145622b767f859e3b0"> 1342</a></span><span class="preprocessor">#define ADC_CR2_JEXTSEL_Pos (16U) </span></div>
|
||
<div class="line"><a id="l01343" name="l01343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57147ca3b182775bc6708bd7edad0a8d"> 1343</a></span><span class="preprocessor">#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) </span></div>
|
||
<div class="line"><a id="l01344" name="l01344"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab3aa5d0e2a4b77960ec8f3b425a3eac"> 1344</a></span><span class="preprocessor">#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk </span></div>
|
||
<div class="line"><a id="l01345" name="l01345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa70c1f30e2101e2177ce564440203ba3"> 1345</a></span><span class="preprocessor">#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) </span></div>
|
||
<div class="line"><a id="l01346" name="l01346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99fa4a240d34ce231d6d0543bac7fd9b"> 1346</a></span><span class="preprocessor">#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) </span></div>
|
||
<div class="line"><a id="l01347" name="l01347"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga571bb97f950181fedbc0d4756482713d"> 1347</a></span><span class="preprocessor">#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) </span></div>
|
||
<div class="line"><a id="l01348" name="l01348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae34f5dda7a153ffd927c9cd38999f822"> 1348</a></span><span class="preprocessor">#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) </span></div>
|
||
<div class="line"><a id="l01349" name="l01349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf91b9e9943eb12821746a1fe4a68988"> 1349</a></span><span class="preprocessor">#define ADC_CR2_JEXTEN_Pos (20U) </span></div>
|
||
<div class="line"><a id="l01350" name="l01350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac444a034ccfbea8f0a0a1b3a40abb600"> 1350</a></span><span class="preprocessor">#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) </span></div>
|
||
<div class="line"><a id="l01351" name="l01351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07330f702208792faca3a563dc4fd9c6"> 1351</a></span><span class="preprocessor">#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk </span></div>
|
||
<div class="line"><a id="l01352" name="l01352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b3c99510de210ff3137ff8de328889b"> 1352</a></span><span class="preprocessor">#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) </span></div>
|
||
<div class="line"><a id="l01353" name="l01353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga949c70fdf36a32a6afcbf44fec123832"> 1353</a></span><span class="preprocessor">#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) </span></div>
|
||
<div class="line"><a id="l01354" name="l01354"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c5de0a53e5697dcb16759a12c47c7a4"> 1354</a></span><span class="preprocessor">#define ADC_CR2_JSWSTART_Pos (22U) </span></div>
|
||
<div class="line"><a id="l01355" name="l01355"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1555cd00a88accf874a2bda2c0ac8d4"> 1355</a></span><span class="preprocessor">#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) </span></div>
|
||
<div class="line"><a id="l01356" name="l01356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac12fe8a6cc24eef2ed2e1f1525855678"> 1356</a></span><span class="preprocessor">#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk </span></div>
|
||
<div class="line"><a id="l01357" name="l01357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98246071e8135d0b92366024e474511c"> 1357</a></span><span class="preprocessor">#define ADC_CR2_EXTSEL_Pos (24U) </span></div>
|
||
<div class="line"><a id="l01358" name="l01358"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef4979d74537d34ce18573d072e33408"> 1358</a></span><span class="preprocessor">#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) </span></div>
|
||
<div class="line"><a id="l01359" name="l01359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d1054d6cd017e305cf6e8a864ce96c8"> 1359</a></span><span class="preprocessor">#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk </span></div>
|
||
<div class="line"><a id="l01360" name="l01360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9410c7fd93f6d0b157ede745ee269d7b"> 1360</a></span><span class="preprocessor">#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) </span></div>
|
||
<div class="line"><a id="l01361" name="l01361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a6725419743a8d01b4a223609952893"> 1361</a></span><span class="preprocessor">#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) </span></div>
|
||
<div class="line"><a id="l01362" name="l01362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c2322988b5fff19d012d9179d412ad0"> 1362</a></span><span class="preprocessor">#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) </span></div>
|
||
<div class="line"><a id="l01363" name="l01363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga387de6160834197888efa43e164c2db9"> 1363</a></span><span class="preprocessor">#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) </span></div>
|
||
<div class="line"><a id="l01364" name="l01364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga902a845718958f3db26c7d56e9c3a286"> 1364</a></span><span class="preprocessor">#define ADC_CR2_EXTEN_Pos (28U) </span></div>
|
||
<div class="line"><a id="l01365" name="l01365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac97138f7c2e3ecbb31756679589c9b62"> 1365</a></span><span class="preprocessor">#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) </span></div>
|
||
<div class="line"><a id="l01366" name="l01366"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga574b4d8e90655d0432882d620e629234"> 1366</a></span><span class="preprocessor">#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk </span></div>
|
||
<div class="line"><a id="l01367" name="l01367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3519da0cc6fbd31444a16244c70232e6"> 1367</a></span><span class="preprocessor">#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) </span></div>
|
||
<div class="line"><a id="l01368" name="l01368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17e37edddbb6ad791bffb350cca23d4d"> 1368</a></span><span class="preprocessor">#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) </span></div>
|
||
<div class="line"><a id="l01369" name="l01369"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf78afe48fe6fdadf00d3c37cfed860a7"> 1369</a></span><span class="preprocessor">#define ADC_CR2_SWSTART_Pos (30U) </span></div>
|
||
<div class="line"><a id="l01370" name="l01370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5c16a177295208be4bed45f350c315e"> 1370</a></span><span class="preprocessor">#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) </span></div>
|
||
<div class="line"><a id="l01371" name="l01371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5eae65bad1a6c975e1911eb5ba117468"> 1371</a></span><span class="preprocessor">#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk </span></div>
|
||
<div class="line"><a id="l01373" name="l01373"></a><span class="lineno"> 1373</span><span class="comment">/****************** Bit definition for ADC_SMPR1 register *******************/</span></div>
|
||
<div class="line"><a id="l01374" name="l01374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2d3f858e16869682edb4fd672167f9e"> 1374</a></span><span class="preprocessor">#define ADC_SMPR1_SMP10_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01375" name="l01375"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa436e3f99d6260a7c0d93c2c7b9e06e0"> 1375</a></span><span class="preprocessor">#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) </span></div>
|
||
<div class="line"><a id="l01376" name="l01376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32242a2c2156a012a7343bcb43d490d0"> 1376</a></span><span class="preprocessor">#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk </span></div>
|
||
<div class="line"><a id="l01377" name="l01377"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a8996c53042759f01e966fb00351ebf"> 1377</a></span><span class="preprocessor">#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) </span></div>
|
||
<div class="line"><a id="l01378" name="l01378"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42b96f058436c8bdcfabe1e08c7edd61"> 1378</a></span><span class="preprocessor">#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) </span></div>
|
||
<div class="line"><a id="l01379" name="l01379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga289d89b4d92d7f685a8e44aeb9ddcded"> 1379</a></span><span class="preprocessor">#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) </span></div>
|
||
<div class="line"><a id="l01380" name="l01380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b0f3653aea6b1db3875f59d5c3bdc74"> 1380</a></span><span class="preprocessor">#define ADC_SMPR1_SMP11_Pos (3U) </span></div>
|
||
<div class="line"><a id="l01381" name="l01381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bed6ca83db1864feb7eb926d8228c85"> 1381</a></span><span class="preprocessor">#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) </span></div>
|
||
<div class="line"><a id="l01382" name="l01382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c74d559f2a70a2e8c807b7bcaccd800"> 1382</a></span><span class="preprocessor">#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk </span></div>
|
||
<div class="line"><a id="l01383" name="l01383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60780d613953f48a2dfc8debce72fb28"> 1383</a></span><span class="preprocessor">#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) </span></div>
|
||
<div class="line"><a id="l01384" name="l01384"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa61e1dbafcae3e1c8eae4320a6e5ec5d"> 1384</a></span><span class="preprocessor">#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) </span></div>
|
||
<div class="line"><a id="l01385" name="l01385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93a876a9a6d90cd30456433b7e38c3f2"> 1385</a></span><span class="preprocessor">#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) </span></div>
|
||
<div class="line"><a id="l01386" name="l01386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb6169f9cd1e9c488526140dcbf464c2"> 1386</a></span><span class="preprocessor">#define ADC_SMPR1_SMP12_Pos (6U) </span></div>
|
||
<div class="line"><a id="l01387" name="l01387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae18d279a21d7ce940d6969500a25a13b"> 1387</a></span><span class="preprocessor">#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) </span></div>
|
||
<div class="line"><a id="l01388" name="l01388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga433b5a7d944666fb7abed3b107c352fc"> 1388</a></span><span class="preprocessor">#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk </span></div>
|
||
<div class="line"><a id="l01389" name="l01389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaaac6ae97c00276d7472bc92a9edd6e2"> 1389</a></span><span class="preprocessor">#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) </span></div>
|
||
<div class="line"><a id="l01390" name="l01390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6020f9d742e15650ad919aaccaf2ff6c"> 1390</a></span><span class="preprocessor">#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) </span></div>
|
||
<div class="line"><a id="l01391" name="l01391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb59adb544d416e91ea0c12d4f39ccc9"> 1391</a></span><span class="preprocessor">#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) </span></div>
|
||
<div class="line"><a id="l01392" name="l01392"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9093533a0a301bae03822d9f8bfc7597"> 1392</a></span><span class="preprocessor">#define ADC_SMPR1_SMP13_Pos (9U) </span></div>
|
||
<div class="line"><a id="l01393" name="l01393"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0b2a1ff66bccc991c783ceca1d69cfd"> 1393</a></span><span class="preprocessor">#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) </span></div>
|
||
<div class="line"><a id="l01394" name="l01394"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2df120cd93a177ea17946a656259129e"> 1394</a></span><span class="preprocessor">#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk </span></div>
|
||
<div class="line"><a id="l01395" name="l01395"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49e7444d6cf630eccfd52fb4155bd553"> 1395</a></span><span class="preprocessor">#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) </span></div>
|
||
<div class="line"><a id="l01396" name="l01396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5d5ad9d8d08feaee18d1f2d8d6787a1"> 1396</a></span><span class="preprocessor">#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) </span></div>
|
||
<div class="line"><a id="l01397" name="l01397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4cd285d46485136deb6223377d0b17c"> 1397</a></span><span class="preprocessor">#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) </span></div>
|
||
<div class="line"><a id="l01398" name="l01398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2da550ca91822740c151e660e6725475"> 1398</a></span><span class="preprocessor">#define ADC_SMPR1_SMP14_Pos (12U) </span></div>
|
||
<div class="line"><a id="l01399" name="l01399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga410946d711bfd8069e7eb95d6d83e832"> 1399</a></span><span class="preprocessor">#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) </span></div>
|
||
<div class="line"><a id="l01400" name="l01400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1574fc02a40f22fc751073e02ebb781"> 1400</a></span><span class="preprocessor">#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk </span></div>
|
||
<div class="line"><a id="l01401" name="l01401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9243898272b1d27018c971eecfa57f78"> 1401</a></span><span class="preprocessor">#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) </span></div>
|
||
<div class="line"><a id="l01402" name="l01402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1016b8ca359247491a2a0a5d77aa1c22"> 1402</a></span><span class="preprocessor">#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) </span></div>
|
||
<div class="line"><a id="l01403" name="l01403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e658a8b72bac244bf919a874690e49e"> 1403</a></span><span class="preprocessor">#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) </span></div>
|
||
<div class="line"><a id="l01404" name="l01404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4a9dac15edbf7dbc2fa521e57cd0929"> 1404</a></span><span class="preprocessor">#define ADC_SMPR1_SMP15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l01405" name="l01405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bd307278f68d42fad28c9a549cee495"> 1405</a></span><span class="preprocessor">#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) </span></div>
|
||
<div class="line"><a id="l01406" name="l01406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ae0043ad863f7710834217bc82c8ecf"> 1406</a></span><span class="preprocessor">#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk </span></div>
|
||
<div class="line"><a id="l01407" name="l01407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5f8e555f5ece2ee632dd9d6c60d9584"> 1407</a></span><span class="preprocessor">#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) </span></div>
|
||
<div class="line"><a id="l01408" name="l01408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab978e10b7dcfe6c1b88dd4fef50498ac"> 1408</a></span><span class="preprocessor">#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) </span></div>
|
||
<div class="line"><a id="l01409" name="l01409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga045285e1c5ab9ae570e37fe627b0e117"> 1409</a></span><span class="preprocessor">#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) </span></div>
|
||
<div class="line"><a id="l01410" name="l01410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad299a50233bbf403f796758fbce28a27"> 1410</a></span><span class="preprocessor">#define ADC_SMPR1_SMP16_Pos (18U) </span></div>
|
||
<div class="line"><a id="l01411" name="l01411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbf22b25f0b78dab59b1f8d2e1bbceeb"> 1411</a></span><span class="preprocessor">#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) </span></div>
|
||
<div class="line"><a id="l01412" name="l01412"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2925d05347e46e9c6a970214fa76bbec"> 1412</a></span><span class="preprocessor">#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk </span></div>
|
||
<div class="line"><a id="l01413" name="l01413"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1a7d0ef695bd2017bcda3949f0134be"> 1413</a></span><span class="preprocessor">#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) </span></div>
|
||
<div class="line"><a id="l01414" name="l01414"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga793ff2f46f51e1d485a9bd728687bf15"> 1414</a></span><span class="preprocessor">#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) </span></div>
|
||
<div class="line"><a id="l01415" name="l01415"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade321fdbf74f830e54951ccfca285686"> 1415</a></span><span class="preprocessor">#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) </span></div>
|
||
<div class="line"><a id="l01416" name="l01416"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f0af7a5db877331daa8770222909d4d"> 1416</a></span><span class="preprocessor">#define ADC_SMPR1_SMP17_Pos (21U) </span></div>
|
||
<div class="line"><a id="l01417" name="l01417"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9ca754667b1437b01fb0da560d36e10"> 1417</a></span><span class="preprocessor">#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) </span></div>
|
||
<div class="line"><a id="l01418" name="l01418"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9867370ecef7b99c32b8ecb44ad9e581"> 1418</a></span><span class="preprocessor">#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk </span></div>
|
||
<div class="line"><a id="l01419" name="l01419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42b004d74f288cb191bfc6a327f94480"> 1419</a></span><span class="preprocessor">#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) </span></div>
|
||
<div class="line"><a id="l01420" name="l01420"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ac4c21586d6a353c208a5175906ecc1"> 1420</a></span><span class="preprocessor">#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) </span></div>
|
||
<div class="line"><a id="l01421" name="l01421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac81ceec799a7da2def4f33339bd5e273"> 1421</a></span><span class="preprocessor">#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) </span></div>
|
||
<div class="line"><a id="l01422" name="l01422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d49003824f10f93348569e720865899"> 1422</a></span><span class="preprocessor">#define ADC_SMPR1_SMP18_Pos (24U) </span></div>
|
||
<div class="line"><a id="l01423" name="l01423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c670627d1f5c73fae79914ba1f04475"> 1423</a></span><span class="preprocessor">#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos) </span></div>
|
||
<div class="line"><a id="l01424" name="l01424"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3c7d84a92899d950de236fe9d14df2c"> 1424</a></span><span class="preprocessor">#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk </span></div>
|
||
<div class="line"><a id="l01425" name="l01425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6862168bb7688638764defc72120716b"> 1425</a></span><span class="preprocessor">#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos) </span></div>
|
||
<div class="line"><a id="l01426" name="l01426"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72a01c59a0a785b18235641b36735090"> 1426</a></span><span class="preprocessor">#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos) </span></div>
|
||
<div class="line"><a id="l01427" name="l01427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec1addc9c417b4b7693768817b058059"> 1427</a></span><span class="preprocessor">#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos) </span></div>
|
||
<div class="line"><a id="l01429" name="l01429"></a><span class="lineno"> 1429</span><span class="comment">/****************** Bit definition for ADC_SMPR2 register *******************/</span></div>
|
||
<div class="line"><a id="l01430" name="l01430"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8509ff53fa9599b3e2756b0029701a12"> 1430</a></span><span class="preprocessor">#define ADC_SMPR2_SMP0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01431" name="l01431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa46fc7c440c9969355b4fd542b9a6447"> 1431</a></span><span class="preprocessor">#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) </span></div>
|
||
<div class="line"><a id="l01432" name="l01432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a13b3c652e5759e2d8bc7e38889bc5e"> 1432</a></span><span class="preprocessor">#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk </span></div>
|
||
<div class="line"><a id="l01433" name="l01433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bde59fce56980a59a3dfdb0da7ebe0c"> 1433</a></span><span class="preprocessor">#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) </span></div>
|
||
<div class="line"><a id="l01434" name="l01434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d5b6e025d8e70767914c144793b93e6"> 1434</a></span><span class="preprocessor">#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) </span></div>
|
||
<div class="line"><a id="l01435" name="l01435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga361de56c56c45834fc837df349f155dc"> 1435</a></span><span class="preprocessor">#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) </span></div>
|
||
<div class="line"><a id="l01436" name="l01436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a7d6076724526beda6cb481eb3ea5e7"> 1436</a></span><span class="preprocessor">#define ADC_SMPR2_SMP1_Pos (3U) </span></div>
|
||
<div class="line"><a id="l01437" name="l01437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39b8904a2aa672a622471712507c39c7"> 1437</a></span><span class="preprocessor">#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) </span></div>
|
||
<div class="line"><a id="l01438" name="l01438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b85dd0b1708cdf1bf403b07ad51da36"> 1438</a></span><span class="preprocessor">#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk </span></div>
|
||
<div class="line"><a id="l01439" name="l01439"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa99de1a2d2bbe8921353114d03cb7f6"> 1439</a></span><span class="preprocessor">#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) </span></div>
|
||
<div class="line"><a id="l01440" name="l01440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6ceb41e5e3cb6ae7da28070bc0b07d2"> 1440</a></span><span class="preprocessor">#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) </span></div>
|
||
<div class="line"><a id="l01441" name="l01441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b9efc8f9488d389301c4a6f9ef4427a"> 1441</a></span><span class="preprocessor">#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) </span></div>
|
||
<div class="line"><a id="l01442" name="l01442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f3716b7531126383d5f4f26c55b17a0"> 1442</a></span><span class="preprocessor">#define ADC_SMPR2_SMP2_Pos (6U) </span></div>
|
||
<div class="line"><a id="l01443" name="l01443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf47f3ef6dad5ad4ab6a70f7256cce7bf"> 1443</a></span><span class="preprocessor">#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) </span></div>
|
||
<div class="line"><a id="l01444" name="l01444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea6e1e298372596bcdcdf93e763b3683"> 1444</a></span><span class="preprocessor">#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk </span></div>
|
||
<div class="line"><a id="l01445" name="l01445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97e2ac0d4d8afb3aa0b4c09c8fa1d018"> 1445</a></span><span class="preprocessor">#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) </span></div>
|
||
<div class="line"><a id="l01446" name="l01446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83fe79e3e10b689a209dc5a724f89199"> 1446</a></span><span class="preprocessor">#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) </span></div>
|
||
<div class="line"><a id="l01447" name="l01447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad580d376e0a0bcb34183a6d6735b3122"> 1447</a></span><span class="preprocessor">#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) </span></div>
|
||
<div class="line"><a id="l01448" name="l01448"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46bbf950a5d9f629a48b7f9faebbcc55"> 1448</a></span><span class="preprocessor">#define ADC_SMPR2_SMP3_Pos (9U) </span></div>
|
||
<div class="line"><a id="l01449" name="l01449"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga305cad42f0aae469c0f63a79de6bbf2a"> 1449</a></span><span class="preprocessor">#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) </span></div>
|
||
<div class="line"><a id="l01450" name="l01450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga081c3d61e5311a11cb046d56630e1fd0"> 1450</a></span><span class="preprocessor">#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk </span></div>
|
||
<div class="line"><a id="l01451" name="l01451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1679a42f67ca4b9b9496dd6000fec01"> 1451</a></span><span class="preprocessor">#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) </span></div>
|
||
<div class="line"><a id="l01452" name="l01452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bf92b0a67dcec9b3c325d58e7e517b0"> 1452</a></span><span class="preprocessor">#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) </span></div>
|
||
<div class="line"><a id="l01453" name="l01453"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40682268fa8534bd369eb64a329bdf46"> 1453</a></span><span class="preprocessor">#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) </span></div>
|
||
<div class="line"><a id="l01454" name="l01454"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8fe44c9dc72211b7255b4355462f680"> 1454</a></span><span class="preprocessor">#define ADC_SMPR2_SMP4_Pos (12U) </span></div>
|
||
<div class="line"><a id="l01455" name="l01455"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41d006fba68f1e84ff3bd0ec21f61233"> 1455</a></span><span class="preprocessor">#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) </span></div>
|
||
<div class="line"><a id="l01456" name="l01456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeab838fcf0aace87b2163b96d208bb64"> 1456</a></span><span class="preprocessor">#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk </span></div>
|
||
<div class="line"><a id="l01457" name="l01457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4123bce64dc4f1831f992b09d6db4f2"> 1457</a></span><span class="preprocessor">#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) </span></div>
|
||
<div class="line"><a id="l01458" name="l01458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3edf57b459804d17d5a588dd446c763"> 1458</a></span><span class="preprocessor">#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) </span></div>
|
||
<div class="line"><a id="l01459" name="l01459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2a2fd74311c4ffcaed4a8d1a3be2245"> 1459</a></span><span class="preprocessor">#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) </span></div>
|
||
<div class="line"><a id="l01460" name="l01460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdd88f74dea228c26eeb5bcbd9513012"> 1460</a></span><span class="preprocessor">#define ADC_SMPR2_SMP5_Pos (15U) </span></div>
|
||
<div class="line"><a id="l01461" name="l01461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b8b4a18f347d72459aa84fd6a2629a8"> 1461</a></span><span class="preprocessor">#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) </span></div>
|
||
<div class="line"><a id="l01462" name="l01462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9500281fa740994b9cfa6a7df8227849"> 1462</a></span><span class="preprocessor">#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk </span></div>
|
||
<div class="line"><a id="l01463" name="l01463"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22dd2b1695a4e7a4b1d4ec2b8e244ffc"> 1463</a></span><span class="preprocessor">#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) </span></div>
|
||
<div class="line"><a id="l01464" name="l01464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4de4f6c62646be62d0710dc46eb5e88"> 1464</a></span><span class="preprocessor">#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) </span></div>
|
||
<div class="line"><a id="l01465" name="l01465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c19081d82f2c6478c6aefc207778e1e"> 1465</a></span><span class="preprocessor">#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) </span></div>
|
||
<div class="line"><a id="l01466" name="l01466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7ad6181795d9407c499d6c5d87c7056"> 1466</a></span><span class="preprocessor">#define ADC_SMPR2_SMP6_Pos (18U) </span></div>
|
||
<div class="line"><a id="l01467" name="l01467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63b337299939afb7336f2579bd3a727c"> 1467</a></span><span class="preprocessor">#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) </span></div>
|
||
<div class="line"><a id="l01468" name="l01468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64cd99c27d07298913541dbdc31aa8ae"> 1468</a></span><span class="preprocessor">#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk </span></div>
|
||
<div class="line"><a id="l01469" name="l01469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbebc0a7f368e5846408d768603d9b44"> 1469</a></span><span class="preprocessor">#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) </span></div>
|
||
<div class="line"><a id="l01470" name="l01470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27f59166864f7cd0a5e8e6b4450e72d3"> 1470</a></span><span class="preprocessor">#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) </span></div>
|
||
<div class="line"><a id="l01471" name="l01471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4139fac7e8ba3e604e35ba906880f909"> 1471</a></span><span class="preprocessor">#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) </span></div>
|
||
<div class="line"><a id="l01472" name="l01472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb68d22ee2b8a9a6238d08b3c5f0417c"> 1472</a></span><span class="preprocessor">#define ADC_SMPR2_SMP7_Pos (21U) </span></div>
|
||
<div class="line"><a id="l01473" name="l01473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f8b7b73b7ac647dd48d114f683afc55"> 1473</a></span><span class="preprocessor">#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) </span></div>
|
||
<div class="line"><a id="l01474" name="l01474"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ec6ee971fc8b2d1890858df94a5c500"> 1474</a></span><span class="preprocessor">#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk </span></div>
|
||
<div class="line"><a id="l01475" name="l01475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f30003c59ab6c232d73aa446c77651a"> 1475</a></span><span class="preprocessor">#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) </span></div>
|
||
<div class="line"><a id="l01476" name="l01476"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c8708fc97082257b43fa4534c721068"> 1476</a></span><span class="preprocessor">#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) </span></div>
|
||
<div class="line"><a id="l01477" name="l01477"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e42897bdc25951a73bac060a7a065ca"> 1477</a></span><span class="preprocessor">#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) </span></div>
|
||
<div class="line"><a id="l01478" name="l01478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab45620208290dbe572341227dd291c5d"> 1478</a></span><span class="preprocessor">#define ADC_SMPR2_SMP8_Pos (24U) </span></div>
|
||
<div class="line"><a id="l01479" name="l01479"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0390786a9cb491305c18fe615acfd13f"> 1479</a></span><span class="preprocessor">#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) </span></div>
|
||
<div class="line"><a id="l01480" name="l01480"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0695c289e658b772070a7f29797e9cc3"> 1480</a></span><span class="preprocessor">#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk </span></div>
|
||
<div class="line"><a id="l01481" name="l01481"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5f1d2290107eda2dfee33810779b0f6"> 1481</a></span><span class="preprocessor">#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) </span></div>
|
||
<div class="line"><a id="l01482" name="l01482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb9ce9d71f989bad0ed686caf4dd5250"> 1482</a></span><span class="preprocessor">#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) </span></div>
|
||
<div class="line"><a id="l01483" name="l01483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3756c6141f55c60da0bcd4d599e7d60d"> 1483</a></span><span class="preprocessor">#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) </span></div>
|
||
<div class="line"><a id="l01484" name="l01484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39bc8143f781965172d5e6e023529abc"> 1484</a></span><span class="preprocessor">#define ADC_SMPR2_SMP9_Pos (27U) </span></div>
|
||
<div class="line"><a id="l01485" name="l01485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b124d3d088448db3cd97db242b125cf"> 1485</a></span><span class="preprocessor">#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) </span></div>
|
||
<div class="line"><a id="l01486" name="l01486"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5348f83daaa38060702d7b9cfe2e4005"> 1486</a></span><span class="preprocessor">#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk </span></div>
|
||
<div class="line"><a id="l01487" name="l01487"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga892f18c89fbaafc74b7d67db74b41423"> 1487</a></span><span class="preprocessor">#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) </span></div>
|
||
<div class="line"><a id="l01488" name="l01488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a6949e61c5845a7ff2331b64cb579bc"> 1488</a></span><span class="preprocessor">#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) </span></div>
|
||
<div class="line"><a id="l01489" name="l01489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga070135017850599b1e19766c6aa31cd1"> 1489</a></span><span class="preprocessor">#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) </span></div>
|
||
<div class="line"><a id="l01491" name="l01491"></a><span class="lineno"> 1491</span><span class="comment">/****************** Bit definition for ADC_JOFR1 register *******************/</span></div>
|
||
<div class="line"><a id="l01492" name="l01492"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga593196324c441869e2b7629db926aafd"> 1492</a></span><span class="preprocessor">#define ADC_JOFR1_JOFFSET1_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01493" name="l01493"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4aeb01e5e14a55e3de62770ff3b3d0fd"> 1493</a></span><span class="preprocessor">#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) </span></div>
|
||
<div class="line"><a id="l01494" name="l01494"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad76f97130b391455094605a6c803026c"> 1494</a></span><span class="preprocessor">#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk </span></div>
|
||
<div class="line"><a id="l01496" name="l01496"></a><span class="lineno"> 1496</span><span class="comment">/****************** Bit definition for ADC_JOFR2 register *******************/</span></div>
|
||
<div class="line"><a id="l01497" name="l01497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15e0dc116f3623901fdda1e743838334"> 1497</a></span><span class="preprocessor">#define ADC_JOFR2_JOFFSET2_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01498" name="l01498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21ef3d2ed0de640e567ecefb4c902df4"> 1498</a></span><span class="preprocessor">#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) </span></div>
|
||
<div class="line"><a id="l01499" name="l01499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b15a9e9ce10303e233059c1de6d956c"> 1499</a></span><span class="preprocessor">#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk </span></div>
|
||
<div class="line"><a id="l01501" name="l01501"></a><span class="lineno"> 1501</span><span class="comment">/****************** Bit definition for ADC_JOFR3 register *******************/</span></div>
|
||
<div class="line"><a id="l01502" name="l01502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad339e95766c1c4dd3ec3ef2fa5856f8b"> 1502</a></span><span class="preprocessor">#define ADC_JOFR3_JOFFSET3_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01503" name="l01503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e742777e82d2e3a58f789f7785fa530"> 1503</a></span><span class="preprocessor">#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) </span></div>
|
||
<div class="line"><a id="l01504" name="l01504"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga743e4c3a7cefc1a193146e77791c3985"> 1504</a></span><span class="preprocessor">#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk </span></div>
|
||
<div class="line"><a id="l01506" name="l01506"></a><span class="lineno"> 1506</span><span class="comment">/****************** Bit definition for ADC_JOFR4 register *******************/</span></div>
|
||
<div class="line"><a id="l01507" name="l01507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb1f1ccebbb9c41f3b6bae1f8c587618"> 1507</a></span><span class="preprocessor">#define ADC_JOFR4_JOFFSET4_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01508" name="l01508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga983eba37929e630bc6bec3c1ab411db5"> 1508</a></span><span class="preprocessor">#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) </span></div>
|
||
<div class="line"><a id="l01509" name="l01509"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada0937f2f6a64bd6b7531ad553471b8d"> 1509</a></span><span class="preprocessor">#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk </span></div>
|
||
<div class="line"><a id="l01511" name="l01511"></a><span class="lineno"> 1511</span><span class="comment">/******************* Bit definition for ADC_HTR register ********************/</span></div>
|
||
<div class="line"><a id="l01512" name="l01512"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a635538ea4e4daa6b302e0d2d5c0932"> 1512</a></span><span class="preprocessor">#define ADC_HTR_HT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01513" name="l01513"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9097907041c9d3893ab46b359ade4b00"> 1513</a></span><span class="preprocessor">#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) </span></div>
|
||
<div class="line"><a id="l01514" name="l01514"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad685f031174465e636ef75a5bd7b637d"> 1514</a></span><span class="preprocessor">#define ADC_HTR_HT ADC_HTR_HT_Msk </span></div>
|
||
<div class="line"><a id="l01516" name="l01516"></a><span class="lineno"> 1516</span><span class="comment">/******************* Bit definition for ADC_LTR register ********************/</span></div>
|
||
<div class="line"><a id="l01517" name="l01517"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga309e0c5c17cfe008132dbc95924ba0cd"> 1517</a></span><span class="preprocessor">#define ADC_LTR_LT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01518" name="l01518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1c59cf6098c3ba86d00ff2eabbee680"> 1518</a></span><span class="preprocessor">#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) </span></div>
|
||
<div class="line"><a id="l01519" name="l01519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7ac18b970378acf726f04ae68232c24"> 1519</a></span><span class="preprocessor">#define ADC_LTR_LT ADC_LTR_LT_Msk </span></div>
|
||
<div class="line"><a id="l01521" name="l01521"></a><span class="lineno"> 1521</span><span class="comment">/******************* Bit definition for ADC_SQR1 register *******************/</span></div>
|
||
<div class="line"><a id="l01522" name="l01522"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga881b03d9be116c006dab51c6c46aee4e"> 1522</a></span><span class="preprocessor">#define ADC_SQR1_SQ13_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01523" name="l01523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08e9c7dc59718bbfbf1a3db4eba22f86"> 1523</a></span><span class="preprocessor">#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) </span></div>
|
||
<div class="line"><a id="l01524" name="l01524"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ae1998c0dd11275958e7347a92852fc"> 1524</a></span><span class="preprocessor">#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk </span></div>
|
||
<div class="line"><a id="l01525" name="l01525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40d24ddd458198e7731d5abf9d15fc08"> 1525</a></span><span class="preprocessor">#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) </span></div>
|
||
<div class="line"><a id="l01526" name="l01526"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccdca8b0f3cab9f62ae2ffbb9c30546f"> 1526</a></span><span class="preprocessor">#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) </span></div>
|
||
<div class="line"><a id="l01527" name="l01527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37e8723bfdc43da0b86e40a49b78c9ad"> 1527</a></span><span class="preprocessor">#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) </span></div>
|
||
<div class="line"><a id="l01528" name="l01528"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga412374f7ce1f62ee187c819391898778"> 1528</a></span><span class="preprocessor">#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) </span></div>
|
||
<div class="line"><a id="l01529" name="l01529"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05ca5e303f844f512c9a9cb5df9a1028"> 1529</a></span><span class="preprocessor">#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) </span></div>
|
||
<div class="line"><a id="l01530" name="l01530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ca511d19962e09ad2294844874a00de"> 1530</a></span><span class="preprocessor">#define ADC_SQR1_SQ14_Pos (5U) </span></div>
|
||
<div class="line"><a id="l01531" name="l01531"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac16eaf610307245433e59aee05bfe254"> 1531</a></span><span class="preprocessor">#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) </span></div>
|
||
<div class="line"><a id="l01532" name="l01532"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0251199146cb3d0d2c1c0608fbca585"> 1532</a></span><span class="preprocessor">#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk </span></div>
|
||
<div class="line"><a id="l01533" name="l01533"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacde3a6d9e94aa1c2399e335911fd6212"> 1533</a></span><span class="preprocessor">#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) </span></div>
|
||
<div class="line"><a id="l01534" name="l01534"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bc61e4d3ea200e1fc3e9d621ebbd2b4"> 1534</a></span><span class="preprocessor">#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) </span></div>
|
||
<div class="line"><a id="l01535" name="l01535"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeea616e444521cd58c5d8d574c47ccf0"> 1535</a></span><span class="preprocessor">#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) </span></div>
|
||
<div class="line"><a id="l01536" name="l01536"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e0c9439633fb5c67c8f2138c9d2efae"> 1536</a></span><span class="preprocessor">#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) </span></div>
|
||
<div class="line"><a id="l01537" name="l01537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea22b4dd0fbb26d2a0babbc483778b0e"> 1537</a></span><span class="preprocessor">#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) </span></div>
|
||
<div class="line"><a id="l01538" name="l01538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21eb97eeceffa9eb2cd4aea37af8b13f"> 1538</a></span><span class="preprocessor">#define ADC_SQR1_SQ15_Pos (10U) </span></div>
|
||
<div class="line"><a id="l01539" name="l01539"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2dcdc56b5476a5cbed60e74735574831"> 1539</a></span><span class="preprocessor">#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) </span></div>
|
||
<div class="line"><a id="l01540" name="l01540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23222c591c6d926f7a741bc9346f1d8f"> 1540</a></span><span class="preprocessor">#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk </span></div>
|
||
<div class="line"><a id="l01541" name="l01541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbfbc70f67ce1d8f227e17a7f19c123b"> 1541</a></span><span class="preprocessor">#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) </span></div>
|
||
<div class="line"><a id="l01542" name="l01542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac00e343ff0dd8f1f29e897148e3e070a"> 1542</a></span><span class="preprocessor">#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) </span></div>
|
||
<div class="line"><a id="l01543" name="l01543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab63443b0c5a2eca60a8c9714f6f31c03"> 1543</a></span><span class="preprocessor">#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) </span></div>
|
||
<div class="line"><a id="l01544" name="l01544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf676d45ba227a2dc641b2afadfa7852"> 1544</a></span><span class="preprocessor">#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) </span></div>
|
||
<div class="line"><a id="l01545" name="l01545"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7dbc07d0904f60abcc15827ccab1a8c2"> 1545</a></span><span class="preprocessor">#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) </span></div>
|
||
<div class="line"><a id="l01546" name="l01546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga175666e476ceceebaa0f3267aeb6ea09"> 1546</a></span><span class="preprocessor">#define ADC_SQR1_SQ16_Pos (15U) </span></div>
|
||
<div class="line"><a id="l01547" name="l01547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabddb795f3c7a42aba72d3961e19cc7fc"> 1547</a></span><span class="preprocessor">#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) </span></div>
|
||
<div class="line"><a id="l01548" name="l01548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafecb33099669a080cede6ce0236389e7"> 1548</a></span><span class="preprocessor">#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk </span></div>
|
||
<div class="line"><a id="l01549" name="l01549"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3404d0bf04b8561bf93455d968b77ea9"> 1549</a></span><span class="preprocessor">#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) </span></div>
|
||
<div class="line"><a id="l01550" name="l01550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ea6af777051f14be5cf166dd4ae69d1"> 1550</a></span><span class="preprocessor">#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) </span></div>
|
||
<div class="line"><a id="l01551" name="l01551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf59e4a113346ac3daf6829c3321444f5"> 1551</a></span><span class="preprocessor">#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) </span></div>
|
||
<div class="line"><a id="l01552" name="l01552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6052517e5fcab3f58c42b59fb3ffee55"> 1552</a></span><span class="preprocessor">#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) </span></div>
|
||
<div class="line"><a id="l01553" name="l01553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7af851b5898b4421958e7a100602c8cd"> 1553</a></span><span class="preprocessor">#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) </span></div>
|
||
<div class="line"><a id="l01554" name="l01554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58db108cdbc75716bedb45ba9fabe727"> 1554</a></span><span class="preprocessor">#define ADC_SQR1_L_Pos (20U) </span></div>
|
||
<div class="line"><a id="l01555" name="l01555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac11490606e7ecc26985deed271f7ff57"> 1555</a></span><span class="preprocessor">#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) </span></div>
|
||
<div class="line"><a id="l01556" name="l01556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae68a19a18d72f6d87c6f2b8cc8bfc6dc"> 1556</a></span><span class="preprocessor">#define ADC_SQR1_L ADC_SQR1_L_Msk </span></div>
|
||
<div class="line"><a id="l01557" name="l01557"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00ec56fbf232492ec12c954e27d03c6c"> 1557</a></span><span class="preprocessor">#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) </span></div>
|
||
<div class="line"><a id="l01558" name="l01558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52708c6570da08c295603e5b52461ecd"> 1558</a></span><span class="preprocessor">#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) </span></div>
|
||
<div class="line"><a id="l01559" name="l01559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b914eeb128157c4acf6f6b9a4be5558"> 1559</a></span><span class="preprocessor">#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) </span></div>
|
||
<div class="line"><a id="l01560" name="l01560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffdd34daa55da53d18055417ae895c47"> 1560</a></span><span class="preprocessor">#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) </span></div>
|
||
<div class="line"><a id="l01562" name="l01562"></a><span class="lineno"> 1562</span><span class="comment">/******************* Bit definition for ADC_SQR2 register *******************/</span></div>
|
||
<div class="line"><a id="l01563" name="l01563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga589d869844063982a6fc59daa2d49aee"> 1563</a></span><span class="preprocessor">#define ADC_SQR2_SQ7_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01564" name="l01564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee89c65015de91a4fc92b922bcef81fe"> 1564</a></span><span class="preprocessor">#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) </span></div>
|
||
<div class="line"><a id="l01565" name="l01565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9f66f702fc124040956117f20ef8df4"> 1565</a></span><span class="preprocessor">#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk </span></div>
|
||
<div class="line"><a id="l01566" name="l01566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12bbc822c10582a80f7e20a11038ce96"> 1566</a></span><span class="preprocessor">#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) </span></div>
|
||
<div class="line"><a id="l01567" name="l01567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d0d7daf3b6db6ff4fa382495f6127c6"> 1567</a></span><span class="preprocessor">#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) </span></div>
|
||
<div class="line"><a id="l01568" name="l01568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74bda24f18a95261661a944cecf45a52"> 1568</a></span><span class="preprocessor">#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) </span></div>
|
||
<div class="line"><a id="l01569" name="l01569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2697675d008dda4e6a4905fc0f8d22af"> 1569</a></span><span class="preprocessor">#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) </span></div>
|
||
<div class="line"><a id="l01570" name="l01570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c46dd0f30ef85094ca0cde2e8c00dac"> 1570</a></span><span class="preprocessor">#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) </span></div>
|
||
<div class="line"><a id="l01571" name="l01571"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab83e34058c7c593c58b4fc8f7d27084"> 1571</a></span><span class="preprocessor">#define ADC_SQR2_SQ8_Pos (5U) </span></div>
|
||
<div class="line"><a id="l01572" name="l01572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9152be162b9262d76b7a59b4c0f25956"> 1572</a></span><span class="preprocessor">#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) </span></div>
|
||
<div class="line"><a id="l01573" name="l01573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga308ec58a8d20dcb3a348c30c332a0a8e"> 1573</a></span><span class="preprocessor">#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk </span></div>
|
||
<div class="line"><a id="l01574" name="l01574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga858717a28d6c26612ad4ced46863ba13"> 1574</a></span><span class="preprocessor">#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) </span></div>
|
||
<div class="line"><a id="l01575" name="l01575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d06168a43b4845409f2fb9193ee474a"> 1575</a></span><span class="preprocessor">#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) </span></div>
|
||
<div class="line"><a id="l01576" name="l01576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5eaea65d6719a8199639ec30bb8a07b"> 1576</a></span><span class="preprocessor">#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) </span></div>
|
||
<div class="line"><a id="l01577" name="l01577"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23e22da18926dd107adc69282a445412"> 1577</a></span><span class="preprocessor">#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) </span></div>
|
||
<div class="line"><a id="l01578" name="l01578"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacadd092f31f37bb129065be175673c63"> 1578</a></span><span class="preprocessor">#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) </span></div>
|
||
<div class="line"><a id="l01579" name="l01579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8585b815abcb076901d4f1a4c8d6c80b"> 1579</a></span><span class="preprocessor">#define ADC_SQR2_SQ9_Pos (10U) </span></div>
|
||
<div class="line"><a id="l01580" name="l01580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03bc5dff92603b8e5dfe5ac87552f40a"> 1580</a></span><span class="preprocessor">#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) </span></div>
|
||
<div class="line"><a id="l01581" name="l01581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5d91ecfc3d40cc6b1960544e526eb91"> 1581</a></span><span class="preprocessor">#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk </span></div>
|
||
<div class="line"><a id="l01582" name="l01582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace032949b436d9af8a20ea10a349d55b"> 1582</a></span><span class="preprocessor">#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) </span></div>
|
||
<div class="line"><a id="l01583" name="l01583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5cf43f1c5de0e73d6159fabc3681b891"> 1583</a></span><span class="preprocessor">#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) </span></div>
|
||
<div class="line"><a id="l01584" name="l01584"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3389c07a9de242151ffa434908fee39d"> 1584</a></span><span class="preprocessor">#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) </span></div>
|
||
<div class="line"><a id="l01585" name="l01585"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13f30540b9f2d33640ea7d9652dc3c71"> 1585</a></span><span class="preprocessor">#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) </span></div>
|
||
<div class="line"><a id="l01586" name="l01586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga910e5bda9852d49117b76b0d9f420ef2"> 1586</a></span><span class="preprocessor">#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) </span></div>
|
||
<div class="line"><a id="l01587" name="l01587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48d10816801feffec06a224ee726a97e"> 1587</a></span><span class="preprocessor">#define ADC_SQR2_SQ10_Pos (15U) </span></div>
|
||
<div class="line"><a id="l01588" name="l01588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a438cb8cfa6116018759eca4d2c2fbb"> 1588</a></span><span class="preprocessor">#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) </span></div>
|
||
<div class="line"><a id="l01589" name="l01589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22e474b65f217ac21137b1d3f3cbb6bb"> 1589</a></span><span class="preprocessor">#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk </span></div>
|
||
<div class="line"><a id="l01590" name="l01590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5a36056dbfce703d22387432ac12262"> 1590</a></span><span class="preprocessor">#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) </span></div>
|
||
<div class="line"><a id="l01591" name="l01591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09a1de734fe67156af26edf3b8a61044"> 1591</a></span><span class="preprocessor">#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) </span></div>
|
||
<div class="line"><a id="l01592" name="l01592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b1d6ad0a40e7171d40a964b361d1eb9"> 1592</a></span><span class="preprocessor">#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) </span></div>
|
||
<div class="line"><a id="l01593" name="l01593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24d63e60eabad897aa9b19dbe56da71e"> 1593</a></span><span class="preprocessor">#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) </span></div>
|
||
<div class="line"><a id="l01594" name="l01594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7df899f74116e6cb3205af2767840cfb"> 1594</a></span><span class="preprocessor">#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) </span></div>
|
||
<div class="line"><a id="l01595" name="l01595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6148bba86967003cb581b42e6eaa29e5"> 1595</a></span><span class="preprocessor">#define ADC_SQR2_SQ11_Pos (20U) </span></div>
|
||
<div class="line"><a id="l01596" name="l01596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f72a350259ac99fdcda7a97eb6fe2a8"> 1596</a></span><span class="preprocessor">#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) </span></div>
|
||
<div class="line"><a id="l01597" name="l01597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7bf491b9c1542fb0d0b83fc96166362e"> 1597</a></span><span class="preprocessor">#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk </span></div>
|
||
<div class="line"><a id="l01598" name="l01598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bc91fec2ef468c5d39d19beda9ecd3e"> 1598</a></span><span class="preprocessor">#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) </span></div>
|
||
<div class="line"><a id="l01599" name="l01599"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e142789d2bd0584480e923754544ff5"> 1599</a></span><span class="preprocessor">#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) </span></div>
|
||
<div class="line"><a id="l01600" name="l01600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6b844fe698c16437e91c9e05a367a4c"> 1600</a></span><span class="preprocessor">#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) </span></div>
|
||
<div class="line"><a id="l01601" name="l01601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a8127191e3c48f4e0952bdb5e196225"> 1601</a></span><span class="preprocessor">#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) </span></div>
|
||
<div class="line"><a id="l01602" name="l01602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e8a39f645505ef84cb94bbc8d21b8e0"> 1602</a></span><span class="preprocessor">#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) </span></div>
|
||
<div class="line"><a id="l01603" name="l01603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2490bed33c8e2523dd8fd0f48cf1ab4"> 1603</a></span><span class="preprocessor">#define ADC_SQR2_SQ12_Pos (25U) </span></div>
|
||
<div class="line"><a id="l01604" name="l01604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a8e8248a0fe8bbf43de3e6f06984a85"> 1604</a></span><span class="preprocessor">#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) </span></div>
|
||
<div class="line"><a id="l01605" name="l01605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8731660b1710e63d5423cd31c11be184"> 1605</a></span><span class="preprocessor">#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk </span></div>
|
||
<div class="line"><a id="l01606" name="l01606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b2da909e54f8f6f61bf2bd2cd3e93e0"> 1606</a></span><span class="preprocessor">#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) </span></div>
|
||
<div class="line"><a id="l01607" name="l01607"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5930c4a07d594aa23bc868526b42601"> 1607</a></span><span class="preprocessor">#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) </span></div>
|
||
<div class="line"><a id="l01608" name="l01608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga377805a21e7da2a66a3913a77bcc1e66"> 1608</a></span><span class="preprocessor">#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) </span></div>
|
||
<div class="line"><a id="l01609" name="l01609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e3b45cac9aeb68d33b31a0914692857"> 1609</a></span><span class="preprocessor">#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) </span></div>
|
||
<div class="line"><a id="l01610" name="l01610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6043d31a6cb9bd7c1542c3d41eb296c7"> 1610</a></span><span class="preprocessor">#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) </span></div>
|
||
<div class="line"><a id="l01612" name="l01612"></a><span class="lineno"> 1612</span><span class="comment">/******************* Bit definition for ADC_SQR3 register *******************/</span></div>
|
||
<div class="line"><a id="l01613" name="l01613"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac825474ea3bcec005557a9fe47526a4f"> 1613</a></span><span class="preprocessor">#define ADC_SQR3_SQ1_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01614" name="l01614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga158e02c01bc2ee902ff9d4ca8c767184"> 1614</a></span><span class="preprocessor">#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) </span></div>
|
||
<div class="line"><a id="l01615" name="l01615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52491114e8394648559004f3bae718d9"> 1615</a></span><span class="preprocessor">#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk </span></div>
|
||
<div class="line"><a id="l01616" name="l01616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53d3bb1c8bb48c7bcb0f7409db69f7b4"> 1616</a></span><span class="preprocessor">#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) </span></div>
|
||
<div class="line"><a id="l01617" name="l01617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddb9af3a3b23a103fbc34c4f422fd2af"> 1617</a></span><span class="preprocessor">#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) </span></div>
|
||
<div class="line"><a id="l01618" name="l01618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf591f43a15c0c2c5afae2598b8f2afc"> 1618</a></span><span class="preprocessor">#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) </span></div>
|
||
<div class="line"><a id="l01619" name="l01619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05cfde0ef0e6a8dd6311f5cd7a806556"> 1619</a></span><span class="preprocessor">#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) </span></div>
|
||
<div class="line"><a id="l01620" name="l01620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9981512f99a6c41ce107a9428d9cfdd0"> 1620</a></span><span class="preprocessor">#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) </span></div>
|
||
<div class="line"><a id="l01621" name="l01621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92d0269f674151ea3e8e38760675099c"> 1621</a></span><span class="preprocessor">#define ADC_SQR3_SQ2_Pos (5U) </span></div>
|
||
<div class="line"><a id="l01622" name="l01622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e5a7d30b953796355d6e134aefa7fc3"> 1622</a></span><span class="preprocessor">#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) </span></div>
|
||
<div class="line"><a id="l01623" name="l01623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60637fb25c099f8da72a8a36211f7a8c"> 1623</a></span><span class="preprocessor">#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk </span></div>
|
||
<div class="line"><a id="l01624" name="l01624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaede0302eb64f023913c7a9e588d77937"> 1624</a></span><span class="preprocessor">#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) </span></div>
|
||
<div class="line"><a id="l01625" name="l01625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga158ab7429a864634a46c81fdb51d7508"> 1625</a></span><span class="preprocessor">#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) </span></div>
|
||
<div class="line"><a id="l01626" name="l01626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae729e21d590271c59c0d653300d5581c"> 1626</a></span><span class="preprocessor">#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) </span></div>
|
||
<div class="line"><a id="l01627" name="l01627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf65c33275178a8777fa8fed8a01f7389"> 1627</a></span><span class="preprocessor">#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) </span></div>
|
||
<div class="line"><a id="l01628" name="l01628"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga990aeb689b7cc8f0bebb3dd6af7b27a6"> 1628</a></span><span class="preprocessor">#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) </span></div>
|
||
<div class="line"><a id="l01629" name="l01629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70ca80250d365fa475d9afed6d03ca8b"> 1629</a></span><span class="preprocessor">#define ADC_SQR3_SQ3_Pos (10U) </span></div>
|
||
<div class="line"><a id="l01630" name="l01630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea87ead7a01cad5a05b3212eb1b5ce35"> 1630</a></span><span class="preprocessor">#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) </span></div>
|
||
<div class="line"><a id="l01631" name="l01631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga601f21b7c1e571fb8c5ff310aca021e1"> 1631</a></span><span class="preprocessor">#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk </span></div>
|
||
<div class="line"><a id="l01632" name="l01632"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fd2c154b5852cb08ce60b4adfa36313"> 1632</a></span><span class="preprocessor">#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) </span></div>
|
||
<div class="line"><a id="l01633" name="l01633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga214580377dd3a424ad819f14f6b025d4"> 1633</a></span><span class="preprocessor">#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) </span></div>
|
||
<div class="line"><a id="l01634" name="l01634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabae2353b109c9cda2a176ea1f44db4fe"> 1634</a></span><span class="preprocessor">#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) </span></div>
|
||
<div class="line"><a id="l01635" name="l01635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d2f00d3372bd1d64bf4eb2271277ab0"> 1635</a></span><span class="preprocessor">#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) </span></div>
|
||
<div class="line"><a id="l01636" name="l01636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5279e505b1a59b223f30e5be139d5042"> 1636</a></span><span class="preprocessor">#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) </span></div>
|
||
<div class="line"><a id="l01637" name="l01637"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01430f2ace37e28c2c79a923632d094a"> 1637</a></span><span class="preprocessor">#define ADC_SQR3_SQ4_Pos (15U) </span></div>
|
||
<div class="line"><a id="l01638" name="l01638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f6ee00d27c507e9b088b1f6b825ab55"> 1638</a></span><span class="preprocessor">#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) </span></div>
|
||
<div class="line"><a id="l01639" name="l01639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3fc43f70bb3c67c639678b91d852390b"> 1639</a></span><span class="preprocessor">#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk </span></div>
|
||
<div class="line"><a id="l01640" name="l01640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2a501b20cf758a7353efcb3f95a3a93"> 1640</a></span><span class="preprocessor">#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) </span></div>
|
||
<div class="line"><a id="l01641" name="l01641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffafa27fd561e4c7d419e3f665d80f2c"> 1641</a></span><span class="preprocessor">#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) </span></div>
|
||
<div class="line"><a id="l01642" name="l01642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0251fa70e400ee74f442d8fba2b1afb"> 1642</a></span><span class="preprocessor">#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) </span></div>
|
||
<div class="line"><a id="l01643" name="l01643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3dc48c3c6b304517261486d8a63637ae"> 1643</a></span><span class="preprocessor">#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) </span></div>
|
||
<div class="line"><a id="l01644" name="l01644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe23b9e640df96ca84eab4b6b4f44083"> 1644</a></span><span class="preprocessor">#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) </span></div>
|
||
<div class="line"><a id="l01645" name="l01645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga834a04bad696f9b1a363e828441e5d6a"> 1645</a></span><span class="preprocessor">#define ADC_SQR3_SQ5_Pos (20U) </span></div>
|
||
<div class="line"><a id="l01646" name="l01646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaade1e4985264c9bc583a6803cc54e7cf"> 1646</a></span><span class="preprocessor">#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) </span></div>
|
||
<div class="line"><a id="l01647" name="l01647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae841d68049442e4568b86322ed4be6f"> 1647</a></span><span class="preprocessor">#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk </span></div>
|
||
<div class="line"><a id="l01648" name="l01648"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1de9fc24755b715c700c6442f4a396b"> 1648</a></span><span class="preprocessor">#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) </span></div>
|
||
<div class="line"><a id="l01649" name="l01649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f704feb58eecb39bc7f199577064172"> 1649</a></span><span class="preprocessor">#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) </span></div>
|
||
<div class="line"><a id="l01650" name="l01650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88a7994f637a75d105cc5975b154c373"> 1650</a></span><span class="preprocessor">#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) </span></div>
|
||
<div class="line"><a id="l01651" name="l01651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31c6fce8f01e75c68124124061f67f0e"> 1651</a></span><span class="preprocessor">#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) </span></div>
|
||
<div class="line"><a id="l01652" name="l01652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b0cad694c068ea8874b6504bd6ae885"> 1652</a></span><span class="preprocessor">#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) </span></div>
|
||
<div class="line"><a id="l01653" name="l01653"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga972ec9142a3fdc4969c91b9743372a9c"> 1653</a></span><span class="preprocessor">#define ADC_SQR3_SQ6_Pos (25U) </span></div>
|
||
<div class="line"><a id="l01654" name="l01654"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab01b48333516c485500fcf186f861bf3"> 1654</a></span><span class="preprocessor">#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) </span></div>
|
||
<div class="line"><a id="l01655" name="l01655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga723792274b16b342d16d6a02fce74ba6"> 1655</a></span><span class="preprocessor">#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk </span></div>
|
||
<div class="line"><a id="l01656" name="l01656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91b8b5293abd0601c543c13a0b53b335"> 1656</a></span><span class="preprocessor">#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) </span></div>
|
||
<div class="line"><a id="l01657" name="l01657"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab29847362a613b43eeeda6db758d781e"> 1657</a></span><span class="preprocessor">#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) </span></div>
|
||
<div class="line"><a id="l01658" name="l01658"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa92c8ea1bfb42ed80622770ae2dc41ab"> 1658</a></span><span class="preprocessor">#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) </span></div>
|
||
<div class="line"><a id="l01659" name="l01659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed2d7edb11fb84b02c175acff305a922"> 1659</a></span><span class="preprocessor">#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) </span></div>
|
||
<div class="line"><a id="l01660" name="l01660"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78f9e51811549a6797ecfe1468def4ff"> 1660</a></span><span class="preprocessor">#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) </span></div>
|
||
<div class="line"><a id="l01662" name="l01662"></a><span class="lineno"> 1662</span><span class="comment">/******************* Bit definition for ADC_JSQR register *******************/</span></div>
|
||
<div class="line"><a id="l01663" name="l01663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9c01f684cb7d1dc5db5d91d29706d1e"> 1663</a></span><span class="preprocessor">#define ADC_JSQR_JSQ1_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01664" name="l01664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d51f520a176b598792f5019ef4e1f7e"> 1664</a></span><span class="preprocessor">#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) </span></div>
|
||
<div class="line"><a id="l01665" name="l01665"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7fa15dfe51b084b36cb5df2fbf44bb2"> 1665</a></span><span class="preprocessor">#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk </span></div>
|
||
<div class="line"><a id="l01666" name="l01666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3ea38b080462c4571524b5fcbfed292"> 1666</a></span><span class="preprocessor">#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) </span></div>
|
||
<div class="line"><a id="l01667" name="l01667"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabae36d7655fb1dce11e60ffa8e57b509"> 1667</a></span><span class="preprocessor">#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) </span></div>
|
||
<div class="line"><a id="l01668" name="l01668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3e7a96d33f640444b40b70e9ee28671"> 1668</a></span><span class="preprocessor">#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) </span></div>
|
||
<div class="line"><a id="l01669" name="l01669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6066a6aef47f317a5df0c9bbf59121fb"> 1669</a></span><span class="preprocessor">#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) </span></div>
|
||
<div class="line"><a id="l01670" name="l01670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2c4baf98380a477cebb01be3e8f0594"> 1670</a></span><span class="preprocessor">#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) </span></div>
|
||
<div class="line"><a id="l01671" name="l01671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga086dad3b0d75e5a34736717f639f54bc"> 1671</a></span><span class="preprocessor">#define ADC_JSQR_JSQ2_Pos (5U) </span></div>
|
||
<div class="line"><a id="l01672" name="l01672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fb22b426f041225a2383fbb9a014c74"> 1672</a></span><span class="preprocessor">#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) </span></div>
|
||
<div class="line"><a id="l01673" name="l01673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e8446a5857e5379cff8cadf822e15d4"> 1673</a></span><span class="preprocessor">#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk </span></div>
|
||
<div class="line"><a id="l01674" name="l01674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabf0889d056b56e4a113142b3694166d"> 1674</a></span><span class="preprocessor">#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) </span></div>
|
||
<div class="line"><a id="l01675" name="l01675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga048f97e9e332adb21eca27b647af1378"> 1675</a></span><span class="preprocessor">#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) </span></div>
|
||
<div class="line"><a id="l01676" name="l01676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18bee187ed94e73b16eeea7501394581"> 1676</a></span><span class="preprocessor">#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) </span></div>
|
||
<div class="line"><a id="l01677" name="l01677"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78b031d11b56e49b2c28c1a79136b48a"> 1677</a></span><span class="preprocessor">#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) </span></div>
|
||
<div class="line"><a id="l01678" name="l01678"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga064d6ccde30a22430c658b8efc431e59"> 1678</a></span><span class="preprocessor">#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) </span></div>
|
||
<div class="line"><a id="l01679" name="l01679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9af86c6e6cd2d134f389580a03449e9e"> 1679</a></span><span class="preprocessor">#define ADC_JSQR_JSQ3_Pos (10U) </span></div>
|
||
<div class="line"><a id="l01680" name="l01680"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b87c9c110f68556c6d266cd9808165b"> 1680</a></span><span class="preprocessor">#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) </span></div>
|
||
<div class="line"><a id="l01681" name="l01681"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2fbdc1b854a54c4288402c2d3a7fca9"> 1681</a></span><span class="preprocessor">#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk </span></div>
|
||
<div class="line"><a id="l01682" name="l01682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12fbc27c3543f23125f632dfa60fdc98"> 1682</a></span><span class="preprocessor">#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) </span></div>
|
||
<div class="line"><a id="l01683" name="l01683"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga169ec7d371e3ee897b73c3ad84b6ed32"> 1683</a></span><span class="preprocessor">#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) </span></div>
|
||
<div class="line"><a id="l01684" name="l01684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga693542d5a536304f364476589ba0bec9"> 1684</a></span><span class="preprocessor">#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) </span></div>
|
||
<div class="line"><a id="l01685" name="l01685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga139ddd01c0faf219dca844477453149e"> 1685</a></span><span class="preprocessor">#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) </span></div>
|
||
<div class="line"><a id="l01686" name="l01686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1452b8cf4acc90fb522d90751043aac"> 1686</a></span><span class="preprocessor">#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) </span></div>
|
||
<div class="line"><a id="l01687" name="l01687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24746201bf3845f70dc4e442d61d470a"> 1687</a></span><span class="preprocessor">#define ADC_JSQR_JSQ4_Pos (15U) </span></div>
|
||
<div class="line"><a id="l01688" name="l01688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3c43ea620dd89338b58bf89feab30fd"> 1688</a></span><span class="preprocessor">#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) </span></div>
|
||
<div class="line"><a id="l01689" name="l01689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39a279051ef198ee34cad73743b996f4"> 1689</a></span><span class="preprocessor">#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk </span></div>
|
||
<div class="line"><a id="l01690" name="l01690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13e250d329673c02f7a0d24d25e83649"> 1690</a></span><span class="preprocessor">#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) </span></div>
|
||
<div class="line"><a id="l01691" name="l01691"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30dad81d708c35136e2da4e96cfe07b7"> 1691</a></span><span class="preprocessor">#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) </span></div>
|
||
<div class="line"><a id="l01692" name="l01692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ceab97acb95b31cb7448c9da38fc11a"> 1692</a></span><span class="preprocessor">#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) </span></div>
|
||
<div class="line"><a id="l01693" name="l01693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52f6571e7efed6a0f72df19c66d3c917"> 1693</a></span><span class="preprocessor">#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) </span></div>
|
||
<div class="line"><a id="l01694" name="l01694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaede3a17ef541039943d9dcd85df223ca"> 1694</a></span><span class="preprocessor">#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) </span></div>
|
||
<div class="line"><a id="l01695" name="l01695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1dd38cefe9e4ca58d8535c9b2386cb1"> 1695</a></span><span class="preprocessor">#define ADC_JSQR_JL_Pos (20U) </span></div>
|
||
<div class="line"><a id="l01696" name="l01696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11fbbdaa929d9ecf3054aaaed0285b05"> 1696</a></span><span class="preprocessor">#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) </span></div>
|
||
<div class="line"><a id="l01697" name="l01697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa624d1fe34014b88873e2dfa91f79232"> 1697</a></span><span class="preprocessor">#define ADC_JSQR_JL ADC_JSQR_JL_Msk </span></div>
|
||
<div class="line"><a id="l01698" name="l01698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga117a6719241f20dbd765bc34f9ffcd58"> 1698</a></span><span class="preprocessor">#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) </span></div>
|
||
<div class="line"><a id="l01699" name="l01699"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f82ef3b6e6350b9e52e622daeaa3e6e"> 1699</a></span><span class="preprocessor">#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) </span></div>
|
||
<div class="line"><a id="l01701" name="l01701"></a><span class="lineno"> 1701</span><span class="comment">/******************* Bit definition for ADC_JDR1 register *******************/</span></div>
|
||
<div class="line"><a id="l01702" name="l01702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb0c0f7960a790d485b1ae99aed0e8c7"> 1702</a></span><span class="preprocessor">#define ADC_JDR1_JDATA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01703" name="l01703"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6440d03419f23870bf5bf1a38a57c79d"> 1703</a></span><span class="preprocessor">#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) </span></div>
|
||
<div class="line"><a id="l01704" name="l01704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad02fcd8fd97b2f7d70a5a04fed60b558"> 1704</a></span><span class="preprocessor">#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk </span></div>
|
||
<div class="line"><a id="l01706" name="l01706"></a><span class="lineno"> 1706</span><span class="comment">/******************* Bit definition for ADC_JDR2 register *******************/</span></div>
|
||
<div class="line"><a id="l01707" name="l01707"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e02f5dbe30f9da55c112634b5636b3d"> 1707</a></span><span class="preprocessor">#define ADC_JDR2_JDATA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01708" name="l01708"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0ff8b95da1c11baf16aa35dd8672670"> 1708</a></span><span class="preprocessor">#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) </span></div>
|
||
<div class="line"><a id="l01709" name="l01709"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fbd8801b9c60269ca477062985a08e8"> 1709</a></span><span class="preprocessor">#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk </span></div>
|
||
<div class="line"><a id="l01711" name="l01711"></a><span class="lineno"> 1711</span><span class="comment">/******************* Bit definition for ADC_JDR3 register *******************/</span></div>
|
||
<div class="line"><a id="l01712" name="l01712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga382b9639cc85f4dc0c4603b83e4e3246"> 1712</a></span><span class="preprocessor">#define ADC_JDR3_JDATA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01713" name="l01713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee0994ddf4fa21f7e6cedc0c3d599683"> 1713</a></span><span class="preprocessor">#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) </span></div>
|
||
<div class="line"><a id="l01714" name="l01714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae84e9e5928bb9ed1aef6c83089fb5ef"> 1714</a></span><span class="preprocessor">#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk </span></div>
|
||
<div class="line"><a id="l01716" name="l01716"></a><span class="lineno"> 1716</span><span class="comment">/******************* Bit definition for ADC_JDR4 register *******************/</span></div>
|
||
<div class="line"><a id="l01717" name="l01717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa993f3df2df14e7be95b96543bd4873f"> 1717</a></span><span class="preprocessor">#define ADC_JDR4_JDATA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01718" name="l01718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad42adbc5ae1c70cdc1926642fcc2baef"> 1718</a></span><span class="preprocessor">#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) </span></div>
|
||
<div class="line"><a id="l01719" name="l01719"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48d8fafdad1fb1bb0f761fd833e7b0c1"> 1719</a></span><span class="preprocessor">#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk </span></div>
|
||
<div class="line"><a id="l01721" name="l01721"></a><span class="lineno"> 1721</span><span class="comment">/******************** Bit definition for ADC_DR register ********************/</span></div>
|
||
<div class="line"><a id="l01722" name="l01722"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84a231db4b53876ee3823b0ea3c92a06"> 1722</a></span><span class="preprocessor">#define ADC_DR_DATA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01723" name="l01723"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85ec9cca38cafd77f3d56fdf80f84eb7"> 1723</a></span><span class="preprocessor">#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) </span></div>
|
||
<div class="line"><a id="l01724" name="l01724"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada596183c4087696c486546e88176038"> 1724</a></span><span class="preprocessor">#define ADC_DR_DATA ADC_DR_DATA_Msk </span></div>
|
||
<div class="line"><a id="l01725" name="l01725"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6fdf317d06706f2a57b4aca8334eb37"> 1725</a></span><span class="preprocessor">#define ADC_DR_ADC2DATA_Pos (16U) </span></div>
|
||
<div class="line"><a id="l01726" name="l01726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86da874944121326b9f268295d8ce9b9"> 1726</a></span><span class="preprocessor">#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) </span></div>
|
||
<div class="line"><a id="l01727" name="l01727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67c396288ac97bfab2d37017bd536b98"> 1727</a></span><span class="preprocessor">#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk </span></div>
|
||
<div class="line"><a id="l01729" name="l01729"></a><span class="lineno"> 1729</span><span class="comment">/******************* Bit definition for ADC_CSR register ********************/</span></div>
|
||
<div class="line"><a id="l01730" name="l01730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabf05dcdb9f298564bf23c2c012e0471"> 1730</a></span><span class="preprocessor">#define ADC_CSR_AWD1_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01731" name="l01731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fc1dc3f69bc55d0dc278a8cfe172200"> 1731</a></span><span class="preprocessor">#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) </span></div>
|
||
<div class="line"><a id="l01732" name="l01732"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e640f7443f14d01a37e29cff004223f"> 1732</a></span><span class="preprocessor">#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk </span></div>
|
||
<div class="line"><a id="l01733" name="l01733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga193522f6fdf87c39545d2697f3650547"> 1733</a></span><span class="preprocessor">#define ADC_CSR_EOC1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l01734" name="l01734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacaca4cc88bbeca3aee454610c500d2fc"> 1734</a></span><span class="preprocessor">#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos) </span></div>
|
||
<div class="line"><a id="l01735" name="l01735"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga715bcb019d713187aacd46f4482fa5f9"> 1735</a></span><span class="preprocessor">#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk </span></div>
|
||
<div class="line"><a id="l01736" name="l01736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabff4c4fa606c1a8c035b453d95da53fd"> 1736</a></span><span class="preprocessor">#define ADC_CSR_JEOC1_Pos (2U) </span></div>
|
||
<div class="line"><a id="l01737" name="l01737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga954441bd559cdbe9da94c7ff0172c859"> 1737</a></span><span class="preprocessor">#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos) </span></div>
|
||
<div class="line"><a id="l01738" name="l01738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a8a134d8b946f3549390294ef94b8d6"> 1738</a></span><span class="preprocessor">#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk </span></div>
|
||
<div class="line"><a id="l01739" name="l01739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa094512686f5c37d85ec4c41b9fe1d21"> 1739</a></span><span class="preprocessor">#define ADC_CSR_JSTRT1_Pos (3U) </span></div>
|
||
<div class="line"><a id="l01740" name="l01740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e0c41a114f966849054e2e43ee9b115"> 1740</a></span><span class="preprocessor">#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) </span></div>
|
||
<div class="line"><a id="l01741" name="l01741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f1e6578b14d71c6d972c6d6f6d48eaa"> 1741</a></span><span class="preprocessor">#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk </span></div>
|
||
<div class="line"><a id="l01742" name="l01742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga186066448c230ab12a99cd67a22aaea5"> 1742</a></span><span class="preprocessor">#define ADC_CSR_STRT1_Pos (4U) </span></div>
|
||
<div class="line"><a id="l01743" name="l01743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d9691131e58b26068e792ad4b458bd6"> 1743</a></span><span class="preprocessor">#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) </span></div>
|
||
<div class="line"><a id="l01744" name="l01744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78ff468cfaa299ef62ab7b8b9910e142"> 1744</a></span><span class="preprocessor">#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk </span></div>
|
||
<div class="line"><a id="l01745" name="l01745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94e77ef740b6a1dccec74746261be4f1"> 1745</a></span><span class="preprocessor">#define ADC_CSR_OVR1_Pos (5U) </span></div>
|
||
<div class="line"><a id="l01746" name="l01746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ab0daf58c1ac552862c36465fc864cc"> 1746</a></span><span class="preprocessor">#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) </span></div>
|
||
<div class="line"><a id="l01747" name="l01747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52c109fe013835222183c22b26d6edec"> 1747</a></span><span class="preprocessor">#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk </span></div>
|
||
<div class="line"><a id="l01748" name="l01748"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f64205df755a2aef86ebb9f9cbe912f"> 1748</a></span><span class="preprocessor">#define ADC_CSR_AWD2_Pos (8U) </span></div>
|
||
<div class="line"><a id="l01749" name="l01749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf07d606cd2ac81d17e0a9cf425261d33"> 1749</a></span><span class="preprocessor">#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos) </span></div>
|
||
<div class="line"><a id="l01750" name="l01750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80d8090a99ec65807ed831fea0d5524c"> 1750</a></span><span class="preprocessor">#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk </span></div>
|
||
<div class="line"><a id="l01751" name="l01751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c366fb2cc8fe08c701b8b8f5babe5f8"> 1751</a></span><span class="preprocessor">#define ADC_CSR_EOC2_Pos (9U) </span></div>
|
||
<div class="line"><a id="l01752" name="l01752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d50d5f274525ebcca937eac9f52d2d1"> 1752</a></span><span class="preprocessor">#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos) </span></div>
|
||
<div class="line"><a id="l01753" name="l01753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga411d79254769bbb4eeb14964abad497a"> 1753</a></span><span class="preprocessor">#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk </span></div>
|
||
<div class="line"><a id="l01754" name="l01754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5615f8b2030741d5188cb255da51a409"> 1754</a></span><span class="preprocessor">#define ADC_CSR_JEOC2_Pos (10U) </span></div>
|
||
<div class="line"><a id="l01755" name="l01755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a92cfaa1c1cf45b621a52cdea84dfb4"> 1755</a></span><span class="preprocessor">#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos) </span></div>
|
||
<div class="line"><a id="l01756" name="l01756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf24dbb77fadc6f928b8e38199a08abc7"> 1756</a></span><span class="preprocessor">#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk </span></div>
|
||
<div class="line"><a id="l01757" name="l01757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7624f0eb95cc1a44180577d68273a13"> 1757</a></span><span class="preprocessor">#define ADC_CSR_JSTRT2_Pos (11U) </span></div>
|
||
<div class="line"><a id="l01758" name="l01758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f6fcf838fd219679c57c9b87eba1444"> 1758</a></span><span class="preprocessor">#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos) </span></div>
|
||
<div class="line"><a id="l01759" name="l01759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ca65d6d580299518fb7491e1cebac1d"> 1759</a></span><span class="preprocessor">#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk </span></div>
|
||
<div class="line"><a id="l01760" name="l01760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf06d7d8b3b81c9fca7b92449c039a859"> 1760</a></span><span class="preprocessor">#define ADC_CSR_STRT2_Pos (12U) </span></div>
|
||
<div class="line"><a id="l01761" name="l01761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae765e2672e081170cb86dc14096b2c9d"> 1761</a></span><span class="preprocessor">#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos) </span></div>
|
||
<div class="line"><a id="l01762" name="l01762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9e79005049b17d08c28aeca86677655"> 1762</a></span><span class="preprocessor">#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk </span></div>
|
||
<div class="line"><a id="l01763" name="l01763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ad98b43be125be93ecac83e636b9b30"> 1763</a></span><span class="preprocessor">#define ADC_CSR_OVR2_Pos (13U) </span></div>
|
||
<div class="line"><a id="l01764" name="l01764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga592e0a5440edb75e0af2cbb8f8e9f4ca"> 1764</a></span><span class="preprocessor">#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos) </span></div>
|
||
<div class="line"><a id="l01765" name="l01765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b0e80da58202660466f6916c0bbb9da"> 1765</a></span><span class="preprocessor">#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk </span></div>
|
||
<div class="line"><a id="l01766" name="l01766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cc0cb58fe0e65bf12a871cd5b4f5a3a"> 1766</a></span><span class="preprocessor">#define ADC_CSR_AWD3_Pos (16U) </span></div>
|
||
<div class="line"><a id="l01767" name="l01767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab466d762c126698b9be1d851411e13b9"> 1767</a></span><span class="preprocessor">#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) </span></div>
|
||
<div class="line"><a id="l01768" name="l01768"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8883de33c5a7b30c611db11340fec6d"> 1768</a></span><span class="preprocessor">#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk </span></div>
|
||
<div class="line"><a id="l01769" name="l01769"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17e2ab7d373bb1befc8891719de8c437"> 1769</a></span><span class="preprocessor">#define ADC_CSR_EOC3_Pos (17U) </span></div>
|
||
<div class="line"><a id="l01770" name="l01770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga337e83ffa1ec72fe00ab4b9c889a5acd"> 1770</a></span><span class="preprocessor">#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) </span></div>
|
||
<div class="line"><a id="l01771" name="l01771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a94c410343ba459146b2bb17833a795"> 1771</a></span><span class="preprocessor">#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk </span></div>
|
||
<div class="line"><a id="l01772" name="l01772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d7e8c14892467a1d198b169c3c0bb78"> 1772</a></span><span class="preprocessor">#define ADC_CSR_JEOC3_Pos (18U) </span></div>
|
||
<div class="line"><a id="l01773" name="l01773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48e83374e0184b6a6ba6f3216d0d2ecc"> 1773</a></span><span class="preprocessor">#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos) </span></div>
|
||
<div class="line"><a id="l01774" name="l01774"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7d3c36f449ef1ee9ee20c5686b4e974"> 1774</a></span><span class="preprocessor">#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk </span></div>
|
||
<div class="line"><a id="l01775" name="l01775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e64575250e915936cf02785b3068c95"> 1775</a></span><span class="preprocessor">#define ADC_CSR_JSTRT3_Pos (19U) </span></div>
|
||
<div class="line"><a id="l01776" name="l01776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa137f40aeea09749a280b436c560a8e6"> 1776</a></span><span class="preprocessor">#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos) </span></div>
|
||
<div class="line"><a id="l01777" name="l01777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94140d21b4c83d9f401cc459a7ec6060"> 1777</a></span><span class="preprocessor">#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk </span></div>
|
||
<div class="line"><a id="l01778" name="l01778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f2699ef95e89fb1803e46d4670ce1f2"> 1778</a></span><span class="preprocessor">#define ADC_CSR_STRT3_Pos (20U) </span></div>
|
||
<div class="line"><a id="l01779" name="l01779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga774dbbb3929e4d525c6fce448459a711"> 1779</a></span><span class="preprocessor">#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos) </span></div>
|
||
<div class="line"><a id="l01780" name="l01780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13ca665cc575b64588475723f5289d4a"> 1780</a></span><span class="preprocessor">#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk </span></div>
|
||
<div class="line"><a id="l01781" name="l01781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab46fd70aefec77d01f6fba4d19d677b6"> 1781</a></span><span class="preprocessor">#define ADC_CSR_OVR3_Pos (21U) </span></div>
|
||
<div class="line"><a id="l01782" name="l01782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef6f4ccc5a845954e07699858b868c9b"> 1782</a></span><span class="preprocessor">#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos) </span></div>
|
||
<div class="line"><a id="l01783" name="l01783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab76495b35a2bc7fc5f1b51ab1ee92384"> 1783</a></span><span class="preprocessor">#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk </span></div>
|
||
<div class="line"><a id="l01785" name="l01785"></a><span class="lineno"> 1785</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l01786" name="l01786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga321ed2ccdf98d3a3307947056a8c401a"> 1786</a></span><span class="preprocessor">#define ADC_CSR_DOVR1 ADC_CSR_OVR1</span></div>
|
||
<div class="line"><a id="l01787" name="l01787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00e2a30df5568b5663e9f016743b3a35"> 1787</a></span><span class="preprocessor">#define ADC_CSR_DOVR2 ADC_CSR_OVR2</span></div>
|
||
<div class="line"><a id="l01788" name="l01788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga396513974cf26f2a4aa0f36e755e227c"> 1788</a></span><span class="preprocessor">#define ADC_CSR_DOVR3 ADC_CSR_OVR3</span></div>
|
||
<div class="line"><a id="l01789" name="l01789"></a><span class="lineno"> 1789</span> </div>
|
||
<div class="line"><a id="l01790" name="l01790"></a><span class="lineno"> 1790</span><span class="comment">/******************* Bit definition for ADC_CCR register ********************/</span></div>
|
||
<div class="line"><a id="l01791" name="l01791"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f9e95bcdc01cb070e8b42441839b517"> 1791</a></span><span class="preprocessor">#define ADC_CCR_MULTI_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01792" name="l01792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga535eaa79d3a77403b2e0981641f10f81"> 1792</a></span><span class="preprocessor">#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos) </span></div>
|
||
<div class="line"><a id="l01793" name="l01793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf70ab04667c7c7da0f29c0e5a6c48e68"> 1793</a></span><span class="preprocessor">#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk </span></div>
|
||
<div class="line"><a id="l01794" name="l01794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4e7104ce01e3a79b8f6138d87dc3684"> 1794</a></span><span class="preprocessor">#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos) </span></div>
|
||
<div class="line"><a id="l01795" name="l01795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8781dec7f076b475b85f8470aee94d06"> 1795</a></span><span class="preprocessor">#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos) </span></div>
|
||
<div class="line"><a id="l01796" name="l01796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6a5be6cff1227431b8d54dffcc1ce88"> 1796</a></span><span class="preprocessor">#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos) </span></div>
|
||
<div class="line"><a id="l01797" name="l01797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae55be7b911b4c0272543f98a0dba5f20"> 1797</a></span><span class="preprocessor">#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos) </span></div>
|
||
<div class="line"><a id="l01798" name="l01798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5087b3cb0d4570b80b3138c277bcbf6c"> 1798</a></span><span class="preprocessor">#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos) </span></div>
|
||
<div class="line"><a id="l01799" name="l01799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga702c581a6341f08b3198cd41b0cb69a3"> 1799</a></span><span class="preprocessor">#define ADC_CCR_DELAY_Pos (8U) </span></div>
|
||
<div class="line"><a id="l01800" name="l01800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c1c63139684661c857ece4937a72415"> 1800</a></span><span class="preprocessor">#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) </span></div>
|
||
<div class="line"><a id="l01801" name="l01801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c13aa04949ed520cf92613d3a619198"> 1801</a></span><span class="preprocessor">#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk </span></div>
|
||
<div class="line"><a id="l01802" name="l01802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22b71e9df8b1fca93802ad602341eb0b"> 1802</a></span><span class="preprocessor">#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) </span></div>
|
||
<div class="line"><a id="l01803" name="l01803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d0d5785cb6c75e700517e88af188573"> 1803</a></span><span class="preprocessor">#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) </span></div>
|
||
<div class="line"><a id="l01804" name="l01804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17f85cbda5dcf9a392a29befb73c6ceb"> 1804</a></span><span class="preprocessor">#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) </span></div>
|
||
<div class="line"><a id="l01805" name="l01805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0216de7d6fcfa507c9aa1400972d862"> 1805</a></span><span class="preprocessor">#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) </span></div>
|
||
<div class="line"><a id="l01806" name="l01806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27c6d297e452d728c075a6f9b953d0a5"> 1806</a></span><span class="preprocessor">#define ADC_CCR_DDS_Pos (13U) </span></div>
|
||
<div class="line"><a id="l01807" name="l01807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad41720d885d32a33cb04782a2a2a74f9"> 1807</a></span><span class="preprocessor">#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos) </span></div>
|
||
<div class="line"><a id="l01808" name="l01808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e745513bbc2e5e5a76ae999d5d535af"> 1808</a></span><span class="preprocessor">#define ADC_CCR_DDS ADC_CCR_DDS_Msk </span></div>
|
||
<div class="line"><a id="l01809" name="l01809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cdf117dd6f678b5d2121253b4e452c6"> 1809</a></span><span class="preprocessor">#define ADC_CCR_DMA_Pos (14U) </span></div>
|
||
<div class="line"><a id="l01810" name="l01810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7933afb88d395724816248ec8fa9b76"> 1810</a></span><span class="preprocessor">#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos) </span></div>
|
||
<div class="line"><a id="l01811" name="l01811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e346b21afcaeced784e6c80b3aa1fb4"> 1811</a></span><span class="preprocessor">#define ADC_CCR_DMA ADC_CCR_DMA_Msk </span></div>
|
||
<div class="line"><a id="l01812" name="l01812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a42ee6ec5115244aef8f60d35abcc47"> 1812</a></span><span class="preprocessor">#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos) </span></div>
|
||
<div class="line"><a id="l01813" name="l01813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdc9d29cafdd54e5c0dd752c358e1bc8"> 1813</a></span><span class="preprocessor">#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos) </span></div>
|
||
<div class="line"><a id="l01814" name="l01814"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafceea99dc2287c360b275732f9862bca"> 1814</a></span><span class="preprocessor">#define ADC_CCR_ADCPRE_Pos (16U) </span></div>
|
||
<div class="line"><a id="l01815" name="l01815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2458ab94917987a44a275e1ed886e825"> 1815</a></span><span class="preprocessor">#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) </span></div>
|
||
<div class="line"><a id="l01816" name="l01816"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a2ee019aef4c64fffc72141f7aaab2c"> 1816</a></span><span class="preprocessor">#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk </span></div>
|
||
<div class="line"><a id="l01817" name="l01817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3108cc8fb81f6efd1e93fa5f82ac313"> 1817</a></span><span class="preprocessor">#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) </span></div>
|
||
<div class="line"><a id="l01818" name="l01818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa090830d2d359db04f365d46c6644d5"> 1818</a></span><span class="preprocessor">#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) </span></div>
|
||
<div class="line"><a id="l01819" name="l01819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ece9c9847db39ff9782d07ed5104bbf"> 1819</a></span><span class="preprocessor">#define ADC_CCR_VBATE_Pos (22U) </span></div>
|
||
<div class="line"><a id="l01820" name="l01820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3d86d837c7c40d14882728116a3722b"> 1820</a></span><span class="preprocessor">#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos) </span></div>
|
||
<div class="line"><a id="l01821" name="l01821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga519645e42dcf6b19af9c05dc40300abb"> 1821</a></span><span class="preprocessor">#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk </span></div>
|
||
<div class="line"><a id="l01822" name="l01822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9741df391649af046f8310352ca3b3be"> 1822</a></span><span class="preprocessor">#define ADC_CCR_TSVREFE_Pos (23U) </span></div>
|
||
<div class="line"><a id="l01823" name="l01823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e1a3df0d33a0c78197ad8c161c22a7a"> 1823</a></span><span class="preprocessor">#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) </span></div>
|
||
<div class="line"><a id="l01824" name="l01824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc020d85a8740491ce3f218a0706f1dc"> 1824</a></span><span class="preprocessor">#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk </span></div>
|
||
<div class="line"><a id="l01826" name="l01826"></a><span class="lineno"> 1826</span><span class="comment">/******************* Bit definition for ADC_CDR register ********************/</span></div>
|
||
<div class="line"><a id="l01827" name="l01827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa14929dd3fe8ae466d2ad41c395ca2c1"> 1827</a></span><span class="preprocessor">#define ADC_CDR_DATA1_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01828" name="l01828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb4c80caea7b29ec5b2b863e84288cf1"> 1828</a></span><span class="preprocessor">#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos) </span></div>
|
||
<div class="line"><a id="l01829" name="l01829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d7a0a18c77816c45c5682c3884e3d56"> 1829</a></span><span class="preprocessor">#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk </span></div>
|
||
<div class="line"><a id="l01830" name="l01830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab562b2adbf577b621d81758fa806e5fc"> 1830</a></span><span class="preprocessor">#define ADC_CDR_DATA2_Pos (16U) </span></div>
|
||
<div class="line"><a id="l01831" name="l01831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e8ac90ba8958b4d858c24e2896f7733"> 1831</a></span><span class="preprocessor">#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos) </span></div>
|
||
<div class="line"><a id="l01832" name="l01832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55f0776b9bf2612c194c1ab478d8a371"> 1832</a></span><span class="preprocessor">#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk </span></div>
|
||
<div class="line"><a id="l01834" name="l01834"></a><span class="lineno"> 1834</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l01835" name="l01835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga588fd6c0f172ca0e7683bb54034564fe"> 1835</a></span><span class="preprocessor">#define ADC_CDR_RDATA_MST ADC_CDR_DATA1</span></div>
|
||
<div class="line"><a id="l01836" name="l01836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad582026e4b62991d8281b51494902a33"> 1836</a></span><span class="preprocessor">#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2</span></div>
|
||
<div class="line"><a id="l01837" name="l01837"></a><span class="lineno"> 1837</span> </div>
|
||
<div class="line"><a id="l01838" name="l01838"></a><span class="lineno"> 1838</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l01839" name="l01839"></a><span class="lineno"> 1839</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l01840" name="l01840"></a><span class="lineno"> 1840</span><span class="comment">/* Controller Area Network */</span></div>
|
||
<div class="line"><a id="l01841" name="l01841"></a><span class="lineno"> 1841</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l01842" name="l01842"></a><span class="lineno"> 1842</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l01844" name="l01844"></a><span class="lineno"> 1844</span><span class="comment">/******************* Bit definition for CAN_MCR register ********************/</span></div>
|
||
<div class="line"><a id="l01845" name="l01845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bcdd01eb82046959b22b3d254073c22"> 1845</a></span><span class="preprocessor">#define CAN_MCR_INRQ_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01846" name="l01846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7afc4335014982a4cfac31de0cdbebc"> 1846</a></span><span class="preprocessor">#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) </span></div>
|
||
<div class="line"><a id="l01847" name="l01847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cf12be5661908dbe38aa14cd4c3a356"> 1847</a></span><span class="preprocessor">#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk </span></div>
|
||
<div class="line"><a id="l01848" name="l01848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60009c948dbdf525fb2fc932d988c245"> 1848</a></span><span class="preprocessor">#define CAN_MCR_SLEEP_Pos (1U) </span></div>
|
||
<div class="line"><a id="l01849" name="l01849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4181676e5d50d29f09805be441efc9b"> 1849</a></span><span class="preprocessor">#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) </span></div>
|
||
<div class="line"><a id="l01850" name="l01850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf9602dfb2f95b481b6e642b95991176"> 1850</a></span><span class="preprocessor">#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk </span></div>
|
||
<div class="line"><a id="l01851" name="l01851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80233affcdda60458e98647fe1416f85"> 1851</a></span><span class="preprocessor">#define CAN_MCR_TXFP_Pos (2U) </span></div>
|
||
<div class="line"><a id="l01852" name="l01852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc1c0efc56b72fa75b6e25d773ada7d2"> 1852</a></span><span class="preprocessor">#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) </span></div>
|
||
<div class="line"><a id="l01853" name="l01853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35e7e66f9cd8cb6efa6a80367d2294a9"> 1853</a></span><span class="preprocessor">#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk </span></div>
|
||
<div class="line"><a id="l01854" name="l01854"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf728107056b7bc1dbab277967ad255bc"> 1854</a></span><span class="preprocessor">#define CAN_MCR_RFLM_Pos (3U) </span></div>
|
||
<div class="line"><a id="l01855" name="l01855"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ff5789ccbdf18976ec76ab44cd798e0"> 1855</a></span><span class="preprocessor">#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) </span></div>
|
||
<div class="line"><a id="l01856" name="l01856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga501125ff257a7d02c35a0d6dcbaa2ba8"> 1856</a></span><span class="preprocessor">#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk </span></div>
|
||
<div class="line"><a id="l01857" name="l01857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa15d8c6ceddacbfdcfe732d9bcb0cd50"> 1857</a></span><span class="preprocessor">#define CAN_MCR_NART_Pos (4U) </span></div>
|
||
<div class="line"><a id="l01858" name="l01858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f03d5006b20e144bec0f3739345bc60"> 1858</a></span><span class="preprocessor">#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) </span></div>
|
||
<div class="line"><a id="l01859" name="l01859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2774f04e286942d36a5b6135c8028049"> 1859</a></span><span class="preprocessor">#define CAN_MCR_NART CAN_MCR_NART_Msk </span></div>
|
||
<div class="line"><a id="l01860" name="l01860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga191178a51ef5243b2ecf547aeb1d5eb9"> 1860</a></span><span class="preprocessor">#define CAN_MCR_AWUM_Pos (5U) </span></div>
|
||
<div class="line"><a id="l01861" name="l01861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a62120fa01d4bb366f02555ddd6a0d4"> 1861</a></span><span class="preprocessor">#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) </span></div>
|
||
<div class="line"><a id="l01862" name="l01862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2745f1a565c3f2ec5b16612d1fd66e0"> 1862</a></span><span class="preprocessor">#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk </span></div>
|
||
<div class="line"><a id="l01863" name="l01863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cc28c00c9766a53c2ba8c0d42feba92"> 1863</a></span><span class="preprocessor">#define CAN_MCR_ABOM_Pos (6U) </span></div>
|
||
<div class="line"><a id="l01864" name="l01864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb5d923de1437f1c441b540c74c6ebd9"> 1864</a></span><span class="preprocessor">#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) </span></div>
|
||
<div class="line"><a id="l01865" name="l01865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7aff5c0a3ead7f937849ab66eba7490"> 1865</a></span><span class="preprocessor">#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk </span></div>
|
||
<div class="line"><a id="l01866" name="l01866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16b15e96f1e4a0203c3974949c2e54a2"> 1866</a></span><span class="preprocessor">#define CAN_MCR_TTCM_Pos (7U) </span></div>
|
||
<div class="line"><a id="l01867" name="l01867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a53a37c946b05dbafc5b7392d5163a3"> 1867</a></span><span class="preprocessor">#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) </span></div>
|
||
<div class="line"><a id="l01868" name="l01868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32b2eda9cad8a969c5d2349bd1d853bb"> 1868</a></span><span class="preprocessor">#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk </span></div>
|
||
<div class="line"><a id="l01869" name="l01869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21598a34f72464c29fccedd71b51d519"> 1869</a></span><span class="preprocessor">#define CAN_MCR_RESET_Pos (15U) </span></div>
|
||
<div class="line"><a id="l01870" name="l01870"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa6c92ebbf496383e92f30301169b1b7"> 1870</a></span><span class="preprocessor">#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) </span></div>
|
||
<div class="line"><a id="l01871" name="l01871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga410fdbad37a9dbda508b8c437277e79f"> 1871</a></span><span class="preprocessor">#define CAN_MCR_RESET CAN_MCR_RESET_Msk </span></div>
|
||
<div class="line"><a id="l01872" name="l01872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa32526e641ef7eed19b3b8db98befbd4"> 1872</a></span><span class="preprocessor">#define CAN_MCR_DBF_Pos (16U) </span></div>
|
||
<div class="line"><a id="l01873" name="l01873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7284f1c36b5a1422050a8204ff673557"> 1873</a></span><span class="preprocessor">#define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos) </span></div>
|
||
<div class="line"><a id="l01874" name="l01874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf74445921cdd9df3e44b6b9ba8f67491"> 1874</a></span><span class="preprocessor">#define CAN_MCR_DBF CAN_MCR_DBF_Msk </span></div>
|
||
<div class="line"><a id="l01875" name="l01875"></a><span class="lineno"> 1875</span><span class="comment">/******************* Bit definition for CAN_MSR register ********************/</span></div>
|
||
<div class="line"><a id="l01876" name="l01876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2a392cb8353ef23ff078a068ad8cdf9"> 1876</a></span><span class="preprocessor">#define CAN_MSR_INAK_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01877" name="l01877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac65998a2ace7015bb67d9a4a64e4fba5"> 1877</a></span><span class="preprocessor">#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) </span></div>
|
||
<div class="line"><a id="l01878" name="l01878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2871cee90ebecb760bab16e9c039b682"> 1878</a></span><span class="preprocessor">#define CAN_MSR_INAK CAN_MSR_INAK_Msk </span></div>
|
||
<div class="line"><a id="l01879" name="l01879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac27c0590f11b2b5fb894a60a9700567c"> 1879</a></span><span class="preprocessor">#define CAN_MSR_SLAK_Pos (1U) </span></div>
|
||
<div class="line"><a id="l01880" name="l01880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81eeee3e575f4bd0cf494ad946b11a90"> 1880</a></span><span class="preprocessor">#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) </span></div>
|
||
<div class="line"><a id="l01881" name="l01881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1611badb362f0fd9047af965509f074"> 1881</a></span><span class="preprocessor">#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk </span></div>
|
||
<div class="line"><a id="l01882" name="l01882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ff8b9d234d0cd377443d4cc21ccd663"> 1882</a></span><span class="preprocessor">#define CAN_MSR_ERRI_Pos (2U) </span></div>
|
||
<div class="line"><a id="l01883" name="l01883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a189bb7f091383b4cbc858f14cf1dbc"> 1883</a></span><span class="preprocessor">#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) </span></div>
|
||
<div class="line"><a id="l01884" name="l01884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c424768e9e963402f37cb95ae87a1ae"> 1884</a></span><span class="preprocessor">#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk </span></div>
|
||
<div class="line"><a id="l01885" name="l01885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga953a3a5616c5bff5392ff196772915d7"> 1885</a></span><span class="preprocessor">#define CAN_MSR_WKUI_Pos (3U) </span></div>
|
||
<div class="line"><a id="l01886" name="l01886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad3ddd5d76a1f1e9af5926464efff245"> 1886</a></span><span class="preprocessor">#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) </span></div>
|
||
<div class="line"><a id="l01887" name="l01887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f4c753b96d21c5001b39ad5b08519fc"> 1887</a></span><span class="preprocessor">#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk </span></div>
|
||
<div class="line"><a id="l01888" name="l01888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5030b442fd7a20eb18897625d8d68078"> 1888</a></span><span class="preprocessor">#define CAN_MSR_SLAKI_Pos (4U) </span></div>
|
||
<div class="line"><a id="l01889" name="l01889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5373a083dae43a5491e9bc91d9478dd5"> 1889</a></span><span class="preprocessor">#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) </span></div>
|
||
<div class="line"><a id="l01890" name="l01890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47ab62ae123c791de27ad05dde5bee91"> 1890</a></span><span class="preprocessor">#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk </span></div>
|
||
<div class="line"><a id="l01891" name="l01891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3d01c4e4a870b78aca2a679d1936095"> 1891</a></span><span class="preprocessor">#define CAN_MSR_TXM_Pos (8U) </span></div>
|
||
<div class="line"><a id="l01892" name="l01892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ef1d9966b0022bbbeef87229714ec59"> 1892</a></span><span class="preprocessor">#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) </span></div>
|
||
<div class="line"><a id="l01893" name="l01893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga651580d35b658e90ea831cb13b8a8988"> 1893</a></span><span class="preprocessor">#define CAN_MSR_TXM CAN_MSR_TXM_Msk </span></div>
|
||
<div class="line"><a id="l01894" name="l01894"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e954c04ec46d198ac7e9b88f46e9a93"> 1894</a></span><span class="preprocessor">#define CAN_MSR_RXM_Pos (9U) </span></div>
|
||
<div class="line"><a id="l01895" name="l01895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8eec1fe9e0ab8545330e597a28d9035d"> 1895</a></span><span class="preprocessor">#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) </span></div>
|
||
<div class="line"><a id="l01896" name="l01896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67f8e1140b0304930d5b4f2a041a7884"> 1896</a></span><span class="preprocessor">#define CAN_MSR_RXM CAN_MSR_RXM_Msk </span></div>
|
||
<div class="line"><a id="l01897" name="l01897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7ede877266831078649ab791547ba3e"> 1897</a></span><span class="preprocessor">#define CAN_MSR_SAMP_Pos (10U) </span></div>
|
||
<div class="line"><a id="l01898" name="l01898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga092ef8e336f9e5bf5121d0a5c28606cb"> 1898</a></span><span class="preprocessor">#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) </span></div>
|
||
<div class="line"><a id="l01899" name="l01899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf68038824bb78c4a5c4dee1730848f69"> 1899</a></span><span class="preprocessor">#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk </span></div>
|
||
<div class="line"><a id="l01900" name="l01900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef4c2abade47710dcb184a0f406eaf85"> 1900</a></span><span class="preprocessor">#define CAN_MSR_RX_Pos (11U) </span></div>
|
||
<div class="line"><a id="l01901" name="l01901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga453cbc8d18bbadf9be9ec9b7987f1dc4"> 1901</a></span><span class="preprocessor">#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) </span></div>
|
||
<div class="line"><a id="l01902" name="l01902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6564a1d2f23f246053188a454264eb4b"> 1902</a></span><span class="preprocessor">#define CAN_MSR_RX CAN_MSR_RX_Msk </span></div>
|
||
<div class="line"><a id="l01904" name="l01904"></a><span class="lineno"> 1904</span><span class="comment">/******************* Bit definition for CAN_TSR register ********************/</span></div>
|
||
<div class="line"><a id="l01905" name="l01905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab31d05fd93767905fa9bde4b5d6143d4"> 1905</a></span><span class="preprocessor">#define CAN_TSR_RQCP0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01906" name="l01906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d71df41ef791745448cbd0aaaad6e38"> 1906</a></span><span class="preprocessor">#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) </span></div>
|
||
<div class="line"><a id="l01907" name="l01907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a4809b8908618df57e6393cc7fe0f52"> 1907</a></span><span class="preprocessor">#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk </span></div>
|
||
<div class="line"><a id="l01908" name="l01908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83553d6d8a8baa6d29b9df2e97689281"> 1908</a></span><span class="preprocessor">#define CAN_TSR_TXOK0_Pos (1U) </span></div>
|
||
<div class="line"><a id="l01909" name="l01909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13bd0e217ec398f9ac7c605b03eaa566"> 1909</a></span><span class="preprocessor">#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) </span></div>
|
||
<div class="line"><a id="l01910" name="l01910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacedb237b31d29aef7f38475e9a6b297"> 1910</a></span><span class="preprocessor">#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk </span></div>
|
||
<div class="line"><a id="l01911" name="l01911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91b96c96a75628fa3b50f792e68b2b27"> 1911</a></span><span class="preprocessor">#define CAN_TSR_ALST0_Pos (2U) </span></div>
|
||
<div class="line"><a id="l01912" name="l01912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d2ee6ceab2eab0f30a108d406855c7e"> 1912</a></span><span class="preprocessor">#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) </span></div>
|
||
<div class="line"><a id="l01913" name="l01913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b94ea5001d70a26ec32d9dc6ff76e47"> 1913</a></span><span class="preprocessor">#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk </span></div>
|
||
<div class="line"><a id="l01914" name="l01914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52966440e5d87a89726c19d62645a27c"> 1914</a></span><span class="preprocessor">#define CAN_TSR_TERR0_Pos (3U) </span></div>
|
||
<div class="line"><a id="l01915" name="l01915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58999cde45dd10f2f351be5cc8ec1a8b"> 1915</a></span><span class="preprocessor">#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) </span></div>
|
||
<div class="line"><a id="l01916" name="l01916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga805d2dab5b1d4618492b1cf2a3f5e1e0"> 1916</a></span><span class="preprocessor">#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk </span></div>
|
||
<div class="line"><a id="l01917" name="l01917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56679e8aea1650e19f2baf79b35be24f"> 1917</a></span><span class="preprocessor">#define CAN_TSR_ABRQ0_Pos (7U) </span></div>
|
||
<div class="line"><a id="l01918" name="l01918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa78f950ccfd5a5a906c03de00a311047"> 1918</a></span><span class="preprocessor">#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) </span></div>
|
||
<div class="line"><a id="l01919" name="l01919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdac6b87a303b0d0ec9b0d94a54ae31f"> 1919</a></span><span class="preprocessor">#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk </span></div>
|
||
<div class="line"><a id="l01920" name="l01920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd31c6bc75f595b504cc521280752259"> 1920</a></span><span class="preprocessor">#define CAN_TSR_RQCP1_Pos (8U) </span></div>
|
||
<div class="line"><a id="l01921" name="l01921"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27fdee112d3e6e2b5f6bad6c9d95cb2b"> 1921</a></span><span class="preprocessor">#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) </span></div>
|
||
<div class="line"><a id="l01922" name="l01922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd3118dec59c3a45d2f262b090699538"> 1922</a></span><span class="preprocessor">#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk </span></div>
|
||
<div class="line"><a id="l01923" name="l01923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabf7c2bb1371409780b6aa677d30505d"> 1923</a></span><span class="preprocessor">#define CAN_TSR_TXOK1_Pos (9U) </span></div>
|
||
<div class="line"><a id="l01924" name="l01924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d08d43b83ebfa8f93c1ac842ccb1e31"> 1924</a></span><span class="preprocessor">#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) </span></div>
|
||
<div class="line"><a id="l01925" name="l01925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea918e510c5471b1ac797350b7950151"> 1925</a></span><span class="preprocessor">#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk </span></div>
|
||
<div class="line"><a id="l01926" name="l01926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3647d7d831be09723b38baaf9011fe0"> 1926</a></span><span class="preprocessor">#define CAN_TSR_ALST1_Pos (10U) </span></div>
|
||
<div class="line"><a id="l01927" name="l01927"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ffcef1919cf06d2874bff8879d69c23"> 1927</a></span><span class="preprocessor">#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) </span></div>
|
||
<div class="line"><a id="l01928" name="l01928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a34d996177f23148c9b4cd6b0a80529"> 1928</a></span><span class="preprocessor">#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk </span></div>
|
||
<div class="line"><a id="l01929" name="l01929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c91415cb60af76367c9c03ddb9d1791"> 1929</a></span><span class="preprocessor">#define CAN_TSR_TERR1_Pos (11U) </span></div>
|
||
<div class="line"><a id="l01930" name="l01930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5cd5d4653c34defa63b29c42292358dd"> 1930</a></span><span class="preprocessor">#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) </span></div>
|
||
<div class="line"><a id="l01931" name="l01931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b01eca562bdb60e5416840fca47fff6"> 1931</a></span><span class="preprocessor">#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk </span></div>
|
||
<div class="line"><a id="l01932" name="l01932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2254de573340c2b341cecb12bb6ead4e"> 1932</a></span><span class="preprocessor">#define CAN_TSR_ABRQ1_Pos (15U) </span></div>
|
||
<div class="line"><a id="l01933" name="l01933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadca8d9c91c9b53a361a07cea552fe847"> 1933</a></span><span class="preprocessor">#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) </span></div>
|
||
<div class="line"><a id="l01934" name="l01934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c44a4e585b3ab1c37a6c2c28c90d6cd"> 1934</a></span><span class="preprocessor">#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk </span></div>
|
||
<div class="line"><a id="l01935" name="l01935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac32ff69b06375749e0a00c17c010f1fe"> 1935</a></span><span class="preprocessor">#define CAN_TSR_RQCP2_Pos (16U) </span></div>
|
||
<div class="line"><a id="l01936" name="l01936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8137af39f29d789c1794527149da1e70"> 1936</a></span><span class="preprocessor">#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) </span></div>
|
||
<div class="line"><a id="l01937" name="l01937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cf9e83cec96164f1dadf4e43411ebf0"> 1937</a></span><span class="preprocessor">#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk </span></div>
|
||
<div class="line"><a id="l01938" name="l01938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c1c09375222011c0dba1bdb1cf56fd2"> 1938</a></span><span class="preprocessor">#define CAN_TSR_TXOK2_Pos (17U) </span></div>
|
||
<div class="line"><a id="l01939" name="l01939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab26c50058879d92619cbc4bef2e9d492"> 1939</a></span><span class="preprocessor">#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) </span></div>
|
||
<div class="line"><a id="l01940" name="l01940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga782c591bb204d751b470dd53a37d240e"> 1940</a></span><span class="preprocessor">#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk </span></div>
|
||
<div class="line"><a id="l01941" name="l01941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga435fe7e72dd93d43d2a3f1bd89a89c44"> 1941</a></span><span class="preprocessor">#define CAN_TSR_ALST2_Pos (18U) </span></div>
|
||
<div class="line"><a id="l01942" name="l01942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5a24da79f81578dafc2126d5f731d4a"> 1942</a></span><span class="preprocessor">#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) </span></div>
|
||
<div class="line"><a id="l01943" name="l01943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75db1172038ebd72db1ed2fedc6108ff"> 1943</a></span><span class="preprocessor">#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk </span></div>
|
||
<div class="line"><a id="l01944" name="l01944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99b204977a683ed30b391720352e3260"> 1944</a></span><span class="preprocessor">#define CAN_TSR_TERR2_Pos (19U) </span></div>
|
||
<div class="line"><a id="l01945" name="l01945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd1cf1551625e3972c4942983a394acc"> 1945</a></span><span class="preprocessor">#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) </span></div>
|
||
<div class="line"><a id="l01946" name="l01946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26a85626eb26bf99413ba80c676d0af8"> 1946</a></span><span class="preprocessor">#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk </span></div>
|
||
<div class="line"><a id="l01947" name="l01947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ad0f8e1da30d1f2b0c6713ae0cc2793"> 1947</a></span><span class="preprocessor">#define CAN_TSR_ABRQ2_Pos (23U) </span></div>
|
||
<div class="line"><a id="l01948" name="l01948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafba8518081068f7375284a1e07873417"> 1948</a></span><span class="preprocessor">#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) </span></div>
|
||
<div class="line"><a id="l01949" name="l01949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a3b7e4be7cebb35ad66cb85b82901bb"> 1949</a></span><span class="preprocessor">#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk </span></div>
|
||
<div class="line"><a id="l01950" name="l01950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca63bcf7a21cf13d7fcd42d49ee2a59f"> 1950</a></span><span class="preprocessor">#define CAN_TSR_CODE_Pos (24U) </span></div>
|
||
<div class="line"><a id="l01951" name="l01951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13f9f007576f8a12578052bdbd224681"> 1951</a></span><span class="preprocessor">#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) </span></div>
|
||
<div class="line"><a id="l01952" name="l01952"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac00145ea43822f362f3d473bba62fa13"> 1952</a></span><span class="preprocessor">#define CAN_TSR_CODE CAN_TSR_CODE_Msk </span></div>
|
||
<div class="line"><a id="l01954" name="l01954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4348cbdeed004189582a35db2ff12d74"> 1954</a></span><span class="preprocessor">#define CAN_TSR_TME_Pos (26U) </span></div>
|
||
<div class="line"><a id="l01955" name="l01955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga635aef2e8090ae256c1251a3a1736965"> 1955</a></span><span class="preprocessor">#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) </span></div>
|
||
<div class="line"><a id="l01956" name="l01956"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61ab11e97b42c5210109516e30af9b05"> 1956</a></span><span class="preprocessor">#define CAN_TSR_TME CAN_TSR_TME_Msk </span></div>
|
||
<div class="line"><a id="l01957" name="l01957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37b566e4628d2f032e393c1b86748f2c"> 1957</a></span><span class="preprocessor">#define CAN_TSR_TME0_Pos (26U) </span></div>
|
||
<div class="line"><a id="l01958" name="l01958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga440056199033e966155a795be606acdc"> 1958</a></span><span class="preprocessor">#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) </span></div>
|
||
<div class="line"><a id="l01959" name="l01959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7500e491fe82e67ed5d40759e8a50f0"> 1959</a></span><span class="preprocessor">#define CAN_TSR_TME0 CAN_TSR_TME0_Msk </span></div>
|
||
<div class="line"><a id="l01960" name="l01960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad799e75ed3dad61e73e34781df0f87f2"> 1960</a></span><span class="preprocessor">#define CAN_TSR_TME1_Pos (27U) </span></div>
|
||
<div class="line"><a id="l01961" name="l01961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39fa95bef47ce6b3631b924d25556454"> 1961</a></span><span class="preprocessor">#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) </span></div>
|
||
<div class="line"><a id="l01962" name="l01962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ba2b51def4b1683fd050e43045306ea"> 1962</a></span><span class="preprocessor">#define CAN_TSR_TME1 CAN_TSR_TME1_Msk </span></div>
|
||
<div class="line"><a id="l01963" name="l01963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1884d523a48ffedf27bb137b34ac6c78"> 1963</a></span><span class="preprocessor">#define CAN_TSR_TME2_Pos (28U) </span></div>
|
||
<div class="line"><a id="l01964" name="l01964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4977ccde238489d3291b2fe91434c713"> 1964</a></span><span class="preprocessor">#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) </span></div>
|
||
<div class="line"><a id="l01965" name="l01965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6523fac51d3aed2e36de4c2f07c2a21"> 1965</a></span><span class="preprocessor">#define CAN_TSR_TME2 CAN_TSR_TME2_Msk </span></div>
|
||
<div class="line"><a id="l01967" name="l01967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga702291f34c1368501b753d7af3d553fe"> 1967</a></span><span class="preprocessor">#define CAN_TSR_LOW_Pos (29U) </span></div>
|
||
<div class="line"><a id="l01968" name="l01968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd34530d99bc8ff61a5e6ce04caf7d67"> 1968</a></span><span class="preprocessor">#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) </span></div>
|
||
<div class="line"><a id="l01969" name="l01969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96c6453caa447cc4a9961d6ee5dea74e"> 1969</a></span><span class="preprocessor">#define CAN_TSR_LOW CAN_TSR_LOW_Msk </span></div>
|
||
<div class="line"><a id="l01970" name="l01970"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca4490d8d7d5ccfdf3200cf4be7d6641"> 1970</a></span><span class="preprocessor">#define CAN_TSR_LOW0_Pos (29U) </span></div>
|
||
<div class="line"><a id="l01971" name="l01971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ae04ec8ef32d4f5aa583628114cb54e"> 1971</a></span><span class="preprocessor">#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) </span></div>
|
||
<div class="line"><a id="l01972" name="l01972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79ff582efea1d7be2d1de7a1fd1a2b65"> 1972</a></span><span class="preprocessor">#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk </span></div>
|
||
<div class="line"><a id="l01973" name="l01973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cb85fb2c45304df1a329b7d2320c511"> 1973</a></span><span class="preprocessor">#define CAN_TSR_LOW1_Pos (30U) </span></div>
|
||
<div class="line"><a id="l01974" name="l01974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b5f0c70b09a3395c07d6b2287210b7d"> 1974</a></span><span class="preprocessor">#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) </span></div>
|
||
<div class="line"><a id="l01975" name="l01975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1e550c2e6a5f8425322f9943fd7c7ed"> 1975</a></span><span class="preprocessor">#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk </span></div>
|
||
<div class="line"><a id="l01976" name="l01976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa822557268b20255c2be98727a357202"> 1976</a></span><span class="preprocessor">#define CAN_TSR_LOW2_Pos (31U) </span></div>
|
||
<div class="line"><a id="l01977" name="l01977"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga987f19b94125300653186bb50bb43ca6"> 1977</a></span><span class="preprocessor">#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) </span></div>
|
||
<div class="line"><a id="l01978" name="l01978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd1db2c2ce76b732fdb71df65fb8124f"> 1978</a></span><span class="preprocessor">#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk </span></div>
|
||
<div class="line"><a id="l01980" name="l01980"></a><span class="lineno"> 1980</span><span class="comment">/******************* Bit definition for CAN_RF0R register *******************/</span></div>
|
||
<div class="line"><a id="l01981" name="l01981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab868d2c9f9b9e52d7d3b3e8227b8e862"> 1981</a></span><span class="preprocessor">#define CAN_RF0R_FMP0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01982" name="l01982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad74fc3f4e266805779daf7f69194bd97"> 1982</a></span><span class="preprocessor">#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) </span></div>
|
||
<div class="line"><a id="l01983" name="l01983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e23f3d7947e58531524d77b5c4741cc"> 1983</a></span><span class="preprocessor">#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk </span></div>
|
||
<div class="line"><a id="l01984" name="l01984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab168d7bfdd89ac5e7654804ff6c16d3"> 1984</a></span><span class="preprocessor">#define CAN_RF0R_FULL0_Pos (3U) </span></div>
|
||
<div class="line"><a id="l01985" name="l01985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27305e8a2d6f381b6d0ff05d6d0c74ba"> 1985</a></span><span class="preprocessor">#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) </span></div>
|
||
<div class="line"><a id="l01986" name="l01986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae934674f6e22a758e430f32cfc386d70"> 1986</a></span><span class="preprocessor">#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk </span></div>
|
||
<div class="line"><a id="l01987" name="l01987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0aad54077e9896ec6f7599d126e54e1"> 1987</a></span><span class="preprocessor">#define CAN_RF0R_FOVR0_Pos (4U) </span></div>
|
||
<div class="line"><a id="l01988" name="l01988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0699f23293ca0bc417c7c1a343f53ba"> 1988</a></span><span class="preprocessor">#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) </span></div>
|
||
<div class="line"><a id="l01989" name="l01989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a3d15b3abab8199c16e26a3dffdc8b8"> 1989</a></span><span class="preprocessor">#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk </span></div>
|
||
<div class="line"><a id="l01990" name="l01990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae75e432559ee49ae55397f529f199ad0"> 1990</a></span><span class="preprocessor">#define CAN_RF0R_RFOM0_Pos (5U) </span></div>
|
||
<div class="line"><a id="l01991" name="l01991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3c768b2f6a6c8b8b434991528110467"> 1991</a></span><span class="preprocessor">#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) </span></div>
|
||
<div class="line"><a id="l01992" name="l01992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74d2db4b9b7d52712e47557dcc61964d"> 1992</a></span><span class="preprocessor">#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk </span></div>
|
||
<div class="line"><a id="l01994" name="l01994"></a><span class="lineno"> 1994</span><span class="comment">/******************* Bit definition for CAN_RF1R register *******************/</span></div>
|
||
<div class="line"><a id="l01995" name="l01995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00fcf8bdc5087d5ff6d55c5206b346f3"> 1995</a></span><span class="preprocessor">#define CAN_RF1R_FMP1_Pos (0U) </span></div>
|
||
<div class="line"><a id="l01996" name="l01996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b08002573d35c943f136ab6c667f363"> 1996</a></span><span class="preprocessor">#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) </span></div>
|
||
<div class="line"><a id="l01997" name="l01997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f9254d05043df6f21bf96234a03f72f"> 1997</a></span><span class="preprocessor">#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk </span></div>
|
||
<div class="line"><a id="l01998" name="l01998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc6bab0544e01fcd1bcf0487139f729e"> 1998</a></span><span class="preprocessor">#define CAN_RF1R_FULL1_Pos (3U) </span></div>
|
||
<div class="line"><a id="l01999" name="l01999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0ac244ab1c525913bfcc3d03b9ab06f"> 1999</a></span><span class="preprocessor">#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) </span></div>
|
||
<div class="line"><a id="l02000" name="l02000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdaa12fe4d14254cc4a6a4de749a7d0a"> 2000</a></span><span class="preprocessor">#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk </span></div>
|
||
<div class="line"><a id="l02001" name="l02001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9faad05fc13813a198405bb5f064fb05"> 2001</a></span><span class="preprocessor">#define CAN_RF1R_FOVR1_Pos (4U) </span></div>
|
||
<div class="line"><a id="l02002" name="l02002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacee8c5b572eb85447912dcbc62aac97c"> 2002</a></span><span class="preprocessor">#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) </span></div>
|
||
<div class="line"><a id="l02003" name="l02003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5eeaabd4db3825bc53d860aca8d7590"> 2003</a></span><span class="preprocessor">#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk </span></div>
|
||
<div class="line"><a id="l02004" name="l02004"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2e95cc6d93830acc8669871fff26939"> 2004</a></span><span class="preprocessor">#define CAN_RF1R_RFOM1_Pos (5U) </span></div>
|
||
<div class="line"><a id="l02005" name="l02005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec98a01deaf5464a0ba9052a028bf483"> 2005</a></span><span class="preprocessor">#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) </span></div>
|
||
<div class="line"><a id="l02006" name="l02006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6930f860de4a90e3344e63fbc209b9ab"> 2006</a></span><span class="preprocessor">#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk </span></div>
|
||
<div class="line"><a id="l02008" name="l02008"></a><span class="lineno"> 2008</span><span class="comment">/******************** Bit definition for CAN_IER register *******************/</span></div>
|
||
<div class="line"><a id="l02009" name="l02009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea8fc846d9892de7b30d31bdf6b54edb"> 2009</a></span><span class="preprocessor">#define CAN_IER_TMEIE_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02010" name="l02010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac38696874c8fbbd05b6413ac11746d6b"> 2010</a></span><span class="preprocessor">#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) </span></div>
|
||
<div class="line"><a id="l02011" name="l02011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe027af7acd051f5a52db78608a36e26"> 2011</a></span><span class="preprocessor">#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk </span></div>
|
||
<div class="line"><a id="l02012" name="l02012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3325defd7e318b63baa1f78b50394280"> 2012</a></span><span class="preprocessor">#define CAN_IER_FMPIE0_Pos (1U) </span></div>
|
||
<div class="line"><a id="l02013" name="l02013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6885c5945dc4db64d46aa83bd8367e83"> 2013</a></span><span class="preprocessor">#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) </span></div>
|
||
<div class="line"><a id="l02014" name="l02014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59eecd1bb7d1d0e17422a26ae89cf39d"> 2014</a></span><span class="preprocessor">#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk </span></div>
|
||
<div class="line"><a id="l02015" name="l02015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga411ce03315531b3f90698b7e9224b93a"> 2015</a></span><span class="preprocessor">#define CAN_IER_FFIE0_Pos (2U) </span></div>
|
||
<div class="line"><a id="l02016" name="l02016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8885a2f34117d17dfb78fb78fb18b7a7"> 2016</a></span><span class="preprocessor">#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) </span></div>
|
||
<div class="line"><a id="l02017" name="l02017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf926ae29d98a8b72ef48f001fda07fc3"> 2017</a></span><span class="preprocessor">#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk </span></div>
|
||
<div class="line"><a id="l02018" name="l02018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7cded06b69c3ab261928a1b48ece5f9"> 2018</a></span><span class="preprocessor">#define CAN_IER_FOVIE0_Pos (3U) </span></div>
|
||
<div class="line"><a id="l02019" name="l02019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7859520258dfc8c61eca8da04ff180f9"> 2019</a></span><span class="preprocessor">#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) </span></div>
|
||
<div class="line"><a id="l02020" name="l02020"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c423699fdcd2ddddb3046a368505679"> 2020</a></span><span class="preprocessor">#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk </span></div>
|
||
<div class="line"><a id="l02021" name="l02021"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b904e14bd25a2d2e155364c2ebb5c7e"> 2021</a></span><span class="preprocessor">#define CAN_IER_FMPIE1_Pos (4U) </span></div>
|
||
<div class="line"><a id="l02022" name="l02022"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac66a68cb8bc52e699f9d83673515c3b9"> 2022</a></span><span class="preprocessor">#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) </span></div>
|
||
<div class="line"><a id="l02023" name="l02023"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b8492d1b8ce13fead7869a0e4ef39ed"> 2023</a></span><span class="preprocessor">#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk </span></div>
|
||
<div class="line"><a id="l02024" name="l02024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0c5e16c335ad2459a1726d123b8f720"> 2024</a></span><span class="preprocessor">#define CAN_IER_FFIE1_Pos (5U) </span></div>
|
||
<div class="line"><a id="l02025" name="l02025"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20cba05b98222a9ce8bf5b5804c78ead"> 2025</a></span><span class="preprocessor">#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) </span></div>
|
||
<div class="line"><a id="l02026" name="l02026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5a7e9d13e8d96bef2ac1972520b1c4f"> 2026</a></span><span class="preprocessor">#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk </span></div>
|
||
<div class="line"><a id="l02027" name="l02027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga210db948ed64aa24bc8176041966f934"> 2027</a></span><span class="preprocessor">#define CAN_IER_FOVIE1_Pos (6U) </span></div>
|
||
<div class="line"><a id="l02028" name="l02028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0256723529d4c2adf64c0f5b6da56e7a"> 2028</a></span><span class="preprocessor">#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) </span></div>
|
||
<div class="line"><a id="l02029" name="l02029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3734d9bf5cd08ff219b2d8c2f8300dbf"> 2029</a></span><span class="preprocessor">#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk </span></div>
|
||
<div class="line"><a id="l02030" name="l02030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ed2cabb36a1f1b250a8d344896b1c9c"> 2030</a></span><span class="preprocessor">#define CAN_IER_EWGIE_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02031" name="l02031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac15046ca7a384201773a9dfeb03deabc"> 2031</a></span><span class="preprocessor">#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) </span></div>
|
||
<div class="line"><a id="l02032" name="l02032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa80103eca53d74a2b047f761336918e3"> 2032</a></span><span class="preprocessor">#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk </span></div>
|
||
<div class="line"><a id="l02033" name="l02033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9f52eb0782253e0623c7bdd27823743"> 2033</a></span><span class="preprocessor">#define CAN_IER_EPVIE_Pos (9U) </span></div>
|
||
<div class="line"><a id="l02034" name="l02034"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gababf833052c2a6ffbd6ce2aa5960a61b"> 2034</a></span><span class="preprocessor">#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) </span></div>
|
||
<div class="line"><a id="l02035" name="l02035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e3307992cabee858287305a64e5031b"> 2035</a></span><span class="preprocessor">#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk </span></div>
|
||
<div class="line"><a id="l02036" name="l02036"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa110152ba07d311efc4c513a0e39eb4"> 2036</a></span><span class="preprocessor">#define CAN_IER_BOFIE_Pos (10U) </span></div>
|
||
<div class="line"><a id="l02037" name="l02037"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga748f02d794157dc9684f6c15096d4e75"> 2037</a></span><span class="preprocessor">#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) </span></div>
|
||
<div class="line"><a id="l02038" name="l02038"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d953fd5b625af04f95f5414259769ef"> 2038</a></span><span class="preprocessor">#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk </span></div>
|
||
<div class="line"><a id="l02039" name="l02039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ccd7e2e333c2dae013674b5bac0ecbc"> 2039</a></span><span class="preprocessor">#define CAN_IER_LECIE_Pos (11U) </span></div>
|
||
<div class="line"><a id="l02040" name="l02040"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga386f61a3f7ef21600969ef0c936e255c"> 2040</a></span><span class="preprocessor">#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) </span></div>
|
||
<div class="line"><a id="l02041" name="l02041"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81514ecf1b6596e9930906779c4bdf39"> 2041</a></span><span class="preprocessor">#define CAN_IER_LECIE CAN_IER_LECIE_Msk </span></div>
|
||
<div class="line"><a id="l02042" name="l02042"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5a98a5d7ea27cfd207b83364fb3b8e2"> 2042</a></span><span class="preprocessor">#define CAN_IER_ERRIE_Pos (15U) </span></div>
|
||
<div class="line"><a id="l02043" name="l02043"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3df7133242e3ff1636bb946649faa8d0"> 2043</a></span><span class="preprocessor">#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) </span></div>
|
||
<div class="line"><a id="l02044" name="l02044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga962968c3ee1f70c714a5b12442369d9a"> 2044</a></span><span class="preprocessor">#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk </span></div>
|
||
<div class="line"><a id="l02045" name="l02045"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf233f7c7c686ed81c4bc295143eb3a4b"> 2045</a></span><span class="preprocessor">#define CAN_IER_WKUIE_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02046" name="l02046"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga181d122c65769851c2cc82f4bd764d80"> 2046</a></span><span class="preprocessor">#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) </span></div>
|
||
<div class="line"><a id="l02047" name="l02047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37f3438e80288c1791de27042df9838e"> 2047</a></span><span class="preprocessor">#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk </span></div>
|
||
<div class="line"><a id="l02048" name="l02048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa7b49f18204d00911b39f940b63e0f3"> 2048</a></span><span class="preprocessor">#define CAN_IER_SLKIE_Pos (17U) </span></div>
|
||
<div class="line"><a id="l02049" name="l02049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf34b93be0df4cfdaad8dbb99f4fa1bc7"> 2049</a></span><span class="preprocessor">#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) </span></div>
|
||
<div class="line"><a id="l02050" name="l02050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82389b79f21410f5d5f6bef38d192812"> 2050</a></span><span class="preprocessor">#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk </span></div>
|
||
<div class="line"><a id="l02051" name="l02051"></a><span class="lineno"> 2051</span><span class="preprocessor">#define CAN_IER_EWGIE_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02052" name="l02052"></a><span class="lineno"> 2052</span> </div>
|
||
<div class="line"><a id="l02053" name="l02053"></a><span class="lineno"> 2053</span><span class="comment">/******************** Bit definition for CAN_ESR register *******************/</span></div>
|
||
<div class="line"><a id="l02054" name="l02054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecadeaf7d9cadf19529cab6314ccc5e6"> 2054</a></span><span class="preprocessor">#define CAN_ESR_EWGF_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02055" name="l02055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaace0e3b331bea3a3f35a3bdf88a40b86"> 2055</a></span><span class="preprocessor">#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) </span></div>
|
||
<div class="line"><a id="l02056" name="l02056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c0c02829fb41ac2a1b1852c19931de8"> 2056</a></span><span class="preprocessor">#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk </span></div>
|
||
<div class="line"><a id="l02057" name="l02057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c53494946cb6ee312e947da2e4329b6"> 2057</a></span><span class="preprocessor">#define CAN_ESR_EPVF_Pos (1U) </span></div>
|
||
<div class="line"><a id="l02058" name="l02058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab80e2d629b9aaf329dee50e9e4ee4a3e"> 2058</a></span><span class="preprocessor">#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) </span></div>
|
||
<div class="line"><a id="l02059" name="l02059"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga633c961d528cbf8093b0e05e92225ff0"> 2059</a></span><span class="preprocessor">#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk </span></div>
|
||
<div class="line"><a id="l02060" name="l02060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe022d4e68fb0eca8278904fcfe3c783"> 2060</a></span><span class="preprocessor">#define CAN_ESR_BOFF_Pos (2U) </span></div>
|
||
<div class="line"><a id="l02061" name="l02061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6607245f6b97f83691b9f9d9a3cf592"> 2061</a></span><span class="preprocessor">#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) </span></div>
|
||
<div class="line"><a id="l02062" name="l02062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga619d49f67f1835a7efc457205fea1225"> 2062</a></span><span class="preprocessor">#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk </span></div>
|
||
<div class="line"><a id="l02064" name="l02064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d2dfedaf48ce2f4787afd43cad691bf"> 2064</a></span><span class="preprocessor">#define CAN_ESR_LEC_Pos (4U) </span></div>
|
||
<div class="line"><a id="l02065" name="l02065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad88ad0a905fbbe60fa2900f2cec42f5c"> 2065</a></span><span class="preprocessor">#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) </span></div>
|
||
<div class="line"><a id="l02066" name="l02066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9f86741dd89034900e300499ae2272e"> 2066</a></span><span class="preprocessor">#define CAN_ESR_LEC CAN_ESR_LEC_Msk </span></div>
|
||
<div class="line"><a id="l02067" name="l02067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga054ebb41578d890d4d9dffb4828f02e7"> 2067</a></span><span class="preprocessor">#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) </span></div>
|
||
<div class="line"><a id="l02068" name="l02068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae570e9ba39dbe11808db929392250cf4"> 2068</a></span><span class="preprocessor">#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) </span></div>
|
||
<div class="line"><a id="l02069" name="l02069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4998e7bfd002999413c68107911c6e8c"> 2069</a></span><span class="preprocessor">#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) </span></div>
|
||
<div class="line"><a id="l02071" name="l02071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11fde56e8a41fc98f69d84636121a361"> 2071</a></span><span class="preprocessor">#define CAN_ESR_TEC_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02072" name="l02072"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56c7759712292904bf0d15c2d968bbad"> 2072</a></span><span class="preprocessor">#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) </span></div>
|
||
<div class="line"><a id="l02073" name="l02073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3de2080f48cc851c20d920acfd1737d"> 2073</a></span><span class="preprocessor">#define CAN_ESR_TEC CAN_ESR_TEC_Msk </span></div>
|
||
<div class="line"><a id="l02074" name="l02074"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga804f28bce21721cd4e9fcabf772f0f9d"> 2074</a></span><span class="preprocessor">#define CAN_ESR_REC_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02075" name="l02075"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0143dc7eea1099168ef7fef24192949e"> 2075</a></span><span class="preprocessor">#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) </span></div>
|
||
<div class="line"><a id="l02076" name="l02076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0df5b2ea3f419182e9bd885f55ee5dc9"> 2076</a></span><span class="preprocessor">#define CAN_ESR_REC CAN_ESR_REC_Msk </span></div>
|
||
<div class="line"><a id="l02078" name="l02078"></a><span class="lineno"> 2078</span><span class="comment">/******************* Bit definition for CAN_BTR register ********************/</span></div>
|
||
<div class="line"><a id="l02079" name="l02079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3a0f2dc6767c5297f2f3475fdea8bef"> 2079</a></span><span class="preprocessor">#define CAN_BTR_BRP_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02080" name="l02080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad530ac34faa377b770d56624f009934d"> 2080</a></span><span class="preprocessor">#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) </span></div>
|
||
<div class="line"><a id="l02081" name="l02081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96a5522b4c06551856f7185bdd448b02"> 2081</a></span><span class="preprocessor">#define CAN_BTR_BRP CAN_BTR_BRP_Msk </span></div>
|
||
<div class="line"><a id="l02082" name="l02082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac00e3a010662ce93bd9e67f340bd2646"> 2082</a></span><span class="preprocessor">#define CAN_BTR_TS1_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02083" name="l02083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf97266c03c918c7ff4a0d90b9f80b4f2"> 2083</a></span><span class="preprocessor">#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) </span></div>
|
||
<div class="line"><a id="l02084" name="l02084"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d7ae8f06f8fbbf5dcfbbbb887057be9"> 2084</a></span><span class="preprocessor">#define CAN_BTR_TS1 CAN_BTR_TS1_Msk </span></div>
|
||
<div class="line"><a id="l02085" name="l02085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga164ffd2240a76982894ce41143a12d82"> 2085</a></span><span class="preprocessor">#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) </span></div>
|
||
<div class="line"><a id="l02086" name="l02086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4365204ebb29eb5595027a4ee9c5f0d"> 2086</a></span><span class="preprocessor">#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) </span></div>
|
||
<div class="line"><a id="l02087" name="l02087"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43dc43f11ee173cf07f77aa6e41f1275"> 2087</a></span><span class="preprocessor">#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) </span></div>
|
||
<div class="line"><a id="l02088" name="l02088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a5cd639329fe3eef8cde846247a4be9"> 2088</a></span><span class="preprocessor">#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) </span></div>
|
||
<div class="line"><a id="l02089" name="l02089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac80e236530969bf1f520e8e0dd7b7e79"> 2089</a></span><span class="preprocessor">#define CAN_BTR_TS2_Pos (20U) </span></div>
|
||
<div class="line"><a id="l02090" name="l02090"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7c657a3c97363915a9d739defa0f516"> 2090</a></span><span class="preprocessor">#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) </span></div>
|
||
<div class="line"><a id="l02091" name="l02091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac006aa2ab26c50227ccaa18e0a79bff3"> 2091</a></span><span class="preprocessor">#define CAN_BTR_TS2 CAN_BTR_TS2_Msk </span></div>
|
||
<div class="line"><a id="l02092" name="l02092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee307fe50e8d3cfdc9513da803808880"> 2092</a></span><span class="preprocessor">#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) </span></div>
|
||
<div class="line"><a id="l02093" name="l02093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33265730e1d25198d9fb4347bdce8019"> 2093</a></span><span class="preprocessor">#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) </span></div>
|
||
<div class="line"><a id="l02094" name="l02094"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac4720d91283fc1fc74c1f0baaa8a3da"> 2094</a></span><span class="preprocessor">#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) </span></div>
|
||
<div class="line"><a id="l02095" name="l02095"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cc4270d185b17bd0ce09ebb14c30121"> 2095</a></span><span class="preprocessor">#define CAN_BTR_SJW_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02096" name="l02096"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddf7f2fb84354e7e4756bdc25569d6cc"> 2096</a></span><span class="preprocessor">#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) </span></div>
|
||
<div class="line"><a id="l02097" name="l02097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04c8b91ddacdcbb779bae42398c94cf2"> 2097</a></span><span class="preprocessor">#define CAN_BTR_SJW CAN_BTR_SJW_Msk </span></div>
|
||
<div class="line"><a id="l02098" name="l02098"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08ae9e8258ef5c241733f6d58eb2a4e4"> 2098</a></span><span class="preprocessor">#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) </span></div>
|
||
<div class="line"><a id="l02099" name="l02099"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8178f0abe0f854f4503ded1ad1adb531"> 2099</a></span><span class="preprocessor">#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) </span></div>
|
||
<div class="line"><a id="l02100" name="l02100"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d6dac3caae5bf3f69716d7417e920d7"> 2100</a></span><span class="preprocessor">#define CAN_BTR_LBKM_Pos (30U) </span></div>
|
||
<div class="line"><a id="l02101" name="l02101"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa32a82ff55c8008f4c0a1e16c0492d6c"> 2101</a></span><span class="preprocessor">#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) </span></div>
|
||
<div class="line"><a id="l02102" name="l02102"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6c0a81d8dcde61a1f2772232f5343b8"> 2102</a></span><span class="preprocessor">#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk </span></div>
|
||
<div class="line"><a id="l02103" name="l02103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac19407ed54b60ae709840db37855a0a4"> 2103</a></span><span class="preprocessor">#define CAN_BTR_SILM_Pos (31U) </span></div>
|
||
<div class="line"><a id="l02104" name="l02104"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a7f4e5e22b9959994c790ac9c7f03d3"> 2104</a></span><span class="preprocessor">#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) </span></div>
|
||
<div class="line"><a id="l02105" name="l02105"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa36bc23e833190cbee9b8cf5cf49159d"> 2105</a></span><span class="preprocessor">#define CAN_BTR_SILM CAN_BTR_SILM_Msk </span></div>
|
||
<div class="line"><a id="l02109" name="l02109"></a><span class="lineno"> 2109</span><span class="comment">/****************** Bit definition for CAN_TI0R register ********************/</span></div>
|
||
<div class="line"><a id="l02110" name="l02110"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga255ce6dd558937c9b33efa43d01b7029"> 2110</a></span><span class="preprocessor">#define CAN_TI0R_TXRQ_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02111" name="l02111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53cf2d76df5b85e7363ca6fb45e71c4a"> 2111</a></span><span class="preprocessor">#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) </span></div>
|
||
<div class="line"><a id="l02112" name="l02112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b79cbb7ebb7f3419aa6ac04bd76899a"> 2112</a></span><span class="preprocessor">#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk </span></div>
|
||
<div class="line"><a id="l02113" name="l02113"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98b5217c83959ca007cb09ba59f1c182"> 2113</a></span><span class="preprocessor">#define CAN_TI0R_RTR_Pos (1U) </span></div>
|
||
<div class="line"><a id="l02114" name="l02114"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab713759c47fadc25119dd265c413f771"> 2114</a></span><span class="preprocessor">#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) </span></div>
|
||
<div class="line"><a id="l02115" name="l02115"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5556f2ceb5b71b8afa76a18a31cbb6a"> 2115</a></span><span class="preprocessor">#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk </span></div>
|
||
<div class="line"><a id="l02116" name="l02116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10b3ea5dc6c4d2f6d3925debfc2ba267"> 2116</a></span><span class="preprocessor">#define CAN_TI0R_IDE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l02117" name="l02117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga080d97de6d25618d06b2d0a453c692b6"> 2117</a></span><span class="preprocessor">#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) </span></div>
|
||
<div class="line"><a id="l02118" name="l02118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06f761a877f8ad39f878284f69119c0b"> 2118</a></span><span class="preprocessor">#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk </span></div>
|
||
<div class="line"><a id="l02119" name="l02119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4e738c64e396face3bbc9c5011e6b0e"> 2119</a></span><span class="preprocessor">#define CAN_TI0R_EXID_Pos (3U) </span></div>
|
||
<div class="line"><a id="l02120" name="l02120"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2138165e39efac11d31381e1d7c72bfa"> 2120</a></span><span class="preprocessor">#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) </span></div>
|
||
<div class="line"><a id="l02121" name="l02121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga894df6ad0d2976fe643dcb77052672f5"> 2121</a></span><span class="preprocessor">#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk </span></div>
|
||
<div class="line"><a id="l02122" name="l02122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9e827ddbaa36f5651329cc61375221f"> 2122</a></span><span class="preprocessor">#define CAN_TI0R_STID_Pos (21U) </span></div>
|
||
<div class="line"><a id="l02123" name="l02123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4b180d9e1ecf00b104d18670496a8db"> 2123</a></span><span class="preprocessor">#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) </span></div>
|
||
<div class="line"><a id="l02124" name="l02124"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d3b5882e1f9f76f5cfebffb5bc2f717"> 2124</a></span><span class="preprocessor">#define CAN_TI0R_STID CAN_TI0R_STID_Msk </span></div>
|
||
<div class="line"><a id="l02126" name="l02126"></a><span class="lineno"> 2126</span><span class="comment">/****************** Bit definition for CAN_TDT0R register *******************/</span></div>
|
||
<div class="line"><a id="l02127" name="l02127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ba7824b92498610f685f712c1075702"> 2127</a></span><span class="preprocessor">#define CAN_TDT0R_DLC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02128" name="l02128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06a3a47edaaf175482a18feccbce3a61"> 2128</a></span><span class="preprocessor">#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) </span></div>
|
||
<div class="line"><a id="l02129" name="l02129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf812eaee11f12863773b3f8e95ae6e2"> 2129</a></span><span class="preprocessor">#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk </span></div>
|
||
<div class="line"><a id="l02130" name="l02130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac770efaeca5e93c9dbde1fa508ab79aa"> 2130</a></span><span class="preprocessor">#define CAN_TDT0R_TGT_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02131" name="l02131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga394785c0a3d16b48d7bbcc524d2821a3"> 2131</a></span><span class="preprocessor">#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) </span></div>
|
||
<div class="line"><a id="l02132" name="l02132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2d329960b527a62fab099a084bfa906"> 2132</a></span><span class="preprocessor">#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk </span></div>
|
||
<div class="line"><a id="l02133" name="l02133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ffd9f8d93bb7f96dfc8f2b202986ec5"> 2133</a></span><span class="preprocessor">#define CAN_TDT0R_TIME_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02134" name="l02134"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga544adf091e79aa36d9d7a6e47bafcb41"> 2134</a></span><span class="preprocessor">#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) </span></div>
|
||
<div class="line"><a id="l02135" name="l02135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga104ba91151bf88edd44593b1690b879a"> 2135</a></span><span class="preprocessor">#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk </span></div>
|
||
<div class="line"><a id="l02137" name="l02137"></a><span class="lineno"> 2137</span><span class="comment">/****************** Bit definition for CAN_TDL0R register *******************/</span></div>
|
||
<div class="line"><a id="l02138" name="l02138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2dfd1e20e5283d40302140066d527d3"> 2138</a></span><span class="preprocessor">#define CAN_TDL0R_DATA0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02139" name="l02139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21c0f147ab22439d7677e400651302c4"> 2139</a></span><span class="preprocessor">#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) </span></div>
|
||
<div class="line"><a id="l02140" name="l02140"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadec3350607b41410ddb6e00a71a4384e"> 2140</a></span><span class="preprocessor">#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk </span></div>
|
||
<div class="line"><a id="l02141" name="l02141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ebdc896d4816e5d5eee1c1700c7fb25"> 2141</a></span><span class="preprocessor">#define CAN_TDL0R_DATA1_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02142" name="l02142"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae03b879d3e573023038e211ea211ae9f"> 2142</a></span><span class="preprocessor">#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) </span></div>
|
||
<div class="line"><a id="l02143" name="l02143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cd20d218027e7432178c67414475830"> 2143</a></span><span class="preprocessor">#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk </span></div>
|
||
<div class="line"><a id="l02144" name="l02144"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad46a5808e83c8ce1c6c2da8c3ee2898d"> 2144</a></span><span class="preprocessor">#define CAN_TDL0R_DATA2_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02145" name="l02145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcc788dc5db08c074c7026e60d3af7cb"> 2145</a></span><span class="preprocessor">#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) </span></div>
|
||
<div class="line"><a id="l02146" name="l02146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa04384f0a7c5026c91a33a005c755d68"> 2146</a></span><span class="preprocessor">#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk </span></div>
|
||
<div class="line"><a id="l02147" name="l02147"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66d8189fd904326f4be09972047fda59"> 2147</a></span><span class="preprocessor">#define CAN_TDL0R_DATA3_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02148" name="l02148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga782c6f20d550a56c15fe265a75105255"> 2148</a></span><span class="preprocessor">#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) </span></div>
|
||
<div class="line"><a id="l02149" name="l02149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga283a1bfa52851ea4ee45f45817985752"> 2149</a></span><span class="preprocessor">#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk </span></div>
|
||
<div class="line"><a id="l02151" name="l02151"></a><span class="lineno"> 2151</span><span class="comment">/****************** Bit definition for CAN_TDH0R register *******************/</span></div>
|
||
<div class="line"><a id="l02152" name="l02152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67239c62f07e5a4d0f348f9595d4fb0e"> 2152</a></span><span class="preprocessor">#define CAN_TDH0R_DATA4_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02153" name="l02153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2389e6393c4c90eac09ecadd67e77203"> 2153</a></span><span class="preprocessor">#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) </span></div>
|
||
<div class="line"><a id="l02154" name="l02154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0114ae75b33f978ca7825f7bcd836982"> 2154</a></span><span class="preprocessor">#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk </span></div>
|
||
<div class="line"><a id="l02155" name="l02155"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac19fa11ce4c6d4c00690d453a3b42354"> 2155</a></span><span class="preprocessor">#define CAN_TDH0R_DATA5_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02156" name="l02156"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadeaa64cd95a54957ee402f9edbd62411"> 2156</a></span><span class="preprocessor">#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) </span></div>
|
||
<div class="line"><a id="l02157" name="l02157"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5b6a0742ac1bcd5ef0408cb0f92ef75"> 2157</a></span><span class="preprocessor">#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk </span></div>
|
||
<div class="line"><a id="l02158" name="l02158"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19b1609d2ed4f6b59e9b175e022123b5"> 2158</a></span><span class="preprocessor">#define CAN_TDH0R_DATA6_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02159" name="l02159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80deb2e84b16aa300ba4b6dad03ced70"> 2159</a></span><span class="preprocessor">#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) </span></div>
|
||
<div class="line"><a id="l02160" name="l02160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8ea7090da55c7cc9993235efa1c4a02"> 2160</a></span><span class="preprocessor">#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk </span></div>
|
||
<div class="line"><a id="l02161" name="l02161"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed76c2a3e8d2946eeed952bb2ff20e94"> 2161</a></span><span class="preprocessor">#define CAN_TDH0R_DATA7_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02162" name="l02162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad14d21df0b2b694450b769b900c1161e"> 2162</a></span><span class="preprocessor">#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) </span></div>
|
||
<div class="line"><a id="l02163" name="l02163"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6021a4045fbfd71817bf9aec6cbc731c"> 2163</a></span><span class="preprocessor">#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk </span></div>
|
||
<div class="line"><a id="l02165" name="l02165"></a><span class="lineno"> 2165</span><span class="comment">/******************* Bit definition for CAN_TI1R register *******************/</span></div>
|
||
<div class="line"><a id="l02166" name="l02166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab1e199d262fd92f1702125a8e8f5b49"> 2166</a></span><span class="preprocessor">#define CAN_TI1R_TXRQ_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02167" name="l02167"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89f8f9283cb55ff6427db96afb6ad799"> 2167</a></span><span class="preprocessor">#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) </span></div>
|
||
<div class="line"><a id="l02168" name="l02168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0adf4a08415673753fafedf463f93bee"> 2168</a></span><span class="preprocessor">#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk </span></div>
|
||
<div class="line"><a id="l02169" name="l02169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35a4cc56a2487c645c3b318bfba5e8ca"> 2169</a></span><span class="preprocessor">#define CAN_TI1R_RTR_Pos (1U) </span></div>
|
||
<div class="line"><a id="l02170" name="l02170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f27bd0f65fe4d7afe69a92c28bef94e"> 2170</a></span><span class="preprocessor">#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) </span></div>
|
||
<div class="line"><a id="l02171" name="l02171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga476cde56b1a2a13cde8477d5178ba34b"> 2171</a></span><span class="preprocessor">#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk </span></div>
|
||
<div class="line"><a id="l02172" name="l02172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga176b1ffea4ad6af7a07044e30d9a210e"> 2172</a></span><span class="preprocessor">#define CAN_TI1R_IDE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l02173" name="l02173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20f905ac8ef34db338cd9b9e94ea7216"> 2173</a></span><span class="preprocessor">#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) </span></div>
|
||
<div class="line"><a id="l02174" name="l02174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f338f3e295b7b512ed865b3f9a8d6de"> 2174</a></span><span class="preprocessor">#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk </span></div>
|
||
<div class="line"><a id="l02175" name="l02175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab927997e1cb30013ce0c58a974a1ea55"> 2175</a></span><span class="preprocessor">#define CAN_TI1R_EXID_Pos (3U) </span></div>
|
||
<div class="line"><a id="l02176" name="l02176"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ba8b24afd72b47c403129c09a6f295f"> 2176</a></span><span class="preprocessor">#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) </span></div>
|
||
<div class="line"><a id="l02177" name="l02177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c660943fa3c70c4974c2dacd3e4ca2e"> 2177</a></span><span class="preprocessor">#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk </span></div>
|
||
<div class="line"><a id="l02178" name="l02178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a5e1691eb28536f2773609a195e4cbf"> 2178</a></span><span class="preprocessor">#define CAN_TI1R_STID_Pos (21U) </span></div>
|
||
<div class="line"><a id="l02179" name="l02179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fb9bb620f8051f9059d78eb2fd09cd9"> 2179</a></span><span class="preprocessor">#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) </span></div>
|
||
<div class="line"><a id="l02180" name="l02180"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga842071768c2f8f5eae11a764a77dd0dd"> 2180</a></span><span class="preprocessor">#define CAN_TI1R_STID CAN_TI1R_STID_Msk </span></div>
|
||
<div class="line"><a id="l02182" name="l02182"></a><span class="lineno"> 2182</span><span class="comment">/******************* Bit definition for CAN_TDT1R register ******************/</span></div>
|
||
<div class="line"><a id="l02183" name="l02183"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b088fcd5a224ff04b87ca90fe4ad93a"> 2183</a></span><span class="preprocessor">#define CAN_TDT1R_DLC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02184" name="l02184"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78cb2a08e7abfd8105acee53c2fe6957"> 2184</a></span><span class="preprocessor">#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) </span></div>
|
||
<div class="line"><a id="l02185" name="l02185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68ef8b6cb43a80d29c5fc318a67acd3b"> 2185</a></span><span class="preprocessor">#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk </span></div>
|
||
<div class="line"><a id="l02186" name="l02186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf17aa4d8323302bc493c93d38be34b60"> 2186</a></span><span class="preprocessor">#define CAN_TDT1R_TGT_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02187" name="l02187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36274682f7c568c18db742816468f08d"> 2187</a></span><span class="preprocessor">#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) </span></div>
|
||
<div class="line"><a id="l02188" name="l02188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35757787e6481553885fdf4fd2738c4b"> 2188</a></span><span class="preprocessor">#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk </span></div>
|
||
<div class="line"><a id="l02189" name="l02189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37df5b75c3aedc37c37f308d32b178b6"> 2189</a></span><span class="preprocessor">#define CAN_TDT1R_TIME_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02190" name="l02190"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96a341aceed7cefa4f144685b047b5aa"> 2190</a></span><span class="preprocessor">#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) </span></div>
|
||
<div class="line"><a id="l02191" name="l02191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad28ac334a59a6679c362611d65666910"> 2191</a></span><span class="preprocessor">#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk </span></div>
|
||
<div class="line"><a id="l02193" name="l02193"></a><span class="lineno"> 2193</span><span class="comment">/******************* Bit definition for CAN_TDL1R register ******************/</span></div>
|
||
<div class="line"><a id="l02194" name="l02194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a9794992e11c29ba12088b41a9215cd"> 2194</a></span><span class="preprocessor">#define CAN_TDL1R_DATA0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02195" name="l02195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16520ea88ace96a458b0818d3e4d5cf2"> 2195</a></span><span class="preprocessor">#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) </span></div>
|
||
<div class="line"><a id="l02196" name="l02196"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21abc05257bcdfa47fc824b4d806a105"> 2196</a></span><span class="preprocessor">#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk </span></div>
|
||
<div class="line"><a id="l02197" name="l02197"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15870798808b9bf8e3b389d99f8205bd"> 2197</a></span><span class="preprocessor">#define CAN_TDL1R_DATA1_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02198" name="l02198"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22d121d05d7faac3231ab8b0cc3fd4e2"> 2198</a></span><span class="preprocessor">#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) </span></div>
|
||
<div class="line"><a id="l02199" name="l02199"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bf459dee1be706b38141722be67e4ab"> 2199</a></span><span class="preprocessor">#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk </span></div>
|
||
<div class="line"><a id="l02200" name="l02200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga822b0dd09688ddb0241506b3657d3e76"> 2200</a></span><span class="preprocessor">#define CAN_TDL1R_DATA2_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02201" name="l02201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06359cf64606bd479a4a5e074c5e70ac"> 2201</a></span><span class="preprocessor">#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) </span></div>
|
||
<div class="line"><a id="l02202" name="l02202"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb92a65c225432fab0daa30808d5065c"> 2202</a></span><span class="preprocessor">#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk </span></div>
|
||
<div class="line"><a id="l02203" name="l02203"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26002007d5645d59e1de29fecb91c906"> 2203</a></span><span class="preprocessor">#define CAN_TDL1R_DATA3_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02204" name="l02204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17d98be9066ebe1cf701052043be89bc"> 2204</a></span><span class="preprocessor">#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) </span></div>
|
||
<div class="line"><a id="l02205" name="l02205"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga482506faa59360c6a48aa9bc55a024c4"> 2205</a></span><span class="preprocessor">#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk </span></div>
|
||
<div class="line"><a id="l02207" name="l02207"></a><span class="lineno"> 2207</span><span class="comment">/******************* Bit definition for CAN_TDH1R register ******************/</span></div>
|
||
<div class="line"><a id="l02208" name="l02208"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4acd3f2aaf9f8a62bc486733feb4fba8"> 2208</a></span><span class="preprocessor">#define CAN_TDH1R_DATA4_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02209" name="l02209"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44d94c7419786e7bba7ec0a1b35395cb"> 2209</a></span><span class="preprocessor">#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) </span></div>
|
||
<div class="line"><a id="l02210" name="l02210"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41c3f19eea0d63211f643833da984c90"> 2210</a></span><span class="preprocessor">#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk </span></div>
|
||
<div class="line"><a id="l02211" name="l02211"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f2050d91710f0b977d984e164067f9f"> 2211</a></span><span class="preprocessor">#define CAN_TDH1R_DATA5_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02212" name="l02212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa946d8a10e5f952a5c4eda78228042af"> 2212</a></span><span class="preprocessor">#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) </span></div>
|
||
<div class="line"><a id="l02213" name="l02213"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35cbe73d2ce87b6aaf19510818610d16"> 2213</a></span><span class="preprocessor">#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk </span></div>
|
||
<div class="line"><a id="l02214" name="l02214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f3a0e5d886a7db9accd6e2d1316174f"> 2214</a></span><span class="preprocessor">#define CAN_TDH1R_DATA6_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02215" name="l02215"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff0a58abbdfa5e21213dbc2f82935250"> 2215</a></span><span class="preprocessor">#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) </span></div>
|
||
<div class="line"><a id="l02216" name="l02216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b731ca095cbad8e56ba4147c14d7128"> 2216</a></span><span class="preprocessor">#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk </span></div>
|
||
<div class="line"><a id="l02217" name="l02217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae01db20e595c85191c3abd91a1f74717"> 2217</a></span><span class="preprocessor">#define CAN_TDH1R_DATA7_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02218" name="l02218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga625d5b8e464b8dfc789e4191f55444cf"> 2218</a></span><span class="preprocessor">#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) </span></div>
|
||
<div class="line"><a id="l02219" name="l02219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec56ce4aba46e836d44e2c034a9ed817"> 2219</a></span><span class="preprocessor">#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk </span></div>
|
||
<div class="line"><a id="l02221" name="l02221"></a><span class="lineno"> 2221</span><span class="comment">/******************* Bit definition for CAN_TI2R register *******************/</span></div>
|
||
<div class="line"><a id="l02222" name="l02222"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fa18e2cbbb88117b1b6272c0c1ffea4"> 2222</a></span><span class="preprocessor">#define CAN_TI2R_TXRQ_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02223" name="l02223"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76f8681c59cc25db5a1089ecfc20a2ce"> 2223</a></span><span class="preprocessor">#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) </span></div>
|
||
<div class="line"><a id="l02224" name="l02224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4edd8438a684e353c497f80cb37365f"> 2224</a></span><span class="preprocessor">#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk </span></div>
|
||
<div class="line"><a id="l02225" name="l02225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ac8d95e007f7ca50f787eac4e08aa1e"> 2225</a></span><span class="preprocessor">#define CAN_TI2R_RTR_Pos (1U) </span></div>
|
||
<div class="line"><a id="l02226" name="l02226"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe417e434f32c25426c52b68fb763c9f"> 2226</a></span><span class="preprocessor">#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) </span></div>
|
||
<div class="line"><a id="l02227" name="l02227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga980cfab3daebb05da35b6166a051385d"> 2227</a></span><span class="preprocessor">#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk </span></div>
|
||
<div class="line"><a id="l02228" name="l02228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade77331f4ecfa76912b1a1b439583b61"> 2228</a></span><span class="preprocessor">#define CAN_TI2R_IDE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l02229" name="l02229"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5048adf1f603ea5d5170f3f9bcb92b4"> 2229</a></span><span class="preprocessor">#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) </span></div>
|
||
<div class="line"><a id="l02230" name="l02230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1d888a2225c77452f73bf66fb0e1b78"> 2230</a></span><span class="preprocessor">#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk </span></div>
|
||
<div class="line"><a id="l02231" name="l02231"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd2af643048de0df22426f9066d19223"> 2231</a></span><span class="preprocessor">#define CAN_TI2R_EXID_Pos (3U) </span></div>
|
||
<div class="line"><a id="l02232" name="l02232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade10da0694545f61f922cc3679f719d1"> 2232</a></span><span class="preprocessor">#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) </span></div>
|
||
<div class="line"><a id="l02233" name="l02233"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae62678bd1dc39aae5a153e9c9b3c3f3b"> 2233</a></span><span class="preprocessor">#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk </span></div>
|
||
<div class="line"><a id="l02234" name="l02234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fa5a1ec336dd0151f1027aa25379708"> 2234</a></span><span class="preprocessor">#define CAN_TI2R_STID_Pos (21U) </span></div>
|
||
<div class="line"><a id="l02235" name="l02235"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78165cdc898ec9184cf14df3d1940a46"> 2235</a></span><span class="preprocessor">#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) </span></div>
|
||
<div class="line"><a id="l02236" name="l02236"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41c8bd734dd29caa40d34ced3981443a"> 2236</a></span><span class="preprocessor">#define CAN_TI2R_STID CAN_TI2R_STID_Msk </span></div>
|
||
<div class="line"><a id="l02238" name="l02238"></a><span class="lineno"> 2238</span><span class="comment">/******************* Bit definition for CAN_TDT2R register ******************/</span> </div>
|
||
<div class="line"><a id="l02239" name="l02239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45143135ab0f9c01d85cca11d7949b26"> 2239</a></span><span class="preprocessor">#define CAN_TDT2R_DLC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02240" name="l02240"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63e75710f89ae715962fd2e2c5465edb"> 2240</a></span><span class="preprocessor">#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) </span></div>
|
||
<div class="line"><a id="l02241" name="l02241"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52898eb9fa3bcf0b8086220971af49f5"> 2241</a></span><span class="preprocessor">#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk </span></div>
|
||
<div class="line"><a id="l02242" name="l02242"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9e5a3e9a2526007920e8a255b7e1c3a"> 2242</a></span><span class="preprocessor">#define CAN_TDT2R_TGT_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02243" name="l02243"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01d388232664bf958d0396c19e39c815"> 2243</a></span><span class="preprocessor">#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) </span></div>
|
||
<div class="line"><a id="l02244" name="l02244"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c51b43d309b56e8a64724ef1517033e"> 2244</a></span><span class="preprocessor">#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk </span></div>
|
||
<div class="line"><a id="l02245" name="l02245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaceba646b9f79f648862f0ec8cf1e6a85"> 2245</a></span><span class="preprocessor">#define CAN_TDT2R_TIME_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02246" name="l02246"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9585327a9b756069b9a3ee0727e35f19"> 2246</a></span><span class="preprocessor">#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) </span></div>
|
||
<div class="line"><a id="l02247" name="l02247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga508aea584f7c81700b485916a13431fa"> 2247</a></span><span class="preprocessor">#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk </span></div>
|
||
<div class="line"><a id="l02249" name="l02249"></a><span class="lineno"> 2249</span><span class="comment">/******************* Bit definition for CAN_TDL2R register ******************/</span></div>
|
||
<div class="line"><a id="l02250" name="l02250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e9d0286857aaf4744cae03ce9379b74"> 2250</a></span><span class="preprocessor">#define CAN_TDL2R_DATA0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02251" name="l02251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9d44c13085429bc76007fa3aff31964"> 2251</a></span><span class="preprocessor">#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) </span></div>
|
||
<div class="line"><a id="l02252" name="l02252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a9852d0f6058c19f0e678228ea14a21"> 2252</a></span><span class="preprocessor">#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk </span></div>
|
||
<div class="line"><a id="l02253" name="l02253"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58e2da210f0a94f67e20d4c6179034c6"> 2253</a></span><span class="preprocessor">#define CAN_TDL2R_DATA1_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02254" name="l02254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9e6c39a9c27791be19e6cde5f8c45c7"> 2254</a></span><span class="preprocessor">#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) </span></div>
|
||
<div class="line"><a id="l02255" name="l02255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5be1bcda68f562be669184b30727be1"> 2255</a></span><span class="preprocessor">#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk </span></div>
|
||
<div class="line"><a id="l02256" name="l02256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d7a1f37d86fae4a8efd1beb1322a4de"> 2256</a></span><span class="preprocessor">#define CAN_TDL2R_DATA2_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02257" name="l02257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dae494d814d7c4c5785066ffc203f11"> 2257</a></span><span class="preprocessor">#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) </span></div>
|
||
<div class="line"><a id="l02258" name="l02258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62cd5e7f3e98fe5b247998d39ebdd6fb"> 2258</a></span><span class="preprocessor">#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk </span></div>
|
||
<div class="line"><a id="l02259" name="l02259"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b77eb2ec1d44ecd49eae21f5d238a32"> 2259</a></span><span class="preprocessor">#define CAN_TDL2R_DATA3_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02260" name="l02260"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9551d67aa378b224e317e4f298ccd195"> 2260</a></span><span class="preprocessor">#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) </span></div>
|
||
<div class="line"><a id="l02261" name="l02261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d76ed3982f13fb34a54d62f0caa3fa2"> 2261</a></span><span class="preprocessor">#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk </span></div>
|
||
<div class="line"><a id="l02263" name="l02263"></a><span class="lineno"> 2263</span><span class="comment">/******************* Bit definition for CAN_TDH2R register ******************/</span></div>
|
||
<div class="line"><a id="l02264" name="l02264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61800b82cf4fd9229d91e7f9e3ac7158"> 2264</a></span><span class="preprocessor">#define CAN_TDH2R_DATA4_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02265" name="l02265"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae061c8ed2699c7a7be546e5825946c60"> 2265</a></span><span class="preprocessor">#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) </span></div>
|
||
<div class="line"><a id="l02266" name="l02266"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23a93a13da2f302ecd2f0c462065428d"> 2266</a></span><span class="preprocessor">#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk </span></div>
|
||
<div class="line"><a id="l02267" name="l02267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd401f60132154e0d004d262ba48e862"> 2267</a></span><span class="preprocessor">#define CAN_TDH2R_DATA5_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02268" name="l02268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5ace2c6eb67c621bf571e285b76b007"> 2268</a></span><span class="preprocessor">#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) </span></div>
|
||
<div class="line"><a id="l02269" name="l02269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9f372328c8d1e4fe2503d45aed50fb6"> 2269</a></span><span class="preprocessor">#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk </span></div>
|
||
<div class="line"><a id="l02270" name="l02270"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf512e0c618635a2b56048d1712930843"> 2270</a></span><span class="preprocessor">#define CAN_TDH2R_DATA6_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02271" name="l02271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga621fec630f1758b3f11a2e52e62fa970"> 2271</a></span><span class="preprocessor">#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) </span></div>
|
||
<div class="line"><a id="l02272" name="l02272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae96248bcf102a3c6f39f72cdcf8e4fe5"> 2272</a></span><span class="preprocessor">#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk </span></div>
|
||
<div class="line"><a id="l02273" name="l02273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57346e5378ab4dbab77f4f84d5a1e780"> 2273</a></span><span class="preprocessor">#define CAN_TDH2R_DATA7_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02274" name="l02274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee62fccda69811932555a125bce78606"> 2274</a></span><span class="preprocessor">#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) </span></div>
|
||
<div class="line"><a id="l02275" name="l02275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga895341b943e4b01938857b84a0b0dbda"> 2275</a></span><span class="preprocessor">#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk </span></div>
|
||
<div class="line"><a id="l02277" name="l02277"></a><span class="lineno"> 2277</span><span class="comment">/******************* Bit definition for CAN_RI0R register *******************/</span></div>
|
||
<div class="line"><a id="l02278" name="l02278"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1534235598ebdacd295d6e248ca1732f"> 2278</a></span><span class="preprocessor">#define CAN_RI0R_RTR_Pos (1U) </span></div>
|
||
<div class="line"><a id="l02279" name="l02279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga833387b84a95443455bffb4a6390b7b9"> 2279</a></span><span class="preprocessor">#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) </span></div>
|
||
<div class="line"><a id="l02280" name="l02280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41f4780b822a42834bf1927eb92b4fba"> 2280</a></span><span class="preprocessor">#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk </span></div>
|
||
<div class="line"><a id="l02281" name="l02281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1f9c6a0d27ac2f4c05fa3d0f6aab88b"> 2281</a></span><span class="preprocessor">#define CAN_RI0R_IDE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l02282" name="l02282"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80f4b044d79d1e751d54a604b637c26c"> 2282</a></span><span class="preprocessor">#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) </span></div>
|
||
<div class="line"><a id="l02283" name="l02283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga688074182caafff289c921548bc9afca"> 2283</a></span><span class="preprocessor">#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk </span></div>
|
||
<div class="line"><a id="l02284" name="l02284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga782a6732674fa4ee7b2581709d2a45b7"> 2284</a></span><span class="preprocessor">#define CAN_RI0R_EXID_Pos (3U) </span></div>
|
||
<div class="line"><a id="l02285" name="l02285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf95ca68eadd026273958ef22678dc37"> 2285</a></span><span class="preprocessor">#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) </span></div>
|
||
<div class="line"><a id="l02286" name="l02286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d81487e8b340810e3193cd8f1386240"> 2286</a></span><span class="preprocessor">#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk </span></div>
|
||
<div class="line"><a id="l02287" name="l02287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac72774c622ac99f08cc1f7e2814be168"> 2287</a></span><span class="preprocessor">#define CAN_RI0R_STID_Pos (21U) </span></div>
|
||
<div class="line"><a id="l02288" name="l02288"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02a63ecf925c0930d317bdbf439e9486"> 2288</a></span><span class="preprocessor">#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) </span></div>
|
||
<div class="line"><a id="l02289" name="l02289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga101aa355c83b8c7d068f02b7dcc5b98f"> 2289</a></span><span class="preprocessor">#define CAN_RI0R_STID CAN_RI0R_STID_Msk </span></div>
|
||
<div class="line"><a id="l02291" name="l02291"></a><span class="lineno"> 2291</span><span class="comment">/******************* Bit definition for CAN_RDT0R register ******************/</span></div>
|
||
<div class="line"><a id="l02292" name="l02292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabcb714f10d7dba636a67e79c0473dbf9"> 2292</a></span><span class="preprocessor">#define CAN_RDT0R_DLC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02293" name="l02293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace43bd7d7388fd3cf4c33142d62ef541"> 2293</a></span><span class="preprocessor">#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) </span></div>
|
||
<div class="line"><a id="l02294" name="l02294"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17ca0af4afd89e6a1c43ffd1430359b7"> 2294</a></span><span class="preprocessor">#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk </span></div>
|
||
<div class="line"><a id="l02295" name="l02295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6076b1e14b5a81a0a25e4e8973a28477"> 2295</a></span><span class="preprocessor">#define CAN_RDT0R_FMI_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02296" name="l02296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9bafb8a31e8370f9d068a1acfe30e222"> 2296</a></span><span class="preprocessor">#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) </span></div>
|
||
<div class="line"><a id="l02297" name="l02297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5081739b6e21e033b95e68af9331a6d1"> 2297</a></span><span class="preprocessor">#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk </span></div>
|
||
<div class="line"><a id="l02298" name="l02298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44d89e7d66e3f4c953cbaeb271a30ada"> 2298</a></span><span class="preprocessor">#define CAN_RDT0R_TIME_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02299" name="l02299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcf8581ecb0c6b9bf464155b93f1003a"> 2299</a></span><span class="preprocessor">#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) </span></div>
|
||
<div class="line"><a id="l02300" name="l02300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae20b7a72690033591eeda7a511ac4a2e"> 2300</a></span><span class="preprocessor">#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk </span></div>
|
||
<div class="line"><a id="l02302" name="l02302"></a><span class="lineno"> 2302</span><span class="comment">/******************* Bit definition for CAN_RDL0R register ******************/</span></div>
|
||
<div class="line"><a id="l02303" name="l02303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd7172931b3e1d8cf3daba5edfdd42c4"> 2303</a></span><span class="preprocessor">#define CAN_RDL0R_DATA0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02304" name="l02304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15f91b45288700ef7858e998d598ea21"> 2304</a></span><span class="preprocessor">#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) </span></div>
|
||
<div class="line"><a id="l02305" name="l02305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44313106efc3a5a65633168a2ad1928d"> 2305</a></span><span class="preprocessor">#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk </span></div>
|
||
<div class="line"><a id="l02306" name="l02306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab942d411c058da0f504d49adabdf7f11"> 2306</a></span><span class="preprocessor">#define CAN_RDL0R_DATA1_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02307" name="l02307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86f144804d9b849f9bf589f9d0d53b4c"> 2307</a></span><span class="preprocessor">#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) </span></div>
|
||
<div class="line"><a id="l02308" name="l02308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73d4025ce501af78db93761e8b8c3b9e"> 2308</a></span><span class="preprocessor">#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk </span></div>
|
||
<div class="line"><a id="l02309" name="l02309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe0336c208a9884936f3527688c349de"> 2309</a></span><span class="preprocessor">#define CAN_RDL0R_DATA2_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02310" name="l02310"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75e00e47c6f9bab7a6602af43e7d9d4d"> 2310</a></span><span class="preprocessor">#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) </span></div>
|
||
<div class="line"><a id="l02311" name="l02311"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52b3c31ad72881e11a4d3cae073a0df8"> 2311</a></span><span class="preprocessor">#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk </span></div>
|
||
<div class="line"><a id="l02312" name="l02312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga839a3d98930a4ab823b30dc7ac805e9a"> 2312</a></span><span class="preprocessor">#define CAN_RDL0R_DATA3_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02313" name="l02313"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0b46bd6794046d7c70d8db43a5c5524"> 2313</a></span><span class="preprocessor">#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) </span></div>
|
||
<div class="line"><a id="l02314" name="l02314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad637a53ae780998f95f2bb570d5cd05a"> 2314</a></span><span class="preprocessor">#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk </span></div>
|
||
<div class="line"><a id="l02316" name="l02316"></a><span class="lineno"> 2316</span><span class="comment">/******************* Bit definition for CAN_RDH0R register ******************/</span></div>
|
||
<div class="line"><a id="l02317" name="l02317"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cb8238c1f77ff904290afdc572b31bc"> 2317</a></span><span class="preprocessor">#define CAN_RDH0R_DATA4_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02318" name="l02318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga043ce7187baa93bc909445ec56a283b1"> 2318</a></span><span class="preprocessor">#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) </span></div>
|
||
<div class="line"><a id="l02319" name="l02319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dc7309c31cda93d05bb1fe1c923646c"> 2319</a></span><span class="preprocessor">#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk </span></div>
|
||
<div class="line"><a id="l02320" name="l02320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafeef959f9d8913e402c9a08f964da52f"> 2320</a></span><span class="preprocessor">#define CAN_RDH0R_DATA5_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02321" name="l02321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a76bc6ca34c282e8d5e6d80de4d2ae6"> 2321</a></span><span class="preprocessor">#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) </span></div>
|
||
<div class="line"><a id="l02322" name="l02322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga577eba5ab3a66283f5c0837e91f1776a"> 2322</a></span><span class="preprocessor">#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk </span></div>
|
||
<div class="line"><a id="l02323" name="l02323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e54ca30453b2103004ca2b87da2e052"> 2323</a></span><span class="preprocessor">#define CAN_RDH0R_DATA6_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02324" name="l02324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ea6c132f074602725c9d14d4a66826c"> 2324</a></span><span class="preprocessor">#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) </span></div>
|
||
<div class="line"><a id="l02325" name="l02325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27a0bd49dc24e59b776ad5a00aabb97b"> 2325</a></span><span class="preprocessor">#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk </span></div>
|
||
<div class="line"><a id="l02326" name="l02326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga676e501253a8d78d74a13f9dbc87d222"> 2326</a></span><span class="preprocessor">#define CAN_RDH0R_DATA7_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02327" name="l02327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga167fa92520367130afbb5e929ff8b542"> 2327</a></span><span class="preprocessor">#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) </span></div>
|
||
<div class="line"><a id="l02328" name="l02328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga243b8a3632812b2f8c7b447ed635ce5f"> 2328</a></span><span class="preprocessor">#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk </span></div>
|
||
<div class="line"><a id="l02330" name="l02330"></a><span class="lineno"> 2330</span><span class="comment">/******************* Bit definition for CAN_RI1R register *******************/</span></div>
|
||
<div class="line"><a id="l02331" name="l02331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga726ed3ef9d26e53ea346a23731e0e967"> 2331</a></span><span class="preprocessor">#define CAN_RI1R_RTR_Pos (1U) </span></div>
|
||
<div class="line"><a id="l02332" name="l02332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e9658541637a4332c1ccf67b34a8fb9"> 2332</a></span><span class="preprocessor">#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) </span></div>
|
||
<div class="line"><a id="l02333" name="l02333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbd0ecd9579a339bffb95ea3b7c9f1e8"> 2333</a></span><span class="preprocessor">#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk </span></div>
|
||
<div class="line"><a id="l02334" name="l02334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0367ce97761605b4cdc45b529f791417"> 2334</a></span><span class="preprocessor">#define CAN_RI1R_IDE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l02335" name="l02335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68b6e874a467bca60ef46e3ffb30f098"> 2335</a></span><span class="preprocessor">#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) </span></div>
|
||
<div class="line"><a id="l02336" name="l02336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8dcedeb4250767a66a4d60c67e367cf8"> 2336</a></span><span class="preprocessor">#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk </span></div>
|
||
<div class="line"><a id="l02337" name="l02337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd36dce59fa984a072c332c0fae7a29a"> 2337</a></span><span class="preprocessor">#define CAN_RI1R_EXID_Pos (3U) </span></div>
|
||
<div class="line"><a id="l02338" name="l02338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f8b1261a02cdc318caab37e7cff0f5f"> 2338</a></span><span class="preprocessor">#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) </span></div>
|
||
<div class="line"><a id="l02339" name="l02339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ca45b282f2582c91450d4e1204121cf"> 2339</a></span><span class="preprocessor">#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk </span></div>
|
||
<div class="line"><a id="l02340" name="l02340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7488f084446b0c0907a5f4851f48d38c"> 2340</a></span><span class="preprocessor">#define CAN_RI1R_STID_Pos (21U) </span></div>
|
||
<div class="line"><a id="l02341" name="l02341"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27b4d8511b43ff7f56e18c15c6b260e0"> 2341</a></span><span class="preprocessor">#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) </span></div>
|
||
<div class="line"><a id="l02342" name="l02342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f3c3aab0f24533821188d14901b3980"> 2342</a></span><span class="preprocessor">#define CAN_RI1R_STID CAN_RI1R_STID_Msk </span></div>
|
||
<div class="line"><a id="l02344" name="l02344"></a><span class="lineno"> 2344</span><span class="comment">/******************* Bit definition for CAN_RDT1R register ******************/</span></div>
|
||
<div class="line"><a id="l02345" name="l02345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2e0b7a55b05caab1a213c35742696a6"> 2345</a></span><span class="preprocessor">#define CAN_RDT1R_DLC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02346" name="l02346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa33d633807f57ecc34d45c20e704a330"> 2346</a></span><span class="preprocessor">#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) </span></div>
|
||
<div class="line"><a id="l02347" name="l02347"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga964b0fa7c70a24a74165c57b3486aae8"> 2347</a></span><span class="preprocessor">#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk </span></div>
|
||
<div class="line"><a id="l02348" name="l02348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga683fd9390aff2459ef66760d02f7f654"> 2348</a></span><span class="preprocessor">#define CAN_RDT1R_FMI_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02349" name="l02349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41ca9a71d5f237de7e4d758b2b5850b5"> 2349</a></span><span class="preprocessor">#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) </span></div>
|
||
<div class="line"><a id="l02350" name="l02350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7f72aec91130a20e3a855e78eabb48b"> 2350</a></span><span class="preprocessor">#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk </span></div>
|
||
<div class="line"><a id="l02351" name="l02351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a2fdfc1f548be70a30752803fea6a27"> 2351</a></span><span class="preprocessor">#define CAN_RDT1R_TIME_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02352" name="l02352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22e450deb1ed7a778b47b4cebad44f42"> 2352</a></span><span class="preprocessor">#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) </span></div>
|
||
<div class="line"><a id="l02353" name="l02353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac112cba5a4cd0b541c1150263132c68a"> 2353</a></span><span class="preprocessor">#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk </span></div>
|
||
<div class="line"><a id="l02355" name="l02355"></a><span class="lineno"> 2355</span><span class="comment">/******************* Bit definition for CAN_RDL1R register ******************/</span></div>
|
||
<div class="line"><a id="l02356" name="l02356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5c0ebcd26923922b646df3064f4d5ad"> 2356</a></span><span class="preprocessor">#define CAN_RDL1R_DATA0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02357" name="l02357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d11f01bf6ac61f279f5227e5cfa87ac"> 2357</a></span><span class="preprocessor">#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) </span></div>
|
||
<div class="line"><a id="l02358" name="l02358"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e399fed282a5aac0b25b059fcf04020"> 2358</a></span><span class="preprocessor">#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk </span></div>
|
||
<div class="line"><a id="l02359" name="l02359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac291bf56ea60efcd3123d4c89fcc00fb"> 2359</a></span><span class="preprocessor">#define CAN_RDL1R_DATA1_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02360" name="l02360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2754a3d3971d890a60306c923f4c027d"> 2360</a></span><span class="preprocessor">#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) </span></div>
|
||
<div class="line"><a id="l02361" name="l02361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27ec34e08f87e8836f32bbfed52e860a"> 2361</a></span><span class="preprocessor">#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk </span></div>
|
||
<div class="line"><a id="l02362" name="l02362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38f1bee2b3aac2261c4f9c5aa92550bc"> 2362</a></span><span class="preprocessor">#define CAN_RDL1R_DATA2_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02363" name="l02363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5ea71525f58798512e56b01db47f6d5"> 2363</a></span><span class="preprocessor">#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) </span></div>
|
||
<div class="line"><a id="l02364" name="l02364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea34eded40932d364743969643a598c4"> 2364</a></span><span class="preprocessor">#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk </span></div>
|
||
<div class="line"><a id="l02365" name="l02365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f201d587103efa2fc6da443415d7127"> 2365</a></span><span class="preprocessor">#define CAN_RDL1R_DATA3_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02366" name="l02366"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02684a0300f1d9e9c803b5afefb193fc"> 2366</a></span><span class="preprocessor">#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) </span></div>
|
||
<div class="line"><a id="l02367" name="l02367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80bfe3e724b28e8d2a5b7ac4393212cf"> 2367</a></span><span class="preprocessor">#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk </span></div>
|
||
<div class="line"><a id="l02369" name="l02369"></a><span class="lineno"> 2369</span><span class="comment">/******************* Bit definition for CAN_RDH1R register ******************/</span></div>
|
||
<div class="line"><a id="l02370" name="l02370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48e5ea8ab1e1cf135a10b2dbc69932f2"> 2370</a></span><span class="preprocessor">#define CAN_RDH1R_DATA4_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02371" name="l02371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e0ca00fb558f95f4f692d5f7b90d157"> 2371</a></span><span class="preprocessor">#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) </span></div>
|
||
<div class="line"><a id="l02372" name="l02372"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc2a55c1b5195cf043ef33e79d736255"> 2372</a></span><span class="preprocessor">#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk </span></div>
|
||
<div class="line"><a id="l02373" name="l02373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacb82a6a71a2687b303c54a5c3aca105"> 2373</a></span><span class="preprocessor">#define CAN_RDH1R_DATA5_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02374" name="l02374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga247617fd1c2c8daa148b3ed059f0603a"> 2374</a></span><span class="preprocessor">#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) </span></div>
|
||
<div class="line"><a id="l02375" name="l02375"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81d25a1ea5ad28e7db4a2adbb8a651ad"> 2375</a></span><span class="preprocessor">#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk </span></div>
|
||
<div class="line"><a id="l02376" name="l02376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab2ec9fa28c3b6f72ed102d5d255e875"> 2376</a></span><span class="preprocessor">#define CAN_RDH1R_DATA6_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02377" name="l02377"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5eeec37fc704ce7cf1c9ef92f6d87635"> 2377</a></span><span class="preprocessor">#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) </span></div>
|
||
<div class="line"><a id="l02378" name="l02378"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39212ea40388510bde1931f7b3a064ae"> 2378</a></span><span class="preprocessor">#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk </span></div>
|
||
<div class="line"><a id="l02379" name="l02379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga021f76c67a2d07b56c4e10cd56cc416a"> 2379</a></span><span class="preprocessor">#define CAN_RDH1R_DATA7_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02380" name="l02380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9e7a5ddb046143d3ca7c85ddb9c94c0"> 2380</a></span><span class="preprocessor">#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) </span></div>
|
||
<div class="line"><a id="l02381" name="l02381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdfbb90b5ef2ac1e7f23a5f15c0287eb"> 2381</a></span><span class="preprocessor">#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk </span></div>
|
||
<div class="line"><a id="l02384" name="l02384"></a><span class="lineno"> 2384</span><span class="comment">/******************* Bit definition for CAN_FMR register ********************/</span></div>
|
||
<div class="line"><a id="l02385" name="l02385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d07843af8269762b43ed1bef5fc29b3"> 2385</a></span><span class="preprocessor">#define CAN_FMR_FINIT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02386" name="l02386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99a8549f1c1784779e00b257c216102d"> 2386</a></span><span class="preprocessor">#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) </span></div>
|
||
<div class="line"><a id="l02387" name="l02387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5eb5b835ee11a78bd391b9d1049f2549"> 2387</a></span><span class="preprocessor">#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk </span></div>
|
||
<div class="line"><a id="l02388" name="l02388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaaea537f2e7bfc1d90c43a60d12145b7"> 2388</a></span><span class="preprocessor">#define CAN_FMR_CAN2SB_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02389" name="l02389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92c82386fd3904c98b94f78cfb9570d2"> 2389</a></span><span class="preprocessor">#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) </span></div>
|
||
<div class="line"><a id="l02390" name="l02390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3753c67c075a4508104d112ef9047f21"> 2390</a></span><span class="preprocessor">#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk </span></div>
|
||
<div class="line"><a id="l02392" name="l02392"></a><span class="lineno"> 2392</span><span class="comment">/******************* Bit definition for CAN_FM1R register *******************/</span></div>
|
||
<div class="line"><a id="l02393" name="l02393"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa97dffd3da7f8927e2168a6dce9d8312"> 2393</a></span><span class="preprocessor">#define CAN_FM1R_FBM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02394" name="l02394"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97376a7949c1758c1f294cc9a85cbe8c"> 2394</a></span><span class="preprocessor">#define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos) </span></div>
|
||
<div class="line"><a id="l02395" name="l02395"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga481099e17a895e92cfbcfca617d52860"> 2395</a></span><span class="preprocessor">#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk </span></div>
|
||
<div class="line"><a id="l02396" name="l02396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab47e86b4f2e3c77569cfe84fbcb8806b"> 2396</a></span><span class="preprocessor">#define CAN_FM1R_FBM0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02397" name="l02397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19e1fd75a24ae366d58b0a18e15f38bf"> 2397</a></span><span class="preprocessor">#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) </span></div>
|
||
<div class="line"><a id="l02398" name="l02398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d95ff05ed6ef9a38e9af9c0d3db3687"> 2398</a></span><span class="preprocessor">#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk </span></div>
|
||
<div class="line"><a id="l02399" name="l02399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56b3a50f8a5df07e09f78d165ae0ebb0"> 2399</a></span><span class="preprocessor">#define CAN_FM1R_FBM1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l02400" name="l02400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad57540467b1e1e98c24df335d72b6715"> 2400</a></span><span class="preprocessor">#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) </span></div>
|
||
<div class="line"><a id="l02401" name="l02401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2839d73344a7601aa22b5ed3fc0e5d1"> 2401</a></span><span class="preprocessor">#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk </span></div>
|
||
<div class="line"><a id="l02402" name="l02402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9893bef42453161269747598ec908d49"> 2402</a></span><span class="preprocessor">#define CAN_FM1R_FBM2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l02403" name="l02403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab036323d5ff180c94cb011bda0e93738"> 2403</a></span><span class="preprocessor">#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) </span></div>
|
||
<div class="line"><a id="l02404" name="l02404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ba7963ac4eb5b936c444258c13f8940"> 2404</a></span><span class="preprocessor">#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk </span></div>
|
||
<div class="line"><a id="l02405" name="l02405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga612d9e0e776abfcdbc2b24a964d6ab6e"> 2405</a></span><span class="preprocessor">#define CAN_FM1R_FBM3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l02406" name="l02406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8514f94421b8d4665c84a5e09ea814b6"> 2406</a></span><span class="preprocessor">#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) </span></div>
|
||
<div class="line"><a id="l02407" name="l02407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d129b27c2af41ae39e606e802a53386"> 2407</a></span><span class="preprocessor">#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk </span></div>
|
||
<div class="line"><a id="l02408" name="l02408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb58de50d9b0a1508617d885f052d7a6"> 2408</a></span><span class="preprocessor">#define CAN_FM1R_FBM4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l02409" name="l02409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bca8d2dab6ca215db7dfe45702c9c88"> 2409</a></span><span class="preprocessor">#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) </span></div>
|
||
<div class="line"><a id="l02410" name="l02410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0c94e5f4dcceea510fc72b86128aff3"> 2410</a></span><span class="preprocessor">#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk </span></div>
|
||
<div class="line"><a id="l02411" name="l02411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b8f80f23a5ab8f322c9b4b441a8d768"> 2411</a></span><span class="preprocessor">#define CAN_FM1R_FBM5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l02412" name="l02412"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8534298a873d6eeba40f67ccd8e44dc"> 2412</a></span><span class="preprocessor">#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) </span></div>
|
||
<div class="line"><a id="l02413" name="l02413"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d7fb7c366544a1ef7a85481d3e6325d"> 2413</a></span><span class="preprocessor">#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk </span></div>
|
||
<div class="line"><a id="l02414" name="l02414"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4a556397deec72a65aec5ec5600e16f"> 2414</a></span><span class="preprocessor">#define CAN_FM1R_FBM6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l02415" name="l02415"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e635abf1f1fda09814600ac218b25a5"> 2415</a></span><span class="preprocessor">#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) </span></div>
|
||
<div class="line"><a id="l02416" name="l02416"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ff70e74447679a0d1cde1aa69ea2db1"> 2416</a></span><span class="preprocessor">#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk </span></div>
|
||
<div class="line"><a id="l02417" name="l02417"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2d58da6b63e9ebe66d43e438f0df884"> 2417</a></span><span class="preprocessor">#define CAN_FM1R_FBM7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l02418" name="l02418"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e697f5e347652a49756219c13e6cc89"> 2418</a></span><span class="preprocessor">#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) </span></div>
|
||
<div class="line"><a id="l02419" name="l02419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga657fc12fd334bc626b2eb53fb03457b0"> 2419</a></span><span class="preprocessor">#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk </span></div>
|
||
<div class="line"><a id="l02420" name="l02420"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30b41b013fad0569137363aa33b5fd8e"> 2420</a></span><span class="preprocessor">#define CAN_FM1R_FBM8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02421" name="l02421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b3e86a2ff5df79cb0d1fc1d09da5309"> 2421</a></span><span class="preprocessor">#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) </span></div>
|
||
<div class="line"><a id="l02422" name="l02422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6bc390ed9a658014fd09fd1073e3037"> 2422</a></span><span class="preprocessor">#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk </span></div>
|
||
<div class="line"><a id="l02423" name="l02423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae891964bdca74710cfb7a1587b9c75a2"> 2423</a></span><span class="preprocessor">#define CAN_FM1R_FBM9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l02424" name="l02424"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9787e28f4d47535624b593b042e7aef"> 2424</a></span><span class="preprocessor">#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) </span></div>
|
||
<div class="line"><a id="l02425" name="l02425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga375758246b99234dda725b7c64daff32"> 2425</a></span><span class="preprocessor">#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk </span></div>
|
||
<div class="line"><a id="l02426" name="l02426"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4c4d40f98e3c5e6116b323184afca0a"> 2426</a></span><span class="preprocessor">#define CAN_FM1R_FBM10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l02427" name="l02427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb10a1a029fdb320217c7443225df7f8"> 2427</a></span><span class="preprocessor">#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) </span></div>
|
||
<div class="line"><a id="l02428" name="l02428"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a98c6bde07c570463b6c0e32c0f6805"> 2428</a></span><span class="preprocessor">#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk </span></div>
|
||
<div class="line"><a id="l02429" name="l02429"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8310bf4c9b121dad00152f0d9e0aaf3d"> 2429</a></span><span class="preprocessor">#define CAN_FM1R_FBM11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l02430" name="l02430"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa8a7616c4e1d6b08a96a629877107ad"> 2430</a></span><span class="preprocessor">#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) </span></div>
|
||
<div class="line"><a id="l02431" name="l02431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab88796333c19954176ef77208cae4964"> 2431</a></span><span class="preprocessor">#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk </span></div>
|
||
<div class="line"><a id="l02432" name="l02432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c1c28f5a8c8f6e7c1203c3268307e7d"> 2432</a></span><span class="preprocessor">#define CAN_FM1R_FBM12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l02433" name="l02433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8b7c4c9581b2f876fe0cdf0bba3edaf"> 2433</a></span><span class="preprocessor">#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) </span></div>
|
||
<div class="line"><a id="l02434" name="l02434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga858eaac0a8e23c03e13e5c1736bf9842"> 2434</a></span><span class="preprocessor">#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk </span></div>
|
||
<div class="line"><a id="l02435" name="l02435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga510dd73a783e59a7d85c00d8190c89db"> 2435</a></span><span class="preprocessor">#define CAN_FM1R_FBM13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l02436" name="l02436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13e0f2dc1023e882b4f2392c68444858"> 2436</a></span><span class="preprocessor">#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) </span></div>
|
||
<div class="line"><a id="l02437" name="l02437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf03b553802edd3ae23b70e97228b6dcc"> 2437</a></span><span class="preprocessor">#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk </span></div>
|
||
<div class="line"><a id="l02438" name="l02438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b3286a1f53a442b35a01c37ea2f1f08"> 2438</a></span><span class="preprocessor">#define CAN_FM1R_FBM14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l02439" name="l02439"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bc6cdb01d2d74ae091d20b682ceb0e3"> 2439</a></span><span class="preprocessor">#define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos) </span></div>
|
||
<div class="line"><a id="l02440" name="l02440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae348cc5bec6eecd8a188c3e90a9618d1"> 2440</a></span><span class="preprocessor">#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk </span></div>
|
||
<div class="line"><a id="l02441" name="l02441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa1a315f40ac71ced3066bf3edd9b459"> 2441</a></span><span class="preprocessor">#define CAN_FM1R_FBM15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l02442" name="l02442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d59e547e543eeddb35d6d003b18458c"> 2442</a></span><span class="preprocessor">#define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos) </span></div>
|
||
<div class="line"><a id="l02443" name="l02443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga815c710d287cec5c46a901d01e4cac76"> 2443</a></span><span class="preprocessor">#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk </span></div>
|
||
<div class="line"><a id="l02444" name="l02444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a18fbe03eb8d83dc877be06ecdc7810"> 2444</a></span><span class="preprocessor">#define CAN_FM1R_FBM16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02445" name="l02445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd51db2c7330341bf43bb888e63a61f5"> 2445</a></span><span class="preprocessor">#define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos) </span></div>
|
||
<div class="line"><a id="l02446" name="l02446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6500fcdf1baf5d5019364ad155e30bf0"> 2446</a></span><span class="preprocessor">#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk </span></div>
|
||
<div class="line"><a id="l02447" name="l02447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5b340bc770061dc909bbf5761db8352"> 2447</a></span><span class="preprocessor">#define CAN_FM1R_FBM17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l02448" name="l02448"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54acc06d013985e059388599e2df40b7"> 2448</a></span><span class="preprocessor">#define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos) </span></div>
|
||
<div class="line"><a id="l02449" name="l02449"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga698a1a5cf309ba539973ad61a08ed531"> 2449</a></span><span class="preprocessor">#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk </span></div>
|
||
<div class="line"><a id="l02450" name="l02450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7c2e03e37aa98be8846eb3582a59515"> 2450</a></span><span class="preprocessor">#define CAN_FM1R_FBM18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l02451" name="l02451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7251ea74eaf728ad4538cd5a6ac34eaa"> 2451</a></span><span class="preprocessor">#define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos) </span></div>
|
||
<div class="line"><a id="l02452" name="l02452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa47585a76a3ddf465abad7176e993ca1"> 2452</a></span><span class="preprocessor">#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk </span></div>
|
||
<div class="line"><a id="l02453" name="l02453"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga728ea8bee75db988971d2f69cef3aa9a"> 2453</a></span><span class="preprocessor">#define CAN_FM1R_FBM19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l02454" name="l02454"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga185b29bf8e41d61399645ccab8efdf07"> 2454</a></span><span class="preprocessor">#define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos) </span></div>
|
||
<div class="line"><a id="l02455" name="l02455"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70c9e6ce3b2e262912480c533cb94c30"> 2455</a></span><span class="preprocessor">#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk </span></div>
|
||
<div class="line"><a id="l02456" name="l02456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae918f1bdbe01f6350fe05cad4d2c07fc"> 2456</a></span><span class="preprocessor">#define CAN_FM1R_FBM20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l02457" name="l02457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3557afecc8db6dab2c8ab6a19a76b245"> 2457</a></span><span class="preprocessor">#define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos) </span></div>
|
||
<div class="line"><a id="l02458" name="l02458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4af2f860f3d7c3bf3509daf366143baf"> 2458</a></span><span class="preprocessor">#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk </span></div>
|
||
<div class="line"><a id="l02459" name="l02459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7890f90e73ef96b5497aeca708dd950a"> 2459</a></span><span class="preprocessor">#define CAN_FM1R_FBM21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l02460" name="l02460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c4575301b441f99be4fecfbdc0c06a5"> 2460</a></span><span class="preprocessor">#define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos) </span></div>
|
||
<div class="line"><a id="l02461" name="l02461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9bfdcf62b11bffb9afbee7f6258f089b"> 2461</a></span><span class="preprocessor">#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk </span></div>
|
||
<div class="line"><a id="l02462" name="l02462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e18237e288612926c6e8855345b2d47"> 2462</a></span><span class="preprocessor">#define CAN_FM1R_FBM22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l02463" name="l02463"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad10cf074d53c11a4700ad7983e2ba34"> 2463</a></span><span class="preprocessor">#define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos) </span></div>
|
||
<div class="line"><a id="l02464" name="l02464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67e71ecc049fe1c882be5e03aaecdc01"> 2464</a></span><span class="preprocessor">#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk </span></div>
|
||
<div class="line"><a id="l02465" name="l02465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ced626c3b41a506cd8cd737c03fe787"> 2465</a></span><span class="preprocessor">#define CAN_FM1R_FBM23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l02466" name="l02466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d600617dc97adc1e75a2abcf1909d3b"> 2466</a></span><span class="preprocessor">#define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos) </span></div>
|
||
<div class="line"><a id="l02467" name="l02467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70ac1d53ad6dbc162272b92aa704eff4"> 2467</a></span><span class="preprocessor">#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk </span></div>
|
||
<div class="line"><a id="l02468" name="l02468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea93cbe9b69f821ed9475b0585c15637"> 2468</a></span><span class="preprocessor">#define CAN_FM1R_FBM24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02469" name="l02469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d68bf08a503f10fa7c9728ddafa8ed7"> 2469</a></span><span class="preprocessor">#define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos) </span></div>
|
||
<div class="line"><a id="l02470" name="l02470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2befceefa1b4600adb96b1150a738dcf"> 2470</a></span><span class="preprocessor">#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk </span></div>
|
||
<div class="line"><a id="l02471" name="l02471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cf69597e272b2e3db7bb54b60609553"> 2471</a></span><span class="preprocessor">#define CAN_FM1R_FBM25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l02472" name="l02472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4f8c432102ad6270ae8c8faa92599e7"> 2472</a></span><span class="preprocessor">#define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos) </span></div>
|
||
<div class="line"><a id="l02473" name="l02473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8302ff02a952e32bd6cb5d8ce17ef94"> 2473</a></span><span class="preprocessor">#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk </span></div>
|
||
<div class="line"><a id="l02474" name="l02474"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20c45ed77383fe5ccf21614fe569ab6e"> 2474</a></span><span class="preprocessor">#define CAN_FM1R_FBM26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l02475" name="l02475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83528f848c64886be406a292c49f6b55"> 2475</a></span><span class="preprocessor">#define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos) </span></div>
|
||
<div class="line"><a id="l02476" name="l02476"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ea4af83b76361928669dc1de5681bd5"> 2476</a></span><span class="preprocessor">#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk </span></div>
|
||
<div class="line"><a id="l02477" name="l02477"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9dbac6ff3f18e5f1104e326dc24302bf"> 2477</a></span><span class="preprocessor">#define CAN_FM1R_FBM27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l02478" name="l02478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf50cb4ff71b1cf38397efdff320e80cb"> 2478</a></span><span class="preprocessor">#define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos) </span></div>
|
||
<div class="line"><a id="l02479" name="l02479"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40ca208f170b85611874b2f832623aa8"> 2479</a></span><span class="preprocessor">#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk </span></div>
|
||
<div class="line"><a id="l02481" name="l02481"></a><span class="lineno"> 2481</span><span class="comment">/******************* Bit definition for CAN_FS1R register *******************/</span></div>
|
||
<div class="line"><a id="l02482" name="l02482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada2ff6f825375b0d42b92e7446a4e39c"> 2482</a></span><span class="preprocessor">#define CAN_FS1R_FSC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02483" name="l02483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f5fd354abb81f726d16ba3df34d75d2"> 2483</a></span><span class="preprocessor">#define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos) </span></div>
|
||
<div class="line"><a id="l02484" name="l02484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab41471f35878bcdff72d9cd05acf4714"> 2484</a></span><span class="preprocessor">#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk </span></div>
|
||
<div class="line"><a id="l02485" name="l02485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga975c66c5f2d56c2ba83d022200c37958"> 2485</a></span><span class="preprocessor">#define CAN_FS1R_FSC0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02486" name="l02486"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga521e7ed67be2a02528c2dd393abf8980"> 2486</a></span><span class="preprocessor">#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) </span></div>
|
||
<div class="line"><a id="l02487" name="l02487"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab5ea9e0ed17df35894fff7828c89cad"> 2487</a></span><span class="preprocessor">#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk </span></div>
|
||
<div class="line"><a id="l02488" name="l02488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga642ead0693a426283dce755b276cc60b"> 2488</a></span><span class="preprocessor">#define CAN_FS1R_FSC1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l02489" name="l02489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1084aab8cb7c0fa2ebb1d54c8b1e5aec"> 2489</a></span><span class="preprocessor">#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) </span></div>
|
||
<div class="line"><a id="l02490" name="l02490"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83304e93d2e75c1cd8bfe7c2ec30c1c8"> 2490</a></span><span class="preprocessor">#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk </span></div>
|
||
<div class="line"><a id="l02491" name="l02491"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7026c45f4a48271ab35dd5e090c4568c"> 2491</a></span><span class="preprocessor">#define CAN_FS1R_FSC2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l02492" name="l02492"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5c2bf5abff8b81f574f616837e91391"> 2492</a></span><span class="preprocessor">#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) </span></div>
|
||
<div class="line"><a id="l02493" name="l02493"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ba1fa61fcf851188a6f16323dda1358"> 2493</a></span><span class="preprocessor">#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk </span></div>
|
||
<div class="line"><a id="l02494" name="l02494"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4262b5fb400ad83240758a8e0033bb98"> 2494</a></span><span class="preprocessor">#define CAN_FS1R_FSC3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l02495" name="l02495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8783da3e87efcfa99529dc7f6d3e9b8e"> 2495</a></span><span class="preprocessor">#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) </span></div>
|
||
<div class="line"><a id="l02496" name="l02496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2175f52f4308c088458f9e54a1f1354"> 2496</a></span><span class="preprocessor">#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk </span></div>
|
||
<div class="line"><a id="l02497" name="l02497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba967abdc8c83c0d6e4590c691c16c1c"> 2497</a></span><span class="preprocessor">#define CAN_FS1R_FSC4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l02498" name="l02498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31ca51fc93d252a1a57a65ebf4163c46"> 2498</a></span><span class="preprocessor">#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) </span></div>
|
||
<div class="line"><a id="l02499" name="l02499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga791ac090d6a8f2c79cd72f9072aef30f"> 2499</a></span><span class="preprocessor">#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk </span></div>
|
||
<div class="line"><a id="l02500" name="l02500"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13a409ade293eec6d218a684042312d3"> 2500</a></span><span class="preprocessor">#define CAN_FS1R_FSC5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l02501" name="l02501"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f3efc361a57e98dc7fd35b9ad6db3f3"> 2501</a></span><span class="preprocessor">#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) </span></div>
|
||
<div class="line"><a id="l02502" name="l02502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb4ef2030ec70a4635ca4ac38cca76cb"> 2502</a></span><span class="preprocessor">#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk </span></div>
|
||
<div class="line"><a id="l02503" name="l02503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8cf40d32e952d3fddc0cdc49ef695b5"> 2503</a></span><span class="preprocessor">#define CAN_FS1R_FSC6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l02504" name="l02504"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a42808ce8e7e8c94c7a1748bc42b256"> 2504</a></span><span class="preprocessor">#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) </span></div>
|
||
<div class="line"><a id="l02505" name="l02505"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf015be41f803007b9d0b2f3371e3621b"> 2505</a></span><span class="preprocessor">#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk </span></div>
|
||
<div class="line"><a id="l02506" name="l02506"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8936fed15d6db3d7d1079851f2cf3679"> 2506</a></span><span class="preprocessor">#define CAN_FS1R_FSC7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l02507" name="l02507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68d4a45e6f9068e4c7ed2af48eeb9e16"> 2507</a></span><span class="preprocessor">#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) </span></div>
|
||
<div class="line"><a id="l02508" name="l02508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga206d175417e2c787b44b0734708a5c9a"> 2508</a></span><span class="preprocessor">#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk </span></div>
|
||
<div class="line"><a id="l02509" name="l02509"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed8e8f6dee42172cd578e1abab937b8b"> 2509</a></span><span class="preprocessor">#define CAN_FS1R_FSC8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02510" name="l02510"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab90fee6d415260e5eb61df78ff0bbc3d"> 2510</a></span><span class="preprocessor">#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) </span></div>
|
||
<div class="line"><a id="l02511" name="l02511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7209f008874dadf147cb5357ee46c226"> 2511</a></span><span class="preprocessor">#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk </span></div>
|
||
<div class="line"><a id="l02512" name="l02512"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d172244d6448c45cb6be5d36474a4e1"> 2512</a></span><span class="preprocessor">#define CAN_FS1R_FSC9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l02513" name="l02513"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fb2cac86c92bee0c7d29a1ee401aaa0"> 2513</a></span><span class="preprocessor">#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) </span></div>
|
||
<div class="line"><a id="l02514" name="l02514"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58b4d8fa56d898ad6bf66ba8a4e098eb"> 2514</a></span><span class="preprocessor">#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk </span></div>
|
||
<div class="line"><a id="l02515" name="l02515"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaba757c59e5d37c1acdbed8af1ab90b4"> 2515</a></span><span class="preprocessor">#define CAN_FS1R_FSC10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l02516" name="l02516"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4915e6d23184afe98e5669b2575bfad"> 2516</a></span><span class="preprocessor">#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) </span></div>
|
||
<div class="line"><a id="l02517" name="l02517"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93162a66091ffd4829ed8265f53fe977"> 2517</a></span><span class="preprocessor">#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk </span></div>
|
||
<div class="line"><a id="l02518" name="l02518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2dd37596f667cdfd2771f05b413633e"> 2518</a></span><span class="preprocessor">#define CAN_FS1R_FSC11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l02519" name="l02519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17d1cabb7f95d9e773867888654ea3b0"> 2519</a></span><span class="preprocessor">#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) </span></div>
|
||
<div class="line"><a id="l02520" name="l02520"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2e0bf399ea9175123c95c7010ef527d"> 2520</a></span><span class="preprocessor">#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk </span></div>
|
||
<div class="line"><a id="l02521" name="l02521"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84011d0e3b79daa5ce4c9a076e774bca"> 2521</a></span><span class="preprocessor">#define CAN_FS1R_FSC12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l02522" name="l02522"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad12de017f6c66c2b893b34d99c36c031"> 2522</a></span><span class="preprocessor">#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) </span></div>
|
||
<div class="line"><a id="l02523" name="l02523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89ea9e9c914052e2aecab16d57f2569d"> 2523</a></span><span class="preprocessor">#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk </span></div>
|
||
<div class="line"><a id="l02524" name="l02524"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e5c2f04599975dff25a01253f0ed0db"> 2524</a></span><span class="preprocessor">#define CAN_FS1R_FSC13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l02525" name="l02525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga325adfc64e83297e5feb842002f09142"> 2525</a></span><span class="preprocessor">#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) </span></div>
|
||
<div class="line"><a id="l02526" name="l02526"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2df1f2a554fc014529da34620739bc4"> 2526</a></span><span class="preprocessor">#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk </span></div>
|
||
<div class="line"><a id="l02527" name="l02527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga711edd554bca297c3257d40b351c20c3"> 2527</a></span><span class="preprocessor">#define CAN_FS1R_FSC14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l02528" name="l02528"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34624026fcafcbee1b6c88d7e7756aae"> 2528</a></span><span class="preprocessor">#define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos) </span></div>
|
||
<div class="line"><a id="l02529" name="l02529"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga361a4228de4644d1d6a810f4d074eb5f"> 2529</a></span><span class="preprocessor">#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk </span></div>
|
||
<div class="line"><a id="l02530" name="l02530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3333c522cd42beec23bccc79a2ae1ba"> 2530</a></span><span class="preprocessor">#define CAN_FS1R_FSC15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l02531" name="l02531"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49834a4dc96f2cb8f792bd39d032abb4"> 2531</a></span><span class="preprocessor">#define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos) </span></div>
|
||
<div class="line"><a id="l02532" name="l02532"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5ff2e59c16311405dc891f956c7ec96"> 2532</a></span><span class="preprocessor">#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk </span></div>
|
||
<div class="line"><a id="l02533" name="l02533"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94d84c5617fa0b58145211fc852fa55a"> 2533</a></span><span class="preprocessor">#define CAN_FS1R_FSC16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02534" name="l02534"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1eb533d142b86083e8b163adc30999a7"> 2534</a></span><span class="preprocessor">#define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos) </span></div>
|
||
<div class="line"><a id="l02535" name="l02535"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0996ddbc1dcd487c052a0ae81ab852e"> 2535</a></span><span class="preprocessor">#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk </span></div>
|
||
<div class="line"><a id="l02536" name="l02536"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08ac31ff1870b11302f9e3b27d69789c"> 2536</a></span><span class="preprocessor">#define CAN_FS1R_FSC17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l02537" name="l02537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d4c2ff7be6ee9b3e31108c9877aef03"> 2537</a></span><span class="preprocessor">#define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos) </span></div>
|
||
<div class="line"><a id="l02538" name="l02538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65482dccb8701bf35d1397aadc1e7dde"> 2538</a></span><span class="preprocessor">#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk </span></div>
|
||
<div class="line"><a id="l02539" name="l02539"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e256893bf2da548fa31dacc67b8833b"> 2539</a></span><span class="preprocessor">#define CAN_FS1R_FSC18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l02540" name="l02540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8d890a441fc7b0a75e36caf1cbd7f2d"> 2540</a></span><span class="preprocessor">#define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos) </span></div>
|
||
<div class="line"><a id="l02541" name="l02541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2657192999f8d7f7fdd5c5ef14d884f"> 2541</a></span><span class="preprocessor">#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk </span></div>
|
||
<div class="line"><a id="l02542" name="l02542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga691b7c4f52419323104f755201811d0b"> 2542</a></span><span class="preprocessor">#define CAN_FS1R_FSC19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l02543" name="l02543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga562629687ae7a0c506aa310709b5451e"> 2543</a></span><span class="preprocessor">#define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos) </span></div>
|
||
<div class="line"><a id="l02544" name="l02544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd584a3a9b6d6ae964c0484decb86a93"> 2544</a></span><span class="preprocessor">#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk </span></div>
|
||
<div class="line"><a id="l02545" name="l02545"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0c2995214cad61a44cfbe386fafe5ff"> 2545</a></span><span class="preprocessor">#define CAN_FS1R_FSC20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l02546" name="l02546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0fce6ba0c9c134b3f634c8495b1e9a2"> 2546</a></span><span class="preprocessor">#define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos) </span></div>
|
||
<div class="line"><a id="l02547" name="l02547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5a5e1f0f1a66d607984d02b96b7fa2a"> 2547</a></span><span class="preprocessor">#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk </span></div>
|
||
<div class="line"><a id="l02548" name="l02548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ea9c1362c0aa5d3d03f5df6b92ba9d4"> 2548</a></span><span class="preprocessor">#define CAN_FS1R_FSC21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l02549" name="l02549"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga733db908c55117942e05d21f1ed80d7e"> 2549</a></span><span class="preprocessor">#define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos) </span></div>
|
||
<div class="line"><a id="l02550" name="l02550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa1d6dbc3fc5025a9e7416cc4b40cb7d"> 2550</a></span><span class="preprocessor">#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk </span></div>
|
||
<div class="line"><a id="l02551" name="l02551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2f345b172c571948a3357dd94b72adf"> 2551</a></span><span class="preprocessor">#define CAN_FS1R_FSC22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l02552" name="l02552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabe5f4c3cd58ca9f4749942e3e6e04ee"> 2552</a></span><span class="preprocessor">#define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos) </span></div>
|
||
<div class="line"><a id="l02553" name="l02553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga586c662a1dd2458cd1644e597c8da86d"> 2553</a></span><span class="preprocessor">#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk </span></div>
|
||
<div class="line"><a id="l02554" name="l02554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga152bf04e1b1d963bfed4425d41dd27c8"> 2554</a></span><span class="preprocessor">#define CAN_FS1R_FSC23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l02555" name="l02555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f8a8529c7e6e9b2d9bcd4512888365a"> 2555</a></span><span class="preprocessor">#define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos) </span></div>
|
||
<div class="line"><a id="l02556" name="l02556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga941b39874446041b446c3102646a49b8"> 2556</a></span><span class="preprocessor">#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk </span></div>
|
||
<div class="line"><a id="l02557" name="l02557"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51ea9d18bbbe2db9eed4a8e58e59e957"> 2557</a></span><span class="preprocessor">#define CAN_FS1R_FSC24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02558" name="l02558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68e6bfdc20abbec37b36857af02f466d"> 2558</a></span><span class="preprocessor">#define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos) </span></div>
|
||
<div class="line"><a id="l02559" name="l02559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga702728de40ecf0afc5bc8f05ee243ece"> 2559</a></span><span class="preprocessor">#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk </span></div>
|
||
<div class="line"><a id="l02560" name="l02560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f0bdcc4ed01c8beabedfc4b16a146f6"> 2560</a></span><span class="preprocessor">#define CAN_FS1R_FSC25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l02561" name="l02561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2211e33f4ca75397983086826a688656"> 2561</a></span><span class="preprocessor">#define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos) </span></div>
|
||
<div class="line"><a id="l02562" name="l02562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bd08e49dcb537e967ef7e8a7b30e9d0"> 2562</a></span><span class="preprocessor">#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk </span></div>
|
||
<div class="line"><a id="l02563" name="l02563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab61794b3ead79416791289685a95db4d"> 2563</a></span><span class="preprocessor">#define CAN_FS1R_FSC26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l02564" name="l02564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d55d2d1459b5de35264036663bc430b"> 2564</a></span><span class="preprocessor">#define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos) </span></div>
|
||
<div class="line"><a id="l02565" name="l02565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac642623c62041b1be7ce3af929c4f924"> 2565</a></span><span class="preprocessor">#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk </span></div>
|
||
<div class="line"><a id="l02566" name="l02566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d7b516bf7cf68e60c3feb66b1c3588e"> 2566</a></span><span class="preprocessor">#define CAN_FS1R_FSC27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l02567" name="l02567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c2c04e71ea402536a26c54e6f23116d"> 2567</a></span><span class="preprocessor">#define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos) </span></div>
|
||
<div class="line"><a id="l02568" name="l02568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e86579ebc64eda3a65fd8d40e15af57"> 2568</a></span><span class="preprocessor">#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk </span></div>
|
||
<div class="line"><a id="l02570" name="l02570"></a><span class="lineno"> 2570</span><span class="comment">/****************** Bit definition for CAN_FFA1R register *******************/</span></div>
|
||
<div class="line"><a id="l02571" name="l02571"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8a13781d7e62a0c62344a9e3d32c31b"> 2571</a></span><span class="preprocessor">#define CAN_FFA1R_FFA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02572" name="l02572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d6813f166c5bc78b7ceabcaf544202e"> 2572</a></span><span class="preprocessor">#define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos) </span></div>
|
||
<div class="line"><a id="l02573" name="l02573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16fa4bf13579d29b57f7602489d043fe"> 2573</a></span><span class="preprocessor">#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk </span></div>
|
||
<div class="line"><a id="l02574" name="l02574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e673e4b99624b2b674c1a0cb814af7d"> 2574</a></span><span class="preprocessor">#define CAN_FFA1R_FFA0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02575" name="l02575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63a732f91a0c26a9e29151486e2af798"> 2575</a></span><span class="preprocessor">#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) </span></div>
|
||
<div class="line"><a id="l02576" name="l02576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b1a0f95bac4fed1a801da0cdbf2a833"> 2576</a></span><span class="preprocessor">#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk </span></div>
|
||
<div class="line"><a id="l02577" name="l02577"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafce5ceec640174f6e6c06aafc980bb82"> 2577</a></span><span class="preprocessor">#define CAN_FFA1R_FFA1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l02578" name="l02578"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga692f0c606853b771a99e052cd0fe0995"> 2578</a></span><span class="preprocessor">#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) </span></div>
|
||
<div class="line"><a id="l02579" name="l02579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba35e135e17431de861e57b550421386"> 2579</a></span><span class="preprocessor">#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk </span></div>
|
||
<div class="line"><a id="l02580" name="l02580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7a54c1f4d9f576917d36df988c7cce0"> 2580</a></span><span class="preprocessor">#define CAN_FFA1R_FFA2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l02581" name="l02581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga197d8ba6187ed4b6842505ae99104992"> 2581</a></span><span class="preprocessor">#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) </span></div>
|
||
<div class="line"><a id="l02582" name="l02582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b64393197f5cd0bd6e4853828a98065"> 2582</a></span><span class="preprocessor">#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk </span></div>
|
||
<div class="line"><a id="l02583" name="l02583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57037066dc96ae3ac826b462ab6916ac"> 2583</a></span><span class="preprocessor">#define CAN_FFA1R_FFA3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l02584" name="l02584"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6c1a5ee723cd899b098e277386d86a4"> 2584</a></span><span class="preprocessor">#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) </span></div>
|
||
<div class="line"><a id="l02585" name="l02585"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga111ce1e4500e2c0f543128dddbe941e9"> 2585</a></span><span class="preprocessor">#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk </span></div>
|
||
<div class="line"><a id="l02586" name="l02586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69b604f0eea6a02bb71611b830ff32c2"> 2586</a></span><span class="preprocessor">#define CAN_FFA1R_FFA4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l02587" name="l02587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d03c010394020f6172d2fceba9e02ea"> 2587</a></span><span class="preprocessor">#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) </span></div>
|
||
<div class="line"><a id="l02588" name="l02588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a824c777e7fea25f580bc313ed2ece6"> 2588</a></span><span class="preprocessor">#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk </span></div>
|
||
<div class="line"><a id="l02589" name="l02589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacacfe37b33ceac03e2abad22e7bbce28"> 2589</a></span><span class="preprocessor">#define CAN_FFA1R_FFA5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l02590" name="l02590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51918688a8985d110c995bf441a4f763"> 2590</a></span><span class="preprocessor">#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) </span></div>
|
||
<div class="line"><a id="l02591" name="l02591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd571c9c746225e9b856ce3a46c3bb2f"> 2591</a></span><span class="preprocessor">#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk </span></div>
|
||
<div class="line"><a id="l02592" name="l02592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga165fe8139c6eb2b3971def9579d1d497"> 2592</a></span><span class="preprocessor">#define CAN_FFA1R_FFA6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l02593" name="l02593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01b319af3e2f1b59d544501192e24b68"> 2593</a></span><span class="preprocessor">#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) </span></div>
|
||
<div class="line"><a id="l02594" name="l02594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2afec157fe9684f1fa4b4401500f035"> 2594</a></span><span class="preprocessor">#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk </span></div>
|
||
<div class="line"><a id="l02595" name="l02595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1f1bf154b1ffb5f5e1f7bb5d8b0a300"> 2595</a></span><span class="preprocessor">#define CAN_FFA1R_FFA7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l02596" name="l02596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62ff14edc65346f9e08e9f259a7fd45a"> 2596</a></span><span class="preprocessor">#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) </span></div>
|
||
<div class="line"><a id="l02597" name="l02597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d70e150cfd4866ea6b0a264ad45f51b"> 2597</a></span><span class="preprocessor">#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk </span></div>
|
||
<div class="line"><a id="l02598" name="l02598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9092a75173fa128b0d1fb7616df2cd07"> 2598</a></span><span class="preprocessor">#define CAN_FFA1R_FFA8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02599" name="l02599"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga141132dbc9c5d5a0a125c8aae363445b"> 2599</a></span><span class="preprocessor">#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) </span></div>
|
||
<div class="line"><a id="l02600" name="l02600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa802583aa70aadeb46366ff98eccaf1"> 2600</a></span><span class="preprocessor">#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk </span></div>
|
||
<div class="line"><a id="l02601" name="l02601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa26f182a322fb252ccb2c4e573677ad7"> 2601</a></span><span class="preprocessor">#define CAN_FFA1R_FFA9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l02602" name="l02602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3270aaea7647ea2c5ccbaf747ceffb5b"> 2602</a></span><span class="preprocessor">#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) </span></div>
|
||
<div class="line"><a id="l02603" name="l02603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ee7da4c7e42fa7576d965c4bf94c089"> 2603</a></span><span class="preprocessor">#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk </span></div>
|
||
<div class="line"><a id="l02604" name="l02604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf1221d604b06bcee9432d1438ddd2f1"> 2604</a></span><span class="preprocessor">#define CAN_FFA1R_FFA10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l02605" name="l02605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ac746965c32524f17be780be809bf29"> 2605</a></span><span class="preprocessor">#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) </span></div>
|
||
<div class="line"><a id="l02606" name="l02606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ac0384eab9b0cfdb491a960279fc438"> 2606</a></span><span class="preprocessor">#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk </span></div>
|
||
<div class="line"><a id="l02607" name="l02607"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4435daea27c23de8ac235d2dc6ce988d"> 2607</a></span><span class="preprocessor">#define CAN_FFA1R_FFA11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l02608" name="l02608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5fec989f32c99595a73b0910dc92787"> 2608</a></span><span class="preprocessor">#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) </span></div>
|
||
<div class="line"><a id="l02609" name="l02609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacd7e79ab503ec5143b5848edac71817"> 2609</a></span><span class="preprocessor">#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk </span></div>
|
||
<div class="line"><a id="l02610" name="l02610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga088625981d2bbc9e281ad21fb592022d"> 2610</a></span><span class="preprocessor">#define CAN_FFA1R_FFA12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l02611" name="l02611"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e3859f0d8f9b1a52beaa72de195222b"> 2611</a></span><span class="preprocessor">#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) </span></div>
|
||
<div class="line"><a id="l02612" name="l02612"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7873f1526050f5e666c22fb6a7e68b65"> 2612</a></span><span class="preprocessor">#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk </span></div>
|
||
<div class="line"><a id="l02613" name="l02613"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89646cfa2e98d87000f27e4bd22e0d48"> 2613</a></span><span class="preprocessor">#define CAN_FFA1R_FFA13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l02614" name="l02614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ff3bf3a563646cf44a6dacfa1652cb0"> 2614</a></span><span class="preprocessor">#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) </span></div>
|
||
<div class="line"><a id="l02615" name="l02615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac74339b69a2e6f67df9b6e136089c0ee"> 2615</a></span><span class="preprocessor">#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk </span></div>
|
||
<div class="line"><a id="l02616" name="l02616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf8560a004719b166cfaf281a67f79e1"> 2616</a></span><span class="preprocessor">#define CAN_FFA1R_FFA14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l02617" name="l02617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10da524219356b7c7aa0fff90ef718f1"> 2617</a></span><span class="preprocessor">#define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos) </span></div>
|
||
<div class="line"><a id="l02618" name="l02618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6bdc473bfe275c940734d2c1775d982d"> 2618</a></span><span class="preprocessor">#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk </span></div>
|
||
<div class="line"><a id="l02619" name="l02619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae41306fbd5429b13073a556e9c851470"> 2619</a></span><span class="preprocessor">#define CAN_FFA1R_FFA15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l02620" name="l02620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef1dfb17246f207f68f459a0f7f440df"> 2620</a></span><span class="preprocessor">#define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos) </span></div>
|
||
<div class="line"><a id="l02621" name="l02621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c72b1a17bc4a9c7ec3251af645e290d"> 2621</a></span><span class="preprocessor">#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk </span></div>
|
||
<div class="line"><a id="l02622" name="l02622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga799996bdb9bc84e5bcd03e7d75f3ec4e"> 2622</a></span><span class="preprocessor">#define CAN_FFA1R_FFA16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02623" name="l02623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f03a68e7428cc6c56b0f755246ecff4"> 2623</a></span><span class="preprocessor">#define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos) </span></div>
|
||
<div class="line"><a id="l02624" name="l02624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadac411834c4a2118354f7b160c292dd6"> 2624</a></span><span class="preprocessor">#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk </span></div>
|
||
<div class="line"><a id="l02625" name="l02625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa772ef7c7e8e47f6c54d342f83a6f4ab"> 2625</a></span><span class="preprocessor">#define CAN_FFA1R_FFA17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l02626" name="l02626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9eccf63346520ce0fc6d72774b62957d"> 2626</a></span><span class="preprocessor">#define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos) </span></div>
|
||
<div class="line"><a id="l02627" name="l02627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf73b3c3d378246929f1092416546aa45"> 2627</a></span><span class="preprocessor">#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk </span></div>
|
||
<div class="line"><a id="l02628" name="l02628"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89199c68d5354b179d13f125beb8866b"> 2628</a></span><span class="preprocessor">#define CAN_FFA1R_FFA18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l02629" name="l02629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad328f6b0426811376fb96edd92ee17dd"> 2629</a></span><span class="preprocessor">#define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos) </span></div>
|
||
<div class="line"><a id="l02630" name="l02630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc2bf72b9f9c57ddcaf09449a208a4ef"> 2630</a></span><span class="preprocessor">#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk </span></div>
|
||
<div class="line"><a id="l02631" name="l02631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d1c21deb9827442f5607348e34abc98"> 2631</a></span><span class="preprocessor">#define CAN_FFA1R_FFA19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l02632" name="l02632"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffc95b44aaf8c77fb00666241311d78b"> 2632</a></span><span class="preprocessor">#define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos) </span></div>
|
||
<div class="line"><a id="l02633" name="l02633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a2371494a1ab03e90ff471b4e88d4eb"> 2633</a></span><span class="preprocessor">#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk </span></div>
|
||
<div class="line"><a id="l02634" name="l02634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga077f389aa603e8dc048bc6af4cbec654"> 2634</a></span><span class="preprocessor">#define CAN_FFA1R_FFA20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l02635" name="l02635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87cf0758a707ef8bae3f14ca07009487"> 2635</a></span><span class="preprocessor">#define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos) </span></div>
|
||
<div class="line"><a id="l02636" name="l02636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7359bb245f5bc6f9298bdae577c7f2d1"> 2636</a></span><span class="preprocessor">#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk </span></div>
|
||
<div class="line"><a id="l02637" name="l02637"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b4ab4a10e2a0cb2bb32bee0c1d1fe8d"> 2637</a></span><span class="preprocessor">#define CAN_FFA1R_FFA21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l02638" name="l02638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49398f11989a0fac67eea74c169add65"> 2638</a></span><span class="preprocessor">#define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos) </span></div>
|
||
<div class="line"><a id="l02639" name="l02639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4390bdfd6fb22feb6b64de18b45304d8"> 2639</a></span><span class="preprocessor">#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk </span></div>
|
||
<div class="line"><a id="l02640" name="l02640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08da105ae70ea87f80128a8451fb14d8"> 2640</a></span><span class="preprocessor">#define CAN_FFA1R_FFA22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l02641" name="l02641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab501571f610235c7a89d5ed6148ee4bb"> 2641</a></span><span class="preprocessor">#define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos) </span></div>
|
||
<div class="line"><a id="l02642" name="l02642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga029cfaf7e13f5214dd3e056b0984b1d8"> 2642</a></span><span class="preprocessor">#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk </span></div>
|
||
<div class="line"><a id="l02643" name="l02643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabcc71274e0234226241674e65a697913"> 2643</a></span><span class="preprocessor">#define CAN_FFA1R_FFA23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l02644" name="l02644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1258ce7b88510c0942cca2ec7443c749"> 2644</a></span><span class="preprocessor">#define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos) </span></div>
|
||
<div class="line"><a id="l02645" name="l02645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad969df81e8f4d8902ddf9ac76c7ff9d2"> 2645</a></span><span class="preprocessor">#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk </span></div>
|
||
<div class="line"><a id="l02646" name="l02646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabae42ffc06637b9ac6424b2019cef2a"> 2646</a></span><span class="preprocessor">#define CAN_FFA1R_FFA24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02647" name="l02647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fe02633e558b53290fc5645ac903318"> 2647</a></span><span class="preprocessor">#define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos) </span></div>
|
||
<div class="line"><a id="l02648" name="l02648"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d1adf29e37676017c67204623a45985"> 2648</a></span><span class="preprocessor">#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk </span></div>
|
||
<div class="line"><a id="l02649" name="l02649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcf4053a355ef612cbf6a56415cf8583"> 2649</a></span><span class="preprocessor">#define CAN_FFA1R_FFA25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l02650" name="l02650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf586e3c813baaa9026b78e158c90df0c"> 2650</a></span><span class="preprocessor">#define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos) </span></div>
|
||
<div class="line"><a id="l02651" name="l02651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40553faf034d88e215c71d40c08f774e"> 2651</a></span><span class="preprocessor">#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk </span></div>
|
||
<div class="line"><a id="l02652" name="l02652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24094060ed59ce5c405fbb2f4212694a"> 2652</a></span><span class="preprocessor">#define CAN_FFA1R_FFA26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l02653" name="l02653"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac224810fe7b45a273faa3d655bc64d44"> 2653</a></span><span class="preprocessor">#define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos) </span></div>
|
||
<div class="line"><a id="l02654" name="l02654"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d347ff7528138f59d223adf7c838440"> 2654</a></span><span class="preprocessor">#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk </span></div>
|
||
<div class="line"><a id="l02655" name="l02655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cf95c6d995ed5e1dded3e5d55020cbf"> 2655</a></span><span class="preprocessor">#define CAN_FFA1R_FFA27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l02656" name="l02656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae312771a3ea200b9df91e30ddc1392d2"> 2656</a></span><span class="preprocessor">#define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos) </span></div>
|
||
<div class="line"><a id="l02657" name="l02657"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ace5c7e4d87bebdc36d66de6cef7442"> 2657</a></span><span class="preprocessor">#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk </span></div>
|
||
<div class="line"><a id="l02659" name="l02659"></a><span class="lineno"> 2659</span><span class="comment">/******************* Bit definition for CAN_FA1R register *******************/</span></div>
|
||
<div class="line"><a id="l02660" name="l02660"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21e8eff485fa16ae0d289eacce72bd56"> 2660</a></span><span class="preprocessor">#define CAN_FA1R_FACT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02661" name="l02661"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f05941c6d7ad0294283a20dc4307a56"> 2661</a></span><span class="preprocessor">#define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos) </span></div>
|
||
<div class="line"><a id="l02662" name="l02662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa571445875b08a9514e1d1b410a93ebd"> 2662</a></span><span class="preprocessor">#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk </span></div>
|
||
<div class="line"><a id="l02663" name="l02663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4be3d2c02fe8f070f95f234191482b86"> 2663</a></span><span class="preprocessor">#define CAN_FA1R_FACT0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02664" name="l02664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc33c5308d541004ba2961a7d0527278"> 2664</a></span><span class="preprocessor">#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) </span></div>
|
||
<div class="line"><a id="l02665" name="l02665"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3ec1e2f9b9ccf2b4869cdf7c7328e60"> 2665</a></span><span class="preprocessor">#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk </span></div>
|
||
<div class="line"><a id="l02666" name="l02666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd6506d842c27928a8647942fbdb0602"> 2666</a></span><span class="preprocessor">#define CAN_FA1R_FACT1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l02667" name="l02667"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10ee3a44fa9dc10a77c9a0668a19ddab"> 2667</a></span><span class="preprocessor">#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) </span></div>
|
||
<div class="line"><a id="l02668" name="l02668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2457026460aecb52dba7ea17237b4dbe"> 2668</a></span><span class="preprocessor">#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk </span></div>
|
||
<div class="line"><a id="l02669" name="l02669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac70ad8a114259387ba6eb4bf21a2c13"> 2669</a></span><span class="preprocessor">#define CAN_FA1R_FACT2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l02670" name="l02670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafc57ac18afd7bd0eb14e84dbc265a83"> 2670</a></span><span class="preprocessor">#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) </span></div>
|
||
<div class="line"><a id="l02671" name="l02671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66354c26d0252cc86729365b315a69ee"> 2671</a></span><span class="preprocessor">#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk </span></div>
|
||
<div class="line"><a id="l02672" name="l02672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa93067be654983f42daf67ab9da3fbc3"> 2672</a></span><span class="preprocessor">#define CAN_FA1R_FACT3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l02673" name="l02673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b9b6a83d65b39753f8208f45d0d72ce"> 2673</a></span><span class="preprocessor">#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) </span></div>
|
||
<div class="line"><a id="l02674" name="l02674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga087dc5f2bdfe084eb98d2a0d06a29f1d"> 2674</a></span><span class="preprocessor">#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk </span></div>
|
||
<div class="line"><a id="l02675" name="l02675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd3f42141b00002a6db3db68ecd9909d"> 2675</a></span><span class="preprocessor">#define CAN_FA1R_FACT4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l02676" name="l02676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga562dc354461029230ead72878c01ba30"> 2676</a></span><span class="preprocessor">#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) </span></div>
|
||
<div class="line"><a id="l02677" name="l02677"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c46367b7e5ea831e34ba4cf824a63da"> 2677</a></span><span class="preprocessor">#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk </span></div>
|
||
<div class="line"><a id="l02678" name="l02678"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf840e6f2d239bf5fc59c6f3454c2d122"> 2678</a></span><span class="preprocessor">#define CAN_FA1R_FACT5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l02679" name="l02679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe67ef97c9d6b04fcad49eccad2ce8a1"> 2679</a></span><span class="preprocessor">#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) </span></div>
|
||
<div class="line"><a id="l02680" name="l02680"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga548238c7babf34116fdb44b4575e2664"> 2680</a></span><span class="preprocessor">#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk </span></div>
|
||
<div class="line"><a id="l02681" name="l02681"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga390f38386d4c2a6940d7dfe88bc4ab70"> 2681</a></span><span class="preprocessor">#define CAN_FA1R_FACT6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l02682" name="l02682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab13ad536db58592d5b4f2beb9c4f0469"> 2682</a></span><span class="preprocessor">#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) </span></div>
|
||
<div class="line"><a id="l02683" name="l02683"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae403370a70f9ea2b6f9b449cafa6a91c"> 2683</a></span><span class="preprocessor">#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk </span></div>
|
||
<div class="line"><a id="l02684" name="l02684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade2b7e97d515badec6d07154c8fdec2e"> 2684</a></span><span class="preprocessor">#define CAN_FA1R_FACT7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l02685" name="l02685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32a9fa687af9f4bc3800be29ee32a3e6"> 2685</a></span><span class="preprocessor">#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) </span></div>
|
||
<div class="line"><a id="l02686" name="l02686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33e9f4334cf3bf9e7e30d5edf278a02b"> 2686</a></span><span class="preprocessor">#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk </span></div>
|
||
<div class="line"><a id="l02687" name="l02687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac34978a6e1dbc7ff9a62d577d0473308"> 2687</a></span><span class="preprocessor">#define CAN_FA1R_FACT8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02688" name="l02688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9addaf5198f1b165bb8a1c5abe8c9a1f"> 2688</a></span><span class="preprocessor">#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) </span></div>
|
||
<div class="line"><a id="l02689" name="l02689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ccbdd2932828bfa1d68777cb595f12e"> 2689</a></span><span class="preprocessor">#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk </span></div>
|
||
<div class="line"><a id="l02690" name="l02690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6bd9a79b3e73c5343df683cb08e213e1"> 2690</a></span><span class="preprocessor">#define CAN_FA1R_FACT9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l02691" name="l02691"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9cb920b1dd24719e2fe959bc9fa27b2c"> 2691</a></span><span class="preprocessor">#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) </span></div>
|
||
<div class="line"><a id="l02692" name="l02692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8e4011791e551feeae33c47ef2b6a6a"> 2692</a></span><span class="preprocessor">#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk </span></div>
|
||
<div class="line"><a id="l02693" name="l02693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga095e0af1331f6dbf70921399cb9d5930"> 2693</a></span><span class="preprocessor">#define CAN_FA1R_FACT10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l02694" name="l02694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafff61cabd030366925d3f3608cd81ec4"> 2694</a></span><span class="preprocessor">#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) </span></div>
|
||
<div class="line"><a id="l02695" name="l02695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19696d8b702b33eafe7f18aa0c6c1955"> 2695</a></span><span class="preprocessor">#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk </span></div>
|
||
<div class="line"><a id="l02696" name="l02696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd79b5d1d4a66c46c60190ff3e356419"> 2696</a></span><span class="preprocessor">#define CAN_FA1R_FACT11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l02697" name="l02697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad043d708a8b891182f6f36217bba8a70"> 2697</a></span><span class="preprocessor">#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) </span></div>
|
||
<div class="line"><a id="l02698" name="l02698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89e5e3ccd4250ad2360b91ef51248a66"> 2698</a></span><span class="preprocessor">#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk </span></div>
|
||
<div class="line"><a id="l02699" name="l02699"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ec82f6225d96fddd6fdb40033aa54d8"> 2699</a></span><span class="preprocessor">#define CAN_FA1R_FACT12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l02700" name="l02700"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7de851ce57bd07d4913bd409dee3f51"> 2700</a></span><span class="preprocessor">#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) </span></div>
|
||
<div class="line"><a id="l02701" name="l02701"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae78ec392640f05b20a7c6877983588ae"> 2701</a></span><span class="preprocessor">#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk </span></div>
|
||
<div class="line"><a id="l02702" name="l02702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6056bd9c2a6de9289b06bbcd0eab4599"> 2702</a></span><span class="preprocessor">#define CAN_FA1R_FACT13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l02703" name="l02703"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fc2cc6acea1e2a86083f9f0d5ce05c0"> 2703</a></span><span class="preprocessor">#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) </span></div>
|
||
<div class="line"><a id="l02704" name="l02704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa722eeef87f8a3f58ebfcb531645cc05"> 2704</a></span><span class="preprocessor">#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk </span></div>
|
||
<div class="line"><a id="l02705" name="l02705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8afb5078389340fd934c7f18978f45ce"> 2705</a></span><span class="preprocessor">#define CAN_FA1R_FACT14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l02706" name="l02706"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5aad7b1d23bd498ecd99b4adcb239560"> 2706</a></span><span class="preprocessor">#define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos) </span></div>
|
||
<div class="line"><a id="l02707" name="l02707"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2de45b22180cee8e9b3fef000869af3"> 2707</a></span><span class="preprocessor">#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk </span></div>
|
||
<div class="line"><a id="l02708" name="l02708"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83dd3c9202d4e42a35c2b5ccb4eee21b"> 2708</a></span><span class="preprocessor">#define CAN_FA1R_FACT15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l02709" name="l02709"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d0e0b9363ac2965048f42ce3abc9518"> 2709</a></span><span class="preprocessor">#define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos) </span></div>
|
||
<div class="line"><a id="l02710" name="l02710"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9e8c965500f24cb92a72038e9db3a03"> 2710</a></span><span class="preprocessor">#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk </span></div>
|
||
<div class="line"><a id="l02711" name="l02711"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0dd1b09262007ca3c8753891838f2291"> 2711</a></span><span class="preprocessor">#define CAN_FA1R_FACT16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02712" name="l02712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b832148df149f3f89b168bf1da68449"> 2712</a></span><span class="preprocessor">#define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos) </span></div>
|
||
<div class="line"><a id="l02713" name="l02713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4054fdf1fced195e59509a2282fd023"> 2713</a></span><span class="preprocessor">#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk </span></div>
|
||
<div class="line"><a id="l02714" name="l02714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga061545e7d6c13e4699c81dc71e7ac59d"> 2714</a></span><span class="preprocessor">#define CAN_FA1R_FACT17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l02715" name="l02715"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec1081e22c20c398d0a24cf2dba852ba"> 2715</a></span><span class="preprocessor">#define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos) </span></div>
|
||
<div class="line"><a id="l02716" name="l02716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a0970d03bb791397495af0762f54d65"> 2716</a></span><span class="preprocessor">#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk </span></div>
|
||
<div class="line"><a id="l02717" name="l02717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccded4c9f678c1e12ecd3f296eaa6f6b"> 2717</a></span><span class="preprocessor">#define CAN_FA1R_FACT18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l02718" name="l02718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0844889fa76d91d278d5694d916a04ca"> 2718</a></span><span class="preprocessor">#define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos) </span></div>
|
||
<div class="line"><a id="l02719" name="l02719"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98ba61a8ef9d4e5cea606148281e432d"> 2719</a></span><span class="preprocessor">#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk </span></div>
|
||
<div class="line"><a id="l02720" name="l02720"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga707b4f7a3fd6e7ed30c17c5cd1933ef3"> 2720</a></span><span class="preprocessor">#define CAN_FA1R_FACT19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l02721" name="l02721"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74353cfdb58079f47563079de3fd778b"> 2721</a></span><span class="preprocessor">#define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos) </span></div>
|
||
<div class="line"><a id="l02722" name="l02722"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87064c634cec6fc2ee70fecbb04b92c2"> 2722</a></span><span class="preprocessor">#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk </span></div>
|
||
<div class="line"><a id="l02723" name="l02723"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a3d2f351f0a92a5604b01e36a921de2"> 2723</a></span><span class="preprocessor">#define CAN_FA1R_FACT20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l02724" name="l02724"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga093d17300bad7b8fa43bd6d264b07217"> 2724</a></span><span class="preprocessor">#define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos) </span></div>
|
||
<div class="line"><a id="l02725" name="l02725"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0222f2ac5c4d4b9e6382d4dd8286bb2"> 2725</a></span><span class="preprocessor">#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk </span></div>
|
||
<div class="line"><a id="l02726" name="l02726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae280cc92b21856b1da77deef88ae0aea"> 2726</a></span><span class="preprocessor">#define CAN_FA1R_FACT21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l02727" name="l02727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bcf854bcce93e28d97db435631b81d8"> 2727</a></span><span class="preprocessor">#define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos) </span></div>
|
||
<div class="line"><a id="l02728" name="l02728"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22534866322499e9d05513f0d41754fe"> 2728</a></span><span class="preprocessor">#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk </span></div>
|
||
<div class="line"><a id="l02729" name="l02729"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae195ba574d695a543786b5a60e2535d3"> 2729</a></span><span class="preprocessor">#define CAN_FA1R_FACT22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l02730" name="l02730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1090ef53e33de146fb08fdee8e8874f9"> 2730</a></span><span class="preprocessor">#define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos) </span></div>
|
||
<div class="line"><a id="l02731" name="l02731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9febd35acb8257833bf9dbbe18b063b"> 2731</a></span><span class="preprocessor">#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk </span></div>
|
||
<div class="line"><a id="l02732" name="l02732"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36f892196608ea5f8567c9027e5f8f36"> 2732</a></span><span class="preprocessor">#define CAN_FA1R_FACT23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l02733" name="l02733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64eea4ed2c7c6a0c0c1a1b2e4acfd32f"> 2733</a></span><span class="preprocessor">#define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos) </span></div>
|
||
<div class="line"><a id="l02734" name="l02734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12e95e773be98669c171971d3be8cc8b"> 2734</a></span><span class="preprocessor">#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk </span></div>
|
||
<div class="line"><a id="l02735" name="l02735"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga311ef25d716f12e324d3dccbe2f8ec66"> 2735</a></span><span class="preprocessor">#define CAN_FA1R_FACT24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02736" name="l02736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57f3f41e8a31cd07be66cbd05eabfbe4"> 2736</a></span><span class="preprocessor">#define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos) </span></div>
|
||
<div class="line"><a id="l02737" name="l02737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63dd04052a79614027b3efe30ea1724a"> 2737</a></span><span class="preprocessor">#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk </span></div>
|
||
<div class="line"><a id="l02738" name="l02738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5dfb5fd56f8ed22e24ee02ebbf37d58c"> 2738</a></span><span class="preprocessor">#define CAN_FA1R_FACT25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l02739" name="l02739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d5955b25bf2b59795d8864719ff0bf0"> 2739</a></span><span class="preprocessor">#define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos) </span></div>
|
||
<div class="line"><a id="l02740" name="l02740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga994fbfb885e73b4221b64f8bcb19631e"> 2740</a></span><span class="preprocessor">#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk </span></div>
|
||
<div class="line"><a id="l02741" name="l02741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01ddadbe0437498108088593d769776e"> 2741</a></span><span class="preprocessor">#define CAN_FA1R_FACT26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l02742" name="l02742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac30095caad0d9f62fc1aa0ba0ddd70c7"> 2742</a></span><span class="preprocessor">#define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos) </span></div>
|
||
<div class="line"><a id="l02743" name="l02743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf64c2c798a0c3bbe2745bf603e034a89"> 2743</a></span><span class="preprocessor">#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk </span></div>
|
||
<div class="line"><a id="l02744" name="l02744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20dee91cf99643da8f3cbcabefe188dc"> 2744</a></span><span class="preprocessor">#define CAN_FA1R_FACT27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l02745" name="l02745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4c4ecc7e23c652a42b36df4494bc0bf"> 2745</a></span><span class="preprocessor">#define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos) </span></div>
|
||
<div class="line"><a id="l02746" name="l02746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf72e900b51c3c380a81832d0314643c2"> 2746</a></span><span class="preprocessor">#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk </span></div>
|
||
<div class="line"><a id="l02749" name="l02749"></a><span class="lineno"> 2749</span><span class="comment">/******************* Bit definition for CAN_F0R1 register *******************/</span></div>
|
||
<div class="line"><a id="l02750" name="l02750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c98aba7c4d97ff22da1127911917846"> 2750</a></span><span class="preprocessor">#define CAN_F0R1_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02751" name="l02751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf41ce0d3efb93360593d51fc1507ef37"> 2751</a></span><span class="preprocessor">#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l02752" name="l02752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38014ea45b62975627f8e222390f6819"> 2752</a></span><span class="preprocessor">#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk </span></div>
|
||
<div class="line"><a id="l02753" name="l02753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa503478584d6bd0535d29df9839816a0"> 2753</a></span><span class="preprocessor">#define CAN_F0R1_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l02754" name="l02754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf16111eec26fa5058aeac0945c0a481"> 2754</a></span><span class="preprocessor">#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l02755" name="l02755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e01c05df79304035c7aab1c7295bf3f"> 2755</a></span><span class="preprocessor">#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk </span></div>
|
||
<div class="line"><a id="l02756" name="l02756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30edb71ea81cfa7a3e881e2692093d70"> 2756</a></span><span class="preprocessor">#define CAN_F0R1_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l02757" name="l02757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga269a36e254bdc397d46b7b04b25cf58c"> 2757</a></span><span class="preprocessor">#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l02758" name="l02758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga083282146d4db7f757fef86cf302eded"> 2758</a></span><span class="preprocessor">#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk </span></div>
|
||
<div class="line"><a id="l02759" name="l02759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3365da181d4986260f3f1d0adfe2337a"> 2759</a></span><span class="preprocessor">#define CAN_F0R1_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l02760" name="l02760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad40133f8c3bdff4edac51999e63eb616"> 2760</a></span><span class="preprocessor">#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l02761" name="l02761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4a1adc2e4e550a38649a2bfd3662680"> 2761</a></span><span class="preprocessor">#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk </span></div>
|
||
<div class="line"><a id="l02762" name="l02762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5732df35cf88b47553b239d79818d29f"> 2762</a></span><span class="preprocessor">#define CAN_F0R1_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l02763" name="l02763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5be6df46bddda042bca88f23939d6cf"> 2763</a></span><span class="preprocessor">#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l02764" name="l02764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0bfa15bf30fefb21f351228cde87981"> 2764</a></span><span class="preprocessor">#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk </span></div>
|
||
<div class="line"><a id="l02765" name="l02765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ef90325b70b6dbc93a5468d6571ae60"> 2765</a></span><span class="preprocessor">#define CAN_F0R1_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l02766" name="l02766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0d0c4979d148b7aadf88999d127a8e4"> 2766</a></span><span class="preprocessor">#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l02767" name="l02767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5381c154ba89611bf4381657305ecb85"> 2767</a></span><span class="preprocessor">#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk </span></div>
|
||
<div class="line"><a id="l02768" name="l02768"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58c06570c4e947c9f58d0fa0ec81490b"> 2768</a></span><span class="preprocessor">#define CAN_F0R1_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l02769" name="l02769"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga559e44745ca384b08f8e3d370539e2a4"> 2769</a></span><span class="preprocessor">#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l02770" name="l02770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae224160853946732608f00ad008a6b1a"> 2770</a></span><span class="preprocessor">#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk </span></div>
|
||
<div class="line"><a id="l02771" name="l02771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19c4bdfb75f490af25c59c8feabf2be0"> 2771</a></span><span class="preprocessor">#define CAN_F0R1_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l02772" name="l02772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d0b187d74d01d2d7a9e0946287a523f"> 2772</a></span><span class="preprocessor">#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l02773" name="l02773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0c44034b5f42fa8250dbb8e46bc83eb"> 2773</a></span><span class="preprocessor">#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk </span></div>
|
||
<div class="line"><a id="l02774" name="l02774"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6ba4e35ff552a0750f809d3749a5861"> 2774</a></span><span class="preprocessor">#define CAN_F0R1_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02775" name="l02775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae373e9d2f9a170895ffab6051243a0f6"> 2775</a></span><span class="preprocessor">#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l02776" name="l02776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga465e092af3e73882f9eaffad13f36dea"> 2776</a></span><span class="preprocessor">#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk </span></div>
|
||
<div class="line"><a id="l02777" name="l02777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea4ec2d33b8ef0f635bfac9654be0551"> 2777</a></span><span class="preprocessor">#define CAN_F0R1_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l02778" name="l02778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ac0f1442cbee02cb21fca28b5fc61f6"> 2778</a></span><span class="preprocessor">#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l02779" name="l02779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1cb7ff6d513fec365eb5a830c3746f0"> 2779</a></span><span class="preprocessor">#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk </span></div>
|
||
<div class="line"><a id="l02780" name="l02780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5df4d89fa55adb9f8984b482e8b84598"> 2780</a></span><span class="preprocessor">#define CAN_F0R1_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l02781" name="l02781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabcb7c073dbc77461d7519a85f6377a08"> 2781</a></span><span class="preprocessor">#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l02782" name="l02782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b8a688856ca6b53417948f79932534d"> 2782</a></span><span class="preprocessor">#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk </span></div>
|
||
<div class="line"><a id="l02783" name="l02783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51c39129e454b5f9ea84e7ff296d977b"> 2783</a></span><span class="preprocessor">#define CAN_F0R1_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l02784" name="l02784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f982ab6a096e4421079c592b6791d47"> 2784</a></span><span class="preprocessor">#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l02785" name="l02785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72b81011a2d626ac398a387c89055935"> 2785</a></span><span class="preprocessor">#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk </span></div>
|
||
<div class="line"><a id="l02786" name="l02786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83390adff1d103861b00e3a6a7ff4eb2"> 2786</a></span><span class="preprocessor">#define CAN_F0R1_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l02787" name="l02787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac70bfdc26446118697edbcd2d95b7676"> 2787</a></span><span class="preprocessor">#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l02788" name="l02788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac178a6710aeb6c58f725dd7f00af5d5a"> 2788</a></span><span class="preprocessor">#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk </span></div>
|
||
<div class="line"><a id="l02789" name="l02789"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cb3bc6c8af39e8e548d35945c4b4ec0"> 2789</a></span><span class="preprocessor">#define CAN_F0R1_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l02790" name="l02790"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad67a5fe07e6f9e3b3330ad2a46d69d98"> 2790</a></span><span class="preprocessor">#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l02791" name="l02791"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8aee1182bef65da056242c4ed49dd0ef"> 2791</a></span><span class="preprocessor">#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk </span></div>
|
||
<div class="line"><a id="l02792" name="l02792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0802c1f18214f151a01a44be1669efac"> 2792</a></span><span class="preprocessor">#define CAN_F0R1_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l02793" name="l02793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac932d38da89bcc4fe8cde14ebb59a29e"> 2793</a></span><span class="preprocessor">#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l02794" name="l02794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe16c95f454da44949977e4225590658"> 2794</a></span><span class="preprocessor">#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk </span></div>
|
||
<div class="line"><a id="l02795" name="l02795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa270d9f780ab40ae9dc1a3650d4bd8d5"> 2795</a></span><span class="preprocessor">#define CAN_F0R1_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l02796" name="l02796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71b253d3185e16b606150fee2a19760d"> 2796</a></span><span class="preprocessor">#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l02797" name="l02797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb07dca9fddf64a3476f25f227e33e1f"> 2797</a></span><span class="preprocessor">#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk </span></div>
|
||
<div class="line"><a id="l02798" name="l02798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7ff7c8fd59e93239bfc6b509e3698ce"> 2798</a></span><span class="preprocessor">#define CAN_F0R1_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02799" name="l02799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab87631b267fd39cfee4d253a3d7295b2"> 2799</a></span><span class="preprocessor">#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l02800" name="l02800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf019423a4b07e564dfe917b859e68e80"> 2800</a></span><span class="preprocessor">#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk </span></div>
|
||
<div class="line"><a id="l02801" name="l02801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga594b502afc2b215e7b712f53a14bc5bc"> 2801</a></span><span class="preprocessor">#define CAN_F0R1_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l02802" name="l02802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa35416758e3db5bceaff708bdbe5bdc0"> 2802</a></span><span class="preprocessor">#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l02803" name="l02803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ee508d40637a9d558d2ab85753395bd"> 2803</a></span><span class="preprocessor">#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk </span></div>
|
||
<div class="line"><a id="l02804" name="l02804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf097e8cb0757c526b83c45390ffa4b26"> 2804</a></span><span class="preprocessor">#define CAN_F0R1_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l02805" name="l02805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1a49c7f4d13a4e4b4038caaea711391"> 2805</a></span><span class="preprocessor">#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l02806" name="l02806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga827a459cd51a193d571a16e1d38fac22"> 2806</a></span><span class="preprocessor">#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk </span></div>
|
||
<div class="line"><a id="l02807" name="l02807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga467f1f2d0208a355d18cdd375eef9aed"> 2807</a></span><span class="preprocessor">#define CAN_F0R1_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l02808" name="l02808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75a34023fcd221fc010aaa51065d59dc"> 2808</a></span><span class="preprocessor">#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l02809" name="l02809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ecfbfd6f5e129d690f1cb62ee344d78"> 2809</a></span><span class="preprocessor">#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk </span></div>
|
||
<div class="line"><a id="l02810" name="l02810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffdb169bfcc229d44b6f2cbd39327458"> 2810</a></span><span class="preprocessor">#define CAN_F0R1_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l02811" name="l02811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga574954093b93f62bcfa5cd31e366c2e8"> 2811</a></span><span class="preprocessor">#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l02812" name="l02812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a0568e276f245e1f167e673a1f5b92e"> 2812</a></span><span class="preprocessor">#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk </span></div>
|
||
<div class="line"><a id="l02813" name="l02813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9e0fc7eadce21f8851416d9cecbdb22"> 2813</a></span><span class="preprocessor">#define CAN_F0R1_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l02814" name="l02814"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41cb6ebc16634fc1a187d536575f47dc"> 2814</a></span><span class="preprocessor">#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l02815" name="l02815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb71599bae1e35e750524708ac5824f1"> 2815</a></span><span class="preprocessor">#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk </span></div>
|
||
<div class="line"><a id="l02816" name="l02816"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb02ba4a871b3e83ba9ffddc0aa283da"> 2816</a></span><span class="preprocessor">#define CAN_F0R1_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l02817" name="l02817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56eff75e99dbbdd3e4ffe99ae98cd769"> 2817</a></span><span class="preprocessor">#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l02818" name="l02818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7589f9a62f9f5406934266820a265f3a"> 2818</a></span><span class="preprocessor">#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk </span></div>
|
||
<div class="line"><a id="l02819" name="l02819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4fab79aa6648f9590bb08efd5ad74f4"> 2819</a></span><span class="preprocessor">#define CAN_F0R1_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l02820" name="l02820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95d558afd743b97060008ebad600c249"> 2820</a></span><span class="preprocessor">#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l02821" name="l02821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a0db2ff3fcf3ecd929d61e548905685"> 2821</a></span><span class="preprocessor">#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk </span></div>
|
||
<div class="line"><a id="l02822" name="l02822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13b36c39c67b88f41d78466dabf1fc68"> 2822</a></span><span class="preprocessor">#define CAN_F0R1_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02823" name="l02823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05249fde15f0ea5a4447a370ba33f344"> 2823</a></span><span class="preprocessor">#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l02824" name="l02824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2161321c3b0857a9ca07bc45ac9cd1be"> 2824</a></span><span class="preprocessor">#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk </span></div>
|
||
<div class="line"><a id="l02825" name="l02825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32f93a785540423f910b0fbba693c50c"> 2825</a></span><span class="preprocessor">#define CAN_F0R1_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l02826" name="l02826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2e99f0edf1d250d640fda6790e5f8e7"> 2826</a></span><span class="preprocessor">#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l02827" name="l02827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa85c1d5ccfd6241059822a3aadc1053d"> 2827</a></span><span class="preprocessor">#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk </span></div>
|
||
<div class="line"><a id="l02828" name="l02828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd7f7ef5b97b2df3a159a4f5d0c62485"> 2828</a></span><span class="preprocessor">#define CAN_F0R1_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l02829" name="l02829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d00a7d84706b341bf587c7f329ddf88"> 2829</a></span><span class="preprocessor">#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l02830" name="l02830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d82ba565f065b4dec733d002c02498b"> 2830</a></span><span class="preprocessor">#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk </span></div>
|
||
<div class="line"><a id="l02831" name="l02831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga080266e7390127c1e4efa9bf8a1d3894"> 2831</a></span><span class="preprocessor">#define CAN_F0R1_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l02832" name="l02832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf334329b9d4faf3443e12317303b45d6"> 2832</a></span><span class="preprocessor">#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l02833" name="l02833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga199d63d7155cb5212982d4902e31e70c"> 2833</a></span><span class="preprocessor">#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk </span></div>
|
||
<div class="line"><a id="l02834" name="l02834"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga828088c9ccc3e6f4a3b16fe6cf527a58"> 2834</a></span><span class="preprocessor">#define CAN_F0R1_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l02835" name="l02835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb63f1377b7f9dfd87c3ef59a5977ee3"> 2835</a></span><span class="preprocessor">#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l02836" name="l02836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac82d92ad6fb51b340e8a52da903e1009"> 2836</a></span><span class="preprocessor">#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk </span></div>
|
||
<div class="line"><a id="l02837" name="l02837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b9440886e48f1f2f9c8737120f2458c"> 2837</a></span><span class="preprocessor">#define CAN_F0R1_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l02838" name="l02838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe7e2b3d7caf0ff01c856374d60f8345"> 2838</a></span><span class="preprocessor">#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l02839" name="l02839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa0a651933135336bc14baa3e0a56ab1"> 2839</a></span><span class="preprocessor">#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk </span></div>
|
||
<div class="line"><a id="l02840" name="l02840"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fcf33bc1f1bcea9c87040747e2aa6ad"> 2840</a></span><span class="preprocessor">#define CAN_F0R1_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l02841" name="l02841"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9766eac13c78b86a31cd64e0d6bea0d"> 2841</a></span><span class="preprocessor">#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l02842" name="l02842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad2a1d8bb83dfcd9f13d25e8ed098b54"> 2842</a></span><span class="preprocessor">#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk </span></div>
|
||
<div class="line"><a id="l02843" name="l02843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c57e8d1ef05bc7b1c23812904b290f3"> 2843</a></span><span class="preprocessor">#define CAN_F0R1_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l02844" name="l02844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e5e5a0416bc721a85eb46e256c35262"> 2844</a></span><span class="preprocessor">#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l02845" name="l02845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c9745bc78a65538cbe0fb0d09911554"> 2845</a></span><span class="preprocessor">#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk </span></div>
|
||
<div class="line"><a id="l02847" name="l02847"></a><span class="lineno"> 2847</span><span class="comment">/******************* Bit definition for CAN_F1R1 register *******************/</span></div>
|
||
<div class="line"><a id="l02848" name="l02848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27eb131cdda754065a82c251b02d26ec"> 2848</a></span><span class="preprocessor">#define CAN_F1R1_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02849" name="l02849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7196f5a41c5a7692fa31249177a70de5"> 2849</a></span><span class="preprocessor">#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l02850" name="l02850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf74bbd84aff2eb3891f6f6d0c418793c"> 2850</a></span><span class="preprocessor">#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk </span></div>
|
||
<div class="line"><a id="l02851" name="l02851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1aecffb61aa34f1bfd36d4230fbf1e87"> 2851</a></span><span class="preprocessor">#define CAN_F1R1_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l02852" name="l02852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa957dafcd250c1c36d38a0da7a94d0b6"> 2852</a></span><span class="preprocessor">#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l02853" name="l02853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2cb33663f4220e5a0d416cbddcec193"> 2853</a></span><span class="preprocessor">#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk </span></div>
|
||
<div class="line"><a id="l02854" name="l02854"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e4d64e1f9cacf34eb857db24e2aaed7"> 2854</a></span><span class="preprocessor">#define CAN_F1R1_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l02855" name="l02855"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab76348b5edccc3dff80131b8c8c66d91"> 2855</a></span><span class="preprocessor">#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l02856" name="l02856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86d75200e9ead1afbe88add086ac4bb4"> 2856</a></span><span class="preprocessor">#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk </span></div>
|
||
<div class="line"><a id="l02857" name="l02857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70b163a4031c8c84fd3b1691a0310ffa"> 2857</a></span><span class="preprocessor">#define CAN_F1R1_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l02858" name="l02858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga489dfc442d364861f5f985aae7651179"> 2858</a></span><span class="preprocessor">#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l02859" name="l02859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4dbe3b567fca94f5d5e4c877e0383d4"> 2859</a></span><span class="preprocessor">#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk </span></div>
|
||
<div class="line"><a id="l02860" name="l02860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfea6ec572e4c78a63141351020434f3"> 2860</a></span><span class="preprocessor">#define CAN_F1R1_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l02861" name="l02861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48fba4b8013f5aa76ca9008eb1942423"> 2861</a></span><span class="preprocessor">#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l02862" name="l02862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab74c1e5fba0af06b783289d56a8d743a"> 2862</a></span><span class="preprocessor">#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk </span></div>
|
||
<div class="line"><a id="l02863" name="l02863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07413947413c933237227a8f37ac6728"> 2863</a></span><span class="preprocessor">#define CAN_F1R1_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l02864" name="l02864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13b02c35ea2380f0f839784fc618090a"> 2864</a></span><span class="preprocessor">#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l02865" name="l02865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga163dda15630c6f057bac420a8cb393d8"> 2865</a></span><span class="preprocessor">#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk </span></div>
|
||
<div class="line"><a id="l02866" name="l02866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0428081f736b6a2888514dccd2af1f28"> 2866</a></span><span class="preprocessor">#define CAN_F1R1_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l02867" name="l02867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbe821726bd0ab42de7eb6ba9b497e56"> 2867</a></span><span class="preprocessor">#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l02868" name="l02868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd27041e24d500c940abed9aaa53910d"> 2868</a></span><span class="preprocessor">#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk </span></div>
|
||
<div class="line"><a id="l02869" name="l02869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f7fad2e9157b6680041f1a4ff200af4"> 2869</a></span><span class="preprocessor">#define CAN_F1R1_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l02870" name="l02870"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga655b773dfa0dfe1e62cd8560a8dcb150"> 2870</a></span><span class="preprocessor">#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l02871" name="l02871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadfffc15f309b85cc3abd7439ea4b8c6"> 2871</a></span><span class="preprocessor">#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk </span></div>
|
||
<div class="line"><a id="l02872" name="l02872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72753a76f8413d0a00ace38793d7ec9a"> 2872</a></span><span class="preprocessor">#define CAN_F1R1_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02873" name="l02873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1dd516a1cf52c63b64b028d7528da7b"> 2873</a></span><span class="preprocessor">#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l02874" name="l02874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf2588b13464de27f12768d33a75d2ba"> 2874</a></span><span class="preprocessor">#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk </span></div>
|
||
<div class="line"><a id="l02875" name="l02875"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80f45f8de5ab075f633d21443c8b2226"> 2875</a></span><span class="preprocessor">#define CAN_F1R1_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l02876" name="l02876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4645154d1f265dee267626ae43e35eae"> 2876</a></span><span class="preprocessor">#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l02877" name="l02877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga979839e5c63f94eb294a09b74f5c09bf"> 2877</a></span><span class="preprocessor">#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk </span></div>
|
||
<div class="line"><a id="l02878" name="l02878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf483657f1c8087691588ad2b4e8aa007"> 2878</a></span><span class="preprocessor">#define CAN_F1R1_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l02879" name="l02879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0dbe75098babb0ad9de21a966115c4cb"> 2879</a></span><span class="preprocessor">#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l02880" name="l02880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f049fa606d557a8a468747c6d285357"> 2880</a></span><span class="preprocessor">#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk </span></div>
|
||
<div class="line"><a id="l02881" name="l02881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6ebfb27d5d594fdb472d31751a25092"> 2881</a></span><span class="preprocessor">#define CAN_F1R1_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l02882" name="l02882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b5ea83ec6fdbcc28d0f2c907276bec9"> 2882</a></span><span class="preprocessor">#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l02883" name="l02883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43409866ee9e6ea1712f50679a4bb212"> 2883</a></span><span class="preprocessor">#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk </span></div>
|
||
<div class="line"><a id="l02884" name="l02884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f87b433c7752b209f54f04ecb3f2e40"> 2884</a></span><span class="preprocessor">#define CAN_F1R1_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l02885" name="l02885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd728a049ed7528b585dd56bd4e1d2cd"> 2885</a></span><span class="preprocessor">#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l02886" name="l02886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f86fb2f2080f513d8392d389cdaa1fd"> 2886</a></span><span class="preprocessor">#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk </span></div>
|
||
<div class="line"><a id="l02887" name="l02887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcf14a236c390185aa76b3223e2ab573"> 2887</a></span><span class="preprocessor">#define CAN_F1R1_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l02888" name="l02888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf67d90e15499f16cb9903c75ffa2cdd"> 2888</a></span><span class="preprocessor">#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l02889" name="l02889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c1b7aeeb196a6564b2b3f049590520e"> 2889</a></span><span class="preprocessor">#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk </span></div>
|
||
<div class="line"><a id="l02890" name="l02890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga166ab6b1478e95f89a920b63c1fe83b3"> 2890</a></span><span class="preprocessor">#define CAN_F1R1_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l02891" name="l02891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5dd92e83b650c454a58a4e5bb0a2bae0"> 2891</a></span><span class="preprocessor">#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l02892" name="l02892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45bad406315318f9cecb0c783ac7218d"> 2892</a></span><span class="preprocessor">#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk </span></div>
|
||
<div class="line"><a id="l02893" name="l02893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8dc185faf155706578f28896e413294"> 2893</a></span><span class="preprocessor">#define CAN_F1R1_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l02894" name="l02894"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga303d03c806b2cd4ae51703db085ff55b"> 2894</a></span><span class="preprocessor">#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l02895" name="l02895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b105deaf668c0e04950be0de975bcde"> 2895</a></span><span class="preprocessor">#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk </span></div>
|
||
<div class="line"><a id="l02896" name="l02896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e9dd89c5bb2dbfb38154cf3d0f52f19"> 2896</a></span><span class="preprocessor">#define CAN_F1R1_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02897" name="l02897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd648d6b54d04ac636e7536a08d11ebb"> 2897</a></span><span class="preprocessor">#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l02898" name="l02898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84fabcf9736d7ef78587ff63cb6b1373"> 2898</a></span><span class="preprocessor">#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk </span></div>
|
||
<div class="line"><a id="l02899" name="l02899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9816f741200a82b429a0ea6e18d4f481"> 2899</a></span><span class="preprocessor">#define CAN_F1R1_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l02900" name="l02900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48d839533fbd0dcc34aee11644d5f849"> 2900</a></span><span class="preprocessor">#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l02901" name="l02901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga966d41aca2269fd8cb6830dbbd176140"> 2901</a></span><span class="preprocessor">#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk </span></div>
|
||
<div class="line"><a id="l02902" name="l02902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae67138d3787bf67035e1eb1d7420b999"> 2902</a></span><span class="preprocessor">#define CAN_F1R1_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l02903" name="l02903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab67914799f407244afdbf1ade349dbf3"> 2903</a></span><span class="preprocessor">#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l02904" name="l02904"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a53cd0cf8722dc63b8ff26d4b0fa0f7"> 2904</a></span><span class="preprocessor">#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk </span></div>
|
||
<div class="line"><a id="l02905" name="l02905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac725ea9b9e3b26ac347f66ccc4ddfae4"> 2905</a></span><span class="preprocessor">#define CAN_F1R1_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l02906" name="l02906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e0c47dda83f3ce3f3e5b18f3fb93b35"> 2906</a></span><span class="preprocessor">#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l02907" name="l02907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3fb64b2b59f73045b3ead12ab1211b4b"> 2907</a></span><span class="preprocessor">#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk </span></div>
|
||
<div class="line"><a id="l02908" name="l02908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeba0bf91f16395564def3f873084dc0b"> 2908</a></span><span class="preprocessor">#define CAN_F1R1_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l02909" name="l02909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga122f1435ff77893cee8ec0d39fbfb178"> 2909</a></span><span class="preprocessor">#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l02910" name="l02910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad558faeeeaf748bdface31d4bd3ed5b6"> 2910</a></span><span class="preprocessor">#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk </span></div>
|
||
<div class="line"><a id="l02911" name="l02911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16a40175f3f3d5fdb28dc172aa7a1595"> 2911</a></span><span class="preprocessor">#define CAN_F1R1_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l02912" name="l02912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7164f10425d3caf734b284f3bc3b5449"> 2912</a></span><span class="preprocessor">#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l02913" name="l02913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab16bc53f206b1f318e5fe8c248294fec"> 2913</a></span><span class="preprocessor">#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk </span></div>
|
||
<div class="line"><a id="l02914" name="l02914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga069b7dc2e0e3e0ab6445a2bf2bfc3bed"> 2914</a></span><span class="preprocessor">#define CAN_F1R1_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l02915" name="l02915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ddbed5a2b9531b528d32857123af10a"> 2915</a></span><span class="preprocessor">#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l02916" name="l02916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42841c82744146dc70e8e679b5904e02"> 2916</a></span><span class="preprocessor">#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk </span></div>
|
||
<div class="line"><a id="l02917" name="l02917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1be33c0c1d5b547f65b90e763ac7bbd"> 2917</a></span><span class="preprocessor">#define CAN_F1R1_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l02918" name="l02918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccc01c86ecce551ede43bfeafbbbb384"> 2918</a></span><span class="preprocessor">#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l02919" name="l02919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1f961b642e42faaaf495c9ec099c128"> 2919</a></span><span class="preprocessor">#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk </span></div>
|
||
<div class="line"><a id="l02920" name="l02920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cf527d0f7d4dfa543c7961d56909885"> 2920</a></span><span class="preprocessor">#define CAN_F1R1_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l02921" name="l02921"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9660622aa2fe3253f7b29e7591462002"> 2921</a></span><span class="preprocessor">#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l02922" name="l02922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96670686c71a15631ec2f772973dd7d5"> 2922</a></span><span class="preprocessor">#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk </span></div>
|
||
<div class="line"><a id="l02923" name="l02923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6c5577c558a7f155db47732b868711c"> 2923</a></span><span class="preprocessor">#define CAN_F1R1_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l02924" name="l02924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0f80f8443876e5a992b6b320f19d537"> 2924</a></span><span class="preprocessor">#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l02925" name="l02925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2d8b1a30c3a6ae1f75369abc445ab7d"> 2925</a></span><span class="preprocessor">#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk </span></div>
|
||
<div class="line"><a id="l02926" name="l02926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27cc17673e3a875235664981d3ca221a"> 2926</a></span><span class="preprocessor">#define CAN_F1R1_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l02927" name="l02927"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad90d82d2f8485e7e9a530992ac4a84e0"> 2927</a></span><span class="preprocessor">#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l02928" name="l02928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf027c958889ab93acfb1b86988269874"> 2928</a></span><span class="preprocessor">#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk </span></div>
|
||
<div class="line"><a id="l02929" name="l02929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2db09a50ddde24f79862191ca42bc451"> 2929</a></span><span class="preprocessor">#define CAN_F1R1_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l02930" name="l02930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1dd73fe9a0c9c29fcb103e241ed3c4af"> 2930</a></span><span class="preprocessor">#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l02931" name="l02931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32400e283bc0037da21f0c913bb860b6"> 2931</a></span><span class="preprocessor">#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk </span></div>
|
||
<div class="line"><a id="l02932" name="l02932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e0fe7f80eac137fc59498aaf1a4cda5"> 2932</a></span><span class="preprocessor">#define CAN_F1R1_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l02933" name="l02933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1bc410d11b14bfa426de7b7977bee14"> 2933</a></span><span class="preprocessor">#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l02934" name="l02934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb0467d664f27b3ca8ef4ad220593c46"> 2934</a></span><span class="preprocessor">#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk </span></div>
|
||
<div class="line"><a id="l02935" name="l02935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa51f300d424e7cd192b6af1f81cc2019"> 2935</a></span><span class="preprocessor">#define CAN_F1R1_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l02936" name="l02936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac48a223c7f7282dc22db7c2e0d557f35"> 2936</a></span><span class="preprocessor">#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l02937" name="l02937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c3e3090ab67a54830be208a628efd8f"> 2937</a></span><span class="preprocessor">#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk </span></div>
|
||
<div class="line"><a id="l02938" name="l02938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20dd3f33af971def89d8e3ca8abd8f63"> 2938</a></span><span class="preprocessor">#define CAN_F1R1_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l02939" name="l02939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf45ba201e41f2fd71cda39c7010f65e0"> 2939</a></span><span class="preprocessor">#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l02940" name="l02940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85034e026be1af5e45e5d15537449e6d"> 2940</a></span><span class="preprocessor">#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk </span></div>
|
||
<div class="line"><a id="l02941" name="l02941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e42f6407392d9744b324a3b9bca2ab8"> 2941</a></span><span class="preprocessor">#define CAN_F1R1_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l02942" name="l02942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1345bf0889997c6316180e9754c3e18"> 2942</a></span><span class="preprocessor">#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l02943" name="l02943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ddfc083d58a190057fb67e4eb31136b"> 2943</a></span><span class="preprocessor">#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk </span></div>
|
||
<div class="line"><a id="l02945" name="l02945"></a><span class="lineno"> 2945</span><span class="comment">/******************* Bit definition for CAN_F2R1 register *******************/</span></div>
|
||
<div class="line"><a id="l02946" name="l02946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d22e35b14dc0fd47606ec3e9f5433f0"> 2946</a></span><span class="preprocessor">#define CAN_F2R1_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l02947" name="l02947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac32a7356281dd4bfe7825df1f7cf2cb9"> 2947</a></span><span class="preprocessor">#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l02948" name="l02948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf17f4c3e553020ee893415796bd29d84"> 2948</a></span><span class="preprocessor">#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk </span></div>
|
||
<div class="line"><a id="l02949" name="l02949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bde9b889c0e03d67ce1432aecbd75ce"> 2949</a></span><span class="preprocessor">#define CAN_F2R1_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l02950" name="l02950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63a45584a55de290532b6835fadf480a"> 2950</a></span><span class="preprocessor">#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l02951" name="l02951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae97de172023462e5f40d4b420209809b"> 2951</a></span><span class="preprocessor">#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk </span></div>
|
||
<div class="line"><a id="l02952" name="l02952"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacccd928df24722f7ac8cc22de452ab4b"> 2952</a></span><span class="preprocessor">#define CAN_F2R1_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l02953" name="l02953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42aa2e179dd31d2ef7373acb814223f2"> 2953</a></span><span class="preprocessor">#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l02954" name="l02954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23008ac61893eb6a65ab9041c53a84ee"> 2954</a></span><span class="preprocessor">#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk </span></div>
|
||
<div class="line"><a id="l02955" name="l02955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca191ad3d0d9a8452f6dd9e8465695e5"> 2955</a></span><span class="preprocessor">#define CAN_F2R1_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l02956" name="l02956"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc7f6fc0a5744d9f9246ae814dde3a00"> 2956</a></span><span class="preprocessor">#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l02957" name="l02957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad559580b386d0c621a6bf7292c706e36"> 2957</a></span><span class="preprocessor">#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk </span></div>
|
||
<div class="line"><a id="l02958" name="l02958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc3a2fcc279f4d100b4bf0a3e56c027d"> 2958</a></span><span class="preprocessor">#define CAN_F2R1_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l02959" name="l02959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7555733c5e81d91c22ef16a2954e58a0"> 2959</a></span><span class="preprocessor">#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l02960" name="l02960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e52ca421788d68f3edb9a52434374dd"> 2960</a></span><span class="preprocessor">#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk </span></div>
|
||
<div class="line"><a id="l02961" name="l02961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2706c0511eea92c7c23717696e2039ef"> 2961</a></span><span class="preprocessor">#define CAN_F2R1_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l02962" name="l02962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3302502cfe80c87773630dbb3fe8eab1"> 2962</a></span><span class="preprocessor">#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l02963" name="l02963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96a97a9711a0a53a7ee18907e95d8887"> 2963</a></span><span class="preprocessor">#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk </span></div>
|
||
<div class="line"><a id="l02964" name="l02964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26f556ca64f9a621435b46e87266ceed"> 2964</a></span><span class="preprocessor">#define CAN_F2R1_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l02965" name="l02965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c22e704c9d4404892df4086290e68ec"> 2965</a></span><span class="preprocessor">#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l02966" name="l02966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f73f1bd0d3246f27d7a91a620fb3cc7"> 2966</a></span><span class="preprocessor">#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk </span></div>
|
||
<div class="line"><a id="l02967" name="l02967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga417d9fb1cd03584958223984f973ae45"> 2967</a></span><span class="preprocessor">#define CAN_F2R1_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l02968" name="l02968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga569ec796b80a5c48de939b628a2368d8"> 2968</a></span><span class="preprocessor">#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l02969" name="l02969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72bf4a6050af614eb1ac85c76feb95cc"> 2969</a></span><span class="preprocessor">#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk </span></div>
|
||
<div class="line"><a id="l02970" name="l02970"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ecf568bb243c39cb4b591e10ee4c264"> 2970</a></span><span class="preprocessor">#define CAN_F2R1_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l02971" name="l02971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc5dd0d405b5a0e37c5a7b44e3ddb27d"> 2971</a></span><span class="preprocessor">#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l02972" name="l02972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad484c083bc2023deda5840facc549908"> 2972</a></span><span class="preprocessor">#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk </span></div>
|
||
<div class="line"><a id="l02973" name="l02973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb6429e869387e036a72125c767616a2"> 2973</a></span><span class="preprocessor">#define CAN_F2R1_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l02974" name="l02974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c52c1e2532edd862c9480c22ee72340"> 2974</a></span><span class="preprocessor">#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l02975" name="l02975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d0e05e4824f05e2cf12b3d0a0b7f319"> 2975</a></span><span class="preprocessor">#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk </span></div>
|
||
<div class="line"><a id="l02976" name="l02976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bb1104df1f5ea9a52bad81c16a10f93"> 2976</a></span><span class="preprocessor">#define CAN_F2R1_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l02977" name="l02977"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae64a55a94cadc65b398bd15569223715"> 2977</a></span><span class="preprocessor">#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l02978" name="l02978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga022da7a86e8174aff1054eb1aef2c73c"> 2978</a></span><span class="preprocessor">#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk </span></div>
|
||
<div class="line"><a id="l02979" name="l02979"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8284e29a6acceb7cc51554bb5c1f4e9"> 2979</a></span><span class="preprocessor">#define CAN_F2R1_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l02980" name="l02980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaeac622ae5a702f2f5ca04eb6d07ba57"> 2980</a></span><span class="preprocessor">#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l02981" name="l02981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedf715fa1ef43c8461408944e4aecec7"> 2981</a></span><span class="preprocessor">#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk </span></div>
|
||
<div class="line"><a id="l02982" name="l02982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacccd6d7c8fed17e8a960cdea12e9937c"> 2982</a></span><span class="preprocessor">#define CAN_F2R1_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l02983" name="l02983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6dae1f468ba956371b53f200658cb93e"> 2983</a></span><span class="preprocessor">#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l02984" name="l02984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47960a79c582cbc9bfef85c411a2be94"> 2984</a></span><span class="preprocessor">#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk </span></div>
|
||
<div class="line"><a id="l02985" name="l02985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga859f236a687e19660de99278b9f5639e"> 2985</a></span><span class="preprocessor">#define CAN_F2R1_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l02986" name="l02986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82190e04cc99936f1670f81b3e3306d5"> 2986</a></span><span class="preprocessor">#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l02987" name="l02987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8c6e3cf3a4d1e9d722e820a3a0c1b6a"> 2987</a></span><span class="preprocessor">#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk </span></div>
|
||
<div class="line"><a id="l02988" name="l02988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga719777f190551358a8e55b4551246985"> 2988</a></span><span class="preprocessor">#define CAN_F2R1_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l02989" name="l02989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6722c1954e4dc9dce4931ca68545afd"> 2989</a></span><span class="preprocessor">#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l02990" name="l02990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga421a366074fb422686461a92abd1259e"> 2990</a></span><span class="preprocessor">#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk </span></div>
|
||
<div class="line"><a id="l02991" name="l02991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37fe8abfa46f0bd92db7f7a8c67f89b5"> 2991</a></span><span class="preprocessor">#define CAN_F2R1_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l02992" name="l02992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f6b097d716445b57eb181592d9543c7"> 2992</a></span><span class="preprocessor">#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l02993" name="l02993"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga178a0308db954b97818401be1f28a990"> 2993</a></span><span class="preprocessor">#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk </span></div>
|
||
<div class="line"><a id="l02994" name="l02994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16b5440836903f347ea7693c40da4a01"> 2994</a></span><span class="preprocessor">#define CAN_F2R1_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l02995" name="l02995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d3c41f4d8ac19d40bc8ce0a6c4bf7bf"> 2995</a></span><span class="preprocessor">#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l02996" name="l02996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab60aef7e45f8d12777032321a33cdb38"> 2996</a></span><span class="preprocessor">#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk </span></div>
|
||
<div class="line"><a id="l02997" name="l02997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a962747d2c8ba69f77cccef2add0bf9"> 2997</a></span><span class="preprocessor">#define CAN_F2R1_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l02998" name="l02998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa515e5239f2fb3f7669106b0a42ce00b"> 2998</a></span><span class="preprocessor">#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l02999" name="l02999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0483dac5b6986246a3ba106fbeb8e3bd"> 2999</a></span><span class="preprocessor">#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk </span></div>
|
||
<div class="line"><a id="l03000" name="l03000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70c37fe14d32d847ebb6880849d71e11"> 3000</a></span><span class="preprocessor">#define CAN_F2R1_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l03001" name="l03001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7132daf6ddf622a30b31b0dc82b77bcf"> 3001</a></span><span class="preprocessor">#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l03002" name="l03002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga259b472c9c9f158e1701c8b8d5a940b9"> 3002</a></span><span class="preprocessor">#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk </span></div>
|
||
<div class="line"><a id="l03003" name="l03003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab020e6235fe4c66882df3b253b4898ef"> 3003</a></span><span class="preprocessor">#define CAN_F2R1_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l03004" name="l03004"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55a8f0a1951ca9c9e8cdbac39f64ec6e"> 3004</a></span><span class="preprocessor">#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l03005" name="l03005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23db612c79422bee815e437d6aaf5a6c"> 3005</a></span><span class="preprocessor">#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk </span></div>
|
||
<div class="line"><a id="l03006" name="l03006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32775644499bea180ed6be905e3ac7bc"> 3006</a></span><span class="preprocessor">#define CAN_F2R1_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l03007" name="l03007"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58042a29bd588ca97015f8de46239641"> 3007</a></span><span class="preprocessor">#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l03008" name="l03008"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef9a469e877bfa29f4edb66730c43d43"> 3008</a></span><span class="preprocessor">#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk </span></div>
|
||
<div class="line"><a id="l03009" name="l03009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaeb4b573d828f2498db857114f0b554f"> 3009</a></span><span class="preprocessor">#define CAN_F2R1_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l03010" name="l03010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6e2ea1ce258fc480fb8b2b12a885c9f"> 3010</a></span><span class="preprocessor">#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l03011" name="l03011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4edc4a54cc13f63afe8dbe3aa37776a5"> 3011</a></span><span class="preprocessor">#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk </span></div>
|
||
<div class="line"><a id="l03012" name="l03012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ed5841ad79cc5cf7e76cc3315b65497"> 3012</a></span><span class="preprocessor">#define CAN_F2R1_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l03013" name="l03013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc6ff16cdc9d4b088573f668d99747af"> 3013</a></span><span class="preprocessor">#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l03014" name="l03014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga169f5fb3dd35ae2b048c8c05c3e202d7"> 3014</a></span><span class="preprocessor">#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk </span></div>
|
||
<div class="line"><a id="l03015" name="l03015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3ced515beee7bd23f0d93610bab275b"> 3015</a></span><span class="preprocessor">#define CAN_F2R1_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l03016" name="l03016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9dd3a87b66e7f305670c551b67bff47"> 3016</a></span><span class="preprocessor">#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l03017" name="l03017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0073b206235b3c33a9b831e5027e3bf0"> 3017</a></span><span class="preprocessor">#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk </span></div>
|
||
<div class="line"><a id="l03018" name="l03018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe33b16774b21585c3661fbe2d9123cd"> 3018</a></span><span class="preprocessor">#define CAN_F2R1_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l03019" name="l03019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga353eaadcd9e7a6ffd389c81f75e5b860"> 3019</a></span><span class="preprocessor">#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l03020" name="l03020"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga459caea38417d17c042e52ba38eb3c1b"> 3020</a></span><span class="preprocessor">#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk </span></div>
|
||
<div class="line"><a id="l03021" name="l03021"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56ce415708ca6b0de210d624e9a5f606"> 3021</a></span><span class="preprocessor">#define CAN_F2R1_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l03022" name="l03022"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6516de993c142d8a23cc647e9b06ecd2"> 3022</a></span><span class="preprocessor">#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l03023" name="l03023"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0da8cd8657f6e67f1d86fc9f695bb4e"> 3023</a></span><span class="preprocessor">#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk </span></div>
|
||
<div class="line"><a id="l03024" name="l03024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga110456643d2876e34dd02e537d9c0453"> 3024</a></span><span class="preprocessor">#define CAN_F2R1_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l03025" name="l03025"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14b6583d5cb48decd72eb2bee4113c48"> 3025</a></span><span class="preprocessor">#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l03026" name="l03026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80c9ae7f2eca3db813737c49d49f2b08"> 3026</a></span><span class="preprocessor">#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk </span></div>
|
||
<div class="line"><a id="l03027" name="l03027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bfbbc6638ac01d28fe719942ed800cd"> 3027</a></span><span class="preprocessor">#define CAN_F2R1_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l03028" name="l03028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14b6942aff7b854ed29d7bb8affba388"> 3028</a></span><span class="preprocessor">#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l03029" name="l03029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d6b6c109e359e3d2a07e6626c2b4aff"> 3029</a></span><span class="preprocessor">#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk </span></div>
|
||
<div class="line"><a id="l03030" name="l03030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga782f72de6bdfb681a0790934b38ff480"> 3030</a></span><span class="preprocessor">#define CAN_F2R1_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l03031" name="l03031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6d262f3000a3723269b53cf0c4f3ad2"> 3031</a></span><span class="preprocessor">#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l03032" name="l03032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c4d05997d8930291c8ab2bb19545714"> 3032</a></span><span class="preprocessor">#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk </span></div>
|
||
<div class="line"><a id="l03033" name="l03033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cb04ee516341a536f69fb6c4b87f8b9"> 3033</a></span><span class="preprocessor">#define CAN_F2R1_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l03034" name="l03034"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7dc1ecaa773500c32c41363b2dff8e72"> 3034</a></span><span class="preprocessor">#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l03035" name="l03035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5431f98aafd2a7f8158a335d65ebea1"> 3035</a></span><span class="preprocessor">#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk </span></div>
|
||
<div class="line"><a id="l03036" name="l03036"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb8ecceb7be34c41af7c161d223689a8"> 3036</a></span><span class="preprocessor">#define CAN_F2R1_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l03037" name="l03037"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga317461fc99abac5a1b3c44487499d315"> 3037</a></span><span class="preprocessor">#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l03038" name="l03038"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad79345a758898023543bd5384be09758"> 3038</a></span><span class="preprocessor">#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk </span></div>
|
||
<div class="line"><a id="l03039" name="l03039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab22488fb69df08c9ffc310f3ab575d02"> 3039</a></span><span class="preprocessor">#define CAN_F2R1_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l03040" name="l03040"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ef1c89364eec52f78811d7a8e40d0b4"> 3040</a></span><span class="preprocessor">#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l03041" name="l03041"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaada8442f47c1fffb00c13e404d036122"> 3041</a></span><span class="preprocessor">#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk </span></div>
|
||
<div class="line"><a id="l03043" name="l03043"></a><span class="lineno"> 3043</span><span class="comment">/******************* Bit definition for CAN_F3R1 register *******************/</span></div>
|
||
<div class="line"><a id="l03044" name="l03044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30d5a0c988cb0f7bded01fd1c5bcd9bb"> 3044</a></span><span class="preprocessor">#define CAN_F3R1_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l03045" name="l03045"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c1d5628f543d31326f122516ae8d36c"> 3045</a></span><span class="preprocessor">#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l03046" name="l03046"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6bc065319a9862c1f5ca7326b790ef53"> 3046</a></span><span class="preprocessor">#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk </span></div>
|
||
<div class="line"><a id="l03047" name="l03047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga423e569040031dc2b17a3923d02c7b0a"> 3047</a></span><span class="preprocessor">#define CAN_F3R1_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l03048" name="l03048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4654a2f7909715abd47c047c550d2ca"> 3048</a></span><span class="preprocessor">#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l03049" name="l03049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42e636521c72a20aa8380fe4fe150b91"> 3049</a></span><span class="preprocessor">#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk </span></div>
|
||
<div class="line"><a id="l03050" name="l03050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga183cdb0180529bd94bc2dfd3a2169316"> 3050</a></span><span class="preprocessor">#define CAN_F3R1_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l03051" name="l03051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06d554341693c4f1e9cb5ec2d90c74ca"> 3051</a></span><span class="preprocessor">#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l03052" name="l03052"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga217f5b77e4fefb2d1135187ee2b5bbf2"> 3052</a></span><span class="preprocessor">#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk </span></div>
|
||
<div class="line"><a id="l03053" name="l03053"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga264110432e8f853262985289f403cf69"> 3053</a></span><span class="preprocessor">#define CAN_F3R1_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l03054" name="l03054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga496aa97ec5c7995b3a6da8e9b33c660e"> 3054</a></span><span class="preprocessor">#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l03055" name="l03055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7693dcf6c0011bbeb19e0413a5ce1f56"> 3055</a></span><span class="preprocessor">#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk </span></div>
|
||
<div class="line"><a id="l03056" name="l03056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad686b1dae4008be31598e02f433f4d6c"> 3056</a></span><span class="preprocessor">#define CAN_F3R1_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l03057" name="l03057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62eb0d7464f228fd13f2d567e66b0225"> 3057</a></span><span class="preprocessor">#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l03058" name="l03058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bffde5d3e1e2e75f4facc98903620f7"> 3058</a></span><span class="preprocessor">#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk </span></div>
|
||
<div class="line"><a id="l03059" name="l03059"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38b58c76fcd660c939b781c7e82a8b81"> 3059</a></span><span class="preprocessor">#define CAN_F3R1_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l03060" name="l03060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e25fcc0e53a3e2d271e06f8985a1e98"> 3060</a></span><span class="preprocessor">#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l03061" name="l03061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30ccdfd3676f314e749cc205ffcfe1cf"> 3061</a></span><span class="preprocessor">#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk </span></div>
|
||
<div class="line"><a id="l03062" name="l03062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c71ff110c18c45c1111ff2ec255da30"> 3062</a></span><span class="preprocessor">#define CAN_F3R1_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l03063" name="l03063"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fa5eeffce32825d18dd6ae540691a43"> 3063</a></span><span class="preprocessor">#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l03064" name="l03064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b2aa80397b4961a33b41303aa348ea1"> 3064</a></span><span class="preprocessor">#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk </span></div>
|
||
<div class="line"><a id="l03065" name="l03065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e1076d0bccc07adfcfdd9b10ef70d49"> 3065</a></span><span class="preprocessor">#define CAN_F3R1_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l03066" name="l03066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f51e4b529f2c096fb6fec2b6d7df1f5"> 3066</a></span><span class="preprocessor">#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l03067" name="l03067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b7072c9b829c7df660eb2dea05ee8d8"> 3067</a></span><span class="preprocessor">#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk </span></div>
|
||
<div class="line"><a id="l03068" name="l03068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99ec42fffa4e19dd6841adeb7c581bbe"> 3068</a></span><span class="preprocessor">#define CAN_F3R1_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l03069" name="l03069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa223fb562425adcb7022b2b5e6f0da6"> 3069</a></span><span class="preprocessor">#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l03070" name="l03070"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad016208d1aa9008aaba9a887a1e8b6fa"> 3070</a></span><span class="preprocessor">#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk </span></div>
|
||
<div class="line"><a id="l03071" name="l03071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a409b79ae2582691f8998c525f259fc"> 3071</a></span><span class="preprocessor">#define CAN_F3R1_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l03072" name="l03072"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga900e4c0c595155e852cbc17fda96e9ee"> 3072</a></span><span class="preprocessor">#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l03073" name="l03073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4f4f0d2b56860e36f7777ab397e8609"> 3073</a></span><span class="preprocessor">#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk </span></div>
|
||
<div class="line"><a id="l03074" name="l03074"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5bff557fd63b73e4490b972bb5ac946"> 3074</a></span><span class="preprocessor">#define CAN_F3R1_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l03075" name="l03075"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a3ae8c895b853d340ff7a133870164a"> 3075</a></span><span class="preprocessor">#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l03076" name="l03076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcfc2559b456c3af3804a22e0fb5c50d"> 3076</a></span><span class="preprocessor">#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk </span></div>
|
||
<div class="line"><a id="l03077" name="l03077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9f0a4a347f318e110ce2139acb78b13"> 3077</a></span><span class="preprocessor">#define CAN_F3R1_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l03078" name="l03078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68222a41a14bb43bc6d2f0fc4dee1e0f"> 3078</a></span><span class="preprocessor">#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l03079" name="l03079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7df8031e3a2f661b45fdbde58a26c6b6"> 3079</a></span><span class="preprocessor">#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk </span></div>
|
||
<div class="line"><a id="l03080" name="l03080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2d38f5393492a54b470fa2b985cec67"> 3080</a></span><span class="preprocessor">#define CAN_F3R1_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l03081" name="l03081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec2bac1777b3ebef8b3a22d22514a4b2"> 3081</a></span><span class="preprocessor">#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l03082" name="l03082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c6baa9ac6a1cdd55c2d51ee40cf8f2d"> 3082</a></span><span class="preprocessor">#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk </span></div>
|
||
<div class="line"><a id="l03083" name="l03083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafaf1ceb6b25d05652aba0ef3a04caf40"> 3083</a></span><span class="preprocessor">#define CAN_F3R1_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l03084" name="l03084"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47f4c6942bebdcb179b5092520842e91"> 3084</a></span><span class="preprocessor">#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l03085" name="l03085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95fc8c778ffa6deac5a202985fdd98ae"> 3085</a></span><span class="preprocessor">#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk </span></div>
|
||
<div class="line"><a id="l03086" name="l03086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2792beb7bfcf3e2ca26e092bb4ed2d50"> 3086</a></span><span class="preprocessor">#define CAN_F3R1_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l03087" name="l03087"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3cbf7b6b28dce1e65f4377273b060b7"> 3087</a></span><span class="preprocessor">#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l03088" name="l03088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c4a4998f2ddc12771da116b1c20d765"> 3088</a></span><span class="preprocessor">#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk </span></div>
|
||
<div class="line"><a id="l03089" name="l03089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7087ca402b574d4cce164525a75942c1"> 3089</a></span><span class="preprocessor">#define CAN_F3R1_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l03090" name="l03090"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d5afdf5c983489b0bcd8029a6e1c45a"> 3090</a></span><span class="preprocessor">#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l03091" name="l03091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fb6157fc48147e6c74ed348d156bfa1"> 3091</a></span><span class="preprocessor">#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk </span></div>
|
||
<div class="line"><a id="l03092" name="l03092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69cf5d074fb4b4a823b2f2071b5a391d"> 3092</a></span><span class="preprocessor">#define CAN_F3R1_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l03093" name="l03093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadc1997d8f970761e068263b8aa9f439"> 3093</a></span><span class="preprocessor">#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l03094" name="l03094"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadcf2a14e752519bf8a90129fb9d42b1"> 3094</a></span><span class="preprocessor">#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk </span></div>
|
||
<div class="line"><a id="l03095" name="l03095"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadccd15d0bba8530373bb5beafd51ccff"> 3095</a></span><span class="preprocessor">#define CAN_F3R1_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l03096" name="l03096"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8221248c305454dd5071679742a56383"> 3096</a></span><span class="preprocessor">#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l03097" name="l03097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47c5296c991b481548302478df85e477"> 3097</a></span><span class="preprocessor">#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk </span></div>
|
||
<div class="line"><a id="l03098" name="l03098"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga667df86ec3ab1ef7d9a90d3e69a97ef7"> 3098</a></span><span class="preprocessor">#define CAN_F3R1_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l03099" name="l03099"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad84e18a8d220d1dbf071afcbe969b976"> 3099</a></span><span class="preprocessor">#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l03100" name="l03100"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga657b8cda94fd736a4831ab4086ae746f"> 3100</a></span><span class="preprocessor">#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk </span></div>
|
||
<div class="line"><a id="l03101" name="l03101"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e23acb5ecf6e18637060239a690c034"> 3101</a></span><span class="preprocessor">#define CAN_F3R1_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l03102" name="l03102"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3806303c3cfe2dcee6e3409eb1492b6"> 3102</a></span><span class="preprocessor">#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l03103" name="l03103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga435edc4b2055ac2d1c3ce616a9c1b236"> 3103</a></span><span class="preprocessor">#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk </span></div>
|
||
<div class="line"><a id="l03104" name="l03104"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf81dbe7a19466ef9c89804d77b695a8a"> 3104</a></span><span class="preprocessor">#define CAN_F3R1_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l03105" name="l03105"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05e8b9d7e4cdc6856c6ad61d15fae9f2"> 3105</a></span><span class="preprocessor">#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l03106" name="l03106"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa508de7087eb832ecaf353a4b6821ef"> 3106</a></span><span class="preprocessor">#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk </span></div>
|
||
<div class="line"><a id="l03107" name="l03107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga504f3a0b162d61b85df522610ce39ef7"> 3107</a></span><span class="preprocessor">#define CAN_F3R1_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l03108" name="l03108"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1c6bf19e9356adcb47a75895b653025"> 3108</a></span><span class="preprocessor">#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l03109" name="l03109"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga643ceb9293665b8307e63ae0e1700d91"> 3109</a></span><span class="preprocessor">#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk </span></div>
|
||
<div class="line"><a id="l03110" name="l03110"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga802dd3b3cb24cf29fef5a437d611f374"> 3110</a></span><span class="preprocessor">#define CAN_F3R1_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l03111" name="l03111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12f9cc55362b508457dae2a22f3577b9"> 3111</a></span><span class="preprocessor">#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l03112" name="l03112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91f5887e884fcf423d680798f4e372bb"> 3112</a></span><span class="preprocessor">#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk </span></div>
|
||
<div class="line"><a id="l03113" name="l03113"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b4c505b76333edc055ec8185ce9cca3"> 3113</a></span><span class="preprocessor">#define CAN_F3R1_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l03114" name="l03114"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53b384413c96686c5b6d955edf3605e7"> 3114</a></span><span class="preprocessor">#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l03115" name="l03115"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6adc9c7706f39f7c33760fe6b8c5d17e"> 3115</a></span><span class="preprocessor">#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk </span></div>
|
||
<div class="line"><a id="l03116" name="l03116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae72365189f731236a0347f2577b26ad1"> 3116</a></span><span class="preprocessor">#define CAN_F3R1_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l03117" name="l03117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84c095337bdce797f169006a2b79ecda"> 3117</a></span><span class="preprocessor">#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l03118" name="l03118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7581186f0241f6db9f63a0a0db22919"> 3118</a></span><span class="preprocessor">#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk </span></div>
|
||
<div class="line"><a id="l03119" name="l03119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7eb5954b6b37e1c895c7e5379b9ed89"> 3119</a></span><span class="preprocessor">#define CAN_F3R1_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l03120" name="l03120"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad411d7ebb23972f68d8d3622a89de73e"> 3120</a></span><span class="preprocessor">#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l03121" name="l03121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43b4c084e802398ad265ceb69cfd7519"> 3121</a></span><span class="preprocessor">#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk </span></div>
|
||
<div class="line"><a id="l03122" name="l03122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa963a783c31dfb619f95c5f36fbbbfbb"> 3122</a></span><span class="preprocessor">#define CAN_F3R1_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l03123" name="l03123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56aa4a1d23228828e880810e6d644054"> 3123</a></span><span class="preprocessor">#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l03124" name="l03124"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade732503a8d41e3f1bb338a2a8103bd2"> 3124</a></span><span class="preprocessor">#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk </span></div>
|
||
<div class="line"><a id="l03125" name="l03125"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga402faf6e5640540970f69b796fec57bc"> 3125</a></span><span class="preprocessor">#define CAN_F3R1_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l03126" name="l03126"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a14d8e964a880b27705af96225917cb"> 3126</a></span><span class="preprocessor">#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l03127" name="l03127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7539a7f651425a757a549205544e508c"> 3127</a></span><span class="preprocessor">#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk </span></div>
|
||
<div class="line"><a id="l03128" name="l03128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac25fde9cd308c5fde521c6c649112109"> 3128</a></span><span class="preprocessor">#define CAN_F3R1_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l03129" name="l03129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62dea0d389306d34595416ca334c7bf1"> 3129</a></span><span class="preprocessor">#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l03130" name="l03130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ec25e4ba3ebaf53780e2b8da63e4a3b"> 3130</a></span><span class="preprocessor">#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk </span></div>
|
||
<div class="line"><a id="l03131" name="l03131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf98ffdf9966c92a5cbbcb23ad6c36b1a"> 3131</a></span><span class="preprocessor">#define CAN_F3R1_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l03132" name="l03132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04da25e051a24c10b8d59f6a87818fb0"> 3132</a></span><span class="preprocessor">#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l03133" name="l03133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8268be8b5477f813c165e851acd41a2"> 3133</a></span><span class="preprocessor">#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk </span></div>
|
||
<div class="line"><a id="l03134" name="l03134"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a6f8058f778d1ec69794aa937d96337"> 3134</a></span><span class="preprocessor">#define CAN_F3R1_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l03135" name="l03135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc9b888a2c0f23588c4f79d7e1545c61"> 3135</a></span><span class="preprocessor">#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l03136" name="l03136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga494ad7f35d8552b8494379916a987074"> 3136</a></span><span class="preprocessor">#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk </span></div>
|
||
<div class="line"><a id="l03137" name="l03137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab45325d0fb96d86f848601a582e47a5d"> 3137</a></span><span class="preprocessor">#define CAN_F3R1_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l03138" name="l03138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf5486013f92f3646e9ac903676b6743"> 3138</a></span><span class="preprocessor">#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l03139" name="l03139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15bbe0d2d24dc95e10156c2541feb4c4"> 3139</a></span><span class="preprocessor">#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk </span></div>
|
||
<div class="line"><a id="l03141" name="l03141"></a><span class="lineno"> 3141</span><span class="comment">/******************* Bit definition for CAN_F4R1 register *******************/</span></div>
|
||
<div class="line"><a id="l03142" name="l03142"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5573bdc4becbeaab63e285f60bb316c6"> 3142</a></span><span class="preprocessor">#define CAN_F4R1_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l03143" name="l03143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7988e6a122cc6084ea40df4b66de5f0f"> 3143</a></span><span class="preprocessor">#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l03144" name="l03144"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0eb0d4d21c082c8381271ab146431993"> 3144</a></span><span class="preprocessor">#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk </span></div>
|
||
<div class="line"><a id="l03145" name="l03145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga279a547f6c7143c59c912d85973493d1"> 3145</a></span><span class="preprocessor">#define CAN_F4R1_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l03146" name="l03146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa88382bdd2a166258413d39fbb436050"> 3146</a></span><span class="preprocessor">#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l03147" name="l03147"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91922c78bf92f051b8e8abbf9cc1f6e9"> 3147</a></span><span class="preprocessor">#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk </span></div>
|
||
<div class="line"><a id="l03148" name="l03148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae735647331c284d403b4917ff3b213ce"> 3148</a></span><span class="preprocessor">#define CAN_F4R1_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l03149" name="l03149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6564dfdae0be64785df0d766aa5c149"> 3149</a></span><span class="preprocessor">#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l03150" name="l03150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae56f77f869114e69525353f96004f955"> 3150</a></span><span class="preprocessor">#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk </span></div>
|
||
<div class="line"><a id="l03151" name="l03151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac731872ee45a7e0569871bfb02c6b6e9"> 3151</a></span><span class="preprocessor">#define CAN_F4R1_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l03152" name="l03152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga786fe254e7a86a2ac517ea453f78e120"> 3152</a></span><span class="preprocessor">#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l03153" name="l03153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga951a8213e55b01ecedcef870c85841e7"> 3153</a></span><span class="preprocessor">#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk </span></div>
|
||
<div class="line"><a id="l03154" name="l03154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17f4894ca5438e060ea17fcb6d0d2f9b"> 3154</a></span><span class="preprocessor">#define CAN_F4R1_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l03155" name="l03155"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd92184f0f30164e14b07a7a4e5208a2"> 3155</a></span><span class="preprocessor">#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l03156" name="l03156"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga453f90cdd0b520b7d65e19af3868d4ec"> 3156</a></span><span class="preprocessor">#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk </span></div>
|
||
<div class="line"><a id="l03157" name="l03157"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3eff06bd3294a077a43d55419ecbfbb"> 3157</a></span><span class="preprocessor">#define CAN_F4R1_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l03158" name="l03158"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a8707829180a6a5ea26822a408facce"> 3158</a></span><span class="preprocessor">#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l03159" name="l03159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace348ba56c1f9676e5b605a6fe0cd52e"> 3159</a></span><span class="preprocessor">#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk </span></div>
|
||
<div class="line"><a id="l03160" name="l03160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaea2a7ac1148da335845a257f1dde33e"> 3160</a></span><span class="preprocessor">#define CAN_F4R1_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l03161" name="l03161"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga270fa51a92450225b554f19353f38f0e"> 3161</a></span><span class="preprocessor">#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l03162" name="l03162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae99d36b50a16c38b2006fdba4683ddd9"> 3162</a></span><span class="preprocessor">#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk </span></div>
|
||
<div class="line"><a id="l03163" name="l03163"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4c8a70e48e55e45b8d3322a344bfa45"> 3163</a></span><span class="preprocessor">#define CAN_F4R1_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l03164" name="l03164"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga474765e4a523545019ad84e02c9af69c"> 3164</a></span><span class="preprocessor">#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l03165" name="l03165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d61ae4af9acc61476493b640cfb4745"> 3165</a></span><span class="preprocessor">#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk </span></div>
|
||
<div class="line"><a id="l03166" name="l03166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4e861543c2dd0e3bfbd34fd6e97927f"> 3166</a></span><span class="preprocessor">#define CAN_F4R1_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l03167" name="l03167"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa256896c733d9155ab9c60d6f2d58a3b"> 3167</a></span><span class="preprocessor">#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l03168" name="l03168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89ded00ec0b6c0918b019457d6cf43f5"> 3168</a></span><span class="preprocessor">#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk </span></div>
|
||
<div class="line"><a id="l03169" name="l03169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fe495bcc370cfd21bdf1b6e751aa23a"> 3169</a></span><span class="preprocessor">#define CAN_F4R1_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l03170" name="l03170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4fdff1d01f74ad524f97bd3a138e6c4d"> 3170</a></span><span class="preprocessor">#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l03171" name="l03171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac658a1ced873fd9dff54833d8c413536"> 3171</a></span><span class="preprocessor">#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk </span></div>
|
||
<div class="line"><a id="l03172" name="l03172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34153173f76d8b1aacbdd013a733fdd2"> 3172</a></span><span class="preprocessor">#define CAN_F4R1_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l03173" name="l03173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d5e8f2c67a528aa361922158ae8eb92"> 3173</a></span><span class="preprocessor">#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l03174" name="l03174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad06bc748776a78f008895be9e0cc7a1d"> 3174</a></span><span class="preprocessor">#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk </span></div>
|
||
<div class="line"><a id="l03175" name="l03175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8adba35f6ed518c3d762d8c791cfb85"> 3175</a></span><span class="preprocessor">#define CAN_F4R1_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l03176" name="l03176"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50cb96e2d638c18f5ce23bed3342f39d"> 3176</a></span><span class="preprocessor">#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l03177" name="l03177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf612f239dcf45bd933136a5c8c5909f9"> 3177</a></span><span class="preprocessor">#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk </span></div>
|
||
<div class="line"><a id="l03178" name="l03178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa308445d00347d34a263c82c0b5cc5a"> 3178</a></span><span class="preprocessor">#define CAN_F4R1_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l03179" name="l03179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga613094782d73b0e3e5272eff72f04d42"> 3179</a></span><span class="preprocessor">#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l03180" name="l03180"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6dc611a52acf6dfa1df7ebf867bc7e2f"> 3180</a></span><span class="preprocessor">#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk </span></div>
|
||
<div class="line"><a id="l03181" name="l03181"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6329ecd1b3904d370e9db06936fd0f5"> 3181</a></span><span class="preprocessor">#define CAN_F4R1_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l03182" name="l03182"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07c564a28ae0d2958891d26110e4c411"> 3182</a></span><span class="preprocessor">#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l03183" name="l03183"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1736bc2808a37aa82358fe1c36c963a6"> 3183</a></span><span class="preprocessor">#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk </span></div>
|
||
<div class="line"><a id="l03184" name="l03184"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e223d1503fe560272d3851eef5850e0"> 3184</a></span><span class="preprocessor">#define CAN_F4R1_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l03185" name="l03185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c7d95aae3c918a4c446ecd57f876383"> 3185</a></span><span class="preprocessor">#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l03186" name="l03186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d7ec466bbf196a41f6da2a7b506675d"> 3186</a></span><span class="preprocessor">#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk </span></div>
|
||
<div class="line"><a id="l03187" name="l03187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga801c05f9333d89c49f62aca3b77152c1"> 3187</a></span><span class="preprocessor">#define CAN_F4R1_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l03188" name="l03188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf226c102853cbf2918931586573641bf"> 3188</a></span><span class="preprocessor">#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l03189" name="l03189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad30ff7e7b0c0f7e56821ecbcd6fcc23c"> 3189</a></span><span class="preprocessor">#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk </span></div>
|
||
<div class="line"><a id="l03190" name="l03190"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9961594daf8302213f375760ba658031"> 3190</a></span><span class="preprocessor">#define CAN_F4R1_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l03191" name="l03191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5885429c36cad6e1bae78efccc6f4c59"> 3191</a></span><span class="preprocessor">#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l03192" name="l03192"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga199bd29b6f3ff56150a9dcd71c8ea13f"> 3192</a></span><span class="preprocessor">#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk </span></div>
|
||
<div class="line"><a id="l03193" name="l03193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b0f6c8b0cd3bedcb4d900b936cb1206"> 3193</a></span><span class="preprocessor">#define CAN_F4R1_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l03194" name="l03194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa31c54bcaf590c65c626253362949c8"> 3194</a></span><span class="preprocessor">#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l03195" name="l03195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga893837534cbc7a043fa995de4619e2da"> 3195</a></span><span class="preprocessor">#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk </span></div>
|
||
<div class="line"><a id="l03196" name="l03196"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga618cffe573cd6ccff53130f3beb6bfcb"> 3196</a></span><span class="preprocessor">#define CAN_F4R1_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l03197" name="l03197"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d6925aa9feee56fba36b3a4e399c2d8"> 3197</a></span><span class="preprocessor">#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l03198" name="l03198"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga551e80c41958417cbcf1d0c53e4947a3"> 3198</a></span><span class="preprocessor">#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk </span></div>
|
||
<div class="line"><a id="l03199" name="l03199"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe302668b9837570409f0e5dafca0480"> 3199</a></span><span class="preprocessor">#define CAN_F4R1_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l03200" name="l03200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebb1f9e546b4c8bb2bcb3d6e9a1f0949"> 3200</a></span><span class="preprocessor">#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l03201" name="l03201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80d9a946bd39dae4b0a862cf21f262ed"> 3201</a></span><span class="preprocessor">#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk </span></div>
|
||
<div class="line"><a id="l03202" name="l03202"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27b7d0c5f497cf6c9bc7e7fa16eccfd9"> 3202</a></span><span class="preprocessor">#define CAN_F4R1_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l03203" name="l03203"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga119fbe324a31a61a0b5aa989658cf15d"> 3203</a></span><span class="preprocessor">#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l03204" name="l03204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5646609987ce174cf3b94bb4538172f4"> 3204</a></span><span class="preprocessor">#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk </span></div>
|
||
<div class="line"><a id="l03205" name="l03205"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec476098d3c0d9c6025f6a2bd35a7f9b"> 3205</a></span><span class="preprocessor">#define CAN_F4R1_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l03206" name="l03206"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa57165c0d07048b0024f56e0febdaccd"> 3206</a></span><span class="preprocessor">#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l03207" name="l03207"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga356faa77de97c61e9b5f6b763173a987"> 3207</a></span><span class="preprocessor">#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk </span></div>
|
||
<div class="line"><a id="l03208" name="l03208"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd5edc6ee520a4896e71f9613676f744"> 3208</a></span><span class="preprocessor">#define CAN_F4R1_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l03209" name="l03209"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91bdc8395c27e8e23092b3f9784b7994"> 3209</a></span><span class="preprocessor">#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l03210" name="l03210"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6b246b3df35cc1db06e8c809137562f"> 3210</a></span><span class="preprocessor">#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk </span></div>
|
||
<div class="line"><a id="l03211" name="l03211"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb9a14d13a2ce6fb41594c8ebc9d1a62"> 3211</a></span><span class="preprocessor">#define CAN_F4R1_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l03212" name="l03212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac32276ab0a34c8ae46eee73ad1f208d7"> 3212</a></span><span class="preprocessor">#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l03213" name="l03213"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4882da3ee5be3aed3d5eb46923859674"> 3213</a></span><span class="preprocessor">#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk </span></div>
|
||
<div class="line"><a id="l03214" name="l03214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5666249f8189bddecf0c24687fb8e1a"> 3214</a></span><span class="preprocessor">#define CAN_F4R1_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l03215" name="l03215"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e1033412ffe01f17f87d0287af5bd70"> 3215</a></span><span class="preprocessor">#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l03216" name="l03216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e178aa8c6f98a866aaae511b9da86c8"> 3216</a></span><span class="preprocessor">#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk </span></div>
|
||
<div class="line"><a id="l03217" name="l03217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6aedd4cfb249867dc58b58f6f4cbedbb"> 3217</a></span><span class="preprocessor">#define CAN_F4R1_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l03218" name="l03218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d8fcea6cb9dd0d6240208ed38acecdc"> 3218</a></span><span class="preprocessor">#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l03219" name="l03219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a5ca327060530761d71362d39b2d364"> 3219</a></span><span class="preprocessor">#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk </span></div>
|
||
<div class="line"><a id="l03220" name="l03220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e69fe695c9a2aa5f7ebf5f8674022bd"> 3220</a></span><span class="preprocessor">#define CAN_F4R1_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l03221" name="l03221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2abd932d950db3d7aafbb9af2639a57"> 3221</a></span><span class="preprocessor">#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l03222" name="l03222"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeabe4836aed74af4adba72b2c7684a6e"> 3222</a></span><span class="preprocessor">#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk </span></div>
|
||
<div class="line"><a id="l03223" name="l03223"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae89e6768b343f3cf2702266b2832ecdc"> 3223</a></span><span class="preprocessor">#define CAN_F4R1_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l03224" name="l03224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac34b9b4abc8d9196ce7aab200c99787c"> 3224</a></span><span class="preprocessor">#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l03225" name="l03225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa8e7d74919e74723f7df71357cc994a"> 3225</a></span><span class="preprocessor">#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk </span></div>
|
||
<div class="line"><a id="l03226" name="l03226"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06a31d8ddb814f830f830b8831821bc4"> 3226</a></span><span class="preprocessor">#define CAN_F4R1_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l03227" name="l03227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga008f59ed84fb846c36803d37e52c09d0"> 3227</a></span><span class="preprocessor">#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l03228" name="l03228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e2b2b9bd5b397e58d57fb379546110b"> 3228</a></span><span class="preprocessor">#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk </span></div>
|
||
<div class="line"><a id="l03229" name="l03229"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fcd8e8ee759e498a068f300ebd67923"> 3229</a></span><span class="preprocessor">#define CAN_F4R1_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l03230" name="l03230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd6c2fc9688b65bda0ca6b9e18e0c072"> 3230</a></span><span class="preprocessor">#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l03231" name="l03231"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb165ede225dc35a825647e5efcab437"> 3231</a></span><span class="preprocessor">#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk </span></div>
|
||
<div class="line"><a id="l03232" name="l03232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga905946914d80198f6e0ecc939097904d"> 3232</a></span><span class="preprocessor">#define CAN_F4R1_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l03233" name="l03233"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2012557ac8ac7ddd510c1dd771062dc2"> 3233</a></span><span class="preprocessor">#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l03234" name="l03234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7898b1f422424fd7fc0896b908748e7c"> 3234</a></span><span class="preprocessor">#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk </span></div>
|
||
<div class="line"><a id="l03235" name="l03235"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1788952bedbeb5ee6a7aff15180cdd85"> 3235</a></span><span class="preprocessor">#define CAN_F4R1_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l03236" name="l03236"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe91e1b46bc8af15c5d727b81e51bfdb"> 3236</a></span><span class="preprocessor">#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l03237" name="l03237"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92d7e6a44e87911e9cc14f6bff854fa2"> 3237</a></span><span class="preprocessor">#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk </span></div>
|
||
<div class="line"><a id="l03239" name="l03239"></a><span class="lineno"> 3239</span><span class="comment">/******************* Bit definition for CAN_F5R1 register *******************/</span></div>
|
||
<div class="line"><a id="l03240" name="l03240"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d79dff94ff5fac00e5f6a357e44f85e"> 3240</a></span><span class="preprocessor">#define CAN_F5R1_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l03241" name="l03241"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18f8312b10016a8ad987ceaa48f7a67f"> 3241</a></span><span class="preprocessor">#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l03242" name="l03242"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5cdf98e317662e286ad2a3344ee516df"> 3242</a></span><span class="preprocessor">#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk </span></div>
|
||
<div class="line"><a id="l03243" name="l03243"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a8d5c8f4366ceabcfe2f90c570bb475"> 3243</a></span><span class="preprocessor">#define CAN_F5R1_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l03244" name="l03244"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4421f59236d1bd77fadc2e093c988466"> 3244</a></span><span class="preprocessor">#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l03245" name="l03245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac814c424ed2ccc11645da6e62f3fb81"> 3245</a></span><span class="preprocessor">#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk </span></div>
|
||
<div class="line"><a id="l03246" name="l03246"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95b23df31b5f7c3556c2702e20c923d6"> 3246</a></span><span class="preprocessor">#define CAN_F5R1_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l03247" name="l03247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39beb5641b129903d6d43a152b9b1fc2"> 3247</a></span><span class="preprocessor">#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l03248" name="l03248"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b0af1936dd43bd319614e3298fd28d1"> 3248</a></span><span class="preprocessor">#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk </span></div>
|
||
<div class="line"><a id="l03249" name="l03249"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabca05592268e423c5ebe595aa0b66bab"> 3249</a></span><span class="preprocessor">#define CAN_F5R1_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l03250" name="l03250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c30456c58159fc9c8b5fc705a897c4b"> 3250</a></span><span class="preprocessor">#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l03251" name="l03251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga013f84e3f3f0e148d3a9a071ccbf6738"> 3251</a></span><span class="preprocessor">#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk </span></div>
|
||
<div class="line"><a id="l03252" name="l03252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c9a7e1161697ffdc810058033c3c915"> 3252</a></span><span class="preprocessor">#define CAN_F5R1_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l03253" name="l03253"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecdbb3ad483c253075f585fb453e6fb8"> 3253</a></span><span class="preprocessor">#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l03254" name="l03254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cfc330921811d76ed6476d6935e84e7"> 3254</a></span><span class="preprocessor">#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk </span></div>
|
||
<div class="line"><a id="l03255" name="l03255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7703402af1cdf92f4711ced3fc67c1ca"> 3255</a></span><span class="preprocessor">#define CAN_F5R1_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l03256" name="l03256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa323c7e6521417879450a4d5996e256"> 3256</a></span><span class="preprocessor">#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l03257" name="l03257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9aebaa8e61198240c1564ce73acb1d2"> 3257</a></span><span class="preprocessor">#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk </span></div>
|
||
<div class="line"><a id="l03258" name="l03258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga256f07a9ee561dfc60a6a3f75d9802e9"> 3258</a></span><span class="preprocessor">#define CAN_F5R1_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l03259" name="l03259"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7e09b9fe8aeb61f4253d15d6bd808f0"> 3259</a></span><span class="preprocessor">#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l03260" name="l03260"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadea331fb6273fda80a8f5a3dc8eaf6f4"> 3260</a></span><span class="preprocessor">#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk </span></div>
|
||
<div class="line"><a id="l03261" name="l03261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f5bf9e5ed786525dbe37eda02710a47"> 3261</a></span><span class="preprocessor">#define CAN_F5R1_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l03262" name="l03262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8ddbee4662088695a19791d9754f060"> 3262</a></span><span class="preprocessor">#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l03263" name="l03263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc7dfaacfba6a42a17b16281f690f952"> 3263</a></span><span class="preprocessor">#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk </span></div>
|
||
<div class="line"><a id="l03264" name="l03264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d5f9ec2683178e836dabd60294ed4b5"> 3264</a></span><span class="preprocessor">#define CAN_F5R1_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l03265" name="l03265"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b80299e85591ee7bb2669dfbd7beced"> 3265</a></span><span class="preprocessor">#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l03266" name="l03266"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba0938e0f55773406fd59c2a0bd7c46e"> 3266</a></span><span class="preprocessor">#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk </span></div>
|
||
<div class="line"><a id="l03267" name="l03267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefafeaebf2f2d7db4ec1c34ab58b7d0d"> 3267</a></span><span class="preprocessor">#define CAN_F5R1_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l03268" name="l03268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad909d1a8817b8daf42ad0ebd18551ae8"> 3268</a></span><span class="preprocessor">#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l03269" name="l03269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9715c4445159d0068172309092e574e3"> 3269</a></span><span class="preprocessor">#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk </span></div>
|
||
<div class="line"><a id="l03270" name="l03270"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d808208c09dd6604510d037d65d804a"> 3270</a></span><span class="preprocessor">#define CAN_F5R1_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l03271" name="l03271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1eba02afe3b8e8f8eebaa38b8499604c"> 3271</a></span><span class="preprocessor">#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l03272" name="l03272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7de15e73395473569a447023dae53c4"> 3272</a></span><span class="preprocessor">#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk </span></div>
|
||
<div class="line"><a id="l03273" name="l03273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8551f14a24c6f6dabb131b9e817a013e"> 3273</a></span><span class="preprocessor">#define CAN_F5R1_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l03274" name="l03274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae735eeb78cc75daa1870ea4d2141e40e"> 3274</a></span><span class="preprocessor">#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l03275" name="l03275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39b60e0befdf681694bc4123b4b7f7bd"> 3275</a></span><span class="preprocessor">#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk </span></div>
|
||
<div class="line"><a id="l03276" name="l03276"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c27662a1518dfbd5d0217709864fc8c"> 3276</a></span><span class="preprocessor">#define CAN_F5R1_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l03277" name="l03277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa57169fb0310c42945b03d791c2f54b"> 3277</a></span><span class="preprocessor">#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l03278" name="l03278"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bc4598d0d603c802b7140f967d84e5c"> 3278</a></span><span class="preprocessor">#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk </span></div>
|
||
<div class="line"><a id="l03279" name="l03279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7b7acc6d79a2decd37c40676d6a2aa7"> 3279</a></span><span class="preprocessor">#define CAN_F5R1_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l03280" name="l03280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65f520a74c377435d6bbbaf002bd72bf"> 3280</a></span><span class="preprocessor">#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l03281" name="l03281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8b4439ac4bc79ff74d21060ff533b12"> 3281</a></span><span class="preprocessor">#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk </span></div>
|
||
<div class="line"><a id="l03282" name="l03282"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37ae18d19c8de2e1d7700aa436fbf0bb"> 3282</a></span><span class="preprocessor">#define CAN_F5R1_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l03283" name="l03283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35a677ded1b04b0ba090b33e4558f658"> 3283</a></span><span class="preprocessor">#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l03284" name="l03284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d117ee64d9c1673f22f12f24bd481a4"> 3284</a></span><span class="preprocessor">#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk </span></div>
|
||
<div class="line"><a id="l03285" name="l03285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fb993ec1c88ae403c53a086db275ac2"> 3285</a></span><span class="preprocessor">#define CAN_F5R1_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l03286" name="l03286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfe4d49efd13e228ed872dbe7f8b5a6c"> 3286</a></span><span class="preprocessor">#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l03287" name="l03287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf761c448bf29c4d93f4c2a75981fa049"> 3287</a></span><span class="preprocessor">#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk </span></div>
|
||
<div class="line"><a id="l03288" name="l03288"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga092e685d17984f38bb1a88432ffc54ee"> 3288</a></span><span class="preprocessor">#define CAN_F5R1_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l03289" name="l03289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6533312fc17838e6d13acb30b3920cb6"> 3289</a></span><span class="preprocessor">#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l03290" name="l03290"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87543e5b7c48580ca9925402ab6ca5a7"> 3290</a></span><span class="preprocessor">#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk </span></div>
|
||
<div class="line"><a id="l03291" name="l03291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac82d98dee909d969dc96f564795027e2"> 3291</a></span><span class="preprocessor">#define CAN_F5R1_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l03292" name="l03292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6f582e0d54bfd7467f6feed9834672a"> 3292</a></span><span class="preprocessor">#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l03293" name="l03293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b9c39ec4649cd68a540c88c3c64d506"> 3293</a></span><span class="preprocessor">#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk </span></div>
|
||
<div class="line"><a id="l03294" name="l03294"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52662c9e857187de4de1d65d6951bc7a"> 3294</a></span><span class="preprocessor">#define CAN_F5R1_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l03295" name="l03295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga241cc69a215db80ad1e1028462f05400"> 3295</a></span><span class="preprocessor">#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l03296" name="l03296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4992301536d388de215273769708b843"> 3296</a></span><span class="preprocessor">#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk </span></div>
|
||
<div class="line"><a id="l03297" name="l03297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c0a5a14d7c4b76f8e6682dd9ef5956f"> 3297</a></span><span class="preprocessor">#define CAN_F5R1_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l03298" name="l03298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ce1dc2e2a4b715e83aeee7419bb9640"> 3298</a></span><span class="preprocessor">#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l03299" name="l03299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab21c0b793d7aff03497a95d5c6528ab2"> 3299</a></span><span class="preprocessor">#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk </span></div>
|
||
<div class="line"><a id="l03300" name="l03300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab743a0f6dd5ac3c4bac9a036b29081ef"> 3300</a></span><span class="preprocessor">#define CAN_F5R1_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l03301" name="l03301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0c7bd885ecb532509cd74d87eef62dc"> 3301</a></span><span class="preprocessor">#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l03302" name="l03302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1c4c5d06a9da5f853aaede3470b07f4"> 3302</a></span><span class="preprocessor">#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk </span></div>
|
||
<div class="line"><a id="l03303" name="l03303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe48131ff33f7f9fbc7714c3d8c7bfeb"> 3303</a></span><span class="preprocessor">#define CAN_F5R1_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l03304" name="l03304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga481485aaa4f39fcdbc5e687452e08cab"> 3304</a></span><span class="preprocessor">#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l03305" name="l03305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91214f1f7dbb4b75b0c425624640fd76"> 3305</a></span><span class="preprocessor">#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk </span></div>
|
||
<div class="line"><a id="l03306" name="l03306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa43bab79ebaba0ef928bdd3a1e63402e"> 3306</a></span><span class="preprocessor">#define CAN_F5R1_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l03307" name="l03307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4629b22e7deeac3e00278086311c7494"> 3307</a></span><span class="preprocessor">#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l03308" name="l03308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b24151a68c59fe0f3aa15e498fdc739"> 3308</a></span><span class="preprocessor">#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk </span></div>
|
||
<div class="line"><a id="l03309" name="l03309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga805d068ed5f42588a3cd264fdeaed117"> 3309</a></span><span class="preprocessor">#define CAN_F5R1_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l03310" name="l03310"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a285e060706ab40c834d30f23584f21"> 3310</a></span><span class="preprocessor">#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l03311" name="l03311"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadea89ef2e5c3dafae174b671c8e083d2"> 3311</a></span><span class="preprocessor">#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk </span></div>
|
||
<div class="line"><a id="l03312" name="l03312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11e981a2d5ffc5c12b41ee861e7bf776"> 3312</a></span><span class="preprocessor">#define CAN_F5R1_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l03313" name="l03313"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafb36d512d79bbf393fd07152d0128b3"> 3313</a></span><span class="preprocessor">#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l03314" name="l03314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2acccf9ab5708116cd888f2d65da54cc"> 3314</a></span><span class="preprocessor">#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk </span></div>
|
||
<div class="line"><a id="l03315" name="l03315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37c511b19288ec9ba0732c9aff018656"> 3315</a></span><span class="preprocessor">#define CAN_F5R1_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l03316" name="l03316"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad908c2a3a6d777350aa5a7c926523d4"> 3316</a></span><span class="preprocessor">#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l03317" name="l03317"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c0b9425117a2409b61032a9c746c2b5"> 3317</a></span><span class="preprocessor">#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk </span></div>
|
||
<div class="line"><a id="l03318" name="l03318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac24657fe7c1ff00ab6b3a5750ba99bd7"> 3318</a></span><span class="preprocessor">#define CAN_F5R1_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l03319" name="l03319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9d0db33c0e7a81c01f442cd914348b7"> 3319</a></span><span class="preprocessor">#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l03320" name="l03320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a0d31d96e75ea32299e78845f584632"> 3320</a></span><span class="preprocessor">#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk </span></div>
|
||
<div class="line"><a id="l03321" name="l03321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga840bed18d4fe71ed9e31e9df74daa351"> 3321</a></span><span class="preprocessor">#define CAN_F5R1_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l03322" name="l03322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffa42eeb73609e01712771d123cf5d9b"> 3322</a></span><span class="preprocessor">#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l03323" name="l03323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade5db4ad8b19580b895356fff66bb6be"> 3323</a></span><span class="preprocessor">#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk </span></div>
|
||
<div class="line"><a id="l03324" name="l03324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47b688950a4a528471aa72a2fb4ee35b"> 3324</a></span><span class="preprocessor">#define CAN_F5R1_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l03325" name="l03325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa88a15489fa10cf7d251f7faa5955ba5"> 3325</a></span><span class="preprocessor">#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l03326" name="l03326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4acec834c3eaf55af5e745d6988ddc1e"> 3326</a></span><span class="preprocessor">#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk </span></div>
|
||
<div class="line"><a id="l03327" name="l03327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd871efe11f26d251caa7bd258791e5b"> 3327</a></span><span class="preprocessor">#define CAN_F5R1_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l03328" name="l03328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c619cf4d0662ee07d2621300d0a22e0"> 3328</a></span><span class="preprocessor">#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l03329" name="l03329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga923a0086ada8e09a9202338b588f27d1"> 3329</a></span><span class="preprocessor">#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk </span></div>
|
||
<div class="line"><a id="l03330" name="l03330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9f1a63c02db020d08a6337a5c35c72c"> 3330</a></span><span class="preprocessor">#define CAN_F5R1_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l03331" name="l03331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad45b2c10d0637cb1279cfdaccd186e11"> 3331</a></span><span class="preprocessor">#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l03332" name="l03332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga840d2b3f751753e9d21b2e23506e6995"> 3332</a></span><span class="preprocessor">#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk </span></div>
|
||
<div class="line"><a id="l03333" name="l03333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83ac5fc7a98ea52047846b17abbf45f6"> 3333</a></span><span class="preprocessor">#define CAN_F5R1_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l03334" name="l03334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cca1e8863cc27c3c8afb9d7cee55fe5"> 3334</a></span><span class="preprocessor">#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l03335" name="l03335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8d28066798958e5730a95353690bcd0"> 3335</a></span><span class="preprocessor">#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk </span></div>
|
||
<div class="line"><a id="l03337" name="l03337"></a><span class="lineno"> 3337</span><span class="comment">/******************* Bit definition for CAN_F6R1 register *******************/</span></div>
|
||
<div class="line"><a id="l03338" name="l03338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a05745a737f85b835db1099ff6e7263"> 3338</a></span><span class="preprocessor">#define CAN_F6R1_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l03339" name="l03339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8aaf448c354a5a325c540df29f7af6ad"> 3339</a></span><span class="preprocessor">#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l03340" name="l03340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb57fe42259bd37deffe11eded640c76"> 3340</a></span><span class="preprocessor">#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk </span></div>
|
||
<div class="line"><a id="l03341" name="l03341"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc9c5707374ef1577ec2a5c7dec11322"> 3341</a></span><span class="preprocessor">#define CAN_F6R1_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l03342" name="l03342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3154b0f8cb4e1e230e37da1e696659f"> 3342</a></span><span class="preprocessor">#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l03343" name="l03343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1de288e28d5547106645ecc5b0c47f2a"> 3343</a></span><span class="preprocessor">#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk </span></div>
|
||
<div class="line"><a id="l03344" name="l03344"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7015e00f7ebf7b7727c89dd1e4d39aa6"> 3344</a></span><span class="preprocessor">#define CAN_F6R1_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l03345" name="l03345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c19eddf607d2cf5941d3b6807ff89cd"> 3345</a></span><span class="preprocessor">#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l03346" name="l03346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa8662caaa28aee37b2689f55400b75c"> 3346</a></span><span class="preprocessor">#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk </span></div>
|
||
<div class="line"><a id="l03347" name="l03347"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac97c920c1437c8ac5df50b171f4aee5f"> 3347</a></span><span class="preprocessor">#define CAN_F6R1_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l03348" name="l03348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec1656844d8617834262a5b6e24936bd"> 3348</a></span><span class="preprocessor">#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l03349" name="l03349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4ccedde67989fcbaa84cae9cae4b1eb"> 3349</a></span><span class="preprocessor">#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk </span></div>
|
||
<div class="line"><a id="l03350" name="l03350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d7ff307582eac29ccb7608880ff227d"> 3350</a></span><span class="preprocessor">#define CAN_F6R1_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l03351" name="l03351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53a812ea22c8f0cfb484edc70dd19d6b"> 3351</a></span><span class="preprocessor">#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l03352" name="l03352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45b063b3c14fd27bd63c03f878ac6cfc"> 3352</a></span><span class="preprocessor">#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk </span></div>
|
||
<div class="line"><a id="l03353" name="l03353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf3202c6c2ba274ba1a5920c47b2141d"> 3353</a></span><span class="preprocessor">#define CAN_F6R1_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l03354" name="l03354"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9afe1da36ff17919dc17466458f924a2"> 3354</a></span><span class="preprocessor">#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l03355" name="l03355"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32f8566fab72dec6d52ad7262e67cbcc"> 3355</a></span><span class="preprocessor">#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk </span></div>
|
||
<div class="line"><a id="l03356" name="l03356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43e24b0fe81f24078bdd007cbe832c07"> 3356</a></span><span class="preprocessor">#define CAN_F6R1_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l03357" name="l03357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd31d2b1806cf454d51d956eb339d096"> 3357</a></span><span class="preprocessor">#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l03358" name="l03358"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8636ecdacc3ca05d69e66737b7f2e7cf"> 3358</a></span><span class="preprocessor">#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk </span></div>
|
||
<div class="line"><a id="l03359" name="l03359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2438dd17101c15d44b533cf1904f2fc"> 3359</a></span><span class="preprocessor">#define CAN_F6R1_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l03360" name="l03360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87b36413ac64900c2398a530bbe647a6"> 3360</a></span><span class="preprocessor">#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l03361" name="l03361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb555ddab4853625c9b48b24e88d0dd8"> 3361</a></span><span class="preprocessor">#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk </span></div>
|
||
<div class="line"><a id="l03362" name="l03362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32fdb53fc39d6a2e09fcbbafb6d2ec81"> 3362</a></span><span class="preprocessor">#define CAN_F6R1_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l03363" name="l03363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45055999ce3c93c3f0e13f6a5fa1da30"> 3363</a></span><span class="preprocessor">#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l03364" name="l03364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1e7ca2d014d77152ff0e6bbb8d5fb63"> 3364</a></span><span class="preprocessor">#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk </span></div>
|
||
<div class="line"><a id="l03365" name="l03365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadad128a04f722f5190105f598e2b6ac8"> 3365</a></span><span class="preprocessor">#define CAN_F6R1_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l03366" name="l03366"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1904252fa35eca764e319ae3d124caa"> 3366</a></span><span class="preprocessor">#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l03367" name="l03367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe4dc5e57c209eb4d3c5ed94b3a2e897"> 3367</a></span><span class="preprocessor">#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk </span></div>
|
||
<div class="line"><a id="l03368" name="l03368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19bca6dcb49673694c6ac968da048d79"> 3368</a></span><span class="preprocessor">#define CAN_F6R1_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l03369" name="l03369"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a103dac7595c91ff96149735c5ce964"> 3369</a></span><span class="preprocessor">#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l03370" name="l03370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa63ca9ec114f553d68e0b0d38ae57ff0"> 3370</a></span><span class="preprocessor">#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk </span></div>
|
||
<div class="line"><a id="l03371" name="l03371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf750a53eaea8fac3215da663a4d1fbd7"> 3371</a></span><span class="preprocessor">#define CAN_F6R1_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l03372" name="l03372"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf418fcb1f3c27715523268e65cacab77"> 3372</a></span><span class="preprocessor">#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l03373" name="l03373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf3394a2675a7cb30556a40cc5b77c08"> 3373</a></span><span class="preprocessor">#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk </span></div>
|
||
<div class="line"><a id="l03374" name="l03374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fe4fd95f7cac5eda54ed4260e350d8e"> 3374</a></span><span class="preprocessor">#define CAN_F6R1_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l03375" name="l03375"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf975da091767c6f1106d725426874602"> 3375</a></span><span class="preprocessor">#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l03376" name="l03376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9c9c04edb492e48619de926196ab695"> 3376</a></span><span class="preprocessor">#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk </span></div>
|
||
<div class="line"><a id="l03377" name="l03377"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0854e19abe416754a29c04869c5dd57b"> 3377</a></span><span class="preprocessor">#define CAN_F6R1_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l03378" name="l03378"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf024ad0a5286c193a57e761ae8dd78ab"> 3378</a></span><span class="preprocessor">#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l03379" name="l03379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga070e91897e07ae11a9d2f60ff31e196a"> 3379</a></span><span class="preprocessor">#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk </span></div>
|
||
<div class="line"><a id="l03380" name="l03380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06cb4f011cdc5345ffd410b209ae38ef"> 3380</a></span><span class="preprocessor">#define CAN_F6R1_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l03381" name="l03381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2dcc33648e9130b7b12dd082032e1e02"> 3381</a></span><span class="preprocessor">#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l03382" name="l03382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3479321a85f1f55e24a1b56d13226a22"> 3382</a></span><span class="preprocessor">#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk </span></div>
|
||
<div class="line"><a id="l03383" name="l03383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a55b3fc85269d073d5cda9c98e2e1ef"> 3383</a></span><span class="preprocessor">#define CAN_F6R1_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l03384" name="l03384"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad577265745548ad4066ee66d7db968f5"> 3384</a></span><span class="preprocessor">#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l03385" name="l03385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a998a2b37fde5207b286a58c115a9e8"> 3385</a></span><span class="preprocessor">#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk </span></div>
|
||
<div class="line"><a id="l03386" name="l03386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d3df4af8b5925814763b952a9c6f328"> 3386</a></span><span class="preprocessor">#define CAN_F6R1_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l03387" name="l03387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba4c35e9c340e717ba471e6913120bac"> 3387</a></span><span class="preprocessor">#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l03388" name="l03388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga891ad3d341cee397d49fc982c509f7d5"> 3388</a></span><span class="preprocessor">#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk </span></div>
|
||
<div class="line"><a id="l03389" name="l03389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96c2447a18f72f6dd8d73e51d72ca71f"> 3389</a></span><span class="preprocessor">#define CAN_F6R1_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l03390" name="l03390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b71b0660dd705a9ebe22c2e768e4172"> 3390</a></span><span class="preprocessor">#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l03391" name="l03391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4a70606f1b07a6bbb5ae4fe8ad374e5"> 3391</a></span><span class="preprocessor">#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk </span></div>
|
||
<div class="line"><a id="l03392" name="l03392"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3aa83c6161527cef489d960584af040"> 3392</a></span><span class="preprocessor">#define CAN_F6R1_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l03393" name="l03393"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42fa5a606d58f2a30da9a58581178127"> 3393</a></span><span class="preprocessor">#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l03394" name="l03394"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1542ea54030e3052c8991b249cd0e504"> 3394</a></span><span class="preprocessor">#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk </span></div>
|
||
<div class="line"><a id="l03395" name="l03395"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6a4e2993cf15d28b3ff030793d110a6"> 3395</a></span><span class="preprocessor">#define CAN_F6R1_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l03396" name="l03396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga433c7e51a79cc95f7aa5593c5d347dfc"> 3396</a></span><span class="preprocessor">#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l03397" name="l03397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e1a7c680bcfc57c6cc521cbaa0749d6"> 3397</a></span><span class="preprocessor">#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk </span></div>
|
||
<div class="line"><a id="l03398" name="l03398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9841eeaf6951092200c67ee2e1d8959d"> 3398</a></span><span class="preprocessor">#define CAN_F6R1_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l03399" name="l03399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b843a11577d4891e11238810c01ccea"> 3399</a></span><span class="preprocessor">#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l03400" name="l03400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fba31d938ab3492c8855c26bebfbef2"> 3400</a></span><span class="preprocessor">#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk </span></div>
|
||
<div class="line"><a id="l03401" name="l03401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef6fa85c2d4ef60e08f9cc04e5531c48"> 3401</a></span><span class="preprocessor">#define CAN_F6R1_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l03402" name="l03402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab49834ceca6245c6bed6b011c37cb51c"> 3402</a></span><span class="preprocessor">#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l03403" name="l03403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga556f3b08cee839e038109e604e5bba4c"> 3403</a></span><span class="preprocessor">#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk </span></div>
|
||
<div class="line"><a id="l03404" name="l03404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7fbd8ee1cf6970c9065f5afa0a7f3d8"> 3404</a></span><span class="preprocessor">#define CAN_F6R1_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l03405" name="l03405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbd32cd4a51845ae3257bec44dea5f36"> 3405</a></span><span class="preprocessor">#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l03406" name="l03406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdc41162219ed6f5be1b5ae7ba328754"> 3406</a></span><span class="preprocessor">#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk </span></div>
|
||
<div class="line"><a id="l03407" name="l03407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa12596b4ab04f15a4de2a08772365def"> 3407</a></span><span class="preprocessor">#define CAN_F6R1_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l03408" name="l03408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga601aa03929a9eed61e4191a049c75fb8"> 3408</a></span><span class="preprocessor">#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l03409" name="l03409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89f4fd5c28d2fd7475081b39b2b358c6"> 3409</a></span><span class="preprocessor">#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk </span></div>
|
||
<div class="line"><a id="l03410" name="l03410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfa75de907e614398eb71f98ebcd4f9e"> 3410</a></span><span class="preprocessor">#define CAN_F6R1_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l03411" name="l03411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2707b11422d80fcc55e5759c7d7a3983"> 3411</a></span><span class="preprocessor">#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l03412" name="l03412"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5eb9d0f3cad0eeea398f2ba5fd83cf2"> 3412</a></span><span class="preprocessor">#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk </span></div>
|
||
<div class="line"><a id="l03413" name="l03413"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafc2b7e2fbf01700501b1d5fb0ed54d6"> 3413</a></span><span class="preprocessor">#define CAN_F6R1_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l03414" name="l03414"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50ed60d8e8930a207039da6873a403b4"> 3414</a></span><span class="preprocessor">#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l03415" name="l03415"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3fa46e9d1fafcb3eb1189d6d43692cd"> 3415</a></span><span class="preprocessor">#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk </span></div>
|
||
<div class="line"><a id="l03416" name="l03416"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63a7a5394639689f077cd23a1bc2a2c3"> 3416</a></span><span class="preprocessor">#define CAN_F6R1_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l03417" name="l03417"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2202fe7314b833d290f25a0e5234169"> 3417</a></span><span class="preprocessor">#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l03418" name="l03418"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9168b4d12ddb654b397ce3ffb66af4c"> 3418</a></span><span class="preprocessor">#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk </span></div>
|
||
<div class="line"><a id="l03419" name="l03419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga193993f46c36ffb52f560dd38e2f2b14"> 3419</a></span><span class="preprocessor">#define CAN_F6R1_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l03420" name="l03420"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45b34d58ea8416ea9ccdadd87259d810"> 3420</a></span><span class="preprocessor">#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l03421" name="l03421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga610fdf301fb1cff5af38f83b4e0c81b1"> 3421</a></span><span class="preprocessor">#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk </span></div>
|
||
<div class="line"><a id="l03422" name="l03422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2064cf4f9bff8a3880b2b3f80225de4f"> 3422</a></span><span class="preprocessor">#define CAN_F6R1_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l03423" name="l03423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab87f159252e6a934b1ecfb6082d8ac50"> 3423</a></span><span class="preprocessor">#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l03424" name="l03424"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a3e033aae51ff31b75fb801599232f5"> 3424</a></span><span class="preprocessor">#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk </span></div>
|
||
<div class="line"><a id="l03425" name="l03425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b8ac47a8b593b2d941f2df07adc8f65"> 3425</a></span><span class="preprocessor">#define CAN_F6R1_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l03426" name="l03426"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87baee8a9cefd8158caf141f29881051"> 3426</a></span><span class="preprocessor">#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l03427" name="l03427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga868ae6fc3bbe273b44d250791a80df58"> 3427</a></span><span class="preprocessor">#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk </span></div>
|
||
<div class="line"><a id="l03428" name="l03428"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga208a9734e163cf973b02b3e7a8d9271a"> 3428</a></span><span class="preprocessor">#define CAN_F6R1_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l03429" name="l03429"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdec0e767a520aa7bcffac3e5652181b"> 3429</a></span><span class="preprocessor">#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l03430" name="l03430"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe08696e215f9e8f1605e60e4817dd8b"> 3430</a></span><span class="preprocessor">#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk </span></div>
|
||
<div class="line"><a id="l03431" name="l03431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76a4f2683f6acc00c48fadadcc75f877"> 3431</a></span><span class="preprocessor">#define CAN_F6R1_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l03432" name="l03432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f2f09b2ada8e9ea6e28a7abe6dfd678"> 3432</a></span><span class="preprocessor">#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l03433" name="l03433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69b2dffd9969ff8658b45a7a2bb1c5ee"> 3433</a></span><span class="preprocessor">#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk </span></div>
|
||
<div class="line"><a id="l03435" name="l03435"></a><span class="lineno"> 3435</span><span class="comment">/******************* Bit definition for CAN_F7R1 register *******************/</span></div>
|
||
<div class="line"><a id="l03436" name="l03436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07592cc9f142c86800624b80ac659191"> 3436</a></span><span class="preprocessor">#define CAN_F7R1_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l03437" name="l03437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad19ad30a6bd063074a8e787ce24f7d3f"> 3437</a></span><span class="preprocessor">#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l03438" name="l03438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2217bcc5b82de25751d3984884b0e0c1"> 3438</a></span><span class="preprocessor">#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk </span></div>
|
||
<div class="line"><a id="l03439" name="l03439"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab323a7481c5d75df36e9e2b25c7e6e32"> 3439</a></span><span class="preprocessor">#define CAN_F7R1_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l03440" name="l03440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab83bdd3955b202a00602bff176ab3cd8"> 3440</a></span><span class="preprocessor">#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l03441" name="l03441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf71cbdd5cbe109fde119adb86d64f0a7"> 3441</a></span><span class="preprocessor">#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk </span></div>
|
||
<div class="line"><a id="l03442" name="l03442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b06796d92491cd5111bad5c6c380190"> 3442</a></span><span class="preprocessor">#define CAN_F7R1_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l03443" name="l03443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffbf82ffead59ec0190dec25b9c8c621"> 3443</a></span><span class="preprocessor">#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l03444" name="l03444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0a7a004058a6b10b5cb3374eb82dd1d"> 3444</a></span><span class="preprocessor">#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk </span></div>
|
||
<div class="line"><a id="l03445" name="l03445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga548972b3e8900613c72d584ac0550d81"> 3445</a></span><span class="preprocessor">#define CAN_F7R1_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l03446" name="l03446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab477aa17c626cac52ef965f21579dc69"> 3446</a></span><span class="preprocessor">#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l03447" name="l03447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2224329373b490c8dd4f0c148ef58997"> 3447</a></span><span class="preprocessor">#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk </span></div>
|
||
<div class="line"><a id="l03448" name="l03448"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga428d061d3d6cd26401f09a0a9d888582"> 3448</a></span><span class="preprocessor">#define CAN_F7R1_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l03449" name="l03449"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e6552b734a4618cff826b853d8e5ac7"> 3449</a></span><span class="preprocessor">#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l03450" name="l03450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3574ea4882319ac08e0df065bdd3566"> 3450</a></span><span class="preprocessor">#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk </span></div>
|
||
<div class="line"><a id="l03451" name="l03451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51f21f5d42dc175f69e397d8a021ec17"> 3451</a></span><span class="preprocessor">#define CAN_F7R1_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l03452" name="l03452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4b90d78121983740c8d803352b68cef"> 3452</a></span><span class="preprocessor">#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l03453" name="l03453"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76f63e712a9a57dacab2874dd695254d"> 3453</a></span><span class="preprocessor">#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk </span></div>
|
||
<div class="line"><a id="l03454" name="l03454"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafaf5d52b07d0fb670d7b754f293193b2"> 3454</a></span><span class="preprocessor">#define CAN_F7R1_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l03455" name="l03455"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e3a549c7bf229dda892b600b320b4e0"> 3455</a></span><span class="preprocessor">#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l03456" name="l03456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22d969f17f8a25a63cb056ee2cb622d3"> 3456</a></span><span class="preprocessor">#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk </span></div>
|
||
<div class="line"><a id="l03457" name="l03457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85318a4750085acc0f67eaf5d748f0b0"> 3457</a></span><span class="preprocessor">#define CAN_F7R1_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l03458" name="l03458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb8ad36251e272dd1487dfec8f4b6cfd"> 3458</a></span><span class="preprocessor">#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l03459" name="l03459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae89ec51b51c83c108880e361caf17ac"> 3459</a></span><span class="preprocessor">#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk </span></div>
|
||
<div class="line"><a id="l03460" name="l03460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3977b859e97377959d730d66dba4cea"> 3460</a></span><span class="preprocessor">#define CAN_F7R1_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l03461" name="l03461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2be453e8e7320b77bc242044038ab02"> 3461</a></span><span class="preprocessor">#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l03462" name="l03462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67fca99c67cab6713605e14d96a9df62"> 3462</a></span><span class="preprocessor">#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk </span></div>
|
||
<div class="line"><a id="l03463" name="l03463"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8aaaf940b9f64ff8cf14a1ccb1f01353"> 3463</a></span><span class="preprocessor">#define CAN_F7R1_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l03464" name="l03464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga271c074cc3a12f895a531d0cfb29a883"> 3464</a></span><span class="preprocessor">#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l03465" name="l03465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacd1ef8f0870bc5a5422a6bedbb61d40"> 3465</a></span><span class="preprocessor">#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk </span></div>
|
||
<div class="line"><a id="l03466" name="l03466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e458cf6d5da73505414aa25098d9282"> 3466</a></span><span class="preprocessor">#define CAN_F7R1_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l03467" name="l03467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad708e8bc52c416ee38bc5bb93822a877"> 3467</a></span><span class="preprocessor">#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l03468" name="l03468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf56408d9914f566396d64609830e2d4f"> 3468</a></span><span class="preprocessor">#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk </span></div>
|
||
<div class="line"><a id="l03469" name="l03469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c05b416f990eebb80363c022661be43"> 3469</a></span><span class="preprocessor">#define CAN_F7R1_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l03470" name="l03470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8fa9afddd282899c92a7647e6f1eb8e"> 3470</a></span><span class="preprocessor">#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l03471" name="l03471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65947100832111c7fb427d1982f801eb"> 3471</a></span><span class="preprocessor">#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk </span></div>
|
||
<div class="line"><a id="l03472" name="l03472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae496f5c9c04aa8d161b380cfc46c1a89"> 3472</a></span><span class="preprocessor">#define CAN_F7R1_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l03473" name="l03473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad694f31ad366db83ec659c93fb75db7f"> 3473</a></span><span class="preprocessor">#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l03474" name="l03474"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga175ed9cdbbf756ec76b9c6fb1f69adff"> 3474</a></span><span class="preprocessor">#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk </span></div>
|
||
<div class="line"><a id="l03475" name="l03475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0706b04b0ddfa96c5ab1120d8973c8fd"> 3475</a></span><span class="preprocessor">#define CAN_F7R1_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l03476" name="l03476"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc73cd4c1973c6d575b12ef8a34aefdf"> 3476</a></span><span class="preprocessor">#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l03477" name="l03477"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91af48b8cd11f119d257311dcf2cc291"> 3477</a></span><span class="preprocessor">#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk </span></div>
|
||
<div class="line"><a id="l03478" name="l03478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace9cd9b7f8196e5831e7a68cc063eabb"> 3478</a></span><span class="preprocessor">#define CAN_F7R1_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l03479" name="l03479"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa51f245c33277eb5e09db8b8302e2df6"> 3479</a></span><span class="preprocessor">#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l03480" name="l03480"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7108bc449a6e328748dd8d2209b83753"> 3480</a></span><span class="preprocessor">#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk </span></div>
|
||
<div class="line"><a id="l03481" name="l03481"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a5c4ef28847f4fa0d27a781b0b8a986"> 3481</a></span><span class="preprocessor">#define CAN_F7R1_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l03482" name="l03482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3dd14c5855dfe51bc8a1a44266d1c925"> 3482</a></span><span class="preprocessor">#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l03483" name="l03483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc47acac1bb59603f58d9aef661d9334"> 3483</a></span><span class="preprocessor">#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk </span></div>
|
||
<div class="line"><a id="l03484" name="l03484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d07c069c5aca9e42f268ab32a062c75"> 3484</a></span><span class="preprocessor">#define CAN_F7R1_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l03485" name="l03485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc661e05b2422313bf88f39f049ce53e"> 3485</a></span><span class="preprocessor">#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l03486" name="l03486"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b07b4ebfaac9e60d6042b1bff98ec33"> 3486</a></span><span class="preprocessor">#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk </span></div>
|
||
<div class="line"><a id="l03487" name="l03487"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga648db438e1aef7f7b35396757e7c7b52"> 3487</a></span><span class="preprocessor">#define CAN_F7R1_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l03488" name="l03488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58a27e2e7fd333f0aba9fbd5919e260d"> 3488</a></span><span class="preprocessor">#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l03489" name="l03489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3328e95d8ae911adc0e5dd4128f8161"> 3489</a></span><span class="preprocessor">#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk </span></div>
|
||
<div class="line"><a id="l03490" name="l03490"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf56090225bc33669e07141a1243cec88"> 3490</a></span><span class="preprocessor">#define CAN_F7R1_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l03491" name="l03491"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga278e31f437817faa9cad12cc69e3112b"> 3491</a></span><span class="preprocessor">#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l03492" name="l03492"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga473e4917f35772cd08b06e166d6e475e"> 3492</a></span><span class="preprocessor">#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk </span></div>
|
||
<div class="line"><a id="l03493" name="l03493"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ab1b958322e9e8924570497657ef396"> 3493</a></span><span class="preprocessor">#define CAN_F7R1_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l03494" name="l03494"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1422787fd4beb2c5679f45908214fd6"> 3494</a></span><span class="preprocessor">#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l03495" name="l03495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf40a4dd0979fb7ffba4b4192fe6dde5f"> 3495</a></span><span class="preprocessor">#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk </span></div>
|
||
<div class="line"><a id="l03496" name="l03496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga638a9090ca2ae17ea3d000deca166de3"> 3496</a></span><span class="preprocessor">#define CAN_F7R1_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l03497" name="l03497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad71fb64ea19cf98ac384fed6babe5fdc"> 3497</a></span><span class="preprocessor">#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l03498" name="l03498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5854aa102655334a6242e43c0b25aede"> 3498</a></span><span class="preprocessor">#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk </span></div>
|
||
<div class="line"><a id="l03499" name="l03499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacf70e06346fa4c3754533c7743bd04f"> 3499</a></span><span class="preprocessor">#define CAN_F7R1_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l03500" name="l03500"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c1d29a629499734298ff81b9892cb0a"> 3500</a></span><span class="preprocessor">#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l03501" name="l03501"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga505dbdeaf89d103795046fb689b81664"> 3501</a></span><span class="preprocessor">#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk </span></div>
|
||
<div class="line"><a id="l03502" name="l03502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcea76ba56f67ee953e46d4a2730b36a"> 3502</a></span><span class="preprocessor">#define CAN_F7R1_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l03503" name="l03503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4535f6c9da894cc9ef7a6ba6f6bc6525"> 3503</a></span><span class="preprocessor">#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l03504" name="l03504"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga692f7a0bbc73be14e9d554394dceb176"> 3504</a></span><span class="preprocessor">#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk </span></div>
|
||
<div class="line"><a id="l03505" name="l03505"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4853c3d121f3c2d11833d11b395e0038"> 3505</a></span><span class="preprocessor">#define CAN_F7R1_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l03506" name="l03506"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14b9c180bade4dad957697b4f5b4354f"> 3506</a></span><span class="preprocessor">#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l03507" name="l03507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a93f243e7acf3f749f2b6ec8ae7bc5f"> 3507</a></span><span class="preprocessor">#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk </span></div>
|
||
<div class="line"><a id="l03508" name="l03508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c2567b1837c81aba2759686438547cc"> 3508</a></span><span class="preprocessor">#define CAN_F7R1_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l03509" name="l03509"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga347cad693a28b872fe402439c9548f35"> 3509</a></span><span class="preprocessor">#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l03510" name="l03510"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68815c969c231268a63c8809a55bc866"> 3510</a></span><span class="preprocessor">#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk </span></div>
|
||
<div class="line"><a id="l03511" name="l03511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5867f7e9cb965e6a3768f6bb02f080e"> 3511</a></span><span class="preprocessor">#define CAN_F7R1_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l03512" name="l03512"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2aefee2f7b7c851315fd09a2ef4df5ed"> 3512</a></span><span class="preprocessor">#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l03513" name="l03513"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7055881b4a6d9fe51e8dcfb99a546139"> 3513</a></span><span class="preprocessor">#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk </span></div>
|
||
<div class="line"><a id="l03514" name="l03514"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb741309bad1c9aef3ede7c187c05a92"> 3514</a></span><span class="preprocessor">#define CAN_F7R1_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l03515" name="l03515"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ae7335a105fc044215160bdafda2485"> 3515</a></span><span class="preprocessor">#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l03516" name="l03516"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19ab918d9499635e8199a143833c6fdb"> 3516</a></span><span class="preprocessor">#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk </span></div>
|
||
<div class="line"><a id="l03517" name="l03517"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadae02d56cf4acb7e92586c65c2da805d"> 3517</a></span><span class="preprocessor">#define CAN_F7R1_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l03518" name="l03518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1f9cbef574790752e5579402adbfcf9"> 3518</a></span><span class="preprocessor">#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l03519" name="l03519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8360f2a2ba21a1b2f361d4330026edfd"> 3519</a></span><span class="preprocessor">#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk </span></div>
|
||
<div class="line"><a id="l03520" name="l03520"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab06f238fd2c787b94e9022a874f0e4f7"> 3520</a></span><span class="preprocessor">#define CAN_F7R1_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l03521" name="l03521"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5accb398c1b8d49f33264729b9248ba"> 3521</a></span><span class="preprocessor">#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l03522" name="l03522"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga681e922052442801310265bab7356fc4"> 3522</a></span><span class="preprocessor">#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk </span></div>
|
||
<div class="line"><a id="l03523" name="l03523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec347619871661fb58366eb358f0d3c8"> 3523</a></span><span class="preprocessor">#define CAN_F7R1_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l03524" name="l03524"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed2a0882ce4432f84db55f3f699cbd93"> 3524</a></span><span class="preprocessor">#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l03525" name="l03525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab12aa3a716a85bf96a1496ecaeae0cec"> 3525</a></span><span class="preprocessor">#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk </span></div>
|
||
<div class="line"><a id="l03526" name="l03526"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga920c885a992444b856bc4df2862f44ae"> 3526</a></span><span class="preprocessor">#define CAN_F7R1_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l03527" name="l03527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63bedd413e3ab8e91f9d779ef40e45b5"> 3527</a></span><span class="preprocessor">#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l03528" name="l03528"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6774583920f7cd42976daa4cf389eff3"> 3528</a></span><span class="preprocessor">#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk </span></div>
|
||
<div class="line"><a id="l03529" name="l03529"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga099ccfbf473ed4897db9b4d16ac3c150"> 3529</a></span><span class="preprocessor">#define CAN_F7R1_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l03530" name="l03530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa85d8f6af8cfade40eaef271291512ef"> 3530</a></span><span class="preprocessor">#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l03531" name="l03531"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9990b9fd20bbe0ff114acace0cb47ad7"> 3531</a></span><span class="preprocessor">#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk </span></div>
|
||
<div class="line"><a id="l03533" name="l03533"></a><span class="lineno"> 3533</span><span class="comment">/******************* Bit definition for CAN_F8R1 register *******************/</span></div>
|
||
<div class="line"><a id="l03534" name="l03534"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e21006790f44d0394235edb9533fe9f"> 3534</a></span><span class="preprocessor">#define CAN_F8R1_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l03535" name="l03535"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43a1537e2aeed84464aed2c398cb24c5"> 3535</a></span><span class="preprocessor">#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l03536" name="l03536"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13cd870005a4712c3a8b9675a962c642"> 3536</a></span><span class="preprocessor">#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk </span></div>
|
||
<div class="line"><a id="l03537" name="l03537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab537c0b3bf184ffb31d73312facd8d44"> 3537</a></span><span class="preprocessor">#define CAN_F8R1_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l03538" name="l03538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga136ab0937c4919934d7dc1185d3c4064"> 3538</a></span><span class="preprocessor">#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l03539" name="l03539"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49082d55960382ded8b2f7235dd3b33d"> 3539</a></span><span class="preprocessor">#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk </span></div>
|
||
<div class="line"><a id="l03540" name="l03540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d30a98a695d270dbff8e07b9079e5d8"> 3540</a></span><span class="preprocessor">#define CAN_F8R1_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l03541" name="l03541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9fac3bd96ed91e471081a51b6b08ca3"> 3541</a></span><span class="preprocessor">#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l03542" name="l03542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdb99f376b40d3933ce6a28ad31f496a"> 3542</a></span><span class="preprocessor">#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk </span></div>
|
||
<div class="line"><a id="l03543" name="l03543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1894d0455f9488198430c70db97c865"> 3543</a></span><span class="preprocessor">#define CAN_F8R1_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l03544" name="l03544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5b9c8ec036840da8f0b04aaa715d031"> 3544</a></span><span class="preprocessor">#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l03545" name="l03545"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cd97fc37fa6ffadbb7af4f9ddf1d014"> 3545</a></span><span class="preprocessor">#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk </span></div>
|
||
<div class="line"><a id="l03546" name="l03546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a0ded25fe64917e6868d95b1d468771"> 3546</a></span><span class="preprocessor">#define CAN_F8R1_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l03547" name="l03547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9829df8a13336ccf61d59be6c282d52"> 3547</a></span><span class="preprocessor">#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l03548" name="l03548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5842614b55172086992fc085955168d7"> 3548</a></span><span class="preprocessor">#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk </span></div>
|
||
<div class="line"><a id="l03549" name="l03549"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5792df4298b71222586c057d8c783ed2"> 3549</a></span><span class="preprocessor">#define CAN_F8R1_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l03550" name="l03550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70d67631dbfe1a1f15fb712df7cca4d8"> 3550</a></span><span class="preprocessor">#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l03551" name="l03551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga373c77cab88912e816a6e12195bd3205"> 3551</a></span><span class="preprocessor">#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk </span></div>
|
||
<div class="line"><a id="l03552" name="l03552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28d2bdc498bb762e71c06682ddcffcd0"> 3552</a></span><span class="preprocessor">#define CAN_F8R1_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l03553" name="l03553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1d9da45066db64dcc7b6d6ea9d8d3f8"> 3553</a></span><span class="preprocessor">#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l03554" name="l03554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5937607627dd44c4fb79f9063534e2b1"> 3554</a></span><span class="preprocessor">#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk </span></div>
|
||
<div class="line"><a id="l03555" name="l03555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40a3d24b2ddf64251f6257500549eb78"> 3555</a></span><span class="preprocessor">#define CAN_F8R1_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l03556" name="l03556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14a2fe60539e333588226dbc4de4fffa"> 3556</a></span><span class="preprocessor">#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l03557" name="l03557"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b6765194a47f1a6d7dfbf78e0b4139c"> 3557</a></span><span class="preprocessor">#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk </span></div>
|
||
<div class="line"><a id="l03558" name="l03558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc32c5836d51b1c7aa00509af2f84335"> 3558</a></span><span class="preprocessor">#define CAN_F8R1_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l03559" name="l03559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f57e77aa8ea032bc07463d82e451e1b"> 3559</a></span><span class="preprocessor">#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l03560" name="l03560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa79159b413994d12b593cc4f1b23d1fa"> 3560</a></span><span class="preprocessor">#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk </span></div>
|
||
<div class="line"><a id="l03561" name="l03561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33e709811995d99e00d150e9bc96fa27"> 3561</a></span><span class="preprocessor">#define CAN_F8R1_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l03562" name="l03562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab30a05da2419398ee1eb3cc0d0c468f3"> 3562</a></span><span class="preprocessor">#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l03563" name="l03563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b959e903cdac33f5da71aa5c7477a0d"> 3563</a></span><span class="preprocessor">#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk </span></div>
|
||
<div class="line"><a id="l03564" name="l03564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9d988713272210141906dbbf7c86e9a"> 3564</a></span><span class="preprocessor">#define CAN_F8R1_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l03565" name="l03565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga250ae96856872467bd01177a14cbd757"> 3565</a></span><span class="preprocessor">#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l03566" name="l03566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5de7f304ca7bfcb9e78c9c2d346d300"> 3566</a></span><span class="preprocessor">#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk </span></div>
|
||
<div class="line"><a id="l03567" name="l03567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b1a8d858999311a306e931621b57f21"> 3567</a></span><span class="preprocessor">#define CAN_F8R1_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l03568" name="l03568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f936dea8e23ad47f01a690e3144442c"> 3568</a></span><span class="preprocessor">#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l03569" name="l03569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d5a19fa7032ef2b68e2feebd0db15e6"> 3569</a></span><span class="preprocessor">#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk </span></div>
|
||
<div class="line"><a id="l03570" name="l03570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6dee94be5857587a290a91b8e69ebd75"> 3570</a></span><span class="preprocessor">#define CAN_F8R1_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l03571" name="l03571"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad340588e0f2e4424892bf86a3df02297"> 3571</a></span><span class="preprocessor">#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l03572" name="l03572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga943a685663474ed7aa509eaccbda2ffb"> 3572</a></span><span class="preprocessor">#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk </span></div>
|
||
<div class="line"><a id="l03573" name="l03573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa36fb31c4e4460571555e84cb306cf0"> 3573</a></span><span class="preprocessor">#define CAN_F8R1_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l03574" name="l03574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38c0634095cd3178f8b2836d6855d3f3"> 3574</a></span><span class="preprocessor">#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l03575" name="l03575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga668cb8a75c4166b5287a09ba98c8ec70"> 3575</a></span><span class="preprocessor">#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk </span></div>
|
||
<div class="line"><a id="l03576" name="l03576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6c42fee1e932aebc586aa5cfa634be5"> 3576</a></span><span class="preprocessor">#define CAN_F8R1_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l03577" name="l03577"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac0c83e006384165f5d1cb982728cc50"> 3577</a></span><span class="preprocessor">#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l03578" name="l03578"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84727d6a0fdcb2870529d7a371a0b660"> 3578</a></span><span class="preprocessor">#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk </span></div>
|
||
<div class="line"><a id="l03579" name="l03579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b62ff2f6a779932be13dfa2eba51c8c"> 3579</a></span><span class="preprocessor">#define CAN_F8R1_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l03580" name="l03580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42f23b1489ef4904d4f0a629f4fff1da"> 3580</a></span><span class="preprocessor">#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l03581" name="l03581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9eb9c851eb03c49bc02f686aee490a28"> 3581</a></span><span class="preprocessor">#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk </span></div>
|
||
<div class="line"><a id="l03582" name="l03582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab6b2bfaa28bb99475c1ffe09c55bedb"> 3582</a></span><span class="preprocessor">#define CAN_F8R1_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l03583" name="l03583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98a05e0a87d907888aed8f07c72d00f9"> 3583</a></span><span class="preprocessor">#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l03584" name="l03584"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ccc46770c70da8546bbbcf492bcdd95"> 3584</a></span><span class="preprocessor">#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk </span></div>
|
||
<div class="line"><a id="l03585" name="l03585"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3e73d311df6235cbf5fc02a800628db"> 3585</a></span><span class="preprocessor">#define CAN_F8R1_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l03586" name="l03586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b5980d9a8107fa12b63f1ee0abe74cd"> 3586</a></span><span class="preprocessor">#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l03587" name="l03587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf24b0628e89b2c27cb9e13b0492876eb"> 3587</a></span><span class="preprocessor">#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk </span></div>
|
||
<div class="line"><a id="l03588" name="l03588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf59f6130156da5081b0eee3acb154374"> 3588</a></span><span class="preprocessor">#define CAN_F8R1_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l03589" name="l03589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae850211d9876f0063e13b5610cf8ac65"> 3589</a></span><span class="preprocessor">#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l03590" name="l03590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36b946c123c3c3f1cdbd1272db24c58b"> 3590</a></span><span class="preprocessor">#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk </span></div>
|
||
<div class="line"><a id="l03591" name="l03591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fe27087a9da8f3202a319dbaf07b6d6"> 3591</a></span><span class="preprocessor">#define CAN_F8R1_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l03592" name="l03592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga666296673c08dd22ca95dab553d430ef"> 3592</a></span><span class="preprocessor">#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l03593" name="l03593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab91129b8b7746111a31a968c1f1a8b19"> 3593</a></span><span class="preprocessor">#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk </span></div>
|
||
<div class="line"><a id="l03594" name="l03594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55046c532cef29a6df857a821d8d9750"> 3594</a></span><span class="preprocessor">#define CAN_F8R1_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l03595" name="l03595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82b241f62e465fede05a749af4f6d46d"> 3595</a></span><span class="preprocessor">#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l03596" name="l03596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19663b29868ae926896961451768d748"> 3596</a></span><span class="preprocessor">#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk </span></div>
|
||
<div class="line"><a id="l03597" name="l03597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef11cb2b0be6f8a07ca34699c89a7098"> 3597</a></span><span class="preprocessor">#define CAN_F8R1_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l03598" name="l03598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga894777fbc3a4cfc64d779ee1bb28447a"> 3598</a></span><span class="preprocessor">#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l03599" name="l03599"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19d8c89621a78de5177481d217bb5033"> 3599</a></span><span class="preprocessor">#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk </span></div>
|
||
<div class="line"><a id="l03600" name="l03600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44d6b1387dd6af3f5f6ad71dc57738bb"> 3600</a></span><span class="preprocessor">#define CAN_F8R1_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l03601" name="l03601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95a971879dd5369d39b1b5a2d55af7f2"> 3601</a></span><span class="preprocessor">#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l03602" name="l03602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab265fadfeb8674b869264ad25bedcac4"> 3602</a></span><span class="preprocessor">#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk </span></div>
|
||
<div class="line"><a id="l03603" name="l03603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga928556e1ce80afd85bc49deca2f1dc2a"> 3603</a></span><span class="preprocessor">#define CAN_F8R1_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l03604" name="l03604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c136499422980d6a619619b67024115"> 3604</a></span><span class="preprocessor">#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l03605" name="l03605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga102fdb92fecd6aa86e5dbd2fea2b2e79"> 3605</a></span><span class="preprocessor">#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk </span></div>
|
||
<div class="line"><a id="l03606" name="l03606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6287f1cbffc6c85b5a8c540bdd238dd1"> 3606</a></span><span class="preprocessor">#define CAN_F8R1_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l03607" name="l03607"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5cb63c9cc186f5a6a188e50e9440b71"> 3607</a></span><span class="preprocessor">#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l03608" name="l03608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b73f4ab4941e6d920e75f7197ed025b"> 3608</a></span><span class="preprocessor">#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk </span></div>
|
||
<div class="line"><a id="l03609" name="l03609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b42664c93972b8ceef0bb224465868a"> 3609</a></span><span class="preprocessor">#define CAN_F8R1_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l03610" name="l03610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad66fb66d8e41424f6a5df8645e889aed"> 3610</a></span><span class="preprocessor">#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l03611" name="l03611"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d72a1b4728fa13d4a2a3f7478f8398b"> 3611</a></span><span class="preprocessor">#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk </span></div>
|
||
<div class="line"><a id="l03612" name="l03612"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4046289146213969c12a1a9c88756853"> 3612</a></span><span class="preprocessor">#define CAN_F8R1_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l03613" name="l03613"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e4ac7b030b72119e7ff52cd7ed2c22b"> 3613</a></span><span class="preprocessor">#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l03614" name="l03614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5826d272442cf9b69336172a039bc439"> 3614</a></span><span class="preprocessor">#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk </span></div>
|
||
<div class="line"><a id="l03615" name="l03615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32f7d4b16bb82b31e2fb4879e64a7632"> 3615</a></span><span class="preprocessor">#define CAN_F8R1_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l03616" name="l03616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36df86343d04760bb4fef8b027e668d6"> 3616</a></span><span class="preprocessor">#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l03617" name="l03617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdb656881f89c0da122383403a816ce1"> 3617</a></span><span class="preprocessor">#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk </span></div>
|
||
<div class="line"><a id="l03618" name="l03618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d24f22e4e970b13528482d65e0bcd21"> 3618</a></span><span class="preprocessor">#define CAN_F8R1_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l03619" name="l03619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga647ae349a353febc85e2d06384798e35"> 3619</a></span><span class="preprocessor">#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l03620" name="l03620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d8c536aab73553ff1913ba806be351c"> 3620</a></span><span class="preprocessor">#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk </span></div>
|
||
<div class="line"><a id="l03621" name="l03621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga270dce4d4b698b43b0f9eed16a95b336"> 3621</a></span><span class="preprocessor">#define CAN_F8R1_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l03622" name="l03622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaddb3d32fc778601342a863d0a6612f5"> 3622</a></span><span class="preprocessor">#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l03623" name="l03623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fb8328cdbf23c9982b769bd39a24113"> 3623</a></span><span class="preprocessor">#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk </span></div>
|
||
<div class="line"><a id="l03624" name="l03624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ac7d47b043f02ea1fe15f4ed1ea69ea"> 3624</a></span><span class="preprocessor">#define CAN_F8R1_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l03625" name="l03625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8cfc8c264df5fef0511b3cd66e459c3"> 3625</a></span><span class="preprocessor">#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l03626" name="l03626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78861665c78657330f9fcfc17283529f"> 3626</a></span><span class="preprocessor">#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk </span></div>
|
||
<div class="line"><a id="l03627" name="l03627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85f280f7adb7d1b1f1a2fd964496d382"> 3627</a></span><span class="preprocessor">#define CAN_F8R1_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l03628" name="l03628"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf1306a969e63813c78f15304cfeef9d"> 3628</a></span><span class="preprocessor">#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l03629" name="l03629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b2fa38175302b2d91f2b45ae16c5db7"> 3629</a></span><span class="preprocessor">#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk </span></div>
|
||
<div class="line"><a id="l03631" name="l03631"></a><span class="lineno"> 3631</span><span class="comment">/******************* Bit definition for CAN_F9R1 register *******************/</span></div>
|
||
<div class="line"><a id="l03632" name="l03632"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e408d4dcf2104036587654b320ef837"> 3632</a></span><span class="preprocessor">#define CAN_F9R1_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l03633" name="l03633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedc0e0cbb432679fb469888559cd8ba0"> 3633</a></span><span class="preprocessor">#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l03634" name="l03634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga930a17d830cb9a95a79531dac2220785"> 3634</a></span><span class="preprocessor">#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk </span></div>
|
||
<div class="line"><a id="l03635" name="l03635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4b2c5ddbad8e4d30df6bae1553ae95f"> 3635</a></span><span class="preprocessor">#define CAN_F9R1_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l03636" name="l03636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga311d13b8b6763e76d9c889e49c7f5254"> 3636</a></span><span class="preprocessor">#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l03637" name="l03637"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8671eac978ebea75e6345adbcdf78026"> 3637</a></span><span class="preprocessor">#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk </span></div>
|
||
<div class="line"><a id="l03638" name="l03638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdac08de057f74084b0df1bdd49ffaa4"> 3638</a></span><span class="preprocessor">#define CAN_F9R1_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l03639" name="l03639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac66033af8f1d5f936090a464ef6af680"> 3639</a></span><span class="preprocessor">#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l03640" name="l03640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee3585fb5ee4081dffeb2a2dda1ce72f"> 3640</a></span><span class="preprocessor">#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk </span></div>
|
||
<div class="line"><a id="l03641" name="l03641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga693575c5b64ad798658952694e636204"> 3641</a></span><span class="preprocessor">#define CAN_F9R1_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l03642" name="l03642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bfd9933c0a4fb97ece209b9fcdfa794"> 3642</a></span><span class="preprocessor">#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l03643" name="l03643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga807e831fafa69e9df65618de855ea186"> 3643</a></span><span class="preprocessor">#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk </span></div>
|
||
<div class="line"><a id="l03644" name="l03644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga726f4f35552287c718dce9b5c46baba1"> 3644</a></span><span class="preprocessor">#define CAN_F9R1_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l03645" name="l03645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga362251d468d76c64459afc82f84acd06"> 3645</a></span><span class="preprocessor">#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l03646" name="l03646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddce646e28626a508b2f98c4f35148b3"> 3646</a></span><span class="preprocessor">#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk </span></div>
|
||
<div class="line"><a id="l03647" name="l03647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6064e11830367708fa478a64d6134471"> 3647</a></span><span class="preprocessor">#define CAN_F9R1_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l03648" name="l03648"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9af391a698294bbcfd73e13d7bc3d45f"> 3648</a></span><span class="preprocessor">#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l03649" name="l03649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ea72662e0243714ace5c0b48e7912f6"> 3649</a></span><span class="preprocessor">#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk </span></div>
|
||
<div class="line"><a id="l03650" name="l03650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa48d9cd13e58139129678537b2a46a54"> 3650</a></span><span class="preprocessor">#define CAN_F9R1_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l03651" name="l03651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf73980f9d3a6a660ab4b0742b849827"> 3651</a></span><span class="preprocessor">#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l03652" name="l03652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b08ddbc0bed91c6a1933e6485ded5e2"> 3652</a></span><span class="preprocessor">#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk </span></div>
|
||
<div class="line"><a id="l03653" name="l03653"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c12d5c48b26fa65b51d8978f372d235"> 3653</a></span><span class="preprocessor">#define CAN_F9R1_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l03654" name="l03654"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93cc25aaf5401c7a3e16cb4609ee0e07"> 3654</a></span><span class="preprocessor">#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l03655" name="l03655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae21fd9c8c790d4bc229c7ccb6d99dd36"> 3655</a></span><span class="preprocessor">#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk </span></div>
|
||
<div class="line"><a id="l03656" name="l03656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fce8e9c5098084f4b4e9fffe064627c"> 3656</a></span><span class="preprocessor">#define CAN_F9R1_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l03657" name="l03657"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba01d797a4d055fe0a1af549c3fb4734"> 3657</a></span><span class="preprocessor">#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l03658" name="l03658"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf1a8f02576caccfddc12f2ead734762"> 3658</a></span><span class="preprocessor">#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk </span></div>
|
||
<div class="line"><a id="l03659" name="l03659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f9d0da640c988023228da572b39189f"> 3659</a></span><span class="preprocessor">#define CAN_F9R1_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l03660" name="l03660"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2e7a7ac6a91de762e00f6ccbde5c982"> 3660</a></span><span class="preprocessor">#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l03661" name="l03661"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80a2594aaa275fd88225927e7115085b"> 3661</a></span><span class="preprocessor">#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk </span></div>
|
||
<div class="line"><a id="l03662" name="l03662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga382c3bfb429d3dcb4dc665af752e569b"> 3662</a></span><span class="preprocessor">#define CAN_F9R1_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l03663" name="l03663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd756a032170c40a6e99e78c1c52eb95"> 3663</a></span><span class="preprocessor">#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l03664" name="l03664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3db445a3214057317d84269116c9a3de"> 3664</a></span><span class="preprocessor">#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk </span></div>
|
||
<div class="line"><a id="l03665" name="l03665"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8154705ae1b389be82edd66ab25b9f81"> 3665</a></span><span class="preprocessor">#define CAN_F9R1_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l03666" name="l03666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7239e8ffb07b9aea8013fec8dded9153"> 3666</a></span><span class="preprocessor">#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l03667" name="l03667"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf09c1d038af593122315a878c15f608"> 3667</a></span><span class="preprocessor">#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk </span></div>
|
||
<div class="line"><a id="l03668" name="l03668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae584c59edb1f026fe49dc993eb084dd3"> 3668</a></span><span class="preprocessor">#define CAN_F9R1_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l03669" name="l03669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7fdb5f76ff7140ead344e774d2a7624"> 3669</a></span><span class="preprocessor">#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l03670" name="l03670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12b2a29143ddf47eb1eddf76f9289cb9"> 3670</a></span><span class="preprocessor">#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk </span></div>
|
||
<div class="line"><a id="l03671" name="l03671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8bce562ccc80042ac70f70fc9c0bc35"> 3671</a></span><span class="preprocessor">#define CAN_F9R1_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l03672" name="l03672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga156dc983e417d37a94dd165f5d3d2f93"> 3672</a></span><span class="preprocessor">#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l03673" name="l03673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga691bc907b71c30dffdf246c95240ac9b"> 3673</a></span><span class="preprocessor">#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk </span></div>
|
||
<div class="line"><a id="l03674" name="l03674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6618206f24c69189d2e432bd4efc0651"> 3674</a></span><span class="preprocessor">#define CAN_F9R1_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l03675" name="l03675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga396a55b76a656a8592faa6c6910dbb40"> 3675</a></span><span class="preprocessor">#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l03676" name="l03676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8669ceaa46f5aecada88accedfb4dbb"> 3676</a></span><span class="preprocessor">#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk </span></div>
|
||
<div class="line"><a id="l03677" name="l03677"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee8557da5e6de53987fbd0a185596107"> 3677</a></span><span class="preprocessor">#define CAN_F9R1_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l03678" name="l03678"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd456c2656ca51201b43ed9831d24d4d"> 3678</a></span><span class="preprocessor">#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l03679" name="l03679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35e8769a1e21c4cf3714667e07201804"> 3679</a></span><span class="preprocessor">#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk </span></div>
|
||
<div class="line"><a id="l03680" name="l03680"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe418890b1a83c8846daace95b47edf9"> 3680</a></span><span class="preprocessor">#define CAN_F9R1_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l03681" name="l03681"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fc59d106067ea2d6a18fd5f08ba2767"> 3681</a></span><span class="preprocessor">#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l03682" name="l03682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7060a1863aa5b08ce8469001d46c630"> 3682</a></span><span class="preprocessor">#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk </span></div>
|
||
<div class="line"><a id="l03683" name="l03683"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04c61d64fef04b48caeba748a9a22aa6"> 3683</a></span><span class="preprocessor">#define CAN_F9R1_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l03684" name="l03684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4ff327faa1fe85083a3ef4f071e86e9"> 3684</a></span><span class="preprocessor">#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l03685" name="l03685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf015fb7231bd315f82948019dcfc725"> 3685</a></span><span class="preprocessor">#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk </span></div>
|
||
<div class="line"><a id="l03686" name="l03686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35916c6399028aaf16c864a1b37f191e"> 3686</a></span><span class="preprocessor">#define CAN_F9R1_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l03687" name="l03687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1580585e09b20a6bc206c033139649a6"> 3687</a></span><span class="preprocessor">#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l03688" name="l03688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02c06b01abb3414394747a7cf8eac888"> 3688</a></span><span class="preprocessor">#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk </span></div>
|
||
<div class="line"><a id="l03689" name="l03689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa5760e3a9d5b2ae2596c1a203ac772a"> 3689</a></span><span class="preprocessor">#define CAN_F9R1_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l03690" name="l03690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa356b4a420c19ac07bfa409d55e53adc"> 3690</a></span><span class="preprocessor">#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l03691" name="l03691"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99a1a20417252e33a4817c0530745239"> 3691</a></span><span class="preprocessor">#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk </span></div>
|
||
<div class="line"><a id="l03692" name="l03692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e961ee93fb85b21e152e98eb2d69e08"> 3692</a></span><span class="preprocessor">#define CAN_F9R1_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l03693" name="l03693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f43ec3ddec319e7dfbda3b44c7c2df4"> 3693</a></span><span class="preprocessor">#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l03694" name="l03694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09c0f503e2ef85b3b6332ccbca7b0251"> 3694</a></span><span class="preprocessor">#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk </span></div>
|
||
<div class="line"><a id="l03695" name="l03695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedf1cb9ca8fd641443fbddc3b66dd953"> 3695</a></span><span class="preprocessor">#define CAN_F9R1_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l03696" name="l03696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a5361a1933b142476427e60fc3f9c72"> 3696</a></span><span class="preprocessor">#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l03697" name="l03697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacab12d06dee3d6dad5fd7c56c23c70d1"> 3697</a></span><span class="preprocessor">#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk </span></div>
|
||
<div class="line"><a id="l03698" name="l03698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad975dfcf3d01716533fb54d8b61787c2"> 3698</a></span><span class="preprocessor">#define CAN_F9R1_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l03699" name="l03699"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55a508f12177632ba51a7ddc551ed9e2"> 3699</a></span><span class="preprocessor">#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l03700" name="l03700"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c72a8d17db1de69086f19579b169c04"> 3700</a></span><span class="preprocessor">#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk </span></div>
|
||
<div class="line"><a id="l03701" name="l03701"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad49102a5c0f38207584062f8303da2f5"> 3701</a></span><span class="preprocessor">#define CAN_F9R1_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l03702" name="l03702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65ef341230d8345ce5e8176674f9f745"> 3702</a></span><span class="preprocessor">#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l03703" name="l03703"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bb3ba674ec6c82ed108f6c0bfb2f854"> 3703</a></span><span class="preprocessor">#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk </span></div>
|
||
<div class="line"><a id="l03704" name="l03704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac621c869012858627036bd298ced7e8f"> 3704</a></span><span class="preprocessor">#define CAN_F9R1_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l03705" name="l03705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga309068d091fa9bd5abd28c709efb96c8"> 3705</a></span><span class="preprocessor">#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l03706" name="l03706"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba13bd7fa1e4c2eaef3de31d933cbc10"> 3706</a></span><span class="preprocessor">#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk </span></div>
|
||
<div class="line"><a id="l03707" name="l03707"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4cb66980120bd88fc4a472a87ea672e4"> 3707</a></span><span class="preprocessor">#define CAN_F9R1_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l03708" name="l03708"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac97a1bd116fc0f32a29c4c3006d0330d"> 3708</a></span><span class="preprocessor">#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l03709" name="l03709"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa72247fe16d8f777c26726063fa43536"> 3709</a></span><span class="preprocessor">#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk </span></div>
|
||
<div class="line"><a id="l03710" name="l03710"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f2aaac573ee7915936b4c68ab36fc5a"> 3710</a></span><span class="preprocessor">#define CAN_F9R1_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l03711" name="l03711"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ed19ac97bbe1e8d109a31af97ac183c"> 3711</a></span><span class="preprocessor">#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l03712" name="l03712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32d7c1678449ff8f4e4b6f548ba85be4"> 3712</a></span><span class="preprocessor">#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk </span></div>
|
||
<div class="line"><a id="l03713" name="l03713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00c420c0a498d9f93ae7b78d10c90171"> 3713</a></span><span class="preprocessor">#define CAN_F9R1_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l03714" name="l03714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bfa05da1393f001376725caac1a5cb1"> 3714</a></span><span class="preprocessor">#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l03715" name="l03715"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga678d4a0a39b379db5c2e0285782c686f"> 3715</a></span><span class="preprocessor">#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk </span></div>
|
||
<div class="line"><a id="l03716" name="l03716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e5d9b745f7bd053a3843faf405b7eb1"> 3716</a></span><span class="preprocessor">#define CAN_F9R1_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l03717" name="l03717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab301858f2e91edd141441ebf4be606b"> 3717</a></span><span class="preprocessor">#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l03718" name="l03718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6033aa5f4d140dc48ddb4a777583163c"> 3718</a></span><span class="preprocessor">#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk </span></div>
|
||
<div class="line"><a id="l03719" name="l03719"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8fc29302b5a2404550b37a1e62c0f11"> 3719</a></span><span class="preprocessor">#define CAN_F9R1_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l03720" name="l03720"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac23f3b612ef426adf60238083766f4a8"> 3720</a></span><span class="preprocessor">#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l03721" name="l03721"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fda159c684d7361094da1883473b544"> 3721</a></span><span class="preprocessor">#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk </span></div>
|
||
<div class="line"><a id="l03722" name="l03722"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec4d21090abcdafb53a216c6507cbf57"> 3722</a></span><span class="preprocessor">#define CAN_F9R1_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l03723" name="l03723"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0799e2743ca085ddc2d3557c81d4fb5a"> 3723</a></span><span class="preprocessor">#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l03724" name="l03724"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83cf4080564c51a0123b97840576c0ab"> 3724</a></span><span class="preprocessor">#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk </span></div>
|
||
<div class="line"><a id="l03725" name="l03725"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c781d400959fec8e3f8636b97c6227c"> 3725</a></span><span class="preprocessor">#define CAN_F9R1_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l03726" name="l03726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac69d0815a7cd9bf18de74375fea92676"> 3726</a></span><span class="preprocessor">#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l03727" name="l03727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga127c155bc5c5236f04cfdcf96ff66cc5"> 3727</a></span><span class="preprocessor">#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk </span></div>
|
||
<div class="line"><a id="l03729" name="l03729"></a><span class="lineno"> 3729</span><span class="comment">/******************* Bit definition for CAN_F10R1 register ******************/</span></div>
|
||
<div class="line"><a id="l03730" name="l03730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34b8639dd16a3b599266e6a777fb604d"> 3730</a></span><span class="preprocessor">#define CAN_F10R1_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l03731" name="l03731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a05b74c330bf04f1f6f3ae982306f57"> 3731</a></span><span class="preprocessor">#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l03732" name="l03732"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d5b5b7bc147da430d9c8fbe03679ca3"> 3732</a></span><span class="preprocessor">#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk </span></div>
|
||
<div class="line"><a id="l03733" name="l03733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61d255693dabbb9177ad7a611aac5958"> 3733</a></span><span class="preprocessor">#define CAN_F10R1_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l03734" name="l03734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccc10e15c593cf151539aaf626131cd6"> 3734</a></span><span class="preprocessor">#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l03735" name="l03735"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ed7be0180fd7096f10cfde27261ecc9"> 3735</a></span><span class="preprocessor">#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk </span></div>
|
||
<div class="line"><a id="l03736" name="l03736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e899e29234df6b50a1866c607823ca8"> 3736</a></span><span class="preprocessor">#define CAN_F10R1_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l03737" name="l03737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cc815403ff9f3643971ecd50b8e1c0a"> 3737</a></span><span class="preprocessor">#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l03738" name="l03738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad099442eb6b71912a81d1f6fccbaec0a"> 3738</a></span><span class="preprocessor">#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk </span></div>
|
||
<div class="line"><a id="l03739" name="l03739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b6414ba4791274ad1dedeae302deb8c"> 3739</a></span><span class="preprocessor">#define CAN_F10R1_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l03740" name="l03740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc1db4c0b25f68a6bd3c6cbb2d2c82ee"> 3740</a></span><span class="preprocessor">#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l03741" name="l03741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4024c53b7b0cec550baed99ae92e3465"> 3741</a></span><span class="preprocessor">#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk </span></div>
|
||
<div class="line"><a id="l03742" name="l03742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1468d4f971fefa12ac2373e9059fcc4"> 3742</a></span><span class="preprocessor">#define CAN_F10R1_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l03743" name="l03743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad91329ef7b3229b4f06f31c8fbaa8507"> 3743</a></span><span class="preprocessor">#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l03744" name="l03744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1859eaac9ae1220c752218e5ad526179"> 3744</a></span><span class="preprocessor">#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk </span></div>
|
||
<div class="line"><a id="l03745" name="l03745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5059f789c76d31ef43d2933a6794ebef"> 3745</a></span><span class="preprocessor">#define CAN_F10R1_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l03746" name="l03746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf7af08619a0d22a111e253c1059024d"> 3746</a></span><span class="preprocessor">#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l03747" name="l03747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5683dc25f0aae9a802a5f57c88bec856"> 3747</a></span><span class="preprocessor">#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk </span></div>
|
||
<div class="line"><a id="l03748" name="l03748"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c9f5e78c2fbffbca7976837c901ae11"> 3748</a></span><span class="preprocessor">#define CAN_F10R1_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l03749" name="l03749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fcb5577636b7acc70f13f92cbfa3f9a"> 3749</a></span><span class="preprocessor">#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l03750" name="l03750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae83dd9ce8a2c7917e278ce4755f8f43e"> 3750</a></span><span class="preprocessor">#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk </span></div>
|
||
<div class="line"><a id="l03751" name="l03751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3456bf703efc85fb20bc9ccae394e575"> 3751</a></span><span class="preprocessor">#define CAN_F10R1_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l03752" name="l03752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga557466eedc11bcfb78333511b3465921"> 3752</a></span><span class="preprocessor">#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l03753" name="l03753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93ad070c9f5abca3c9b9095e3a13db9c"> 3753</a></span><span class="preprocessor">#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk </span></div>
|
||
<div class="line"><a id="l03754" name="l03754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac77280ec33da757f550aa90612a3e45c"> 3754</a></span><span class="preprocessor">#define CAN_F10R1_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l03755" name="l03755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga451e0f30e41e5216fb223e52bdadce7a"> 3755</a></span><span class="preprocessor">#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l03756" name="l03756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd32db3ffec3536cd842e17c34c210d9"> 3756</a></span><span class="preprocessor">#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk </span></div>
|
||
<div class="line"><a id="l03757" name="l03757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5340c5e8483f2ab61e51f7f4b0d6a78a"> 3757</a></span><span class="preprocessor">#define CAN_F10R1_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l03758" name="l03758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga434ad62e086a866ca425960236216d34"> 3758</a></span><span class="preprocessor">#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l03759" name="l03759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85673ce7a92ae8ca9a13ed2fb5574a76"> 3759</a></span><span class="preprocessor">#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk </span></div>
|
||
<div class="line"><a id="l03760" name="l03760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52a16b6466cddacc04e9200bea868510"> 3760</a></span><span class="preprocessor">#define CAN_F10R1_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l03761" name="l03761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga159afb7939de25a56d4a7c72e3669b8c"> 3761</a></span><span class="preprocessor">#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l03762" name="l03762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d525825fe4bfc1d4ffccc21ab89a3fa"> 3762</a></span><span class="preprocessor">#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk </span></div>
|
||
<div class="line"><a id="l03763" name="l03763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77878bda5d61d09fa0b3ea54a208c889"> 3763</a></span><span class="preprocessor">#define CAN_F10R1_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l03764" name="l03764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa37f47760352e40a33327441fa44917a"> 3764</a></span><span class="preprocessor">#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l03765" name="l03765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33336e283eeee9b77f1f289d77f2304e"> 3765</a></span><span class="preprocessor">#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk </span></div>
|
||
<div class="line"><a id="l03766" name="l03766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb667a50ca9535347b011c47aa7f7f8a"> 3766</a></span><span class="preprocessor">#define CAN_F10R1_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l03767" name="l03767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6456e18d6659ec3437ab1b5c84b60681"> 3767</a></span><span class="preprocessor">#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l03768" name="l03768"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf74ee01e72b3de69d6e8fcc092f7461"> 3768</a></span><span class="preprocessor">#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk </span></div>
|
||
<div class="line"><a id="l03769" name="l03769"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf29dbf589e4978181256649c864076da"> 3769</a></span><span class="preprocessor">#define CAN_F10R1_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l03770" name="l03770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f0b809ab8b05e662982533d29d34196"> 3770</a></span><span class="preprocessor">#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l03771" name="l03771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ee416ff22b47bb289bab34afbc74f19"> 3771</a></span><span class="preprocessor">#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk </span></div>
|
||
<div class="line"><a id="l03772" name="l03772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1630e20424cfa65e81a05cce2c1f7337"> 3772</a></span><span class="preprocessor">#define CAN_F10R1_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l03773" name="l03773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1553e078a11eeb8d8ea8c0e0448b4d0"> 3773</a></span><span class="preprocessor">#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l03774" name="l03774"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97a8d8586c64910b0f6c09fef44c4ea7"> 3774</a></span><span class="preprocessor">#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk </span></div>
|
||
<div class="line"><a id="l03775" name="l03775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1651020c3774aaad2dcda820e38a4b61"> 3775</a></span><span class="preprocessor">#define CAN_F10R1_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l03776" name="l03776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga372ca9243e9a38085b93d717f05b885a"> 3776</a></span><span class="preprocessor">#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l03777" name="l03777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9e8e43adc56ba1e593b97e062c79075"> 3777</a></span><span class="preprocessor">#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk </span></div>
|
||
<div class="line"><a id="l03778" name="l03778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad18243430f119e7ed075890d0c4ee9bd"> 3778</a></span><span class="preprocessor">#define CAN_F10R1_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l03779" name="l03779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90ecfd894be7f8a4d1eb0cbfe995f7a8"> 3779</a></span><span class="preprocessor">#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l03780" name="l03780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa64a0b16c073b51cb5e90b94c638fd95"> 3780</a></span><span class="preprocessor">#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk </span></div>
|
||
<div class="line"><a id="l03781" name="l03781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d5b824a1aa2f34e1c413feffd1503fd"> 3781</a></span><span class="preprocessor">#define CAN_F10R1_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l03782" name="l03782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d4bfbfb134e99de69fe63974eae0eba"> 3782</a></span><span class="preprocessor">#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l03783" name="l03783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65f5cc396cfcf3bad71a71326e64f7d9"> 3783</a></span><span class="preprocessor">#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk </span></div>
|
||
<div class="line"><a id="l03784" name="l03784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ca233f5cf20e9ec03df3088fdf56f06"> 3784</a></span><span class="preprocessor">#define CAN_F10R1_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l03785" name="l03785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59843c48e4723e0d3cb389b8dc31e95a"> 3785</a></span><span class="preprocessor">#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l03786" name="l03786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga424940f535aa9a1520e25df53673d01f"> 3786</a></span><span class="preprocessor">#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk </span></div>
|
||
<div class="line"><a id="l03787" name="l03787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6910b732b7855530c3a345d1b027a7f4"> 3787</a></span><span class="preprocessor">#define CAN_F10R1_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l03788" name="l03788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga028e9c16a75cfe1a4209db5761793d65"> 3788</a></span><span class="preprocessor">#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l03789" name="l03789"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga166a4035770c58147d583c3dc571d10a"> 3789</a></span><span class="preprocessor">#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk </span></div>
|
||
<div class="line"><a id="l03790" name="l03790"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab55c921e020738e5610d97fe033855c7"> 3790</a></span><span class="preprocessor">#define CAN_F10R1_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l03791" name="l03791"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d3e3967b90e93cdf5d2dff50ccd6467"> 3791</a></span><span class="preprocessor">#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l03792" name="l03792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga302214ece439e8913b47949bd07d118a"> 3792</a></span><span class="preprocessor">#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk </span></div>
|
||
<div class="line"><a id="l03793" name="l03793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga971d242e49fe7359b6e741466d305411"> 3793</a></span><span class="preprocessor">#define CAN_F10R1_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l03794" name="l03794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f7d08dc1418dc7260c85dcd41c3f2f7"> 3794</a></span><span class="preprocessor">#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l03795" name="l03795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9abe6ae1dcb2bd140e7e28d37fd8abb"> 3795</a></span><span class="preprocessor">#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk </span></div>
|
||
<div class="line"><a id="l03796" name="l03796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf28c54456414ccbb9b51ce644d47601"> 3796</a></span><span class="preprocessor">#define CAN_F10R1_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l03797" name="l03797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33f696dbd8db5370eb9701e521227e2e"> 3797</a></span><span class="preprocessor">#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l03798" name="l03798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99063956b41c4dcf6c78cc29305b1cd1"> 3798</a></span><span class="preprocessor">#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk </span></div>
|
||
<div class="line"><a id="l03799" name="l03799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9adb7b8a937732924faef5a13b6d691c"> 3799</a></span><span class="preprocessor">#define CAN_F10R1_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l03800" name="l03800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4b78077f4a9d949debb3c345fcc8203"> 3800</a></span><span class="preprocessor">#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l03801" name="l03801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81ae64786c3a83bdd21cf72c560c7c1e"> 3801</a></span><span class="preprocessor">#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk </span></div>
|
||
<div class="line"><a id="l03802" name="l03802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3774098d002351e5997edddd0c0ce5d0"> 3802</a></span><span class="preprocessor">#define CAN_F10R1_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l03803" name="l03803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadaa800d4dbab113869136419067683b7"> 3803</a></span><span class="preprocessor">#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l03804" name="l03804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f9083faf8395701c892814694b45d2c"> 3804</a></span><span class="preprocessor">#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk </span></div>
|
||
<div class="line"><a id="l03805" name="l03805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91439fb8d069e77aeb88065b1c685f89"> 3805</a></span><span class="preprocessor">#define CAN_F10R1_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l03806" name="l03806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2755b753aff086d43feba71cc367da2"> 3806</a></span><span class="preprocessor">#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l03807" name="l03807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaeb6942affe306b407940fdf01534e4a"> 3807</a></span><span class="preprocessor">#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk </span></div>
|
||
<div class="line"><a id="l03808" name="l03808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed8963dfbdac3df92f96632e9f8973a9"> 3808</a></span><span class="preprocessor">#define CAN_F10R1_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l03809" name="l03809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea7c4b309760f303d4bbd9ef507673d9"> 3809</a></span><span class="preprocessor">#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l03810" name="l03810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e4ee946a9614316f666852bc266c1f7"> 3810</a></span><span class="preprocessor">#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk </span></div>
|
||
<div class="line"><a id="l03811" name="l03811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacffecbefab44f2d80330ff6b3316404"> 3811</a></span><span class="preprocessor">#define CAN_F10R1_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l03812" name="l03812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga713459bb360bab56e68cd562bcc86992"> 3812</a></span><span class="preprocessor">#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l03813" name="l03813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99153cddc8fc7e846fcc44383936541f"> 3813</a></span><span class="preprocessor">#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk </span></div>
|
||
<div class="line"><a id="l03814" name="l03814"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8670b0f5b08f2106aed385abe471988"> 3814</a></span><span class="preprocessor">#define CAN_F10R1_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l03815" name="l03815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga904044b84be51c67151570af41280109"> 3815</a></span><span class="preprocessor">#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l03816" name="l03816"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e2ba1740577246368e60d94fd3d7c69"> 3816</a></span><span class="preprocessor">#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk </span></div>
|
||
<div class="line"><a id="l03817" name="l03817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac47d24136b51470d74e9e0416110e608"> 3817</a></span><span class="preprocessor">#define CAN_F10R1_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l03818" name="l03818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb9254a4f5e458db48b99024ee4dcf28"> 3818</a></span><span class="preprocessor">#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l03819" name="l03819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca062686821fba26a0e5e5b0a6c5b855"> 3819</a></span><span class="preprocessor">#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk </span></div>
|
||
<div class="line"><a id="l03820" name="l03820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29cf8efcf620782b10885d84e0ebd370"> 3820</a></span><span class="preprocessor">#define CAN_F10R1_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l03821" name="l03821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc17c37afd6e8048e5561cc76204de98"> 3821</a></span><span class="preprocessor">#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l03822" name="l03822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8981f420ef4c8fe1976a09f27a9c13f1"> 3822</a></span><span class="preprocessor">#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk </span></div>
|
||
<div class="line"><a id="l03823" name="l03823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga486a9b2d165733097746c0e075332056"> 3823</a></span><span class="preprocessor">#define CAN_F10R1_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l03824" name="l03824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0010aac3ddd9cb356328c22fcab2fd9"> 3824</a></span><span class="preprocessor">#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l03825" name="l03825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0424bf38917058b166a8bfd861d22b40"> 3825</a></span><span class="preprocessor">#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk </span></div>
|
||
<div class="line"><a id="l03827" name="l03827"></a><span class="lineno"> 3827</span><span class="comment">/******************* Bit definition for CAN_F11R1 register ******************/</span></div>
|
||
<div class="line"><a id="l03828" name="l03828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad825b1610c2deb52c7e2a14d4ffb33ae"> 3828</a></span><span class="preprocessor">#define CAN_F11R1_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l03829" name="l03829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29cf61e4385aa30fbdff533d51bdd612"> 3829</a></span><span class="preprocessor">#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l03830" name="l03830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad059cc9b2fe5634b9330b44c37dadf06"> 3830</a></span><span class="preprocessor">#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk </span></div>
|
||
<div class="line"><a id="l03831" name="l03831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga786a94d3ab775de9da9195130b1b76bb"> 3831</a></span><span class="preprocessor">#define CAN_F11R1_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l03832" name="l03832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e4ad3f7a5ffa1fd9136447924950ea6"> 3832</a></span><span class="preprocessor">#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l03833" name="l03833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad74b116cda63fcd1a662c4de835616e7"> 3833</a></span><span class="preprocessor">#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk </span></div>
|
||
<div class="line"><a id="l03834" name="l03834"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b59aee05e1add366c493e4ccd2637c5"> 3834</a></span><span class="preprocessor">#define CAN_F11R1_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l03835" name="l03835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5614e1e331777400a4903b74f3398d1c"> 3835</a></span><span class="preprocessor">#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l03836" name="l03836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e05bb0c2a5bdcebb974f7dd409724bc"> 3836</a></span><span class="preprocessor">#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk </span></div>
|
||
<div class="line"><a id="l03837" name="l03837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9db6817cdb088212132aebd6b1e6fadb"> 3837</a></span><span class="preprocessor">#define CAN_F11R1_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l03838" name="l03838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cf6f2e8167bd44d1f02ff8de4574d4d"> 3838</a></span><span class="preprocessor">#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l03839" name="l03839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa17242aed4365034dc660ef9e8b9f1bf"> 3839</a></span><span class="preprocessor">#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk </span></div>
|
||
<div class="line"><a id="l03840" name="l03840"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefa798693295399620c2a62defb02ad5"> 3840</a></span><span class="preprocessor">#define CAN_F11R1_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l03841" name="l03841"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ab99e31bdf86aaad8ba7d6ad75ba7dc"> 3841</a></span><span class="preprocessor">#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l03842" name="l03842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga450dbed19882423d70ed7606aada2453"> 3842</a></span><span class="preprocessor">#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk </span></div>
|
||
<div class="line"><a id="l03843" name="l03843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf95e8d5586045005c6fc0dbb9d42017"> 3843</a></span><span class="preprocessor">#define CAN_F11R1_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l03844" name="l03844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga554f40a4480434bf6e3633e52d45e6bd"> 3844</a></span><span class="preprocessor">#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l03845" name="l03845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7ace73f2d3db1e2a1e55257d210fa04"> 3845</a></span><span class="preprocessor">#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk </span></div>
|
||
<div class="line"><a id="l03846" name="l03846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33946da5363485ee484a5fd3b977068d"> 3846</a></span><span class="preprocessor">#define CAN_F11R1_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l03847" name="l03847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4aed14b088705fde497369d39675369e"> 3847</a></span><span class="preprocessor">#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l03848" name="l03848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1459d395a3b08a948c3f5002e0914516"> 3848</a></span><span class="preprocessor">#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk </span></div>
|
||
<div class="line"><a id="l03849" name="l03849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga390e032609e5d44f7dd0c7e9d2f5ee16"> 3849</a></span><span class="preprocessor">#define CAN_F11R1_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l03850" name="l03850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8580e565ee4bc7966aa7c515d6fab446"> 3850</a></span><span class="preprocessor">#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l03851" name="l03851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30fc2236c2a18b7cb6e493fad36d8efe"> 3851</a></span><span class="preprocessor">#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk </span></div>
|
||
<div class="line"><a id="l03852" name="l03852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73563f8f0592450f6c15ad9d91495e62"> 3852</a></span><span class="preprocessor">#define CAN_F11R1_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l03853" name="l03853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga639a8dc5a46ee8b2a380ac7978fb0672"> 3853</a></span><span class="preprocessor">#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l03854" name="l03854"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74ab4a6f6b5a751acda410e0c39b87af"> 3854</a></span><span class="preprocessor">#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk </span></div>
|
||
<div class="line"><a id="l03855" name="l03855"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01de290d95f18b06e6aed12bb01cbe88"> 3855</a></span><span class="preprocessor">#define CAN_F11R1_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l03856" name="l03856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cd49481651b80f8fdcf08efd0e07f8c"> 3856</a></span><span class="preprocessor">#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l03857" name="l03857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e69f7001534264fd027371fa188ac52"> 3857</a></span><span class="preprocessor">#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk </span></div>
|
||
<div class="line"><a id="l03858" name="l03858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ccf16da47b6e8c9a396eaca7ae390d7"> 3858</a></span><span class="preprocessor">#define CAN_F11R1_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l03859" name="l03859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7cb55bd09dade7046aa52361411fb68"> 3859</a></span><span class="preprocessor">#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l03860" name="l03860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e858dd29f741910c8ed8c512cae81b1"> 3860</a></span><span class="preprocessor">#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk </span></div>
|
||
<div class="line"><a id="l03861" name="l03861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91b2fe2b66aa2708feafdf1b5fac1a5d"> 3861</a></span><span class="preprocessor">#define CAN_F11R1_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l03862" name="l03862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6235ef02d18d862d4018aa9d3f2612bd"> 3862</a></span><span class="preprocessor">#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l03863" name="l03863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6ba167c6cd5bc080065430e24c3a866"> 3863</a></span><span class="preprocessor">#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk </span></div>
|
||
<div class="line"><a id="l03864" name="l03864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8638152a30201e227efb08a7239a9a1"> 3864</a></span><span class="preprocessor">#define CAN_F11R1_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l03865" name="l03865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga488ce892527f6e05b74c72d3540e86e9"> 3865</a></span><span class="preprocessor">#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l03866" name="l03866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4629ab1e8632c82f3fb2648a574963b1"> 3866</a></span><span class="preprocessor">#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk </span></div>
|
||
<div class="line"><a id="l03867" name="l03867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b4ada853a29ea4b6975619939ad6aeb"> 3867</a></span><span class="preprocessor">#define CAN_F11R1_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l03868" name="l03868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34726d941ba918d973035cdfd4956f22"> 3868</a></span><span class="preprocessor">#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l03869" name="l03869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga833c408a165cc4ac87a242c08d4ba9b9"> 3869</a></span><span class="preprocessor">#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk </span></div>
|
||
<div class="line"><a id="l03870" name="l03870"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga623aadd0e75b5b15052e0ee6db31b9e8"> 3870</a></span><span class="preprocessor">#define CAN_F11R1_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l03871" name="l03871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a261d1beaaa14ef8021eaa305b4cdf6"> 3871</a></span><span class="preprocessor">#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l03872" name="l03872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabfecd6bbe1a15cd341942d1840b476cc"> 3872</a></span><span class="preprocessor">#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk </span></div>
|
||
<div class="line"><a id="l03873" name="l03873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2162c84a2aee3dc40f2822bbf8967b5d"> 3873</a></span><span class="preprocessor">#define CAN_F11R1_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l03874" name="l03874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddc324a22f00abfe9bcf15478238eeda"> 3874</a></span><span class="preprocessor">#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l03875" name="l03875"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf50e1747d1d9369b7b22c5d591ae82b9"> 3875</a></span><span class="preprocessor">#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk </span></div>
|
||
<div class="line"><a id="l03876" name="l03876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2464caefce933de15008f8e10a0229a"> 3876</a></span><span class="preprocessor">#define CAN_F11R1_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l03877" name="l03877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67cc7cf7f00a9e32c2bd48dcd4941eeb"> 3877</a></span><span class="preprocessor">#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l03878" name="l03878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga603d63333a621594a15696cb03f59eeb"> 3878</a></span><span class="preprocessor">#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk </span></div>
|
||
<div class="line"><a id="l03879" name="l03879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac59287ed65d1bab31859947cf1c0e520"> 3879</a></span><span class="preprocessor">#define CAN_F11R1_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l03880" name="l03880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5442d8600f85b1f2efb8cd2a0a9ec764"> 3880</a></span><span class="preprocessor">#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l03881" name="l03881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb361a00177e6aa2ee19aa5a2d1781aa"> 3881</a></span><span class="preprocessor">#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk </span></div>
|
||
<div class="line"><a id="l03882" name="l03882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd205d1cabe770ac20592d94a9a59a02"> 3882</a></span><span class="preprocessor">#define CAN_F11R1_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l03883" name="l03883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga882ce3ab193542e376fb5f6d4f497a46"> 3883</a></span><span class="preprocessor">#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l03884" name="l03884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf111110e0f5dbda31962f7732e3480c7"> 3884</a></span><span class="preprocessor">#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk </span></div>
|
||
<div class="line"><a id="l03885" name="l03885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdda7d2445b53f67f690c62be9246090"> 3885</a></span><span class="preprocessor">#define CAN_F11R1_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l03886" name="l03886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d345cf87d73bed1e41d1fdd1da16378"> 3886</a></span><span class="preprocessor">#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l03887" name="l03887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf2c4828b07b2b315d27b382818de285"> 3887</a></span><span class="preprocessor">#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk </span></div>
|
||
<div class="line"><a id="l03888" name="l03888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bc43b832b438ebbad185e628f43c46c"> 3888</a></span><span class="preprocessor">#define CAN_F11R1_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l03889" name="l03889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7955a656970b266f1398cdfc4bdb6cb"> 3889</a></span><span class="preprocessor">#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l03890" name="l03890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5afa52941bb68a03ec9804b817d5a90e"> 3890</a></span><span class="preprocessor">#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk </span></div>
|
||
<div class="line"><a id="l03891" name="l03891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga407a5d20941e9430ed2d0a146328ac31"> 3891</a></span><span class="preprocessor">#define CAN_F11R1_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l03892" name="l03892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a5b2c12419c4cff708970be601ad3e2"> 3892</a></span><span class="preprocessor">#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l03893" name="l03893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac042471dbcb1a32ce161f38a144ac5aa"> 3893</a></span><span class="preprocessor">#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk </span></div>
|
||
<div class="line"><a id="l03894" name="l03894"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2af39e6af45c497fc6f8f9e21892aff"> 3894</a></span><span class="preprocessor">#define CAN_F11R1_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l03895" name="l03895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ad2a3cd3442663331b96444d1ed798e"> 3895</a></span><span class="preprocessor">#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l03896" name="l03896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac46f233c9692cb2a2e246daf6547a38"> 3896</a></span><span class="preprocessor">#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk </span></div>
|
||
<div class="line"><a id="l03897" name="l03897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga413238cb6d5869b63b343f15b589a7d0"> 3897</a></span><span class="preprocessor">#define CAN_F11R1_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l03898" name="l03898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0869365b6223739ccb3b62cfadd9f1db"> 3898</a></span><span class="preprocessor">#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l03899" name="l03899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8b379e3832482f2b18f01713d3338d5"> 3899</a></span><span class="preprocessor">#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk </span></div>
|
||
<div class="line"><a id="l03900" name="l03900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac72a9af5034ed0aedfb37bf45717785f"> 3900</a></span><span class="preprocessor">#define CAN_F11R1_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l03901" name="l03901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ed24f7ad9ae64b130e3e2ce65cf5d04"> 3901</a></span><span class="preprocessor">#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l03902" name="l03902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60eabd8db9ec6b439d60dbc2374ce84d"> 3902</a></span><span class="preprocessor">#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk </span></div>
|
||
<div class="line"><a id="l03903" name="l03903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3375fdb7a20bb2603e470ceefb5ea811"> 3903</a></span><span class="preprocessor">#define CAN_F11R1_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l03904" name="l03904"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c2fdd934f06f41139da93cf271c9e5b"> 3904</a></span><span class="preprocessor">#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l03905" name="l03905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga351a183cfab10d3daab415c85cc16203"> 3905</a></span><span class="preprocessor">#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk </span></div>
|
||
<div class="line"><a id="l03906" name="l03906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga856a5c13143c62e9fe351bc40419273a"> 3906</a></span><span class="preprocessor">#define CAN_F11R1_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l03907" name="l03907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga547f899b4aaa6323c75dc4660cc6dd4e"> 3907</a></span><span class="preprocessor">#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l03908" name="l03908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb854a85c7a575a45cdade37efb4edee"> 3908</a></span><span class="preprocessor">#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk </span></div>
|
||
<div class="line"><a id="l03909" name="l03909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bc7863389837d8c6e58d46c87543339"> 3909</a></span><span class="preprocessor">#define CAN_F11R1_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l03910" name="l03910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5499db54e781ed6a09c987857d851e4b"> 3910</a></span><span class="preprocessor">#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l03911" name="l03911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga131776c359f81500d3d2a97535d7e718"> 3911</a></span><span class="preprocessor">#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk </span></div>
|
||
<div class="line"><a id="l03912" name="l03912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6146861f9546873f507b6ec159010caf"> 3912</a></span><span class="preprocessor">#define CAN_F11R1_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l03913" name="l03913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80b8ed435fa7866580be0ec7cfada3ce"> 3913</a></span><span class="preprocessor">#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l03914" name="l03914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga680d7e4c7ebc431a8c72c00e9f110563"> 3914</a></span><span class="preprocessor">#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk </span></div>
|
||
<div class="line"><a id="l03915" name="l03915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14db22bec110547f85af0a1d37723bdc"> 3915</a></span><span class="preprocessor">#define CAN_F11R1_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l03916" name="l03916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fa11c1e2e43d9234f768ca5f3db3521"> 3916</a></span><span class="preprocessor">#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l03917" name="l03917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c1fa00ee18804c169541d18995dc3c1"> 3917</a></span><span class="preprocessor">#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk </span></div>
|
||
<div class="line"><a id="l03918" name="l03918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed80cbf06c649fa59a60cc19bffb3ca5"> 3918</a></span><span class="preprocessor">#define CAN_F11R1_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l03919" name="l03919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga665b624ef9be8a7b67fd0d0c8a2cc28d"> 3919</a></span><span class="preprocessor">#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l03920" name="l03920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec35d8d1097816c5ef8e28ff61469669"> 3920</a></span><span class="preprocessor">#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk </span></div>
|
||
<div class="line"><a id="l03921" name="l03921"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac933da1992c44dc61bea38e44c376f01"> 3921</a></span><span class="preprocessor">#define CAN_F11R1_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l03922" name="l03922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb79224e74be4064c186c1fd8f430b3f"> 3922</a></span><span class="preprocessor">#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l03923" name="l03923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96180b8c64aabd33f016fb97ba152f07"> 3923</a></span><span class="preprocessor">#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk </span></div>
|
||
<div class="line"><a id="l03925" name="l03925"></a><span class="lineno"> 3925</span><span class="comment">/******************* Bit definition for CAN_F12R1 register ******************/</span></div>
|
||
<div class="line"><a id="l03926" name="l03926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f295f2367e770b2d0a6c376512bf73a"> 3926</a></span><span class="preprocessor">#define CAN_F12R1_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l03927" name="l03927"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga493ad4f71737d83380a81e3df1fafca6"> 3927</a></span><span class="preprocessor">#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l03928" name="l03928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccbe3637fb55f28496ca7f692a69f6ca"> 3928</a></span><span class="preprocessor">#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk </span></div>
|
||
<div class="line"><a id="l03929" name="l03929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17093a08b107416231f3d9028b7e161d"> 3929</a></span><span class="preprocessor">#define CAN_F12R1_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l03930" name="l03930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a4cc96e515fe07094a824e27ad4d925"> 3930</a></span><span class="preprocessor">#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l03931" name="l03931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae625d21947ae82cc3509b06363ad0635"> 3931</a></span><span class="preprocessor">#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk </span></div>
|
||
<div class="line"><a id="l03932" name="l03932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9311ab17c937d6e57b9e2e5ae93494b4"> 3932</a></span><span class="preprocessor">#define CAN_F12R1_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l03933" name="l03933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c8d6c0e2c177e40ff60568beffac86b"> 3933</a></span><span class="preprocessor">#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l03934" name="l03934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9de7cc313f2b6b16a564b13b1bc30157"> 3934</a></span><span class="preprocessor">#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk </span></div>
|
||
<div class="line"><a id="l03935" name="l03935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8158fab7bc36d56b1202e637d45e0ee9"> 3935</a></span><span class="preprocessor">#define CAN_F12R1_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l03936" name="l03936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34c79794004930e3de57c8417f7c5d6d"> 3936</a></span><span class="preprocessor">#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l03937" name="l03937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac039cc1ce2281cf10be62cbc44748f5f"> 3937</a></span><span class="preprocessor">#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk </span></div>
|
||
<div class="line"><a id="l03938" name="l03938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2db6bf56bfc0ceb513363931e2f032dc"> 3938</a></span><span class="preprocessor">#define CAN_F12R1_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l03939" name="l03939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93b358c5c72ac735e4c7c802287f9903"> 3939</a></span><span class="preprocessor">#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l03940" name="l03940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc3a35b6f6b3a46c176398ec322fd6fb"> 3940</a></span><span class="preprocessor">#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk </span></div>
|
||
<div class="line"><a id="l03941" name="l03941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2298551f803cc3ee122b170a68369c63"> 3941</a></span><span class="preprocessor">#define CAN_F12R1_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l03942" name="l03942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9cc058f703f84921bf889c9ce3c000d0"> 3942</a></span><span class="preprocessor">#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l03943" name="l03943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d005c10fe75169336104c3155294000"> 3943</a></span><span class="preprocessor">#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk </span></div>
|
||
<div class="line"><a id="l03944" name="l03944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2183cc81753585bdca7ca731db48f6ae"> 3944</a></span><span class="preprocessor">#define CAN_F12R1_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l03945" name="l03945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86849d0bdcd7b03a0770c9fb4e1c0cf8"> 3945</a></span><span class="preprocessor">#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l03946" name="l03946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51256bfed734a95da3e7880e279432bf"> 3946</a></span><span class="preprocessor">#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk </span></div>
|
||
<div class="line"><a id="l03947" name="l03947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f008c792182223c7f2ed45c5cec3461"> 3947</a></span><span class="preprocessor">#define CAN_F12R1_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l03948" name="l03948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd7e08cb6960016b6a352bd8353733dd"> 3948</a></span><span class="preprocessor">#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l03949" name="l03949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c967f124b03968372d801e1393fa209"> 3949</a></span><span class="preprocessor">#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk </span></div>
|
||
<div class="line"><a id="l03950" name="l03950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb125f5efb6b0daae3758f92a2aadcbb"> 3950</a></span><span class="preprocessor">#define CAN_F12R1_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l03951" name="l03951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad138ae340d080c7b69b9dfe0814234f6"> 3951</a></span><span class="preprocessor">#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l03952" name="l03952"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga592f9953deeb56888144c72060d04e24"> 3952</a></span><span class="preprocessor">#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk </span></div>
|
||
<div class="line"><a id="l03953" name="l03953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf5573719f28f6259a0c06f933691797"> 3953</a></span><span class="preprocessor">#define CAN_F12R1_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l03954" name="l03954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb0713b2abf45e4c66dfc0c2f4aa902c"> 3954</a></span><span class="preprocessor">#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l03955" name="l03955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d1613eac2aaeafda711cf3308ccd44c"> 3955</a></span><span class="preprocessor">#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk </span></div>
|
||
<div class="line"><a id="l03956" name="l03956"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae32861a7d09171945a044611c0799be5"> 3956</a></span><span class="preprocessor">#define CAN_F12R1_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l03957" name="l03957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3becedeec4964364eb6a6ca51af6c7a7"> 3957</a></span><span class="preprocessor">#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l03958" name="l03958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b8594ab0c5d9124accd2d6ca85cf4bd"> 3958</a></span><span class="preprocessor">#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk </span></div>
|
||
<div class="line"><a id="l03959" name="l03959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga038226b9a5057333b93511a33a628df5"> 3959</a></span><span class="preprocessor">#define CAN_F12R1_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l03960" name="l03960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ab33464326b0107849ae73eb2d74649"> 3960</a></span><span class="preprocessor">#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l03961" name="l03961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4025ed76892f23e5a63d0d8ac6a2be5f"> 3961</a></span><span class="preprocessor">#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk </span></div>
|
||
<div class="line"><a id="l03962" name="l03962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50aa1cdae5ac88b5dfb35f4e7fa1efa6"> 3962</a></span><span class="preprocessor">#define CAN_F12R1_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l03963" name="l03963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac55c96f63d9cb2115cf779e2108cd2c2"> 3963</a></span><span class="preprocessor">#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l03964" name="l03964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e2e318cc14828c118bd40d982922e14"> 3964</a></span><span class="preprocessor">#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk </span></div>
|
||
<div class="line"><a id="l03965" name="l03965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4705c5fa21a51b511e077c3812068f53"> 3965</a></span><span class="preprocessor">#define CAN_F12R1_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l03966" name="l03966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6754922701ae479453231e3082f5995"> 3966</a></span><span class="preprocessor">#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l03967" name="l03967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e0ff698b5e9f3f99a421166611b041d"> 3967</a></span><span class="preprocessor">#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk </span></div>
|
||
<div class="line"><a id="l03968" name="l03968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabece220b17e1d4e3d305e083f7a8cdf6"> 3968</a></span><span class="preprocessor">#define CAN_F12R1_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l03969" name="l03969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40af5057b396387a1162d0091b2d826e"> 3969</a></span><span class="preprocessor">#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l03970" name="l03970"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b0666538a7646ddc0fcd882a261f5d9"> 3970</a></span><span class="preprocessor">#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk </span></div>
|
||
<div class="line"><a id="l03971" name="l03971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdd867683a9a1ea022cfa4211a5079d0"> 3971</a></span><span class="preprocessor">#define CAN_F12R1_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l03972" name="l03972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4a4f362ed99f3b71078c88c720f7603"> 3972</a></span><span class="preprocessor">#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l03973" name="l03973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga846d84b3d53e305b093198379f442528"> 3973</a></span><span class="preprocessor">#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk </span></div>
|
||
<div class="line"><a id="l03974" name="l03974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab018f535eba98e6869cb39a15b6b27d6"> 3974</a></span><span class="preprocessor">#define CAN_F12R1_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l03975" name="l03975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44038ad11ff535489420a521d43090cd"> 3975</a></span><span class="preprocessor">#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l03976" name="l03976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7940c0898c2ef1d9f829bf1b6b5fcf3"> 3976</a></span><span class="preprocessor">#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk </span></div>
|
||
<div class="line"><a id="l03977" name="l03977"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga518951f7f8d5f8a22f7782ea13a2ac0c"> 3977</a></span><span class="preprocessor">#define CAN_F12R1_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l03978" name="l03978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1462a6bf5fd7f197bf4fc6b40f3531e"> 3978</a></span><span class="preprocessor">#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l03979" name="l03979"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6bdc7bd4dbad1f8e3bb622343bd7c522"> 3979</a></span><span class="preprocessor">#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk </span></div>
|
||
<div class="line"><a id="l03980" name="l03980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1f6af451262400037581950b32da4b8"> 3980</a></span><span class="preprocessor">#define CAN_F12R1_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l03981" name="l03981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ded4d9316004285d4c49d62eb48cce6"> 3981</a></span><span class="preprocessor">#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l03982" name="l03982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c870a6fbae41b4f1c6d66ab690789d6"> 3982</a></span><span class="preprocessor">#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk </span></div>
|
||
<div class="line"><a id="l03983" name="l03983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f9e3a6b9cf0673647bd9adfeadb887c"> 3983</a></span><span class="preprocessor">#define CAN_F12R1_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l03984" name="l03984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38b5a9bb84c7973eb3aee9bcc751a402"> 3984</a></span><span class="preprocessor">#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l03985" name="l03985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09e179b38460e47b81616c46a5f356f8"> 3985</a></span><span class="preprocessor">#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk </span></div>
|
||
<div class="line"><a id="l03986" name="l03986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a25348307ed3392337ad2a40bdfe73a"> 3986</a></span><span class="preprocessor">#define CAN_F12R1_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l03987" name="l03987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33e4aaef17496cf40db364d4c7ead7d5"> 3987</a></span><span class="preprocessor">#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l03988" name="l03988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad42e298d4d97c98cc5149bc552a598fa"> 3988</a></span><span class="preprocessor">#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk </span></div>
|
||
<div class="line"><a id="l03989" name="l03989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga752faf78fd8e420905118261b231241c"> 3989</a></span><span class="preprocessor">#define CAN_F12R1_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l03990" name="l03990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga776befd35d22caa64a1754b75134f2a6"> 3990</a></span><span class="preprocessor">#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l03991" name="l03991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga318e2a6ae62d5172dcdb45e011d5e0c4"> 3991</a></span><span class="preprocessor">#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk </span></div>
|
||
<div class="line"><a id="l03992" name="l03992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3238cf7161e4270d40115f5b61431a22"> 3992</a></span><span class="preprocessor">#define CAN_F12R1_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l03993" name="l03993"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d5b00cf1faf748d52633ee2a1989b49"> 3993</a></span><span class="preprocessor">#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l03994" name="l03994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90e95cb0020289335acd5d7f4b62a880"> 3994</a></span><span class="preprocessor">#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk </span></div>
|
||
<div class="line"><a id="l03995" name="l03995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd7d9b502598ae8cc04847d5cf9c0b52"> 3995</a></span><span class="preprocessor">#define CAN_F12R1_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l03996" name="l03996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa9c58f403ed9bfc19a23aff1960065e"> 3996</a></span><span class="preprocessor">#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l03997" name="l03997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e2720e18fdff00c9fb75d5136e485dc"> 3997</a></span><span class="preprocessor">#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk </span></div>
|
||
<div class="line"><a id="l03998" name="l03998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b9e2a2787690c33948183acf3e600fd"> 3998</a></span><span class="preprocessor">#define CAN_F12R1_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l03999" name="l03999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7efaf0ba941dc22a8a322e75d6495237"> 3999</a></span><span class="preprocessor">#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l04000" name="l04000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4a87123ae5ff76992162152fbb4c92a"> 4000</a></span><span class="preprocessor">#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk </span></div>
|
||
<div class="line"><a id="l04001" name="l04001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae772d3a7da965bbd759aa2ffceeb3ae4"> 4001</a></span><span class="preprocessor">#define CAN_F12R1_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l04002" name="l04002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga495bdfd934bc40aeabfcb0454e47a2c7"> 4002</a></span><span class="preprocessor">#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l04003" name="l04003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9582717e16455f97c7dff65f7beadd6e"> 4003</a></span><span class="preprocessor">#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk </span></div>
|
||
<div class="line"><a id="l04004" name="l04004"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48905689b327cf537df7a4e7f12ed097"> 4004</a></span><span class="preprocessor">#define CAN_F12R1_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l04005" name="l04005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26edbc0aad33ae916a2c765f8a463023"> 4005</a></span><span class="preprocessor">#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l04006" name="l04006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf15e362beb5a3b733c08c8c2ab81efcb"> 4006</a></span><span class="preprocessor">#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk </span></div>
|
||
<div class="line"><a id="l04007" name="l04007"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaece06032650d7777a44ada0b8cc4a85b"> 4007</a></span><span class="preprocessor">#define CAN_F12R1_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l04008" name="l04008"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb051023923964df52386c58e0ee26ed"> 4008</a></span><span class="preprocessor">#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l04009" name="l04009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d600a7a39c7069c216db511d3a5d866"> 4009</a></span><span class="preprocessor">#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk </span></div>
|
||
<div class="line"><a id="l04010" name="l04010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3fe5041f598b90c619dfa60edee91ced"> 4010</a></span><span class="preprocessor">#define CAN_F12R1_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l04011" name="l04011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e1bbde0fef2e2dab933da257a3afd66"> 4011</a></span><span class="preprocessor">#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l04012" name="l04012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9a6addc248c6db2118d1ce6e049d331"> 4012</a></span><span class="preprocessor">#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk </span></div>
|
||
<div class="line"><a id="l04013" name="l04013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89f3ef59e719e677cd850e299d9961a5"> 4013</a></span><span class="preprocessor">#define CAN_F12R1_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l04014" name="l04014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d988431331cf581558317c045e1117b"> 4014</a></span><span class="preprocessor">#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l04015" name="l04015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31d3a46845cd9ca6670472aae2aa2ebe"> 4015</a></span><span class="preprocessor">#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk </span></div>
|
||
<div class="line"><a id="l04016" name="l04016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0704718cb8d28fcbdb546e660b109e73"> 4016</a></span><span class="preprocessor">#define CAN_F12R1_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l04017" name="l04017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03b733b7cb7755ebe4678bf011a490f5"> 4017</a></span><span class="preprocessor">#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l04018" name="l04018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa06596dcbb545fbeea2ec20f629d9555"> 4018</a></span><span class="preprocessor">#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk </span></div>
|
||
<div class="line"><a id="l04019" name="l04019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b666278c8cbde1fda669c22af52c2ab"> 4019</a></span><span class="preprocessor">#define CAN_F12R1_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l04020" name="l04020"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47ce05849eef3967db74c9dcab8d936e"> 4020</a></span><span class="preprocessor">#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l04021" name="l04021"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac441b11b1be9b3608b9a09c2b8069722"> 4021</a></span><span class="preprocessor">#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk </span></div>
|
||
<div class="line"><a id="l04023" name="l04023"></a><span class="lineno"> 4023</span><span class="comment">/******************* Bit definition for CAN_F13R1 register ******************/</span></div>
|
||
<div class="line"><a id="l04024" name="l04024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02ab98a53a5893c727ea9957188ee26a"> 4024</a></span><span class="preprocessor">#define CAN_F13R1_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l04025" name="l04025"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0775804606cd66638da3f6ba1b3b493"> 4025</a></span><span class="preprocessor">#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l04026" name="l04026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa20d063950ad122a1965527a17d93c37"> 4026</a></span><span class="preprocessor">#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk </span></div>
|
||
<div class="line"><a id="l04027" name="l04027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35f9a2ceccf6229be57bb4145d593543"> 4027</a></span><span class="preprocessor">#define CAN_F13R1_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l04028" name="l04028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5af825390c54a3a65aac39d6a998ca48"> 4028</a></span><span class="preprocessor">#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l04029" name="l04029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf60decd61c8a8dc9e4342de8ad67ea76"> 4029</a></span><span class="preprocessor">#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk </span></div>
|
||
<div class="line"><a id="l04030" name="l04030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6613018ad3a9b1086f63172d3fa5322"> 4030</a></span><span class="preprocessor">#define CAN_F13R1_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l04031" name="l04031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34ca97bf95c63ac91fe0bbf664f96c5a"> 4031</a></span><span class="preprocessor">#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l04032" name="l04032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7863b3af06385d0e9037c57a5d2091e2"> 4032</a></span><span class="preprocessor">#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk </span></div>
|
||
<div class="line"><a id="l04033" name="l04033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38212e081d0a3d8b9b5384f034a5407a"> 4033</a></span><span class="preprocessor">#define CAN_F13R1_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l04034" name="l04034"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf217b9312083ea4fee7d1e808d6abb84"> 4034</a></span><span class="preprocessor">#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l04035" name="l04035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga043282b30813ce88dbdb320936ff6aca"> 4035</a></span><span class="preprocessor">#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk </span></div>
|
||
<div class="line"><a id="l04036" name="l04036"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdcbf72e68c8d4c217a3cc35c9a6a19d"> 4036</a></span><span class="preprocessor">#define CAN_F13R1_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l04037" name="l04037"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga325e27d4b7557c9da7685eaaefdd9bbe"> 4037</a></span><span class="preprocessor">#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l04038" name="l04038"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bbc9e9866f20d9d2f3cea1c6777c673"> 4038</a></span><span class="preprocessor">#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk </span></div>
|
||
<div class="line"><a id="l04039" name="l04039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6317c62241dd862ad43be5bd0ce74696"> 4039</a></span><span class="preprocessor">#define CAN_F13R1_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l04040" name="l04040"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53dda4ae54ad09328863f96688745173"> 4040</a></span><span class="preprocessor">#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l04041" name="l04041"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga885b36e017b013ab6deedd91d9ac2c66"> 4041</a></span><span class="preprocessor">#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk </span></div>
|
||
<div class="line"><a id="l04042" name="l04042"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga097998c68e6f03b713fe2eae37670c72"> 4042</a></span><span class="preprocessor">#define CAN_F13R1_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l04043" name="l04043"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae396c50fbe96dbdd418620ffd2fa5b4"> 4043</a></span><span class="preprocessor">#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l04044" name="l04044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa389b53582e5cacf326fff4512626d68"> 4044</a></span><span class="preprocessor">#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk </span></div>
|
||
<div class="line"><a id="l04045" name="l04045"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad30d6f9e145dbaf24c55480181072280"> 4045</a></span><span class="preprocessor">#define CAN_F13R1_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l04046" name="l04046"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0a54488273ee23a74dfe0a0deca7d7d"> 4046</a></span><span class="preprocessor">#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l04047" name="l04047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad09b75feeda08b16962db7da6a32dc9b"> 4047</a></span><span class="preprocessor">#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk </span></div>
|
||
<div class="line"><a id="l04048" name="l04048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b8cb9dd079a3116919ec1e48f3267b7"> 4048</a></span><span class="preprocessor">#define CAN_F13R1_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l04049" name="l04049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8c2421189d009e0b2630cf53f0caaf1"> 4049</a></span><span class="preprocessor">#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l04050" name="l04050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaba75675c019979882ecd8c6ef82d7a4"> 4050</a></span><span class="preprocessor">#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk </span></div>
|
||
<div class="line"><a id="l04051" name="l04051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd53ccc27879017d3a67b404b6cc2e8e"> 4051</a></span><span class="preprocessor">#define CAN_F13R1_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l04052" name="l04052"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa365ae887f59e0e1684a5ed96fb50042"> 4052</a></span><span class="preprocessor">#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l04053" name="l04053"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac579473f666edec0e0fcce278b642a9d"> 4053</a></span><span class="preprocessor">#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk </span></div>
|
||
<div class="line"><a id="l04054" name="l04054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25a6f5d5b2e92245427b68c7961e76c6"> 4054</a></span><span class="preprocessor">#define CAN_F13R1_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l04055" name="l04055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2439f107e699d239c00b630979ba87e1"> 4055</a></span><span class="preprocessor">#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l04056" name="l04056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14640c225c434428ef1870f462eb9bbd"> 4056</a></span><span class="preprocessor">#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk </span></div>
|
||
<div class="line"><a id="l04057" name="l04057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5f5353506ab2189b95cc97232c4fae4"> 4057</a></span><span class="preprocessor">#define CAN_F13R1_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l04058" name="l04058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9103107051eb07e5ae903489b76eb2c4"> 4058</a></span><span class="preprocessor">#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l04059" name="l04059"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d8c9f5879cc4e31fe2e63f82febbc69"> 4059</a></span><span class="preprocessor">#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk </span></div>
|
||
<div class="line"><a id="l04060" name="l04060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef2be27cb238beb59c18bdb3b874f96e"> 4060</a></span><span class="preprocessor">#define CAN_F13R1_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l04061" name="l04061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9dabd107a2de9ccd6461da5926e4d4e4"> 4061</a></span><span class="preprocessor">#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l04062" name="l04062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e0e3cfe033bb34f62312cfe47d1b84a"> 4062</a></span><span class="preprocessor">#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk </span></div>
|
||
<div class="line"><a id="l04063" name="l04063"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c3512eefb28504e6db269b9cd68202e"> 4063</a></span><span class="preprocessor">#define CAN_F13R1_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l04064" name="l04064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1db0ef6756bc958994e6fc702ce75b81"> 4064</a></span><span class="preprocessor">#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l04065" name="l04065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93d91a28c1ffca3f72f10e0b44040791"> 4065</a></span><span class="preprocessor">#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk </span></div>
|
||
<div class="line"><a id="l04066" name="l04066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac817b1dbf5b97572d61f4cb97ac35395"> 4066</a></span><span class="preprocessor">#define CAN_F13R1_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l04067" name="l04067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1412e4fcd6edb251cf356694de9f3f42"> 4067</a></span><span class="preprocessor">#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l04068" name="l04068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga355b438a5abccec89e13bdd00206b36f"> 4068</a></span><span class="preprocessor">#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk </span></div>
|
||
<div class="line"><a id="l04069" name="l04069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba2fba83e1654499f506bfe603b877a6"> 4069</a></span><span class="preprocessor">#define CAN_F13R1_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l04070" name="l04070"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cc8b54a2836661fdd482c004556cba1"> 4070</a></span><span class="preprocessor">#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l04071" name="l04071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89b23d147d2c040eb2317633b3ef46da"> 4071</a></span><span class="preprocessor">#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk </span></div>
|
||
<div class="line"><a id="l04072" name="l04072"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cdea57e0dff6ff19f5cc60f4307e25c"> 4072</a></span><span class="preprocessor">#define CAN_F13R1_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l04073" name="l04073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d570ecd25032c69017c3c117f0aebdf"> 4073</a></span><span class="preprocessor">#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l04074" name="l04074"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81d184cd46306fe24b46087a90e8f8f2"> 4074</a></span><span class="preprocessor">#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk </span></div>
|
||
<div class="line"><a id="l04075" name="l04075"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa862da872daa901ad2449731d9218b4d"> 4075</a></span><span class="preprocessor">#define CAN_F13R1_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l04076" name="l04076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef2321a184dc8aa13baef70a5cb6193f"> 4076</a></span><span class="preprocessor">#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l04077" name="l04077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga151a0e903046edc92bddcd0ef4a23449"> 4077</a></span><span class="preprocessor">#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk </span></div>
|
||
<div class="line"><a id="l04078" name="l04078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f93c38f644d676c7241d539765e044a"> 4078</a></span><span class="preprocessor">#define CAN_F13R1_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l04079" name="l04079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae27c24ba203819e140dfddb8bc05c473"> 4079</a></span><span class="preprocessor">#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l04080" name="l04080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e95e6d0d060fb2cfdf31e1b5fdfe3de"> 4080</a></span><span class="preprocessor">#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk </span></div>
|
||
<div class="line"><a id="l04081" name="l04081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga962217baf4c2af30fc495a0eb0b51879"> 4081</a></span><span class="preprocessor">#define CAN_F13R1_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l04082" name="l04082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga471095d382cce78017304b5db76f7a04"> 4082</a></span><span class="preprocessor">#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l04083" name="l04083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e0fb1cf032c57f954dd2679a05f8115"> 4083</a></span><span class="preprocessor">#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk </span></div>
|
||
<div class="line"><a id="l04084" name="l04084"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48c0363bcb1ee7fa09ecf22f6b94ed2a"> 4084</a></span><span class="preprocessor">#define CAN_F13R1_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l04085" name="l04085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c097cf8909e3cc7825d9500a891be52"> 4085</a></span><span class="preprocessor">#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l04086" name="l04086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb775bb1ded6a8f55f2a0849bec2eeac"> 4086</a></span><span class="preprocessor">#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk </span></div>
|
||
<div class="line"><a id="l04087" name="l04087"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga556fb1d9d20383d707a69806152d2571"> 4087</a></span><span class="preprocessor">#define CAN_F13R1_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l04088" name="l04088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3523d0b622d476255e22d07d76831a75"> 4088</a></span><span class="preprocessor">#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l04089" name="l04089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8743dfb60255d98911ea66605efd3b2f"> 4089</a></span><span class="preprocessor">#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk </span></div>
|
||
<div class="line"><a id="l04090" name="l04090"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec41136c74e99a37d9aca5c92ac9a93c"> 4090</a></span><span class="preprocessor">#define CAN_F13R1_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l04091" name="l04091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae50e71fdf75fcc3e59b95b855d3bf30a"> 4091</a></span><span class="preprocessor">#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l04092" name="l04092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54b067c38f3be3ad6041ea12fec15700"> 4092</a></span><span class="preprocessor">#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk </span></div>
|
||
<div class="line"><a id="l04093" name="l04093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7686cf2ffa6e927845c1064994c8d392"> 4093</a></span><span class="preprocessor">#define CAN_F13R1_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l04094" name="l04094"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45b6b1f5126bfa15739a086d6734cfd5"> 4094</a></span><span class="preprocessor">#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l04095" name="l04095"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00fe1942d9a8767a76f139bd74eafea0"> 4095</a></span><span class="preprocessor">#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk </span></div>
|
||
<div class="line"><a id="l04096" name="l04096"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab03f0061f54b4b410c91e61836225912"> 4096</a></span><span class="preprocessor">#define CAN_F13R1_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l04097" name="l04097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga710ae584f88078c05820eede3729b65c"> 4097</a></span><span class="preprocessor">#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l04098" name="l04098"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05db1c0a2e6e051d616b59f386dc7b1e"> 4098</a></span><span class="preprocessor">#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk </span></div>
|
||
<div class="line"><a id="l04099" name="l04099"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e9fea689cdeac8918508a183517d0db"> 4099</a></span><span class="preprocessor">#define CAN_F13R1_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l04100" name="l04100"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f2580d7250fa56c7a1e25f9d282c942"> 4100</a></span><span class="preprocessor">#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l04101" name="l04101"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66dd0da9fd8ef27b30f1ad56a9982caf"> 4101</a></span><span class="preprocessor">#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk </span></div>
|
||
<div class="line"><a id="l04102" name="l04102"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9eb77bfba6b6a7db4562bce8bb35316b"> 4102</a></span><span class="preprocessor">#define CAN_F13R1_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l04103" name="l04103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdd8f8b38bc3d56b97c8909c7dbb7560"> 4103</a></span><span class="preprocessor">#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l04104" name="l04104"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3b8381bc6ce5ab107cc1a92e565387a"> 4104</a></span><span class="preprocessor">#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk </span></div>
|
||
<div class="line"><a id="l04105" name="l04105"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb78e36a1d8975246d7437b4b3d8c0aa"> 4105</a></span><span class="preprocessor">#define CAN_F13R1_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l04106" name="l04106"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc69c07f91f2c9d6b85c3f26532fad1f"> 4106</a></span><span class="preprocessor">#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l04107" name="l04107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91c99de5ae099ecdee50ebd62e552df5"> 4107</a></span><span class="preprocessor">#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk </span></div>
|
||
<div class="line"><a id="l04108" name="l04108"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ab2ee1db50c027b505177c9b65af835"> 4108</a></span><span class="preprocessor">#define CAN_F13R1_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l04109" name="l04109"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1dd7a2e1000f7df336489982291d76d8"> 4109</a></span><span class="preprocessor">#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l04110" name="l04110"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83713f9e2c3c90f001ab378d9ca1f488"> 4110</a></span><span class="preprocessor">#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk </span></div>
|
||
<div class="line"><a id="l04111" name="l04111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9eed6320b23de2023e8c8ddeb7efaa1b"> 4111</a></span><span class="preprocessor">#define CAN_F13R1_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l04112" name="l04112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ed837627ac02698016cdf0439782fec"> 4112</a></span><span class="preprocessor">#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l04113" name="l04113"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga050fb1e9555d0d24f81682e194677684"> 4113</a></span><span class="preprocessor">#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk </span></div>
|
||
<div class="line"><a id="l04114" name="l04114"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86ba01c60b4b90ff0c58dab1c7e8bc6a"> 4114</a></span><span class="preprocessor">#define CAN_F13R1_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l04115" name="l04115"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e7f63726fd4dffa870717dbf3079be8"> 4115</a></span><span class="preprocessor">#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l04116" name="l04116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga761164856a25bc246396c7c82fdeb447"> 4116</a></span><span class="preprocessor">#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk </span></div>
|
||
<div class="line"><a id="l04117" name="l04117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa0459499e89cee6ff87bb40d6b6a0d7"> 4117</a></span><span class="preprocessor">#define CAN_F13R1_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l04118" name="l04118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad950a42557716b1e66d0e675d4ed0388"> 4118</a></span><span class="preprocessor">#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l04119" name="l04119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a750d71e94876d2f6e73a0e8b7217b2"> 4119</a></span><span class="preprocessor">#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk </span></div>
|
||
<div class="line"><a id="l04121" name="l04121"></a><span class="lineno"> 4121</span><span class="comment">/******************* Bit definition for CAN_F0R2 register *******************/</span></div>
|
||
<div class="line"><a id="l04122" name="l04122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f183a8e746831c98ca9cdb8eabe867b"> 4122</a></span><span class="preprocessor">#define CAN_F0R2_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l04123" name="l04123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa061083b9a300dcb531acbb0ca426943"> 4123</a></span><span class="preprocessor">#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l04124" name="l04124"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34282ddec559ecea4b613f2430334237"> 4124</a></span><span class="preprocessor">#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk </span></div>
|
||
<div class="line"><a id="l04125" name="l04125"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e70a04e0d25e9e87d225a66110b5a26"> 4125</a></span><span class="preprocessor">#define CAN_F0R2_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l04126" name="l04126"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95c94101334ccda880f2c3a2e9e35803"> 4126</a></span><span class="preprocessor">#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l04127" name="l04127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f23fc3814e0eb6af35c01e22c5dc6a7"> 4127</a></span><span class="preprocessor">#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk </span></div>
|
||
<div class="line"><a id="l04128" name="l04128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85d2b4b2c0ce324d0b1356c60cf63257"> 4128</a></span><span class="preprocessor">#define CAN_F0R2_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l04129" name="l04129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81d454ef34d31e40aeecb2da25e5004d"> 4129</a></span><span class="preprocessor">#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l04130" name="l04130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82ee32b6ec44d763b4364fa032d3439c"> 4130</a></span><span class="preprocessor">#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk </span></div>
|
||
<div class="line"><a id="l04131" name="l04131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad65a92a16e022fd160904677f2aa2232"> 4131</a></span><span class="preprocessor">#define CAN_F0R2_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l04132" name="l04132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga526563dd72eb6023c8c6b70ed3eef49f"> 4132</a></span><span class="preprocessor">#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l04133" name="l04133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7867b1d377088c63cdcc615932101997"> 4133</a></span><span class="preprocessor">#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk </span></div>
|
||
<div class="line"><a id="l04134" name="l04134"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34c12a03bd031d6e0f15091903bebca4"> 4134</a></span><span class="preprocessor">#define CAN_F0R2_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l04135" name="l04135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e2ad8285cf2dbc13f19cde26aa841ee"> 4135</a></span><span class="preprocessor">#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l04136" name="l04136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37fc5c9115eb669f1ac493b1c7296250"> 4136</a></span><span class="preprocessor">#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk </span></div>
|
||
<div class="line"><a id="l04137" name="l04137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e4adcc243dd4cd40a7221755e583c91"> 4137</a></span><span class="preprocessor">#define CAN_F0R2_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l04138" name="l04138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae572f8b4bb3bfa4dca31b1d4b189c277"> 4138</a></span><span class="preprocessor">#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l04139" name="l04139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae04b27aad09a3027f20a4eb48884c463"> 4139</a></span><span class="preprocessor">#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk </span></div>
|
||
<div class="line"><a id="l04140" name="l04140"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf319616807592f75d1a61ee9d8607265"> 4140</a></span><span class="preprocessor">#define CAN_F0R2_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l04141" name="l04141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d86d510a3fa0f7bb396b2535ff7412f"> 4141</a></span><span class="preprocessor">#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l04142" name="l04142"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae58d87c9513c11593041c3d43b955e8b"> 4142</a></span><span class="preprocessor">#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk </span></div>
|
||
<div class="line"><a id="l04143" name="l04143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e7fb85c2a88f84eb38d43bf730a11c1"> 4143</a></span><span class="preprocessor">#define CAN_F0R2_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l04144" name="l04144"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga931a307d0830015fa4494ed6a34e3fb5"> 4144</a></span><span class="preprocessor">#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l04145" name="l04145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03a6328d408b8015bb472c76f96a4dd8"> 4145</a></span><span class="preprocessor">#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk </span></div>
|
||
<div class="line"><a id="l04146" name="l04146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8dfb2cfa716e20ca94c9461d0c75dc1f"> 4146</a></span><span class="preprocessor">#define CAN_F0R2_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l04147" name="l04147"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f123f65007d2d150da67e5114b8354f"> 4147</a></span><span class="preprocessor">#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l04148" name="l04148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92fd1acf48665f966b670a0457456deb"> 4148</a></span><span class="preprocessor">#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk </span></div>
|
||
<div class="line"><a id="l04149" name="l04149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf66c4a2200af005c5035aca282158e29"> 4149</a></span><span class="preprocessor">#define CAN_F0R2_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l04150" name="l04150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31eeb8ac004bb1a829c442474a019b05"> 4150</a></span><span class="preprocessor">#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l04151" name="l04151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa853cff5493c4e857b7bb1ad28678ed4"> 4151</a></span><span class="preprocessor">#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk </span></div>
|
||
<div class="line"><a id="l04152" name="l04152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga228d943d2ac8c3e3ca52bcc68bdd0b71"> 4152</a></span><span class="preprocessor">#define CAN_F0R2_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l04153" name="l04153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb8eae7e6372cafdfbb97cee0d3a5906"> 4153</a></span><span class="preprocessor">#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l04154" name="l04154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa43bba65dd777c71e07130fde3fa6216"> 4154</a></span><span class="preprocessor">#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk </span></div>
|
||
<div class="line"><a id="l04155" name="l04155"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef610b498994f7ba1842966f9390548c"> 4155</a></span><span class="preprocessor">#define CAN_F0R2_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l04156" name="l04156"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15c19ccbf1f927445c99e0075e4743f4"> 4156</a></span><span class="preprocessor">#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l04157" name="l04157"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9077b9c35c6721d2a0e090a42af0eaaf"> 4157</a></span><span class="preprocessor">#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk </span></div>
|
||
<div class="line"><a id="l04158" name="l04158"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7158038c6c98cd727869fa152286ac06"> 4158</a></span><span class="preprocessor">#define CAN_F0R2_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l04159" name="l04159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec6f3f414927987a2409f6a4fcee1950"> 4159</a></span><span class="preprocessor">#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l04160" name="l04160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23af8df7d4e843a6e196b1542421ef45"> 4160</a></span><span class="preprocessor">#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk </span></div>
|
||
<div class="line"><a id="l04161" name="l04161"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0430b63b617ae1318cbb17291a67035"> 4161</a></span><span class="preprocessor">#define CAN_F0R2_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l04162" name="l04162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f965255e5ae450386165052ebc91266"> 4162</a></span><span class="preprocessor">#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l04163" name="l04163"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fe7776af3adce7d203aeb16d55d86d4"> 4163</a></span><span class="preprocessor">#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk </span></div>
|
||
<div class="line"><a id="l04164" name="l04164"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f653bbe8993cfe6546ea2947fe85837"> 4164</a></span><span class="preprocessor">#define CAN_F0R2_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l04165" name="l04165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga541cda96227f171eeaef984ec3f3bfde"> 4165</a></span><span class="preprocessor">#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l04166" name="l04166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81168efb90a776e44a96d1fe5e3b88c3"> 4166</a></span><span class="preprocessor">#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk </span></div>
|
||
<div class="line"><a id="l04167" name="l04167"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07875079d9eb2ea959eeec1f42e8e469"> 4167</a></span><span class="preprocessor">#define CAN_F0R2_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l04168" name="l04168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ec4acee70dd0bad3bcfb650e47f99b5"> 4168</a></span><span class="preprocessor">#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l04169" name="l04169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9708e7cde70a19e8e8fa33291e1b9d5"> 4169</a></span><span class="preprocessor">#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk </span></div>
|
||
<div class="line"><a id="l04170" name="l04170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7867b900606b53808ce9dbe518513e55"> 4170</a></span><span class="preprocessor">#define CAN_F0R2_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l04171" name="l04171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae046a3f26c0161e3c40dc1bc568db3b"> 4171</a></span><span class="preprocessor">#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l04172" name="l04172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2f2154c3030cebcfc3f1e4aed74fbf1"> 4172</a></span><span class="preprocessor">#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk </span></div>
|
||
<div class="line"><a id="l04173" name="l04173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f2272ba668cd632f30d77814bc8e465"> 4173</a></span><span class="preprocessor">#define CAN_F0R2_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l04174" name="l04174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06f28b2b9fdaaba93dd8268b5567a8ad"> 4174</a></span><span class="preprocessor">#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l04175" name="l04175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae87c14b75911aa0a9d0349d02d342711"> 4175</a></span><span class="preprocessor">#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk </span></div>
|
||
<div class="line"><a id="l04176" name="l04176"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad72df4766cb512aa607194c64484d9fb"> 4176</a></span><span class="preprocessor">#define CAN_F0R2_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l04177" name="l04177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga134eae58ad5e99cc09201e3f806390b2"> 4177</a></span><span class="preprocessor">#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l04178" name="l04178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fd7859cfc05300f68b175f520ddc31e"> 4178</a></span><span class="preprocessor">#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk </span></div>
|
||
<div class="line"><a id="l04179" name="l04179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga935ebc3c9dd606d36290e38c265ef7dc"> 4179</a></span><span class="preprocessor">#define CAN_F0R2_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l04180" name="l04180"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2288da969d823cf883f0a11d0e66db51"> 4180</a></span><span class="preprocessor">#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l04181" name="l04181"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaea36db8fcada46357137efeea256457"> 4181</a></span><span class="preprocessor">#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk </span></div>
|
||
<div class="line"><a id="l04182" name="l04182"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga392416946fa28a09ba37f510aa39ee2f"> 4182</a></span><span class="preprocessor">#define CAN_F0R2_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l04183" name="l04183"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e695a429859e9c143330c5cf6ad3229"> 4183</a></span><span class="preprocessor">#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l04184" name="l04184"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57872dcfea1f8a56170640842edf9c1a"> 4184</a></span><span class="preprocessor">#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk </span></div>
|
||
<div class="line"><a id="l04185" name="l04185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac77ccf85d70f580674fcce170c086071"> 4185</a></span><span class="preprocessor">#define CAN_F0R2_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l04186" name="l04186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b4a66ffe52286fd25f6bb36fa2e6f21"> 4186</a></span><span class="preprocessor">#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l04187" name="l04187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc01e7f26d0e85da93ca78d0d71a4fed"> 4187</a></span><span class="preprocessor">#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk </span></div>
|
||
<div class="line"><a id="l04188" name="l04188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7de0dedff4a0a111022b7f750c52d8a9"> 4188</a></span><span class="preprocessor">#define CAN_F0R2_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l04189" name="l04189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d02ac9f9a07b7c47059c84a2b0782ee"> 4189</a></span><span class="preprocessor">#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l04190" name="l04190"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07d8c3c8c3eb3c97b5979388c548e2fc"> 4190</a></span><span class="preprocessor">#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk </span></div>
|
||
<div class="line"><a id="l04191" name="l04191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46768113fa95f91e263d6a4b62cffdd3"> 4191</a></span><span class="preprocessor">#define CAN_F0R2_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l04192" name="l04192"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cd190536d4b825b086f682b40886f7f"> 4192</a></span><span class="preprocessor">#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l04193" name="l04193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade31bd75624afeaef9b5ab45a5057db9"> 4193</a></span><span class="preprocessor">#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk </span></div>
|
||
<div class="line"><a id="l04194" name="l04194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c235ae356a2cce22c4c3a46099e3395"> 4194</a></span><span class="preprocessor">#define CAN_F0R2_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l04195" name="l04195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49d6929299df0a13244f0e7958eb711a"> 4195</a></span><span class="preprocessor">#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l04196" name="l04196"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa78ff8fcfe0f14655aaf94ecc92d7532"> 4196</a></span><span class="preprocessor">#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk </span></div>
|
||
<div class="line"><a id="l04197" name="l04197"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc439d9206a0fe829811ba950c98cbb7"> 4197</a></span><span class="preprocessor">#define CAN_F0R2_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l04198" name="l04198"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf6e6acb5b23357732909d4bec0eb95e"> 4198</a></span><span class="preprocessor">#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l04199" name="l04199"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad577ebd9a8cedd1b8b13d5a41d2fbab"> 4199</a></span><span class="preprocessor">#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk </span></div>
|
||
<div class="line"><a id="l04200" name="l04200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3102f1fa9437f6fcd9fa4a51074a837d"> 4200</a></span><span class="preprocessor">#define CAN_F0R2_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l04201" name="l04201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0c77950c4ec1c45ab5c4c2936186d36"> 4201</a></span><span class="preprocessor">#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l04202" name="l04202"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab814105bcd2a2c636c26197b21ead2b0"> 4202</a></span><span class="preprocessor">#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk </span></div>
|
||
<div class="line"><a id="l04203" name="l04203"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf09a3ca077d2274a12ecbf0f8d0aab6"> 4203</a></span><span class="preprocessor">#define CAN_F0R2_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l04204" name="l04204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47a37ea3a0bc9d4232ee89f18782ff53"> 4204</a></span><span class="preprocessor">#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l04205" name="l04205"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea82daeaa71ecddb187613df9517e51c"> 4205</a></span><span class="preprocessor">#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk </span></div>
|
||
<div class="line"><a id="l04206" name="l04206"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90c21de25c1da4b3a3c5715e6212c1e9"> 4206</a></span><span class="preprocessor">#define CAN_F0R2_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l04207" name="l04207"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfb99d019f1abf788685338176fa8595"> 4207</a></span><span class="preprocessor">#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l04208" name="l04208"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef5036edf5bd310e5e06f3ea5cb818a2"> 4208</a></span><span class="preprocessor">#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk </span></div>
|
||
<div class="line"><a id="l04209" name="l04209"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga168f5225f2ca892513f4d58e7c348c58"> 4209</a></span><span class="preprocessor">#define CAN_F0R2_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l04210" name="l04210"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga875a0587956149206e0df84242e5c38a"> 4210</a></span><span class="preprocessor">#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l04211" name="l04211"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0c2db96ddbcfa1b838c283e20ca554b"> 4211</a></span><span class="preprocessor">#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk </span></div>
|
||
<div class="line"><a id="l04212" name="l04212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac273be775b429ef41f46885be62c040d"> 4212</a></span><span class="preprocessor">#define CAN_F0R2_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l04213" name="l04213"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ee59bc46345bde430c9ecf20c8df7a2"> 4213</a></span><span class="preprocessor">#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l04214" name="l04214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5afb46a2d4ccb3f28e8579b26e2b2e2e"> 4214</a></span><span class="preprocessor">#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk </span></div>
|
||
<div class="line"><a id="l04215" name="l04215"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa39384b9da02ee18353528a10b08920"> 4215</a></span><span class="preprocessor">#define CAN_F0R2_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l04216" name="l04216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90f146c0436009e8b77597db4f06dc88"> 4216</a></span><span class="preprocessor">#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l04217" name="l04217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ace83e798931f35c123507e1ef59fbb"> 4217</a></span><span class="preprocessor">#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk </span></div>
|
||
<div class="line"><a id="l04219" name="l04219"></a><span class="lineno"> 4219</span><span class="comment">/******************* Bit definition for CAN_F1R2 register *******************/</span></div>
|
||
<div class="line"><a id="l04220" name="l04220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0dec2c89cd678f3fd1fa90ba991c77c8"> 4220</a></span><span class="preprocessor">#define CAN_F1R2_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l04221" name="l04221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac37390e12fa87a072599d57c581f82b1"> 4221</a></span><span class="preprocessor">#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l04222" name="l04222"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ea3c5d8ab8962d9cd0e2b067167d3d4"> 4222</a></span><span class="preprocessor">#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk </span></div>
|
||
<div class="line"><a id="l04223" name="l04223"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6841efe21767654ecaee1bb96755970"> 4223</a></span><span class="preprocessor">#define CAN_F1R2_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l04224" name="l04224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f4652769a8b81aefaa5acbaddc83e47"> 4224</a></span><span class="preprocessor">#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l04225" name="l04225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfa5449488e7330d8f11f75fcf3e75cd"> 4225</a></span><span class="preprocessor">#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk </span></div>
|
||
<div class="line"><a id="l04226" name="l04226"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga622010c50665f9ae395641902d1834d4"> 4226</a></span><span class="preprocessor">#define CAN_F1R2_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l04227" name="l04227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga550988821dc17b71e58d745367d552fb"> 4227</a></span><span class="preprocessor">#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l04228" name="l04228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe49a3e224459f1bd9b3279ebfa8803b"> 4228</a></span><span class="preprocessor">#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk </span></div>
|
||
<div class="line"><a id="l04229" name="l04229"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24e392fb487c7c70667c53e868bd8ec7"> 4229</a></span><span class="preprocessor">#define CAN_F1R2_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l04230" name="l04230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad52c7978074227730285d698cdcb15c7"> 4230</a></span><span class="preprocessor">#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l04231" name="l04231"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77cf2217ec29e2043bada827249dedd5"> 4231</a></span><span class="preprocessor">#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk </span></div>
|
||
<div class="line"><a id="l04232" name="l04232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga937b036cc35761691dae4719da547038"> 4232</a></span><span class="preprocessor">#define CAN_F1R2_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l04233" name="l04233"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab404d9e8cd80526beb5b83ea62236c40"> 4233</a></span><span class="preprocessor">#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l04234" name="l04234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf35643f0148ed0f93e3ba52e95a4cf6b"> 4234</a></span><span class="preprocessor">#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk </span></div>
|
||
<div class="line"><a id="l04235" name="l04235"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9021382fb04157c3a4ea991a1a0d654"> 4235</a></span><span class="preprocessor">#define CAN_F1R2_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l04236" name="l04236"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3210b70ca25333f077035c8178683b3c"> 4236</a></span><span class="preprocessor">#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l04237" name="l04237"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae08798adabd9cc0fb2b07eaff6444878"> 4237</a></span><span class="preprocessor">#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk </span></div>
|
||
<div class="line"><a id="l04238" name="l04238"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga282ffe71282dcacb6bd4a49da646a7ae"> 4238</a></span><span class="preprocessor">#define CAN_F1R2_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l04239" name="l04239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab840206e4408eeadf35ca5ce492121b7"> 4239</a></span><span class="preprocessor">#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l04240" name="l04240"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06659c9a418d7f4a8729d87bc397be23"> 4240</a></span><span class="preprocessor">#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk </span></div>
|
||
<div class="line"><a id="l04241" name="l04241"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34ffa785ed1b4ab61dfcb4e5d203ec57"> 4241</a></span><span class="preprocessor">#define CAN_F1R2_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l04242" name="l04242"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93f9f5471e1a8abd2ca55fe5a4cf120f"> 4242</a></span><span class="preprocessor">#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l04243" name="l04243"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36bb9ca8dadd6714052f8d31cb01cb7b"> 4243</a></span><span class="preprocessor">#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk </span></div>
|
||
<div class="line"><a id="l04244" name="l04244"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83f47b48b80736f5526b826a9150e32a"> 4244</a></span><span class="preprocessor">#define CAN_F1R2_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l04245" name="l04245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade520b46b08abd462743828dfdb211e1"> 4245</a></span><span class="preprocessor">#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l04246" name="l04246"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d400044261146be3deb722d9cf3d5c1"> 4246</a></span><span class="preprocessor">#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk </span></div>
|
||
<div class="line"><a id="l04247" name="l04247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5018a74c3736b3246b93e642100f1d9"> 4247</a></span><span class="preprocessor">#define CAN_F1R2_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l04248" name="l04248"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28e355feec329b328d200ea79a3c4e73"> 4248</a></span><span class="preprocessor">#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l04249" name="l04249"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3e5769ea8faaed16c6cb2ce979d28a9"> 4249</a></span><span class="preprocessor">#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk </span></div>
|
||
<div class="line"><a id="l04250" name="l04250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4282afc9cf64def8be2dfe7cab903113"> 4250</a></span><span class="preprocessor">#define CAN_F1R2_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l04251" name="l04251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4fa9a6d11d4066ce8cbed7772e5c4c1"> 4251</a></span><span class="preprocessor">#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l04252" name="l04252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga915236a6b5081c2c30bd4d49144bc463"> 4252</a></span><span class="preprocessor">#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk </span></div>
|
||
<div class="line"><a id="l04253" name="l04253"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga796f12ffae3a26f7e0211f55db51da75"> 4253</a></span><span class="preprocessor">#define CAN_F1R2_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l04254" name="l04254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1aef88c920add1bcec693ba43f890cf"> 4254</a></span><span class="preprocessor">#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l04255" name="l04255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf1aa2e62d4eede199196f81795d309c"> 4255</a></span><span class="preprocessor">#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk </span></div>
|
||
<div class="line"><a id="l04256" name="l04256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4000100330d542f8d6375d4ccd450d6d"> 4256</a></span><span class="preprocessor">#define CAN_F1R2_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l04257" name="l04257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4486004019a70c1c41822611cfbc24a7"> 4257</a></span><span class="preprocessor">#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l04258" name="l04258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7db0ae3dcaab35e4c496c8a800b5c994"> 4258</a></span><span class="preprocessor">#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk </span></div>
|
||
<div class="line"><a id="l04259" name="l04259"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadc9998290934d01441ce5d05b335868"> 4259</a></span><span class="preprocessor">#define CAN_F1R2_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l04260" name="l04260"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32ef2954ebc503eaf6c44eb4ec9a593e"> 4260</a></span><span class="preprocessor">#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l04261" name="l04261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02cdb71c56a5d9994ecd2dee668c7184"> 4261</a></span><span class="preprocessor">#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk </span></div>
|
||
<div class="line"><a id="l04262" name="l04262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga412671533d237ac1b2abce675e53e41e"> 4262</a></span><span class="preprocessor">#define CAN_F1R2_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l04263" name="l04263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace28daab139f94dc2ed7e388fd1b9b59"> 4263</a></span><span class="preprocessor">#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l04264" name="l04264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac66691ca840db6c861460d311a942a87"> 4264</a></span><span class="preprocessor">#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk </span></div>
|
||
<div class="line"><a id="l04265" name="l04265"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2face19f24a4459fc7aff4ca49fcb300"> 4265</a></span><span class="preprocessor">#define CAN_F1R2_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l04266" name="l04266"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbb0a0b5dd87d593fc1cf8b9269bf365"> 4266</a></span><span class="preprocessor">#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l04267" name="l04267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabcdd57022e26859db1f81f2df08c8725"> 4267</a></span><span class="preprocessor">#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk </span></div>
|
||
<div class="line"><a id="l04268" name="l04268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4e63a8d7f11fab2b9970eb9402164a1"> 4268</a></span><span class="preprocessor">#define CAN_F1R2_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l04269" name="l04269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga427c05edd87c70fb5bfede3ece583106"> 4269</a></span><span class="preprocessor">#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l04270" name="l04270"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga211795b36769a0b87044f0d82a7a72b1"> 4270</a></span><span class="preprocessor">#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk </span></div>
|
||
<div class="line"><a id="l04271" name="l04271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5972a3d5d5b18772e834e3f56e6d3b1"> 4271</a></span><span class="preprocessor">#define CAN_F1R2_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l04272" name="l04272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e7423c9dd0740125ba2dc7a9068c449"> 4272</a></span><span class="preprocessor">#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l04273" name="l04273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc8c427731f33c76fad0873bb29a4b4c"> 4273</a></span><span class="preprocessor">#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk </span></div>
|
||
<div class="line"><a id="l04274" name="l04274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5916963935ba1112457ff7f497a3105"> 4274</a></span><span class="preprocessor">#define CAN_F1R2_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l04275" name="l04275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcea3b8cd42bcc687c67e62a0ccf7471"> 4275</a></span><span class="preprocessor">#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l04276" name="l04276"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10a3e6be9968b8007562e7afe6b3b342"> 4276</a></span><span class="preprocessor">#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk </span></div>
|
||
<div class="line"><a id="l04277" name="l04277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga925a99e3a206a826cc1abf0bd4adb42f"> 4277</a></span><span class="preprocessor">#define CAN_F1R2_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l04278" name="l04278"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3e119637508ebc998e04873befdea02"> 4278</a></span><span class="preprocessor">#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l04279" name="l04279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4aac6ab4bd4cdeecbe621adf1d11b95a"> 4279</a></span><span class="preprocessor">#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk </span></div>
|
||
<div class="line"><a id="l04280" name="l04280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fe55799241f27062746e57409e2e9f4"> 4280</a></span><span class="preprocessor">#define CAN_F1R2_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l04281" name="l04281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6adb312018dfbe719072be0d6444b62a"> 4281</a></span><span class="preprocessor">#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l04282" name="l04282"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30140ced3da0d0a526c4f4f5881987c1"> 4282</a></span><span class="preprocessor">#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk </span></div>
|
||
<div class="line"><a id="l04283" name="l04283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfa97c392ee8e456dd9ffd6498590c11"> 4283</a></span><span class="preprocessor">#define CAN_F1R2_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l04284" name="l04284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23a75816e8e01c5c9a90d7b2afa4716f"> 4284</a></span><span class="preprocessor">#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l04285" name="l04285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49f36aec2e851ed18c5a382a0708bbcb"> 4285</a></span><span class="preprocessor">#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk </span></div>
|
||
<div class="line"><a id="l04286" name="l04286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga948b363bcf4905731e758e1353c58bde"> 4286</a></span><span class="preprocessor">#define CAN_F1R2_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l04287" name="l04287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace263ed2b1dcb26232c8be718c733490"> 4287</a></span><span class="preprocessor">#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l04288" name="l04288"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99ccab06a8a97616a2fc3e026f36351d"> 4288</a></span><span class="preprocessor">#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk </span></div>
|
||
<div class="line"><a id="l04289" name="l04289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga166035cac78d72360b8019ede0ec3bf7"> 4289</a></span><span class="preprocessor">#define CAN_F1R2_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l04290" name="l04290"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15089c114f7120bd834ecddd74795989"> 4290</a></span><span class="preprocessor">#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l04291" name="l04291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa408889ff6478d6558d4c53c9114bde"> 4291</a></span><span class="preprocessor">#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk </span></div>
|
||
<div class="line"><a id="l04292" name="l04292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b63bc70f339f5773288cb786e9c4459"> 4292</a></span><span class="preprocessor">#define CAN_F1R2_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l04293" name="l04293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga256936e5e1dc313a5846bcdb38746940"> 4293</a></span><span class="preprocessor">#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l04294" name="l04294"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga032dd8dc11aa9013cc0e824e31932951"> 4294</a></span><span class="preprocessor">#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk </span></div>
|
||
<div class="line"><a id="l04295" name="l04295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5bd608220a283001eb3e0739c4b9971"> 4295</a></span><span class="preprocessor">#define CAN_F1R2_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l04296" name="l04296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8861d429f3e5a4cf24015dd24d1035a2"> 4296</a></span><span class="preprocessor">#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l04297" name="l04297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76f29020524ec6403a40de4e260a2ea8"> 4297</a></span><span class="preprocessor">#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk </span></div>
|
||
<div class="line"><a id="l04298" name="l04298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga244707ad262266c922ff70945babc147"> 4298</a></span><span class="preprocessor">#define CAN_F1R2_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l04299" name="l04299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaca03affd919dc4618d7e47f545714fe"> 4299</a></span><span class="preprocessor">#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l04300" name="l04300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bb51cd27fea671be51a59ce7a83008e"> 4300</a></span><span class="preprocessor">#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk </span></div>
|
||
<div class="line"><a id="l04301" name="l04301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cee8ad67d0accf75e5808747e189153"> 4301</a></span><span class="preprocessor">#define CAN_F1R2_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l04302" name="l04302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4685d281238d461eb78b7f846411f6f3"> 4302</a></span><span class="preprocessor">#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l04303" name="l04303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga085c38b511aa4895b6c939a06070c916"> 4303</a></span><span class="preprocessor">#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk </span></div>
|
||
<div class="line"><a id="l04304" name="l04304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28c98f10f41c0d71c4d462d4d12dfa66"> 4304</a></span><span class="preprocessor">#define CAN_F1R2_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l04305" name="l04305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a6e9dc7e9d061ce75e04aceae3cfd6b"> 4305</a></span><span class="preprocessor">#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l04306" name="l04306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe299378c771da8d7d8e72a6f6e41f7f"> 4306</a></span><span class="preprocessor">#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk </span></div>
|
||
<div class="line"><a id="l04307" name="l04307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae336a2f0d44c4ca3a991014f28c2bdff"> 4307</a></span><span class="preprocessor">#define CAN_F1R2_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l04308" name="l04308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fee7c49b899c8af5ae4b60d47461ea2"> 4308</a></span><span class="preprocessor">#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l04309" name="l04309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabc8bef79b09bcfcb0df6ba467ed906b"> 4309</a></span><span class="preprocessor">#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk </span></div>
|
||
<div class="line"><a id="l04310" name="l04310"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga461e28c08af3e31dacf1b1cd7b8ffcc4"> 4310</a></span><span class="preprocessor">#define CAN_F1R2_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l04311" name="l04311"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab87ec718cd11264085752c85b44e6ef3"> 4311</a></span><span class="preprocessor">#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l04312" name="l04312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc4aba2c95f27229987d9eb4cda9890c"> 4312</a></span><span class="preprocessor">#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk </span></div>
|
||
<div class="line"><a id="l04313" name="l04313"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe23be59ff4543be1a357b9bc235ac6e"> 4313</a></span><span class="preprocessor">#define CAN_F1R2_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l04314" name="l04314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9cebad85393ecc2a9214f9788b77c676"> 4314</a></span><span class="preprocessor">#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l04315" name="l04315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21cbfc217d67062d265753964c871065"> 4315</a></span><span class="preprocessor">#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk </span></div>
|
||
<div class="line"><a id="l04317" name="l04317"></a><span class="lineno"> 4317</span><span class="comment">/******************* Bit definition for CAN_F2R2 register *******************/</span></div>
|
||
<div class="line"><a id="l04318" name="l04318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf63fb260c0953b77b1c331f22f38ba67"> 4318</a></span><span class="preprocessor">#define CAN_F2R2_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l04319" name="l04319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4399948716780ec8c4dd96270469843"> 4319</a></span><span class="preprocessor">#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l04320" name="l04320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36964e4bf6aa10467b3d95781da56814"> 4320</a></span><span class="preprocessor">#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk </span></div>
|
||
<div class="line"><a id="l04321" name="l04321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8f29d00c90b617c2336012358753e59"> 4321</a></span><span class="preprocessor">#define CAN_F2R2_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l04322" name="l04322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad77d91c1c72f554e0e99650a3f47e737"> 4322</a></span><span class="preprocessor">#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l04323" name="l04323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d0541eb1a4f8ae0afe429ac0757de6a"> 4323</a></span><span class="preprocessor">#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk </span></div>
|
||
<div class="line"><a id="l04324" name="l04324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ac519efc7774827b8a0acf9c6d84d6e"> 4324</a></span><span class="preprocessor">#define CAN_F2R2_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l04325" name="l04325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96dff14e0209cd48bf0c29dc53ede26b"> 4325</a></span><span class="preprocessor">#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l04326" name="l04326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14fd5aff8767df509b396190ddf7fa28"> 4326</a></span><span class="preprocessor">#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk </span></div>
|
||
<div class="line"><a id="l04327" name="l04327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace335e7b5360756df41deae31f2abe97"> 4327</a></span><span class="preprocessor">#define CAN_F2R2_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l04328" name="l04328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f3b7ec530ba7d4f3effd0c42ab49ca9"> 4328</a></span><span class="preprocessor">#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l04329" name="l04329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7283e2a71983078144fa9a8e5ae563a9"> 4329</a></span><span class="preprocessor">#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk </span></div>
|
||
<div class="line"><a id="l04330" name="l04330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0ff06cee35fcd839c589a9354debd14"> 4330</a></span><span class="preprocessor">#define CAN_F2R2_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l04331" name="l04331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbcaf819adc61da902e94fc549c5eca7"> 4331</a></span><span class="preprocessor">#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l04332" name="l04332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeba1324d32b084c477a0ece7b904a4cd"> 4332</a></span><span class="preprocessor">#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk </span></div>
|
||
<div class="line"><a id="l04333" name="l04333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff548790426c82595b210472f7962e60"> 4333</a></span><span class="preprocessor">#define CAN_F2R2_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l04334" name="l04334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb028302ad008b6326533727d4fb75b0"> 4334</a></span><span class="preprocessor">#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l04335" name="l04335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a367cf9f2f7e604e9f5e30b5ed30779"> 4335</a></span><span class="preprocessor">#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk </span></div>
|
||
<div class="line"><a id="l04336" name="l04336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8d334bdd60f7c353f3be0e0f43ab068"> 4336</a></span><span class="preprocessor">#define CAN_F2R2_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l04337" name="l04337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d23fc25f4bfb50a6f590e31e11c4838"> 4337</a></span><span class="preprocessor">#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l04338" name="l04338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b92ac9785e2f7c890130e9b7d792c79"> 4338</a></span><span class="preprocessor">#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk </span></div>
|
||
<div class="line"><a id="l04339" name="l04339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f1f47aa543e3b89fd13f489408ca8a4"> 4339</a></span><span class="preprocessor">#define CAN_F2R2_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l04340" name="l04340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42c27ede1b3c0ad55b1d3ceeb774abbd"> 4340</a></span><span class="preprocessor">#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l04341" name="l04341"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac969a33d20353d5cd7fb317f5fa71138"> 4341</a></span><span class="preprocessor">#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk </span></div>
|
||
<div class="line"><a id="l04342" name="l04342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3338bc9837ac1f00d007a2ae6d79f27f"> 4342</a></span><span class="preprocessor">#define CAN_F2R2_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l04343" name="l04343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaace122156ecd18b6abea1a5f23e1cfce"> 4343</a></span><span class="preprocessor">#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l04344" name="l04344"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafeaac84fa5eec0173c531e9940327f86"> 4344</a></span><span class="preprocessor">#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk </span></div>
|
||
<div class="line"><a id="l04345" name="l04345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c4389614bb6ca7bd50b0a72d6e6dd90"> 4345</a></span><span class="preprocessor">#define CAN_F2R2_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l04346" name="l04346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95a5442d9fc437bc2acdf878279cf7c6"> 4346</a></span><span class="preprocessor">#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l04347" name="l04347"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga532413ea309fa031e65397a5b31ac92c"> 4347</a></span><span class="preprocessor">#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk </span></div>
|
||
<div class="line"><a id="l04348" name="l04348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5fd8ddf4d48ae6b4b8375791a9fe081"> 4348</a></span><span class="preprocessor">#define CAN_F2R2_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l04349" name="l04349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebf3a00b21dc2a665b2e8e7b99cefaae"> 4349</a></span><span class="preprocessor">#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l04350" name="l04350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga360e02860472400a9000ef2fc8ba7bb1"> 4350</a></span><span class="preprocessor">#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk </span></div>
|
||
<div class="line"><a id="l04351" name="l04351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62d108467a53b2dd5992d6bde9ed771e"> 4351</a></span><span class="preprocessor">#define CAN_F2R2_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l04352" name="l04352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb77bebe0b062fe55efc6304cf8840b4"> 4352</a></span><span class="preprocessor">#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l04353" name="l04353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c917a5b5e1a010229caaa5b3a41d7a6"> 4353</a></span><span class="preprocessor">#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk </span></div>
|
||
<div class="line"><a id="l04354" name="l04354"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga831b9df6d417ca891d10d42826a7412d"> 4354</a></span><span class="preprocessor">#define CAN_F2R2_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l04355" name="l04355"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04dd0cb91d888b98351e33516a4547e1"> 4355</a></span><span class="preprocessor">#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l04356" name="l04356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0956873246e63b41c0a640bc8d117319"> 4356</a></span><span class="preprocessor">#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk </span></div>
|
||
<div class="line"><a id="l04357" name="l04357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a22208eb5078a7bfc81c4d9425d3768"> 4357</a></span><span class="preprocessor">#define CAN_F2R2_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l04358" name="l04358"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f6af8fc2890a6b457435f0ab29908e4"> 4358</a></span><span class="preprocessor">#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l04359" name="l04359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53202218de27d073d577c27427fe0cbe"> 4359</a></span><span class="preprocessor">#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk </span></div>
|
||
<div class="line"><a id="l04360" name="l04360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa084d675b30eec4c52eda4e06ef7e79"> 4360</a></span><span class="preprocessor">#define CAN_F2R2_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l04361" name="l04361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7f01b289ae8ae3eecedd8a29ddc1eb1"> 4361</a></span><span class="preprocessor">#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l04362" name="l04362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga960a1ffd4b153168494d91df69e30742"> 4362</a></span><span class="preprocessor">#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk </span></div>
|
||
<div class="line"><a id="l04363" name="l04363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga956077f7bdb372a7bf0c608b13c8f7f8"> 4363</a></span><span class="preprocessor">#define CAN_F2R2_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l04364" name="l04364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c79b4445a4d0eb87b2121d58c73d9bc"> 4364</a></span><span class="preprocessor">#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l04365" name="l04365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc81e9ab9ab926d1ca30c5b6060a126b"> 4365</a></span><span class="preprocessor">#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk </span></div>
|
||
<div class="line"><a id="l04366" name="l04366"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcb245f4a5552692ce95229e29c99b1d"> 4366</a></span><span class="preprocessor">#define CAN_F2R2_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l04367" name="l04367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ae7788f7206aca6e83ba0cd081af5b2"> 4367</a></span><span class="preprocessor">#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l04368" name="l04368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5f9a5279398454a3a2493b3e1783f52"> 4368</a></span><span class="preprocessor">#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk </span></div>
|
||
<div class="line"><a id="l04369" name="l04369"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e7149f9b6d387983aa9cfddda59c1ac"> 4369</a></span><span class="preprocessor">#define CAN_F2R2_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l04370" name="l04370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0d302da92dc7ff48bfb3935a739c56f"> 4370</a></span><span class="preprocessor">#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l04371" name="l04371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0275ec7527a223a33289118f9e0a2edd"> 4371</a></span><span class="preprocessor">#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk </span></div>
|
||
<div class="line"><a id="l04372" name="l04372"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67d39926ab846913f9cc5a077ab2451a"> 4372</a></span><span class="preprocessor">#define CAN_F2R2_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l04373" name="l04373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ee8abd5207088cb6f59a3fd5af3b89a"> 4373</a></span><span class="preprocessor">#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l04374" name="l04374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34028a240868ca7dd365ce98e31e84ca"> 4374</a></span><span class="preprocessor">#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk </span></div>
|
||
<div class="line"><a id="l04375" name="l04375"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga711201f0da7b487c7111c4e587f84d12"> 4375</a></span><span class="preprocessor">#define CAN_F2R2_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l04376" name="l04376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6ad53d41a895d341e102901c2e4113b"> 4376</a></span><span class="preprocessor">#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l04377" name="l04377"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga807cfa122b6c74d85fdab233dd9ed502"> 4377</a></span><span class="preprocessor">#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk </span></div>
|
||
<div class="line"><a id="l04378" name="l04378"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2664848f3b5f6f02d916a85c2995377e"> 4378</a></span><span class="preprocessor">#define CAN_F2R2_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l04379" name="l04379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6b747f768a440c5e8fe08febc1d0683"> 4379</a></span><span class="preprocessor">#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l04380" name="l04380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1187f1ab7514c90af34b44eff80858fa"> 4380</a></span><span class="preprocessor">#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk </span></div>
|
||
<div class="line"><a id="l04381" name="l04381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga803f8529db84971c2b5c425cf5ece37b"> 4381</a></span><span class="preprocessor">#define CAN_F2R2_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l04382" name="l04382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc046157f775cb1a2c5b2b90aa15d745"> 4382</a></span><span class="preprocessor">#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l04383" name="l04383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacecb18e779a44989b724901f6c2af84f"> 4383</a></span><span class="preprocessor">#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk </span></div>
|
||
<div class="line"><a id="l04384" name="l04384"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga007e6dcd0caab8184192fb9780535e88"> 4384</a></span><span class="preprocessor">#define CAN_F2R2_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l04385" name="l04385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23fdd1fa55e6729712aad51a2ce62834"> 4385</a></span><span class="preprocessor">#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l04386" name="l04386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f2a6017895d8d139dcbc3d0e6e69e69"> 4386</a></span><span class="preprocessor">#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk </span></div>
|
||
<div class="line"><a id="l04387" name="l04387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ed215ff7fa7ffdb6fe61431c3634a53"> 4387</a></span><span class="preprocessor">#define CAN_F2R2_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l04388" name="l04388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4508040a17ba6d514e9c5db40131a196"> 4388</a></span><span class="preprocessor">#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l04389" name="l04389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaceff2f283cbd4935ec5d45ceaa18efe0"> 4389</a></span><span class="preprocessor">#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk </span></div>
|
||
<div class="line"><a id="l04390" name="l04390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga838adce88b9370f7a2559bbb2ce268ce"> 4390</a></span><span class="preprocessor">#define CAN_F2R2_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l04391" name="l04391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae17fde946459dc3fc90da9e8809d6d05"> 4391</a></span><span class="preprocessor">#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l04392" name="l04392"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3086667a209f91ed6d6b496b83111044"> 4392</a></span><span class="preprocessor">#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk </span></div>
|
||
<div class="line"><a id="l04393" name="l04393"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93be5f2dee61eb1a67711f9037864725"> 4393</a></span><span class="preprocessor">#define CAN_F2R2_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l04394" name="l04394"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03da1089ea38abbe1093471a67a971fa"> 4394</a></span><span class="preprocessor">#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l04395" name="l04395"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c8c7b240bb0dd2a3ec8b6c4c25af7ba"> 4395</a></span><span class="preprocessor">#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk </span></div>
|
||
<div class="line"><a id="l04396" name="l04396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b2487dff59abf0a4aff74d5a8e5bf85"> 4396</a></span><span class="preprocessor">#define CAN_F2R2_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l04397" name="l04397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacef46477e39c33367b4cc071c1e3fc69"> 4397</a></span><span class="preprocessor">#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l04398" name="l04398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51498379a1e3b81a83bf8d164c4f7e5e"> 4398</a></span><span class="preprocessor">#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk </span></div>
|
||
<div class="line"><a id="l04399" name="l04399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7470e371f95c91d7222c919e63d3c92f"> 4399</a></span><span class="preprocessor">#define CAN_F2R2_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l04400" name="l04400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga833458f427d74480b7a400ace687432e"> 4400</a></span><span class="preprocessor">#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l04401" name="l04401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1f78e7c530a3ef26d44b9353fa9ee36"> 4401</a></span><span class="preprocessor">#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk </span></div>
|
||
<div class="line"><a id="l04402" name="l04402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7bc089024482b8555fc44374c3ff5bc"> 4402</a></span><span class="preprocessor">#define CAN_F2R2_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l04403" name="l04403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc909d367700acef6e2bf8954fcbed1c"> 4403</a></span><span class="preprocessor">#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l04404" name="l04404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e30d0e50fca346ca8cb427a6c85f9dc"> 4404</a></span><span class="preprocessor">#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk </span></div>
|
||
<div class="line"><a id="l04405" name="l04405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae76e0f99ff3d94336ea5da68bcd0761a"> 4405</a></span><span class="preprocessor">#define CAN_F2R2_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l04406" name="l04406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac030b2a517b48686820ece2c433e2f13"> 4406</a></span><span class="preprocessor">#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l04407" name="l04407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77586d252cad5a0a866b1d9deb6835ba"> 4407</a></span><span class="preprocessor">#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk </span></div>
|
||
<div class="line"><a id="l04408" name="l04408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13dcafb2960be76467f3aa3f5e11c9cd"> 4408</a></span><span class="preprocessor">#define CAN_F2R2_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l04409" name="l04409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fbf050f9c8c01df6dd11938eb663221"> 4409</a></span><span class="preprocessor">#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l04410" name="l04410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a10903e507b35b7425b3ae98a8c6800"> 4410</a></span><span class="preprocessor">#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk </span></div>
|
||
<div class="line"><a id="l04411" name="l04411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e2628938146647cf456f8800cc4c6cc"> 4411</a></span><span class="preprocessor">#define CAN_F2R2_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l04412" name="l04412"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38b5f7d56afc77679c64cc8559c9637c"> 4412</a></span><span class="preprocessor">#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l04413" name="l04413"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac34bca92730b6f7cd0de8af1a2d0014f"> 4413</a></span><span class="preprocessor">#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk </span></div>
|
||
<div class="line"><a id="l04415" name="l04415"></a><span class="lineno"> 4415</span><span class="comment">/******************* Bit definition for CAN_F3R2 register *******************/</span></div>
|
||
<div class="line"><a id="l04416" name="l04416"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e56069f9e4901fdf5d593117c00f56c"> 4416</a></span><span class="preprocessor">#define CAN_F3R2_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l04417" name="l04417"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa00bc043a80895a2364fdb9e51b3c110"> 4417</a></span><span class="preprocessor">#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l04418" name="l04418"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46730b7e64aa771087b6c9d5deb273e1"> 4418</a></span><span class="preprocessor">#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk </span></div>
|
||
<div class="line"><a id="l04419" name="l04419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67bcdd4d126db81bcece2a81de89c904"> 4419</a></span><span class="preprocessor">#define CAN_F3R2_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l04420" name="l04420"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9f4626256cd6e806d02f8ddd1abc6d6"> 4420</a></span><span class="preprocessor">#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l04421" name="l04421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb12b61624912b90382a4ad95281e7f4"> 4421</a></span><span class="preprocessor">#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk </span></div>
|
||
<div class="line"><a id="l04422" name="l04422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2560be72957af6d4f7449908671d8b46"> 4422</a></span><span class="preprocessor">#define CAN_F3R2_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l04423" name="l04423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d2e95083cd9cba8a5e1dea50a2647b5"> 4423</a></span><span class="preprocessor">#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l04424" name="l04424"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6621759dddc575c01f5bbaab43d1f04e"> 4424</a></span><span class="preprocessor">#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk </span></div>
|
||
<div class="line"><a id="l04425" name="l04425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabda68247678b28226021fdfad9efab7a"> 4425</a></span><span class="preprocessor">#define CAN_F3R2_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l04426" name="l04426"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1586ad1b9e7dc5ea9060b11c91c64df"> 4426</a></span><span class="preprocessor">#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l04427" name="l04427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29d052fc2597171767d8cf5d72388ad5"> 4427</a></span><span class="preprocessor">#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk </span></div>
|
||
<div class="line"><a id="l04428" name="l04428"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d8222da6dc5c339fc0b0f189a25cc49"> 4428</a></span><span class="preprocessor">#define CAN_F3R2_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l04429" name="l04429"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e602cc571c125a4b0a37ef41a35944b"> 4429</a></span><span class="preprocessor">#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l04430" name="l04430"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga731e9949d77054ba176340652083ad46"> 4430</a></span><span class="preprocessor">#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk </span></div>
|
||
<div class="line"><a id="l04431" name="l04431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55736898b14b121dec11e82b5aefe05c"> 4431</a></span><span class="preprocessor">#define CAN_F3R2_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l04432" name="l04432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb8c785ed06bbd1d49756b36134e7acb"> 4432</a></span><span class="preprocessor">#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l04433" name="l04433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93c52f51fe9eefe7f0cf094522a592b6"> 4433</a></span><span class="preprocessor">#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk </span></div>
|
||
<div class="line"><a id="l04434" name="l04434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11e7b32a226938156cb9f39271523da5"> 4434</a></span><span class="preprocessor">#define CAN_F3R2_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l04435" name="l04435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf8497045acac1d2e6704dcefa92d3b0"> 4435</a></span><span class="preprocessor">#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l04436" name="l04436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad675c2d3f72d8bc42e0f3088ddbcc3c9"> 4436</a></span><span class="preprocessor">#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk </span></div>
|
||
<div class="line"><a id="l04437" name="l04437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6117333279671f33e6cb91c69434711e"> 4437</a></span><span class="preprocessor">#define CAN_F3R2_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l04438" name="l04438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga655169f5704760518f05c635259c7177"> 4438</a></span><span class="preprocessor">#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l04439" name="l04439"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1734cf6a5a72d403cd043eb704246c85"> 4439</a></span><span class="preprocessor">#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk </span></div>
|
||
<div class="line"><a id="l04440" name="l04440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga927026c4212e401f403b68ed66b2c1c3"> 4440</a></span><span class="preprocessor">#define CAN_F3R2_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l04441" name="l04441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafad82eee295a8a2858712b7a8e78b2a0"> 4441</a></span><span class="preprocessor">#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l04442" name="l04442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97d82554ce38567e44cd87ed99175928"> 4442</a></span><span class="preprocessor">#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk </span></div>
|
||
<div class="line"><a id="l04443" name="l04443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga931d7f76fa1e6a1a49faaf5338829448"> 4443</a></span><span class="preprocessor">#define CAN_F3R2_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l04444" name="l04444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13711889ff55a6b01f7141db5f702c7a"> 4444</a></span><span class="preprocessor">#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l04445" name="l04445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga505f85fadba4397e6d9a241bbc9229bc"> 4445</a></span><span class="preprocessor">#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk </span></div>
|
||
<div class="line"><a id="l04446" name="l04446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c8ef622ab70278942e2dff25afb0ed6"> 4446</a></span><span class="preprocessor">#define CAN_F3R2_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l04447" name="l04447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbdde33568809be7611190d6b1b81012"> 4447</a></span><span class="preprocessor">#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l04448" name="l04448"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb635843951fb42ffeb776d8564d7e14"> 4448</a></span><span class="preprocessor">#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk </span></div>
|
||
<div class="line"><a id="l04449" name="l04449"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ceab55d83e6190c4b159baffae431a1"> 4449</a></span><span class="preprocessor">#define CAN_F3R2_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l04450" name="l04450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaed31d50f1d71f70a49a880e2c743663"> 4450</a></span><span class="preprocessor">#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l04451" name="l04451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5db557239646008004286de15847ced4"> 4451</a></span><span class="preprocessor">#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk </span></div>
|
||
<div class="line"><a id="l04452" name="l04452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae836a910f4fa7d303000f82a1eef47ab"> 4452</a></span><span class="preprocessor">#define CAN_F3R2_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l04453" name="l04453"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66fcb0196d04b5e606b1c4a2287a3f36"> 4453</a></span><span class="preprocessor">#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l04454" name="l04454"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga118b2044dae4c93c66aaa4f28c5b695c"> 4454</a></span><span class="preprocessor">#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk </span></div>
|
||
<div class="line"><a id="l04455" name="l04455"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8a1b5f346de27041c6dcf3d30239664"> 4455</a></span><span class="preprocessor">#define CAN_F3R2_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l04456" name="l04456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7c0fc4c6e615f3274c846c5f63319bb"> 4456</a></span><span class="preprocessor">#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l04457" name="l04457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c041a2b8162a8055a1894d0a0b3d682"> 4457</a></span><span class="preprocessor">#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk </span></div>
|
||
<div class="line"><a id="l04458" name="l04458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a4239e4164239d1ec1f6fa7e378f245"> 4458</a></span><span class="preprocessor">#define CAN_F3R2_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l04459" name="l04459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7318a2aa45622bb3ff2067b295c89839"> 4459</a></span><span class="preprocessor">#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l04460" name="l04460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb6e0947fcb7594d12dcbca38d60c9f8"> 4460</a></span><span class="preprocessor">#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk </span></div>
|
||
<div class="line"><a id="l04461" name="l04461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0abb9b1be5c5538b70b95c29f5f8feb0"> 4461</a></span><span class="preprocessor">#define CAN_F3R2_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l04462" name="l04462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdf5ab40d21a35f3bd2330139043b4c6"> 4462</a></span><span class="preprocessor">#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l04463" name="l04463"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1dae8addc6fa59e824e1a67fc8c91ddd"> 4463</a></span><span class="preprocessor">#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk </span></div>
|
||
<div class="line"><a id="l04464" name="l04464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3ee39cb4edc55608b96077047dc790a"> 4464</a></span><span class="preprocessor">#define CAN_F3R2_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l04465" name="l04465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae505ba19e3d139a3e51aa661927c2f79"> 4465</a></span><span class="preprocessor">#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l04466" name="l04466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga992795c5e0b3b8a8c5d4d6e9eceb7366"> 4466</a></span><span class="preprocessor">#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk </span></div>
|
||
<div class="line"><a id="l04467" name="l04467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe35a463b0df8233fd2c252d9e476671"> 4467</a></span><span class="preprocessor">#define CAN_F3R2_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l04468" name="l04468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45fcd762f60b60e56fe4bd937ac7950b"> 4468</a></span><span class="preprocessor">#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l04469" name="l04469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1637eff70416eb85d5d2a54e1f5d412e"> 4469</a></span><span class="preprocessor">#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk </span></div>
|
||
<div class="line"><a id="l04470" name="l04470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa713ee3afe34a389483703fe9f8246da"> 4470</a></span><span class="preprocessor">#define CAN_F3R2_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l04471" name="l04471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga347cadef74e15229097c45f255cdeb8e"> 4471</a></span><span class="preprocessor">#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l04472" name="l04472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7bbfdfa29b84ea60e67d41f775c6ffc6"> 4472</a></span><span class="preprocessor">#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk </span></div>
|
||
<div class="line"><a id="l04473" name="l04473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79eb2b7440516e0a76367dc2fa83bad5"> 4473</a></span><span class="preprocessor">#define CAN_F3R2_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l04474" name="l04474"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31404c72668cd4b409b16a1335a73dae"> 4474</a></span><span class="preprocessor">#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l04475" name="l04475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga827747e8cc66e4dcd22498c59e45c776"> 4475</a></span><span class="preprocessor">#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk </span></div>
|
||
<div class="line"><a id="l04476" name="l04476"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga464afddcd2bbd06df0bb2ee572a9cfd4"> 4476</a></span><span class="preprocessor">#define CAN_F3R2_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l04477" name="l04477"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd69af5b3822a2a480bb9041a8011074"> 4477</a></span><span class="preprocessor">#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l04478" name="l04478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe0bb6919615ec6311e8c39f62bca618"> 4478</a></span><span class="preprocessor">#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk </span></div>
|
||
<div class="line"><a id="l04479" name="l04479"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8770034c4717ac38141892bd84b23079"> 4479</a></span><span class="preprocessor">#define CAN_F3R2_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l04480" name="l04480"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab102b108170e7865f895d7ca6c40f12e"> 4480</a></span><span class="preprocessor">#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l04481" name="l04481"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c3e4716d3e52ec99451a942dceb59de"> 4481</a></span><span class="preprocessor">#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk </span></div>
|
||
<div class="line"><a id="l04482" name="l04482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga033a69b00a00cef04f5526c727bad275"> 4482</a></span><span class="preprocessor">#define CAN_F3R2_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l04483" name="l04483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22a42411bd3d2c7a7dc3e41bd40777ae"> 4483</a></span><span class="preprocessor">#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l04484" name="l04484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffefb44a948d36dcd94248f63aa68d2b"> 4484</a></span><span class="preprocessor">#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk </span></div>
|
||
<div class="line"><a id="l04485" name="l04485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03beb9a7aeb8179ceed1d97083e28bbd"> 4485</a></span><span class="preprocessor">#define CAN_F3R2_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l04486" name="l04486"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5cae3507194258095f48d348f1307b0"> 4486</a></span><span class="preprocessor">#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l04487" name="l04487"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79ce25d44a38f520b4a93384d6f5ac40"> 4487</a></span><span class="preprocessor">#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk </span></div>
|
||
<div class="line"><a id="l04488" name="l04488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7099835a0d2250cc0cbd274f7f4390ff"> 4488</a></span><span class="preprocessor">#define CAN_F3R2_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l04489" name="l04489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9218c367ef6f00e60b093f3f23a7a0b9"> 4489</a></span><span class="preprocessor">#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l04490" name="l04490"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3fe1ced752dc811f9418181275c8c3fe"> 4490</a></span><span class="preprocessor">#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk </span></div>
|
||
<div class="line"><a id="l04491" name="l04491"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac02382c65073c2552fc97fae6cf64b23"> 4491</a></span><span class="preprocessor">#define CAN_F3R2_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l04492" name="l04492"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f46cde0b8517ab5b9625a614ea3d922"> 4492</a></span><span class="preprocessor">#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l04493" name="l04493"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fb2f469246193f6fc9e4ade42192d28"> 4493</a></span><span class="preprocessor">#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk </span></div>
|
||
<div class="line"><a id="l04494" name="l04494"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5cce1ce749c1341320ab27c5ccaf9c7"> 4494</a></span><span class="preprocessor">#define CAN_F3R2_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l04495" name="l04495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab13acbfad9a6174945e4b814d2b3e5a8"> 4495</a></span><span class="preprocessor">#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l04496" name="l04496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae85be7f7d7a9ddb8a60edb30d2a5727"> 4496</a></span><span class="preprocessor">#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk </span></div>
|
||
<div class="line"><a id="l04497" name="l04497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8bda0fbf28a49b2b7513f6d6810d9979"> 4497</a></span><span class="preprocessor">#define CAN_F3R2_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l04498" name="l04498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb6f5115c365c1103bfb0c2e447de450"> 4498</a></span><span class="preprocessor">#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l04499" name="l04499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga850c21b26100c68b9cb57608c0249543"> 4499</a></span><span class="preprocessor">#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk </span></div>
|
||
<div class="line"><a id="l04500" name="l04500"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77eba2b30abdf4a2a9b5ecb3f8616519"> 4500</a></span><span class="preprocessor">#define CAN_F3R2_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l04501" name="l04501"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga969752803fe126111b3cd5149859c94e"> 4501</a></span><span class="preprocessor">#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l04502" name="l04502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82ec6ad2ad1b6115496adcb3e66fae25"> 4502</a></span><span class="preprocessor">#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk </span></div>
|
||
<div class="line"><a id="l04503" name="l04503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59cecf28681a17397c201f6ee9dc450f"> 4503</a></span><span class="preprocessor">#define CAN_F3R2_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l04504" name="l04504"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83e06415202aa98552793b9fa28ee9a7"> 4504</a></span><span class="preprocessor">#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l04505" name="l04505"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4fa34cc998edfdd1b3db93395ee6500"> 4505</a></span><span class="preprocessor">#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk </span></div>
|
||
<div class="line"><a id="l04506" name="l04506"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0238173e08b65c4ddffb5f300616bbd5"> 4506</a></span><span class="preprocessor">#define CAN_F3R2_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l04507" name="l04507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga367133e3ee7501aef9513944565cea6f"> 4507</a></span><span class="preprocessor">#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l04508" name="l04508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f4fea5ecec28e7f47647067b75cb24e"> 4508</a></span><span class="preprocessor">#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk </span></div>
|
||
<div class="line"><a id="l04509" name="l04509"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacda1d6cbc1ba76b6fbf6b69d5b805969"> 4509</a></span><span class="preprocessor">#define CAN_F3R2_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l04510" name="l04510"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga994e84701ba2b7c21cdc7392a46e9d80"> 4510</a></span><span class="preprocessor">#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l04511" name="l04511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58a154f4d0cb787f23429b3f7cf70fd6"> 4511</a></span><span class="preprocessor">#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk </span></div>
|
||
<div class="line"><a id="l04513" name="l04513"></a><span class="lineno"> 4513</span><span class="comment">/******************* Bit definition for CAN_F4R2 register *******************/</span></div>
|
||
<div class="line"><a id="l04514" name="l04514"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1419ddd39b1b989b7bd57df584d40e93"> 4514</a></span><span class="preprocessor">#define CAN_F4R2_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l04515" name="l04515"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f9048515e8f37041f6aff9999aff569"> 4515</a></span><span class="preprocessor">#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l04516" name="l04516"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97250d3eed2504846f39c50dce71c9d0"> 4516</a></span><span class="preprocessor">#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk </span></div>
|
||
<div class="line"><a id="l04517" name="l04517"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga960af74ce166416ac55bc7c945adaec8"> 4517</a></span><span class="preprocessor">#define CAN_F4R2_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l04518" name="l04518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63b07509549c3a1b2559040dd01c9a0e"> 4518</a></span><span class="preprocessor">#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l04519" name="l04519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga145e11678ee6062df5164894ad8f80b1"> 4519</a></span><span class="preprocessor">#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk </span></div>
|
||
<div class="line"><a id="l04520" name="l04520"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b9fe6bf1b80f4cc053b9e9f8bddb224"> 4520</a></span><span class="preprocessor">#define CAN_F4R2_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l04521" name="l04521"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f84ea90801ae445733a36c8f10ec608"> 4521</a></span><span class="preprocessor">#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l04522" name="l04522"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d19193baf5412ec2e38822d062196b8"> 4522</a></span><span class="preprocessor">#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk </span></div>
|
||
<div class="line"><a id="l04523" name="l04523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81bfbead828bc1a65eee77e210a82107"> 4523</a></span><span class="preprocessor">#define CAN_F4R2_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l04524" name="l04524"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c4fe680c0484c7757d15d939a50e8b1"> 4524</a></span><span class="preprocessor">#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l04525" name="l04525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94b8b1428b640932aced6446f8b41f83"> 4525</a></span><span class="preprocessor">#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk </span></div>
|
||
<div class="line"><a id="l04526" name="l04526"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84bb4ceedefb72e55d9b84543e1e7996"> 4526</a></span><span class="preprocessor">#define CAN_F4R2_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l04527" name="l04527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91056080450f8e5f68b3120ed7b609fb"> 4527</a></span><span class="preprocessor">#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l04528" name="l04528"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93164ec00412eb5eed168e8a30557f25"> 4528</a></span><span class="preprocessor">#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk </span></div>
|
||
<div class="line"><a id="l04529" name="l04529"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74b468294e8df41868bf3c06bdf481bd"> 4529</a></span><span class="preprocessor">#define CAN_F4R2_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l04530" name="l04530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96484b04cb3e058e3f70b722713990dc"> 4530</a></span><span class="preprocessor">#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l04531" name="l04531"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04e44c5a14e44c20f3b81044a915db13"> 4531</a></span><span class="preprocessor">#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk </span></div>
|
||
<div class="line"><a id="l04532" name="l04532"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad305c1f3555c0dc3ccdf8da5bc775504"> 4532</a></span><span class="preprocessor">#define CAN_F4R2_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l04533" name="l04533"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacde7359de773b8b427dddca91f99a3c2"> 4533</a></span><span class="preprocessor">#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l04534" name="l04534"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37e57dec99c33f462a2dbb6273df2f57"> 4534</a></span><span class="preprocessor">#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk </span></div>
|
||
<div class="line"><a id="l04535" name="l04535"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74a2c4a85e2ced48f8e8c14e28e8a527"> 4535</a></span><span class="preprocessor">#define CAN_F4R2_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l04536" name="l04536"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87bfab19292dba8c2e7c6f6d366f1490"> 4536</a></span><span class="preprocessor">#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l04537" name="l04537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6c7d3ec0375e356192583142f7fccca"> 4537</a></span><span class="preprocessor">#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk </span></div>
|
||
<div class="line"><a id="l04538" name="l04538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0e0dd86f16cceefbb63044d48a7f4ae"> 4538</a></span><span class="preprocessor">#define CAN_F4R2_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l04539" name="l04539"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad82667269e283535191eb3439f4ad6a2"> 4539</a></span><span class="preprocessor">#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l04540" name="l04540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad33f7d788aea161826a86bc2c5567450"> 4540</a></span><span class="preprocessor">#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk </span></div>
|
||
<div class="line"><a id="l04541" name="l04541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad6bc30c3c453102c6ff321a9b74ff94"> 4541</a></span><span class="preprocessor">#define CAN_F4R2_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l04542" name="l04542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae060ee50f1193b9e8a2b2ad84789eed7"> 4542</a></span><span class="preprocessor">#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l04543" name="l04543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab998448b0bd20ff6384c26ad9e6baaf"> 4543</a></span><span class="preprocessor">#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk </span></div>
|
||
<div class="line"><a id="l04544" name="l04544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30c085eaa270c21b83fb471ae334e59f"> 4544</a></span><span class="preprocessor">#define CAN_F4R2_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l04545" name="l04545"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3152ad433d216935b86e5014dd69626e"> 4545</a></span><span class="preprocessor">#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l04546" name="l04546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8794112fcbb0dca0c7d0316ac8725e8"> 4546</a></span><span class="preprocessor">#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk </span></div>
|
||
<div class="line"><a id="l04547" name="l04547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a4b0466c13c7c8259301cd2f23cc8de"> 4547</a></span><span class="preprocessor">#define CAN_F4R2_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l04548" name="l04548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabc14b1315fea6d9b3948d9f00f07de7"> 4548</a></span><span class="preprocessor">#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l04549" name="l04549"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d22e782a9ca087f99ab9f53b2626aed"> 4549</a></span><span class="preprocessor">#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk </span></div>
|
||
<div class="line"><a id="l04550" name="l04550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e89e50734d1ff90c8246f14bcb4d83a"> 4550</a></span><span class="preprocessor">#define CAN_F4R2_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l04551" name="l04551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8d1eae74bfd099a0512f44a4bd928c9"> 4551</a></span><span class="preprocessor">#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l04552" name="l04552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa8d5c2635a62bdfa6e3a5a12b127fc8"> 4552</a></span><span class="preprocessor">#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk </span></div>
|
||
<div class="line"><a id="l04553" name="l04553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7394fbd307de3a0701d41b984658940"> 4553</a></span><span class="preprocessor">#define CAN_F4R2_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l04554" name="l04554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ad9d3c7bbf0cf276350b00a04b43c37"> 4554</a></span><span class="preprocessor">#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l04555" name="l04555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad491689799985f0c8f17b270cd8873c4"> 4555</a></span><span class="preprocessor">#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk </span></div>
|
||
<div class="line"><a id="l04556" name="l04556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedcf4b945f92674309ef9535166dc473"> 4556</a></span><span class="preprocessor">#define CAN_F4R2_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l04557" name="l04557"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31079d3271fc34363eed112cb9a3ed23"> 4557</a></span><span class="preprocessor">#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l04558" name="l04558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1b80d40d87204de4687735de852f47f"> 4558</a></span><span class="preprocessor">#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk </span></div>
|
||
<div class="line"><a id="l04559" name="l04559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc517c539daa4ed10cd59739b5eac588"> 4559</a></span><span class="preprocessor">#define CAN_F4R2_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l04560" name="l04560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd57e61b87f3e1e9632ad2075732fa5a"> 4560</a></span><span class="preprocessor">#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l04561" name="l04561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0994b341ba8a73b950f01d83d012780d"> 4561</a></span><span class="preprocessor">#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk </span></div>
|
||
<div class="line"><a id="l04562" name="l04562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f7127ca82dc78b93a37e7cf80a5ceb8"> 4562</a></span><span class="preprocessor">#define CAN_F4R2_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l04563" name="l04563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac24f6b4c83f05dfbd05e15c128ad6fbf"> 4563</a></span><span class="preprocessor">#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l04564" name="l04564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ae8b77d791ba7403618989a77e62922"> 4564</a></span><span class="preprocessor">#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk </span></div>
|
||
<div class="line"><a id="l04565" name="l04565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0189abc764580a8777fff47521d38303"> 4565</a></span><span class="preprocessor">#define CAN_F4R2_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l04566" name="l04566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga973be88ab5b27952acbdb24e0b817d78"> 4566</a></span><span class="preprocessor">#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l04567" name="l04567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc116988117a7e7fabc722855351d257"> 4567</a></span><span class="preprocessor">#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk </span></div>
|
||
<div class="line"><a id="l04568" name="l04568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad6a2d9360b2d898f9f52098f68ea290"> 4568</a></span><span class="preprocessor">#define CAN_F4R2_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l04569" name="l04569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf85749ab4396b250aac41526571cecf3"> 4569</a></span><span class="preprocessor">#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l04570" name="l04570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07b1fc6ee0dc4cc892d69ed496b59007"> 4570</a></span><span class="preprocessor">#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk </span></div>
|
||
<div class="line"><a id="l04571" name="l04571"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga610320557b86dc3210d49af3a2ff476b"> 4571</a></span><span class="preprocessor">#define CAN_F4R2_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l04572" name="l04572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab74002038e0de0bebc00117c89343be6"> 4572</a></span><span class="preprocessor">#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l04573" name="l04573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa58785812f0d3e73a657426b81f0b78b"> 4573</a></span><span class="preprocessor">#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk </span></div>
|
||
<div class="line"><a id="l04574" name="l04574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga338e34091813fe910437c7f4b07f4a15"> 4574</a></span><span class="preprocessor">#define CAN_F4R2_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l04575" name="l04575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga814015c75ef6ae829af165ba84aa7692"> 4575</a></span><span class="preprocessor">#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l04576" name="l04576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga363da353073d7ee6421cf171688ef52b"> 4576</a></span><span class="preprocessor">#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk </span></div>
|
||
<div class="line"><a id="l04577" name="l04577"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3b436d0a50503f95b84d596659fb1a4"> 4577</a></span><span class="preprocessor">#define CAN_F4R2_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l04578" name="l04578"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7d83298755e6833a20617ab15f8712d"> 4578</a></span><span class="preprocessor">#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l04579" name="l04579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f22695359aa9a1b07763aef44a9a1c4"> 4579</a></span><span class="preprocessor">#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk </span></div>
|
||
<div class="line"><a id="l04580" name="l04580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2906d67400ef4a87ffb17a1f26d6ae7b"> 4580</a></span><span class="preprocessor">#define CAN_F4R2_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l04581" name="l04581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac94ecf7d43f6a018320c3d25bc9b46c2"> 4581</a></span><span class="preprocessor">#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l04582" name="l04582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0f8c1ef382225198407474f2b7fa073"> 4582</a></span><span class="preprocessor">#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk </span></div>
|
||
<div class="line"><a id="l04583" name="l04583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3b071adef809e00edf9cb9d891d6d44"> 4583</a></span><span class="preprocessor">#define CAN_F4R2_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l04584" name="l04584"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55e657b91bf8789bccd4f52b8f865b2d"> 4584</a></span><span class="preprocessor">#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l04585" name="l04585"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9476c54044db3182ee789e9df1d1aa19"> 4585</a></span><span class="preprocessor">#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk </span></div>
|
||
<div class="line"><a id="l04586" name="l04586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5da4e3d58f6f15b8c756e0bb38be4cc4"> 4586</a></span><span class="preprocessor">#define CAN_F4R2_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l04587" name="l04587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1696522c0eecd85f864be345e40a29ea"> 4587</a></span><span class="preprocessor">#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l04588" name="l04588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73158a3669d2ef96db84e4f196d040bf"> 4588</a></span><span class="preprocessor">#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk </span></div>
|
||
<div class="line"><a id="l04589" name="l04589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f7d61b349c5bca004c6af7eaaee0a05"> 4589</a></span><span class="preprocessor">#define CAN_F4R2_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l04590" name="l04590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92bfc25c457c753a6e6635781a348471"> 4590</a></span><span class="preprocessor">#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l04591" name="l04591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17d36fcf8e08c76597a7b2c05e831f98"> 4591</a></span><span class="preprocessor">#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk </span></div>
|
||
<div class="line"><a id="l04592" name="l04592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ad5b4c8debdf28b0c25c49b678ea058"> 4592</a></span><span class="preprocessor">#define CAN_F4R2_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l04593" name="l04593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03b9b82299251b22f45b8ead71dc2675"> 4593</a></span><span class="preprocessor">#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l04594" name="l04594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa683635426f418ead45032c25e0179ee"> 4594</a></span><span class="preprocessor">#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk </span></div>
|
||
<div class="line"><a id="l04595" name="l04595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacaf248d9dc1f65a0536fa18819437aea"> 4595</a></span><span class="preprocessor">#define CAN_F4R2_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l04596" name="l04596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9295be11108120ae840e8c0f12f0ed5"> 4596</a></span><span class="preprocessor">#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l04597" name="l04597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23c77145ea84805a785b49c0a7f31774"> 4597</a></span><span class="preprocessor">#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk </span></div>
|
||
<div class="line"><a id="l04598" name="l04598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga380250b4976a40ee70fbe9f86f566de1"> 4598</a></span><span class="preprocessor">#define CAN_F4R2_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l04599" name="l04599"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9d7545d55253cd33e9bc8a186692071"> 4599</a></span><span class="preprocessor">#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l04600" name="l04600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18492e954ec07174a1b140104062f941"> 4600</a></span><span class="preprocessor">#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk </span></div>
|
||
<div class="line"><a id="l04601" name="l04601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98aa4a050c05406a714f4046fc7e7461"> 4601</a></span><span class="preprocessor">#define CAN_F4R2_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l04602" name="l04602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9db3158da58bb55ec0b8e038214bf57c"> 4602</a></span><span class="preprocessor">#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l04603" name="l04603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf94626a8450c20e241ad6298660ec23"> 4603</a></span><span class="preprocessor">#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk </span></div>
|
||
<div class="line"><a id="l04604" name="l04604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c597a7985c16b24ef4cca5c0a14e60b"> 4604</a></span><span class="preprocessor">#define CAN_F4R2_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l04605" name="l04605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga172377c09e98ed68359ffe7bb49f556c"> 4605</a></span><span class="preprocessor">#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l04606" name="l04606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d7da9aa234705aff3ddc9845b1589d4"> 4606</a></span><span class="preprocessor">#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk </span></div>
|
||
<div class="line"><a id="l04607" name="l04607"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43fc86c148a9c62cf94e0c4b1827b4ad"> 4607</a></span><span class="preprocessor">#define CAN_F4R2_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l04608" name="l04608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a9da9f03b531cb1019a2a401e9177d6"> 4608</a></span><span class="preprocessor">#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l04609" name="l04609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70293ff8a71e353d84a3da134eb427d9"> 4609</a></span><span class="preprocessor">#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk </span></div>
|
||
<div class="line"><a id="l04611" name="l04611"></a><span class="lineno"> 4611</span><span class="comment">/******************* Bit definition for CAN_F5R2 register *******************/</span></div>
|
||
<div class="line"><a id="l04612" name="l04612"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31ac96e599e5acbc734ad3ae742ba942"> 4612</a></span><span class="preprocessor">#define CAN_F5R2_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l04613" name="l04613"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab01f1756425341377c80a011da4cfcb1"> 4613</a></span><span class="preprocessor">#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l04614" name="l04614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17b264aaa84a3c6ab5a35014eb5dfb09"> 4614</a></span><span class="preprocessor">#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk </span></div>
|
||
<div class="line"><a id="l04615" name="l04615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf76834e934a1e6431cc7d604747050e1"> 4615</a></span><span class="preprocessor">#define CAN_F5R2_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l04616" name="l04616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa669537bb8f8adf60f0d40d76f5d9fb9"> 4616</a></span><span class="preprocessor">#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l04617" name="l04617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa871f5bc692996efc8c1bad1d08b43c5"> 4617</a></span><span class="preprocessor">#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk </span></div>
|
||
<div class="line"><a id="l04618" name="l04618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8245d1c94d1b1b37f88fbb8361d0995"> 4618</a></span><span class="preprocessor">#define CAN_F5R2_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l04619" name="l04619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa81eadbcd56cc52d9c0b7435ba5b40e9"> 4619</a></span><span class="preprocessor">#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l04620" name="l04620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf44a72156023a5889a1c22d77e188e2e"> 4620</a></span><span class="preprocessor">#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk </span></div>
|
||
<div class="line"><a id="l04621" name="l04621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53e88ec5a445a1a06d1106bb8d306ef6"> 4621</a></span><span class="preprocessor">#define CAN_F5R2_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l04622" name="l04622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4271ce693ee149054334055f32083514"> 4622</a></span><span class="preprocessor">#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l04623" name="l04623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d8828885a79299bc65c2011f71240e2"> 4623</a></span><span class="preprocessor">#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk </span></div>
|
||
<div class="line"><a id="l04624" name="l04624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4516eaeaa55e303db71ed3ae9babff88"> 4624</a></span><span class="preprocessor">#define CAN_F5R2_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l04625" name="l04625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4dd49575e4657b373fd5cdc67067e0d"> 4625</a></span><span class="preprocessor">#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l04626" name="l04626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfa978108927c827e3021499a20d0372"> 4626</a></span><span class="preprocessor">#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk </span></div>
|
||
<div class="line"><a id="l04627" name="l04627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4cd2ba17430db1908a126f95f8b3811"> 4627</a></span><span class="preprocessor">#define CAN_F5R2_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l04628" name="l04628"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac14329fcf8b7c680e02b7967e8cb98ea"> 4628</a></span><span class="preprocessor">#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l04629" name="l04629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3b3c48011935170a9bd120b724030fe"> 4629</a></span><span class="preprocessor">#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk </span></div>
|
||
<div class="line"><a id="l04630" name="l04630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9c07be713f85a6784c934880b47fac6"> 4630</a></span><span class="preprocessor">#define CAN_F5R2_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l04631" name="l04631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga119d967c2b9dff5291f892ed55650722"> 4631</a></span><span class="preprocessor">#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l04632" name="l04632"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56cf7f6d0bf48847f3d8f72777774e58"> 4632</a></span><span class="preprocessor">#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk </span></div>
|
||
<div class="line"><a id="l04633" name="l04633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0853bd11144bb38e99488b1bb31899a"> 4633</a></span><span class="preprocessor">#define CAN_F5R2_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l04634" name="l04634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae72af802de3283727835678b4d783b7e"> 4634</a></span><span class="preprocessor">#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l04635" name="l04635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cb8a5551d90c8d79b09b4d82f3f59c2"> 4635</a></span><span class="preprocessor">#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk </span></div>
|
||
<div class="line"><a id="l04636" name="l04636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafef8fdd804993ad8b9cbce7223f888c8"> 4636</a></span><span class="preprocessor">#define CAN_F5R2_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l04637" name="l04637"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa770d4e9ecd17918854fc97a3d96bdfd"> 4637</a></span><span class="preprocessor">#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l04638" name="l04638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga423b7b77bfd5dd6791f1b1dd16e9807a"> 4638</a></span><span class="preprocessor">#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk </span></div>
|
||
<div class="line"><a id="l04639" name="l04639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6eed4d57ced26b73f1b76bdfbabfe980"> 4639</a></span><span class="preprocessor">#define CAN_F5R2_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l04640" name="l04640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4d4e4451476d46716de06cef008beb1"> 4640</a></span><span class="preprocessor">#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l04641" name="l04641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c50420a128a70341e63ad23b0bedba5"> 4641</a></span><span class="preprocessor">#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk </span></div>
|
||
<div class="line"><a id="l04642" name="l04642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef3f52dc2809f93b4bc777b1ef062556"> 4642</a></span><span class="preprocessor">#define CAN_F5R2_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l04643" name="l04643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga860f7fadc560b00fe1878226c9a847be"> 4643</a></span><span class="preprocessor">#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l04644" name="l04644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga392844657c800d2e16e7916ed5fb9891"> 4644</a></span><span class="preprocessor">#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk </span></div>
|
||
<div class="line"><a id="l04645" name="l04645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga998e4248e08394cf031b6d25a909a654"> 4645</a></span><span class="preprocessor">#define CAN_F5R2_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l04646" name="l04646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3cf1650e026cc5bb83c111dc8e9ce5e"> 4646</a></span><span class="preprocessor">#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l04647" name="l04647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb35a3bbc447c46929643115490e250d"> 4647</a></span><span class="preprocessor">#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk </span></div>
|
||
<div class="line"><a id="l04648" name="l04648"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bf1445ca1ebcf7eed420cf412e07f05"> 4648</a></span><span class="preprocessor">#define CAN_F5R2_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l04649" name="l04649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed02925c42bc722b25c350bc00ec815f"> 4649</a></span><span class="preprocessor">#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l04650" name="l04650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga974bae58f9819eee0377d709c985bcbe"> 4650</a></span><span class="preprocessor">#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk </span></div>
|
||
<div class="line"><a id="l04651" name="l04651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80ab623333a37c66175f1b9b239cce27"> 4651</a></span><span class="preprocessor">#define CAN_F5R2_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l04652" name="l04652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6a2dbe8f45f7a844a2dd0dcf07786d6"> 4652</a></span><span class="preprocessor">#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l04653" name="l04653"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2823bb25e138cc52d11b154456947ab7"> 4653</a></span><span class="preprocessor">#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk </span></div>
|
||
<div class="line"><a id="l04654" name="l04654"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga019a3a59115f5994ef92a14ea8373bef"> 4654</a></span><span class="preprocessor">#define CAN_F5R2_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l04655" name="l04655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6d471b7cf1edcabeba6eb8af6a2ca83"> 4655</a></span><span class="preprocessor">#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l04656" name="l04656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98cf223bdcc1a106f7573b57f836f9ed"> 4656</a></span><span class="preprocessor">#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk </span></div>
|
||
<div class="line"><a id="l04657" name="l04657"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9dac6309c6bf54e66e6fdae4771190ad"> 4657</a></span><span class="preprocessor">#define CAN_F5R2_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l04658" name="l04658"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3dde50a6686b9be1d26d3d855e85f7c"> 4658</a></span><span class="preprocessor">#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l04659" name="l04659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26bfd14720495dd180f1524f2fdb3743"> 4659</a></span><span class="preprocessor">#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk </span></div>
|
||
<div class="line"><a id="l04660" name="l04660"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f6cb58d414c1819c65d080328db8044"> 4660</a></span><span class="preprocessor">#define CAN_F5R2_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l04661" name="l04661"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ee326307cb31cf3cc82c36765a14f5f"> 4661</a></span><span class="preprocessor">#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l04662" name="l04662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41b457c721dc855d05b2f353c22a83a7"> 4662</a></span><span class="preprocessor">#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk </span></div>
|
||
<div class="line"><a id="l04663" name="l04663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5c8011137b67c4ad3a51b1139a3e0ed"> 4663</a></span><span class="preprocessor">#define CAN_F5R2_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l04664" name="l04664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4d64f35fb861a436083a675a4d55087"> 4664</a></span><span class="preprocessor">#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l04665" name="l04665"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bc89534aaf3f810a2151b04b0086717"> 4665</a></span><span class="preprocessor">#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk </span></div>
|
||
<div class="line"><a id="l04666" name="l04666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96dcca6b4fa2e2cf12ffe3af72a1b679"> 4666</a></span><span class="preprocessor">#define CAN_F5R2_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l04667" name="l04667"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae05e7364c82e1f610e927785ec039d6a"> 4667</a></span><span class="preprocessor">#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l04668" name="l04668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga070940536728fad3c0e5336926131b4b"> 4668</a></span><span class="preprocessor">#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk </span></div>
|
||
<div class="line"><a id="l04669" name="l04669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60046c4ebf351deeaf74223758d53675"> 4669</a></span><span class="preprocessor">#define CAN_F5R2_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l04670" name="l04670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac707fb2bec18e9152234fc5c58b5cbc9"> 4670</a></span><span class="preprocessor">#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l04671" name="l04671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddf2e4aa8107150a86d37ce03a0e1c0e"> 4671</a></span><span class="preprocessor">#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk </span></div>
|
||
<div class="line"><a id="l04672" name="l04672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3ae858c989b3736de3373c42fac5775"> 4672</a></span><span class="preprocessor">#define CAN_F5R2_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l04673" name="l04673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga543013c958dcfd0719772fcea3ec7442"> 4673</a></span><span class="preprocessor">#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l04674" name="l04674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1788704faad47f1d45017df41a35f053"> 4674</a></span><span class="preprocessor">#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk </span></div>
|
||
<div class="line"><a id="l04675" name="l04675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb635f8a3ff310a99ae6ef459d681ac6"> 4675</a></span><span class="preprocessor">#define CAN_F5R2_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l04676" name="l04676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab64136662c15ae221d5a0c1a5dd54b08"> 4676</a></span><span class="preprocessor">#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l04677" name="l04677"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11c4aeffb6646643c412e19e6f5cc015"> 4677</a></span><span class="preprocessor">#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk </span></div>
|
||
<div class="line"><a id="l04678" name="l04678"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga684958cea52e6120dcdc40a55c1442e2"> 4678</a></span><span class="preprocessor">#define CAN_F5R2_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l04679" name="l04679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61b1a77cc46c59213948b974f622090d"> 4679</a></span><span class="preprocessor">#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l04680" name="l04680"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef348c2d37f96f5e5324368f90c80d42"> 4680</a></span><span class="preprocessor">#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk </span></div>
|
||
<div class="line"><a id="l04681" name="l04681"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8ecdc64db223884f8a2a539045a52a2"> 4681</a></span><span class="preprocessor">#define CAN_F5R2_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l04682" name="l04682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99c053ca550685ca82a4068cb35dcf1e"> 4682</a></span><span class="preprocessor">#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l04683" name="l04683"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga398d842cfcb2d441d999e1407fc54f83"> 4683</a></span><span class="preprocessor">#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk </span></div>
|
||
<div class="line"><a id="l04684" name="l04684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab98edeba8a885855d8ab39e4da3b2a23"> 4684</a></span><span class="preprocessor">#define CAN_F5R2_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l04685" name="l04685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95a78f8f2aa15cad8513b89355533e9c"> 4685</a></span><span class="preprocessor">#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l04686" name="l04686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6575f8d4d154e2e8342b3f88352a9d52"> 4686</a></span><span class="preprocessor">#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk </span></div>
|
||
<div class="line"><a id="l04687" name="l04687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a4842fb46f7a105bbd49413c6eee911"> 4687</a></span><span class="preprocessor">#define CAN_F5R2_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l04688" name="l04688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga008957461f388566b56639ecbc17cebb"> 4688</a></span><span class="preprocessor">#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l04689" name="l04689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9e6ad77b1d8ac7303e920658aceb354"> 4689</a></span><span class="preprocessor">#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk </span></div>
|
||
<div class="line"><a id="l04690" name="l04690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7170d32e10c78e3fc54d039496f53506"> 4690</a></span><span class="preprocessor">#define CAN_F5R2_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l04691" name="l04691"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga933f9591f9dd20f70ba06053f261fac2"> 4691</a></span><span class="preprocessor">#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l04692" name="l04692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga911ade78e30d1a037d35dda5eb7cbd4b"> 4692</a></span><span class="preprocessor">#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk </span></div>
|
||
<div class="line"><a id="l04693" name="l04693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36212c15d8fb9e6fd90221aa199ce898"> 4693</a></span><span class="preprocessor">#define CAN_F5R2_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l04694" name="l04694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb9d77aef830c128d7c7582c5b05799b"> 4694</a></span><span class="preprocessor">#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l04695" name="l04695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49542b9334bc4917e25d6808c78787d1"> 4695</a></span><span class="preprocessor">#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk </span></div>
|
||
<div class="line"><a id="l04696" name="l04696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe87106ef6da9830afb1aa98c5e65823"> 4696</a></span><span class="preprocessor">#define CAN_F5R2_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l04697" name="l04697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28c9aaa77d535cf3323afecae54f2014"> 4697</a></span><span class="preprocessor">#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l04698" name="l04698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga255da64f4a66ff888f6633d6e51658c6"> 4698</a></span><span class="preprocessor">#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk </span></div>
|
||
<div class="line"><a id="l04699" name="l04699"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae96aac0fb32c68c6803fa56115592c4d"> 4699</a></span><span class="preprocessor">#define CAN_F5R2_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l04700" name="l04700"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3a0ff1fd4b5ea4e84e5ef7c11553ac6"> 4700</a></span><span class="preprocessor">#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l04701" name="l04701"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8335d23f9fd156f40dc7fd63ba6783cb"> 4701</a></span><span class="preprocessor">#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk </span></div>
|
||
<div class="line"><a id="l04702" name="l04702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e488b1f7932407cda7b439bf69df464"> 4702</a></span><span class="preprocessor">#define CAN_F5R2_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l04703" name="l04703"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3d4abd59ef329e2a4cdacd80450b71e"> 4703</a></span><span class="preprocessor">#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l04704" name="l04704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf81786b7519b39f705729de2c55e4faa"> 4704</a></span><span class="preprocessor">#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk </span></div>
|
||
<div class="line"><a id="l04705" name="l04705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb423f7f26c55460925e1d1a7e5a073d"> 4705</a></span><span class="preprocessor">#define CAN_F5R2_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l04706" name="l04706"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga872287cb1dc75d841a74fef1df7d04c4"> 4706</a></span><span class="preprocessor">#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l04707" name="l04707"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f7122b0ad8cb4fc1797d0dbecbb4a05"> 4707</a></span><span class="preprocessor">#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk </span></div>
|
||
<div class="line"><a id="l04709" name="l04709"></a><span class="lineno"> 4709</span><span class="comment">/******************* Bit definition for CAN_F6R2 register *******************/</span></div>
|
||
<div class="line"><a id="l04710" name="l04710"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20cc3ea8010fbf026315233056de5b0d"> 4710</a></span><span class="preprocessor">#define CAN_F6R2_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l04711" name="l04711"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f57610bbf8a5efd029417aae54d4bbb"> 4711</a></span><span class="preprocessor">#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l04712" name="l04712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71ad6452660daed3d6c436533a25efc2"> 4712</a></span><span class="preprocessor">#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk </span></div>
|
||
<div class="line"><a id="l04713" name="l04713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57ea3c021bd5598a314a2dc310b2c242"> 4713</a></span><span class="preprocessor">#define CAN_F6R2_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l04714" name="l04714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b30db0682c6a7847de91680b2532808"> 4714</a></span><span class="preprocessor">#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l04715" name="l04715"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9e24abd8d2f0775661415b6565f4f6d"> 4715</a></span><span class="preprocessor">#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk </span></div>
|
||
<div class="line"><a id="l04716" name="l04716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb418d7998996d8fbbbe6a7f9f81a6d3"> 4716</a></span><span class="preprocessor">#define CAN_F6R2_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l04717" name="l04717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa901630470057df2e214f14994a714aa"> 4717</a></span><span class="preprocessor">#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l04718" name="l04718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6dc3f6ce4dde435743aadbe17cc78b9"> 4718</a></span><span class="preprocessor">#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk </span></div>
|
||
<div class="line"><a id="l04719" name="l04719"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a70af83c83018fdb987a9121ef6bba7"> 4719</a></span><span class="preprocessor">#define CAN_F6R2_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l04720" name="l04720"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0d1bbfb93db519a92310ca7074289e7"> 4720</a></span><span class="preprocessor">#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l04721" name="l04721"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1f5163490dffe1f4d7c635458359c2f"> 4721</a></span><span class="preprocessor">#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk </span></div>
|
||
<div class="line"><a id="l04722" name="l04722"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaff0bb055714dfce4422592cc05805c2"> 4722</a></span><span class="preprocessor">#define CAN_F6R2_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l04723" name="l04723"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga747c01d82b012765a96bf20ae2d1e614"> 4723</a></span><span class="preprocessor">#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l04724" name="l04724"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89e9191d214d05f4d90fbcd38daa73e1"> 4724</a></span><span class="preprocessor">#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk </span></div>
|
||
<div class="line"><a id="l04725" name="l04725"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69724e09645446cfec63ef3720f3424e"> 4725</a></span><span class="preprocessor">#define CAN_F6R2_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l04726" name="l04726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga731205c17b0265b0aed17e7335d665f1"> 4726</a></span><span class="preprocessor">#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l04727" name="l04727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97d29588281c546d98e09760cc5ef593"> 4727</a></span><span class="preprocessor">#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk </span></div>
|
||
<div class="line"><a id="l04728" name="l04728"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cee5f9332b40105e0594c546910a2e2"> 4728</a></span><span class="preprocessor">#define CAN_F6R2_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l04729" name="l04729"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab107baf898c53eca495a0cec40383c4a"> 4729</a></span><span class="preprocessor">#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l04730" name="l04730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53f5717aca9932255049b133661765bf"> 4730</a></span><span class="preprocessor">#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk </span></div>
|
||
<div class="line"><a id="l04731" name="l04731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4ca498cfaea259d91ac4f15692a3bcc"> 4731</a></span><span class="preprocessor">#define CAN_F6R2_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l04732" name="l04732"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacec3cbdfadb57b83f4a10629f5ff93a6"> 4732</a></span><span class="preprocessor">#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l04733" name="l04733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ec93958e936379d891bc3450dba3d1d"> 4733</a></span><span class="preprocessor">#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk </span></div>
|
||
<div class="line"><a id="l04734" name="l04734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f8b7c262d5a1e51c7cd479cf7a47719"> 4734</a></span><span class="preprocessor">#define CAN_F6R2_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l04735" name="l04735"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecb8cf6a22127fde7bbef7da331362fa"> 4735</a></span><span class="preprocessor">#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l04736" name="l04736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f97c7eb9d6e69d589db38d745ae321c"> 4736</a></span><span class="preprocessor">#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk </span></div>
|
||
<div class="line"><a id="l04737" name="l04737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2541190f9817b863fcaea7925a9ab152"> 4737</a></span><span class="preprocessor">#define CAN_F6R2_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l04738" name="l04738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1625345e2205b59ee47e4522833a023f"> 4738</a></span><span class="preprocessor">#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l04739" name="l04739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga372ebb5d42d147d41688f7c0fcf467d2"> 4739</a></span><span class="preprocessor">#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk </span></div>
|
||
<div class="line"><a id="l04740" name="l04740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga681ae7ccefdd04ea0b9fac2b6d8ce2c7"> 4740</a></span><span class="preprocessor">#define CAN_F6R2_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l04741" name="l04741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6ee3ac5a1ecd2c3e5a1805bbcfe6611"> 4741</a></span><span class="preprocessor">#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l04742" name="l04742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47baa2c9c05c7c422a49994b8f80016f"> 4742</a></span><span class="preprocessor">#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk </span></div>
|
||
<div class="line"><a id="l04743" name="l04743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a088bdcb4c43b019ccc2916cefc597c"> 4743</a></span><span class="preprocessor">#define CAN_F6R2_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l04744" name="l04744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacbaa9f91a1fc5474ecf6e149dbd309d"> 4744</a></span><span class="preprocessor">#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l04745" name="l04745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55d7665b118e98586c2a9b1900ce7292"> 4745</a></span><span class="preprocessor">#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk </span></div>
|
||
<div class="line"><a id="l04746" name="l04746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1041051f130d6cccb3b866a899bbd865"> 4746</a></span><span class="preprocessor">#define CAN_F6R2_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l04747" name="l04747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7899cda2b27c9f78f33a3050f975a22"> 4747</a></span><span class="preprocessor">#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l04748" name="l04748"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5095a203d07244e75dd6deca125b4468"> 4748</a></span><span class="preprocessor">#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk </span></div>
|
||
<div class="line"><a id="l04749" name="l04749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf408b8462d783790125f047604eb7201"> 4749</a></span><span class="preprocessor">#define CAN_F6R2_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l04750" name="l04750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae07a6c5c781e5f858d27a824a3228ad6"> 4750</a></span><span class="preprocessor">#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l04751" name="l04751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga533dbb10e8fce9aa6ec23573fb49c339"> 4751</a></span><span class="preprocessor">#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk </span></div>
|
||
<div class="line"><a id="l04752" name="l04752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga116e5b298af1faddc25c9a2be1c0f2bf"> 4752</a></span><span class="preprocessor">#define CAN_F6R2_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l04753" name="l04753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada5ad2ab34322414451520650bf405b8"> 4753</a></span><span class="preprocessor">#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l04754" name="l04754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b95be922291e534609302c0c833f1f7"> 4754</a></span><span class="preprocessor">#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk </span></div>
|
||
<div class="line"><a id="l04755" name="l04755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac87bd58b70908b22b5fd39b0a62a95a3"> 4755</a></span><span class="preprocessor">#define CAN_F6R2_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l04756" name="l04756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8109424b373ae93010f98f0c7ad80e5c"> 4756</a></span><span class="preprocessor">#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l04757" name="l04757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17301d50c7b6ad30ffc05ee2c63f6171"> 4757</a></span><span class="preprocessor">#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk </span></div>
|
||
<div class="line"><a id="l04758" name="l04758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2636cde6a4bc3ba023bc4c0fe5de75b4"> 4758</a></span><span class="preprocessor">#define CAN_F6R2_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l04759" name="l04759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5a59865040cac5815a6a4099e72e0e4"> 4759</a></span><span class="preprocessor">#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l04760" name="l04760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf23dfb03247544122ed01472b8a31b4d"> 4760</a></span><span class="preprocessor">#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk </span></div>
|
||
<div class="line"><a id="l04761" name="l04761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab93f20ff2225a03f65492b6e5d499ddb"> 4761</a></span><span class="preprocessor">#define CAN_F6R2_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l04762" name="l04762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd1ca2f91f8ea1af952b18ebd27dc725"> 4762</a></span><span class="preprocessor">#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l04763" name="l04763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf8d35fbfa677fc446da68f4043b633e"> 4763</a></span><span class="preprocessor">#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk </span></div>
|
||
<div class="line"><a id="l04764" name="l04764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga362d1f3ea3b3bfb78fc3ccb70b813de0"> 4764</a></span><span class="preprocessor">#define CAN_F6R2_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l04765" name="l04765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3c4bcd69ad9af4bd97c63269e95278a"> 4765</a></span><span class="preprocessor">#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l04766" name="l04766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c81a1972ec8d87421c6113bb9747c3e"> 4766</a></span><span class="preprocessor">#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk </span></div>
|
||
<div class="line"><a id="l04767" name="l04767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a05fd66da3b0a785893d7e4ae4c38ec"> 4767</a></span><span class="preprocessor">#define CAN_F6R2_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l04768" name="l04768"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b19c8600e4c828eab5759dae7cf2fc5"> 4768</a></span><span class="preprocessor">#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l04769" name="l04769"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11ea1bd4bae8b27a5fd73d210eb83d39"> 4769</a></span><span class="preprocessor">#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk </span></div>
|
||
<div class="line"><a id="l04770" name="l04770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga126bec7490158480e1c8011828bc900b"> 4770</a></span><span class="preprocessor">#define CAN_F6R2_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l04771" name="l04771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21e7a0134b94773f327e99d20877707b"> 4771</a></span><span class="preprocessor">#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l04772" name="l04772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c48dcd1ac5e23827813ed695bdff0d1"> 4772</a></span><span class="preprocessor">#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk </span></div>
|
||
<div class="line"><a id="l04773" name="l04773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga003e56f189cb2d03ceb4d86ebbfb1a96"> 4773</a></span><span class="preprocessor">#define CAN_F6R2_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l04774" name="l04774"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga049c4c90a51a7370af5575dd2ce43b25"> 4774</a></span><span class="preprocessor">#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l04775" name="l04775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd115d29d9f0a8fddc13a32c013af26b"> 4775</a></span><span class="preprocessor">#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk </span></div>
|
||
<div class="line"><a id="l04776" name="l04776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga178f147b77209ef59f0d73059ff40734"> 4776</a></span><span class="preprocessor">#define CAN_F6R2_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l04777" name="l04777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70456f1faf630198eb6a6aa9d014465b"> 4777</a></span><span class="preprocessor">#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l04778" name="l04778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3f116b2e31dd40bcdd6617fee83907e"> 4778</a></span><span class="preprocessor">#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk </span></div>
|
||
<div class="line"><a id="l04779" name="l04779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga252f65a784a6e484323ecbb340a06540"> 4779</a></span><span class="preprocessor">#define CAN_F6R2_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l04780" name="l04780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1523937cea2319fb9c692056b8599861"> 4780</a></span><span class="preprocessor">#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l04781" name="l04781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga090da76d2d9379dbfc54f7c3fcf69fe4"> 4781</a></span><span class="preprocessor">#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk </span></div>
|
||
<div class="line"><a id="l04782" name="l04782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e75f6bf8e5658bb7539704812be0267"> 4782</a></span><span class="preprocessor">#define CAN_F6R2_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l04783" name="l04783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b080d0ae18594e56bc64fa67e298d6d"> 4783</a></span><span class="preprocessor">#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l04784" name="l04784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9c8a59a8065400f4a75be49a78e2a9e"> 4784</a></span><span class="preprocessor">#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk </span></div>
|
||
<div class="line"><a id="l04785" name="l04785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac10f8f8e4e72fae0d0b8f910c1fe96d9"> 4785</a></span><span class="preprocessor">#define CAN_F6R2_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l04786" name="l04786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb8abbda99bc68f0dcfe984ee985bd5d"> 4786</a></span><span class="preprocessor">#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l04787" name="l04787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3854a1a11c72e64d3c4722494f463421"> 4787</a></span><span class="preprocessor">#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk </span></div>
|
||
<div class="line"><a id="l04788" name="l04788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga266f93b0c8f656140718c98f2c93d0bd"> 4788</a></span><span class="preprocessor">#define CAN_F6R2_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l04789" name="l04789"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5cf38e7dad669f04679189c848749f3"> 4789</a></span><span class="preprocessor">#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l04790" name="l04790"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b5ceb9d7ae0c6e34490b8d8659919c9"> 4790</a></span><span class="preprocessor">#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk </span></div>
|
||
<div class="line"><a id="l04791" name="l04791"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ef9ca5e08378882d65e1f754e8b197c"> 4791</a></span><span class="preprocessor">#define CAN_F6R2_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l04792" name="l04792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga607397b46ace68583b5b13f6d6f23cb7"> 4792</a></span><span class="preprocessor">#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l04793" name="l04793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac01a4accedd624ceccf8f8976a043177"> 4793</a></span><span class="preprocessor">#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk </span></div>
|
||
<div class="line"><a id="l04794" name="l04794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea647666f32db62170873fb233f9eeda"> 4794</a></span><span class="preprocessor">#define CAN_F6R2_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l04795" name="l04795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed265f9447716d0d3bc7dad1a295630c"> 4795</a></span><span class="preprocessor">#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l04796" name="l04796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc2d754207055a5a87696eb1bb7d8cae"> 4796</a></span><span class="preprocessor">#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk </span></div>
|
||
<div class="line"><a id="l04797" name="l04797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68de26372621969702f54818909e3d45"> 4797</a></span><span class="preprocessor">#define CAN_F6R2_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l04798" name="l04798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61e13bb0d4c0c6e131e3989c5a5d88b0"> 4798</a></span><span class="preprocessor">#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l04799" name="l04799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga471631ee112af3bde77d848c22d743ef"> 4799</a></span><span class="preprocessor">#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk </span></div>
|
||
<div class="line"><a id="l04800" name="l04800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e57f1bffaa844b03cdb0743f9b78c2b"> 4800</a></span><span class="preprocessor">#define CAN_F6R2_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l04801" name="l04801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ef6901cea91b3ea9b40c0d40980f554"> 4801</a></span><span class="preprocessor">#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l04802" name="l04802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9574ec7dddcea6b80368778c01f62598"> 4802</a></span><span class="preprocessor">#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk </span></div>
|
||
<div class="line"><a id="l04803" name="l04803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga245979ba9e0a5c2d545fae929eb99892"> 4803</a></span><span class="preprocessor">#define CAN_F6R2_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l04804" name="l04804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf6098323e8ea2d82b3dd9b355977d6b"> 4804</a></span><span class="preprocessor">#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l04805" name="l04805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64bcb159347ad8e2a2609ce89ed030df"> 4805</a></span><span class="preprocessor">#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk </span></div>
|
||
<div class="line"><a id="l04807" name="l04807"></a><span class="lineno"> 4807</span><span class="comment">/******************* Bit definition for CAN_F7R2 register *******************/</span></div>
|
||
<div class="line"><a id="l04808" name="l04808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f4317b3af8e10a0d4b70433d705208f"> 4808</a></span><span class="preprocessor">#define CAN_F7R2_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l04809" name="l04809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7e6ac71d87a53fb60da7f7d7bb4a31c"> 4809</a></span><span class="preprocessor">#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l04810" name="l04810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec0803330590bf9aba9d09342034b2c1"> 4810</a></span><span class="preprocessor">#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk </span></div>
|
||
<div class="line"><a id="l04811" name="l04811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24c69591a6d5b2f86f6e57027640dd73"> 4811</a></span><span class="preprocessor">#define CAN_F7R2_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l04812" name="l04812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac046be844d45ddd93b750c2b3fdeffb5"> 4812</a></span><span class="preprocessor">#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l04813" name="l04813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c633d4cbfdf79f09ae1df5e75c98439"> 4813</a></span><span class="preprocessor">#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk </span></div>
|
||
<div class="line"><a id="l04814" name="l04814"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91c5dc8630c3f5d987bdbd9000dbde85"> 4814</a></span><span class="preprocessor">#define CAN_F7R2_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l04815" name="l04815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae222910542a55154e8b02affd43c1bb1"> 4815</a></span><span class="preprocessor">#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l04816" name="l04816"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31a0c4ece8b73760ad295344b8558ddb"> 4816</a></span><span class="preprocessor">#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk </span></div>
|
||
<div class="line"><a id="l04817" name="l04817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86e2b7893638f3661915edb722d2adde"> 4817</a></span><span class="preprocessor">#define CAN_F7R2_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l04818" name="l04818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf47bc62b248184ab11796b147fd12fa4"> 4818</a></span><span class="preprocessor">#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l04819" name="l04819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe2fc15309540b87538ea3e8460d8d11"> 4819</a></span><span class="preprocessor">#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk </span></div>
|
||
<div class="line"><a id="l04820" name="l04820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8f96b4a3fa62b12e2529a91b67f1f4c"> 4820</a></span><span class="preprocessor">#define CAN_F7R2_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l04821" name="l04821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6532dbd923dbc1ae43394d64065b01f9"> 4821</a></span><span class="preprocessor">#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l04822" name="l04822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac81d4c021f4579021ddf9485472a84f5"> 4822</a></span><span class="preprocessor">#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk </span></div>
|
||
<div class="line"><a id="l04823" name="l04823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga996bd937bc577755b88acdaee8493640"> 4823</a></span><span class="preprocessor">#define CAN_F7R2_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l04824" name="l04824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga791664168f6ee37eea4331bf0f17f878"> 4824</a></span><span class="preprocessor">#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l04825" name="l04825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5dd6a00bb403a3e19e66c68f5ee308e2"> 4825</a></span><span class="preprocessor">#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk </span></div>
|
||
<div class="line"><a id="l04826" name="l04826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fcf07c4563ff3e099d9d88926d135d5"> 4826</a></span><span class="preprocessor">#define CAN_F7R2_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l04827" name="l04827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f12b37158633c7274a01feacbf342c6"> 4827</a></span><span class="preprocessor">#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l04828" name="l04828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b5eaf37458d0426fd7f847775fd41e9"> 4828</a></span><span class="preprocessor">#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk </span></div>
|
||
<div class="line"><a id="l04829" name="l04829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe34ced987191e7acda093c4b726148d"> 4829</a></span><span class="preprocessor">#define CAN_F7R2_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l04830" name="l04830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae323bdff49096a4afee6dec3d9d9aebd"> 4830</a></span><span class="preprocessor">#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l04831" name="l04831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga780440ce173cde12fd117b519419424c"> 4831</a></span><span class="preprocessor">#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk </span></div>
|
||
<div class="line"><a id="l04832" name="l04832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c5cd0875fa5ecc52ab306eb47020388"> 4832</a></span><span class="preprocessor">#define CAN_F7R2_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l04833" name="l04833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ec8c5b0a88b30a17f9afb284bcc95c1"> 4833</a></span><span class="preprocessor">#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l04834" name="l04834"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99ae0e27d14b42fef4551d83ee88b4ac"> 4834</a></span><span class="preprocessor">#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk </span></div>
|
||
<div class="line"><a id="l04835" name="l04835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae07c159d533af5bd5d2a6733db52e400"> 4835</a></span><span class="preprocessor">#define CAN_F7R2_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l04836" name="l04836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf18ed7d215a3e4a3ebbca297626877c"> 4836</a></span><span class="preprocessor">#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l04837" name="l04837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace90c0624446480421fac233739413dc"> 4837</a></span><span class="preprocessor">#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk </span></div>
|
||
<div class="line"><a id="l04838" name="l04838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bc252c24c4748c4596a5fbd9bcff7b1"> 4838</a></span><span class="preprocessor">#define CAN_F7R2_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l04839" name="l04839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81766a9d745aeadd4ba0a34d3ded18e7"> 4839</a></span><span class="preprocessor">#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l04840" name="l04840"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae60d566699df87580584ed496681562"> 4840</a></span><span class="preprocessor">#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk </span></div>
|
||
<div class="line"><a id="l04841" name="l04841"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14f3c2bf58159e154369752dae336477"> 4841</a></span><span class="preprocessor">#define CAN_F7R2_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l04842" name="l04842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33730db505f710ba327f8c6c1f04da4f"> 4842</a></span><span class="preprocessor">#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l04843" name="l04843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6325b37cc369b92b2334e482dbe3bf06"> 4843</a></span><span class="preprocessor">#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk </span></div>
|
||
<div class="line"><a id="l04844" name="l04844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1f505ec544d393c5f905b294bce4401"> 4844</a></span><span class="preprocessor">#define CAN_F7R2_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l04845" name="l04845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02c278c9bfd9314c34ac6da260c08403"> 4845</a></span><span class="preprocessor">#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l04846" name="l04846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace846d293ac11d535ee2aad17cf099bc"> 4846</a></span><span class="preprocessor">#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk </span></div>
|
||
<div class="line"><a id="l04847" name="l04847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac30df90b8299022e421c729f7088cf11"> 4847</a></span><span class="preprocessor">#define CAN_F7R2_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l04848" name="l04848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40fec0160eec943f81f05ad9d48ce9b2"> 4848</a></span><span class="preprocessor">#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l04849" name="l04849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91b26397a75fc4c0124e84903d31221e"> 4849</a></span><span class="preprocessor">#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk </span></div>
|
||
<div class="line"><a id="l04850" name="l04850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8eb41c28b8059b9d0f25f05341cff65"> 4850</a></span><span class="preprocessor">#define CAN_F7R2_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l04851" name="l04851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga906faed52246a867bbe9675b588c2fe0"> 4851</a></span><span class="preprocessor">#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l04852" name="l04852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada2e01c05c216ba6ff4756d043297c0e"> 4852</a></span><span class="preprocessor">#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk </span></div>
|
||
<div class="line"><a id="l04853" name="l04853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66ab5a2d62ff7650618d15f893046efa"> 4853</a></span><span class="preprocessor">#define CAN_F7R2_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l04854" name="l04854"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf54c82654d230ba010300b9b879f606"> 4854</a></span><span class="preprocessor">#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l04855" name="l04855"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeef08aa6565ff24bd9863b4b8a9c2ff5"> 4855</a></span><span class="preprocessor">#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk </span></div>
|
||
<div class="line"><a id="l04856" name="l04856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14b6874b4f61096d8e2f21efddb07831"> 4856</a></span><span class="preprocessor">#define CAN_F7R2_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l04857" name="l04857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac23ba211219c2ece524f3867e2b1cc4e"> 4857</a></span><span class="preprocessor">#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l04858" name="l04858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16c3ccb033b9541b57c338b9737f18dd"> 4858</a></span><span class="preprocessor">#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk </span></div>
|
||
<div class="line"><a id="l04859" name="l04859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9070f003ab14a0a9e619c82acc6d357f"> 4859</a></span><span class="preprocessor">#define CAN_F7R2_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l04860" name="l04860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga714ba087c8c662749a5e1db9f82af81d"> 4860</a></span><span class="preprocessor">#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l04861" name="l04861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad898ca382f57efb1842884d46217245c"> 4861</a></span><span class="preprocessor">#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk </span></div>
|
||
<div class="line"><a id="l04862" name="l04862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69277e05f3cfeb8c75d9b008c7db5d37"> 4862</a></span><span class="preprocessor">#define CAN_F7R2_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l04863" name="l04863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga228a38b1060b3ff498d35aed4e128917"> 4863</a></span><span class="preprocessor">#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l04864" name="l04864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf419938e132cc1a0bf59a6c058e2c7c5"> 4864</a></span><span class="preprocessor">#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk </span></div>
|
||
<div class="line"><a id="l04865" name="l04865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6251821d862bf793711e13753c7ae5a"> 4865</a></span><span class="preprocessor">#define CAN_F7R2_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l04866" name="l04866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4893f06f2a927a5e1a38e9faf3edb90"> 4866</a></span><span class="preprocessor">#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l04867" name="l04867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae991abb6f2e64443be7e39633f192aba"> 4867</a></span><span class="preprocessor">#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk </span></div>
|
||
<div class="line"><a id="l04868" name="l04868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb34c2b052df01aa362473d670d42ed0"> 4868</a></span><span class="preprocessor">#define CAN_F7R2_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l04869" name="l04869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9074bda7aca4edf2e11e8125a57cbc5a"> 4869</a></span><span class="preprocessor">#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l04870" name="l04870"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3738a42e2767c928de21a2f784ce6bce"> 4870</a></span><span class="preprocessor">#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk </span></div>
|
||
<div class="line"><a id="l04871" name="l04871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d955eb8acf2decac2bd58e6746fd407"> 4871</a></span><span class="preprocessor">#define CAN_F7R2_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l04872" name="l04872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8dacdf1e167c8a3f7509e4ddf5757e1"> 4872</a></span><span class="preprocessor">#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l04873" name="l04873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5cb252582e6b7bd706b37447f71d6cd"> 4873</a></span><span class="preprocessor">#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk </span></div>
|
||
<div class="line"><a id="l04874" name="l04874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade58525a8af1d2246aea9a8f494dc3a7"> 4874</a></span><span class="preprocessor">#define CAN_F7R2_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l04875" name="l04875"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad37f85aab2fa384e5d0643b17eae8440"> 4875</a></span><span class="preprocessor">#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l04876" name="l04876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae616e53b9d961571eea4ff2df31f8399"> 4876</a></span><span class="preprocessor">#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk </span></div>
|
||
<div class="line"><a id="l04877" name="l04877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa07aee43f61765d654ba4f1a965c3d15"> 4877</a></span><span class="preprocessor">#define CAN_F7R2_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l04878" name="l04878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad01aed48c87877406fcd8a0da994b8b6"> 4878</a></span><span class="preprocessor">#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l04879" name="l04879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2049c9bb27af3cde01334b1901aa417"> 4879</a></span><span class="preprocessor">#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk </span></div>
|
||
<div class="line"><a id="l04880" name="l04880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed455c42e4814928236cee53101a2863"> 4880</a></span><span class="preprocessor">#define CAN_F7R2_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l04881" name="l04881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3274b8fc32c7104c1ae6015fe725c63b"> 4881</a></span><span class="preprocessor">#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l04882" name="l04882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e69c2fd32e2c523c9e939df825fc605"> 4882</a></span><span class="preprocessor">#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk </span></div>
|
||
<div class="line"><a id="l04883" name="l04883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebdd728474eecad67ed5816c533f575b"> 4883</a></span><span class="preprocessor">#define CAN_F7R2_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l04884" name="l04884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ee9ad1b18fe010798526b61b23773b7"> 4884</a></span><span class="preprocessor">#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l04885" name="l04885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga659cc84b9186e279c37e88b94e1c9829"> 4885</a></span><span class="preprocessor">#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk </span></div>
|
||
<div class="line"><a id="l04886" name="l04886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68cc77bf1d501625c5e639909e29c118"> 4886</a></span><span class="preprocessor">#define CAN_F7R2_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l04887" name="l04887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga649a2979cf8c968b94a82ade9eb7aa77"> 4887</a></span><span class="preprocessor">#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l04888" name="l04888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43c9da5ad4c2d261858f73b779cc3dae"> 4888</a></span><span class="preprocessor">#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk </span></div>
|
||
<div class="line"><a id="l04889" name="l04889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d61a9597fe302aa59b1bf6944f69aad"> 4889</a></span><span class="preprocessor">#define CAN_F7R2_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l04890" name="l04890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga005b8dfa3d1f6eb19c33deed337fab12"> 4890</a></span><span class="preprocessor">#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l04891" name="l04891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a1ea8d66ada6cea7268fba151c00d91"> 4891</a></span><span class="preprocessor">#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk </span></div>
|
||
<div class="line"><a id="l04892" name="l04892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga317154057e36bcfb50408ffa8c106559"> 4892</a></span><span class="preprocessor">#define CAN_F7R2_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l04893" name="l04893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadaa906c94d6d83a7a5c1d8645e814fa3"> 4893</a></span><span class="preprocessor">#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l04894" name="l04894"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbd6032652515423412ad73b8a004bbb"> 4894</a></span><span class="preprocessor">#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk </span></div>
|
||
<div class="line"><a id="l04895" name="l04895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ed2a1e8330f343d50d3ead9b7426715"> 4895</a></span><span class="preprocessor">#define CAN_F7R2_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l04896" name="l04896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd1f2f87a2de3ef977b9f042559110f7"> 4896</a></span><span class="preprocessor">#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l04897" name="l04897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a991a0bb5a81748b091d6b96c59fc37"> 4897</a></span><span class="preprocessor">#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk </span></div>
|
||
<div class="line"><a id="l04898" name="l04898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa60296ad3c0c0597363499038128c431"> 4898</a></span><span class="preprocessor">#define CAN_F7R2_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l04899" name="l04899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac67c413d3294aa6762edf76c05352d13"> 4899</a></span><span class="preprocessor">#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l04900" name="l04900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedae5e816af0dd734311bf44be7571f2"> 4900</a></span><span class="preprocessor">#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk </span></div>
|
||
<div class="line"><a id="l04901" name="l04901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b8852c12eaf0286767bf738087f5774"> 4901</a></span><span class="preprocessor">#define CAN_F7R2_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l04902" name="l04902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d0df32a1bad3f616506614c53de9a18"> 4902</a></span><span class="preprocessor">#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l04903" name="l04903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f88a239b8a39ff3343b1cfe70b06139"> 4903</a></span><span class="preprocessor">#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk </span></div>
|
||
<div class="line"><a id="l04905" name="l04905"></a><span class="lineno"> 4905</span><span class="comment">/******************* Bit definition for CAN_F8R2 register *******************/</span></div>
|
||
<div class="line"><a id="l04906" name="l04906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga272fec3946dc588a9c312573c358a162"> 4906</a></span><span class="preprocessor">#define CAN_F8R2_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l04907" name="l04907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a5424a898996971be642271b0cb305d"> 4907</a></span><span class="preprocessor">#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l04908" name="l04908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cfe399fb494ff6ab1d5b91258c42764"> 4908</a></span><span class="preprocessor">#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk </span></div>
|
||
<div class="line"><a id="l04909" name="l04909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d5a712e64c1b04b7114f562f2605e87"> 4909</a></span><span class="preprocessor">#define CAN_F8R2_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l04910" name="l04910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4bdeb68c24f386e0181eb04937cf109"> 4910</a></span><span class="preprocessor">#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l04911" name="l04911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ca04b514b4d6a3b19619932513b8953"> 4911</a></span><span class="preprocessor">#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk </span></div>
|
||
<div class="line"><a id="l04912" name="l04912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5cead607181f44f52c174e67034ea71"> 4912</a></span><span class="preprocessor">#define CAN_F8R2_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l04913" name="l04913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad180babb8dfebb2d725c57d12ee6c434"> 4913</a></span><span class="preprocessor">#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l04914" name="l04914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4c3c099bf7db702b7bf5f71cddaaec2"> 4914</a></span><span class="preprocessor">#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk </span></div>
|
||
<div class="line"><a id="l04915" name="l04915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b2a97e11174175e038a5e49de693d81"> 4915</a></span><span class="preprocessor">#define CAN_F8R2_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l04916" name="l04916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b411230765103ce07b48d181683a8ff"> 4916</a></span><span class="preprocessor">#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l04917" name="l04917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1e53037e7f7171d8a7358590f0e7420"> 4917</a></span><span class="preprocessor">#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk </span></div>
|
||
<div class="line"><a id="l04918" name="l04918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08ad27ee47d20cf06c110a7a921f6bb1"> 4918</a></span><span class="preprocessor">#define CAN_F8R2_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l04919" name="l04919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f5f223e200cbe85d62785c1c1411780"> 4919</a></span><span class="preprocessor">#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l04920" name="l04920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51e2af45725e06538c4d09ad07296316"> 4920</a></span><span class="preprocessor">#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk </span></div>
|
||
<div class="line"><a id="l04921" name="l04921"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga102d50c9df36acfccfadb2129cc7e933"> 4921</a></span><span class="preprocessor">#define CAN_F8R2_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l04922" name="l04922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga715b276f569abd0659cef3d6041ca97f"> 4922</a></span><span class="preprocessor">#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l04923" name="l04923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ee5e9d68190f0d41a5b8603d1933922"> 4923</a></span><span class="preprocessor">#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk </span></div>
|
||
<div class="line"><a id="l04924" name="l04924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5650f6465760671e23d1ba17e7d1a9fb"> 4924</a></span><span class="preprocessor">#define CAN_F8R2_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l04925" name="l04925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bc83f8b713c699af6c4a058d97a0212"> 4925</a></span><span class="preprocessor">#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l04926" name="l04926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66c636150cfad43a32652dba3ded8383"> 4926</a></span><span class="preprocessor">#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk </span></div>
|
||
<div class="line"><a id="l04927" name="l04927"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6913723330621f154c8c69d67fc8eabf"> 4927</a></span><span class="preprocessor">#define CAN_F8R2_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l04928" name="l04928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b34be24a3201f24c3c5fb3e4518496a"> 4928</a></span><span class="preprocessor">#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l04929" name="l04929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fc81a4ee32f76ce3a6fdbb3fc49425c"> 4929</a></span><span class="preprocessor">#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk </span></div>
|
||
<div class="line"><a id="l04930" name="l04930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e6f7d79c9bcd9461cca14ea772df10e"> 4930</a></span><span class="preprocessor">#define CAN_F8R2_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l04931" name="l04931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga246521830f06fc6e78fa76e3460c0c90"> 4931</a></span><span class="preprocessor">#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l04932" name="l04932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68a36336242e8259c779f1c8f4544737"> 4932</a></span><span class="preprocessor">#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk </span></div>
|
||
<div class="line"><a id="l04933" name="l04933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9ccf2f0df421c8136a57c0c60a28bd9"> 4933</a></span><span class="preprocessor">#define CAN_F8R2_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l04934" name="l04934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga109bccb45d80c850a1753d91810b17e6"> 4934</a></span><span class="preprocessor">#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l04935" name="l04935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0014717b3c4c65afb7542308980803d"> 4935</a></span><span class="preprocessor">#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk </span></div>
|
||
<div class="line"><a id="l04936" name="l04936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9536c00d19421f818bf61a281ca53852"> 4936</a></span><span class="preprocessor">#define CAN_F8R2_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l04937" name="l04937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4781d01da4573f59d5bf3d87e3f55c3"> 4937</a></span><span class="preprocessor">#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l04938" name="l04938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga315a7e30b95c05db01b7f56f4d825e62"> 4938</a></span><span class="preprocessor">#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk </span></div>
|
||
<div class="line"><a id="l04939" name="l04939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2c8b3acb216b4a20646195872c91cc3"> 4939</a></span><span class="preprocessor">#define CAN_F8R2_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l04940" name="l04940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34eab8d93d53237b1f29ca2989602250"> 4940</a></span><span class="preprocessor">#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l04941" name="l04941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga353aad2279bf6b72bd861f6c79253635"> 4941</a></span><span class="preprocessor">#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk </span></div>
|
||
<div class="line"><a id="l04942" name="l04942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35aa0762c3b9e705075fb629b92f3d52"> 4942</a></span><span class="preprocessor">#define CAN_F8R2_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l04943" name="l04943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee44ebdb7cb153d4776813386c72d379"> 4943</a></span><span class="preprocessor">#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l04944" name="l04944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25193c4b44d05db08ba40f0e0f2c45e1"> 4944</a></span><span class="preprocessor">#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk </span></div>
|
||
<div class="line"><a id="l04945" name="l04945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0af605c2d87e6f02f3bfee167a40b818"> 4945</a></span><span class="preprocessor">#define CAN_F8R2_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l04946" name="l04946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a533bc42a75cb20b6d2225af3259335"> 4946</a></span><span class="preprocessor">#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l04947" name="l04947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4469bfc90525f84d9d04d3a4996997e6"> 4947</a></span><span class="preprocessor">#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk </span></div>
|
||
<div class="line"><a id="l04948" name="l04948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52e8448ddc34d6068dad3607d6485056"> 4948</a></span><span class="preprocessor">#define CAN_F8R2_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l04949" name="l04949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5d8dd791898a26610ad5c99e04c7b85"> 4949</a></span><span class="preprocessor">#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l04950" name="l04950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b17ebf3dd1e53d8417f955ebcf743b3"> 4950</a></span><span class="preprocessor">#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk </span></div>
|
||
<div class="line"><a id="l04951" name="l04951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f802cc15926cffb97f3a6bc7642501d"> 4951</a></span><span class="preprocessor">#define CAN_F8R2_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l04952" name="l04952"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9a10d9b3c535b4c04f30d1976a74003"> 4952</a></span><span class="preprocessor">#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l04953" name="l04953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6db6c2262434fc76213a441d8ce2edf1"> 4953</a></span><span class="preprocessor">#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk </span></div>
|
||
<div class="line"><a id="l04954" name="l04954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7064892926519c2643608a52959b7d19"> 4954</a></span><span class="preprocessor">#define CAN_F8R2_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l04955" name="l04955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79a44278629e098fdeefef5c6e699a21"> 4955</a></span><span class="preprocessor">#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l04956" name="l04956"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a1e1e9aa84af36845402d19236c1214"> 4956</a></span><span class="preprocessor">#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk </span></div>
|
||
<div class="line"><a id="l04957" name="l04957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7b91a4fcae3e6ffb8acace86ba3106a"> 4957</a></span><span class="preprocessor">#define CAN_F8R2_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l04958" name="l04958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga743f3fc9128154a5e10a49378b39dde0"> 4958</a></span><span class="preprocessor">#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l04959" name="l04959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0a9ee665444a6b42e98e0f988d1ba7a"> 4959</a></span><span class="preprocessor">#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk </span></div>
|
||
<div class="line"><a id="l04960" name="l04960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49483e1f9418b80826fb30374977b711"> 4960</a></span><span class="preprocessor">#define CAN_F8R2_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l04961" name="l04961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6355102db61d562b19aea995401360f5"> 4961</a></span><span class="preprocessor">#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l04962" name="l04962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16cde37565a3d3ec3a8c41013df6f6f1"> 4962</a></span><span class="preprocessor">#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk </span></div>
|
||
<div class="line"><a id="l04963" name="l04963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0718c73bddee55cbf8c17f5e5393982"> 4963</a></span><span class="preprocessor">#define CAN_F8R2_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l04964" name="l04964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fd103af2e8859f67477580800625162"> 4964</a></span><span class="preprocessor">#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l04965" name="l04965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57ca000fea3be225ddf5f295437b6e36"> 4965</a></span><span class="preprocessor">#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk </span></div>
|
||
<div class="line"><a id="l04966" name="l04966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c8ae876dd909a399bd06bca0e991f9d"> 4966</a></span><span class="preprocessor">#define CAN_F8R2_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l04967" name="l04967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac32a8af72eea61e6976bb97fdff7fe51"> 4967</a></span><span class="preprocessor">#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l04968" name="l04968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad60ee9ebdce23be6d2adca113ca918e8"> 4968</a></span><span class="preprocessor">#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk </span></div>
|
||
<div class="line"><a id="l04969" name="l04969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36935ee8104559d55726f7a19ccc510e"> 4969</a></span><span class="preprocessor">#define CAN_F8R2_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l04970" name="l04970"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47bb6e52fcfdf43778db13faf53a6591"> 4970</a></span><span class="preprocessor">#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l04971" name="l04971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae186c9794783eb47b460532801afe43a"> 4971</a></span><span class="preprocessor">#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk </span></div>
|
||
<div class="line"><a id="l04972" name="l04972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad26f6f6f8960a65ceac0a9ffb52c075"> 4972</a></span><span class="preprocessor">#define CAN_F8R2_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l04973" name="l04973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d5d496538d2bf3157c80523c0c5fb45"> 4973</a></span><span class="preprocessor">#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l04974" name="l04974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga106a5e5b8ae8d683fcec85b076688f34"> 4974</a></span><span class="preprocessor">#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk </span></div>
|
||
<div class="line"><a id="l04975" name="l04975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6a23988caae50f093de7fd6ee0442fa"> 4975</a></span><span class="preprocessor">#define CAN_F8R2_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l04976" name="l04976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa768932cd5eef5a2ee54bfe8a0ac41ea"> 4976</a></span><span class="preprocessor">#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l04977" name="l04977"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1643a77c219a9b2706f438c5123bccc8"> 4977</a></span><span class="preprocessor">#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk </span></div>
|
||
<div class="line"><a id="l04978" name="l04978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3064ef4c61853f56528fb7649e723d4f"> 4978</a></span><span class="preprocessor">#define CAN_F8R2_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l04979" name="l04979"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0989578ce3e5a1a533853538f3b649ff"> 4979</a></span><span class="preprocessor">#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l04980" name="l04980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab21aa6ed09bed09347e07dbcbd0e9e93"> 4980</a></span><span class="preprocessor">#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk </span></div>
|
||
<div class="line"><a id="l04981" name="l04981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a918c2c68e3e3a6ed3208377e7eb11c"> 4981</a></span><span class="preprocessor">#define CAN_F8R2_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l04982" name="l04982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5a4af539b9ed1e260226c5a2f4c8242"> 4982</a></span><span class="preprocessor">#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l04983" name="l04983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8267e4cdc484abd75634469f9b255c5"> 4983</a></span><span class="preprocessor">#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk </span></div>
|
||
<div class="line"><a id="l04984" name="l04984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a749b77630a78e7ab323f7f7fcd1930"> 4984</a></span><span class="preprocessor">#define CAN_F8R2_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l04985" name="l04985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d064f4e04559c8ceeb38759b0332381"> 4985</a></span><span class="preprocessor">#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l04986" name="l04986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga697d286473e81666c91f28e853aab4ad"> 4986</a></span><span class="preprocessor">#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk </span></div>
|
||
<div class="line"><a id="l04987" name="l04987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cdc04f6f8ebf42d24d0ea4ad895205e"> 4987</a></span><span class="preprocessor">#define CAN_F8R2_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l04988" name="l04988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11bcaf39d0176157117636c373492ded"> 4988</a></span><span class="preprocessor">#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l04989" name="l04989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga295c26638700a849ee3c6504caf6ceab"> 4989</a></span><span class="preprocessor">#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk </span></div>
|
||
<div class="line"><a id="l04990" name="l04990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb1387b35a958f97ce27f663dfe35c06"> 4990</a></span><span class="preprocessor">#define CAN_F8R2_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l04991" name="l04991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b60416465405bc628ede32f1ca22221"> 4991</a></span><span class="preprocessor">#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l04992" name="l04992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f8469008983b405bfc5855258f4f6e6"> 4992</a></span><span class="preprocessor">#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk </span></div>
|
||
<div class="line"><a id="l04993" name="l04993"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga910e2428c8fa737c1779f3536d97bff1"> 4993</a></span><span class="preprocessor">#define CAN_F8R2_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l04994" name="l04994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae62518d43230d7fe0907da3068092020"> 4994</a></span><span class="preprocessor">#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l04995" name="l04995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad18d894a75ebe73c0185d905cfb81dbf"> 4995</a></span><span class="preprocessor">#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk </span></div>
|
||
<div class="line"><a id="l04996" name="l04996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae383ae7f7183c4fe7ce61ffb0e90b8aa"> 4996</a></span><span class="preprocessor">#define CAN_F8R2_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l04997" name="l04997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1cd28b7dd676bb4df664b0f4c886dba"> 4997</a></span><span class="preprocessor">#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l04998" name="l04998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccdf92a69572b56641ddd2967c034a7a"> 4998</a></span><span class="preprocessor">#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk </span></div>
|
||
<div class="line"><a id="l04999" name="l04999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45effc10b4b4f084d64ee099dee2537d"> 4999</a></span><span class="preprocessor">#define CAN_F8R2_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l05000" name="l05000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cdbb1cd26bdd6c1690ac3b208a27898"> 5000</a></span><span class="preprocessor">#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l05001" name="l05001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0636c9c9fd84e5e8d12e78f236f2a56c"> 5001</a></span><span class="preprocessor">#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk </span></div>
|
||
<div class="line"><a id="l05003" name="l05003"></a><span class="lineno"> 5003</span><span class="comment">/******************* Bit definition for CAN_F9R2 register *******************/</span></div>
|
||
<div class="line"><a id="l05004" name="l05004"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71fb77883884a56d1b3e9d2029007d02"> 5004</a></span><span class="preprocessor">#define CAN_F9R2_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05005" name="l05005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47309fd6134f2abe4e3b1b496093d9be"> 5005</a></span><span class="preprocessor">#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l05006" name="l05006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1209cec0d1199b7f74bb2e2b1cca424"> 5006</a></span><span class="preprocessor">#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk </span></div>
|
||
<div class="line"><a id="l05007" name="l05007"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1b8c8d47bf8d4009b79c69e629106d8"> 5007</a></span><span class="preprocessor">#define CAN_F9R2_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l05008" name="l05008"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfe55444ba47900acdea02a8e64db98b"> 5008</a></span><span class="preprocessor">#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l05009" name="l05009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fd983be0f74b7f183261f21cd2f6910"> 5009</a></span><span class="preprocessor">#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk </span></div>
|
||
<div class="line"><a id="l05010" name="l05010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36e5b680c042a6052bfd32e8ae58b221"> 5010</a></span><span class="preprocessor">#define CAN_F9R2_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l05011" name="l05011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e3aeaa699aed8591a458dbdb8fd3358"> 5011</a></span><span class="preprocessor">#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l05012" name="l05012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e363da951c1191e733a8bc603cda3f5"> 5012</a></span><span class="preprocessor">#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk </span></div>
|
||
<div class="line"><a id="l05013" name="l05013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c3e1cc66212316557b21298d3852b22"> 5013</a></span><span class="preprocessor">#define CAN_F9R2_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l05014" name="l05014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9bf0ad567bc6a89528616adb3d30cc0"> 5014</a></span><span class="preprocessor">#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l05015" name="l05015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabab5a59d405ae1684853988e95ab9844"> 5015</a></span><span class="preprocessor">#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk </span></div>
|
||
<div class="line"><a id="l05016" name="l05016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc1f6b4960d803c1e388f0f6a7525736"> 5016</a></span><span class="preprocessor">#define CAN_F9R2_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l05017" name="l05017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5010d303de1ed187fcf3d663cc5b7b3a"> 5017</a></span><span class="preprocessor">#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l05018" name="l05018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b5b46878001f43618c726b3429e4b50"> 5018</a></span><span class="preprocessor">#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk </span></div>
|
||
<div class="line"><a id="l05019" name="l05019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9555447cbcc79096f5ae9e132455e2c6"> 5019</a></span><span class="preprocessor">#define CAN_F9R2_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l05020" name="l05020"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga596e424fe2e4186174d148aeef611074"> 5020</a></span><span class="preprocessor">#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l05021" name="l05021"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga582895a48cfeb8d7ecf6c9757ba0aa39"> 5021</a></span><span class="preprocessor">#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk </span></div>
|
||
<div class="line"><a id="l05022" name="l05022"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0961df6b41382621852dc673c9101f39"> 5022</a></span><span class="preprocessor">#define CAN_F9R2_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l05023" name="l05023"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga652ee4940983c9766b517598ad270e1f"> 5023</a></span><span class="preprocessor">#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l05024" name="l05024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe18a44ac1a9c4cf2a6e94bb946af17f"> 5024</a></span><span class="preprocessor">#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk </span></div>
|
||
<div class="line"><a id="l05025" name="l05025"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f7b07d1129f4ea3727306744500577a"> 5025</a></span><span class="preprocessor">#define CAN_F9R2_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l05026" name="l05026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed416d6141752c65110daae0c617859a"> 5026</a></span><span class="preprocessor">#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l05027" name="l05027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae497ffa0ef246a52e57a394fa57e616d"> 5027</a></span><span class="preprocessor">#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk </span></div>
|
||
<div class="line"><a id="l05028" name="l05028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff37f998935141f0cb7203a5b74baeea"> 5028</a></span><span class="preprocessor">#define CAN_F9R2_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l05029" name="l05029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad301a470b47c85751c573fc3579d91a9"> 5029</a></span><span class="preprocessor">#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l05030" name="l05030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4eedc431183ceae7240d11afc05bacfa"> 5030</a></span><span class="preprocessor">#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk </span></div>
|
||
<div class="line"><a id="l05031" name="l05031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga232ef1a0d6455d0f6afe6ae0f7c5a911"> 5031</a></span><span class="preprocessor">#define CAN_F9R2_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l05032" name="l05032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa912a018c3cc0adcbeacd61b6e5871a6"> 5032</a></span><span class="preprocessor">#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l05033" name="l05033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71d1294050a77f52ecd4b00568cd7477"> 5033</a></span><span class="preprocessor">#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk </span></div>
|
||
<div class="line"><a id="l05034" name="l05034"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91dd86a4bf1da1e33c7b56503eebbd52"> 5034</a></span><span class="preprocessor">#define CAN_F9R2_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l05035" name="l05035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0f169b5d13d9d6d69d89d99c8451ebd"> 5035</a></span><span class="preprocessor">#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l05036" name="l05036"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5adc0ffeba391461d887f5d176a9b5bd"> 5036</a></span><span class="preprocessor">#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk </span></div>
|
||
<div class="line"><a id="l05037" name="l05037"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae624263208ca55d8690f216d3a4dfb78"> 5037</a></span><span class="preprocessor">#define CAN_F9R2_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l05038" name="l05038"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b87e7eba6f9fbe4a1e390599703e4ea"> 5038</a></span><span class="preprocessor">#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l05039" name="l05039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga989f1dea5a35e78b08649ac699955563"> 5039</a></span><span class="preprocessor">#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk </span></div>
|
||
<div class="line"><a id="l05040" name="l05040"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6860cb0d3b72432d7e35b0ade6a3d05"> 5040</a></span><span class="preprocessor">#define CAN_F9R2_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l05041" name="l05041"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b961aa158542f370fd755e37e3ebbf7"> 5041</a></span><span class="preprocessor">#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l05042" name="l05042"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b71e1b7db02ef8c5853534921b33aee"> 5042</a></span><span class="preprocessor">#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk </span></div>
|
||
<div class="line"><a id="l05043" name="l05043"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5031b931df96b65727ccbb5298e678c1"> 5043</a></span><span class="preprocessor">#define CAN_F9R2_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l05044" name="l05044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01e88250b1d9d44f23df2ddc46397574"> 5044</a></span><span class="preprocessor">#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l05045" name="l05045"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48cff2713910823bbf9c8aeb399d6695"> 5045</a></span><span class="preprocessor">#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk </span></div>
|
||
<div class="line"><a id="l05046" name="l05046"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88f67bd4804724913a1ace948970d584"> 5046</a></span><span class="preprocessor">#define CAN_F9R2_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l05047" name="l05047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2659b21a47fe2b7475163ef583622c7"> 5047</a></span><span class="preprocessor">#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l05048" name="l05048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9e0057c4eb0f7238d2ec98ae0702ff3"> 5048</a></span><span class="preprocessor">#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk </span></div>
|
||
<div class="line"><a id="l05049" name="l05049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69a42974dfe7527cbb7e2db8d402393b"> 5049</a></span><span class="preprocessor">#define CAN_F9R2_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l05050" name="l05050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga034e40bc2fcebd32d4d77b2b38c68dda"> 5050</a></span><span class="preprocessor">#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l05051" name="l05051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc16f71c9ee3bc56be17f7488c1df807"> 5051</a></span><span class="preprocessor">#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk </span></div>
|
||
<div class="line"><a id="l05052" name="l05052"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f2ba5f0426b80b58ec6842414929185"> 5052</a></span><span class="preprocessor">#define CAN_F9R2_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l05053" name="l05053"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacae78b5a3198b22b6590676496caa801"> 5053</a></span><span class="preprocessor">#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l05054" name="l05054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3909a33262113171b7d4dc11fcf8c3b1"> 5054</a></span><span class="preprocessor">#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk </span></div>
|
||
<div class="line"><a id="l05055" name="l05055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e3fde8ece69886d20cd8e258f981645"> 5055</a></span><span class="preprocessor">#define CAN_F9R2_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l05056" name="l05056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30db50cc21514e923c0bf91374491e91"> 5056</a></span><span class="preprocessor">#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l05057" name="l05057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cead3f8d10075aa34c9446859356e2d"> 5057</a></span><span class="preprocessor">#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk </span></div>
|
||
<div class="line"><a id="l05058" name="l05058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17263ecd2c5f80d8c32b697f375bff23"> 5058</a></span><span class="preprocessor">#define CAN_F9R2_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l05059" name="l05059"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac07c3cc02fa2a02058063f3fed95f97c"> 5059</a></span><span class="preprocessor">#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l05060" name="l05060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7730d43a2cf07a1568ed738a4f69692"> 5060</a></span><span class="preprocessor">#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk </span></div>
|
||
<div class="line"><a id="l05061" name="l05061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19083a2e70e921dcb5e560c236c19b97"> 5061</a></span><span class="preprocessor">#define CAN_F9R2_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l05062" name="l05062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga280fd7273494894b41cf8b3e05a94423"> 5062</a></span><span class="preprocessor">#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l05063" name="l05063"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b2f5ba8403cbd679694cf9665e2690f"> 5063</a></span><span class="preprocessor">#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk </span></div>
|
||
<div class="line"><a id="l05064" name="l05064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcd8dc4d422b78b03a7190665e89fc7d"> 5064</a></span><span class="preprocessor">#define CAN_F9R2_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l05065" name="l05065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ebf7e69a5cbb23be0d72df90d938455"> 5065</a></span><span class="preprocessor">#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l05066" name="l05066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca5a17ed59696ed0572b80767c4bef81"> 5066</a></span><span class="preprocessor">#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk </span></div>
|
||
<div class="line"><a id="l05067" name="l05067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ee45801f88c81aa88d1dcb0cb13da8d"> 5067</a></span><span class="preprocessor">#define CAN_F9R2_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l05068" name="l05068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29e80a00a8a175f05ccec5b2465f707f"> 5068</a></span><span class="preprocessor">#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l05069" name="l05069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac318672024cefb98843d473cbb2d46b2"> 5069</a></span><span class="preprocessor">#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk </span></div>
|
||
<div class="line"><a id="l05070" name="l05070"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a828c3ecaa65b06ed7262618009f645"> 5070</a></span><span class="preprocessor">#define CAN_F9R2_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l05071" name="l05071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae2e762f3d91189614712c5f708c13ec"> 5071</a></span><span class="preprocessor">#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l05072" name="l05072"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3523d55c8cf0a308fea4837b00f89abb"> 5072</a></span><span class="preprocessor">#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk </span></div>
|
||
<div class="line"><a id="l05073" name="l05073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac77e06fc859440775bed41060185f84d"> 5073</a></span><span class="preprocessor">#define CAN_F9R2_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l05074" name="l05074"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6411880c098bbbe9e746ae660f1d3643"> 5074</a></span><span class="preprocessor">#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l05075" name="l05075"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21d8d812323030dd39f417318c36b8dc"> 5075</a></span><span class="preprocessor">#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk </span></div>
|
||
<div class="line"><a id="l05076" name="l05076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e3da3cb77f9bab0b9688ee8ac1ead87"> 5076</a></span><span class="preprocessor">#define CAN_F9R2_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l05077" name="l05077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9112971db909b1bf0bd272c687ca44ba"> 5077</a></span><span class="preprocessor">#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l05078" name="l05078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga065bba6dde8a5b81b42c2618204bf0be"> 5078</a></span><span class="preprocessor">#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk </span></div>
|
||
<div class="line"><a id="l05079" name="l05079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga784ec53e7bab49da60d9ede528c85b17"> 5079</a></span><span class="preprocessor">#define CAN_F9R2_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l05080" name="l05080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a276cb2e015ee7b075eec7a16686ac3"> 5080</a></span><span class="preprocessor">#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l05081" name="l05081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade5290535026c192f7e94a4cb98e48b4"> 5081</a></span><span class="preprocessor">#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk </span></div>
|
||
<div class="line"><a id="l05082" name="l05082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4802401202cdadbd984547f05b09fd1b"> 5082</a></span><span class="preprocessor">#define CAN_F9R2_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l05083" name="l05083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga664cbbe2443064efe7fb3129550c226b"> 5083</a></span><span class="preprocessor">#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l05084" name="l05084"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac7e7544d60c3084da344ee20ab6a760"> 5084</a></span><span class="preprocessor">#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk </span></div>
|
||
<div class="line"><a id="l05085" name="l05085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f56af8f8de74632465471450552f8d5"> 5085</a></span><span class="preprocessor">#define CAN_F9R2_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l05086" name="l05086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21473aad3bbd0a024b0e714c9bbf4e47"> 5086</a></span><span class="preprocessor">#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l05087" name="l05087"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae965845f1e45d1f45831be60829e63bc"> 5087</a></span><span class="preprocessor">#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk </span></div>
|
||
<div class="line"><a id="l05088" name="l05088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d4d14753760fee8b7edf9c281f43bfa"> 5088</a></span><span class="preprocessor">#define CAN_F9R2_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l05089" name="l05089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23124d9ac50f080e32aebae3449ee1a0"> 5089</a></span><span class="preprocessor">#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l05090" name="l05090"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63bbecf009bf6bd61dc9e8fe0603da73"> 5090</a></span><span class="preprocessor">#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk </span></div>
|
||
<div class="line"><a id="l05091" name="l05091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9834ba7e7b11eff8cca5d8ad9845f03"> 5091</a></span><span class="preprocessor">#define CAN_F9R2_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l05092" name="l05092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c149f89a9b7f6a847fc01fe55304dd2"> 5092</a></span><span class="preprocessor">#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l05093" name="l05093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga834cf606ef4b69b0c459b8cb9e836a9b"> 5093</a></span><span class="preprocessor">#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk </span></div>
|
||
<div class="line"><a id="l05094" name="l05094"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1765e9fda5089f19109be26e678e6e2d"> 5094</a></span><span class="preprocessor">#define CAN_F9R2_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l05095" name="l05095"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76d278d95612c8049d4ade5a1a30fabe"> 5095</a></span><span class="preprocessor">#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l05096" name="l05096"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c833e07b7a842ba7425291f628c9a11"> 5096</a></span><span class="preprocessor">#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk </span></div>
|
||
<div class="line"><a id="l05097" name="l05097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e51a4af2c6e972bfd49080723c0ac48"> 5097</a></span><span class="preprocessor">#define CAN_F9R2_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l05098" name="l05098"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3863b24c5580c3f1dcf4dcfccb08796f"> 5098</a></span><span class="preprocessor">#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l05099" name="l05099"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18ef7c7bae75406a267e6a333c549a9f"> 5099</a></span><span class="preprocessor">#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk </span></div>
|
||
<div class="line"><a id="l05101" name="l05101"></a><span class="lineno"> 5101</span><span class="comment">/******************* Bit definition for CAN_F10R2 register ******************/</span></div>
|
||
<div class="line"><a id="l05102" name="l05102"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga067cb17fa931fc8ec805a317221d553f"> 5102</a></span><span class="preprocessor">#define CAN_F10R2_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05103" name="l05103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac774a841f16adc00aaa2ec9fc7e19fcb"> 5103</a></span><span class="preprocessor">#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l05104" name="l05104"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga616898121d5befed0eb5ab61492872f2"> 5104</a></span><span class="preprocessor">#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk </span></div>
|
||
<div class="line"><a id="l05105" name="l05105"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga742179253216598663252628f54678a8"> 5105</a></span><span class="preprocessor">#define CAN_F10R2_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l05106" name="l05106"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a4ed750a26abda88304eac5be92b6a5"> 5106</a></span><span class="preprocessor">#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l05107" name="l05107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa24b6ba1e723098e55e4affc793558c5"> 5107</a></span><span class="preprocessor">#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk </span></div>
|
||
<div class="line"><a id="l05108" name="l05108"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36eff8cda50911988d0a0d6d36d8c267"> 5108</a></span><span class="preprocessor">#define CAN_F10R2_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l05109" name="l05109"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf87f405ddb1abb90958df292c6fc0a4a"> 5109</a></span><span class="preprocessor">#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l05110" name="l05110"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b7fc9db4e77e216f37bf088d7b7703c"> 5110</a></span><span class="preprocessor">#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk </span></div>
|
||
<div class="line"><a id="l05111" name="l05111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae61032600bc3bbd5751c1883555311ae"> 5111</a></span><span class="preprocessor">#define CAN_F10R2_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l05112" name="l05112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fd1293748da16cb1139224b528082c4"> 5112</a></span><span class="preprocessor">#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l05113" name="l05113"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2348cdfff622628147e2c1df0a35363c"> 5113</a></span><span class="preprocessor">#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk </span></div>
|
||
<div class="line"><a id="l05114" name="l05114"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bde5e4239f61759d51e0eda6b788e7e"> 5114</a></span><span class="preprocessor">#define CAN_F10R2_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l05115" name="l05115"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga445fedfbaf84b454483c73e6b72bedfe"> 5115</a></span><span class="preprocessor">#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l05116" name="l05116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebde0ea1e0aaf38fdcf1584e9c9b2063"> 5116</a></span><span class="preprocessor">#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk </span></div>
|
||
<div class="line"><a id="l05117" name="l05117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdd558b92af16682b2ebd3b573a1a07b"> 5117</a></span><span class="preprocessor">#define CAN_F10R2_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l05118" name="l05118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26b37e77455ba2d98eee41464c2fe039"> 5118</a></span><span class="preprocessor">#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l05119" name="l05119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b5b32b71c86c6dc7040b3044be61af7"> 5119</a></span><span class="preprocessor">#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk </span></div>
|
||
<div class="line"><a id="l05120" name="l05120"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7351a6a4b667479d490e6146b8cd9b41"> 5120</a></span><span class="preprocessor">#define CAN_F10R2_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l05121" name="l05121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42f57e8c16bb81bb9291c5ebb4a04b1a"> 5121</a></span><span class="preprocessor">#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l05122" name="l05122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9df7daa799c7c73d9a56de5f92285aca"> 5122</a></span><span class="preprocessor">#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk </span></div>
|
||
<div class="line"><a id="l05123" name="l05123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga061fd86dd7cab205318a1b63c443c0f9"> 5123</a></span><span class="preprocessor">#define CAN_F10R2_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l05124" name="l05124"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6d86237a0fff09a8f49360d47f28d05"> 5124</a></span><span class="preprocessor">#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l05125" name="l05125"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed755173b9d4375b40d73cab90396adc"> 5125</a></span><span class="preprocessor">#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk </span></div>
|
||
<div class="line"><a id="l05126" name="l05126"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31ba127731d0de563aabf8397b0011ac"> 5126</a></span><span class="preprocessor">#define CAN_F10R2_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l05127" name="l05127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad459c18ab4e613bb142e5c1f78691bb8"> 5127</a></span><span class="preprocessor">#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l05128" name="l05128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a8d08fea6e7307f6d1d602e113a6d27"> 5128</a></span><span class="preprocessor">#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk </span></div>
|
||
<div class="line"><a id="l05129" name="l05129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d043efe65c029bd4849d543b3d5b9c4"> 5129</a></span><span class="preprocessor">#define CAN_F10R2_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l05130" name="l05130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5ac6067a7226de096a846276a7770e9"> 5130</a></span><span class="preprocessor">#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l05131" name="l05131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6aecdda55a484aa0e96c89f5d0f42aba"> 5131</a></span><span class="preprocessor">#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk </span></div>
|
||
<div class="line"><a id="l05132" name="l05132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e968d8513a58a5be0ce2cbce6cd7642"> 5132</a></span><span class="preprocessor">#define CAN_F10R2_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l05133" name="l05133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bb490d175c5c7ea273dc5a2ed089028"> 5133</a></span><span class="preprocessor">#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l05134" name="l05134"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4da658bf0a044b327c5efcc592e0ebe1"> 5134</a></span><span class="preprocessor">#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk </span></div>
|
||
<div class="line"><a id="l05135" name="l05135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb10c3617ae2bd30b86196797e26ecba"> 5135</a></span><span class="preprocessor">#define CAN_F10R2_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l05136" name="l05136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga898eafb1c345981f1feaa3e1750f7c32"> 5136</a></span><span class="preprocessor">#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l05137" name="l05137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6ec91db97da763ae1da98ef3a3f7fea"> 5137</a></span><span class="preprocessor">#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk </span></div>
|
||
<div class="line"><a id="l05138" name="l05138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafedb8df9e02ae3bbe23bba2d1afb8e2e"> 5138</a></span><span class="preprocessor">#define CAN_F10R2_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l05139" name="l05139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0d87b23898f43c4c310c9e9098e78b9"> 5139</a></span><span class="preprocessor">#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l05140" name="l05140"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62bba82d177602a29448acf481a7f691"> 5140</a></span><span class="preprocessor">#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk </span></div>
|
||
<div class="line"><a id="l05141" name="l05141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabec06c12b62b4aa0ee4391e6e663ced3"> 5141</a></span><span class="preprocessor">#define CAN_F10R2_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l05142" name="l05142"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7044a16f8b7a80cfaeaca7c1c8b244f"> 5142</a></span><span class="preprocessor">#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l05143" name="l05143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ce79aa37f7a175695fb910f986b7d81"> 5143</a></span><span class="preprocessor">#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk </span></div>
|
||
<div class="line"><a id="l05144" name="l05144"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50210bdcea0f100cf7bb58790cdace47"> 5144</a></span><span class="preprocessor">#define CAN_F10R2_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l05145" name="l05145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccaaa620579ebfb8e1d78f1c3a0960c8"> 5145</a></span><span class="preprocessor">#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l05146" name="l05146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf31488587e33ea32b60a5c21f3e3aff"> 5146</a></span><span class="preprocessor">#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk </span></div>
|
||
<div class="line"><a id="l05147" name="l05147"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fe557c8dc9f510fed958662e88e3e7a"> 5147</a></span><span class="preprocessor">#define CAN_F10R2_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l05148" name="l05148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad44ba649751e52a75f36d5279ae51668"> 5148</a></span><span class="preprocessor">#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l05149" name="l05149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8c7c289c07afb023bb3eedfe4d5a9b1"> 5149</a></span><span class="preprocessor">#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk </span></div>
|
||
<div class="line"><a id="l05150" name="l05150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae18123a344ee82992f3a7af5e7f901fa"> 5150</a></span><span class="preprocessor">#define CAN_F10R2_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l05151" name="l05151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b8427af5b1aa6b8275902848c766a6a"> 5151</a></span><span class="preprocessor">#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l05152" name="l05152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74258ab493246fefc21ddc475dcfda4a"> 5152</a></span><span class="preprocessor">#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk </span></div>
|
||
<div class="line"><a id="l05153" name="l05153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ae29a19824d47f5c97c8ccbd6f6b663"> 5153</a></span><span class="preprocessor">#define CAN_F10R2_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l05154" name="l05154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bc510b54127fe09c9fc93d265f197fd"> 5154</a></span><span class="preprocessor">#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l05155" name="l05155"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabcf9f2daaa27f340a8cd4e64533f5caf"> 5155</a></span><span class="preprocessor">#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk </span></div>
|
||
<div class="line"><a id="l05156" name="l05156"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac05d35a5ccbe652b9d4c5d8ac19a3188"> 5156</a></span><span class="preprocessor">#define CAN_F10R2_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l05157" name="l05157"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15818be97fc1df403386e5fa3791f02f"> 5157</a></span><span class="preprocessor">#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l05158" name="l05158"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b8ad53931f4cb3bebb3f557d8686066"> 5158</a></span><span class="preprocessor">#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk </span></div>
|
||
<div class="line"><a id="l05159" name="l05159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8425c341a53e4648190d86ea2c452fa7"> 5159</a></span><span class="preprocessor">#define CAN_F10R2_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l05160" name="l05160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdc7ed5a571a970931be36e0883c9821"> 5160</a></span><span class="preprocessor">#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l05161" name="l05161"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f0b00c508bddf59fd290091e738a340"> 5161</a></span><span class="preprocessor">#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk </span></div>
|
||
<div class="line"><a id="l05162" name="l05162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf22b16751fb337af287331048cfcae91"> 5162</a></span><span class="preprocessor">#define CAN_F10R2_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l05163" name="l05163"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31df60197cdd2e5914c14a7dd75e026b"> 5163</a></span><span class="preprocessor">#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l05164" name="l05164"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb9db852d4bf1332f748a0cfc0063364"> 5164</a></span><span class="preprocessor">#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk </span></div>
|
||
<div class="line"><a id="l05165" name="l05165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f49963bc7d859f4d79f5f9f55649013"> 5165</a></span><span class="preprocessor">#define CAN_F10R2_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l05166" name="l05166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19dd43ea7d9942f810f2d93169ff5ca6"> 5166</a></span><span class="preprocessor">#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l05167" name="l05167"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga616164fcd20341e4eed5b10a8fd2837c"> 5167</a></span><span class="preprocessor">#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk </span></div>
|
||
<div class="line"><a id="l05168" name="l05168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb17a1d300b8ffde0b9ef278aead2bbc"> 5168</a></span><span class="preprocessor">#define CAN_F10R2_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l05169" name="l05169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace06a38396f56ff90887b648c8683acc"> 5169</a></span><span class="preprocessor">#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l05170" name="l05170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae70893925ea53547e9ce780c0480587b"> 5170</a></span><span class="preprocessor">#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk </span></div>
|
||
<div class="line"><a id="l05171" name="l05171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55d1af80d3c1e3fa6474ccf0509abf83"> 5171</a></span><span class="preprocessor">#define CAN_F10R2_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l05172" name="l05172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2806783fb4a13314098d247596f8ac9c"> 5172</a></span><span class="preprocessor">#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l05173" name="l05173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed74e80c74c6c5e12d26abbc0d923787"> 5173</a></span><span class="preprocessor">#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk </span></div>
|
||
<div class="line"><a id="l05174" name="l05174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga869fa5f46955a937b321cdc30d0c08b1"> 5174</a></span><span class="preprocessor">#define CAN_F10R2_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l05175" name="l05175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad57d7ec2281a4b5a7ecd3db7a80110ba"> 5175</a></span><span class="preprocessor">#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l05176" name="l05176"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecb5b90d073107f3c5612379aaffa7ce"> 5176</a></span><span class="preprocessor">#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk </span></div>
|
||
<div class="line"><a id="l05177" name="l05177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8dc7dc1019cca26cba0b729119ba43b1"> 5177</a></span><span class="preprocessor">#define CAN_F10R2_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l05178" name="l05178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b18d4f50852e67f214d2c885ab1d96b"> 5178</a></span><span class="preprocessor">#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l05179" name="l05179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga678702522f87f63edfcad21194be3c53"> 5179</a></span><span class="preprocessor">#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk </span></div>
|
||
<div class="line"><a id="l05180" name="l05180"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cc3ae2b65d3e4aca044242f0f8b4a29"> 5180</a></span><span class="preprocessor">#define CAN_F10R2_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l05181" name="l05181"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac022d750541154d1c25ae0b342ff3c8d"> 5181</a></span><span class="preprocessor">#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l05182" name="l05182"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4523c34e7f333636fade643b895b8f5"> 5182</a></span><span class="preprocessor">#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk </span></div>
|
||
<div class="line"><a id="l05183" name="l05183"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3aa23672b58bce5c01c0964f8588e5bd"> 5183</a></span><span class="preprocessor">#define CAN_F10R2_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l05184" name="l05184"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga441739ed3bdd065bee7417d50afc96ab"> 5184</a></span><span class="preprocessor">#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l05185" name="l05185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf0e55fcb496970abe8fea481561f886"> 5185</a></span><span class="preprocessor">#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk </span></div>
|
||
<div class="line"><a id="l05186" name="l05186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0b2954975958605274276c9ae1ea7a6"> 5186</a></span><span class="preprocessor">#define CAN_F10R2_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l05187" name="l05187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga906bacdcf21c6bffaa9d45fa6746f80e"> 5187</a></span><span class="preprocessor">#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l05188" name="l05188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e4683223d46d60897b2c46b02addec5"> 5188</a></span><span class="preprocessor">#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk </span></div>
|
||
<div class="line"><a id="l05189" name="l05189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga382e8caf7bca3cea6323f83220c5f04c"> 5189</a></span><span class="preprocessor">#define CAN_F10R2_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l05190" name="l05190"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe8c560adab03768e49cad994a71cccb"> 5190</a></span><span class="preprocessor">#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l05191" name="l05191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6df50371abf968f0638faf7e0bf76cc8"> 5191</a></span><span class="preprocessor">#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk </span></div>
|
||
<div class="line"><a id="l05192" name="l05192"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20abbd298e588db3094637ad1b76b0fb"> 5192</a></span><span class="preprocessor">#define CAN_F10R2_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l05193" name="l05193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d7ed61987ecdd8236e5236edc35946f"> 5193</a></span><span class="preprocessor">#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l05194" name="l05194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab294aa73a3fdfc60672b206bd57a1e08"> 5194</a></span><span class="preprocessor">#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk </span></div>
|
||
<div class="line"><a id="l05195" name="l05195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c0d5f4f54822978cc2fb6d8e46d532f"> 5195</a></span><span class="preprocessor">#define CAN_F10R2_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l05196" name="l05196"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6278728b6cc74ad7d4bc41d6014839f3"> 5196</a></span><span class="preprocessor">#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l05197" name="l05197"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2de1906dc4119b37b29bbe25e3e6dbe0"> 5197</a></span><span class="preprocessor">#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk </span></div>
|
||
<div class="line"><a id="l05199" name="l05199"></a><span class="lineno"> 5199</span><span class="comment">/******************* Bit definition for CAN_F11R2 register ******************/</span></div>
|
||
<div class="line"><a id="l05200" name="l05200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad70c5d7ca84956020778f4467b9e66ba"> 5200</a></span><span class="preprocessor">#define CAN_F11R2_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05201" name="l05201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga756b9a7f35ddb243019a737cc9c5d4aa"> 5201</a></span><span class="preprocessor">#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l05202" name="l05202"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacad6560088b586891d446952bbd8fbbe"> 5202</a></span><span class="preprocessor">#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk </span></div>
|
||
<div class="line"><a id="l05203" name="l05203"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa225421da3627c8bf8e836c516c36ff9"> 5203</a></span><span class="preprocessor">#define CAN_F11R2_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l05204" name="l05204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73175a30063e3781dd1b5ee2b9ff5c7c"> 5204</a></span><span class="preprocessor">#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l05205" name="l05205"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac81bc667cb0c63aa0448f6e0eb1d105d"> 5205</a></span><span class="preprocessor">#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk </span></div>
|
||
<div class="line"><a id="l05206" name="l05206"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70986cdccec7c3a2997094e5a026ea7d"> 5206</a></span><span class="preprocessor">#define CAN_F11R2_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l05207" name="l05207"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43042d452e6efb4e24fecc0ef71f0b53"> 5207</a></span><span class="preprocessor">#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l05208" name="l05208"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8dab8868637d6d6fb707b6a37a5989b5"> 5208</a></span><span class="preprocessor">#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk </span></div>
|
||
<div class="line"><a id="l05209" name="l05209"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4404f58525379b7462074c1f4d94abc"> 5209</a></span><span class="preprocessor">#define CAN_F11R2_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l05210" name="l05210"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga603a033a522647ec072b27204f411c27"> 5210</a></span><span class="preprocessor">#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l05211" name="l05211"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga559246cfa4658a5adaa282e4a3b35dd5"> 5211</a></span><span class="preprocessor">#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk </span></div>
|
||
<div class="line"><a id="l05212" name="l05212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83a62db93a855fc670d041db3f95f7ce"> 5212</a></span><span class="preprocessor">#define CAN_F11R2_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l05213" name="l05213"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7f3cc6f8734688ffd55f0eae6d8a3e1"> 5213</a></span><span class="preprocessor">#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l05214" name="l05214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga499aebdfc0c14b9c399698e28fde3e50"> 5214</a></span><span class="preprocessor">#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk </span></div>
|
||
<div class="line"><a id="l05215" name="l05215"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24cd2b60689ccae14ae3254487a564b9"> 5215</a></span><span class="preprocessor">#define CAN_F11R2_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l05216" name="l05216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga100d5a8929cac40dc2d8d6bfaf2effb0"> 5216</a></span><span class="preprocessor">#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l05217" name="l05217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1613d097fe5b7107ff36f97a9263bd38"> 5217</a></span><span class="preprocessor">#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk </span></div>
|
||
<div class="line"><a id="l05218" name="l05218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga595220fc83b10a19867b00b7bc58221f"> 5218</a></span><span class="preprocessor">#define CAN_F11R2_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l05219" name="l05219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2541f8510aa2f59dd2b2cfbf1bc99c1"> 5219</a></span><span class="preprocessor">#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l05220" name="l05220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9db1830185822d66619059a644d86ffe"> 5220</a></span><span class="preprocessor">#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk </span></div>
|
||
<div class="line"><a id="l05221" name="l05221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga196fb045bc38774e8d3b9c18345f799e"> 5221</a></span><span class="preprocessor">#define CAN_F11R2_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l05222" name="l05222"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2739365d7644847c2b2e9424b5361782"> 5222</a></span><span class="preprocessor">#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l05223" name="l05223"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab35bedade0c9f71455abfbbac2edee14"> 5223</a></span><span class="preprocessor">#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk </span></div>
|
||
<div class="line"><a id="l05224" name="l05224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94ab78b385a77559abd1bc055656fa5a"> 5224</a></span><span class="preprocessor">#define CAN_F11R2_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l05225" name="l05225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7159e2db436359c52f6db1dda067a7c2"> 5225</a></span><span class="preprocessor">#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l05226" name="l05226"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac79ac007ffed536eedddffdd2615c5f7"> 5226</a></span><span class="preprocessor">#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk </span></div>
|
||
<div class="line"><a id="l05227" name="l05227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga818a9cf4d1a1ebfc566869487c5ede4e"> 5227</a></span><span class="preprocessor">#define CAN_F11R2_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l05228" name="l05228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2d8d29dcf8047b47275915562036f6e"> 5228</a></span><span class="preprocessor">#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l05229" name="l05229"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5900c2273c405ce35b9bd52b189c102"> 5229</a></span><span class="preprocessor">#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk </span></div>
|
||
<div class="line"><a id="l05230" name="l05230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cda459a8f36d3ebc3b572df16998ad2"> 5230</a></span><span class="preprocessor">#define CAN_F11R2_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l05231" name="l05231"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d867bbf2aeec0751fb8d9bc028a3e20"> 5231</a></span><span class="preprocessor">#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l05232" name="l05232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9dad5ea347a6a928997a0a1c149369ce"> 5232</a></span><span class="preprocessor">#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk </span></div>
|
||
<div class="line"><a id="l05233" name="l05233"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9aed466e0487ccf8da142590ea6a0c9"> 5233</a></span><span class="preprocessor">#define CAN_F11R2_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l05234" name="l05234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f02c0270c8560877a6849dc3ec12734"> 5234</a></span><span class="preprocessor">#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l05235" name="l05235"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9285109080a523012f27b3bdbabc6949"> 5235</a></span><span class="preprocessor">#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk </span></div>
|
||
<div class="line"><a id="l05236" name="l05236"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9f6c874f151de08d9e16f7f25e69519"> 5236</a></span><span class="preprocessor">#define CAN_F11R2_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l05237" name="l05237"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f27deb61d7cecd98a3707baeee44c33"> 5237</a></span><span class="preprocessor">#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l05238" name="l05238"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65cdf759738f8b0cb8c4c3231453aad8"> 5238</a></span><span class="preprocessor">#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk </span></div>
|
||
<div class="line"><a id="l05239" name="l05239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga466d8e9611e69bfd911aeab18a24f790"> 5239</a></span><span class="preprocessor">#define CAN_F11R2_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l05240" name="l05240"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e89abf41152c9c443eec298c3c4ee0a"> 5240</a></span><span class="preprocessor">#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l05241" name="l05241"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24a40efa6debcdcfef0f7ab6d8b3eb04"> 5241</a></span><span class="preprocessor">#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk </span></div>
|
||
<div class="line"><a id="l05242" name="l05242"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06aa722740f4a12a01fcec5930b44e4e"> 5242</a></span><span class="preprocessor">#define CAN_F11R2_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l05243" name="l05243"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf385990b78e0ad2903adf8ca5d31592d"> 5243</a></span><span class="preprocessor">#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l05244" name="l05244"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa923634a3432436c4c84e65be1fd39d6"> 5244</a></span><span class="preprocessor">#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk </span></div>
|
||
<div class="line"><a id="l05245" name="l05245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1084133f89fd1b056a0001b496010b9e"> 5245</a></span><span class="preprocessor">#define CAN_F11R2_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l05246" name="l05246"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac617eb6a2c9da89608e9a1fd20bedb05"> 5246</a></span><span class="preprocessor">#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l05247" name="l05247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65bae4ee01f83fe051acee8ee4c8a10e"> 5247</a></span><span class="preprocessor">#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk </span></div>
|
||
<div class="line"><a id="l05248" name="l05248"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c28a61b0bd631ca5fe08c4aa30f9567"> 5248</a></span><span class="preprocessor">#define CAN_F11R2_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l05249" name="l05249"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f7a12de16318eca8c069f7a4a107ba4"> 5249</a></span><span class="preprocessor">#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l05250" name="l05250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b6762f3642ce7a06fff58270ac9f53f"> 5250</a></span><span class="preprocessor">#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk </span></div>
|
||
<div class="line"><a id="l05251" name="l05251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4a696446a3ba4010fe43d401efc22b8"> 5251</a></span><span class="preprocessor">#define CAN_F11R2_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l05252" name="l05252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6194082f1b79eacc5490d6c4571f2993"> 5252</a></span><span class="preprocessor">#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l05253" name="l05253"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69c7d6a41708543278980035b64bd31b"> 5253</a></span><span class="preprocessor">#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk </span></div>
|
||
<div class="line"><a id="l05254" name="l05254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87528786c246818857315a7728117d16"> 5254</a></span><span class="preprocessor">#define CAN_F11R2_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l05255" name="l05255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga578e9b0b0fc78522d232926aa5a474b4"> 5255</a></span><span class="preprocessor">#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l05256" name="l05256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88d6d67020cbc5a4d5f0b7c5dc488aa6"> 5256</a></span><span class="preprocessor">#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk </span></div>
|
||
<div class="line"><a id="l05257" name="l05257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb57ae932a28d7bae3af99c7cc73d6f0"> 5257</a></span><span class="preprocessor">#define CAN_F11R2_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l05258" name="l05258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4aa7935ffacb2eb500c03e6f297c9abf"> 5258</a></span><span class="preprocessor">#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l05259" name="l05259"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07f4a8d606f2063be35b52e1fc5e4b58"> 5259</a></span><span class="preprocessor">#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk </span></div>
|
||
<div class="line"><a id="l05260" name="l05260"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac77f12ec2cab52d721629fe0ae73c093"> 5260</a></span><span class="preprocessor">#define CAN_F11R2_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l05261" name="l05261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecca1f88d1ccfd94c942c1dba195f566"> 5261</a></span><span class="preprocessor">#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l05262" name="l05262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58c6e5b0076c31b7bee1c9aea94e11fb"> 5262</a></span><span class="preprocessor">#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk </span></div>
|
||
<div class="line"><a id="l05263" name="l05263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbc3adfab5e37044e4b71efcd3e045c3"> 5263</a></span><span class="preprocessor">#define CAN_F11R2_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l05264" name="l05264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26b076a8a45e423f12d66b72888a62c1"> 5264</a></span><span class="preprocessor">#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l05265" name="l05265"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93bf815d462dc3a40725f73e107e11f5"> 5265</a></span><span class="preprocessor">#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk </span></div>
|
||
<div class="line"><a id="l05266" name="l05266"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabfb18cb42280379ea211f97dda828964"> 5266</a></span><span class="preprocessor">#define CAN_F11R2_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l05267" name="l05267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69a3601ecccef7d68dceacf69694f57c"> 5267</a></span><span class="preprocessor">#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l05268" name="l05268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeebe934727476f5fde11c888c424c417"> 5268</a></span><span class="preprocessor">#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk </span></div>
|
||
<div class="line"><a id="l05269" name="l05269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56baa11c41451f4e27adb7df35046d74"> 5269</a></span><span class="preprocessor">#define CAN_F11R2_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l05270" name="l05270"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9acb53490837c29f03538f37e92ab7b0"> 5270</a></span><span class="preprocessor">#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l05271" name="l05271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8324877e56a61c15119f2ebf929894cc"> 5271</a></span><span class="preprocessor">#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk </span></div>
|
||
<div class="line"><a id="l05272" name="l05272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09624fe67ae7144c103e70325bb4bbd9"> 5272</a></span><span class="preprocessor">#define CAN_F11R2_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l05273" name="l05273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54d08ee868e97a722b5e25b145581435"> 5273</a></span><span class="preprocessor">#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l05274" name="l05274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfd994c36da11529ac494df973b5759c"> 5274</a></span><span class="preprocessor">#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk </span></div>
|
||
<div class="line"><a id="l05275" name="l05275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadeeb62a3987c1ad5b7bd6ed7424c4a1b"> 5275</a></span><span class="preprocessor">#define CAN_F11R2_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l05276" name="l05276"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e9aaac92b7b5c524dfd488651f66d1b"> 5276</a></span><span class="preprocessor">#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l05277" name="l05277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f3e9d272b625f7d6269057aee5d7761"> 5277</a></span><span class="preprocessor">#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk </span></div>
|
||
<div class="line"><a id="l05278" name="l05278"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa50568c5112b9d364a4a1a6a7d668ba2"> 5278</a></span><span class="preprocessor">#define CAN_F11R2_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l05279" name="l05279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga769efd27c8d450433589d3a59e4b49b7"> 5279</a></span><span class="preprocessor">#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l05280" name="l05280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5da4d794a9797d14536197679b7b2b14"> 5280</a></span><span class="preprocessor">#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk </span></div>
|
||
<div class="line"><a id="l05281" name="l05281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc07b263056b681c3834e366c8cb060e"> 5281</a></span><span class="preprocessor">#define CAN_F11R2_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l05282" name="l05282"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38daca04f9249b41d451122bfcb63b2d"> 5282</a></span><span class="preprocessor">#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l05283" name="l05283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9b9a815f36e7c2929f4313ca424c83a"> 5283</a></span><span class="preprocessor">#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk </span></div>
|
||
<div class="line"><a id="l05284" name="l05284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70db281007bc66b283e8bb8f0dc05af4"> 5284</a></span><span class="preprocessor">#define CAN_F11R2_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l05285" name="l05285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb214fcb4208a4d5db09465c5260d5e4"> 5285</a></span><span class="preprocessor">#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l05286" name="l05286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf162471f4c070d13fa409d44467373fc"> 5286</a></span><span class="preprocessor">#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk </span></div>
|
||
<div class="line"><a id="l05287" name="l05287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga111f04007588ff775bbd03d30f7e1bb7"> 5287</a></span><span class="preprocessor">#define CAN_F11R2_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l05288" name="l05288"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10d6ff5e482dc1d88d0f39a0e2329427"> 5288</a></span><span class="preprocessor">#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l05289" name="l05289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c301fd37e3fa27d3bd28a1f3f553e77"> 5289</a></span><span class="preprocessor">#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk </span></div>
|
||
<div class="line"><a id="l05290" name="l05290"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga537283f338bc941c2749698732cba679"> 5290</a></span><span class="preprocessor">#define CAN_F11R2_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l05291" name="l05291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7be4778f941b5287fcc39a5ce3724e71"> 5291</a></span><span class="preprocessor">#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l05292" name="l05292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bdc4ba1d0e44ba4d7a03cfd3197b687"> 5292</a></span><span class="preprocessor">#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk </span></div>
|
||
<div class="line"><a id="l05293" name="l05293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7120051826cab6e84712aafd60e7f0e"> 5293</a></span><span class="preprocessor">#define CAN_F11R2_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l05294" name="l05294"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f08f45859f87d045ab080dd511302bd"> 5294</a></span><span class="preprocessor">#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l05295" name="l05295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6525c1ff364a229c9ea1b353b11be8c3"> 5295</a></span><span class="preprocessor">#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk </span></div>
|
||
<div class="line"><a id="l05297" name="l05297"></a><span class="lineno"> 5297</span><span class="comment">/******************* Bit definition for CAN_F12R2 register ******************/</span></div>
|
||
<div class="line"><a id="l05298" name="l05298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga761234dc8a340812052ad359ca15346e"> 5298</a></span><span class="preprocessor">#define CAN_F12R2_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05299" name="l05299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8707c57f295a01f74ba15708f138c27"> 5299</a></span><span class="preprocessor">#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l05300" name="l05300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5fd095552b3108c685514e78e43e52d"> 5300</a></span><span class="preprocessor">#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk </span></div>
|
||
<div class="line"><a id="l05301" name="l05301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30aeb440ddfed5b394b5d2a24e3ae6a9"> 5301</a></span><span class="preprocessor">#define CAN_F12R2_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l05302" name="l05302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c445b90087e01550b4d69a41d01920b"> 5302</a></span><span class="preprocessor">#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l05303" name="l05303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga450e88e19b2e478e73cbc5eef74a72d2"> 5303</a></span><span class="preprocessor">#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk </span></div>
|
||
<div class="line"><a id="l05304" name="l05304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga453ef335bb8ebc552ac07085c3c1787b"> 5304</a></span><span class="preprocessor">#define CAN_F12R2_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l05305" name="l05305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae07ef8899e2a3d28d760dfd1ecc26534"> 5305</a></span><span class="preprocessor">#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l05306" name="l05306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17875db304b98c38e627f7d7db339136"> 5306</a></span><span class="preprocessor">#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk </span></div>
|
||
<div class="line"><a id="l05307" name="l05307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaac55989758901512f579aef6dc250d5"> 5307</a></span><span class="preprocessor">#define CAN_F12R2_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l05308" name="l05308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5918b1d48e5c6e30363e5f5274428f6f"> 5308</a></span><span class="preprocessor">#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l05309" name="l05309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2960fee8bc56574e1b51975da7d2f041"> 5309</a></span><span class="preprocessor">#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk </span></div>
|
||
<div class="line"><a id="l05310" name="l05310"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0582dd4f64bdf4f05d1049191cd0ead5"> 5310</a></span><span class="preprocessor">#define CAN_F12R2_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l05311" name="l05311"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7278ef3ee9707ed890c9fe0e6100898e"> 5311</a></span><span class="preprocessor">#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l05312" name="l05312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b3b6f518fae0cb1123aa187138d90b6"> 5312</a></span><span class="preprocessor">#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk </span></div>
|
||
<div class="line"><a id="l05313" name="l05313"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50ff5f436b22533d9c3d008b3b5ad936"> 5313</a></span><span class="preprocessor">#define CAN_F12R2_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l05314" name="l05314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9db42645316b7d12f6761201dde5266e"> 5314</a></span><span class="preprocessor">#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l05315" name="l05315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39cedc414fa80ef987825daf32e11ac4"> 5315</a></span><span class="preprocessor">#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk </span></div>
|
||
<div class="line"><a id="l05316" name="l05316"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f48821b5d51b30776a550c461e9f39e"> 5316</a></span><span class="preprocessor">#define CAN_F12R2_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l05317" name="l05317"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga105d22692de0996a549d7381117a9343"> 5317</a></span><span class="preprocessor">#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l05318" name="l05318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10aa07474c2e7cf7f2845d0d2b2bd383"> 5318</a></span><span class="preprocessor">#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk </span></div>
|
||
<div class="line"><a id="l05319" name="l05319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3bda5bd0a94bb8f667f350b5d1bd575"> 5319</a></span><span class="preprocessor">#define CAN_F12R2_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l05320" name="l05320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ef9a09cde9defbbef26f0fdb18e2eab"> 5320</a></span><span class="preprocessor">#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l05321" name="l05321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga227ef5f36f6e03969cd952d62a3bc0a9"> 5321</a></span><span class="preprocessor">#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk </span></div>
|
||
<div class="line"><a id="l05322" name="l05322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c35633aeeaa4b60f618d6b59d5450d1"> 5322</a></span><span class="preprocessor">#define CAN_F12R2_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l05323" name="l05323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga997778eae60bd7c86e4ac5f512cf37d1"> 5323</a></span><span class="preprocessor">#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l05324" name="l05324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a946c991cee617b322ff9a372af3512"> 5324</a></span><span class="preprocessor">#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk </span></div>
|
||
<div class="line"><a id="l05325" name="l05325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab378df5d0ef5f7b73f9cc93d9deb28d"> 5325</a></span><span class="preprocessor">#define CAN_F12R2_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l05326" name="l05326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d597dd76bca430d66ce6cdc1dab0039"> 5326</a></span><span class="preprocessor">#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l05327" name="l05327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0ab582743e96fcd36662a9434b875bd"> 5327</a></span><span class="preprocessor">#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk </span></div>
|
||
<div class="line"><a id="l05328" name="l05328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf3a83fdb8ed55330b72d88624d3eeca"> 5328</a></span><span class="preprocessor">#define CAN_F12R2_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l05329" name="l05329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2fe14171ea2823a2cc42bd77f8285f5"> 5329</a></span><span class="preprocessor">#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l05330" name="l05330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga854c2b7108e33d263cc8269648f8bbbe"> 5330</a></span><span class="preprocessor">#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk </span></div>
|
||
<div class="line"><a id="l05331" name="l05331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7506fa1356769f671cc4ac661aca30df"> 5331</a></span><span class="preprocessor">#define CAN_F12R2_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l05332" name="l05332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf995048a494eef63803ad6d1ee208669"> 5332</a></span><span class="preprocessor">#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l05333" name="l05333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ed3de0039e458bac5530d08c2e9af51"> 5333</a></span><span class="preprocessor">#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk </span></div>
|
||
<div class="line"><a id="l05334" name="l05334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga842fb02b43bc973392d1befc14475398"> 5334</a></span><span class="preprocessor">#define CAN_F12R2_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l05335" name="l05335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b1c705252d4dda9fc1e08a83bf44014"> 5335</a></span><span class="preprocessor">#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l05336" name="l05336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadad0db6fe916794156f773e98b524b07"> 5336</a></span><span class="preprocessor">#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk </span></div>
|
||
<div class="line"><a id="l05337" name="l05337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga584c1f14c88da55dfb8846e31b6fad4f"> 5337</a></span><span class="preprocessor">#define CAN_F12R2_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l05338" name="l05338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a5720bd6028451390e7e09643a959eb"> 5338</a></span><span class="preprocessor">#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l05339" name="l05339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7a50bd0de8b4e85d9e90c1f48ef7bc8"> 5339</a></span><span class="preprocessor">#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk </span></div>
|
||
<div class="line"><a id="l05340" name="l05340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga199bffabf961f45cd68a0cafcc4be3e4"> 5340</a></span><span class="preprocessor">#define CAN_F12R2_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l05341" name="l05341"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac46f9e9d46f1bebfa7abcb094e87536"> 5341</a></span><span class="preprocessor">#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l05342" name="l05342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c5558cc37c62c5570a5e2716e30ed99"> 5342</a></span><span class="preprocessor">#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk </span></div>
|
||
<div class="line"><a id="l05343" name="l05343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba0f51aaeeb7e039aa521f88a20bacd6"> 5343</a></span><span class="preprocessor">#define CAN_F12R2_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l05344" name="l05344"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1114ed600ca719c7df01b6e0ebd1b46e"> 5344</a></span><span class="preprocessor">#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l05345" name="l05345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fa511d56f90a2ee10e44e56e378f7ed"> 5345</a></span><span class="preprocessor">#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk </span></div>
|
||
<div class="line"><a id="l05346" name="l05346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02f84ccd7431b78532fed1e1b219cc5f"> 5346</a></span><span class="preprocessor">#define CAN_F12R2_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l05347" name="l05347"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94b484b519e43973af447f5f39fa9ea6"> 5347</a></span><span class="preprocessor">#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l05348" name="l05348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77ae08ea078773a1aecbf74e89dc2a5d"> 5348</a></span><span class="preprocessor">#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk </span></div>
|
||
<div class="line"><a id="l05349" name="l05349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2dd4b026306377b126988db6f40b925b"> 5349</a></span><span class="preprocessor">#define CAN_F12R2_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l05350" name="l05350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a2460e4afab4b8dc064ffc0342f4d9d"> 5350</a></span><span class="preprocessor">#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l05351" name="l05351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a94ac3d4ba5c16a98fc04144ae3bb86"> 5351</a></span><span class="preprocessor">#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk </span></div>
|
||
<div class="line"><a id="l05352" name="l05352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b9aaf58c37cc1c397c235b6f3359a8e"> 5352</a></span><span class="preprocessor">#define CAN_F12R2_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l05353" name="l05353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae63f4ec2056e1d8cee09e7582dd0cc4f"> 5353</a></span><span class="preprocessor">#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l05354" name="l05354"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9070c9b9eec5dea6b5c4cdbaa1d5918"> 5354</a></span><span class="preprocessor">#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk </span></div>
|
||
<div class="line"><a id="l05355" name="l05355"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b87a32833eb49ae6e9d6016b23f1a77"> 5355</a></span><span class="preprocessor">#define CAN_F12R2_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l05356" name="l05356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17513f0a12a63dd49ef869f7f69c89b0"> 5356</a></span><span class="preprocessor">#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l05357" name="l05357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga758cacc8b96577bb3663da1fae36040b"> 5357</a></span><span class="preprocessor">#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk </span></div>
|
||
<div class="line"><a id="l05358" name="l05358"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9723713bf9c96c6e2a843cc4c8851512"> 5358</a></span><span class="preprocessor">#define CAN_F12R2_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l05359" name="l05359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98344bb2606581ffe2826c660c129f8b"> 5359</a></span><span class="preprocessor">#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l05360" name="l05360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80db4704807d6df4aaee2eebfcf5210a"> 5360</a></span><span class="preprocessor">#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk </span></div>
|
||
<div class="line"><a id="l05361" name="l05361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e7ede0dcef51b6f58598345d03231b2"> 5361</a></span><span class="preprocessor">#define CAN_F12R2_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l05362" name="l05362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27369d641bde06fff00068460db1fad7"> 5362</a></span><span class="preprocessor">#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l05363" name="l05363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3d3fb3a9b4b6b90139024bef933bc3d"> 5363</a></span><span class="preprocessor">#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk </span></div>
|
||
<div class="line"><a id="l05364" name="l05364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafda2d00458700d6f0d9bc992032c143a"> 5364</a></span><span class="preprocessor">#define CAN_F12R2_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l05365" name="l05365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0293d477ec5d1c58228b05da05d5ab9a"> 5365</a></span><span class="preprocessor">#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l05366" name="l05366"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24e87973f51235e81195d84f78489cb0"> 5366</a></span><span class="preprocessor">#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk </span></div>
|
||
<div class="line"><a id="l05367" name="l05367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f0bf90c297ea4e534fa8dc777f84308"> 5367</a></span><span class="preprocessor">#define CAN_F12R2_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l05368" name="l05368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9bb02cff06985ebc935cd0c71033e309"> 5368</a></span><span class="preprocessor">#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l05369" name="l05369"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e917f2a362569d86a75a34eddce636c"> 5369</a></span><span class="preprocessor">#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk </span></div>
|
||
<div class="line"><a id="l05370" name="l05370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d42baff6206f76c15caec946f2e163f"> 5370</a></span><span class="preprocessor">#define CAN_F12R2_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l05371" name="l05371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5942038c40cb69a4523cf59d41addaf"> 5371</a></span><span class="preprocessor">#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l05372" name="l05372"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6e5f2c5de8981fbfc152926fc8fb057"> 5372</a></span><span class="preprocessor">#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk </span></div>
|
||
<div class="line"><a id="l05373" name="l05373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf89410be942af8dd01a4a82d2419ebc"> 5373</a></span><span class="preprocessor">#define CAN_F12R2_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l05374" name="l05374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab77c232170c49225690370bd7b94cc34"> 5374</a></span><span class="preprocessor">#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l05375" name="l05375"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaad1149501e8f926a247aa532405c0b9"> 5375</a></span><span class="preprocessor">#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk </span></div>
|
||
<div class="line"><a id="l05376" name="l05376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga099dae9dd45974395166a31031a7a9a4"> 5376</a></span><span class="preprocessor">#define CAN_F12R2_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l05377" name="l05377"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga051ec82cb86668c1907e9091bf7db162"> 5377</a></span><span class="preprocessor">#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l05378" name="l05378"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53538969afd7e43cc7fed4c400ab6f5a"> 5378</a></span><span class="preprocessor">#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk </span></div>
|
||
<div class="line"><a id="l05379" name="l05379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ed6233846959dbe830448c085f9895d"> 5379</a></span><span class="preprocessor">#define CAN_F12R2_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l05380" name="l05380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1eb6cc6be0e68041cb7e72b9ef73e22"> 5380</a></span><span class="preprocessor">#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l05381" name="l05381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74e04fa5d17a7cc7687c0ca40dd571ce"> 5381</a></span><span class="preprocessor">#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk </span></div>
|
||
<div class="line"><a id="l05382" name="l05382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefa74afb06c20c7d6fdfadd641e55047"> 5382</a></span><span class="preprocessor">#define CAN_F12R2_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l05383" name="l05383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c63cc29f569c165a9b93cb0cb2d7557"> 5383</a></span><span class="preprocessor">#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l05384" name="l05384"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc1d97354c1649fa5ddc46f4271297d9"> 5384</a></span><span class="preprocessor">#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk </span></div>
|
||
<div class="line"><a id="l05385" name="l05385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2d97a557450fc2f40af9032f9e6c123"> 5385</a></span><span class="preprocessor">#define CAN_F12R2_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l05386" name="l05386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa58b7118e577b7ea51f92ed3d6a86a56"> 5386</a></span><span class="preprocessor">#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l05387" name="l05387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71b870003e469dcb24979e835a2f81a4"> 5387</a></span><span class="preprocessor">#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk </span></div>
|
||
<div class="line"><a id="l05388" name="l05388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87899a68fb53be2c0c66183254f8e74c"> 5388</a></span><span class="preprocessor">#define CAN_F12R2_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l05389" name="l05389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fe16c8a9c44110d181e931e96458cee"> 5389</a></span><span class="preprocessor">#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l05390" name="l05390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2894b732a9683d32620fb90b06ba9f62"> 5390</a></span><span class="preprocessor">#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk </span></div>
|
||
<div class="line"><a id="l05391" name="l05391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6180d0787f865b2a5da3c308dc9df3ee"> 5391</a></span><span class="preprocessor">#define CAN_F12R2_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l05392" name="l05392"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga677ce6a45ad5da29fbe4b3674294c356"> 5392</a></span><span class="preprocessor">#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l05393" name="l05393"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab11cddebcb4e1ab70b7222a999d0c58a"> 5393</a></span><span class="preprocessor">#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk </span></div>
|
||
<div class="line"><a id="l05395" name="l05395"></a><span class="lineno"> 5395</span><span class="comment">/******************* Bit definition for CAN_F13R2 register ******************/</span></div>
|
||
<div class="line"><a id="l05396" name="l05396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf65fd29198dc6498a41e5fc67ab0092c"> 5396</a></span><span class="preprocessor">#define CAN_F13R2_FB0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05397" name="l05397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5829958d09421fd61fcf0b77d51d2da9"> 5397</a></span><span class="preprocessor">#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) </span></div>
|
||
<div class="line"><a id="l05398" name="l05398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b6865be0c757b49a250a537d73ae85e"> 5398</a></span><span class="preprocessor">#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk </span></div>
|
||
<div class="line"><a id="l05399" name="l05399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44b45587e81d3899b99a4292ef37ea94"> 5399</a></span><span class="preprocessor">#define CAN_F13R2_FB1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l05400" name="l05400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d158b5eebb1632e54e5be5d97c8ac26"> 5400</a></span><span class="preprocessor">#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) </span></div>
|
||
<div class="line"><a id="l05401" name="l05401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf18df9b2fd549b8991fdd9f8f94e7cbb"> 5401</a></span><span class="preprocessor">#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk </span></div>
|
||
<div class="line"><a id="l05402" name="l05402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16867534ce37ae3319f3e8a5cf087cb8"> 5402</a></span><span class="preprocessor">#define CAN_F13R2_FB2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l05403" name="l05403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4433c9b9f1466001eaf2305aa5abcf88"> 5403</a></span><span class="preprocessor">#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) </span></div>
|
||
<div class="line"><a id="l05404" name="l05404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga034e8f5b7675ce34eb2792531c7e174d"> 5404</a></span><span class="preprocessor">#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk </span></div>
|
||
<div class="line"><a id="l05405" name="l05405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed05bb756f656fb754091e64b176bd78"> 5405</a></span><span class="preprocessor">#define CAN_F13R2_FB3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l05406" name="l05406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab05ac64cc9be63004a672f439a7ab70"> 5406</a></span><span class="preprocessor">#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) </span></div>
|
||
<div class="line"><a id="l05407" name="l05407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf19767c0892dffb6eff8c5a3b0e254f5"> 5407</a></span><span class="preprocessor">#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk </span></div>
|
||
<div class="line"><a id="l05408" name="l05408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44666780046b34e5f5b14ba31f39cefc"> 5408</a></span><span class="preprocessor">#define CAN_F13R2_FB4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l05409" name="l05409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b936b6b027a2936ab21bd3f46c830aa"> 5409</a></span><span class="preprocessor">#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) </span></div>
|
||
<div class="line"><a id="l05410" name="l05410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad03b0ab4d686a1ad858f1ba4b679fff9"> 5410</a></span><span class="preprocessor">#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk </span></div>
|
||
<div class="line"><a id="l05411" name="l05411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa84e2ee25ea5266c9ebc55eb15b232ce"> 5411</a></span><span class="preprocessor">#define CAN_F13R2_FB5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l05412" name="l05412"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff4ab0ef27b2b9cc09019b73f3cffed1"> 5412</a></span><span class="preprocessor">#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) </span></div>
|
||
<div class="line"><a id="l05413" name="l05413"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e37522978ae2e88c27f5604c5517d42"> 5413</a></span><span class="preprocessor">#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk </span></div>
|
||
<div class="line"><a id="l05414" name="l05414"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf66b4b2eff656482af6adcf8afc007b"> 5414</a></span><span class="preprocessor">#define CAN_F13R2_FB6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l05415" name="l05415"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf96e3c22df9a1af249c91056375c24dc"> 5415</a></span><span class="preprocessor">#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) </span></div>
|
||
<div class="line"><a id="l05416" name="l05416"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bf6fff2ca4adf6e093a13b2db77adbb"> 5416</a></span><span class="preprocessor">#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk </span></div>
|
||
<div class="line"><a id="l05417" name="l05417"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa23426711b2a872dc4c34147415f101c"> 5417</a></span><span class="preprocessor">#define CAN_F13R2_FB7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l05418" name="l05418"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d3accaea73cb0bb14c61c8327adff66"> 5418</a></span><span class="preprocessor">#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) </span></div>
|
||
<div class="line"><a id="l05419" name="l05419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabca970c306c9c9b576ef3424f686f324"> 5419</a></span><span class="preprocessor">#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk </span></div>
|
||
<div class="line"><a id="l05420" name="l05420"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3559eca84f9b7d1f99f2a7aee2e4393c"> 5420</a></span><span class="preprocessor">#define CAN_F13R2_FB8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l05421" name="l05421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5134cad65b0825f53f4f4e78f0c8e11c"> 5421</a></span><span class="preprocessor">#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) </span></div>
|
||
<div class="line"><a id="l05422" name="l05422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae44e1d120c773c9dc26f418acf3cb6de"> 5422</a></span><span class="preprocessor">#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk </span></div>
|
||
<div class="line"><a id="l05423" name="l05423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c54a85b5280816543e0e415fbc96d09"> 5423</a></span><span class="preprocessor">#define CAN_F13R2_FB9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l05424" name="l05424"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf13c3a79fcb1bc2bb884dcda8e10ffd0"> 5424</a></span><span class="preprocessor">#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) </span></div>
|
||
<div class="line"><a id="l05425" name="l05425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga891d1d97e1a57c4cfa1a714b61b083eb"> 5425</a></span><span class="preprocessor">#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk </span></div>
|
||
<div class="line"><a id="l05426" name="l05426"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c9c5a2239ce7d523894181eacd0a52e"> 5426</a></span><span class="preprocessor">#define CAN_F13R2_FB10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l05427" name="l05427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ad8207a0741ab38136b3b5c3b1d3d91"> 5427</a></span><span class="preprocessor">#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) </span></div>
|
||
<div class="line"><a id="l05428" name="l05428"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb4be9c1da46b251c43c0aafe7b04497"> 5428</a></span><span class="preprocessor">#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk </span></div>
|
||
<div class="line"><a id="l05429" name="l05429"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9228d8f828f658636990f7cd5896ccf4"> 5429</a></span><span class="preprocessor">#define CAN_F13R2_FB11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l05430" name="l05430"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga001860328be3ee22113d0c10f4d3cf23"> 5430</a></span><span class="preprocessor">#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) </span></div>
|
||
<div class="line"><a id="l05431" name="l05431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47f5215de00574378a489f90eb11eff4"> 5431</a></span><span class="preprocessor">#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk </span></div>
|
||
<div class="line"><a id="l05432" name="l05432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae031e0a0fe7facb0d7d56c7efd3aa2ea"> 5432</a></span><span class="preprocessor">#define CAN_F13R2_FB12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l05433" name="l05433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd232459994d381a778abd4aa43bbb70"> 5433</a></span><span class="preprocessor">#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) </span></div>
|
||
<div class="line"><a id="l05434" name="l05434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3bbd5350aeb18966e2a40e2dc4223e3"> 5434</a></span><span class="preprocessor">#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk </span></div>
|
||
<div class="line"><a id="l05435" name="l05435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5bd52b9aa672bbd50a4a60f2e01c2d1"> 5435</a></span><span class="preprocessor">#define CAN_F13R2_FB13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l05436" name="l05436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga078d3a3cfba178ef1d8b0499e04326e1"> 5436</a></span><span class="preprocessor">#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) </span></div>
|
||
<div class="line"><a id="l05437" name="l05437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2d97199e363dd56cd9a455aec75ef1c"> 5437</a></span><span class="preprocessor">#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk </span></div>
|
||
<div class="line"><a id="l05438" name="l05438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab32e372353ed3e56c1aad445b2616c58"> 5438</a></span><span class="preprocessor">#define CAN_F13R2_FB14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l05439" name="l05439"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47b3e370df1a4ec6f8a69cd648a823cb"> 5439</a></span><span class="preprocessor">#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) </span></div>
|
||
<div class="line"><a id="l05440" name="l05440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0731f4e60125130bebf88d33fd4ae3ca"> 5440</a></span><span class="preprocessor">#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk </span></div>
|
||
<div class="line"><a id="l05441" name="l05441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb6696be0087357ad560cf24aa616021"> 5441</a></span><span class="preprocessor">#define CAN_F13R2_FB15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l05442" name="l05442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga760672a8bb29f0054fbef52bc3b71c0a"> 5442</a></span><span class="preprocessor">#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) </span></div>
|
||
<div class="line"><a id="l05443" name="l05443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1683c0cc3b3143a919f4dd59243eba9f"> 5443</a></span><span class="preprocessor">#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk </span></div>
|
||
<div class="line"><a id="l05444" name="l05444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83eca0eb5bea5956eeb4ab174c366f75"> 5444</a></span><span class="preprocessor">#define CAN_F13R2_FB16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l05445" name="l05445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ce486f2da389ec7cf80e6d102b7bc56"> 5445</a></span><span class="preprocessor">#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) </span></div>
|
||
<div class="line"><a id="l05446" name="l05446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2ed74a0929c6d397c14f49f114f13bf"> 5446</a></span><span class="preprocessor">#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk </span></div>
|
||
<div class="line"><a id="l05447" name="l05447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8db0458a7ddad624a4fe50458f06ebe7"> 5447</a></span><span class="preprocessor">#define CAN_F13R2_FB17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l05448" name="l05448"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d552599612053845141e0db3c89ca86"> 5448</a></span><span class="preprocessor">#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) </span></div>
|
||
<div class="line"><a id="l05449" name="l05449"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafde6cdff22bf29d31b5be1b309fe4dde"> 5449</a></span><span class="preprocessor">#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk </span></div>
|
||
<div class="line"><a id="l05450" name="l05450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga041ea608c1e920eca8e6b12027331761"> 5450</a></span><span class="preprocessor">#define CAN_F13R2_FB18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l05451" name="l05451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34fcf71e30ba700e1b975c6273a99de5"> 5451</a></span><span class="preprocessor">#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) </span></div>
|
||
<div class="line"><a id="l05452" name="l05452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb873fa1c32fbf6c5a2f3be93ba2f2e6"> 5452</a></span><span class="preprocessor">#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk </span></div>
|
||
<div class="line"><a id="l05453" name="l05453"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7e96e3beea2a3c1bffb610cebf01012"> 5453</a></span><span class="preprocessor">#define CAN_F13R2_FB19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l05454" name="l05454"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5b5c1ede34327d024575f334f3895b7"> 5454</a></span><span class="preprocessor">#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) </span></div>
|
||
<div class="line"><a id="l05455" name="l05455"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf82a4dfd4d3c7a13232479be997ed1f9"> 5455</a></span><span class="preprocessor">#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk </span></div>
|
||
<div class="line"><a id="l05456" name="l05456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa79bef1cef0cab3783a6351067a28670"> 5456</a></span><span class="preprocessor">#define CAN_F13R2_FB20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l05457" name="l05457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae823f61c39d0a97b05947308792e122"> 5457</a></span><span class="preprocessor">#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) </span></div>
|
||
<div class="line"><a id="l05458" name="l05458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7bf4384e44f002392339a71bc9c912c"> 5458</a></span><span class="preprocessor">#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk </span></div>
|
||
<div class="line"><a id="l05459" name="l05459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c135cf4d4773022ff4a284d13672082"> 5459</a></span><span class="preprocessor">#define CAN_F13R2_FB21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l05460" name="l05460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabea7b7f481ba0bc31d2909460e0bc54e"> 5460</a></span><span class="preprocessor">#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) </span></div>
|
||
<div class="line"><a id="l05461" name="l05461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7023986be02dd8f736e04e658844061"> 5461</a></span><span class="preprocessor">#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk </span></div>
|
||
<div class="line"><a id="l05462" name="l05462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06db7af2bea27dea18c2c36b0ff73afa"> 5462</a></span><span class="preprocessor">#define CAN_F13R2_FB22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l05463" name="l05463"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66fb2f382a4967515fa63a8454131fb9"> 5463</a></span><span class="preprocessor">#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) </span></div>
|
||
<div class="line"><a id="l05464" name="l05464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd059121f2a882342a409ebef8a96999"> 5464</a></span><span class="preprocessor">#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk </span></div>
|
||
<div class="line"><a id="l05465" name="l05465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb354c4f61952c7a85f0ef302163b0e9"> 5465</a></span><span class="preprocessor">#define CAN_F13R2_FB23_Pos (23U) </span></div>
|
||
<div class="line"><a id="l05466" name="l05466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bee64a9c633df1a34f5435406103085"> 5466</a></span><span class="preprocessor">#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) </span></div>
|
||
<div class="line"><a id="l05467" name="l05467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ef57f88bf1e6e34b0096013278926c0"> 5467</a></span><span class="preprocessor">#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk </span></div>
|
||
<div class="line"><a id="l05468" name="l05468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b46be4b9570584370ce39342df1d8c5"> 5468</a></span><span class="preprocessor">#define CAN_F13R2_FB24_Pos (24U) </span></div>
|
||
<div class="line"><a id="l05469" name="l05469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b4176f0f14ef22173c436763a6c483e"> 5469</a></span><span class="preprocessor">#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) </span></div>
|
||
<div class="line"><a id="l05470" name="l05470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4847de9f5b54fc5ce00e0fba69564d2d"> 5470</a></span><span class="preprocessor">#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk </span></div>
|
||
<div class="line"><a id="l05471" name="l05471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d1923954a761ac8ae84432354317806"> 5471</a></span><span class="preprocessor">#define CAN_F13R2_FB25_Pos (25U) </span></div>
|
||
<div class="line"><a id="l05472" name="l05472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad55a497a172eeaeb711d04f5cc81f411"> 5472</a></span><span class="preprocessor">#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) </span></div>
|
||
<div class="line"><a id="l05473" name="l05473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c415fa87c556bd8a4fc0f680d25f160"> 5473</a></span><span class="preprocessor">#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk </span></div>
|
||
<div class="line"><a id="l05474" name="l05474"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27b86a7f094043e077a15a6b36cab7fe"> 5474</a></span><span class="preprocessor">#define CAN_F13R2_FB26_Pos (26U) </span></div>
|
||
<div class="line"><a id="l05475" name="l05475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga117bfac3184445e41ca1709495cd1603"> 5475</a></span><span class="preprocessor">#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) </span></div>
|
||
<div class="line"><a id="l05476" name="l05476"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20487222c41a08fe68b9ce58dfd52fff"> 5476</a></span><span class="preprocessor">#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk </span></div>
|
||
<div class="line"><a id="l05477" name="l05477"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e7f1c6169d847c9acf1cc737ecf4e6f"> 5477</a></span><span class="preprocessor">#define CAN_F13R2_FB27_Pos (27U) </span></div>
|
||
<div class="line"><a id="l05478" name="l05478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2716a8a28de7a05f7f448d6b581928fe"> 5478</a></span><span class="preprocessor">#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) </span></div>
|
||
<div class="line"><a id="l05479" name="l05479"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0d5ca021778a6e84fd3c0ad8981255d"> 5479</a></span><span class="preprocessor">#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk </span></div>
|
||
<div class="line"><a id="l05480" name="l05480"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63a19687e787196f324bf380130defc4"> 5480</a></span><span class="preprocessor">#define CAN_F13R2_FB28_Pos (28U) </span></div>
|
||
<div class="line"><a id="l05481" name="l05481"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf9c86580fedab6d11c0e935e787fd31"> 5481</a></span><span class="preprocessor">#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) </span></div>
|
||
<div class="line"><a id="l05482" name="l05482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f0c8c09be20a14f29ab46d53dd712ba"> 5482</a></span><span class="preprocessor">#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk </span></div>
|
||
<div class="line"><a id="l05483" name="l05483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6229421e0e7697e0210ab0281c949f45"> 5483</a></span><span class="preprocessor">#define CAN_F13R2_FB29_Pos (29U) </span></div>
|
||
<div class="line"><a id="l05484" name="l05484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabed854c540fda686a9c51d21cf45cff3"> 5484</a></span><span class="preprocessor">#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) </span></div>
|
||
<div class="line"><a id="l05485" name="l05485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26161b84a5fc507f959b620c8e380703"> 5485</a></span><span class="preprocessor">#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk </span></div>
|
||
<div class="line"><a id="l05486" name="l05486"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36f10ded80a4a78d7cf92f8b6f3ed078"> 5486</a></span><span class="preprocessor">#define CAN_F13R2_FB30_Pos (30U) </span></div>
|
||
<div class="line"><a id="l05487" name="l05487"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga812a202cba22a21b94811b815cc57611"> 5487</a></span><span class="preprocessor">#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) </span></div>
|
||
<div class="line"><a id="l05488" name="l05488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e753550a0a8547c7f64346e22925012"> 5488</a></span><span class="preprocessor">#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk </span></div>
|
||
<div class="line"><a id="l05489" name="l05489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6af7dbbe2d835ab3d050971ac07a0ea3"> 5489</a></span><span class="preprocessor">#define CAN_F13R2_FB31_Pos (31U) </span></div>
|
||
<div class="line"><a id="l05490" name="l05490"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6eceafce3dabadee19db4afd0e0884d6"> 5490</a></span><span class="preprocessor">#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) </span></div>
|
||
<div class="line"><a id="l05491" name="l05491"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga305ac04b1c5198a4f82c78c570ce7f97"> 5491</a></span><span class="preprocessor">#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk </span></div>
|
||
<div class="line"><a id="l05493" name="l05493"></a><span class="lineno"> 5493</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l05494" name="l05494"></a><span class="lineno"> 5494</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l05495" name="l05495"></a><span class="lineno"> 5495</span><span class="comment">/* CRC calculation unit */</span></div>
|
||
<div class="line"><a id="l05496" name="l05496"></a><span class="lineno"> 5496</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l05497" name="l05497"></a><span class="lineno"> 5497</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l05498" name="l05498"></a><span class="lineno"> 5498</span><span class="comment">/******************* Bit definition for CRC_DR register *********************/</span></div>
|
||
<div class="line"><a id="l05499" name="l05499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3deebcf1cf5fae1957476154502b1fb5"> 5499</a></span><span class="preprocessor">#define CRC_DR_DR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05500" name="l05500"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd43c14689d281daa4e9a32bf8ec89e1"> 5500</a></span><span class="preprocessor">#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) </span></div>
|
||
<div class="line"><a id="l05501" name="l05501"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bf4701d3b15924e657942ce3caa4105"> 5501</a></span><span class="preprocessor">#define CRC_DR_DR CRC_DR_DR_Msk </span></div>
|
||
<div class="line"><a id="l05504" name="l05504"></a><span class="lineno"> 5504</span><span class="comment">/******************* Bit definition for CRC_IDR register ********************/</span></div>
|
||
<div class="line"><a id="l05505" name="l05505"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab63759809b1cd1cfdf46d92becc60f85"> 5505</a></span><span class="preprocessor">#define CRC_IDR_IDR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05506" name="l05506"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga306789258d5416a44e545aa2ad6b2f7a"> 5506</a></span><span class="preprocessor">#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) </span></div>
|
||
<div class="line"><a id="l05507" name="l05507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9a0feb3cf1d8c5871e663ca4a174cc0"> 5507</a></span><span class="preprocessor">#define CRC_IDR_IDR CRC_IDR_IDR_Msk </span></div>
|
||
<div class="line"><a id="l05510" name="l05510"></a><span class="lineno"> 5510</span><span class="comment">/******************** Bit definition for CRC_CR register ********************/</span></div>
|
||
<div class="line"><a id="l05511" name="l05511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a12ab5306d6320069e08e63cd9a56f1"> 5511</a></span><span class="preprocessor">#define CRC_CR_RESET_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05512" name="l05512"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04d46dadb6b31660c4ef0af2b00053f5"> 5512</a></span><span class="preprocessor">#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) </span></div>
|
||
<div class="line"><a id="l05513" name="l05513"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d57481fb891a0964b40f721354c56d7"> 5513</a></span><span class="preprocessor">#define CRC_CR_RESET CRC_CR_RESET_Msk </span></div>
|
||
<div class="line"><a id="l05515" name="l05515"></a><span class="lineno"> 5515</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l05516" name="l05516"></a><span class="lineno"> 5516</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l05517" name="l05517"></a><span class="lineno"> 5517</span><span class="comment">/* Digital to Analog Converter */</span></div>
|
||
<div class="line"><a id="l05518" name="l05518"></a><span class="lineno"> 5518</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l05519" name="l05519"></a><span class="lineno"> 5519</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l05520" name="l05520"></a><span class="lineno"> 5520</span><span class="comment">/*</span></div>
|
||
<div class="line"><a id="l05521" name="l05521"></a><span class="lineno"> 5521</span><span class="comment"> * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)</span></div>
|
||
<div class="line"><a id="l05522" name="l05522"></a><span class="lineno"> 5522</span><span class="comment"> */</span></div>
|
||
<div class="line"><a id="l05523" name="l05523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88aaf7e89ddcd648227fd514315c9838"> 5523</a></span><span class="preprocessor">#define DAC_CHANNEL2_SUPPORT </span></div>
|
||
<div class="line"><a id="l05524" name="l05524"></a><span class="lineno"> 5524</span><span class="comment">/******************** Bit definition for DAC_CR register ********************/</span></div>
|
||
<div class="line"><a id="l05525" name="l05525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7663eb8440e12383fc88241acbfc99cf"> 5525</a></span><span class="preprocessor">#define DAC_CR_EN1_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05526" name="l05526"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4462abe77801be4a752c73aa2ff9a70"> 5526</a></span><span class="preprocessor">#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) </span></div>
|
||
<div class="line"><a id="l05527" name="l05527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd8cedbb3dda03d56ac0ba92d2d9cefd"> 5527</a></span><span class="preprocessor">#define DAC_CR_EN1 DAC_CR_EN1_Msk </span></div>
|
||
<div class="line"><a id="l05528" name="l05528"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f43af44fba93c50bf4765608ec6d902"> 5528</a></span><span class="preprocessor">#define DAC_CR_BOFF1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l05529" name="l05529"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4cba0a69210b9ccb8566cfb83196e6f"> 5529</a></span><span class="preprocessor">#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) </span></div>
|
||
<div class="line"><a id="l05530" name="l05530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b1e2b83ae1ab889cb1e34a99746c9d8"> 5530</a></span><span class="preprocessor">#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk </span></div>
|
||
<div class="line"><a id="l05531" name="l05531"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ef4ab719505604c7a41e31c27fd05dd"> 5531</a></span><span class="preprocessor">#define DAC_CR_TEN1_Pos (2U) </span></div>
|
||
<div class="line"><a id="l05532" name="l05532"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1be7eb4a830047b463d611c2c813f437"> 5532</a></span><span class="preprocessor">#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) </span></div>
|
||
<div class="line"><a id="l05533" name="l05533"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga998aa4fd791ea2f4626df6ddc8fc7109"> 5533</a></span><span class="preprocessor">#define DAC_CR_TEN1 DAC_CR_TEN1_Msk </span></div>
|
||
<div class="line"><a id="l05535" name="l05535"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc5baf43a193c631ad3c05eb24b97a7b"> 5535</a></span><span class="preprocessor">#define DAC_CR_TSEL1_Pos (3U) </span></div>
|
||
<div class="line"><a id="l05536" name="l05536"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ca56925c2b1f9c7662c850146bec7bd"> 5536</a></span><span class="preprocessor">#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) </span></div>
|
||
<div class="line"><a id="l05537" name="l05537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf951c1a57a1a19e356df57d908f09c6c"> 5537</a></span><span class="preprocessor">#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk </span></div>
|
||
<div class="line"><a id="l05538" name="l05538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8dfa13ec123c583136e24b7890add45b"> 5538</a></span><span class="preprocessor">#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) </span></div>
|
||
<div class="line"><a id="l05539" name="l05539"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga265e32c4fc43310acdf3ebea01376766"> 5539</a></span><span class="preprocessor">#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) </span></div>
|
||
<div class="line"><a id="l05540" name="l05540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa625d7638422e90a616ac93edd4bf408"> 5540</a></span><span class="preprocessor">#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) </span></div>
|
||
<div class="line"><a id="l05542" name="l05542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16a0202d6e3295400dc21b2088d333e1"> 5542</a></span><span class="preprocessor">#define DAC_CR_WAVE1_Pos (6U) </span></div>
|
||
<div class="line"><a id="l05543" name="l05543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d85e9d75f265088a37b911f573e7dd3"> 5543</a></span><span class="preprocessor">#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) </span></div>
|
||
<div class="line"><a id="l05544" name="l05544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90491f31219d07175629eecdcdc9271e"> 5544</a></span><span class="preprocessor">#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk </span></div>
|
||
<div class="line"><a id="l05545" name="l05545"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0871e6466e3a7378103c431832ae525a"> 5545</a></span><span class="preprocessor">#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) </span></div>
|
||
<div class="line"><a id="l05546" name="l05546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48e167ae02d2ad5bc9fd30c2f8ea5b37"> 5546</a></span><span class="preprocessor">#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) </span></div>
|
||
<div class="line"><a id="l05548" name="l05548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga018b4d24c02a803f2efb996745f49015"> 5548</a></span><span class="preprocessor">#define DAC_CR_MAMP1_Pos (8U) </span></div>
|
||
<div class="line"><a id="l05549" name="l05549"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f4fc31ff760aaa38ad85da8c4f1918a"> 5549</a></span><span class="preprocessor">#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) </span></div>
|
||
<div class="line"><a id="l05550" name="l05550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bcf611b2f0b975513325895bf16e085"> 5550</a></span><span class="preprocessor">#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk </span></div>
|
||
<div class="line"><a id="l05551" name="l05551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4225dcce22b440fcd3a8ad96c5f2baec"> 5551</a></span><span class="preprocessor">#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) </span></div>
|
||
<div class="line"><a id="l05552" name="l05552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cc15817842cb7992d449c448684f68d"> 5552</a></span><span class="preprocessor">#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) </span></div>
|
||
<div class="line"><a id="l05553" name="l05553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fefef1d798a2685b03e44bd9fdac06b"> 5553</a></span><span class="preprocessor">#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) </span></div>
|
||
<div class="line"><a id="l05554" name="l05554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdc83b4feb742c632ba66f55d102432b"> 5554</a></span><span class="preprocessor">#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) </span></div>
|
||
<div class="line"><a id="l05556" name="l05556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1caf9621895f2a99c4b33a0908247b6"> 5556</a></span><span class="preprocessor">#define DAC_CR_DMAEN1_Pos (12U) </span></div>
|
||
<div class="line"><a id="l05557" name="l05557"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6509ff097fb987e9f1c592d6d5869356"> 5557</a></span><span class="preprocessor">#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) </span></div>
|
||
<div class="line"><a id="l05558" name="l05558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga995c19d8c8de9ee09057ec6151154e17"> 5558</a></span><span class="preprocessor">#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk </span></div>
|
||
<div class="line"><a id="l05559" name="l05559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a11a25b89aa18648594cb72bf3918bf"> 5559</a></span><span class="preprocessor">#define DAC_CR_DMAUDRIE1_Pos (13U) </span></div>
|
||
<div class="line"><a id="l05560" name="l05560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ad8aa68545055eac63ab43cc5d3da91"> 5560</a></span><span class="preprocessor">#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) </span></div>
|
||
<div class="line"><a id="l05561" name="l05561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbb0585e1053abf18cd129ad76a66bea"> 5561</a></span><span class="preprocessor">#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk </span></div>
|
||
<div class="line"><a id="l05562" name="l05562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2dbea8c55239069a24139f398785af4"> 5562</a></span><span class="preprocessor">#define DAC_CR_EN2_Pos (16U) </span></div>
|
||
<div class="line"><a id="l05563" name="l05563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84b276403310ffa2407b8c57996456e7"> 5563</a></span><span class="preprocessor">#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) </span></div>
|
||
<div class="line"><a id="l05564" name="l05564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa65db2420e02fc6813842f57134d898f"> 5564</a></span><span class="preprocessor">#define DAC_CR_EN2 DAC_CR_EN2_Msk </span></div>
|
||
<div class="line"><a id="l05565" name="l05565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb3eb9eaa48220ba7cac6204c4637b75"> 5565</a></span><span class="preprocessor">#define DAC_CR_BOFF2_Pos (17U) </span></div>
|
||
<div class="line"><a id="l05566" name="l05566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga088fea2fa6ece1301af6818b836469f3"> 5566</a></span><span class="preprocessor">#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) </span></div>
|
||
<div class="line"><a id="l05567" name="l05567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd6f660a5f15262beca06b9098a559e9"> 5567</a></span><span class="preprocessor">#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk </span></div>
|
||
<div class="line"><a id="l05568" name="l05568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2ef8fa2150330a16a2b19f17caa051e"> 5568</a></span><span class="preprocessor">#define DAC_CR_TEN2_Pos (18U) </span></div>
|
||
<div class="line"><a id="l05569" name="l05569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac16d129b7793ddcfef47bd642478d1df"> 5569</a></span><span class="preprocessor">#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) </span></div>
|
||
<div class="line"><a id="l05570" name="l05570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8fc527f6ddb787123da09d2085b772f"> 5570</a></span><span class="preprocessor">#define DAC_CR_TEN2 DAC_CR_TEN2_Msk </span></div>
|
||
<div class="line"><a id="l05572" name="l05572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80a933188591c4fbcad260c256105277"> 5572</a></span><span class="preprocessor">#define DAC_CR_TSEL2_Pos (19U) </span></div>
|
||
<div class="line"><a id="l05573" name="l05573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c9339a1dc175b09378d1168ab514333"> 5573</a></span><span class="preprocessor">#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) </span></div>
|
||
<div class="line"><a id="l05574" name="l05574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73b4d0ccff78f7c3862903e7b0e66302"> 5574</a></span><span class="preprocessor">#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk </span></div>
|
||
<div class="line"><a id="l05575" name="l05575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9753b87f31e7106ecf77b2f01a99b237"> 5575</a></span><span class="preprocessor">#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) </span></div>
|
||
<div class="line"><a id="l05576" name="l05576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac79323a6c81bfa5c8239b23cd3db737a"> 5576</a></span><span class="preprocessor">#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) </span></div>
|
||
<div class="line"><a id="l05577" name="l05577"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ad3da8a9c5fe9566d8ffe38916caaff"> 5577</a></span><span class="preprocessor">#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) </span></div>
|
||
<div class="line"><a id="l05579" name="l05579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7795c9de47dc6747045ee7e2e6fb8ba9"> 5579</a></span><span class="preprocessor">#define DAC_CR_WAVE2_Pos (22U) </span></div>
|
||
<div class="line"><a id="l05580" name="l05580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0420dd10713d50b05ab6c477ab502893"> 5580</a></span><span class="preprocessor">#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) </span></div>
|
||
<div class="line"><a id="l05581" name="l05581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf24e48cf288db4a4643057dd09e3a7b"> 5581</a></span><span class="preprocessor">#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk </span></div>
|
||
<div class="line"><a id="l05582" name="l05582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55d97d8bcbfdd72d5aeb9e9fbc0d592d"> 5582</a></span><span class="preprocessor">#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) </span></div>
|
||
<div class="line"><a id="l05583" name="l05583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4798bf254010b442b4ac4288c2f1b65f"> 5583</a></span><span class="preprocessor">#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) </span></div>
|
||
<div class="line"><a id="l05585" name="l05585"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cccefc999aeab6622afaf662c7c8c50"> 5585</a></span><span class="preprocessor">#define DAC_CR_MAMP2_Pos (24U) </span></div>
|
||
<div class="line"><a id="l05586" name="l05586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace1bce6cad4004ab884396a1d73a1725"> 5586</a></span><span class="preprocessor">#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) </span></div>
|
||
<div class="line"><a id="l05587" name="l05587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cf03fe2359cb0f11c33f793c2e92bdd"> 5587</a></span><span class="preprocessor">#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk </span></div>
|
||
<div class="line"><a id="l05588" name="l05588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8d952192721dbdcea8d707d43096454"> 5588</a></span><span class="preprocessor">#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) </span></div>
|
||
<div class="line"><a id="l05589" name="l05589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga860032e8196838cd36a655c1749139d6"> 5589</a></span><span class="preprocessor">#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) </span></div>
|
||
<div class="line"><a id="l05590" name="l05590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2147ffa3282e9ff22475e5d6040f269e"> 5590</a></span><span class="preprocessor">#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) </span></div>
|
||
<div class="line"><a id="l05591" name="l05591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0fe77a2029873111cbe723a5cba9c57"> 5591</a></span><span class="preprocessor">#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) </span></div>
|
||
<div class="line"><a id="l05593" name="l05593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga264e3d328584463c5164a7cca726cabb"> 5593</a></span><span class="preprocessor">#define DAC_CR_DMAEN2_Pos (28U) </span></div>
|
||
<div class="line"><a id="l05594" name="l05594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa85027944d9eddc64c42ee2ed98611f4"> 5594</a></span><span class="preprocessor">#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) </span></div>
|
||
<div class="line"><a id="l05595" name="l05595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f905c2ac89f976df6c4beffdde58b53"> 5595</a></span><span class="preprocessor">#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk </span></div>
|
||
<div class="line"><a id="l05596" name="l05596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6bf1e308092f2ef72387eb0fc5a8412"> 5596</a></span><span class="preprocessor">#define DAC_CR_DMAUDRIE2_Pos (29U) </span></div>
|
||
<div class="line"><a id="l05597" name="l05597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga239ab4f68c1a74d0e9423bbf6c98c5da"> 5597</a></span><span class="preprocessor">#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) </span></div>
|
||
<div class="line"><a id="l05598" name="l05598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga803e3bae78ced744b93aa76615303e15"> 5598</a></span><span class="preprocessor">#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk </span></div>
|
||
<div class="line"><a id="l05600" name="l05600"></a><span class="lineno"> 5600</span><span class="comment">/***************** Bit definition for DAC_SWTRIGR register ******************/</span></div>
|
||
<div class="line"><a id="l05601" name="l05601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32d8b5dafe7a5f4963e5f12656e48ee1"> 5601</a></span><span class="preprocessor">#define DAC_SWTRIGR_SWTRIG1_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05602" name="l05602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga819696c72cca7dd861aa7a3d9081e425"> 5602</a></span><span class="preprocessor">#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) </span></div>
|
||
<div class="line"><a id="l05603" name="l05603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga970ef02dffaceb35ff1dd7aceb67acdd"> 5603</a></span><span class="preprocessor">#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk </span></div>
|
||
<div class="line"><a id="l05604" name="l05604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb85dac71ddd76ce877fad49a47634b5"> 5604</a></span><span class="preprocessor">#define DAC_SWTRIGR_SWTRIG2_Pos (1U) </span></div>
|
||
<div class="line"><a id="l05605" name="l05605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga107859f1c6bd2dc30bf632941121bb05"> 5605</a></span><span class="preprocessor">#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) </span></div>
|
||
<div class="line"><a id="l05606" name="l05606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0e53585b505d21f5c457476bd5a18f8"> 5606</a></span><span class="preprocessor">#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk </span></div>
|
||
<div class="line"><a id="l05608" name="l05608"></a><span class="lineno"> 5608</span><span class="comment">/***************** Bit definition for DAC_DHR12R1 register ******************/</span></div>
|
||
<div class="line"><a id="l05609" name="l05609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3250ec13530e0e363f0ab92c149774f"> 5609</a></span><span class="preprocessor">#define DAC_DHR12R1_DACC1DHR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05610" name="l05610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga203fee3fe672b7468231c91ce8a55e4b"> 5610</a></span><span class="preprocessor">#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) </span></div>
|
||
<div class="line"><a id="l05611" name="l05611"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5295b5cb7f5d71ed2e8a310deb00013d"> 5611</a></span><span class="preprocessor">#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk </span></div>
|
||
<div class="line"><a id="l05613" name="l05613"></a><span class="lineno"> 5613</span><span class="comment">/***************** Bit definition for DAC_DHR12L1 register ******************/</span></div>
|
||
<div class="line"><a id="l05614" name="l05614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1dcdc73fc338b3548cddcf84fb0c951"> 5614</a></span><span class="preprocessor">#define DAC_DHR12L1_DACC1DHR_Pos (4U) </span></div>
|
||
<div class="line"><a id="l05615" name="l05615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga065dab2c8181ab7e3ff6cb43a86400c4"> 5615</a></span><span class="preprocessor">#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) </span></div>
|
||
<div class="line"><a id="l05616" name="l05616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d34667f8f4b753689c8c936c28471c5"> 5616</a></span><span class="preprocessor">#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk </span></div>
|
||
<div class="line"><a id="l05618" name="l05618"></a><span class="lineno"> 5618</span><span class="comment">/****************** Bit definition for DAC_DHR8R1 register ******************/</span></div>
|
||
<div class="line"><a id="l05619" name="l05619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b874c02d121c755a1d4523f2e39134e"> 5619</a></span><span class="preprocessor">#define DAC_DHR8R1_DACC1DHR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05620" name="l05620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacde0062be02bb512e2bdc5ee84b4f17f"> 5620</a></span><span class="preprocessor">#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) </span></div>
|
||
<div class="line"><a id="l05621" name="l05621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1fc9f022fe4a08f67c51646177b26cb"> 5621</a></span><span class="preprocessor">#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk </span></div>
|
||
<div class="line"><a id="l05623" name="l05623"></a><span class="lineno"> 5623</span><span class="comment">/***************** Bit definition for DAC_DHR12R2 register ******************/</span></div>
|
||
<div class="line"><a id="l05624" name="l05624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd13752ec5bc912023c608426e47908e"> 5624</a></span><span class="preprocessor">#define DAC_DHR12R2_DACC2DHR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05625" name="l05625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3cf4f31c9248dc74d00b813c1f2b2e0"> 5625</a></span><span class="preprocessor">#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) </span></div>
|
||
<div class="line"><a id="l05626" name="l05626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7506e369b37d55826042b540b10e44c7"> 5626</a></span><span class="preprocessor">#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk </span></div>
|
||
<div class="line"><a id="l05628" name="l05628"></a><span class="lineno"> 5628</span><span class="comment">/***************** Bit definition for DAC_DHR12L2 register ******************/</span></div>
|
||
<div class="line"><a id="l05629" name="l05629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fe559f6278c4abd3b5db6277e82925b"> 5629</a></span><span class="preprocessor">#define DAC_DHR12L2_DACC2DHR_Pos (4U) </span></div>
|
||
<div class="line"><a id="l05630" name="l05630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40a67db51971c777b7ee75c4da5bc8e8"> 5630</a></span><span class="preprocessor">#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) </span></div>
|
||
<div class="line"><a id="l05631" name="l05631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f66bd794202221e1a55547673b7abab"> 5631</a></span><span class="preprocessor">#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk </span></div>
|
||
<div class="line"><a id="l05633" name="l05633"></a><span class="lineno"> 5633</span><span class="comment">/****************** Bit definition for DAC_DHR8R2 register ******************/</span></div>
|
||
<div class="line"><a id="l05634" name="l05634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a8082de99f7eef453237a409763718b"> 5634</a></span><span class="preprocessor">#define DAC_DHR8R2_DACC2DHR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05635" name="l05635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf3e9e86edc54f83e02d2a0d3f486658"> 5635</a></span><span class="preprocessor">#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) </span></div>
|
||
<div class="line"><a id="l05636" name="l05636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7da94dc053e6637efb9ccb57b7ae481c"> 5636</a></span><span class="preprocessor">#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk </span></div>
|
||
<div class="line"><a id="l05638" name="l05638"></a><span class="lineno"> 5638</span><span class="comment">/***************** Bit definition for DAC_DHR12RD register ******************/</span></div>
|
||
<div class="line"><a id="l05639" name="l05639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d1a7b56cdc34694e1aa032be202e79d"> 5639</a></span><span class="preprocessor">#define DAC_DHR12RD_DACC1DHR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05640" name="l05640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cf050c1d3f7c651b461b463c8ae659e"> 5640</a></span><span class="preprocessor">#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) </span></div>
|
||
<div class="line"><a id="l05641" name="l05641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca45719f3d365c9495bdcf6364ae59f8"> 5641</a></span><span class="preprocessor">#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk </span></div>
|
||
<div class="line"><a id="l05642" name="l05642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae522220c8b02ab4bcf82f122a45997d3"> 5642</a></span><span class="preprocessor">#define DAC_DHR12RD_DACC2DHR_Pos (16U) </span></div>
|
||
<div class="line"><a id="l05643" name="l05643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0ae28d5d855fd8fe53de3d5fc2ee437"> 5643</a></span><span class="preprocessor">#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) </span></div>
|
||
<div class="line"><a id="l05644" name="l05644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3edd68db1697af93027e05f6b764c540"> 5644</a></span><span class="preprocessor">#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk </span></div>
|
||
<div class="line"><a id="l05646" name="l05646"></a><span class="lineno"> 5646</span><span class="comment">/***************** Bit definition for DAC_DHR12LD register ******************/</span></div>
|
||
<div class="line"><a id="l05647" name="l05647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa367fe7ed3f9b2d5114dcc46ccab7468"> 5647</a></span><span class="preprocessor">#define DAC_DHR12LD_DACC1DHR_Pos (4U) </span></div>
|
||
<div class="line"><a id="l05648" name="l05648"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbf9e7bb591e9c954f648ce36f5f9f90"> 5648</a></span><span class="preprocessor">#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) </span></div>
|
||
<div class="line"><a id="l05649" name="l05649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga203db656bfef6fedee17b99fb77b1bdd"> 5649</a></span><span class="preprocessor">#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk </span></div>
|
||
<div class="line"><a id="l05650" name="l05650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade1db665f01f9d179045057d0e857da0"> 5650</a></span><span class="preprocessor">#define DAC_DHR12LD_DACC2DHR_Pos (20U) </span></div>
|
||
<div class="line"><a id="l05651" name="l05651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c6a0375af61a42378851c55436f0e23"> 5651</a></span><span class="preprocessor">#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) </span></div>
|
||
<div class="line"><a id="l05652" name="l05652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8421d613b182aab8d6c58592bcda6c17"> 5652</a></span><span class="preprocessor">#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk </span></div>
|
||
<div class="line"><a id="l05654" name="l05654"></a><span class="lineno"> 5654</span><span class="comment">/****************** Bit definition for DAC_DHR8RD register ******************/</span></div>
|
||
<div class="line"><a id="l05655" name="l05655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac004fb7fdc93225fb835b27e39229a57"> 5655</a></span><span class="preprocessor">#define DAC_DHR8RD_DACC1DHR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05656" name="l05656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1b85c14a79ef230c7771336ab683678"> 5656</a></span><span class="preprocessor">#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) </span></div>
|
||
<div class="line"><a id="l05657" name="l05657"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9aee01ad181fa5b541864ed62907d70d"> 5657</a></span><span class="preprocessor">#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk </span></div>
|
||
<div class="line"><a id="l05658" name="l05658"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf849d0278349997f891d987def91224"> 5658</a></span><span class="preprocessor">#define DAC_DHR8RD_DACC2DHR_Pos (8U) </span></div>
|
||
<div class="line"><a id="l05659" name="l05659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3520456f0013e51d3d2c3694d86488b6"> 5659</a></span><span class="preprocessor">#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) </span></div>
|
||
<div class="line"><a id="l05660" name="l05660"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae31631eaac76ebecb059918c351ef3c9"> 5660</a></span><span class="preprocessor">#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk </span></div>
|
||
<div class="line"><a id="l05662" name="l05662"></a><span class="lineno"> 5662</span><span class="comment">/******************* Bit definition for DAC_DOR1 register *******************/</span></div>
|
||
<div class="line"><a id="l05663" name="l05663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacef98a0af264fa6b23a187e74d7c82d"> 5663</a></span><span class="preprocessor">#define DAC_DOR1_DACC1DOR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05664" name="l05664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae11b4b811ab6ba4e981ee60318f7d1a4"> 5664</a></span><span class="preprocessor">#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) </span></div>
|
||
<div class="line"><a id="l05665" name="l05665"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b4192938e039dc25a7df8fcc5f3932a"> 5665</a></span><span class="preprocessor">#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk </span></div>
|
||
<div class="line"><a id="l05667" name="l05667"></a><span class="lineno"> 5667</span><span class="comment">/******************* Bit definition for DAC_DOR2 register *******************/</span></div>
|
||
<div class="line"><a id="l05668" name="l05668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17aa70d42a524b2dd911326fa65630f1"> 5668</a></span><span class="preprocessor">#define DAC_DOR2_DACC2DOR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05669" name="l05669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a6d4d4b3b48221d195a3acb51ad6fbe"> 5669</a></span><span class="preprocessor">#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) </span></div>
|
||
<div class="line"><a id="l05670" name="l05670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacaaa39c1e82279918918b072fd56db04"> 5670</a></span><span class="preprocessor">#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk </span></div>
|
||
<div class="line"><a id="l05672" name="l05672"></a><span class="lineno"> 5672</span><span class="comment">/******************** Bit definition for DAC_SR register ********************/</span></div>
|
||
<div class="line"><a id="l05673" name="l05673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadeeefee596334ca7c00e9dfa12cfdd83"> 5673</a></span><span class="preprocessor">#define DAC_SR_DMAUDR1_Pos (13U) </span></div>
|
||
<div class="line"><a id="l05674" name="l05674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75ded00bd7866ed6e38c52beb4854d64"> 5674</a></span><span class="preprocessor">#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) </span></div>
|
||
<div class="line"><a id="l05675" name="l05675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d2048d6b521fb0946dc8c4e577a49c0"> 5675</a></span><span class="preprocessor">#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk </span></div>
|
||
<div class="line"><a id="l05676" name="l05676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa918fd0130e9edc2b4a21ff4ba17aa5e"> 5676</a></span><span class="preprocessor">#define DAC_SR_DMAUDR2_Pos (29U) </span></div>
|
||
<div class="line"><a id="l05677" name="l05677"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccadc59668f44b530b866ebcce6f0c74"> 5677</a></span><span class="preprocessor">#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) </span></div>
|
||
<div class="line"><a id="l05678" name="l05678"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf16e48ab85d9261c5b599c56b14aea5d"> 5678</a></span><span class="preprocessor">#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk </span></div>
|
||
<div class="line"><a id="l05680" name="l05680"></a><span class="lineno"> 5680</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l05681" name="l05681"></a><span class="lineno"> 5681</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l05682" name="l05682"></a><span class="lineno"> 5682</span><span class="comment">/* DCMI */</span></div>
|
||
<div class="line"><a id="l05683" name="l05683"></a><span class="lineno"> 5683</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l05684" name="l05684"></a><span class="lineno"> 5684</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l05685" name="l05685"></a><span class="lineno"> 5685</span><span class="comment">/******************** Bits definition for DCMI_CR register ******************/</span></div>
|
||
<div class="line"><a id="l05686" name="l05686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa3a454c9236fd257a8bfb17071637dc"> 5686</a></span><span class="preprocessor">#define DCMI_CR_CAPTURE_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05687" name="l05687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15f2c325d001c3d3d5a1939106584fb3"> 5687</a></span><span class="preprocessor">#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) </span></div>
|
||
<div class="line"><a id="l05688" name="l05688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f8b54f16f7e17b3da807b6dae1d649e"> 5688</a></span><span class="preprocessor">#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk </span></div>
|
||
<div class="line"><a id="l05689" name="l05689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade41604d334508afeb14b82e21f421be"> 5689</a></span><span class="preprocessor">#define DCMI_CR_CM_Pos (1U) </span></div>
|
||
<div class="line"><a id="l05690" name="l05690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9213d50a3270e1e2df73b73a97300b0"> 5690</a></span><span class="preprocessor">#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) </span></div>
|
||
<div class="line"><a id="l05691" name="l05691"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47bacab13c750dc0ecc9aaf935d1f435"> 5691</a></span><span class="preprocessor">#define DCMI_CR_CM DCMI_CR_CM_Msk </span></div>
|
||
<div class="line"><a id="l05692" name="l05692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cd43899ca78a773ae0132b07b795b73"> 5692</a></span><span class="preprocessor">#define DCMI_CR_CROP_Pos (2U) </span></div>
|
||
<div class="line"><a id="l05693" name="l05693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45cccbefdbcefa8f1b4effbd30e4fd57"> 5693</a></span><span class="preprocessor">#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) </span></div>
|
||
<div class="line"><a id="l05694" name="l05694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bb929e7d3b4ea62e80ba66c7bc5c216"> 5694</a></span><span class="preprocessor">#define DCMI_CR_CROP DCMI_CR_CROP_Msk </span></div>
|
||
<div class="line"><a id="l05695" name="l05695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab93600cf87f62ab21c0270966eb49853"> 5695</a></span><span class="preprocessor">#define DCMI_CR_JPEG_Pos (3U) </span></div>
|
||
<div class="line"><a id="l05696" name="l05696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef4bc80edc936ebf381a4c2149a9aa9c"> 5696</a></span><span class="preprocessor">#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) </span></div>
|
||
<div class="line"><a id="l05697" name="l05697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd10a1f9c5a588f468e550bb56051b03"> 5697</a></span><span class="preprocessor">#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk </span></div>
|
||
<div class="line"><a id="l05698" name="l05698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02f02e4a058fb7854a3e9c5f79cb6fb3"> 5698</a></span><span class="preprocessor">#define DCMI_CR_ESS_Pos (4U) </span></div>
|
||
<div class="line"><a id="l05699" name="l05699"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd4f4d68488cc78decac4e7fe8838655"> 5699</a></span><span class="preprocessor">#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) </span></div>
|
||
<div class="line"><a id="l05700" name="l05700"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46851e2b6011a84ecdfc5218a855ad78"> 5700</a></span><span class="preprocessor">#define DCMI_CR_ESS DCMI_CR_ESS_Msk </span></div>
|
||
<div class="line"><a id="l05701" name="l05701"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3929ea65cd626b5f7d472af5d21f4c1b"> 5701</a></span><span class="preprocessor">#define DCMI_CR_PCKPOL_Pos (5U) </span></div>
|
||
<div class="line"><a id="l05702" name="l05702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09ec8d81a49c61ae9fd02cc5de658f8c"> 5702</a></span><span class="preprocessor">#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) </span></div>
|
||
<div class="line"><a id="l05703" name="l05703"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00769f93cbcc2693c8fd42f0e8aa31ad"> 5703</a></span><span class="preprocessor">#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk </span></div>
|
||
<div class="line"><a id="l05704" name="l05704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fd28eb0687c6a1704733a53c08dd797"> 5704</a></span><span class="preprocessor">#define DCMI_CR_HSPOL_Pos (6U) </span></div>
|
||
<div class="line"><a id="l05705" name="l05705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c027a03833f80bfddbf2205d092769e"> 5705</a></span><span class="preprocessor">#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) </span></div>
|
||
<div class="line"><a id="l05706" name="l05706"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2042d3da2719b7c9c6708e0566e46c5"> 5706</a></span><span class="preprocessor">#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk </span></div>
|
||
<div class="line"><a id="l05707" name="l05707"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c2656a42de18085bf84a731e82df2a7"> 5707</a></span><span class="preprocessor">#define DCMI_CR_VSPOL_Pos (7U) </span></div>
|
||
<div class="line"><a id="l05708" name="l05708"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3ac7d448956eaddaa8f416598662089"> 5708</a></span><span class="preprocessor">#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) </span></div>
|
||
<div class="line"><a id="l05709" name="l05709"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga497c7c4bf6fcc842ffc45eedc876ffdb"> 5709</a></span><span class="preprocessor">#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk </span></div>
|
||
<div class="line"><a id="l05710" name="l05710"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13263970b396f75e00278ff7b78b313d"> 5710</a></span><span class="preprocessor">#define DCMI_CR_FCRC_0 0x00000100U </span></div>
|
||
<div class="line"><a id="l05711" name="l05711"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1658bed43e7d0c3579151498104d5747"> 5711</a></span><span class="preprocessor">#define DCMI_CR_FCRC_1 0x00000200U </span></div>
|
||
<div class="line"><a id="l05712" name="l05712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9efa61252be662ff473d14156f09d32c"> 5712</a></span><span class="preprocessor">#define DCMI_CR_EDM_0 0x00000400U </span></div>
|
||
<div class="line"><a id="l05713" name="l05713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga884b51a3e5bf0d615944f46b1751a97c"> 5713</a></span><span class="preprocessor">#define DCMI_CR_EDM_1 0x00000800U </span></div>
|
||
<div class="line"><a id="l05714" name="l05714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57ff97d20c4f41748dda19d71f7da8d9"> 5714</a></span><span class="preprocessor">#define DCMI_CR_CRE_Pos (12U) </span></div>
|
||
<div class="line"><a id="l05715" name="l05715"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3810273d9f0eeae0f5b8e3d3b5a14b3a"> 5715</a></span><span class="preprocessor">#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) </span></div>
|
||
<div class="line"><a id="l05716" name="l05716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79e4190a772dc07958573a110106db69"> 5716</a></span><span class="preprocessor">#define DCMI_CR_CRE DCMI_CR_CRE_Msk </span></div>
|
||
<div class="line"><a id="l05717" name="l05717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef22c09278ab657cc3af24dcbff864be"> 5717</a></span><span class="preprocessor">#define DCMI_CR_ENABLE_Pos (14U) </span></div>
|
||
<div class="line"><a id="l05718" name="l05718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38f1b2217a7ae182f5cb6739fd28c0cc"> 5718</a></span><span class="preprocessor">#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) </span></div>
|
||
<div class="line"><a id="l05719" name="l05719"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fa2461ca2f0629c2ddd77fea94bbd06"> 5719</a></span><span class="preprocessor">#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk </span></div>
|
||
<div class="line"><a id="l05720" name="l05720"></a><span class="lineno"> 5720</span> </div>
|
||
<div class="line"><a id="l05721" name="l05721"></a><span class="lineno"> 5721</span><span class="comment">/******************** Bits definition for DCMI_SR register ******************/</span></div>
|
||
<div class="line"><a id="l05722" name="l05722"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5e7fd85cd8977bbd867cacd10016b9a"> 5722</a></span><span class="preprocessor">#define DCMI_SR_HSYNC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05723" name="l05723"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52a8a170e5bc418b043e712c65852121"> 5723</a></span><span class="preprocessor">#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) </span></div>
|
||
<div class="line"><a id="l05724" name="l05724"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb10174e5a89c32d6413ecf77e6610a0"> 5724</a></span><span class="preprocessor">#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk </span></div>
|
||
<div class="line"><a id="l05725" name="l05725"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8518f9299351064b5d42d297d3337e9a"> 5725</a></span><span class="preprocessor">#define DCMI_SR_VSYNC_Pos (1U) </span></div>
|
||
<div class="line"><a id="l05726" name="l05726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae563614237e37f375f3a0cea5d01d272"> 5726</a></span><span class="preprocessor">#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) </span></div>
|
||
<div class="line"><a id="l05727" name="l05727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9608c2fdd5feb3c8c022545f8d7e6adf"> 5727</a></span><span class="preprocessor">#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk </span></div>
|
||
<div class="line"><a id="l05728" name="l05728"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4425f4dfb86dbb4249d27b92b90caafe"> 5728</a></span><span class="preprocessor">#define DCMI_SR_FNE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l05729" name="l05729"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad19357d2286c9647ce0fce32c8b0578c"> 5729</a></span><span class="preprocessor">#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) </span></div>
|
||
<div class="line"><a id="l05730" name="l05730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga990aaedf052bc3b9ebd115f06aa43ab2"> 5730</a></span><span class="preprocessor">#define DCMI_SR_FNE DCMI_SR_FNE_Msk </span></div>
|
||
<div class="line"><a id="l05731" name="l05731"></a><span class="lineno"> 5731</span> </div>
|
||
<div class="line"><a id="l05732" name="l05732"></a><span class="lineno"> 5732</span><span class="comment">/******************** Bits definition for DCMI_RIS register *****************/</span></div>
|
||
<div class="line"><a id="l05733" name="l05733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dd9257e83488a0c5a4f22d1b687227e"> 5733</a></span><span class="preprocessor">#define DCMI_RIS_FRAME_RIS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05734" name="l05734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28f7059f0838e9089197abd09dbb1773"> 5734</a></span><span class="preprocessor">#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) </span></div>
|
||
<div class="line"><a id="l05735" name="l05735"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga188d7dafa72efe56f8363ffee4b0662b"> 5735</a></span><span class="preprocessor">#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk </span></div>
|
||
<div class="line"><a id="l05736" name="l05736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace86e6047cb5cae4000378626d291678"> 5736</a></span><span class="preprocessor">#define DCMI_RIS_OVR_RIS_Pos (1U) </span></div>
|
||
<div class="line"><a id="l05737" name="l05737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8bf3ee23039b601106d1d91e9acced53"> 5737</a></span><span class="preprocessor">#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) </span></div>
|
||
<div class="line"><a id="l05738" name="l05738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaeb2e93438e3aa6b72a2f897c3ed86bc"> 5738</a></span><span class="preprocessor">#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk </span></div>
|
||
<div class="line"><a id="l05739" name="l05739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae917e074e286a7a44b7d192d540eb367"> 5739</a></span><span class="preprocessor">#define DCMI_RIS_ERR_RIS_Pos (2U) </span></div>
|
||
<div class="line"><a id="l05740" name="l05740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92f212d4ebfc932e28a9a190f96e1861"> 5740</a></span><span class="preprocessor">#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) </span></div>
|
||
<div class="line"><a id="l05741" name="l05741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60312c64ac11224348e6817b16b38ace"> 5741</a></span><span class="preprocessor">#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk </span></div>
|
||
<div class="line"><a id="l05742" name="l05742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b953f571921dbaecbf126b7768ce9e0"> 5742</a></span><span class="preprocessor">#define DCMI_RIS_VSYNC_RIS_Pos (3U) </span></div>
|
||
<div class="line"><a id="l05743" name="l05743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf2902c19b9063c83d8e269f83428a6d"> 5743</a></span><span class="preprocessor">#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) </span></div>
|
||
<div class="line"><a id="l05744" name="l05744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57777e4dfeb6df63ffc1eee8e1fd51e9"> 5744</a></span><span class="preprocessor">#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk </span></div>
|
||
<div class="line"><a id="l05745" name="l05745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6c35d6c01b791049b926e626703a043"> 5745</a></span><span class="preprocessor">#define DCMI_RIS_LINE_RIS_Pos (4U) </span></div>
|
||
<div class="line"><a id="l05746" name="l05746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga143c2c95deb861fb392953a15b99c174"> 5746</a></span><span class="preprocessor">#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) </span></div>
|
||
<div class="line"><a id="l05747" name="l05747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7df083b857fd655d11a90a7a1ee94d66"> 5747</a></span><span class="preprocessor">#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk </span></div>
|
||
<div class="line"><a id="l05748" name="l05748"></a><span class="lineno"> 5748</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l05749" name="l05749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99308f49b63dd49db671a2a26d0d07fa"> 5749</a></span><span class="preprocessor">#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS</span></div>
|
||
<div class="line"><a id="l05750" name="l05750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae893218ce7d16540e5af7c3afb03bc98"> 5750</a></span><span class="preprocessor">#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS</span></div>
|
||
<div class="line"><a id="l05751" name="l05751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf03ca1f0e5e1a7868c07c8237d7e33a3"> 5751</a></span><span class="preprocessor">#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS</span></div>
|
||
<div class="line"><a id="l05752" name="l05752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08625c101d8419ca58cc7032f4a936ec"> 5752</a></span><span class="preprocessor">#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS</span></div>
|
||
<div class="line"><a id="l05753" name="l05753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf06b386a61d97e046a7f0546478b91b8"> 5753</a></span><span class="preprocessor">#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS</span></div>
|
||
<div class="line"><a id="l05754" name="l05754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga510c3f423fdddf8a41b6b69d55b6c66d"> 5754</a></span><span class="preprocessor">#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS</span></div>
|
||
<div class="line"><a id="l05755" name="l05755"></a><span class="lineno"> 5755</span> </div>
|
||
<div class="line"><a id="l05756" name="l05756"></a><span class="lineno"> 5756</span><span class="comment">/******************** Bits definition for DCMI_IER register *****************/</span></div>
|
||
<div class="line"><a id="l05757" name="l05757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8bd2b1d1f6d0b24c0871bd617f0fcca8"> 5757</a></span><span class="preprocessor">#define DCMI_IER_FRAME_IE_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05758" name="l05758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f620e3f5ac8a334cda95e761e7e410b"> 5758</a></span><span class="preprocessor">#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) </span></div>
|
||
<div class="line"><a id="l05759" name="l05759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78d30c219bf7b5ebe0f8ee74cbdae61d"> 5759</a></span><span class="preprocessor">#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk </span></div>
|
||
<div class="line"><a id="l05760" name="l05760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e618e53a00804740c96a6a87fe4eb5d"> 5760</a></span><span class="preprocessor">#define DCMI_IER_OVR_IE_Pos (1U) </span></div>
|
||
<div class="line"><a id="l05761" name="l05761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b10a920924f2a6b2fbc3a29e1dfab62"> 5761</a></span><span class="preprocessor">#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) </span></div>
|
||
<div class="line"><a id="l05762" name="l05762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3526fa00f78f05a35551294374134d81"> 5762</a></span><span class="preprocessor">#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk </span></div>
|
||
<div class="line"><a id="l05763" name="l05763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71ba0a7a3bdbddd9117d28170b69f043"> 5763</a></span><span class="preprocessor">#define DCMI_IER_ERR_IE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l05764" name="l05764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3fdbc46256c696cc52602dbb3c275090"> 5764</a></span><span class="preprocessor">#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) </span></div>
|
||
<div class="line"><a id="l05765" name="l05765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc9d64d6edc4e8ff9452db0065c12831"> 5765</a></span><span class="preprocessor">#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk </span></div>
|
||
<div class="line"><a id="l05766" name="l05766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e02ca273e7458bbdb7e204666748b19"> 5766</a></span><span class="preprocessor">#define DCMI_IER_VSYNC_IE_Pos (3U) </span></div>
|
||
<div class="line"><a id="l05767" name="l05767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8df43e41d5ffd5f74e8ab0e892a5eb9"> 5767</a></span><span class="preprocessor">#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) </span></div>
|
||
<div class="line"><a id="l05768" name="l05768"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2f335c69d18e49ffb5314e85ac1f4fc"> 5768</a></span><span class="preprocessor">#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk </span></div>
|
||
<div class="line"><a id="l05769" name="l05769"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8afd81592f141ee1f028a7e65f4418d1"> 5769</a></span><span class="preprocessor">#define DCMI_IER_LINE_IE_Pos (4U) </span></div>
|
||
<div class="line"><a id="l05770" name="l05770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61b024ef7c45524af9a733769c453ee4"> 5770</a></span><span class="preprocessor">#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) </span></div>
|
||
<div class="line"><a id="l05771" name="l05771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a06c700c5e779551834862a2d14612e"> 5771</a></span><span class="preprocessor">#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk </span></div>
|
||
<div class="line"><a id="l05772" name="l05772"></a><span class="lineno"> 5772</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l05773" name="l05773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f313352a86f6b09726e63f89e161187"> 5773</a></span><span class="preprocessor">#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE</span></div>
|
||
<div class="line"><a id="l05774" name="l05774"></a><span class="lineno"> 5774</span> </div>
|
||
<div class="line"><a id="l05775" name="l05775"></a><span class="lineno"> 5775</span><span class="comment">/******************** Bits definition for DCMI_MIS register *****************/</span></div>
|
||
<div class="line"><a id="l05776" name="l05776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf50f1645c609ecf4c86539214559b13a"> 5776</a></span><span class="preprocessor">#define DCMI_MIS_FRAME_MIS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05777" name="l05777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bccb72ae32d9e1af338767329728ecf"> 5777</a></span><span class="preprocessor">#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) </span></div>
|
||
<div class="line"><a id="l05778" name="l05778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga941155c6f476426df918e806a0f32e4e"> 5778</a></span><span class="preprocessor">#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk </span></div>
|
||
<div class="line"><a id="l05779" name="l05779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac62263a4027c8db50c73af02ce4c61f1"> 5779</a></span><span class="preprocessor">#define DCMI_MIS_OVR_MIS_Pos (1U) </span></div>
|
||
<div class="line"><a id="l05780" name="l05780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56960bc01ad1ed046aab7db0fc2d0a5e"> 5780</a></span><span class="preprocessor">#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) </span></div>
|
||
<div class="line"><a id="l05781" name="l05781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bf479b833da567f2ee940d570a54517"> 5781</a></span><span class="preprocessor">#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk </span></div>
|
||
<div class="line"><a id="l05782" name="l05782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga794cffd7108134514729d69dc29e3adc"> 5782</a></span><span class="preprocessor">#define DCMI_MIS_ERR_MIS_Pos (2U) </span></div>
|
||
<div class="line"><a id="l05783" name="l05783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae49e11fcd9d6e779c0f03fb206ba50dd"> 5783</a></span><span class="preprocessor">#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) </span></div>
|
||
<div class="line"><a id="l05784" name="l05784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46deae49ce6acb93a2c9827b7de125ed"> 5784</a></span><span class="preprocessor">#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk </span></div>
|
||
<div class="line"><a id="l05785" name="l05785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6e09a3ece4317ea262cd9f5e0e5a2a7"> 5785</a></span><span class="preprocessor">#define DCMI_MIS_VSYNC_MIS_Pos (3U) </span></div>
|
||
<div class="line"><a id="l05786" name="l05786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4ff5663b22aac5464b75cb3514f262e"> 5786</a></span><span class="preprocessor">#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) </span></div>
|
||
<div class="line"><a id="l05787" name="l05787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8559771f71aa7c77eec58339c628f26a"> 5787</a></span><span class="preprocessor">#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk </span></div>
|
||
<div class="line"><a id="l05788" name="l05788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88e5fa975bd3ac9ba03ef27f9647c916"> 5788</a></span><span class="preprocessor">#define DCMI_MIS_LINE_MIS_Pos (4U) </span></div>
|
||
<div class="line"><a id="l05789" name="l05789"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06dbeaf099a326aa55f1ea65dd821af4"> 5789</a></span><span class="preprocessor">#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) </span></div>
|
||
<div class="line"><a id="l05790" name="l05790"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga340adf786e70c8b9ebc2deef9aa30ced"> 5790</a></span><span class="preprocessor">#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk </span></div>
|
||
<div class="line"><a id="l05791" name="l05791"></a><span class="lineno"> 5791</span> </div>
|
||
<div class="line"><a id="l05792" name="l05792"></a><span class="lineno"> 5792</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l05793" name="l05793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73b7d7359389df61668089920ed5b28e"> 5793</a></span><span class="preprocessor">#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS</span></div>
|
||
<div class="line"><a id="l05794" name="l05794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacaced5931c5790bdf6fc9ede4591496"> 5794</a></span><span class="preprocessor">#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS</span></div>
|
||
<div class="line"><a id="l05795" name="l05795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga117dd3b10b1c7a03016fce867a6a8281"> 5795</a></span><span class="preprocessor">#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS</span></div>
|
||
<div class="line"><a id="l05796" name="l05796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a02749de4576d3631cf35dbb4e4bf5c"> 5796</a></span><span class="preprocessor">#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS</span></div>
|
||
<div class="line"><a id="l05797" name="l05797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77aad6389ea95913c34b2ba3a14cfdca"> 5797</a></span><span class="preprocessor">#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS</span></div>
|
||
<div class="line"><a id="l05798" name="l05798"></a><span class="lineno"> 5798</span> </div>
|
||
<div class="line"><a id="l05799" name="l05799"></a><span class="lineno"> 5799</span><span class="comment">/******************** Bits definition for DCMI_ICR register *****************/</span></div>
|
||
<div class="line"><a id="l05800" name="l05800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa522718b7f9eeec5df1dc941c4caa092"> 5800</a></span><span class="preprocessor">#define DCMI_ICR_FRAME_ISC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05801" name="l05801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6bc8bd2a6b5de3b723915ab6fbfc9603"> 5801</a></span><span class="preprocessor">#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) </span></div>
|
||
<div class="line"><a id="l05802" name="l05802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ce2decf4166be0a5376ea2810403030"> 5802</a></span><span class="preprocessor">#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk </span></div>
|
||
<div class="line"><a id="l05803" name="l05803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03be33d65b8a9c6c9c2ed69ba286f387"> 5803</a></span><span class="preprocessor">#define DCMI_ICR_OVR_ISC_Pos (1U) </span></div>
|
||
<div class="line"><a id="l05804" name="l05804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63ef3349d85e073e5a212e523ad1ac50"> 5804</a></span><span class="preprocessor">#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) </span></div>
|
||
<div class="line"><a id="l05805" name="l05805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9d9f8083bf587a6e6d6f5470fb29a88"> 5805</a></span><span class="preprocessor">#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk </span></div>
|
||
<div class="line"><a id="l05806" name="l05806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef56d07e9430cebe51d917c96a46bd4a"> 5806</a></span><span class="preprocessor">#define DCMI_ICR_ERR_ISC_Pos (2U) </span></div>
|
||
<div class="line"><a id="l05807" name="l05807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab819f4eb028d0bce638a7fc5aac68e1e"> 5807</a></span><span class="preprocessor">#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) </span></div>
|
||
<div class="line"><a id="l05808" name="l05808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8da69cdd9d4f4c280279fa05fdf235bc"> 5808</a></span><span class="preprocessor">#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk </span></div>
|
||
<div class="line"><a id="l05809" name="l05809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0087c275317c3692ea9ba74b5792f2a"> 5809</a></span><span class="preprocessor">#define DCMI_ICR_VSYNC_ISC_Pos (3U) </span></div>
|
||
<div class="line"><a id="l05810" name="l05810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f7f889d6c3a2e1f6300618333b54b78"> 5810</a></span><span class="preprocessor">#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) </span></div>
|
||
<div class="line"><a id="l05811" name="l05811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedd101bdda4f13c30d7af5a85156a047"> 5811</a></span><span class="preprocessor">#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk </span></div>
|
||
<div class="line"><a id="l05812" name="l05812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga166cd5d629e51a08b20b7fd3ceb8739a"> 5812</a></span><span class="preprocessor">#define DCMI_ICR_LINE_ISC_Pos (4U) </span></div>
|
||
<div class="line"><a id="l05813" name="l05813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdca5913b4eae2aeb02469e77434d557"> 5813</a></span><span class="preprocessor">#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) </span></div>
|
||
<div class="line"><a id="l05814" name="l05814"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae64182a042ceb8275c54819458b1ca9c"> 5814</a></span><span class="preprocessor">#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk </span></div>
|
||
<div class="line"><a id="l05815" name="l05815"></a><span class="lineno"> 5815</span> </div>
|
||
<div class="line"><a id="l05816" name="l05816"></a><span class="lineno"> 5816</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l05817" name="l05817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0318fb46a8594834640d08a9ae06f79e"> 5817</a></span><span class="preprocessor">#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC</span></div>
|
||
<div class="line"><a id="l05818" name="l05818"></a><span class="lineno"> 5818</span> </div>
|
||
<div class="line"><a id="l05819" name="l05819"></a><span class="lineno"> 5819</span><span class="comment">/******************** Bits definition for DCMI_ESCR register ******************/</span></div>
|
||
<div class="line"><a id="l05820" name="l05820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga606ebaec78811eb133a2adef912d16ee"> 5820</a></span><span class="preprocessor">#define DCMI_ESCR_FSC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05821" name="l05821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ce58bb8ea8ca57dc51016be5eadb2d6"> 5821</a></span><span class="preprocessor">#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) </span></div>
|
||
<div class="line"><a id="l05822" name="l05822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga822e9340b78048f18504488c6af07b17"> 5822</a></span><span class="preprocessor">#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk </span></div>
|
||
<div class="line"><a id="l05823" name="l05823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2a19d08646392458bfc5b1db2fcd401"> 5823</a></span><span class="preprocessor">#define DCMI_ESCR_LSC_Pos (8U) </span></div>
|
||
<div class="line"><a id="l05824" name="l05824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70700ed96c539f193ff3dde57c41e414"> 5824</a></span><span class="preprocessor">#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) </span></div>
|
||
<div class="line"><a id="l05825" name="l05825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f673b3dfe4d73c36ec941780cc91ce5"> 5825</a></span><span class="preprocessor">#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk </span></div>
|
||
<div class="line"><a id="l05826" name="l05826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ae8266875df6979d97b6f2ef0bf9dfd"> 5826</a></span><span class="preprocessor">#define DCMI_ESCR_LEC_Pos (16U) </span></div>
|
||
<div class="line"><a id="l05827" name="l05827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab48737db683e9eb6c654fb009eccd7be"> 5827</a></span><span class="preprocessor">#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) </span></div>
|
||
<div class="line"><a id="l05828" name="l05828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga174d7f3b7ae442fa4fa8a95bc551d7fe"> 5828</a></span><span class="preprocessor">#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk </span></div>
|
||
<div class="line"><a id="l05829" name="l05829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8fa0ea70437313587a37aa718f1b2be"> 5829</a></span><span class="preprocessor">#define DCMI_ESCR_FEC_Pos (24U) </span></div>
|
||
<div class="line"><a id="l05830" name="l05830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79ae393fc1fb2182bdf482cc4a1f5ff3"> 5830</a></span><span class="preprocessor">#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) </span></div>
|
||
<div class="line"><a id="l05831" name="l05831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab398e0b4ccde3ef98da25a420ad0d47d"> 5831</a></span><span class="preprocessor">#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk </span></div>
|
||
<div class="line"><a id="l05832" name="l05832"></a><span class="lineno"> 5832</span> </div>
|
||
<div class="line"><a id="l05833" name="l05833"></a><span class="lineno"> 5833</span><span class="comment">/******************** Bits definition for DCMI_ESUR register ******************/</span></div>
|
||
<div class="line"><a id="l05834" name="l05834"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8ab290d57eea4b8ee06ab5d5be8260c"> 5834</a></span><span class="preprocessor">#define DCMI_ESUR_FSU_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05835" name="l05835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga036205fd064f7ac796af221a5c01d719"> 5835</a></span><span class="preprocessor">#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) </span></div>
|
||
<div class="line"><a id="l05836" name="l05836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07da26e3445ad620bf9f79853f521985"> 5836</a></span><span class="preprocessor">#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk </span></div>
|
||
<div class="line"><a id="l05837" name="l05837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad05dbef1970d3d226f390de22b5f9e36"> 5837</a></span><span class="preprocessor">#define DCMI_ESUR_LSU_Pos (8U) </span></div>
|
||
<div class="line"><a id="l05838" name="l05838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28f623ee4d63d33aa7ffba98e4eb56d2"> 5838</a></span><span class="preprocessor">#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) </span></div>
|
||
<div class="line"><a id="l05839" name="l05839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef06107788d6ef1164cca2eec17ccd82"> 5839</a></span><span class="preprocessor">#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk </span></div>
|
||
<div class="line"><a id="l05840" name="l05840"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67c976e3d9e4b572622087768cd82438"> 5840</a></span><span class="preprocessor">#define DCMI_ESUR_LEU_Pos (16U) </span></div>
|
||
<div class="line"><a id="l05841" name="l05841"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa57fa1027141af3c9cbca28d364bfff6"> 5841</a></span><span class="preprocessor">#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) </span></div>
|
||
<div class="line"><a id="l05842" name="l05842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65e5d6c1fa10262d9deb97e557fd294c"> 5842</a></span><span class="preprocessor">#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk </span></div>
|
||
<div class="line"><a id="l05843" name="l05843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc1a3b6739ae97c70421d9e43fc190c7"> 5843</a></span><span class="preprocessor">#define DCMI_ESUR_FEU_Pos (24U) </span></div>
|
||
<div class="line"><a id="l05844" name="l05844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9324fdd6bc3877df9bc3bdc2adecb6c"> 5844</a></span><span class="preprocessor">#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) </span></div>
|
||
<div class="line"><a id="l05845" name="l05845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71824df64b1b6626e66e5a83d4663a6e"> 5845</a></span><span class="preprocessor">#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk </span></div>
|
||
<div class="line"><a id="l05846" name="l05846"></a><span class="lineno"> 5846</span> </div>
|
||
<div class="line"><a id="l05847" name="l05847"></a><span class="lineno"> 5847</span><span class="comment">/******************** Bits definition for DCMI_CWSTRT register ******************/</span></div>
|
||
<div class="line"><a id="l05848" name="l05848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9a493eb26260002c069a0a548cf3fd2"> 5848</a></span><span class="preprocessor">#define DCMI_CWSTRT_HOFFCNT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05849" name="l05849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0fae460ad5a360aada91b734fa3ba57"> 5849</a></span><span class="preprocessor">#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) </span></div>
|
||
<div class="line"><a id="l05850" name="l05850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae099a5f83a683df21addd2efd2d9400a"> 5850</a></span><span class="preprocessor">#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk </span></div>
|
||
<div class="line"><a id="l05851" name="l05851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4f2d38ccf4538602e4b0fd463d978ae"> 5851</a></span><span class="preprocessor">#define DCMI_CWSTRT_VST_Pos (16U) </span></div>
|
||
<div class="line"><a id="l05852" name="l05852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1652ad176cc9fbdcec26e5ee24e1f90"> 5852</a></span><span class="preprocessor">#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) </span></div>
|
||
<div class="line"><a id="l05853" name="l05853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1f7a07e86f5331bd024197bf986f7fb"> 5853</a></span><span class="preprocessor">#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk </span></div>
|
||
<div class="line"><a id="l05854" name="l05854"></a><span class="lineno"> 5854</span> </div>
|
||
<div class="line"><a id="l05855" name="l05855"></a><span class="lineno"> 5855</span><span class="comment">/******************** Bits definition for DCMI_CWSIZE register ******************/</span></div>
|
||
<div class="line"><a id="l05856" name="l05856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga909bd8775d484d961f2e95e832ccda6d"> 5856</a></span><span class="preprocessor">#define DCMI_CWSIZE_CAPCNT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05857" name="l05857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad530930a69892f9cd7ad4ff52a92b133"> 5857</a></span><span class="preprocessor">#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) </span></div>
|
||
<div class="line"><a id="l05858" name="l05858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c31745cc8efc121ae47c30cc42b384f"> 5858</a></span><span class="preprocessor">#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk </span></div>
|
||
<div class="line"><a id="l05859" name="l05859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab47763252d37347f698b9f1d6b459448"> 5859</a></span><span class="preprocessor">#define DCMI_CWSIZE_VLINE_Pos (16U) </span></div>
|
||
<div class="line"><a id="l05860" name="l05860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga628637bf9713da908eca5a53e0f42d4b"> 5860</a></span><span class="preprocessor">#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) </span></div>
|
||
<div class="line"><a id="l05861" name="l05861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11c87e423cc974fce1a8a50213e47af8"> 5861</a></span><span class="preprocessor">#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk </span></div>
|
||
<div class="line"><a id="l05862" name="l05862"></a><span class="lineno"> 5862</span> </div>
|
||
<div class="line"><a id="l05863" name="l05863"></a><span class="lineno"> 5863</span><span class="comment">/******************** Bits definition for DCMI_DR register *********************/</span></div>
|
||
<div class="line"><a id="l05864" name="l05864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac71db8315705b6ed05cf43460426e159"> 5864</a></span><span class="preprocessor">#define DCMI_DR_BYTE0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05865" name="l05865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07c270f5e6d112768db06c11b2cc6e56"> 5865</a></span><span class="preprocessor">#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) </span></div>
|
||
<div class="line"><a id="l05866" name="l05866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0910a5a593672f96d201adc561a04b9"> 5866</a></span><span class="preprocessor">#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk </span></div>
|
||
<div class="line"><a id="l05867" name="l05867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5763f364e81aa40dd960d40ba88fa6a"> 5867</a></span><span class="preprocessor">#define DCMI_DR_BYTE1_Pos (8U) </span></div>
|
||
<div class="line"><a id="l05868" name="l05868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab17364d3900caed76aecc643774c54bc"> 5868</a></span><span class="preprocessor">#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) </span></div>
|
||
<div class="line"><a id="l05869" name="l05869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab01aefc5cd095660ac49a2b7b9180c82"> 5869</a></span><span class="preprocessor">#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk </span></div>
|
||
<div class="line"><a id="l05870" name="l05870"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbc045a35af6103ab0f7fc88ff6ba02d"> 5870</a></span><span class="preprocessor">#define DCMI_DR_BYTE2_Pos (16U) </span></div>
|
||
<div class="line"><a id="l05871" name="l05871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ee34bf9dabcdca52c0cbf44f25d9c5a"> 5871</a></span><span class="preprocessor">#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) </span></div>
|
||
<div class="line"><a id="l05872" name="l05872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1bfbeeca97efa76992487f3c22d6aff"> 5872</a></span><span class="preprocessor">#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk </span></div>
|
||
<div class="line"><a id="l05873" name="l05873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bc8e1dc5f89d3476b28267f4b84a8ce"> 5873</a></span><span class="preprocessor">#define DCMI_DR_BYTE3_Pos (24U) </span></div>
|
||
<div class="line"><a id="l05874" name="l05874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa294b6ac2643ebf5c1492257ad79f45d"> 5874</a></span><span class="preprocessor">#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) </span></div>
|
||
<div class="line"><a id="l05875" name="l05875"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa63e80a5e9f30b03e3b01b0c597a5cf"> 5875</a></span><span class="preprocessor">#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk </span></div>
|
||
<div class="line"><a id="l05876" name="l05876"></a><span class="lineno"> 5876</span> </div>
|
||
<div class="line"><a id="l05877" name="l05877"></a><span class="lineno"> 5877</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l05878" name="l05878"></a><span class="lineno"> 5878</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l05879" name="l05879"></a><span class="lineno"> 5879</span><span class="comment">/* DMA Controller */</span></div>
|
||
<div class="line"><a id="l05880" name="l05880"></a><span class="lineno"> 5880</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l05881" name="l05881"></a><span class="lineno"> 5881</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l05882" name="l05882"></a><span class="lineno"> 5882</span><span class="comment">/******************** Bits definition for DMA_SxCR register *****************/</span></div>
|
||
<div class="line"><a id="l05883" name="l05883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79fe8c72b18021aec9a18b68b9df324c"> 5883</a></span><span class="preprocessor">#define DMA_SxCR_CHSEL_Pos (25U) </span></div>
|
||
<div class="line"><a id="l05884" name="l05884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27c7e607fbf7db7b5515bacbb9070346"> 5884</a></span><span class="preprocessor">#define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) </span></div>
|
||
<div class="line"><a id="l05885" name="l05885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf353426d72702c7801416ba36d53dc6"> 5885</a></span><span class="preprocessor">#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk </span></div>
|
||
<div class="line"><a id="l05886" name="l05886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17d34dad5c7bdb97fdcadaebfed80d90"> 5886</a></span><span class="preprocessor">#define DMA_SxCR_CHSEL_0 0x02000000U </span></div>
|
||
<div class="line"><a id="l05887" name="l05887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa59d7ef4d7e0895f18ca4ef1210edae"> 5887</a></span><span class="preprocessor">#define DMA_SxCR_CHSEL_1 0x04000000U </span></div>
|
||
<div class="line"><a id="l05888" name="l05888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae001e60d3fd84c18bb5e2f96b695af38"> 5888</a></span><span class="preprocessor">#define DMA_SxCR_CHSEL_2 0x08000000U </span></div>
|
||
<div class="line"><a id="l05889" name="l05889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9bf6407dc86ae23902425ed20d90421"> 5889</a></span><span class="preprocessor">#define DMA_SxCR_MBURST_Pos (23U) </span></div>
|
||
<div class="line"><a id="l05890" name="l05890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa451942408f8a368a57eb9c45e43e7c8"> 5890</a></span><span class="preprocessor">#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) </span></div>
|
||
<div class="line"><a id="l05891" name="l05891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c1174bff38faf5d87b71521bce8f84f"> 5891</a></span><span class="preprocessor">#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk </span></div>
|
||
<div class="line"><a id="l05892" name="l05892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e3931a8f14ffe008b8717e1b3232fca"> 5892</a></span><span class="preprocessor">#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) </span></div>
|
||
<div class="line"><a id="l05893" name="l05893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf28eac7212392083bbf1b3d475022b74"> 5893</a></span><span class="preprocessor">#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) </span></div>
|
||
<div class="line"><a id="l05894" name="l05894"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga596bbd1719434d9b94dc57641788484e"> 5894</a></span><span class="preprocessor">#define DMA_SxCR_PBURST_Pos (21U) </span></div>
|
||
<div class="line"><a id="l05895" name="l05895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0522a557e1c258b7973e76da59cb7bbb"> 5895</a></span><span class="preprocessor">#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) </span></div>
|
||
<div class="line"><a id="l05896" name="l05896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga502380abb155eb3b37a2ca9359e2da2e"> 5896</a></span><span class="preprocessor">#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk </span></div>
|
||
<div class="line"><a id="l05897" name="l05897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf0eee1ad1788868a194f95107057a16"> 5897</a></span><span class="preprocessor">#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) </span></div>
|
||
<div class="line"><a id="l05898" name="l05898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga061207b2c654a0dd62e40187c9557eda"> 5898</a></span><span class="preprocessor">#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) </span></div>
|
||
<div class="line"><a id="l05899" name="l05899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ae631c89765d8c92dde7eece6b28c58"> 5899</a></span><span class="preprocessor">#define DMA_SxCR_CT_Pos (19U) </span></div>
|
||
<div class="line"><a id="l05900" name="l05900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3ef149321f19c6fdda5eea2d622b78e"> 5900</a></span><span class="preprocessor">#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) </span></div>
|
||
<div class="line"><a id="l05901" name="l05901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd36c677ee53f56dc408cd549e64cf7d"> 5901</a></span><span class="preprocessor">#define DMA_SxCR_CT DMA_SxCR_CT_Msk </span></div>
|
||
<div class="line"><a id="l05902" name="l05902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d74a7510babe49319a47e4fccaceba7"> 5902</a></span><span class="preprocessor">#define DMA_SxCR_DBM_Pos (18U) </span></div>
|
||
<div class="line"><a id="l05903" name="l05903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga460b7d274a9e54d2ddabddc9832425b4"> 5903</a></span><span class="preprocessor">#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) </span></div>
|
||
<div class="line"><a id="l05904" name="l05904"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53a1cde736b2afc5a394a67849f0c497"> 5904</a></span><span class="preprocessor">#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk </span></div>
|
||
<div class="line"><a id="l05905" name="l05905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0df2c0e1e3fa3614d74ee91cefa8173"> 5905</a></span><span class="preprocessor">#define DMA_SxCR_PL_Pos (16U) </span></div>
|
||
<div class="line"><a id="l05906" name="l05906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3dc66d05a0b6c646926e155f584c2164"> 5906</a></span><span class="preprocessor">#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) </span></div>
|
||
<div class="line"><a id="l05907" name="l05907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14c115d71a4e3b3c4da360108288154c"> 5907</a></span><span class="preprocessor">#define DMA_SxCR_PL DMA_SxCR_PL_Msk </span></div>
|
||
<div class="line"><a id="l05908" name="l05908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41b1b2f7bd6f0af932ff0fb7df9336b6"> 5908</a></span><span class="preprocessor">#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) </span></div>
|
||
<div class="line"><a id="l05909" name="l05909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81817adc8c0ee54dea0f67a1a9e8eb77"> 5909</a></span><span class="preprocessor">#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) </span></div>
|
||
<div class="line"><a id="l05910" name="l05910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e2c688c88288e3f899e47c4d11ca4fa"> 5910</a></span><span class="preprocessor">#define DMA_SxCR_PINCOS_Pos (15U) </span></div>
|
||
<div class="line"><a id="l05911" name="l05911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78df7ff746fecc4afaa5e980f11de4d6"> 5911</a></span><span class="preprocessor">#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) </span></div>
|
||
<div class="line"><a id="l05912" name="l05912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb929908d2e7fdef2136c20c93377c70"> 5912</a></span><span class="preprocessor">#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk </span></div>
|
||
<div class="line"><a id="l05913" name="l05913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55693651f2994a1c09f7b47455638a6a"> 5913</a></span><span class="preprocessor">#define DMA_SxCR_MSIZE_Pos (13U) </span></div>
|
||
<div class="line"><a id="l05914" name="l05914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga769dd95d6aa84f0bc0080891094cd5bd"> 5914</a></span><span class="preprocessor">#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l05915" name="l05915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9a98cb706a722d726d8ec6e9fe4a773"> 5915</a></span><span class="preprocessor">#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk </span></div>
|
||
<div class="line"><a id="l05916" name="l05916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39adb60b3394b61366691b45b8c2b80f"> 5916</a></span><span class="preprocessor">#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l05917" name="l05917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5c2ef08ab52de52b4e1fd785f60e263"> 5917</a></span><span class="preprocessor">#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l05918" name="l05918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56479851c087f5fe7ea9656862ad35e1"> 5918</a></span><span class="preprocessor">#define DMA_SxCR_PSIZE_Pos (11U) </span></div>
|
||
<div class="line"><a id="l05919" name="l05919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ddb21769dcff3c41c4bb61e66d8459a"> 5919</a></span><span class="preprocessor">#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l05920" name="l05920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea0808f979c27b7b68d79ad511e95ea0"> 5920</a></span><span class="preprocessor">#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk </span></div>
|
||
<div class="line"><a id="l05921" name="l05921"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab05cf3e3f7c9edae5c70d59b3b75b14f"> 5921</a></span><span class="preprocessor">#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l05922" name="l05922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f376d0900380a3045cbeadd6a037302"> 5922</a></span><span class="preprocessor">#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l05923" name="l05923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11d90925c956a5196f58cf3fc89aa56f"> 5923</a></span><span class="preprocessor">#define DMA_SxCR_MINC_Pos (10U) </span></div>
|
||
<div class="line"><a id="l05924" name="l05924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b9b94c796c25b6dac673c711f74eb48"> 5924</a></span><span class="preprocessor">#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) </span></div>
|
||
<div class="line"><a id="l05925" name="l05925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga771a295832a584a3777ede523a691719"> 5925</a></span><span class="preprocessor">#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk </span></div>
|
||
<div class="line"><a id="l05926" name="l05926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f2a2143daf87c92d37da6503762f7c5"> 5926</a></span><span class="preprocessor">#define DMA_SxCR_PINC_Pos (9U) </span></div>
|
||
<div class="line"><a id="l05927" name="l05927"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0829e862db027069781244f9820113ab"> 5927</a></span><span class="preprocessor">#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) </span></div>
|
||
<div class="line"><a id="l05928" name="l05928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29c5d5c559dd14646fdc170e74f1f03b"> 5928</a></span><span class="preprocessor">#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk </span></div>
|
||
<div class="line"><a id="l05929" name="l05929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34774d3e38a7f910c9eb723208457a83"> 5929</a></span><span class="preprocessor">#define DMA_SxCR_CIRC_Pos (8U) </span></div>
|
||
<div class="line"><a id="l05930" name="l05930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga873f1581fb2b88c20d6621143a5751ac"> 5930</a></span><span class="preprocessor">#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) </span></div>
|
||
<div class="line"><a id="l05931" name="l05931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc248dbc519cc580621cdadcdd8741fb"> 5931</a></span><span class="preprocessor">#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk </span></div>
|
||
<div class="line"><a id="l05932" name="l05932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8302200753a3788a5b45462513a84b6b"> 5932</a></span><span class="preprocessor">#define DMA_SxCR_DIR_Pos (6U) </span></div>
|
||
<div class="line"><a id="l05933" name="l05933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6c4f77554490fc06ecbd63e0e81a696"> 5933</a></span><span class="preprocessor">#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) </span></div>
|
||
<div class="line"><a id="l05934" name="l05934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16bc78076551c42cbdc084e9d0006bd4"> 5934</a></span><span class="preprocessor">#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk </span></div>
|
||
<div class="line"><a id="l05935" name="l05935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadca9547536f3d2f76577275964b4875e"> 5935</a></span><span class="preprocessor">#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) </span></div>
|
||
<div class="line"><a id="l05936" name="l05936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac52c8d6ecad03bfe531867fa7457f2ae"> 5936</a></span><span class="preprocessor">#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) </span></div>
|
||
<div class="line"><a id="l05937" name="l05937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9b6e1601b8fe4d4315dabeb21d87871"> 5937</a></span><span class="preprocessor">#define DMA_SxCR_PFCTRL_Pos (5U) </span></div>
|
||
<div class="line"><a id="l05938" name="l05938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab67e3396d4689bc81191afda92e1864c"> 5938</a></span><span class="preprocessor">#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) </span></div>
|
||
<div class="line"><a id="l05939" name="l05939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11f412d256043bec3e01ceef7f2099f2"> 5939</a></span><span class="preprocessor">#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk </span></div>
|
||
<div class="line"><a id="l05940" name="l05940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04d5934cc3988e035dcb1bf40f6e755a"> 5940</a></span><span class="preprocessor">#define DMA_SxCR_TCIE_Pos (4U) </span></div>
|
||
<div class="line"><a id="l05941" name="l05941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86e6592b451e33103e1d6d119046a5e3"> 5941</a></span><span class="preprocessor">#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) </span></div>
|
||
<div class="line"><a id="l05942" name="l05942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ae47cc2cd2e985d29cb6b0bb65da1d7"> 5942</a></span><span class="preprocessor">#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk </span></div>
|
||
<div class="line"><a id="l05943" name="l05943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ed0223ba349ffb6e55d16415be0a92e"> 5943</a></span><span class="preprocessor">#define DMA_SxCR_HTIE_Pos (3U) </span></div>
|
||
<div class="line"><a id="l05944" name="l05944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b2b5b47a0da93f112effd85edf7e27b"> 5944</a></span><span class="preprocessor">#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) </span></div>
|
||
<div class="line"><a id="l05945" name="l05945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13a7fe097608bc5031d42ba69effed20"> 5945</a></span><span class="preprocessor">#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk </span></div>
|
||
<div class="line"><a id="l05946" name="l05946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3416da006a6a698c8f95f91e0b9b4b5f"> 5946</a></span><span class="preprocessor">#define DMA_SxCR_TEIE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l05947" name="l05947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e7331240fc8545d3dba92568b243039"> 5947</a></span><span class="preprocessor">#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) </span></div>
|
||
<div class="line"><a id="l05948" name="l05948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeee99c36ba3ea56cdb4f73a0b01fb602"> 5948</a></span><span class="preprocessor">#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk </span></div>
|
||
<div class="line"><a id="l05949" name="l05949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90d77b99e19ffb0ce8533726db577011"> 5949</a></span><span class="preprocessor">#define DMA_SxCR_DMEIE_Pos (1U) </span></div>
|
||
<div class="line"><a id="l05950" name="l05950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga640f196b45fc4e81ac468cbc3503148b"> 5950</a></span><span class="preprocessor">#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) </span></div>
|
||
<div class="line"><a id="l05951" name="l05951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacaecc56f94a9af756d077cf7df1b6c41"> 5951</a></span><span class="preprocessor">#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk </span></div>
|
||
<div class="line"><a id="l05952" name="l05952"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ae3e4666ee54b89bca73e5ce40032a8"> 5952</a></span><span class="preprocessor">#define DMA_SxCR_EN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05953" name="l05953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga038999913cf4b5608f4b06bde0f5b6f1"> 5953</a></span><span class="preprocessor">#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) </span></div>
|
||
<div class="line"><a id="l05954" name="l05954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabf69fe92e9a44167535365b0fe4ea9e"> 5954</a></span><span class="preprocessor">#define DMA_SxCR_EN DMA_SxCR_EN_Msk </span></div>
|
||
<div class="line"><a id="l05955" name="l05955"></a><span class="lineno"> 5955</span> </div>
|
||
<div class="line"><a id="l05956" name="l05956"></a><span class="lineno"> 5956</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l05957" name="l05957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4c9d3fe3ecd436e1e33bf246a8a1d81"> 5957</a></span><span class="preprocessor">#define DMA_SxCR_ACK_Pos (20U) </span></div>
|
||
<div class="line"><a id="l05958" name="l05958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae03b6c12b1fc9d635ce6abac4b15006e"> 5958</a></span><span class="preprocessor">#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) </span></div>
|
||
<div class="line"><a id="l05959" name="l05959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f597f58faf86d2b78ad931079f57305"> 5959</a></span><span class="preprocessor">#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk </span></div>
|
||
<div class="line"><a id="l05960" name="l05960"></a><span class="lineno"> 5960</span> </div>
|
||
<div class="line"><a id="l05961" name="l05961"></a><span class="lineno"> 5961</span><span class="comment">/******************** Bits definition for DMA_SxCNDTR register **************/</span></div>
|
||
<div class="line"><a id="l05962" name="l05962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1"> 5962</a></span><span class="preprocessor">#define DMA_SxNDT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05963" name="l05963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9525ced3fadc78d4d5bb8234d226a52"> 5963</a></span><span class="preprocessor">#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05964" name="l05964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62e0e1a1121885de705e618855ba83b0"> 5964</a></span><span class="preprocessor">#define DMA_SxNDT DMA_SxNDT_Msk </span></div>
|
||
<div class="line"><a id="l05965" name="l05965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ae52f0e22e621d60861143ca6027852"> 5965</a></span><span class="preprocessor">#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05966" name="l05966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c4223f0a871ccfee403988befa42d94"> 5966</a></span><span class="preprocessor">#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05967" name="l05967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4766cc41262f7b530351ecc5939fc222"> 5967</a></span><span class="preprocessor">#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05968" name="l05968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa43d96546fce4a436e4478a99ac0394"> 5968</a></span><span class="preprocessor">#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05969" name="l05969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81412c27b9d192be6c8c251b3a750e3c"> 5969</a></span><span class="preprocessor">#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05970" name="l05970"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeff6beaa117fca4b6d1bbd87de34f674"> 5970</a></span><span class="preprocessor">#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05971" name="l05971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7533a77655a960f82d08edfd2f4bf7ee"> 5971</a></span><span class="preprocessor">#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05972" name="l05972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b2791b19fcf8586ffd28204bab2f2b4"> 5972</a></span><span class="preprocessor">#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05973" name="l05973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6d77fc0aa9e027fc906f70f8e6a4aca"> 5973</a></span><span class="preprocessor">#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05974" name="l05974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b4f096ed9b7f778e5b6beec36ca9698"> 5974</a></span><span class="preprocessor">#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05975" name="l05975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64a0c2548db60b344bbbda72b53089ca"> 5975</a></span><span class="preprocessor">#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05976" name="l05976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e37fe0da3a0c2e6ac94f999c8455187"> 5976</a></span><span class="preprocessor">#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05977" name="l05977"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa27c8ece8e904ef16ea45be9f7733103"> 5977</a></span><span class="preprocessor">#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05978" name="l05978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f320a375482fe097d3f1579925013bb"> 5978</a></span><span class="preprocessor">#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05979" name="l05979"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8882d292259d683b075bf6c4e009b3ae"> 5979</a></span><span class="preprocessor">#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05980" name="l05980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga386a1a2048a470bed80654cd548dea65"> 5980</a></span><span class="preprocessor">#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) </span></div>
|
||
<div class="line"><a id="l05982" name="l05982"></a><span class="lineno"> 5982</span><span class="comment">/******************** Bits definition for DMA_SxFCR register ****************/</span> </div>
|
||
<div class="line"><a id="l05983" name="l05983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10b0f3097f54eff7dd2d43bb1c31f736"> 5983</a></span><span class="preprocessor">#define DMA_SxFCR_FEIE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l05984" name="l05984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadff36ebec91293d8106a40bbf580be00"> 5984</a></span><span class="preprocessor">#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) </span></div>
|
||
<div class="line"><a id="l05985" name="l05985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba9ca2264bc381abe0f4183729ab1fb1"> 5985</a></span><span class="preprocessor">#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk </span></div>
|
||
<div class="line"><a id="l05986" name="l05986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6719968db5f4e50b30015434339db896"> 5986</a></span><span class="preprocessor">#define DMA_SxFCR_FS_Pos (3U) </span></div>
|
||
<div class="line"><a id="l05987" name="l05987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46ecd57c9b56be53a38263c02d25c50f"> 5987</a></span><span class="preprocessor">#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) </span></div>
|
||
<div class="line"><a id="l05988" name="l05988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56094479dc9b173b00ccfb199d8a2853"> 5988</a></span><span class="preprocessor">#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk </span></div>
|
||
<div class="line"><a id="l05989" name="l05989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccf0cb1a99fb8265535b15fc6a428060"> 5989</a></span><span class="preprocessor">#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) </span></div>
|
||
<div class="line"><a id="l05990" name="l05990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b5dd8e40fe393762866522caa0ab842"> 5990</a></span><span class="preprocessor">#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) </span></div>
|
||
<div class="line"><a id="l05991" name="l05991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51558a53d17a6deeed3937c15787361c"> 5991</a></span><span class="preprocessor">#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) </span></div>
|
||
<div class="line"><a id="l05992" name="l05992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga562b4b1bcd309931c42bfe7793044e91"> 5992</a></span><span class="preprocessor">#define DMA_SxFCR_DMDIS_Pos (2U) </span></div>
|
||
<div class="line"><a id="l05993" name="l05993"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadedd400be2f182737e484d52be6b80c1"> 5993</a></span><span class="preprocessor">#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) </span></div>
|
||
<div class="line"><a id="l05994" name="l05994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89406bb954742665691c0ac2f8d95ec9"> 5994</a></span><span class="preprocessor">#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk </span></div>
|
||
<div class="line"><a id="l05995" name="l05995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6876e8621d30962774d2b72dbc720ec"> 5995</a></span><span class="preprocessor">#define DMA_SxFCR_FTH_Pos (0U) </span></div>
|
||
<div class="line"><a id="l05996" name="l05996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e436952c24ada5a0c553043092285e7"> 5996</a></span><span class="preprocessor">#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) </span></div>
|
||
<div class="line"><a id="l05997" name="l05997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44c16978164026a81f5b07280e800e7f"> 5997</a></span><span class="preprocessor">#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk </span></div>
|
||
<div class="line"><a id="l05998" name="l05998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63716e11d34bca95927671055aa63fe8"> 5998</a></span><span class="preprocessor">#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) </span></div>
|
||
<div class="line"><a id="l05999" name="l05999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3d780fc1222a183071c73e62a0524a1"> 5999</a></span><span class="preprocessor">#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) </span></div>
|
||
<div class="line"><a id="l06001" name="l06001"></a><span class="lineno"> 6001</span><span class="comment">/******************** Bits definition for DMA_LISR register *****************/</span> </div>
|
||
<div class="line"><a id="l06002" name="l06002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1917ec61d4f0b063c4d63c94d00f104c"> 6002</a></span><span class="preprocessor">#define DMA_LISR_TCIF3_Pos (27U) </span></div>
|
||
<div class="line"><a id="l06003" name="l06003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fcbb22f764dbcd84f9f7679ba140fd8"> 6003</a></span><span class="preprocessor">#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) </span></div>
|
||
<div class="line"><a id="l06004" name="l06004"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44e5bf8adbb2646d325cba8d5dd670d8"> 6004</a></span><span class="preprocessor">#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk </span></div>
|
||
<div class="line"><a id="l06005" name="l06005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc365b9d116f7bf0fb0bdb4a36b025f0"> 6005</a></span><span class="preprocessor">#define DMA_LISR_HTIF3_Pos (26U) </span></div>
|
||
<div class="line"><a id="l06006" name="l06006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga202e6ae73e145494851e4c40f5c2eb2e"> 6006</a></span><span class="preprocessor">#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) </span></div>
|
||
<div class="line"><a id="l06007" name="l06007"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa10c891ee2ec333b7f87eea5886d574f"> 6007</a></span><span class="preprocessor">#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk </span></div>
|
||
<div class="line"><a id="l06008" name="l06008"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3eb3514f45c12c124807ea04b5e5206d"> 6008</a></span><span class="preprocessor">#define DMA_LISR_TEIF3_Pos (25U) </span></div>
|
||
<div class="line"><a id="l06009" name="l06009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga770b6645dff14ef5d2950aff2995ec72"> 6009</a></span><span class="preprocessor">#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) </span></div>
|
||
<div class="line"><a id="l06010" name="l06010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5dfaba3a5db7cdcbddf9ee5974b44c2f"> 6010</a></span><span class="preprocessor">#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk </span></div>
|
||
<div class="line"><a id="l06011" name="l06011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f039fe3193408bc81d812149996ea9f"> 6011</a></span><span class="preprocessor">#define DMA_LISR_DMEIF3_Pos (24U) </span></div>
|
||
<div class="line"><a id="l06012" name="l06012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4331e1ec530a0dc0cbee400d5950b3a"> 6012</a></span><span class="preprocessor">#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) </span></div>
|
||
<div class="line"><a id="l06013" name="l06013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01fd1397b41221f5bdf6f107cb92e196"> 6013</a></span><span class="preprocessor">#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk </span></div>
|
||
<div class="line"><a id="l06014" name="l06014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace4ae0196dace02aceafe1fe77b6e6d7"> 6014</a></span><span class="preprocessor">#define DMA_LISR_FEIF3_Pos (22U) </span></div>
|
||
<div class="line"><a id="l06015" name="l06015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46bd312d438cb54d4b68b189cf120fd1"> 6015</a></span><span class="preprocessor">#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) </span></div>
|
||
<div class="line"><a id="l06016" name="l06016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5367443a1378eef82aed62ca22763952"> 6016</a></span><span class="preprocessor">#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk </span></div>
|
||
<div class="line"><a id="l06017" name="l06017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d0716b2ad4127572e8b69fb92652f19"> 6017</a></span><span class="preprocessor">#define DMA_LISR_TCIF2_Pos (21U) </span></div>
|
||
<div class="line"><a id="l06018" name="l06018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae271580139c8f7d241532d0c833afe06"> 6018</a></span><span class="preprocessor">#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) </span></div>
|
||
<div class="line"><a id="l06019" name="l06019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf21350cce8c4cb5d7c6fcf5edc930cf8"> 6019</a></span><span class="preprocessor">#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk </span></div>
|
||
<div class="line"><a id="l06020" name="l06020"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2700c5fdeaa7186a38c920f5ec85ea49"> 6020</a></span><span class="preprocessor">#define DMA_LISR_HTIF2_Pos (20U) </span></div>
|
||
<div class="line"><a id="l06021" name="l06021"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83c87fe2679a6130003dd72b363e9c53"> 6021</a></span><span class="preprocessor">#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) </span></div>
|
||
<div class="line"><a id="l06022" name="l06022"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ca25185d14a1f0c208ec8ceadc787a6"> 6022</a></span><span class="preprocessor">#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk </span></div>
|
||
<div class="line"><a id="l06023" name="l06023"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac01bf79870cef24f0875200fba8ab778"> 6023</a></span><span class="preprocessor">#define DMA_LISR_TEIF2_Pos (19U) </span></div>
|
||
<div class="line"><a id="l06024" name="l06024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64f9f609e2612044dd911f853c401ce9"> 6024</a></span><span class="preprocessor">#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) </span></div>
|
||
<div class="line"><a id="l06025" name="l06025"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74d540802cadde42bdd6debae5d8ab89"> 6025</a></span><span class="preprocessor">#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk </span></div>
|
||
<div class="line"><a id="l06026" name="l06026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad852ffba4cb1b34e1cc77ba3f5075c03"> 6026</a></span><span class="preprocessor">#define DMA_LISR_DMEIF2_Pos (18U) </span></div>
|
||
<div class="line"><a id="l06027" name="l06027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f7a3d352057475b51e9627d497bf8d5"> 6027</a></span><span class="preprocessor">#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) </span></div>
|
||
<div class="line"><a id="l06028" name="l06028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc7edcd7404f0dcf19a724dfad22026a"> 6028</a></span><span class="preprocessor">#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk </span></div>
|
||
<div class="line"><a id="l06029" name="l06029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53433f2c39d945b72231cff33c0b6ccb"> 6029</a></span><span class="preprocessor">#define DMA_LISR_FEIF2_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06030" name="l06030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d4c97aa0bf50b5ff36e271bde6b2285"> 6030</a></span><span class="preprocessor">#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) </span></div>
|
||
<div class="line"><a id="l06031" name="l06031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99c42b194213872753460ef9b7745213"> 6031</a></span><span class="preprocessor">#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk </span></div>
|
||
<div class="line"><a id="l06032" name="l06032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03abe37d6a707015bd502285aa4ab71c"> 6032</a></span><span class="preprocessor">#define DMA_LISR_TCIF1_Pos (11U) </span></div>
|
||
<div class="line"><a id="l06033" name="l06033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga338a63d76a175d0ef90bd5469232cc69"> 6033</a></span><span class="preprocessor">#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) </span></div>
|
||
<div class="line"><a id="l06034" name="l06034"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae02aec39ded937b3ce816d3df4520d9b"> 6034</a></span><span class="preprocessor">#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk </span></div>
|
||
<div class="line"><a id="l06035" name="l06035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00c7637307de891e63bc8ca8cb7750f4"> 6035</a></span><span class="preprocessor">#define DMA_LISR_HTIF1_Pos (10U) </span></div>
|
||
<div class="line"><a id="l06036" name="l06036"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c9343cd010bd919a13bf32f9a8d998f"> 6036</a></span><span class="preprocessor">#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) </span></div>
|
||
<div class="line"><a id="l06037" name="l06037"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04304a9f8891e325247c0aaa4c9fac72"> 6037</a></span><span class="preprocessor">#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk </span></div>
|
||
<div class="line"><a id="l06038" name="l06038"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81e7b142424b2a4901007ea232482931"> 6038</a></span><span class="preprocessor">#define DMA_LISR_TEIF1_Pos (9U) </span></div>
|
||
<div class="line"><a id="l06039" name="l06039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga014420a4087c5f7fa521536fed95a57b"> 6039</a></span><span class="preprocessor">#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) </span></div>
|
||
<div class="line"><a id="l06040" name="l06040"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cd826db0b9ea5544d1a93beb90f8972"> 6040</a></span><span class="preprocessor">#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk </span></div>
|
||
<div class="line"><a id="l06041" name="l06041"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga863200d27b1112aa53312c17b3130fb9"> 6041</a></span><span class="preprocessor">#define DMA_LISR_DMEIF1_Pos (8U) </span></div>
|
||
<div class="line"><a id="l06042" name="l06042"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71ddcdc61bbf235161b59b2fa356fa3b"> 6042</a></span><span class="preprocessor">#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) </span></div>
|
||
<div class="line"><a id="l06043" name="l06043"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4903814bfc12dd6193416374fbddf8c"> 6043</a></span><span class="preprocessor">#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk </span></div>
|
||
<div class="line"><a id="l06044" name="l06044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f8b90ddc0ba4459e396755e1fcc156f"> 6044</a></span><span class="preprocessor">#define DMA_LISR_FEIF1_Pos (6U) </span></div>
|
||
<div class="line"><a id="l06045" name="l06045"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa932a51d97ae0952a1cf37b876ac9cbc"> 6045</a></span><span class="preprocessor">#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) </span></div>
|
||
<div class="line"><a id="l06046" name="l06046"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbc4fecde60c09e12f10113a156bb922"> 6046</a></span><span class="preprocessor">#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk </span></div>
|
||
<div class="line"><a id="l06047" name="l06047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ca6a950eb06d3526feab88473965afe"> 6047</a></span><span class="preprocessor">#define DMA_LISR_TCIF0_Pos (5U) </span></div>
|
||
<div class="line"><a id="l06048" name="l06048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0a6dc2ab51b3f572bf7dba9ee25354b"> 6048</a></span><span class="preprocessor">#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) </span></div>
|
||
<div class="line"><a id="l06049" name="l06049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbc3f7e52c0688bed4b71fa37666901d"> 6049</a></span><span class="preprocessor">#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk </span></div>
|
||
<div class="line"><a id="l06050" name="l06050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e84488e6b41b533d99b63e3a08008da"> 6050</a></span><span class="preprocessor">#define DMA_LISR_HTIF0_Pos (4U) </span></div>
|
||
<div class="line"><a id="l06051" name="l06051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c5a05c426a6fc95eee5f6b387139293"> 6051</a></span><span class="preprocessor">#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) </span></div>
|
||
<div class="line"><a id="l06052" name="l06052"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6181727d13abbc46283ff22ce359e3b9"> 6052</a></span><span class="preprocessor">#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk </span></div>
|
||
<div class="line"><a id="l06053" name="l06053"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0ce7d8c40ff5bece107011e99d86e16"> 6053</a></span><span class="preprocessor">#define DMA_LISR_TEIF0_Pos (3U) </span></div>
|
||
<div class="line"><a id="l06054" name="l06054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8213385927a3d6b07c3e035b331fead4"> 6054</a></span><span class="preprocessor">#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) </span></div>
|
||
<div class="line"><a id="l06055" name="l06055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad43cdafa5acfcd683b7a2ee8976dd8ba"> 6055</a></span><span class="preprocessor">#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk </span></div>
|
||
<div class="line"><a id="l06056" name="l06056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga143abdc2acba3fb3ff2e3bc76f8cbf9d"> 6056</a></span><span class="preprocessor">#define DMA_LISR_DMEIF0_Pos (2U) </span></div>
|
||
<div class="line"><a id="l06057" name="l06057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66347e1824698903c1533784c2413f84"> 6057</a></span><span class="preprocessor">#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) </span></div>
|
||
<div class="line"><a id="l06058" name="l06058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72de97ebc9d063dceb38bada91c44878"> 6058</a></span><span class="preprocessor">#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk </span></div>
|
||
<div class="line"><a id="l06059" name="l06059"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0b4469def09a256f7ce049de364650a"> 6059</a></span><span class="preprocessor">#define DMA_LISR_FEIF0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06060" name="l06060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4ecaf3690c72bee4bd08746779615dd"> 6060</a></span><span class="preprocessor">#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) </span></div>
|
||
<div class="line"><a id="l06061" name="l06061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79bcc3f8e773206a66aba95c6f889d6f"> 6061</a></span><span class="preprocessor">#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk </span></div>
|
||
<div class="line"><a id="l06062" name="l06062"></a><span class="lineno"> 6062</span> </div>
|
||
<div class="line"><a id="l06063" name="l06063"></a><span class="lineno"> 6063</span><span class="comment">/******************** Bits definition for DMA_HISR register *****************/</span> </div>
|
||
<div class="line"><a id="l06064" name="l06064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6de32d4d0c47fc9ee420f6f94e02f275"> 6064</a></span><span class="preprocessor">#define DMA_HISR_TCIF7_Pos (27U) </span></div>
|
||
<div class="line"><a id="l06065" name="l06065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cecdf83cc7589761412e00b3d71e657"> 6065</a></span><span class="preprocessor">#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) </span></div>
|
||
<div class="line"><a id="l06066" name="l06066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad20a0a5e103def436d4e329fc0888482"> 6066</a></span><span class="preprocessor">#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk </span></div>
|
||
<div class="line"><a id="l06067" name="l06067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d1b08aa592736655c679f9f57275ecd"> 6067</a></span><span class="preprocessor">#define DMA_HISR_HTIF7_Pos (26U) </span></div>
|
||
<div class="line"><a id="l06068" name="l06068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32a223400ca195866f036f2a3cdf2029"> 6068</a></span><span class="preprocessor">#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) </span></div>
|
||
<div class="line"><a id="l06069" name="l06069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf535d1a3209d2e2e0e616e2d7501525d"> 6069</a></span><span class="preprocessor">#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk </span></div>
|
||
<div class="line"><a id="l06070" name="l06070"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9f7912fe43718644df70d92495a2fe8"> 6070</a></span><span class="preprocessor">#define DMA_HISR_TEIF7_Pos (25U) </span></div>
|
||
<div class="line"><a id="l06071" name="l06071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2754f465bbced1dec2e45bbb8fc9a3c4"> 6071</a></span><span class="preprocessor">#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) </span></div>
|
||
<div class="line"><a id="l06072" name="l06072"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga960f094539b5afc7f9d5e45b7909afe6"> 6072</a></span><span class="preprocessor">#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk </span></div>
|
||
<div class="line"><a id="l06073" name="l06073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e3c0b6526917df4addd70f13f7b9417"> 6073</a></span><span class="preprocessor">#define DMA_HISR_DMEIF7_Pos (24U) </span></div>
|
||
<div class="line"><a id="l06074" name="l06074"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c027560b6bf31fb7926439500c32d6c"> 6074</a></span><span class="preprocessor">#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) </span></div>
|
||
<div class="line"><a id="l06075" name="l06075"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bb23848f8a022a47ab4abd5aa9b7d39"> 6075</a></span><span class="preprocessor">#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk </span></div>
|
||
<div class="line"><a id="l06076" name="l06076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga419c7042fb7439840a04e5fd445731d2"> 6076</a></span><span class="preprocessor">#define DMA_HISR_FEIF7_Pos (22U) </span></div>
|
||
<div class="line"><a id="l06077" name="l06077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4fe1e3a74167419160edbbc759ca3789"> 6077</a></span><span class="preprocessor">#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) </span></div>
|
||
<div class="line"><a id="l06078" name="l06078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadea53385fca360f16c4474db1cf18bc1"> 6078</a></span><span class="preprocessor">#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk </span></div>
|
||
<div class="line"><a id="l06079" name="l06079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d6ca1e8f590dcd64fae7d0aab508111"> 6079</a></span><span class="preprocessor">#define DMA_HISR_TCIF6_Pos (21U) </span></div>
|
||
<div class="line"><a id="l06080" name="l06080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8504bd4d44054ecc0974a59578f6f6ce"> 6080</a></span><span class="preprocessor">#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) </span></div>
|
||
<div class="line"><a id="l06081" name="l06081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad29468aa609150e241d9ae62c477cf45"> 6081</a></span><span class="preprocessor">#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk </span></div>
|
||
<div class="line"><a id="l06082" name="l06082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27460df561ea71167eb046d7993a3763"> 6082</a></span><span class="preprocessor">#define DMA_HISR_HTIF6_Pos (20U) </span></div>
|
||
<div class="line"><a id="l06083" name="l06083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga722b24166ff10769a7f325a6bda26272"> 6083</a></span><span class="preprocessor">#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) </span></div>
|
||
<div class="line"><a id="l06084" name="l06084"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d39c14138e9ff216c203b288137144b"> 6084</a></span><span class="preprocessor">#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk </span></div>
|
||
<div class="line"><a id="l06085" name="l06085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83a1443bc4b15ef4c44d26611688b2d4"> 6085</a></span><span class="preprocessor">#define DMA_HISR_TEIF6_Pos (19U) </span></div>
|
||
<div class="line"><a id="l06086" name="l06086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6d3a65ce374edd183b14be4f40356e2"> 6086</a></span><span class="preprocessor">#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) </span></div>
|
||
<div class="line"><a id="l06087" name="l06087"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a7ec01955fb504a5aa4f9f16a9ac52c"> 6087</a></span><span class="preprocessor">#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk </span></div>
|
||
<div class="line"><a id="l06088" name="l06088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf94b5e23736cdcfd2980ed8339ea346c"> 6088</a></span><span class="preprocessor">#define DMA_HISR_DMEIF6_Pos (18U) </span></div>
|
||
<div class="line"><a id="l06089" name="l06089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga903b58a651a1aaf08e3058d9aefb2e76"> 6089</a></span><span class="preprocessor">#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) </span></div>
|
||
<div class="line"><a id="l06090" name="l06090"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7b58e7ba316d3fc296f4433b3e62c38"> 6090</a></span><span class="preprocessor">#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk </span></div>
|
||
<div class="line"><a id="l06091" name="l06091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5e631133a8a3dbcdad903d73cccb160"> 6091</a></span><span class="preprocessor">#define DMA_HISR_FEIF6_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06092" name="l06092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1736288bfd961d56e8571bdc91bd65b"> 6092</a></span><span class="preprocessor">#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) </span></div>
|
||
<div class="line"><a id="l06093" name="l06093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb297f94bde8d1aea580683d466ca8ca"> 6093</a></span><span class="preprocessor">#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk </span></div>
|
||
<div class="line"><a id="l06094" name="l06094"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9ec95df27557b62d73eb337ef879433"> 6094</a></span><span class="preprocessor">#define DMA_HISR_TCIF5_Pos (11U) </span></div>
|
||
<div class="line"><a id="l06095" name="l06095"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57c25c3b163cfb7c292d5ebce785a2b7"> 6095</a></span><span class="preprocessor">#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) </span></div>
|
||
<div class="line"><a id="l06096" name="l06096"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64f15eaf1dd30450d1d35ee517507321"> 6096</a></span><span class="preprocessor">#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk </span></div>
|
||
<div class="line"><a id="l06097" name="l06097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga922891bcfc085c0d080ce473b8515655"> 6097</a></span><span class="preprocessor">#define DMA_HISR_HTIF5_Pos (10U) </span></div>
|
||
<div class="line"><a id="l06098" name="l06098"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad021f5ec7b128f0493f3f0989ad154ce"> 6098</a></span><span class="preprocessor">#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) </span></div>
|
||
<div class="line"><a id="l06099" name="l06099"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8617bf8160d1027879ffd354e04908d9"> 6099</a></span><span class="preprocessor">#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk </span></div>
|
||
<div class="line"><a id="l06100" name="l06100"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6e505b2a29cc145b957dd8ea1c9c63f"> 6100</a></span><span class="preprocessor">#define DMA_HISR_TEIF5_Pos (9U) </span></div>
|
||
<div class="line"><a id="l06101" name="l06101"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga706c81ee1877cd6f10dd96fd1668d0f8"> 6101</a></span><span class="preprocessor">#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) </span></div>
|
||
<div class="line"><a id="l06102" name="l06102"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf16fb0e5d87f704c89824f961bfb7637"> 6102</a></span><span class="preprocessor">#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk </span></div>
|
||
<div class="line"><a id="l06103" name="l06103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga327eb55ab7770ef13a50436627bc5edf"> 6103</a></span><span class="preprocessor">#define DMA_HISR_DMEIF5_Pos (8U) </span></div>
|
||
<div class="line"><a id="l06104" name="l06104"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae170cce8a55fc679cc5a50b1b947969d"> 6104</a></span><span class="preprocessor">#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) </span></div>
|
||
<div class="line"><a id="l06105" name="l06105"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5ee964eee9c88fa28d32ce3ea6478f2"> 6105</a></span><span class="preprocessor">#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk </span></div>
|
||
<div class="line"><a id="l06106" name="l06106"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24d536ac56c423089622de3d22968843"> 6106</a></span><span class="preprocessor">#define DMA_HISR_FEIF5_Pos (6U) </span></div>
|
||
<div class="line"><a id="l06107" name="l06107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bc4fff852e4fcf19079f79234caf9ae"> 6107</a></span><span class="preprocessor">#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) </span></div>
|
||
<div class="line"><a id="l06108" name="l06108"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d62494b31bb830433ddd683f4872519"> 6108</a></span><span class="preprocessor">#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk </span></div>
|
||
<div class="line"><a id="l06109" name="l06109"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98b35dac75c8a374912b8e99af926c97"> 6109</a></span><span class="preprocessor">#define DMA_HISR_TCIF4_Pos (5U) </span></div>
|
||
<div class="line"><a id="l06110" name="l06110"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0436cbb07d44b1049a8c9ff1e5438c48"> 6110</a></span><span class="preprocessor">#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) </span></div>
|
||
<div class="line"><a id="l06111" name="l06111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcce25c245499f9e62cb757e1871d973"> 6111</a></span><span class="preprocessor">#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk </span></div>
|
||
<div class="line"><a id="l06112" name="l06112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf39dc71e13779a10a6855de4801528a2"> 6112</a></span><span class="preprocessor">#define DMA_HISR_HTIF4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l06113" name="l06113"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6117628ef3e354f4e6ce4ac3656bcd70"> 6113</a></span><span class="preprocessor">#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) </span></div>
|
||
<div class="line"><a id="l06114" name="l06114"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadba8d24329c676d70560eda0b8c1e5b0"> 6114</a></span><span class="preprocessor">#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk </span></div>
|
||
<div class="line"><a id="l06115" name="l06115"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga792ee749e2d12f4aa0cf3daca6b35057"> 6115</a></span><span class="preprocessor">#define DMA_HISR_TEIF4_Pos (3U) </span></div>
|
||
<div class="line"><a id="l06116" name="l06116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac851827ca11788591231f3d29f4ecc1c"> 6116</a></span><span class="preprocessor">#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) </span></div>
|
||
<div class="line"><a id="l06117" name="l06117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9005d4b958193fbd701c879eede467c1"> 6117</a></span><span class="preprocessor">#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk </span></div>
|
||
<div class="line"><a id="l06118" name="l06118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88c83f6ccfd101de6926df1d9112fb4a"> 6118</a></span><span class="preprocessor">#define DMA_HISR_DMEIF4_Pos (2U) </span></div>
|
||
<div class="line"><a id="l06119" name="l06119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3bcb3c175f9e00b37de22d0d5cc041d"> 6119</a></span><span class="preprocessor">#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) </span></div>
|
||
<div class="line"><a id="l06120" name="l06120"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf716f1bc12ea70f49802d84fb77646e8"> 6120</a></span><span class="preprocessor">#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk </span></div>
|
||
<div class="line"><a id="l06121" name="l06121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d7e45dd9031bcf619e6ca233a56a2db"> 6121</a></span><span class="preprocessor">#define DMA_HISR_FEIF4_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06122" name="l06122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2dd4eb12e7b05343a0bddd0dd413ba4c"> 6122</a></span><span class="preprocessor">#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) </span></div>
|
||
<div class="line"><a id="l06123" name="l06123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacab90057201b1da9774308ff3fb6cfa1"> 6123</a></span><span class="preprocessor">#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk </span></div>
|
||
<div class="line"><a id="l06124" name="l06124"></a><span class="lineno"> 6124</span> </div>
|
||
<div class="line"><a id="l06125" name="l06125"></a><span class="lineno"> 6125</span><span class="comment">/******************** Bits definition for DMA_LIFCR register ****************/</span> </div>
|
||
<div class="line"><a id="l06126" name="l06126"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2297c4815dff938a02b0af13da8c42cd"> 6126</a></span><span class="preprocessor">#define DMA_LIFCR_CTCIF3_Pos (27U) </span></div>
|
||
<div class="line"><a id="l06127" name="l06127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ae2b6bed517a5d5f1f39e8fdd5ff18a"> 6127</a></span><span class="preprocessor">#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) </span></div>
|
||
<div class="line"><a id="l06128" name="l06128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5210736d34dc24eb9507975921233137"> 6128</a></span><span class="preprocessor">#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk </span></div>
|
||
<div class="line"><a id="l06129" name="l06129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga879918dd49c563c83d9b0baf39f608c8"> 6129</a></span><span class="preprocessor">#define DMA_LIFCR_CHTIF3_Pos (26U) </span></div>
|
||
<div class="line"><a id="l06130" name="l06130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36f893f7c820962403289cc0f05e58bd"> 6130</a></span><span class="preprocessor">#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) </span></div>
|
||
<div class="line"><a id="l06131" name="l06131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ed3ab4e5d7975f985eb25dc65f99be3"> 6131</a></span><span class="preprocessor">#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk </span></div>
|
||
<div class="line"><a id="l06132" name="l06132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga200a4cd37d937325c0f891cd99b879a5"> 6132</a></span><span class="preprocessor">#define DMA_LIFCR_CTEIF3_Pos (25U) </span></div>
|
||
<div class="line"><a id="l06133" name="l06133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafeab970135917ddac9a49e5c5d246188"> 6133</a></span><span class="preprocessor">#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) </span></div>
|
||
<div class="line"><a id="l06134" name="l06134"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a51c601387d1ae49333d5ace8ae86ee"> 6134</a></span><span class="preprocessor">#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk </span></div>
|
||
<div class="line"><a id="l06135" name="l06135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5766d430a30ebb01d926b73c4838ee7"> 6135</a></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF3_Pos (24U) </span></div>
|
||
<div class="line"><a id="l06136" name="l06136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87881333fb961788c6b31d08a9705cc5"> 6136</a></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) </span></div>
|
||
<div class="line"><a id="l06137" name="l06137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabea10cdf2d3b0773b4e6b7fc9422f361"> 6137</a></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk </span></div>
|
||
<div class="line"><a id="l06138" name="l06138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ce98c26903f04095ebeb872ab8599e2"> 6138</a></span><span class="preprocessor">#define DMA_LIFCR_CFEIF3_Pos (22U) </span></div>
|
||
<div class="line"><a id="l06139" name="l06139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1733762b49e7da8c32a4d27044966872"> 6139</a></span><span class="preprocessor">#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) </span></div>
|
||
<div class="line"><a id="l06140" name="l06140"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9432964145dc55af9186aea425e9963"> 6140</a></span><span class="preprocessor">#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk </span></div>
|
||
<div class="line"><a id="l06141" name="l06141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80de3a47390cdc24fdbb7a1c101d52df"> 6141</a></span><span class="preprocessor">#define DMA_LIFCR_CTCIF2_Pos (21U) </span></div>
|
||
<div class="line"><a id="l06142" name="l06142"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19e090383d9196956fa52d732415263d"> 6142</a></span><span class="preprocessor">#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) </span></div>
|
||
<div class="line"><a id="l06143" name="l06143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52d6df2b5ab2b43da273a702fe139b59"> 6143</a></span><span class="preprocessor">#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk </span></div>
|
||
<div class="line"><a id="l06144" name="l06144"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54fe74158bbf9ebfc8905b256c16b1aa"> 6144</a></span><span class="preprocessor">#define DMA_LIFCR_CHTIF2_Pos (20U) </span></div>
|
||
<div class="line"><a id="l06145" name="l06145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac756f07e62c4b7f720924d67b42b9af7"> 6145</a></span><span class="preprocessor">#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) </span></div>
|
||
<div class="line"><a id="l06146" name="l06146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae19254e8ad726a73c6edc01bc7cf2cfa"> 6146</a></span><span class="preprocessor">#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk </span></div>
|
||
<div class="line"><a id="l06147" name="l06147"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e4b3f5d3bbfba08a7716e8e14c7c7b2"> 6147</a></span><span class="preprocessor">#define DMA_LIFCR_CTEIF2_Pos (19U) </span></div>
|
||
<div class="line"><a id="l06148" name="l06148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27d209fe8a4bec205b32f36435895a3a"> 6148</a></span><span class="preprocessor">#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) </span></div>
|
||
<div class="line"><a id="l06149" name="l06149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9d761752657a3d268da5434a04c6c6a"> 6149</a></span><span class="preprocessor">#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk </span></div>
|
||
<div class="line"><a id="l06150" name="l06150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefc5081ac74c4a7cd7b9294d8be92251"> 6150</a></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF2_Pos (18U) </span></div>
|
||
<div class="line"><a id="l06151" name="l06151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacac8f0e26e7170255fb9d9fd31b1ccbe"> 6151</a></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) </span></div>
|
||
<div class="line"><a id="l06152" name="l06152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7680fc5f5e6c0032044f1d8ab7766de8"> 6152</a></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk </span></div>
|
||
<div class="line"><a id="l06153" name="l06153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5cf455eeb40c690897a63399e06b980a"> 6153</a></span><span class="preprocessor">#define DMA_LIFCR_CFEIF2_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06154" name="l06154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga117212472340bb8a793f05a4dcb98f03"> 6154</a></span><span class="preprocessor">#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) </span></div>
|
||
<div class="line"><a id="l06155" name="l06155"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0f58173c721a4cee3f3885b352fa2a3"> 6155</a></span><span class="preprocessor">#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk </span></div>
|
||
<div class="line"><a id="l06156" name="l06156"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2be6c298222759f49d71995f225a9c8"> 6156</a></span><span class="preprocessor">#define DMA_LIFCR_CTCIF1_Pos (11U) </span></div>
|
||
<div class="line"><a id="l06157" name="l06157"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81fc3bbc2471af2fc722698c394b5595"> 6157</a></span><span class="preprocessor">#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) </span></div>
|
||
<div class="line"><a id="l06158" name="l06158"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7494c54901b8f5bcb4894d20b8cfafed"> 6158</a></span><span class="preprocessor">#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk </span></div>
|
||
<div class="line"><a id="l06159" name="l06159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cceed053af9c55ee130b9cac3dfa40f"> 6159</a></span><span class="preprocessor">#define DMA_LIFCR_CHTIF1_Pos (10U) </span></div>
|
||
<div class="line"><a id="l06160" name="l06160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c3edca2d07701c0b50a844454593d54"> 6160</a></span><span class="preprocessor">#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) </span></div>
|
||
<div class="line"><a id="l06161" name="l06161"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2f38b0c141a9afb3943276dacdcb969"> 6161</a></span><span class="preprocessor">#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk </span></div>
|
||
<div class="line"><a id="l06162" name="l06162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e5563a90f78b2aa62d4cc65fd2ea2e8"> 6162</a></span><span class="preprocessor">#define DMA_LIFCR_CTEIF1_Pos (9U) </span></div>
|
||
<div class="line"><a id="l06163" name="l06163"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf08b5acf028d011d3ccf519066f4e58e"> 6163</a></span><span class="preprocessor">#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) </span></div>
|
||
<div class="line"><a id="l06164" name="l06164"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6d8adf52567aee2969492db65d448d4"> 6164</a></span><span class="preprocessor">#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk </span></div>
|
||
<div class="line"><a id="l06165" name="l06165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7f3844824818f2a180921ec71e10165"> 6165</a></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF1_Pos (8U) </span></div>
|
||
<div class="line"><a id="l06166" name="l06166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d5941929a8582fdaf1e413063b56728"> 6166</a></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) </span></div>
|
||
<div class="line"><a id="l06167" name="l06167"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a5aea54a390886f7de82e87e6dfc936"> 6167</a></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk </span></div>
|
||
<div class="line"><a id="l06168" name="l06168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7449839b8ccb071b0297c04b3f308374"> 6168</a></span><span class="preprocessor">#define DMA_LIFCR_CFEIF1_Pos (6U) </span></div>
|
||
<div class="line"><a id="l06169" name="l06169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0809a566feea19caa99820c0beb7593a"> 6169</a></span><span class="preprocessor">#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) </span></div>
|
||
<div class="line"><a id="l06170" name="l06170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96cea0049553ab806bbc956f52528c37"> 6170</a></span><span class="preprocessor">#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk </span></div>
|
||
<div class="line"><a id="l06171" name="l06171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafee1c266c0c7d8ae75506988c24f197a"> 6171</a></span><span class="preprocessor">#define DMA_LIFCR_CTCIF0_Pos (5U) </span></div>
|
||
<div class="line"><a id="l06172" name="l06172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a99e08422f2f1ab8858824e873f0a5d"> 6172</a></span><span class="preprocessor">#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) </span></div>
|
||
<div class="line"><a id="l06173" name="l06173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7a0b2cc41c63504195714614e59dc8e"> 6173</a></span><span class="preprocessor">#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk </span></div>
|
||
<div class="line"><a id="l06174" name="l06174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4745b0ea4d34ffb750b377de2865dee"> 6174</a></span><span class="preprocessor">#define DMA_LIFCR_CHTIF0_Pos (4U) </span></div>
|
||
<div class="line"><a id="l06175" name="l06175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca0f3b2beb4ae475024f013bfbe7813e"> 6175</a></span><span class="preprocessor">#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) </span></div>
|
||
<div class="line"><a id="l06176" name="l06176"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44f83ba08feb98240a553403d977b8d1"> 6176</a></span><span class="preprocessor">#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk </span></div>
|
||
<div class="line"><a id="l06177" name="l06177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac20301e14197382e7e5f532fe6d3c21f"> 6177</a></span><span class="preprocessor">#define DMA_LIFCR_CTEIF0_Pos (3U) </span></div>
|
||
<div class="line"><a id="l06178" name="l06178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e2bd6764a2c823750659f82e6ab82e4"> 6178</a></span><span class="preprocessor">#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) </span></div>
|
||
<div class="line"><a id="l06179" name="l06179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5824a64683ce2039260c952d989bf420"> 6179</a></span><span class="preprocessor">#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk </span></div>
|
||
<div class="line"><a id="l06180" name="l06180"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9328d47385259284470fe88126f161c1"> 6180</a></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF0_Pos (2U) </span></div>
|
||
<div class="line"><a id="l06181" name="l06181"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad09384dd4e933d5ae8490599f09b60f"> 6181</a></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) </span></div>
|
||
<div class="line"><a id="l06182" name="l06182"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe80a122bf0537e8c95877ccf2b7b6d9"> 6182</a></span><span class="preprocessor">#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk </span></div>
|
||
<div class="line"><a id="l06183" name="l06183"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89140d2a2a82950d5cbd470e264fb525"> 6183</a></span><span class="preprocessor">#define DMA_LIFCR_CFEIF0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06184" name="l06184"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5e3b1026a57f00f382879e844835e95"> 6184</a></span><span class="preprocessor">#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) </span></div>
|
||
<div class="line"><a id="l06185" name="l06185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf6b8892189f3779f7fecf529ed87c74"> 6185</a></span><span class="preprocessor">#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk </span></div>
|
||
<div class="line"><a id="l06186" name="l06186"></a><span class="lineno"> 6186</span> </div>
|
||
<div class="line"><a id="l06187" name="l06187"></a><span class="lineno"> 6187</span><span class="comment">/******************** Bits definition for DMA_HIFCR register ****************/</span> </div>
|
||
<div class="line"><a id="l06188" name="l06188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42d3e6cfd2eef1e3d12e677af584447e"> 6188</a></span><span class="preprocessor">#define DMA_HIFCR_CTCIF7_Pos (27U) </span></div>
|
||
<div class="line"><a id="l06189" name="l06189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade1f557e9a94cd3841f22f0955ab2a43"> 6189</a></span><span class="preprocessor">#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) </span></div>
|
||
<div class="line"><a id="l06190" name="l06190"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf8056629f4948fb236b4339e213cc69"> 6190</a></span><span class="preprocessor">#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk </span></div>
|
||
<div class="line"><a id="l06191" name="l06191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade6f40f4c574d22ec8527d8c27e78b58"> 6191</a></span><span class="preprocessor">#define DMA_HIFCR_CHTIF7_Pos (26U) </span></div>
|
||
<div class="line"><a id="l06192" name="l06192"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga256a0e76673c186a39f9f717af2e2287"> 6192</a></span><span class="preprocessor">#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) </span></div>
|
||
<div class="line"><a id="l06193" name="l06193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95e9989cbd70b18d833bb4cfcb8afce9"> 6193</a></span><span class="preprocessor">#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk </span></div>
|
||
<div class="line"><a id="l06194" name="l06194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafae9da1fff2402f645b428368a4aea14"> 6194</a></span><span class="preprocessor">#define DMA_HIFCR_CTEIF7_Pos (25U) </span></div>
|
||
<div class="line"><a id="l06195" name="l06195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08c1daec30b9644c55db577867afe491"> 6195</a></span><span class="preprocessor">#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) </span></div>
|
||
<div class="line"><a id="l06196" name="l06196"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84ab215e0b217547745beefb65dfefdf"> 6196</a></span><span class="preprocessor">#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk </span></div>
|
||
<div class="line"><a id="l06197" name="l06197"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f4cf4a690ee458370ce8482e3a9b1b9"> 6197</a></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF7_Pos (24U) </span></div>
|
||
<div class="line"><a id="l06198" name="l06198"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb5c753438fac42cee45e0e9a34fab6c"> 6198</a></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) </span></div>
|
||
<div class="line"><a id="l06199" name="l06199"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad70bf852fd8c24d79fcc104c950a589f"> 6199</a></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk </span></div>
|
||
<div class="line"><a id="l06200" name="l06200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga913da2290fb4ba8484a69b34e71840c7"> 6200</a></span><span class="preprocessor">#define DMA_HIFCR_CFEIF7_Pos (22U) </span></div>
|
||
<div class="line"><a id="l06201" name="l06201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga962da3b48acc29b53beae6ae483f5331"> 6201</a></span><span class="preprocessor">#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) </span></div>
|
||
<div class="line"><a id="l06202" name="l06202"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50332abe2e7b5a4f9cffd65d9a29382a"> 6202</a></span><span class="preprocessor">#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk </span></div>
|
||
<div class="line"><a id="l06203" name="l06203"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga194f6a4be6fd796e114fb77ea2f15220"> 6203</a></span><span class="preprocessor">#define DMA_HIFCR_CTCIF6_Pos (21U) </span></div>
|
||
<div class="line"><a id="l06204" name="l06204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8367ef52cfc4bb3dd4e1bbf8c01fc189"> 6204</a></span><span class="preprocessor">#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) </span></div>
|
||
<div class="line"><a id="l06205" name="l06205"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd88be16962491e41e586f5109014bc6"> 6205</a></span><span class="preprocessor">#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk </span></div>
|
||
<div class="line"><a id="l06206" name="l06206"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4768327967dc957b842d2433d2cc5c2"> 6206</a></span><span class="preprocessor">#define DMA_HIFCR_CHTIF6_Pos (20U) </span></div>
|
||
<div class="line"><a id="l06207" name="l06207"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6464e076a7b905e1b4a73e367fb4488e"> 6207</a></span><span class="preprocessor">#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) </span></div>
|
||
<div class="line"><a id="l06208" name="l06208"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed7cbbbc0602d00e101e3f57aa3b696a"> 6208</a></span><span class="preprocessor">#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk </span></div>
|
||
<div class="line"><a id="l06209" name="l06209"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e0f6b1fd4902396d59d0d9865bd329e"> 6209</a></span><span class="preprocessor">#define DMA_HIFCR_CTEIF6_Pos (19U) </span></div>
|
||
<div class="line"><a id="l06210" name="l06210"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4328c04dd38fc2360b7333d6e22d8f73"> 6210</a></span><span class="preprocessor">#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) </span></div>
|
||
<div class="line"><a id="l06211" name="l06211"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69e01e2f6a5cd1c800321e4121f8e788"> 6211</a></span><span class="preprocessor">#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk </span></div>
|
||
<div class="line"><a id="l06212" name="l06212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a658f3e303a31be475cb1ea9957dc2e"> 6212</a></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF6_Pos (18U) </span></div>
|
||
<div class="line"><a id="l06213" name="l06213"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga798be301c7de50d3015965037a8ec2bd"> 6213</a></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) </span></div>
|
||
<div class="line"><a id="l06214" name="l06214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f73fa93a4e01fbf279e920eca139807"> 6214</a></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk </span></div>
|
||
<div class="line"><a id="l06215" name="l06215"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cbdd122358aad1b832dcc0a7a4405af"> 6215</a></span><span class="preprocessor">#define DMA_HIFCR_CFEIF6_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06216" name="l06216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4bb45a54e669718435808019bd2b9fb"> 6216</a></span><span class="preprocessor">#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) </span></div>
|
||
<div class="line"><a id="l06217" name="l06217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39a0a7f42498f71dedae8140483b7ced"> 6217</a></span><span class="preprocessor">#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk </span></div>
|
||
<div class="line"><a id="l06218" name="l06218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e2ab5fecba1f2673c14bc21e9052dc9"> 6218</a></span><span class="preprocessor">#define DMA_HIFCR_CTCIF5_Pos (11U) </span></div>
|
||
<div class="line"><a id="l06219" name="l06219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bec2f8ae9244ef971aed8aa9253f7fe"> 6219</a></span><span class="preprocessor">#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) </span></div>
|
||
<div class="line"><a id="l06220" name="l06220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa55d19705147a6ee16effe9ec1012a72"> 6220</a></span><span class="preprocessor">#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk </span></div>
|
||
<div class="line"><a id="l06221" name="l06221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f5d41d4856f8ff464ce01e96e9f6e3f"> 6221</a></span><span class="preprocessor">#define DMA_HIFCR_CHTIF5_Pos (10U) </span></div>
|
||
<div class="line"><a id="l06222" name="l06222"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1ff3abfbb813d2e7c030d9b16786d00"> 6222</a></span><span class="preprocessor">#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) </span></div>
|
||
<div class="line"><a id="l06223" name="l06223"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cef7eeccd11737c1ebf5735284046cc"> 6223</a></span><span class="preprocessor">#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk </span></div>
|
||
<div class="line"><a id="l06224" name="l06224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42493eb990d42aa17c178842ecef08bd"> 6224</a></span><span class="preprocessor">#define DMA_HIFCR_CTEIF5_Pos (9U) </span></div>
|
||
<div class="line"><a id="l06225" name="l06225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca104c26dd5e9190434023a88d0dc4ac"> 6225</a></span><span class="preprocessor">#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) </span></div>
|
||
<div class="line"><a id="l06226" name="l06226"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33394fe20a3567c8baaeb15ad9aab586"> 6226</a></span><span class="preprocessor">#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk </span></div>
|
||
<div class="line"><a id="l06227" name="l06227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f259d0788bd3ae21521c574d0d1a00b"> 6227</a></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF5_Pos (8U) </span></div>
|
||
<div class="line"><a id="l06228" name="l06228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b99d7b4f3c6346ccafa79d425ee6873"> 6228</a></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) </span></div>
|
||
<div class="line"><a id="l06229" name="l06229"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15b404d9e1601cf3627cbf0163b50221"> 6229</a></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk </span></div>
|
||
<div class="line"><a id="l06230" name="l06230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60dbe00935c13e0ef57c08970f711a6a"> 6230</a></span><span class="preprocessor">#define DMA_HIFCR_CFEIF5_Pos (6U) </span></div>
|
||
<div class="line"><a id="l06231" name="l06231"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab48755800a0d03cf51f6c69848c6e1ce"> 6231</a></span><span class="preprocessor">#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) </span></div>
|
||
<div class="line"><a id="l06232" name="l06232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a4e90af967fa0a76c842384264e0e52"> 6232</a></span><span class="preprocessor">#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk </span></div>
|
||
<div class="line"><a id="l06233" name="l06233"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeaf0336605023f5db079294ebe4ea822"> 6233</a></span><span class="preprocessor">#define DMA_HIFCR_CTCIF4_Pos (5U) </span></div>
|
||
<div class="line"><a id="l06234" name="l06234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae02d30716d6c3e975c13073ae65f69e5"> 6234</a></span><span class="preprocessor">#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) </span></div>
|
||
<div class="line"><a id="l06235" name="l06235"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42e529507a40f0dc4c16da7cc6d659db"> 6235</a></span><span class="preprocessor">#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk </span></div>
|
||
<div class="line"><a id="l06236" name="l06236"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3415c8fd19bcb513fc96363d287784a4"> 6236</a></span><span class="preprocessor">#define DMA_HIFCR_CHTIF4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l06237" name="l06237"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa1aa9781098072d161c20890c3d1918"> 6237</a></span><span class="preprocessor">#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) </span></div>
|
||
<div class="line"><a id="l06238" name="l06238"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8f0afa9a6526f7f4413766417a56be8"> 6238</a></span><span class="preprocessor">#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk </span></div>
|
||
<div class="line"><a id="l06239" name="l06239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d1ac1b86e7505eceef920910bd930e2"> 6239</a></span><span class="preprocessor">#define DMA_HIFCR_CTEIF4_Pos (3U) </span></div>
|
||
<div class="line"><a id="l06240" name="l06240"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5aa004e3db2fb6845a6678bd30d9a604"> 6240</a></span><span class="preprocessor">#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) </span></div>
|
||
<div class="line"><a id="l06241" name="l06241"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e05ff4fc6bace9cc6c0f0d4ec7b3314"> 6241</a></span><span class="preprocessor">#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk </span></div>
|
||
<div class="line"><a id="l06242" name="l06242"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga465e500de4458c78f26aa483d8f61ee7"> 6242</a></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF4_Pos (2U) </span></div>
|
||
<div class="line"><a id="l06243" name="l06243"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c5757329dbf0633cbe2ff33591b7f2d"> 6243</a></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) </span></div>
|
||
<div class="line"><a id="l06244" name="l06244"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d70d58a4423ac8973c30ddbc7404b44"> 6244</a></span><span class="preprocessor">#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk </span></div>
|
||
<div class="line"><a id="l06245" name="l06245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga348534b63d5c5d29a3fdd8b080866566"> 6245</a></span><span class="preprocessor">#define DMA_HIFCR_CFEIF4_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06246" name="l06246"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd6d4a4e8764fa0406a1c9dd1bc4535f"> 6246</a></span><span class="preprocessor">#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) </span></div>
|
||
<div class="line"><a id="l06247" name="l06247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e5ea118900178d4fa2d19656c1b48ff"> 6247</a></span><span class="preprocessor">#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk </span></div>
|
||
<div class="line"><a id="l06248" name="l06248"></a><span class="lineno"> 6248</span> </div>
|
||
<div class="line"><a id="l06249" name="l06249"></a><span class="lineno"> 6249</span><span class="comment">/****************** Bit definition for DMA_SxPAR register ********************/</span></div>
|
||
<div class="line"><a id="l06250" name="l06250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga323024ac58e46cdcb78e207f1749775c"> 6250</a></span><span class="preprocessor">#define DMA_SxPAR_PA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06251" name="l06251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19727ba46d26c121b0133381ceb4b521"> 6251</a></span><span class="preprocessor">#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) </span></div>
|
||
<div class="line"><a id="l06252" name="l06252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05ea0d30f566ad469a7794e088b93ecf"> 6252</a></span><span class="preprocessor">#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk </span></div>
|
||
<div class="line"><a id="l06254" name="l06254"></a><span class="lineno"> 6254</span><span class="comment">/****************** Bit definition for DMA_SxM0AR register ********************/</span></div>
|
||
<div class="line"><a id="l06255" name="l06255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade05cbad452eb0b6e0a2627ff70c0145"> 6255</a></span><span class="preprocessor">#define DMA_SxM0AR_M0A_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06256" name="l06256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9675f5a5f6306fe441e0ee395b055d36"> 6256</a></span><span class="preprocessor">#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) </span></div>
|
||
<div class="line"><a id="l06257" name="l06257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad87688b73616d4ff9503421a820f1cf"> 6257</a></span><span class="preprocessor">#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk </span></div>
|
||
<div class="line"><a id="l06259" name="l06259"></a><span class="lineno"> 6259</span><span class="comment">/****************** Bit definition for DMA_SxM1AR register ********************/</span></div>
|
||
<div class="line"><a id="l06260" name="l06260"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa61888c070a3873c9fb8ee1486772e3a"> 6260</a></span><span class="preprocessor">#define DMA_SxM1AR_M1A_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06261" name="l06261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73d1e5bcfadadcb890897b907225cd73"> 6261</a></span><span class="preprocessor">#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) </span></div>
|
||
<div class="line"><a id="l06262" name="l06262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae057bfb6e5d7b553b668a050fcdb152d"> 6262</a></span><span class="preprocessor">#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk </span></div>
|
||
<div class="line"><a id="l06265" name="l06265"></a><span class="lineno"> 6265</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l06266" name="l06266"></a><span class="lineno"> 6266</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l06267" name="l06267"></a><span class="lineno"> 6267</span><span class="comment">/* External Interrupt/Event Controller */</span></div>
|
||
<div class="line"><a id="l06268" name="l06268"></a><span class="lineno"> 6268</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l06269" name="l06269"></a><span class="lineno"> 6269</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l06270" name="l06270"></a><span class="lineno"> 6270</span><span class="comment">/******************* Bit definition for EXTI_IMR register *******************/</span></div>
|
||
<div class="line"><a id="l06271" name="l06271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4702ca255bab973cffa5dd240594a7a3"> 6271</a></span><span class="preprocessor">#define EXTI_IMR_MR0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06272" name="l06272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf1117a400c80d740d3dbb7fbea0f8ce"> 6272</a></span><span class="preprocessor">#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) </span></div>
|
||
<div class="line"><a id="l06273" name="l06273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad03b2ba6cde99065627fccabd54ac097"> 6273</a></span><span class="preprocessor">#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk </span></div>
|
||
<div class="line"><a id="l06274" name="l06274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27eb2217e842fa69573590793a1e6b38"> 6274</a></span><span class="preprocessor">#define EXTI_IMR_MR1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l06275" name="l06275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacadc6566dd71406d2d516785c4b776bd"> 6275</a></span><span class="preprocessor">#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) </span></div>
|
||
<div class="line"><a id="l06276" name="l06276"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaaf3f9a86c620149893db38c83f8ba58"> 6276</a></span><span class="preprocessor">#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk </span></div>
|
||
<div class="line"><a id="l06277" name="l06277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58855e17d769f246e7422b3f875c85a2"> 6277</a></span><span class="preprocessor">#define EXTI_IMR_MR2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l06278" name="l06278"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga183b9b9663a6aeec66f0238abbbf282f"> 6278</a></span><span class="preprocessor">#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) </span></div>
|
||
<div class="line"><a id="l06279" name="l06279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71604d1c29973c5e2bf69c8e94e89f67"> 6279</a></span><span class="preprocessor">#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk </span></div>
|
||
<div class="line"><a id="l06280" name="l06280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0b0d4c04570bfe939843d7cb5bf15f6"> 6280</a></span><span class="preprocessor">#define EXTI_IMR_MR3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l06281" name="l06281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f6badc25c27d6185c0e560454384a90"> 6281</a></span><span class="preprocessor">#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) </span></div>
|
||
<div class="line"><a id="l06282" name="l06282"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5edd42f9b2129c18cfa3c3598dcd1134"> 6282</a></span><span class="preprocessor">#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk </span></div>
|
||
<div class="line"><a id="l06283" name="l06283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae18a7ef85db4597309170659c7ff1e6c"> 6283</a></span><span class="preprocessor">#define EXTI_IMR_MR4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l06284" name="l06284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64dbc3def48abe258dd1e1ecce481086"> 6284</a></span><span class="preprocessor">#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) </span></div>
|
||
<div class="line"><a id="l06285" name="l06285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23e920ad334439cd2ad4d683054914e3"> 6285</a></span><span class="preprocessor">#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk </span></div>
|
||
<div class="line"><a id="l06286" name="l06286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01f6ecdcfdf234180e99e7d9c02affc7"> 6286</a></span><span class="preprocessor">#define EXTI_IMR_MR5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l06287" name="l06287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18ca0d16b43ed78d36f52dd5ab0c21c2"> 6287</a></span><span class="preprocessor">#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) </span></div>
|
||
<div class="line"><a id="l06288" name="l06288"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cd3c5a2e4c4cb9b81e8965fcbf1c3a5"> 6288</a></span><span class="preprocessor">#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk </span></div>
|
||
<div class="line"><a id="l06289" name="l06289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc6874ec52a6b876dd48842a28d219ba"> 6289</a></span><span class="preprocessor">#define EXTI_IMR_MR6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l06290" name="l06290"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6dcc5b70b0a599e944d99f53ac071e1a"> 6290</a></span><span class="preprocessor">#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) </span></div>
|
||
<div class="line"><a id="l06291" name="l06291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5533c8ec796e3bbc9dc4474376056e06"> 6291</a></span><span class="preprocessor">#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk </span></div>
|
||
<div class="line"><a id="l06292" name="l06292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1b52dd9408a254ec3ba436ede0e42fa"> 6292</a></span><span class="preprocessor">#define EXTI_IMR_MR7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l06293" name="l06293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae41e117f93d5e426758ee40bd7d45755"> 6293</a></span><span class="preprocessor">#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) </span></div>
|
||
<div class="line"><a id="l06294" name="l06294"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab620165d3fea1c564fcf1016805a1a8e"> 6294</a></span><span class="preprocessor">#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk </span></div>
|
||
<div class="line"><a id="l06295" name="l06295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1ad8042623ea52664eb00b43e35dcb7"> 6295</a></span><span class="preprocessor">#define EXTI_IMR_MR8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l06296" name="l06296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02a618dd052d47d30cadf578ee58e416"> 6296</a></span><span class="preprocessor">#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) </span></div>
|
||
<div class="line"><a id="l06297" name="l06297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88e8b274e4398fdcb1c68da2b6320d5b"> 6297</a></span><span class="preprocessor">#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk </span></div>
|
||
<div class="line"><a id="l06298" name="l06298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b9b5e7500420b3ce5a2b711ed73fa50"> 6298</a></span><span class="preprocessor">#define EXTI_IMR_MR9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l06299" name="l06299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7433c8c28acd006d4a71e803f6d95de3"> 6299</a></span><span class="preprocessor">#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) </span></div>
|
||
<div class="line"><a id="l06300" name="l06300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4d177dcf33bb9a34f8590ec509746e8"> 6300</a></span><span class="preprocessor">#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk </span></div>
|
||
<div class="line"><a id="l06301" name="l06301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f8a8f8245716f96dde7049e27435f9a"> 6301</a></span><span class="preprocessor">#define EXTI_IMR_MR10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l06302" name="l06302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga530c1c2659363a1edaba4af52c7e6a7d"> 6302</a></span><span class="preprocessor">#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) </span></div>
|
||
<div class="line"><a id="l06303" name="l06303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fd7db9a1ce82c152ca7bc6fddf31366"> 6303</a></span><span class="preprocessor">#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk </span></div>
|
||
<div class="line"><a id="l06304" name="l06304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29cc04d8d5116420b5b63c2f7c6b98e3"> 6304</a></span><span class="preprocessor">#define EXTI_IMR_MR11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l06305" name="l06305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25a00372781fec24bbabb7d2aeca82bd"> 6305</a></span><span class="preprocessor">#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) </span></div>
|
||
<div class="line"><a id="l06306" name="l06306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68cfe8fe938fcb0fc6925bf493ccfaa7"> 6306</a></span><span class="preprocessor">#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk </span></div>
|
||
<div class="line"><a id="l06307" name="l06307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddd5fe4e39d5ff13ad5d3a051ffd2b73"> 6307</a></span><span class="preprocessor">#define EXTI_IMR_MR12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l06308" name="l06308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c26fd0b40d6d66aec7cc5fff86f6720"> 6308</a></span><span class="preprocessor">#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) </span></div>
|
||
<div class="line"><a id="l06309" name="l06309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad21caf923d2083fb106852493667c16e"> 6309</a></span><span class="preprocessor">#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk </span></div>
|
||
<div class="line"><a id="l06310" name="l06310"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3658584854eb1f7c9ad43934e5cb9f2a"> 6310</a></span><span class="preprocessor">#define EXTI_IMR_MR13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l06311" name="l06311"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf4095ebf9c75696a62d7bead70cc5cc"> 6311</a></span><span class="preprocessor">#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) </span></div>
|
||
<div class="line"><a id="l06312" name="l06312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e1938a063c48d7d6504cb32f7965c0e"> 6312</a></span><span class="preprocessor">#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk </span></div>
|
||
<div class="line"><a id="l06313" name="l06313"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05cb292831097d4790e00b89987cf5bb"> 6313</a></span><span class="preprocessor">#define EXTI_IMR_MR14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l06314" name="l06314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga052609a42da3b6c6895f006e50c12ab6"> 6314</a></span><span class="preprocessor">#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) </span></div>
|
||
<div class="line"><a id="l06315" name="l06315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8827cee06670f256bc8f6301bea9cab"> 6315</a></span><span class="preprocessor">#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk </span></div>
|
||
<div class="line"><a id="l06316" name="l06316"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84e87a9c94dd2cdf7ea1851c2af7727b"> 6316</a></span><span class="preprocessor">#define EXTI_IMR_MR15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l06317" name="l06317"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27011a5c7488ed0273c821804ef6a27b"> 6317</a></span><span class="preprocessor">#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) </span></div>
|
||
<div class="line"><a id="l06318" name="l06318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88d9990be7f8f9e530a9f930a365fa44"> 6318</a></span><span class="preprocessor">#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk </span></div>
|
||
<div class="line"><a id="l06319" name="l06319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fc8dc837cd6326f1fb7fae42e56ef74"> 6319</a></span><span class="preprocessor">#define EXTI_IMR_MR16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06320" name="l06320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga155179198c3735dd1e35baf733f1542e"> 6320</a></span><span class="preprocessor">#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) </span></div>
|
||
<div class="line"><a id="l06321" name="l06321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7419f78ed9044bdd237b452ef49e1b7f"> 6321</a></span><span class="preprocessor">#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk </span></div>
|
||
<div class="line"><a id="l06322" name="l06322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbc90bbbbc4137c8af29df2fc0162ae5"> 6322</a></span><span class="preprocessor">#define EXTI_IMR_MR17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l06323" name="l06323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6eb3bf08d4a51133e62dd719f2e48b8"> 6323</a></span><span class="preprocessor">#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) </span></div>
|
||
<div class="line"><a id="l06324" name="l06324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4489fa85d1552b8f40faed93483a5d35"> 6324</a></span><span class="preprocessor">#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk </span></div>
|
||
<div class="line"><a id="l06325" name="l06325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9084142db0eac80226038ced74846aa8"> 6325</a></span><span class="preprocessor">#define EXTI_IMR_MR18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l06326" name="l06326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52a2709f4f9d2ccb8d63c36958517b26"> 6326</a></span><span class="preprocessor">#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) </span></div>
|
||
<div class="line"><a id="l06327" name="l06327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05e16f2cda40cca58a45458cc44d510f"> 6327</a></span><span class="preprocessor">#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk </span></div>
|
||
<div class="line"><a id="l06328" name="l06328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92d1beae3a87cd1515fd1104bb2e0ac5"> 6328</a></span><span class="preprocessor">#define EXTI_IMR_MR19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l06329" name="l06329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab55fbb64891a3120b3d5c53984abe6ca"> 6329</a></span><span class="preprocessor">#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) </span></div>
|
||
<div class="line"><a id="l06330" name="l06330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad47f7a023cbba165dfb95845d3c8c55c"> 6330</a></span><span class="preprocessor">#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk </span></div>
|
||
<div class="line"><a id="l06331" name="l06331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8a252b7afd91a453cd613fca4792aed"> 6331</a></span><span class="preprocessor">#define EXTI_IMR_MR20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l06332" name="l06332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e9bb3e1445d27d46816b0be57cbfbbd"> 6332</a></span><span class="preprocessor">#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) </span></div>
|
||
<div class="line"><a id="l06333" name="l06333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4aee679baf5820e1666b60e48a64cafa"> 6333</a></span><span class="preprocessor">#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk </span></div>
|
||
<div class="line"><a id="l06334" name="l06334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga777cbe130041b394e728de96fac11175"> 6334</a></span><span class="preprocessor">#define EXTI_IMR_MR21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l06335" name="l06335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae66e025fa607e21af5498613c7ec7ebf"> 6335</a></span><span class="preprocessor">#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) </span></div>
|
||
<div class="line"><a id="l06336" name="l06336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cc7e64c45d273ca7396ac1e0ce38c36"> 6336</a></span><span class="preprocessor">#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk </span></div>
|
||
<div class="line"><a id="l06337" name="l06337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83efcf05bd49c293779334f366a3e342"> 6337</a></span><span class="preprocessor">#define EXTI_IMR_MR22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l06338" name="l06338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20c62ffabf9a216bc5d682fc0f1ad5f6"> 6338</a></span><span class="preprocessor">#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) </span></div>
|
||
<div class="line"><a id="l06339" name="l06339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2aec84941d816be18a1607b6ee25acb1"> 6339</a></span><span class="preprocessor">#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk </span></div>
|
||
<div class="line"><a id="l06341" name="l06341"></a><span class="lineno"> 6341</span><span class="comment">/* Reference Defines */</span></div>
|
||
<div class="line"><a id="l06342" name="l06342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae43e6abdba2e7d7b7eaa07b268f288b3"> 6342</a></span><span class="preprocessor">#define EXTI_IMR_IM0 EXTI_IMR_MR0</span></div>
|
||
<div class="line"><a id="l06343" name="l06343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1498c6a9cb8eb9842b83a2e91b3c290d"> 6343</a></span><span class="preprocessor">#define EXTI_IMR_IM1 EXTI_IMR_MR1</span></div>
|
||
<div class="line"><a id="l06344" name="l06344"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10013221a5de01374bb63623ca68d5a5"> 6344</a></span><span class="preprocessor">#define EXTI_IMR_IM2 EXTI_IMR_MR2</span></div>
|
||
<div class="line"><a id="l06345" name="l06345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a7e8e899926ae962ae34dc9d143fd09"> 6345</a></span><span class="preprocessor">#define EXTI_IMR_IM3 EXTI_IMR_MR3</span></div>
|
||
<div class="line"><a id="l06346" name="l06346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadad3c244ed0a107b5c4f96470a914348"> 6346</a></span><span class="preprocessor">#define EXTI_IMR_IM4 EXTI_IMR_MR4</span></div>
|
||
<div class="line"><a id="l06347" name="l06347"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91070bca3731cbe48e7bc97de97631a5"> 6347</a></span><span class="preprocessor">#define EXTI_IMR_IM5 EXTI_IMR_MR5</span></div>
|
||
<div class="line"><a id="l06348" name="l06348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ab55682980062f57cdb981aa649fbf3"> 6348</a></span><span class="preprocessor">#define EXTI_IMR_IM6 EXTI_IMR_MR6</span></div>
|
||
<div class="line"><a id="l06349" name="l06349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd6ee214b24d450efe0c52d0b1dae0f4"> 6349</a></span><span class="preprocessor">#define EXTI_IMR_IM7 EXTI_IMR_MR7</span></div>
|
||
<div class="line"><a id="l06350" name="l06350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc41defd6bd026adde49d44ad1e8a5c4"> 6350</a></span><span class="preprocessor">#define EXTI_IMR_IM8 EXTI_IMR_MR8</span></div>
|
||
<div class="line"><a id="l06351" name="l06351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a43b1d5d7f5dabbc44b03bdab7a6c3e"> 6351</a></span><span class="preprocessor">#define EXTI_IMR_IM9 EXTI_IMR_MR9</span></div>
|
||
<div class="line"><a id="l06352" name="l06352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e31c6dd167542dc8660c7dd6f31e0e9"> 6352</a></span><span class="preprocessor">#define EXTI_IMR_IM10 EXTI_IMR_MR10</span></div>
|
||
<div class="line"><a id="l06353" name="l06353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5441a9f074c104d67a7629467724f3a0"> 6353</a></span><span class="preprocessor">#define EXTI_IMR_IM11 EXTI_IMR_MR11</span></div>
|
||
<div class="line"><a id="l06354" name="l06354"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab736b78d54e4ae9b5f1ee0bebbda1e4d"> 6354</a></span><span class="preprocessor">#define EXTI_IMR_IM12 EXTI_IMR_MR12</span></div>
|
||
<div class="line"><a id="l06355" name="l06355"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b835eee91599273c334d6bed80bdaca"> 6355</a></span><span class="preprocessor">#define EXTI_IMR_IM13 EXTI_IMR_MR13</span></div>
|
||
<div class="line"><a id="l06356" name="l06356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga933e1e28d08958b9800cbfbea953b9e6"> 6356</a></span><span class="preprocessor">#define EXTI_IMR_IM14 EXTI_IMR_MR14</span></div>
|
||
<div class="line"><a id="l06357" name="l06357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16ac63565a42896a10eb5b56d45df7f1"> 6357</a></span><span class="preprocessor">#define EXTI_IMR_IM15 EXTI_IMR_MR15</span></div>
|
||
<div class="line"><a id="l06358" name="l06358"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33e28d73aacdcc55491fe44c2e840398"> 6358</a></span><span class="preprocessor">#define EXTI_IMR_IM16 EXTI_IMR_MR16</span></div>
|
||
<div class="line"><a id="l06359" name="l06359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0db46755679e595721057e90574b1434"> 6359</a></span><span class="preprocessor">#define EXTI_IMR_IM17 EXTI_IMR_MR17</span></div>
|
||
<div class="line"><a id="l06360" name="l06360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f0a2063e564c44ba51733e0fcf25745"> 6360</a></span><span class="preprocessor">#define EXTI_IMR_IM18 EXTI_IMR_MR18</span></div>
|
||
<div class="line"><a id="l06361" name="l06361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cc8bc70fd30f54311218abe6c52c21c"> 6361</a></span><span class="preprocessor">#define EXTI_IMR_IM19 EXTI_IMR_MR19</span></div>
|
||
<div class="line"><a id="l06362" name="l06362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ec4f917392fcd3b64bfae4d17fe1808"> 6362</a></span><span class="preprocessor">#define EXTI_IMR_IM20 EXTI_IMR_MR20</span></div>
|
||
<div class="line"><a id="l06363" name="l06363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9539fd6427a262f7cdbd42cd68a10eca"> 6363</a></span><span class="preprocessor">#define EXTI_IMR_IM21 EXTI_IMR_MR21</span></div>
|
||
<div class="line"><a id="l06364" name="l06364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab05cb948001efcf6d1cf4968160f3aa5"> 6364</a></span><span class="preprocessor">#define EXTI_IMR_IM22 EXTI_IMR_MR22</span></div>
|
||
<div class="line"><a id="l06365" name="l06365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fe01103a449e5f81a25c733a3c1a03c"> 6365</a></span><span class="preprocessor">#define EXTI_IMR_IM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06366" name="l06366"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06eeb49b799d40a72140618195e6a55d"> 6366</a></span><span class="preprocessor">#define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos) </span></div>
|
||
<div class="line"><a id="l06367" name="l06367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4f23236f2d0bb9ed886556064714c50"> 6367</a></span><span class="preprocessor">#define EXTI_IMR_IM EXTI_IMR_IM_Msk </span></div>
|
||
<div class="line"><a id="l06369" name="l06369"></a><span class="lineno"> 6369</span><span class="comment">/******************* Bit definition for EXTI_EMR register *******************/</span></div>
|
||
<div class="line"><a id="l06370" name="l06370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf10ad3eba24a4fadc9e58e9b81c17494"> 6370</a></span><span class="preprocessor">#define EXTI_EMR_MR0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06371" name="l06371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga016c23b6c1164758878753e14201fdbc"> 6371</a></span><span class="preprocessor">#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) </span></div>
|
||
<div class="line"><a id="l06372" name="l06372"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga515c0dc6d2472e06a89e4bb19725e8f3"> 6372</a></span><span class="preprocessor">#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk </span></div>
|
||
<div class="line"><a id="l06373" name="l06373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2891b4a57f827defecd2ebb2cac457b"> 6373</a></span><span class="preprocessor">#define EXTI_EMR_MR1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l06374" name="l06374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa419f81a443fd7eac16ac340c971dc63"> 6374</a></span><span class="preprocessor">#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) </span></div>
|
||
<div class="line"><a id="l06375" name="l06375"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d88e7c10e5985fa425ea7ab4fe4c3e5"> 6375</a></span><span class="preprocessor">#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk </span></div>
|
||
<div class="line"><a id="l06376" name="l06376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09e8782d37f1f13cc30d86c2c3a02576"> 6376</a></span><span class="preprocessor">#define EXTI_EMR_MR2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l06377" name="l06377"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga546cba14a3e8a8172d5652e670ac9ed3"> 6377</a></span><span class="preprocessor">#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) </span></div>
|
||
<div class="line"><a id="l06378" name="l06378"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga460d5d4c0b53bcc04d5804e1204ded21"> 6378</a></span><span class="preprocessor">#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk </span></div>
|
||
<div class="line"><a id="l06379" name="l06379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeac760511bc46050ceb4ece479ead54b"> 6379</a></span><span class="preprocessor">#define EXTI_EMR_MR3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l06380" name="l06380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14290334e49a34a93a3ce229bd5ecf74"> 6380</a></span><span class="preprocessor">#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) </span></div>
|
||
<div class="line"><a id="l06381" name="l06381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73944983ce5a6bde9dc172b4f483898c"> 6381</a></span><span class="preprocessor">#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk </span></div>
|
||
<div class="line"><a id="l06382" name="l06382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a337713821f1ea29a953eee7a2a6d2f"> 6382</a></span><span class="preprocessor">#define EXTI_EMR_MR4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l06383" name="l06383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga478ee1f30cf0d4ef71d512507fcb9cb7"> 6383</a></span><span class="preprocessor">#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) </span></div>
|
||
<div class="line"><a id="l06384" name="l06384"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab80f809ead83e747677a31c80c6aae03"> 6384</a></span><span class="preprocessor">#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk </span></div>
|
||
<div class="line"><a id="l06385" name="l06385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79e7760224986ab31fc06f5d84aa3b7f"> 6385</a></span><span class="preprocessor">#define EXTI_EMR_MR5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l06386" name="l06386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e60a767b0307626c3cd4cbd01d10304"> 6386</a></span><span class="preprocessor">#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) </span></div>
|
||
<div class="line"><a id="l06387" name="l06387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65976f75b703f740dea3562ba3b8db59"> 6387</a></span><span class="preprocessor">#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk </span></div>
|
||
<div class="line"><a id="l06388" name="l06388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3210ae740c584799c07b1e7995e4252"> 6388</a></span><span class="preprocessor">#define EXTI_EMR_MR6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l06389" name="l06389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ca40f93d86d921adecd19479b7ab5c6"> 6389</a></span><span class="preprocessor">#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) </span></div>
|
||
<div class="line"><a id="l06390" name="l06390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea480bd932cd1fa0904f5eb1caee9a12"> 6390</a></span><span class="preprocessor">#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk </span></div>
|
||
<div class="line"><a id="l06391" name="l06391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafafbf203c2dae41123f2eaf6565bb2f4"> 6391</a></span><span class="preprocessor">#define EXTI_EMR_MR7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l06392" name="l06392"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace6755a5d4b361648f0b2c76a0b32282"> 6392</a></span><span class="preprocessor">#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) </span></div>
|
||
<div class="line"><a id="l06393" name="l06393"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbb27ff8664928994ef96f87052d14be"> 6393</a></span><span class="preprocessor">#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk </span></div>
|
||
<div class="line"><a id="l06394" name="l06394"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3349563ae0947ec6c441fe912fb0ede"> 6394</a></span><span class="preprocessor">#define EXTI_EMR_MR8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l06395" name="l06395"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00700896523030015c081b6caa3b72b5"> 6395</a></span><span class="preprocessor">#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) </span></div>
|
||
<div class="line"><a id="l06396" name="l06396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ed4b371da871ffd0cc12ee00147282f"> 6396</a></span><span class="preprocessor">#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk </span></div>
|
||
<div class="line"><a id="l06397" name="l06397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac42d64759efd55a329c207a31c7e3033"> 6397</a></span><span class="preprocessor">#define EXTI_EMR_MR9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l06398" name="l06398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47c54d6a078dcc8b9aec22e327785fdd"> 6398</a></span><span class="preprocessor">#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) </span></div>
|
||
<div class="line"><a id="l06399" name="l06399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga109af342179fff1fccfdde582834867a"> 6399</a></span><span class="preprocessor">#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk </span></div>
|
||
<div class="line"><a id="l06400" name="l06400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaead96297678ea28e56765731de3f8511"> 6400</a></span><span class="preprocessor">#define EXTI_EMR_MR10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l06401" name="l06401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ef7af204b6807cb09f10a11f774889e"> 6401</a></span><span class="preprocessor">#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) </span></div>
|
||
<div class="line"><a id="l06402" name="l06402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf342d34ed1b8e4aa916bf49e30c2a234"> 6402</a></span><span class="preprocessor">#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk </span></div>
|
||
<div class="line"><a id="l06403" name="l06403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga744443e18392efb9d31ceeabc2ba9786"> 6403</a></span><span class="preprocessor">#define EXTI_EMR_MR11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l06404" name="l06404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb1a0c32eb56c845232f07d6e1498633"> 6404</a></span><span class="preprocessor">#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) </span></div>
|
||
<div class="line"><a id="l06405" name="l06405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ec516af1de770c82c3c9c458cbc0172"> 6405</a></span><span class="preprocessor">#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk </span></div>
|
||
<div class="line"><a id="l06406" name="l06406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdf200c3d4abdc44356ff3bfc66c136e"> 6406</a></span><span class="preprocessor">#define EXTI_EMR_MR12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l06407" name="l06407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga988ba6ff638ee9d2bc8a2dec8ef8ea32"> 6407</a></span><span class="preprocessor">#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) </span></div>
|
||
<div class="line"><a id="l06408" name="l06408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15732553e5b0de9f58180a0b024d4cad"> 6408</a></span><span class="preprocessor">#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk </span></div>
|
||
<div class="line"><a id="l06409" name="l06409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacf17cbe9663809770d498fe8d28a6e5"> 6409</a></span><span class="preprocessor">#define EXTI_EMR_MR13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l06410" name="l06410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06991d09dc3fd7373da2375b7e196452"> 6410</a></span><span class="preprocessor">#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) </span></div>
|
||
<div class="line"><a id="l06411" name="l06411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fd2ec6472e46869956acb28f5e1b55f"> 6411</a></span><span class="preprocessor">#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk </span></div>
|
||
<div class="line"><a id="l06412" name="l06412"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0dd6f7d71f00964f930cba3e7fc9d14"> 6412</a></span><span class="preprocessor">#define EXTI_EMR_MR14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l06413" name="l06413"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56cd35406916f89cc00f5c4c153f7f3b"> 6413</a></span><span class="preprocessor">#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) </span></div>
|
||
<div class="line"><a id="l06414" name="l06414"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecf5890ea71eea034ec1cd9e96284f89"> 6414</a></span><span class="preprocessor">#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk </span></div>
|
||
<div class="line"><a id="l06415" name="l06415"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ee0004caa46c2946bb05305cd93baa1"> 6415</a></span><span class="preprocessor">#define EXTI_EMR_MR15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l06416" name="l06416"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa1778406979e6566a10b085f1146a28"> 6416</a></span><span class="preprocessor">#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) </span></div>
|
||
<div class="line"><a id="l06417" name="l06417"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a7bacc32351a36aefcd5614abc76ae3"> 6417</a></span><span class="preprocessor">#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk </span></div>
|
||
<div class="line"><a id="l06418" name="l06418"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga112b3657ea27bac2cfe0676dfa893157"> 6418</a></span><span class="preprocessor">#define EXTI_EMR_MR16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06419" name="l06419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cb43eaaa268ddc9d407c5edcfb05ff4"> 6419</a></span><span class="preprocessor">#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) </span></div>
|
||
<div class="line"><a id="l06420" name="l06420"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34b1a6934265da759bc061f73d5d1374"> 6420</a></span><span class="preprocessor">#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk </span></div>
|
||
<div class="line"><a id="l06421" name="l06421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad853ef0d4af0ed5b68581464a067e1ab"> 6421</a></span><span class="preprocessor">#define EXTI_EMR_MR17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l06422" name="l06422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga889175528233c464f6c0a5f8a901a06d"> 6422</a></span><span class="preprocessor">#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) </span></div>
|
||
<div class="line"><a id="l06423" name="l06423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a30aa20cf475eecf7e15171e83035e4"> 6423</a></span><span class="preprocessor">#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk </span></div>
|
||
<div class="line"><a id="l06424" name="l06424"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7edb364e6ab767686e3c40b177489f00"> 6424</a></span><span class="preprocessor">#define EXTI_EMR_MR18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l06425" name="l06425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e6e89686fa4e8fe58365b684331f398"> 6425</a></span><span class="preprocessor">#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) </span></div>
|
||
<div class="line"><a id="l06426" name="l06426"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25eee729b57b4c78a0613c184fc539e5"> 6426</a></span><span class="preprocessor">#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk </span></div>
|
||
<div class="line"><a id="l06427" name="l06427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8990f832c2588cb200a51d52c5dc8c8a"> 6427</a></span><span class="preprocessor">#define EXTI_EMR_MR19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l06428" name="l06428"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga514f26dc55f8e37ec8ac8bef9dfcadd4"> 6428</a></span><span class="preprocessor">#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) </span></div>
|
||
<div class="line"><a id="l06429" name="l06429"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaeababa85e5ebe6aa93d011d83fd7994"> 6429</a></span><span class="preprocessor">#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk </span></div>
|
||
<div class="line"><a id="l06430" name="l06430"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa67b8f9a15a25b5d2bc93d72082652bd"> 6430</a></span><span class="preprocessor">#define EXTI_EMR_MR20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l06431" name="l06431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae190c58438ea386748cb39b06fc2d62c"> 6431</a></span><span class="preprocessor">#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) </span></div>
|
||
<div class="line"><a id="l06432" name="l06432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga047743f042d00f058dd8cf199c92fbfa"> 6432</a></span><span class="preprocessor">#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk </span></div>
|
||
<div class="line"><a id="l06433" name="l06433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75a62823a85e5c8543646c7c6b273e2f"> 6433</a></span><span class="preprocessor">#define EXTI_EMR_MR21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l06434" name="l06434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga525d06c52556b824cbf29d85a8925532"> 6434</a></span><span class="preprocessor">#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) </span></div>
|
||
<div class="line"><a id="l06435" name="l06435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga935956e41524c1f96d208f63a699377a"> 6435</a></span><span class="preprocessor">#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk </span></div>
|
||
<div class="line"><a id="l06436" name="l06436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae52ca7f79c4b6092d6e2b781f0355bd8"> 6436</a></span><span class="preprocessor">#define EXTI_EMR_MR22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l06437" name="l06437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79c121c40bb976f66094ced0a851419a"> 6437</a></span><span class="preprocessor">#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) </span></div>
|
||
<div class="line"><a id="l06438" name="l06438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fbc202d80be3899d867a0b74abad813"> 6438</a></span><span class="preprocessor">#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk </span></div>
|
||
<div class="line"><a id="l06440" name="l06440"></a><span class="lineno"> 6440</span><span class="comment">/* Reference Defines */</span></div>
|
||
<div class="line"><a id="l06441" name="l06441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf972d7547ed83843150667c301a9d348"> 6441</a></span><span class="preprocessor">#define EXTI_EMR_EM0 EXTI_EMR_MR0</span></div>
|
||
<div class="line"><a id="l06442" name="l06442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07843e6ff5b4ddd02bcf6c66a08cac93"> 6442</a></span><span class="preprocessor">#define EXTI_EMR_EM1 EXTI_EMR_MR1</span></div>
|
||
<div class="line"><a id="l06443" name="l06443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga703c31569533b3b6d76f99da69b4d168"> 6443</a></span><span class="preprocessor">#define EXTI_EMR_EM2 EXTI_EMR_MR2</span></div>
|
||
<div class="line"><a id="l06444" name="l06444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f2bd51b6a0981492a29436ef2b53344"> 6444</a></span><span class="preprocessor">#define EXTI_EMR_EM3 EXTI_EMR_MR3</span></div>
|
||
<div class="line"><a id="l06445" name="l06445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a3f176db76b4eb2cc1400f76afc967a"> 6445</a></span><span class="preprocessor">#define EXTI_EMR_EM4 EXTI_EMR_MR4</span></div>
|
||
<div class="line"><a id="l06446" name="l06446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc0210d29dceb5682d01786b6fcf47fe"> 6446</a></span><span class="preprocessor">#define EXTI_EMR_EM5 EXTI_EMR_MR5</span></div>
|
||
<div class="line"><a id="l06447" name="l06447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c05702eec349cbbcce9b7bc825e2fd8"> 6447</a></span><span class="preprocessor">#define EXTI_EMR_EM6 EXTI_EMR_MR6</span></div>
|
||
<div class="line"><a id="l06448" name="l06448"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf04b9ef7548fb0564beae69739bdea72"> 6448</a></span><span class="preprocessor">#define EXTI_EMR_EM7 EXTI_EMR_MR7</span></div>
|
||
<div class="line"><a id="l06449" name="l06449"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7af57b60f4623e5a65011519dd707991"> 6449</a></span><span class="preprocessor">#define EXTI_EMR_EM8 EXTI_EMR_MR8</span></div>
|
||
<div class="line"><a id="l06450" name="l06450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3757f0da147b7bb49719cb69096b5bc7"> 6450</a></span><span class="preprocessor">#define EXTI_EMR_EM9 EXTI_EMR_MR9</span></div>
|
||
<div class="line"><a id="l06451" name="l06451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad548185c3c99b69f3eaec50067999112"> 6451</a></span><span class="preprocessor">#define EXTI_EMR_EM10 EXTI_EMR_MR10</span></div>
|
||
<div class="line"><a id="l06452" name="l06452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5d0782c45b8b0951c8bbb5e7037a52b"> 6452</a></span><span class="preprocessor">#define EXTI_EMR_EM11 EXTI_EMR_MR11</span></div>
|
||
<div class="line"><a id="l06453" name="l06453"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef9eaec30663289e66b9d9b40682910f"> 6453</a></span><span class="preprocessor">#define EXTI_EMR_EM12 EXTI_EMR_MR12</span></div>
|
||
<div class="line"><a id="l06454" name="l06454"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2fc88afc4ba8231f4368527cc983d50"> 6454</a></span><span class="preprocessor">#define EXTI_EMR_EM13 EXTI_EMR_MR13</span></div>
|
||
<div class="line"><a id="l06455" name="l06455"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf3c10c55ef88bb255f899d0d0939c98"> 6455</a></span><span class="preprocessor">#define EXTI_EMR_EM14 EXTI_EMR_MR14</span></div>
|
||
<div class="line"><a id="l06456" name="l06456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3690bd10db8f6505368f84d1d360d83"> 6456</a></span><span class="preprocessor">#define EXTI_EMR_EM15 EXTI_EMR_MR15</span></div>
|
||
<div class="line"><a id="l06457" name="l06457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadea424b2e5e1e8733e5f8ba76b16c6c"> 6457</a></span><span class="preprocessor">#define EXTI_EMR_EM16 EXTI_EMR_MR16</span></div>
|
||
<div class="line"><a id="l06458" name="l06458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f640eaa67ff0f9e3e849fdc65f7f34e"> 6458</a></span><span class="preprocessor">#define EXTI_EMR_EM17 EXTI_EMR_MR17</span></div>
|
||
<div class="line"><a id="l06459" name="l06459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7162c4422ad98bec692f15dda4e011eb"> 6459</a></span><span class="preprocessor">#define EXTI_EMR_EM18 EXTI_EMR_MR18</span></div>
|
||
<div class="line"><a id="l06460" name="l06460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96076632bf23a1dfb53cfada4008d7b3"> 6460</a></span><span class="preprocessor">#define EXTI_EMR_EM19 EXTI_EMR_MR19</span></div>
|
||
<div class="line"><a id="l06461" name="l06461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a88ab99418d93b7277f19736c14c6c2"> 6461</a></span><span class="preprocessor">#define EXTI_EMR_EM20 EXTI_EMR_MR20</span></div>
|
||
<div class="line"><a id="l06462" name="l06462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf17512ecb4d8572e8b73ab1a427fd500"> 6462</a></span><span class="preprocessor">#define EXTI_EMR_EM21 EXTI_EMR_MR21</span></div>
|
||
<div class="line"><a id="l06463" name="l06463"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31b9e9ec368a547f58ab7f6359c58bdf"> 6463</a></span><span class="preprocessor">#define EXTI_EMR_EM22 EXTI_EMR_MR22</span></div>
|
||
<div class="line"><a id="l06464" name="l06464"></a><span class="lineno"> 6464</span> </div>
|
||
<div class="line"><a id="l06465" name="l06465"></a><span class="lineno"> 6465</span><span class="comment">/****************** Bit definition for EXTI_RTSR register *******************/</span></div>
|
||
<div class="line"><a id="l06466" name="l06466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa359160d5aba50c4aff40330fd99d426"> 6466</a></span><span class="preprocessor">#define EXTI_RTSR_TR0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06467" name="l06467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b3f74a67ed2871290e5cee5ec27e487"> 6467</a></span><span class="preprocessor">#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) </span></div>
|
||
<div class="line"><a id="l06468" name="l06468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb1823a87cd797a6066681a3256cecc6"> 6468</a></span><span class="preprocessor">#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk </span></div>
|
||
<div class="line"><a id="l06469" name="l06469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga099233be3061fa5c0e44cbf3e20b6394"> 6469</a></span><span class="preprocessor">#define EXTI_RTSR_TR1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l06470" name="l06470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57ba4871b93492e5e8c846f2833f9da1"> 6470</a></span><span class="preprocessor">#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) </span></div>
|
||
<div class="line"><a id="l06471" name="l06471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c42cc3763c52d1061b32219fc441566"> 6471</a></span><span class="preprocessor">#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk </span></div>
|
||
<div class="line"><a id="l06472" name="l06472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22b2187bec09d19b2b79382c25ff3b4b"> 6472</a></span><span class="preprocessor">#define EXTI_RTSR_TR2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l06473" name="l06473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbecd9a805326155030f357bc2d70046"> 6473</a></span><span class="preprocessor">#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) </span></div>
|
||
<div class="line"><a id="l06474" name="l06474"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c073b519f09b130e4ab4039823e290c"> 6474</a></span><span class="preprocessor">#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk </span></div>
|
||
<div class="line"><a id="l06475" name="l06475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeae95954e4c5e25f225d3cad0e2b2362"> 6475</a></span><span class="preprocessor">#define EXTI_RTSR_TR3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l06476" name="l06476"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga560d856b177ddb7b90e101caf3ce66be"> 6476</a></span><span class="preprocessor">#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) </span></div>
|
||
<div class="line"><a id="l06477" name="l06477"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga090f295579a774c215585a55e5066b11"> 6477</a></span><span class="preprocessor">#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk </span></div>
|
||
<div class="line"><a id="l06478" name="l06478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa95865d62fde25381efad4f0c38cd8bd"> 6478</a></span><span class="preprocessor">#define EXTI_RTSR_TR4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l06479" name="l06479"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga795eff3140a1d0c0e1fcfc03b2fa5860"> 6479</a></span><span class="preprocessor">#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) </span></div>
|
||
<div class="line"><a id="l06480" name="l06480"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabce4722e99e3f44d40bfb6afb63444cc"> 6480</a></span><span class="preprocessor">#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk </span></div>
|
||
<div class="line"><a id="l06481" name="l06481"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29eade4e6218042bad165fd8cb162662"> 6481</a></span><span class="preprocessor">#define EXTI_RTSR_TR5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l06482" name="l06482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65a7c4c35c85b3e922e1df8447dd8e6d"> 6482</a></span><span class="preprocessor">#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) </span></div>
|
||
<div class="line"><a id="l06483" name="l06483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac57b970ebc88f7bb015119ece9dd32de"> 6483</a></span><span class="preprocessor">#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk </span></div>
|
||
<div class="line"><a id="l06484" name="l06484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a5fd949f067c605127932367ba4dad5"> 6484</a></span><span class="preprocessor">#define EXTI_RTSR_TR6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l06485" name="l06485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85d1a629b7cde96375b82803c46cfcb4"> 6485</a></span><span class="preprocessor">#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) </span></div>
|
||
<div class="line"><a id="l06486" name="l06486"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccc2212ce653d34cf48446ae0a68bed6"> 6486</a></span><span class="preprocessor">#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk </span></div>
|
||
<div class="line"><a id="l06487" name="l06487"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79f320ed539b225c1e4f50e3cfb43100"> 6487</a></span><span class="preprocessor">#define EXTI_RTSR_TR7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l06488" name="l06488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbc9d6a9f75fdff045e4806edad97b47"> 6488</a></span><span class="preprocessor">#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) </span></div>
|
||
<div class="line"><a id="l06489" name="l06489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad380a0bc59524f4a0846a0b91d3c65c1"> 6489</a></span><span class="preprocessor">#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk </span></div>
|
||
<div class="line"><a id="l06490" name="l06490"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f9bcf9229eced0f5101842fd9585e40"> 6490</a></span><span class="preprocessor">#define EXTI_RTSR_TR8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l06491" name="l06491"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16c3b77b33079caf74151ade9fbc3b82"> 6491</a></span><span class="preprocessor">#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) </span></div>
|
||
<div class="line"><a id="l06492" name="l06492"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26cd6a5115b0bbe113f39545bff1ee39"> 6492</a></span><span class="preprocessor">#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk </span></div>
|
||
<div class="line"><a id="l06493" name="l06493"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f3c856ba7076de4742cea9494d2d97b"> 6493</a></span><span class="preprocessor">#define EXTI_RTSR_TR9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l06494" name="l06494"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga394b28a010f7937178112dd11c7edf7b"> 6494</a></span><span class="preprocessor">#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) </span></div>
|
||
<div class="line"><a id="l06495" name="l06495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3127246b2db3571b00c6af2453941d17"> 6495</a></span><span class="preprocessor">#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk </span></div>
|
||
<div class="line"><a id="l06496" name="l06496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf19c55236009d4d88273be1fe6d17b69"> 6496</a></span><span class="preprocessor">#define EXTI_RTSR_TR10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l06497" name="l06497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12717df4fef207dd689f240bbb23cedf"> 6497</a></span><span class="preprocessor">#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) </span></div>
|
||
<div class="line"><a id="l06498" name="l06498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa29df7ddbd067889992eb60ecddce0e4"> 6498</a></span><span class="preprocessor">#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk </span></div>
|
||
<div class="line"><a id="l06499" name="l06499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f11477d08556852c4cf210f75d11920"> 6499</a></span><span class="preprocessor">#define EXTI_RTSR_TR11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l06500" name="l06500"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36a3f679be0d89926b127c4b293111e2"> 6500</a></span><span class="preprocessor">#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) </span></div>
|
||
<div class="line"><a id="l06501" name="l06501"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cf7a92cdb61b3f8cf6eec9513317ab7"> 6501</a></span><span class="preprocessor">#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk </span></div>
|
||
<div class="line"><a id="l06502" name="l06502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8b0314682ff50f85bd8d5570fb6935a"> 6502</a></span><span class="preprocessor">#define EXTI_RTSR_TR12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l06503" name="l06503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4507125ae8a435b97fe643f73e6492e"> 6503</a></span><span class="preprocessor">#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) </span></div>
|
||
<div class="line"><a id="l06504" name="l06504"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0423be12bfb13f34eec9656d6d274e04"> 6504</a></span><span class="preprocessor">#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk </span></div>
|
||
<div class="line"><a id="l06505" name="l06505"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20176d8fa4181b22a833e1598e96b153"> 6505</a></span><span class="preprocessor">#define EXTI_RTSR_TR13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l06506" name="l06506"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga799f99b4edc9604b38ab1f12e0cf9cae"> 6506</a></span><span class="preprocessor">#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) </span></div>
|
||
<div class="line"><a id="l06507" name="l06507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d5ef451fd76dc0fa9c76d7c520d8f12"> 6507</a></span><span class="preprocessor">#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk </span></div>
|
||
<div class="line"><a id="l06508" name="l06508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e76cfdc7657907d423ba90dcac7bc90"> 6508</a></span><span class="preprocessor">#define EXTI_RTSR_TR14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l06509" name="l06509"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42533490cce0d8d3ff55a2d6ad8c24ee"> 6509</a></span><span class="preprocessor">#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) </span></div>
|
||
<div class="line"><a id="l06510" name="l06510"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95b0d883fa0fbc49105bda5596463cda"> 6510</a></span><span class="preprocessor">#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk </span></div>
|
||
<div class="line"><a id="l06511" name="l06511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa62a698b0b47384cd72f49ebb9f17f4c"> 6511</a></span><span class="preprocessor">#define EXTI_RTSR_TR15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l06512" name="l06512"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ffbcdf64f7de2427560316706ddc8c1"> 6512</a></span><span class="preprocessor">#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) </span></div>
|
||
<div class="line"><a id="l06513" name="l06513"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4fe54b09102a18676829c0bafb0aead2"> 6513</a></span><span class="preprocessor">#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk </span></div>
|
||
<div class="line"><a id="l06514" name="l06514"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c280314b145321c6a62ce2764d1fd59"> 6514</a></span><span class="preprocessor">#define EXTI_RTSR_TR16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06515" name="l06515"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad883a3a53902664492c684a6dd435d33"> 6515</a></span><span class="preprocessor">#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) </span></div>
|
||
<div class="line"><a id="l06516" name="l06516"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8e4fb52990f0fa3fb9bed5b74f1a589"> 6516</a></span><span class="preprocessor">#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk </span></div>
|
||
<div class="line"><a id="l06517" name="l06517"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47fa1d5d96ea124413c3b81b9c10f75f"> 6517</a></span><span class="preprocessor">#define EXTI_RTSR_TR17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l06518" name="l06518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42283a804716a4de1910afd032b87681"> 6518</a></span><span class="preprocessor">#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) </span></div>
|
||
<div class="line"><a id="l06519" name="l06519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0a8fcb63516a4ed0d91b556f696f806"> 6519</a></span><span class="preprocessor">#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk </span></div>
|
||
<div class="line"><a id="l06520" name="l06520"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49afa76eab5b3a7d5e5640fced73047c"> 6520</a></span><span class="preprocessor">#define EXTI_RTSR_TR18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l06521" name="l06521"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga708076360f04650ae4bfdd6695caa617"> 6521</a></span><span class="preprocessor">#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) </span></div>
|
||
<div class="line"><a id="l06522" name="l06522"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca4223b8c4bc8726ac96ec64837f7b62"> 6522</a></span><span class="preprocessor">#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk </span></div>
|
||
<div class="line"><a id="l06523" name="l06523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef9bfa9cb8df10ec1e3c2dd50235231c"> 6523</a></span><span class="preprocessor">#define EXTI_RTSR_TR19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l06524" name="l06524"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab40d59af38c6adbe9621b8ab68dbdbe"> 6524</a></span><span class="preprocessor">#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) </span></div>
|
||
<div class="line"><a id="l06525" name="l06525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40a722b0c36e832f619b2136f1510b3e"> 6525</a></span><span class="preprocessor">#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk </span></div>
|
||
<div class="line"><a id="l06526" name="l06526"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga825c9ea20abb9a733bc90b94440fbc63"> 6526</a></span><span class="preprocessor">#define EXTI_RTSR_TR20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l06527" name="l06527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3497416ddbe940f3f87bdbe94dcb423"> 6527</a></span><span class="preprocessor">#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) </span></div>
|
||
<div class="line"><a id="l06528" name="l06528"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga076319b89121213ea97b4767182b17bd"> 6528</a></span><span class="preprocessor">#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk </span></div>
|
||
<div class="line"><a id="l06529" name="l06529"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a92f33d68f20f61d92563404305ba35"> 6529</a></span><span class="preprocessor">#define EXTI_RTSR_TR21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l06530" name="l06530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0acfd045c5ef66801c4f70a7a529a210"> 6530</a></span><span class="preprocessor">#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) </span></div>
|
||
<div class="line"><a id="l06531" name="l06531"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b1fd6472c3739cb5d21ba25bb6f745d"> 6531</a></span><span class="preprocessor">#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk </span></div>
|
||
<div class="line"><a id="l06532" name="l06532"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9b6c8e3b151388284c11fad135c06f3"> 6532</a></span><span class="preprocessor">#define EXTI_RTSR_TR22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l06533" name="l06533"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcf74a99ed3d1bc23d06f4e6d634b46f"> 6533</a></span><span class="preprocessor">#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) </span></div>
|
||
<div class="line"><a id="l06534" name="l06534"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca577c5c1742e043ed5e0a2ffcc88f82"> 6534</a></span><span class="preprocessor">#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk </span></div>
|
||
<div class="line"><a id="l06536" name="l06536"></a><span class="lineno"> 6536</span><span class="comment">/****************** Bit definition for EXTI_FTSR register *******************/</span></div>
|
||
<div class="line"><a id="l06537" name="l06537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a92993932aa377be10ff0376f600b9f"> 6537</a></span><span class="preprocessor">#define EXTI_FTSR_TR0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06538" name="l06538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fd5afa140faff4e562142dc289387cc"> 6538</a></span><span class="preprocessor">#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) </span></div>
|
||
<div class="line"><a id="l06539" name="l06539"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfb6fa5ae3fcaf08aec6d86c3bfefa4c"> 6539</a></span><span class="preprocessor">#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk </span></div>
|
||
<div class="line"><a id="l06540" name="l06540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf26d85ea048d7c483094a9eebaa7aba"> 6540</a></span><span class="preprocessor">#define EXTI_FTSR_TR1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l06541" name="l06541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01090491a062f3b8b4a80b0b66690ce8"> 6541</a></span><span class="preprocessor">#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) </span></div>
|
||
<div class="line"><a id="l06542" name="l06542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac287be3bd3bad84aed48603dbe8bd4ed"> 6542</a></span><span class="preprocessor">#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk </span></div>
|
||
<div class="line"><a id="l06543" name="l06543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga425e560479e3bcf114aca570bd170079"> 6543</a></span><span class="preprocessor">#define EXTI_FTSR_TR2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l06544" name="l06544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71bfd75475e3d65a3bee0a4ccd41e0e3"> 6544</a></span><span class="preprocessor">#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) </span></div>
|
||
<div class="line"><a id="l06545" name="l06545"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c4503803cbe1933cd35519cfc809041"> 6545</a></span><span class="preprocessor">#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk </span></div>
|
||
<div class="line"><a id="l06546" name="l06546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf7f91925c2ac9c267480ed6b9fc1a04"> 6546</a></span><span class="preprocessor">#define EXTI_FTSR_TR3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l06547" name="l06547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71b35fe3af253035fe6c7a8702ef8e5e"> 6547</a></span><span class="preprocessor">#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) </span></div>
|
||
<div class="line"><a id="l06548" name="l06548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23593d2b8a9ec0147bab28765af30e1f"> 6548</a></span><span class="preprocessor">#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk </span></div>
|
||
<div class="line"><a id="l06549" name="l06549"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa295a76e5ee487856be1dde365373f5d"> 6549</a></span><span class="preprocessor">#define EXTI_FTSR_TR4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l06550" name="l06550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabecb16c1706cb6cad8ec0a8e06ac2475"> 6550</a></span><span class="preprocessor">#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) </span></div>
|
||
<div class="line"><a id="l06551" name="l06551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa77211bfa8f4d77cf373296954dad6b2"> 6551</a></span><span class="preprocessor">#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk </span></div>
|
||
<div class="line"><a id="l06552" name="l06552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f3affd9eee854acf6d5e1d820421532"> 6552</a></span><span class="preprocessor">#define EXTI_FTSR_TR5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l06553" name="l06553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafeffba32b6b0854a232493dc2e2634d4"> 6553</a></span><span class="preprocessor">#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) </span></div>
|
||
<div class="line"><a id="l06554" name="l06554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga903f9b080c5971dd5d7935e5b87886e2"> 6554</a></span><span class="preprocessor">#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk </span></div>
|
||
<div class="line"><a id="l06555" name="l06555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5995bc6ec7301b6623c8014fd9db711"> 6555</a></span><span class="preprocessor">#define EXTI_FTSR_TR6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l06556" name="l06556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6590e0e011792337a19831a0ea2df2c"> 6556</a></span><span class="preprocessor">#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) </span></div>
|
||
<div class="line"><a id="l06557" name="l06557"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8527cce22f69e02a08ed67a67f8e5ca"> 6557</a></span><span class="preprocessor">#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk </span></div>
|
||
<div class="line"><a id="l06558" name="l06558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf100b4a2a76bcfdc3f7d0da8d39cc8b1"> 6558</a></span><span class="preprocessor">#define EXTI_FTSR_TR7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l06559" name="l06559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d1347ed594a5d5bb5e0a69f31cbfb20"> 6559</a></span><span class="preprocessor">#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) </span></div>
|
||
<div class="line"><a id="l06560" name="l06560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf408315e497b902922a9bf40a4c6f567"> 6560</a></span><span class="preprocessor">#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk </span></div>
|
||
<div class="line"><a id="l06561" name="l06561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb1e5c22b9a7b2b53fbcc3d50a7ac80a"> 6561</a></span><span class="preprocessor">#define EXTI_FTSR_TR8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l06562" name="l06562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0b6b9ab34a5724cebedd0ccbf1ad65e"> 6562</a></span><span class="preprocessor">#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) </span></div>
|
||
<div class="line"><a id="l06563" name="l06563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00f1bded4d121e21116627b8e80784fc"> 6563</a></span><span class="preprocessor">#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk </span></div>
|
||
<div class="line"><a id="l06564" name="l06564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga165ac2e2e46e32debc7efd99e258e608"> 6564</a></span><span class="preprocessor">#define EXTI_FTSR_TR9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l06565" name="l06565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga898047db88343aeac8c05f39c4bc63e0"> 6565</a></span><span class="preprocessor">#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) </span></div>
|
||
<div class="line"><a id="l06566" name="l06566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89f0c4de2b6acb75302d206b697f83ef"> 6566</a></span><span class="preprocessor">#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk </span></div>
|
||
<div class="line"><a id="l06567" name="l06567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0592581c7bd1ea908087aa319528fdae"> 6567</a></span><span class="preprocessor">#define EXTI_FTSR_TR10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l06568" name="l06568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e6991a6c2f7e8fd99992d7623a31093"> 6568</a></span><span class="preprocessor">#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) </span></div>
|
||
<div class="line"><a id="l06569" name="l06569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9a2b80699a213f0d2b03658f21ad643"> 6569</a></span><span class="preprocessor">#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk </span></div>
|
||
<div class="line"><a id="l06570" name="l06570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32ce99e8292f13831e1c8eaa79dc3554"> 6570</a></span><span class="preprocessor">#define EXTI_FTSR_TR11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l06571" name="l06571"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac985e7db4d6a853c4411544878fd0551"> 6571</a></span><span class="preprocessor">#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) </span></div>
|
||
<div class="line"><a id="l06572" name="l06572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c74d4d520406a14c517784cdd5fc6ef"> 6572</a></span><span class="preprocessor">#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk </span></div>
|
||
<div class="line"><a id="l06573" name="l06573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49f1f39d43c981697a040fc94abbbfc1"> 6573</a></span><span class="preprocessor">#define EXTI_FTSR_TR12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l06574" name="l06574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f1c99fa4436d7a5fad4632366db4462"> 6574</a></span><span class="preprocessor">#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) </span></div>
|
||
<div class="line"><a id="l06575" name="l06575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3992511ec1785bdf107873b139d74245"> 6575</a></span><span class="preprocessor">#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk </span></div>
|
||
<div class="line"><a id="l06576" name="l06576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd86158859c108fbe911aff6498eb15b"> 6576</a></span><span class="preprocessor">#define EXTI_FTSR_TR13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l06577" name="l06577"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89275d329ff466aee9a8b226376eb9b7"> 6577</a></span><span class="preprocessor">#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) </span></div>
|
||
<div class="line"><a id="l06578" name="l06578"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0714519a1edcba4695f92f1bba70e825"> 6578</a></span><span class="preprocessor">#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk </span></div>
|
||
<div class="line"><a id="l06579" name="l06579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffd9b96b99f65602a7d5285d62b8c0ac"> 6579</a></span><span class="preprocessor">#define EXTI_FTSR_TR14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l06580" name="l06580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e2e56c2bfea3a94e5bc8905b5008dd0"> 6580</a></span><span class="preprocessor">#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) </span></div>
|
||
<div class="line"><a id="l06581" name="l06581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b92577e64a95ef2069f1a56176d35ff"> 6581</a></span><span class="preprocessor">#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk </span></div>
|
||
<div class="line"><a id="l06582" name="l06582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5a3ca20b1ac9fdf5794fe609a3fe333"> 6582</a></span><span class="preprocessor">#define EXTI_FTSR_TR15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l06583" name="l06583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b78c01259464833376dbc4755fefc21"> 6583</a></span><span class="preprocessor">#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) </span></div>
|
||
<div class="line"><a id="l06584" name="l06584"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a6cc515f13ffe1a3620d06fa08addc7"> 6584</a></span><span class="preprocessor">#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk </span></div>
|
||
<div class="line"><a id="l06585" name="l06585"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b123b9f8f09d0d1fcb29f846279ce21"> 6585</a></span><span class="preprocessor">#define EXTI_FTSR_TR16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06586" name="l06586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad43c9167b3d4af750254db5efaf97aa4"> 6586</a></span><span class="preprocessor">#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) </span></div>
|
||
<div class="line"><a id="l06587" name="l06587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1b4b850094ccc48790a1e4616ceebd2"> 6587</a></span><span class="preprocessor">#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk </span></div>
|
||
<div class="line"><a id="l06588" name="l06588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf5a7f78ce681c3f1b7afbaf3471d1f4"> 6588</a></span><span class="preprocessor">#define EXTI_FTSR_TR17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l06589" name="l06589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3170e25ad439045d2372d1e052cea88c"> 6589</a></span><span class="preprocessor">#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) </span></div>
|
||
<div class="line"><a id="l06590" name="l06590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga009e618c9563b3a8dcaec493006115c7"> 6590</a></span><span class="preprocessor">#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk </span></div>
|
||
<div class="line"><a id="l06591" name="l06591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52a49bf16fd86f2e5f0c0cd439be375f"> 6591</a></span><span class="preprocessor">#define EXTI_FTSR_TR18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l06592" name="l06592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac793e138d33f0b8106662bb5783b0eaf"> 6592</a></span><span class="preprocessor">#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) </span></div>
|
||
<div class="line"><a id="l06593" name="l06593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga405285cdc474ee20085b17ef1f61517e"> 6593</a></span><span class="preprocessor">#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk </span></div>
|
||
<div class="line"><a id="l06594" name="l06594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf317413191ad372394192996edebfcb3"> 6594</a></span><span class="preprocessor">#define EXTI_FTSR_TR19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l06595" name="l06595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1a59ec9892e009f734e6c7703af85c4"> 6595</a></span><span class="preprocessor">#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) </span></div>
|
||
<div class="line"><a id="l06596" name="l06596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1277527e2fa727fdec2dcc7a300ea1af"> 6596</a></span><span class="preprocessor">#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk </span></div>
|
||
<div class="line"><a id="l06597" name="l06597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga159e0d936264a23e36e44430355412c3"> 6597</a></span><span class="preprocessor">#define EXTI_FTSR_TR20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l06598" name="l06598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f627753cee5eab2cc5111bc5698fd36"> 6598</a></span><span class="preprocessor">#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) </span></div>
|
||
<div class="line"><a id="l06599" name="l06599"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae185289c161b407cdcd5ca185aca5477"> 6599</a></span><span class="preprocessor">#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk </span></div>
|
||
<div class="line"><a id="l06600" name="l06600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53324986eef8e0f233b9d7c7650f88f8"> 6600</a></span><span class="preprocessor">#define EXTI_FTSR_TR21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l06601" name="l06601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bb39db3d5a47c3e7baf4240b5738064"> 6601</a></span><span class="preprocessor">#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) </span></div>
|
||
<div class="line"><a id="l06602" name="l06602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04957f9a7aa38bc50d6ac9340697a826"> 6602</a></span><span class="preprocessor">#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk </span></div>
|
||
<div class="line"><a id="l06603" name="l06603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf272ea16ee6c30f486255e71179f34d"> 6603</a></span><span class="preprocessor">#define EXTI_FTSR_TR22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l06604" name="l06604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf39fdb81f4c5e0e4a566369b17b1a88a"> 6604</a></span><span class="preprocessor">#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) </span></div>
|
||
<div class="line"><a id="l06605" name="l06605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7931f3a5864584bc80de7ab3455517e"> 6605</a></span><span class="preprocessor">#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk </span></div>
|
||
<div class="line"><a id="l06607" name="l06607"></a><span class="lineno"> 6607</span><span class="comment">/****************** Bit definition for EXTI_SWIER register ******************/</span></div>
|
||
<div class="line"><a id="l06608" name="l06608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47cfabfaaaf3453afad037f2b4ee959d"> 6608</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06609" name="l06609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaded47468bc0aade2a8c36333d64a3fc7"> 6609</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) </span></div>
|
||
<div class="line"><a id="l06610" name="l06610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6df16d2e8010a2897888a4acf19cee3"> 6610</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk </span></div>
|
||
<div class="line"><a id="l06611" name="l06611"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf7afd1d1f63c7a76bae06e5c5d86e96"> 6611</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l06612" name="l06612"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43b28416d9efdd9464c175f594ff0490"> 6612</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) </span></div>
|
||
<div class="line"><a id="l06613" name="l06613"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb0c3fa5a03204d743ae92ff925421ae"> 6613</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk </span></div>
|
||
<div class="line"><a id="l06614" name="l06614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6bc778d2738c9f6b76c560c98c0995c6"> 6614</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l06615" name="l06615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga701fc135a83a7a43ca6a977fa51087e1"> 6615</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) </span></div>
|
||
<div class="line"><a id="l06616" name="l06616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6bea1dbaf71e830dd357135524166f4c"> 6616</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk </span></div>
|
||
<div class="line"><a id="l06617" name="l06617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaadaa259d663aebd65a50639e1907e5c"> 6617</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l06618" name="l06618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1adab50a513d2ffc1c7ec8c245bb4ce"> 6618</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) </span></div>
|
||
<div class="line"><a id="l06619" name="l06619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37395ac6729647ab5ee1fa4ca086c08a"> 6619</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk </span></div>
|
||
<div class="line"><a id="l06620" name="l06620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93c17eacb283557123595fb08107d9f5"> 6620</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l06621" name="l06621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cb85edd29e2bbdbb0ec3021c8f80e72"> 6621</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) </span></div>
|
||
<div class="line"><a id="l06622" name="l06622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab051808f7a1ed9aaf43a3df90fc6a575"> 6622</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk </span></div>
|
||
<div class="line"><a id="l06623" name="l06623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga626a1b735d1a60ffd3490c307dce91e5"> 6623</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l06624" name="l06624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9bb6ac1da4531f229770893e8803226"> 6624</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) </span></div>
|
||
<div class="line"><a id="l06625" name="l06625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5b4ace22acacac13ce106b2063a3977"> 6625</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk </span></div>
|
||
<div class="line"><a id="l06626" name="l06626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac5de035fe3b407ebd937d15b85bb8a6"> 6626</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l06627" name="l06627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga820d4fc8485a8c681dd9deddccf85c64"> 6627</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) </span></div>
|
||
<div class="line"><a id="l06628" name="l06628"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8ad0142288597993852e4cf350f61ed"> 6628</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk </span></div>
|
||
<div class="line"><a id="l06629" name="l06629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d9dd65850bb89ff5205240324494035"> 6629</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l06630" name="l06630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac444748417965f0a263e4a3f99c81c22"> 6630</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) </span></div>
|
||
<div class="line"><a id="l06631" name="l06631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdf8eab3e32cc03ca71f519a9111e28f"> 6631</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk </span></div>
|
||
<div class="line"><a id="l06632" name="l06632"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga606f473204836b050515446b252877c5"> 6632</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l06633" name="l06633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga584d2b8877c26e45231b2194baba055a"> 6633</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) </span></div>
|
||
<div class="line"><a id="l06634" name="l06634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e83a373926804449d500b115e9090ce"> 6634</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk </span></div>
|
||
<div class="line"><a id="l06635" name="l06635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d7f6e0def3861e207f4affc4f9755d4"> 6635</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l06636" name="l06636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b275083074cfd7a32fc9af85b56509b"> 6636</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) </span></div>
|
||
<div class="line"><a id="l06637" name="l06637"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab102aa929ffe463ffe9f2db651704a61"> 6637</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk </span></div>
|
||
<div class="line"><a id="l06638" name="l06638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea5b7316b4b5dde162c9acd4e1d1a441"> 6638</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l06639" name="l06639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64deb2466771c956d1e912ea09166925"> 6639</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) </span></div>
|
||
<div class="line"><a id="l06640" name="l06640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9d8691936b6cd80ff8e18c0bfe271d7"> 6640</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk </span></div>
|
||
<div class="line"><a id="l06641" name="l06641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37276792859bdf50b5bc358b78d4fbbd"> 6641</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l06642" name="l06642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaace4933cca50b04988d34d48c7b659c3"> 6642</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) </span></div>
|
||
<div class="line"><a id="l06643" name="l06643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ab9fea9935608ec8ee7fb1e1ae049e7"> 6643</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk </span></div>
|
||
<div class="line"><a id="l06644" name="l06644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab28ccd43920facdbbb974c9e37c40961"> 6644</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l06645" name="l06645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d4daf940040b81b93f70afed1ec62e1"> 6645</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) </span></div>
|
||
<div class="line"><a id="l06646" name="l06646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d67869db50c848f57633ebf00566539"> 6646</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk </span></div>
|
||
<div class="line"><a id="l06647" name="l06647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73603dbe0418523c2c83957265e7e65d"> 6647</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l06648" name="l06648"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa747f781753f3db0d1731ce24ad4ddd"> 6648</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) </span></div>
|
||
<div class="line"><a id="l06649" name="l06649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga930a1d03fe3c32bd65a336ccee418826"> 6649</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk </span></div>
|
||
<div class="line"><a id="l06650" name="l06650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4295bced15121047e453c21f0b32c4de"> 6650</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l06651" name="l06651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga405d264956ba9e06788545e2ad87413e"> 6651</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) </span></div>
|
||
<div class="line"><a id="l06652" name="l06652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5d645db667cd63d1a9b91963c543a4b"> 6652</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk </span></div>
|
||
<div class="line"><a id="l06653" name="l06653"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe3550ed355b125e7e32503596d47d3b"> 6653</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l06654" name="l06654"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga677582734fb712a69ae2d6fb3a3329b6"> 6654</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) </span></div>
|
||
<div class="line"><a id="l06655" name="l06655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b9e64d5a1779371fa4678713ab18e08"> 6655</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk </span></div>
|
||
<div class="line"><a id="l06656" name="l06656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb2a375858bd09f73db412291d9672c5"> 6656</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06657" name="l06657"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c201ce487fab3e1b835a718ee9f11bf"> 6657</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) </span></div>
|
||
<div class="line"><a id="l06658" name="l06658"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55b528743b11f4ab93ae97ee2e639b5b"> 6658</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk </span></div>
|
||
<div class="line"><a id="l06659" name="l06659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a0e994273bfe6b3bdf630b68c673ce7"> 6659</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l06660" name="l06660"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46bf902143efb4e89c7e20de1ed4f108"> 6660</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) </span></div>
|
||
<div class="line"><a id="l06661" name="l06661"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0da944251419887af3a87c86080fb455"> 6661</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk </span></div>
|
||
<div class="line"><a id="l06662" name="l06662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf33aa36748aefb6e66d4c2094a94518"> 6662</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l06663" name="l06663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9db116e94a090f461d8551591f829002"> 6663</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) </span></div>
|
||
<div class="line"><a id="l06664" name="l06664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab07aefbb7a8a18c9338b49d3b10ff068"> 6664</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk </span></div>
|
||
<div class="line"><a id="l06665" name="l06665"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab87df3a3d69a14c70b19e1d69c00a7c6"> 6665</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l06666" name="l06666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fddcdc43381e5daa122589d1a769c41"> 6666</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) </span></div>
|
||
<div class="line"><a id="l06667" name="l06667"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab7c48ac5522385cdb1d7882985f909b"> 6667</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk </span></div>
|
||
<div class="line"><a id="l06668" name="l06668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2a016281fe0bb15bc0ca4ba9b11f97f"> 6668</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l06669" name="l06669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed39df1c85fd5856af03e80a5f42e445"> 6669</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) </span></div>
|
||
<div class="line"><a id="l06670" name="l06670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac71bf967ecd31eaa57ba4064877a75b"> 6670</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk </span></div>
|
||
<div class="line"><a id="l06671" name="l06671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34163f6b2b814470372c81f5591efc8a"> 6671</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l06672" name="l06672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab53e7b09746e33f833ad4143bfeb4977"> 6672</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) </span></div>
|
||
<div class="line"><a id="l06673" name="l06673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23b409de4bca55f1f16cd309e58e88e6"> 6673</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk </span></div>
|
||
<div class="line"><a id="l06674" name="l06674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaedc6a73eb5e640541c1b13a822a315a"> 6674</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l06675" name="l06675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf58cca6423fc2497df3e6a9ff5942ff3"> 6675</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) </span></div>
|
||
<div class="line"><a id="l06676" name="l06676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6bd7759b8d48c722f05ea3d2e64fc02"> 6676</a></span><span class="preprocessor">#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk </span></div>
|
||
<div class="line"><a id="l06678" name="l06678"></a><span class="lineno"> 6678</span><span class="comment">/******************* Bit definition for EXTI_PR register ********************/</span></div>
|
||
<div class="line"><a id="l06679" name="l06679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad67b1832b8c6ebd37c07d774bf7b79c8"> 6679</a></span><span class="preprocessor">#define EXTI_PR_PR0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06680" name="l06680"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e52c51a9d888231a788288e42bb8596"> 6680</a></span><span class="preprocessor">#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) </span></div>
|
||
<div class="line"><a id="l06681" name="l06681"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6da1c8a465606de1f90a74d369fbf25a"> 6681</a></span><span class="preprocessor">#define EXTI_PR_PR0 EXTI_PR_PR0_Msk </span></div>
|
||
<div class="line"><a id="l06682" name="l06682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7adebcc32984cb835d47179d34206eb"> 6682</a></span><span class="preprocessor">#define EXTI_PR_PR1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l06683" name="l06683"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0ea95730ba8514076cc76945a01d850"> 6683</a></span><span class="preprocessor">#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) </span></div>
|
||
<div class="line"><a id="l06684" name="l06684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b9b5f97edeccf442998a65b19e77f25"> 6684</a></span><span class="preprocessor">#define EXTI_PR_PR1 EXTI_PR_PR1_Msk </span></div>
|
||
<div class="line"><a id="l06685" name="l06685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefa65f5976eeb883b977b391e3fbb690"> 6685</a></span><span class="preprocessor">#define EXTI_PR_PR2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l06686" name="l06686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa105697635cbab9ccf5f96efc9feec0d"> 6686</a></span><span class="preprocessor">#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) </span></div>
|
||
<div class="line"><a id="l06687" name="l06687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga085d2105381752a0aadc9be5a93ea665"> 6687</a></span><span class="preprocessor">#define EXTI_PR_PR2 EXTI_PR_PR2_Msk </span></div>
|
||
<div class="line"><a id="l06688" name="l06688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad56d3f9d10fd4c75bf4ba756e3778ea0"> 6688</a></span><span class="preprocessor">#define EXTI_PR_PR3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l06689" name="l06689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbe8a3ee648b4cf47f51e435b8644cee"> 6689</a></span><span class="preprocessor">#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) </span></div>
|
||
<div class="line"><a id="l06690" name="l06690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga064dab3e0d5689b92125713100555ce0"> 6690</a></span><span class="preprocessor">#define EXTI_PR_PR3 EXTI_PR_PR3_Msk </span></div>
|
||
<div class="line"><a id="l06691" name="l06691"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58443521d982443a49db3fb2c273f5e4"> 6691</a></span><span class="preprocessor">#define EXTI_PR_PR4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l06692" name="l06692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9465307df267001826deb47a946dab61"> 6692</a></span><span class="preprocessor">#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) </span></div>
|
||
<div class="line"><a id="l06693" name="l06693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14f73b3693b3353a006d360cb8fd2ddc"> 6693</a></span><span class="preprocessor">#define EXTI_PR_PR4 EXTI_PR_PR4_Msk </span></div>
|
||
<div class="line"><a id="l06694" name="l06694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab011cd54f79dd8093ed093c53f9a69f5"> 6694</a></span><span class="preprocessor">#define EXTI_PR_PR5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l06695" name="l06695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b096f7d09eed26b05531f8b0dbe239c"> 6695</a></span><span class="preprocessor">#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) </span></div>
|
||
<div class="line"><a id="l06696" name="l06696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga319e167fa6e112061997d9a8d79f02f8"> 6696</a></span><span class="preprocessor">#define EXTI_PR_PR5 EXTI_PR_PR5_Msk </span></div>
|
||
<div class="line"><a id="l06697" name="l06697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga348bfafc8c5751e74b93c27f2ddce116"> 6697</a></span><span class="preprocessor">#define EXTI_PR_PR6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l06698" name="l06698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae216f090307338513e0c48b792ff4380"> 6698</a></span><span class="preprocessor">#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) </span></div>
|
||
<div class="line"><a id="l06699" name="l06699"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6f47cd1f602692258985784ed5e8e76"> 6699</a></span><span class="preprocessor">#define EXTI_PR_PR6 EXTI_PR_PR6_Msk </span></div>
|
||
<div class="line"><a id="l06700" name="l06700"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41fd7463743a65921d47e3e888e22fbf"> 6700</a></span><span class="preprocessor">#define EXTI_PR_PR7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l06701" name="l06701"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81bf1c350de28d01e9d252a2a7907a1c"> 6701</a></span><span class="preprocessor">#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) </span></div>
|
||
<div class="line"><a id="l06702" name="l06702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa17ea7e3fb89e98fd6a232f453fcff9e"> 6702</a></span><span class="preprocessor">#define EXTI_PR_PR7 EXTI_PR_PR7_Msk </span></div>
|
||
<div class="line"><a id="l06703" name="l06703"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06e264ce486fde316beef4d01b07377d"> 6703</a></span><span class="preprocessor">#define EXTI_PR_PR8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l06704" name="l06704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf15f6df00912ea82ed99154c1824543"> 6704</a></span><span class="preprocessor">#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) </span></div>
|
||
<div class="line"><a id="l06705" name="l06705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa82e0dcb4961a32a9b7ebdf30493156d"> 6705</a></span><span class="preprocessor">#define EXTI_PR_PR8 EXTI_PR_PR8_Msk </span></div>
|
||
<div class="line"><a id="l06706" name="l06706"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74df770efeeac2a51b21229994b265e8"> 6706</a></span><span class="preprocessor">#define EXTI_PR_PR9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l06707" name="l06707"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5c48dd0cba2bfc3f1cbae965d145019"> 6707</a></span><span class="preprocessor">#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) </span></div>
|
||
<div class="line"><a id="l06708" name="l06708"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fcc64f03d79af531febc077f45c48eb"> 6708</a></span><span class="preprocessor">#define EXTI_PR_PR9 EXTI_PR_PR9_Msk </span></div>
|
||
<div class="line"><a id="l06709" name="l06709"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f38ede7f65d599654716b9c70119997"> 6709</a></span><span class="preprocessor">#define EXTI_PR_PR10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l06710" name="l06710"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19900075592fba3fc4a6641c5a44a4b4"> 6710</a></span><span class="preprocessor">#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) </span></div>
|
||
<div class="line"><a id="l06711" name="l06711"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ef8e9c691b95763007ed228e98fa108"> 6711</a></span><span class="preprocessor">#define EXTI_PR_PR10 EXTI_PR_PR10_Msk </span></div>
|
||
<div class="line"><a id="l06712" name="l06712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0b7515b407f5831dc120540379ab0ee"> 6712</a></span><span class="preprocessor">#define EXTI_PR_PR11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l06713" name="l06713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80e7dba5b45bb3fa090607a33ea4b4b7"> 6713</a></span><span class="preprocessor">#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) </span></div>
|
||
<div class="line"><a id="l06714" name="l06714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga144f1a41abb7b87a1619c15ba5fb548b"> 6714</a></span><span class="preprocessor">#define EXTI_PR_PR11 EXTI_PR_PR11_Msk </span></div>
|
||
<div class="line"><a id="l06715" name="l06715"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe319cbf2bf25f1854993b7e9a88c02e"> 6715</a></span><span class="preprocessor">#define EXTI_PR_PR12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l06716" name="l06716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a607029be3ca6159090afbf66b84d88"> 6716</a></span><span class="preprocessor">#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) </span></div>
|
||
<div class="line"><a id="l06717" name="l06717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1a68025056b8c84bb13635af5e2a07c"> 6717</a></span><span class="preprocessor">#define EXTI_PR_PR12 EXTI_PR_PR12_Msk </span></div>
|
||
<div class="line"><a id="l06718" name="l06718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa74c6b6143b3874744573c9ab8f30f65"> 6718</a></span><span class="preprocessor">#define EXTI_PR_PR13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l06719" name="l06719"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46b3cd3e008be5d766a085378dbde61e"> 6719</a></span><span class="preprocessor">#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) </span></div>
|
||
<div class="line"><a id="l06720" name="l06720"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3471c79d5b19813785387504a1a5f0c4"> 6720</a></span><span class="preprocessor">#define EXTI_PR_PR13 EXTI_PR_PR13_Msk </span></div>
|
||
<div class="line"><a id="l06721" name="l06721"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada52a67e5e44c06a2e40c3d4c721b345"> 6721</a></span><span class="preprocessor">#define EXTI_PR_PR14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l06722" name="l06722"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga845983f32b8eccfafede2ece6a9371a1"> 6722</a></span><span class="preprocessor">#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) </span></div>
|
||
<div class="line"><a id="l06723" name="l06723"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5396ec2dbbee9d7585224fa12273598"> 6723</a></span><span class="preprocessor">#define EXTI_PR_PR14 EXTI_PR_PR14_Msk </span></div>
|
||
<div class="line"><a id="l06724" name="l06724"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d396fd4e0a34ebb0d44d2eb53daa753"> 6724</a></span><span class="preprocessor">#define EXTI_PR_PR15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l06725" name="l06725"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac665a7df31dbb829ee5e8c92b35d1e94"> 6725</a></span><span class="preprocessor">#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) </span></div>
|
||
<div class="line"><a id="l06726" name="l06726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga149f9d9d6c1aab867734b59db1117c41"> 6726</a></span><span class="preprocessor">#define EXTI_PR_PR15 EXTI_PR_PR15_Msk </span></div>
|
||
<div class="line"><a id="l06727" name="l06727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71810ea68a9e4297e245dacdfe77855a"> 6727</a></span><span class="preprocessor">#define EXTI_PR_PR16_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06728" name="l06728"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1577079526c7f1959e2e0c6c3dd8a4e4"> 6728</a></span><span class="preprocessor">#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) </span></div>
|
||
<div class="line"><a id="l06729" name="l06729"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa47e5b07d5a407198e09f05262f18bba"> 6729</a></span><span class="preprocessor">#define EXTI_PR_PR16 EXTI_PR_PR16_Msk </span></div>
|
||
<div class="line"><a id="l06730" name="l06730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c42d3340997c553862f81db64944af9"> 6730</a></span><span class="preprocessor">#define EXTI_PR_PR17_Pos (17U) </span></div>
|
||
<div class="line"><a id="l06731" name="l06731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60b0021b076cb2e50a546abdc74ff497"> 6731</a></span><span class="preprocessor">#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) </span></div>
|
||
<div class="line"><a id="l06732" name="l06732"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbc7d82eb61e2adf0a955ef0cc97690f"> 6732</a></span><span class="preprocessor">#define EXTI_PR_PR17 EXTI_PR_PR17_Msk </span></div>
|
||
<div class="line"><a id="l06733" name="l06733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65cfa57b6c19a9a31eb05adfbb24399a"> 6733</a></span><span class="preprocessor">#define EXTI_PR_PR18_Pos (18U) </span></div>
|
||
<div class="line"><a id="l06734" name="l06734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09184330e3d3e7839d58dec6b07c284a"> 6734</a></span><span class="preprocessor">#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) </span></div>
|
||
<div class="line"><a id="l06735" name="l06735"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga541810a93fbf4cdd9b39f2717f37240d"> 6735</a></span><span class="preprocessor">#define EXTI_PR_PR18 EXTI_PR_PR18_Msk </span></div>
|
||
<div class="line"><a id="l06736" name="l06736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a38e5f6a0896bb0c6c2f3e32a5d51f8"> 6736</a></span><span class="preprocessor">#define EXTI_PR_PR19_Pos (19U) </span></div>
|
||
<div class="line"><a id="l06737" name="l06737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2b3167c29bb083e4c0e025846069a78"> 6737</a></span><span class="preprocessor">#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) </span></div>
|
||
<div class="line"><a id="l06738" name="l06738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41e43af631a30492e09e5fd5c50f47f5"> 6738</a></span><span class="preprocessor">#define EXTI_PR_PR19 EXTI_PR_PR19_Msk </span></div>
|
||
<div class="line"><a id="l06739" name="l06739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3d5ef04e855f2eb705305eba6cf00b9"> 6739</a></span><span class="preprocessor">#define EXTI_PR_PR20_Pos (20U) </span></div>
|
||
<div class="line"><a id="l06740" name="l06740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac02bf4106a2d978a81fc825c808eace4"> 6740</a></span><span class="preprocessor">#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) </span></div>
|
||
<div class="line"><a id="l06741" name="l06741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39358e6261a245eba447dfc1a1842e32"> 6741</a></span><span class="preprocessor">#define EXTI_PR_PR20 EXTI_PR_PR20_Msk </span></div>
|
||
<div class="line"><a id="l06742" name="l06742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad693094b03aec71eeca641ef0739d950"> 6742</a></span><span class="preprocessor">#define EXTI_PR_PR21_Pos (21U) </span></div>
|
||
<div class="line"><a id="l06743" name="l06743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe3b7c51abb06113eb6b53ca2c963fba"> 6743</a></span><span class="preprocessor">#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) </span></div>
|
||
<div class="line"><a id="l06744" name="l06744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac14b609a68b5c4cb4a20fb24e34954df"> 6744</a></span><span class="preprocessor">#define EXTI_PR_PR21 EXTI_PR_PR21_Msk </span></div>
|
||
<div class="line"><a id="l06745" name="l06745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d26bbce3e69e8c80b67e81db99cc2ff"> 6745</a></span><span class="preprocessor">#define EXTI_PR_PR22_Pos (22U) </span></div>
|
||
<div class="line"><a id="l06746" name="l06746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa13b7a89ed2d6deef9017757d311e52a"> 6746</a></span><span class="preprocessor">#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) </span></div>
|
||
<div class="line"><a id="l06747" name="l06747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8199f21c468deeb2685865c26770ac07"> 6747</a></span><span class="preprocessor">#define EXTI_PR_PR22 EXTI_PR_PR22_Msk </span></div>
|
||
<div class="line"><a id="l06749" name="l06749"></a><span class="lineno"> 6749</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l06750" name="l06750"></a><span class="lineno"> 6750</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l06751" name="l06751"></a><span class="lineno"> 6751</span><span class="comment">/* FLASH */</span></div>
|
||
<div class="line"><a id="l06752" name="l06752"></a><span class="lineno"> 6752</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l06753" name="l06753"></a><span class="lineno"> 6753</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l06754" name="l06754"></a><span class="lineno"> 6754</span><span class="comment">/******************* Bits definition for FLASH_ACR register *****************/</span></div>
|
||
<div class="line"><a id="l06755" name="l06755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd27f57311268ed1ad0ddb1a207ce9a4"> 6755</a></span><span class="preprocessor">#define FLASH_ACR_LATENCY_Pos (0U)</span></div>
|
||
<div class="line"><a id="l06756" name="l06756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdcd07c55bf5197e31d5ad9ab61747a3"> 6756</a></span><span class="preprocessor">#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) </span></div>
|
||
<div class="line"><a id="l06757" name="l06757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef5e44cbb084160a6004ca9951ec7318"> 6757</a></span><span class="preprocessor">#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk</span></div>
|
||
<div class="line"><a id="l06758" name="l06758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga936324709ea40109331b76849da2c8b2"> 6758</a></span><span class="preprocessor">#define FLASH_ACR_LATENCY_0WS 0x00000000U</span></div>
|
||
<div class="line"><a id="l06759" name="l06759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec66af244e6afb5bbf9816d7c76e1621"> 6759</a></span><span class="preprocessor">#define FLASH_ACR_LATENCY_1WS 0x00000001U</span></div>
|
||
<div class="line"><a id="l06760" name="l06760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9b09ca8db6df455d0b8f810f8521257"> 6760</a></span><span class="preprocessor">#define FLASH_ACR_LATENCY_2WS 0x00000002U</span></div>
|
||
<div class="line"><a id="l06761" name="l06761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3437dcee177845a407919d3b2d9bd063"> 6761</a></span><span class="preprocessor">#define FLASH_ACR_LATENCY_3WS 0x00000003U</span></div>
|
||
<div class="line"><a id="l06762" name="l06762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3594f2a9e12213efe75cd7df646e1ad"> 6762</a></span><span class="preprocessor">#define FLASH_ACR_LATENCY_4WS 0x00000004U</span></div>
|
||
<div class="line"><a id="l06763" name="l06763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67e55ca49f028a701d0c81420a6e2918"> 6763</a></span><span class="preprocessor">#define FLASH_ACR_LATENCY_5WS 0x00000005U</span></div>
|
||
<div class="line"><a id="l06764" name="l06764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3019ff197b4fd698e9625c9abb67f4be"> 6764</a></span><span class="preprocessor">#define FLASH_ACR_LATENCY_6WS 0x00000006U</span></div>
|
||
<div class="line"><a id="l06765" name="l06765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa164c6e6fdfcae274a84dc87ca87b95e"> 6765</a></span><span class="preprocessor">#define FLASH_ACR_LATENCY_7WS 0x00000007U</span></div>
|
||
<div class="line"><a id="l06766" name="l06766"></a><span class="lineno"> 6766</span> </div>
|
||
<div class="line"><a id="l06767" name="l06767"></a><span class="lineno"> 6767</span> </div>
|
||
<div class="line"><a id="l06768" name="l06768"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf1b922e6400999bfabcde78d1c6f59b"> 6768</a></span><span class="preprocessor">#define FLASH_ACR_PRFTEN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l06769" name="l06769"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga727504c465ce30a499631159bc419179"> 6769</a></span><span class="preprocessor">#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) </span></div>
|
||
<div class="line"><a id="l06770" name="l06770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga082e7e91fffee86db39676396d01a8e0"> 6770</a></span><span class="preprocessor">#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk </span></div>
|
||
<div class="line"><a id="l06771" name="l06771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2045375967b3774ee2a00f3f3de10ad"> 6771</a></span><span class="preprocessor">#define FLASH_ACR_ICEN_Pos (9U) </span></div>
|
||
<div class="line"><a id="l06772" name="l06772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95b43999203bce2ccdea6eba1f9925b9"> 6772</a></span><span class="preprocessor">#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) </span></div>
|
||
<div class="line"><a id="l06773" name="l06773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51d8b1dd2c46942d377c579a38dce711"> 6773</a></span><span class="preprocessor">#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk </span></div>
|
||
<div class="line"><a id="l06774" name="l06774"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga168563c4043c04251fc1524f6780a18e"> 6774</a></span><span class="preprocessor">#define FLASH_ACR_DCEN_Pos (10U) </span></div>
|
||
<div class="line"><a id="l06775" name="l06775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4d8386ca0c38a2a5546714a068e63d5"> 6775</a></span><span class="preprocessor">#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) </span></div>
|
||
<div class="line"><a id="l06776" name="l06776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a9a5cc3aa05dc62264addab1008c896"> 6776</a></span><span class="preprocessor">#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk </span></div>
|
||
<div class="line"><a id="l06777" name="l06777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a8676f7e028638743d0097921be11e5"> 6777</a></span><span class="preprocessor">#define FLASH_ACR_ICRST_Pos (11U) </span></div>
|
||
<div class="line"><a id="l06778" name="l06778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga009d7ec202f2ec4e6322d6051731dcea"> 6778</a></span><span class="preprocessor">#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) </span></div>
|
||
<div class="line"><a id="l06779" name="l06779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga923ff88475799eea9285f77f5383ced5"> 6779</a></span><span class="preprocessor">#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk </span></div>
|
||
<div class="line"><a id="l06780" name="l06780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab97b6c3668fe60543b9d5a4f14e18f06"> 6780</a></span><span class="preprocessor">#define FLASH_ACR_DCRST_Pos (12U) </span></div>
|
||
<div class="line"><a id="l06781" name="l06781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab292276bf617270acde9e91828cbaede"> 6781</a></span><span class="preprocessor">#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) </span></div>
|
||
<div class="line"><a id="l06782" name="l06782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac53d7c85551a9829014d6027d67ce6c7"> 6782</a></span><span class="preprocessor">#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk </span></div>
|
||
<div class="line"><a id="l06783" name="l06783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa35bb342e6db09c1515b40635275212b"> 6783</a></span><span class="preprocessor">#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U) </span></div>
|
||
<div class="line"><a id="l06784" name="l06784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e53f8ca7c06552c5383884a01908a58"> 6784</a></span><span class="preprocessor">#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) </span></div>
|
||
<div class="line"><a id="l06785" name="l06785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga277876cbec14426a7a70ed6b3ead6d49"> 6785</a></span><span class="preprocessor">#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk </span></div>
|
||
<div class="line"><a id="l06786" name="l06786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c66a942588ae72bc8f5d54bea5e3bf2"> 6786</a></span><span class="preprocessor">#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06787" name="l06787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bb60f05f974d5fa62cea9de4dc907d1"> 6787</a></span><span class="preprocessor">#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) </span></div>
|
||
<div class="line"><a id="l06788" name="l06788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7c5712edb158a725d8647c6af19544e"> 6788</a></span><span class="preprocessor">#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk </span></div>
|
||
<div class="line"><a id="l06789" name="l06789"></a><span class="lineno"> 6789</span> </div>
|
||
<div class="line"><a id="l06790" name="l06790"></a><span class="lineno"> 6790</span><span class="comment">/******************* Bits definition for FLASH_SR register ******************/</span></div>
|
||
<div class="line"><a id="l06791" name="l06791"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2013e875c4c210b820e502feea6c9fb1"> 6791</a></span><span class="preprocessor">#define FLASH_SR_EOP_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06792" name="l06792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga386f68b5d2c3622b29811577932360ed"> 6792</a></span><span class="preprocessor">#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) </span></div>
|
||
<div class="line"><a id="l06793" name="l06793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1301c6b487cfefa247c54a576a0c12b"> 6793</a></span><span class="preprocessor">#define FLASH_SR_EOP FLASH_SR_EOP_Msk </span></div>
|
||
<div class="line"><a id="l06794" name="l06794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4af97243ceb7ddfa34b7c3882c41b306"> 6794</a></span><span class="preprocessor">#define FLASH_SR_SOP_Pos (1U) </span></div>
|
||
<div class="line"><a id="l06795" name="l06795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd0272b01aaf5f6f7d69cd5906f3d755"> 6795</a></span><span class="preprocessor">#define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos) </span></div>
|
||
<div class="line"><a id="l06796" name="l06796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab779aa8b88258e15c183041744a846ff"> 6796</a></span><span class="preprocessor">#define FLASH_SR_SOP FLASH_SR_SOP_Msk </span></div>
|
||
<div class="line"><a id="l06797" name="l06797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace591108151f52fd0f18273c00403b80"> 6797</a></span><span class="preprocessor">#define FLASH_SR_WRPERR_Pos (4U) </span></div>
|
||
<div class="line"><a id="l06798" name="l06798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65a2ec1cfe4fece014bacf2c1332e659"> 6798</a></span><span class="preprocessor">#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) </span></div>
|
||
<div class="line"><a id="l06799" name="l06799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf6f52f59b01530928d747cf32bd4d01"> 6799</a></span><span class="preprocessor">#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk </span></div>
|
||
<div class="line"><a id="l06800" name="l06800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e91ef00a66f31c28b41f990b0a5b57f"> 6800</a></span><span class="preprocessor">#define FLASH_SR_PGAERR_Pos (5U) </span></div>
|
||
<div class="line"><a id="l06801" name="l06801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga433ad5d791f6ffcb202165a0131d00de"> 6801</a></span><span class="preprocessor">#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) </span></div>
|
||
<div class="line"><a id="l06802" name="l06802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac98c2458e114e7f419f3222673878ce0"> 6802</a></span><span class="preprocessor">#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk </span></div>
|
||
<div class="line"><a id="l06803" name="l06803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac07140ebffc87a7d5c0e006e9753bc12"> 6803</a></span><span class="preprocessor">#define FLASH_SR_PGPERR_Pos (6U) </span></div>
|
||
<div class="line"><a id="l06804" name="l06804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6caf6ab98ec1dd59205297dcf582c945"> 6804</a></span><span class="preprocessor">#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos) </span></div>
|
||
<div class="line"><a id="l06805" name="l06805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fd2704724528be959f82089f67e3869"> 6805</a></span><span class="preprocessor">#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk </span></div>
|
||
<div class="line"><a id="l06806" name="l06806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa714dc154587b83701170e6795646f36"> 6806</a></span><span class="preprocessor">#define FLASH_SR_PGSERR_Pos (7U) </span></div>
|
||
<div class="line"><a id="l06807" name="l06807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf315476e1c4d69765908a72e0d1946be"> 6807</a></span><span class="preprocessor">#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) </span></div>
|
||
<div class="line"><a id="l06808" name="l06808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d76ad3629a288bee0136b8b34f274f4"> 6808</a></span><span class="preprocessor">#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk </span></div>
|
||
<div class="line"><a id="l06809" name="l06809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fff488dcd0ba14694a05d8c061441e0"> 6809</a></span><span class="preprocessor">#define FLASH_SR_BSY_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06810" name="l06810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3564806c8fbd6e0b6ddde539c3e37045"> 6810</a></span><span class="preprocessor">#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) </span></div>
|
||
<div class="line"><a id="l06811" name="l06811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b86181a96fd2f1cc3828e9d8d83d368"> 6811</a></span><span class="preprocessor">#define FLASH_SR_BSY FLASH_SR_BSY_Msk </span></div>
|
||
<div class="line"><a id="l06812" name="l06812"></a><span class="lineno"> 6812</span> </div>
|
||
<div class="line"><a id="l06813" name="l06813"></a><span class="lineno"> 6813</span><span class="comment">/******************* Bits definition for FLASH_CR register ******************/</span></div>
|
||
<div class="line"><a id="l06814" name="l06814"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a5addaa1ee5049b0c99023d91dd4a70"> 6814</a></span><span class="preprocessor">#define FLASH_CR_PG_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06815" name="l06815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8bc468bdb6b58e9db0f91752dea96b1a"> 6815</a></span><span class="preprocessor">#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) </span></div>
|
||
<div class="line"><a id="l06816" name="l06816"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47754b39bd7a7c79c251d6376f97f661"> 6816</a></span><span class="preprocessor">#define FLASH_CR_PG FLASH_CR_PG_Msk </span></div>
|
||
<div class="line"><a id="l06817" name="l06817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b8aa46dd6b3ec7eac3981210966235e"> 6817</a></span><span class="preprocessor">#define FLASH_CR_SER_Pos (1U) </span></div>
|
||
<div class="line"><a id="l06818" name="l06818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6479f79813e55ff738208840dd3abfeb"> 6818</a></span><span class="preprocessor">#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) </span></div>
|
||
<div class="line"><a id="l06819" name="l06819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0e561d67b381c4bd8714cd6a9c15f56"> 6819</a></span><span class="preprocessor">#define FLASH_CR_SER FLASH_CR_SER_Msk </span></div>
|
||
<div class="line"><a id="l06820" name="l06820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0627fa13f9e31a0250d6917e4d2ecbc1"> 6820</a></span><span class="preprocessor">#define FLASH_CR_MER_Pos (2U) </span></div>
|
||
<div class="line"><a id="l06821" name="l06821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f1b8b67a6173c11f950347f09e63888"> 6821</a></span><span class="preprocessor">#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) </span></div>
|
||
<div class="line"><a id="l06822" name="l06822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a287aa5a625125301306a02fb69c53a"> 6822</a></span><span class="preprocessor">#define FLASH_CR_MER FLASH_CR_MER_Msk </span></div>
|
||
<div class="line"><a id="l06823" name="l06823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab657376caa866d7aebcb539c12d943bb"> 6823</a></span><span class="preprocessor">#define FLASH_CR_SNB_Pos (3U) </span></div>
|
||
<div class="line"><a id="l06824" name="l06824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67d162f1700e851ee1f94a541f761c7d"> 6824</a></span><span class="preprocessor">#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) </span></div>
|
||
<div class="line"><a id="l06825" name="l06825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4375b021000bd1acdecab7f72240f57d"> 6825</a></span><span class="preprocessor">#define FLASH_CR_SNB FLASH_CR_SNB_Msk </span></div>
|
||
<div class="line"><a id="l06826" name="l06826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9937f2386c7127f9855f68e2ec121448"> 6826</a></span><span class="preprocessor">#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) </span></div>
|
||
<div class="line"><a id="l06827" name="l06827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa70c4abfe231ffeab3f34a97c171427b"> 6827</a></span><span class="preprocessor">#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) </span></div>
|
||
<div class="line"><a id="l06828" name="l06828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23c44361d3aaf062fc6b288b1d44b988"> 6828</a></span><span class="preprocessor">#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) </span></div>
|
||
<div class="line"><a id="l06829" name="l06829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga417708b5b7aabfe219fb671f2955af31"> 6829</a></span><span class="preprocessor">#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) </span></div>
|
||
<div class="line"><a id="l06830" name="l06830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga734972442e2704a86bfb69c5707b33a1"> 6830</a></span><span class="preprocessor">#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) </span></div>
|
||
<div class="line"><a id="l06831" name="l06831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0242af989594850be999d37750caa5c5"> 6831</a></span><span class="preprocessor">#define FLASH_CR_PSIZE_Pos (8U) </span></div>
|
||
<div class="line"><a id="l06832" name="l06832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f6b8486e155b78a7617fe046bade831"> 6832</a></span><span class="preprocessor">#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l06833" name="l06833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga948ebea4921be9f981292b6e6733b00f"> 6833</a></span><span class="preprocessor">#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk </span></div>
|
||
<div class="line"><a id="l06834" name="l06834"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadbc673f47f1ed33ca4144e9eee91ad6"> 6834</a></span><span class="preprocessor">#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l06835" name="l06835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga196dca8b265486bf05782e6bbe81d854"> 6835</a></span><span class="preprocessor">#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l06836" name="l06836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7925df36a4d15838d8cb457f671e7532"> 6836</a></span><span class="preprocessor">#define FLASH_CR_STRT_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06837" name="l06837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ce773f84ec7782c408a8d9cef09f496"> 6837</a></span><span class="preprocessor">#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) </span></div>
|
||
<div class="line"><a id="l06838" name="l06838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe4dd28134f93f52b1d4ec5b36a99864"> 6838</a></span><span class="preprocessor">#define FLASH_CR_STRT FLASH_CR_STRT_Msk </span></div>
|
||
<div class="line"><a id="l06839" name="l06839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e162a7fa45cb85ba0df0942a2519478"> 6839</a></span><span class="preprocessor">#define FLASH_CR_EOPIE_Pos (24U) </span></div>
|
||
<div class="line"><a id="l06840" name="l06840"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0866e1ddcbf0e7a895ca9a4794db4bd"> 6840</a></span><span class="preprocessor">#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) </span></div>
|
||
<div class="line"><a id="l06841" name="l06841"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9e69856f654ec430a42791a34799db0"> 6841</a></span><span class="preprocessor">#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk </span></div>
|
||
<div class="line"><a id="l06842" name="l06842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab075c4eeff509cfe0f34040c29edfb05"> 6842</a></span><span class="preprocessor">#define FLASH_CR_ERRIE_Pos (25U)</span></div>
|
||
<div class="line"><a id="l06843" name="l06843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9f1e535996ab89de1ca07a32a11e526"> 6843</a></span><span class="preprocessor">#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)</span></div>
|
||
<div class="line"><a id="l06844" name="l06844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga930897cecdaa9dbef8c640b84acbd8c2"> 6844</a></span><span class="preprocessor">#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk</span></div>
|
||
<div class="line"><a id="l06845" name="l06845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa74509adc6db3db66803966b25423cae"> 6845</a></span><span class="preprocessor">#define FLASH_CR_LOCK_Pos (31U) </span></div>
|
||
<div class="line"><a id="l06846" name="l06846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7954a2bc4dd25495e8c164454817a966"> 6846</a></span><span class="preprocessor">#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) </span></div>
|
||
<div class="line"><a id="l06847" name="l06847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab25f1fa4127fa015361b61a6f3180784"> 6847</a></span><span class="preprocessor">#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk </span></div>
|
||
<div class="line"><a id="l06848" name="l06848"></a><span class="lineno"> 6848</span> </div>
|
||
<div class="line"><a id="l06849" name="l06849"></a><span class="lineno"> 6849</span><span class="comment">/******************* Bits definition for FLASH_OPTCR register ***************/</span></div>
|
||
<div class="line"><a id="l06850" name="l06850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf12a3ac81fbc65a12d83ed398b6ef28"> 6850</a></span><span class="preprocessor">#define FLASH_OPTCR_OPTLOCK_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06851" name="l06851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4fb506626a51c8b29c864573f6c2835"> 6851</a></span><span class="preprocessor">#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) </span></div>
|
||
<div class="line"><a id="l06852" name="l06852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c1da080e341fca41ce7f7d661cc4904"> 6852</a></span><span class="preprocessor">#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk </span></div>
|
||
<div class="line"><a id="l06853" name="l06853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83a4a90f9f76098cdca63d9931bc79d7"> 6853</a></span><span class="preprocessor">#define FLASH_OPTCR_OPTSTRT_Pos (1U) </span></div>
|
||
<div class="line"><a id="l06854" name="l06854"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf93699ed3b5dc9bb83833f2bf1610b11"> 6854</a></span><span class="preprocessor">#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) </span></div>
|
||
<div class="line"><a id="l06855" name="l06855"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0858d561d4790c86b64a60204a09a3b5"> 6855</a></span><span class="preprocessor">#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk </span></div>
|
||
<div class="line"><a id="l06856" name="l06856"></a><span class="lineno"> 6856</span> </div>
|
||
<div class="line"><a id="l06857" name="l06857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf842eaac29efd86925c9431a8eb99b27"> 6857</a></span><span class="preprocessor">#define FLASH_OPTCR_BOR_LEV_0 0x00000004U </span></div>
|
||
<div class="line"><a id="l06858" name="l06858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2971824f63351f09ad3db521d6a5b212"> 6858</a></span><span class="preprocessor">#define FLASH_OPTCR_BOR_LEV_1 0x00000008U </span></div>
|
||
<div class="line"><a id="l06859" name="l06859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga664b8edfc20be3140e72411130fd9c2c"> 6859</a></span><span class="preprocessor">#define FLASH_OPTCR_BOR_LEV_Pos (2U) </span></div>
|
||
<div class="line"><a id="l06860" name="l06860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bbb4145b4e60c9aba5a41b52ca7de42"> 6860</a></span><span class="preprocessor">#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos) </span></div>
|
||
<div class="line"><a id="l06861" name="l06861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62cadc42caa03753ab8733da2b957ead"> 6861</a></span><span class="preprocessor">#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk </span></div>
|
||
<div class="line"><a id="l06862" name="l06862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga135a90817c765ba7f80a463cd48b8dd2"> 6862</a></span><span class="preprocessor">#define FLASH_OPTCR_WDG_SW_Pos (5U) </span></div>
|
||
<div class="line"><a id="l06863" name="l06863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a820fdb171a46fddcc020aa769a7b87"> 6863</a></span><span class="preprocessor">#define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos) </span></div>
|
||
<div class="line"><a id="l06864" name="l06864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf38cbe85e3a2c30dbe6ccb3b3e636504"> 6864</a></span><span class="preprocessor">#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk </span></div>
|
||
<div class="line"><a id="l06865" name="l06865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0df94d9b6c39215d53adeb12124ffe2a"> 6865</a></span><span class="preprocessor">#define FLASH_OPTCR_nRST_STOP_Pos (6U) </span></div>
|
||
<div class="line"><a id="l06866" name="l06866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga203b0fae4100b7cb942d38ab22459793"> 6866</a></span><span class="preprocessor">#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l06867" name="l06867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12b1ec98e521815433b3eec1e4136fd2"> 6867</a></span><span class="preprocessor">#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk </span></div>
|
||
<div class="line"><a id="l06868" name="l06868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1240d379a33450a4a5fd676f13cd4db2"> 6868</a></span><span class="preprocessor">#define FLASH_OPTCR_nRST_STDBY_Pos (7U) </span></div>
|
||
<div class="line"><a id="l06869" name="l06869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02c3e4e48e88b93407109e671e8aaf0e"> 6869</a></span><span class="preprocessor">#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos) </span></div>
|
||
<div class="line"><a id="l06870" name="l06870"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82102d640fe1d3e6e9f9c6a3e0adb56f"> 6870</a></span><span class="preprocessor">#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk </span></div>
|
||
<div class="line"><a id="l06871" name="l06871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e06896e31b4fbbbffaa2865c16a607e"> 6871</a></span><span class="preprocessor">#define FLASH_OPTCR_RDP_Pos (8U) </span></div>
|
||
<div class="line"><a id="l06872" name="l06872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bc4c590daea652ce57f3a44a6a67d84"> 6872</a></span><span class="preprocessor">#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos) </span></div>
|
||
<div class="line"><a id="l06873" name="l06873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa180c5732c34b271618aa58695c8ff5a"> 6873</a></span><span class="preprocessor">#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk </span></div>
|
||
<div class="line"><a id="l06874" name="l06874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd79ca0fb8dd121074f40b83b2313d12"> 6874</a></span><span class="preprocessor">#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos) </span></div>
|
||
<div class="line"><a id="l06875" name="l06875"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga935fe4b6ea955b3dc26110f19e894e60"> 6875</a></span><span class="preprocessor">#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos) </span></div>
|
||
<div class="line"><a id="l06876" name="l06876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02ba844244e374fe8105a7cad59ad523"> 6876</a></span><span class="preprocessor">#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos) </span></div>
|
||
<div class="line"><a id="l06877" name="l06877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga844d4d62b7de476c90dd5f971f5e9041"> 6877</a></span><span class="preprocessor">#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos) </span></div>
|
||
<div class="line"><a id="l06878" name="l06878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73bffe5ebb8d12020ebf3f2875f4a709"> 6878</a></span><span class="preprocessor">#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos) </span></div>
|
||
<div class="line"><a id="l06879" name="l06879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67fef54b7b6c44afcc50e4f20ba461fd"> 6879</a></span><span class="preprocessor">#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos) </span></div>
|
||
<div class="line"><a id="l06880" name="l06880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18946cdea0f463f1e5386f42986f7e67"> 6880</a></span><span class="preprocessor">#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos) </span></div>
|
||
<div class="line"><a id="l06881" name="l06881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad00a8584a84d18d76e147e4873740b4d"> 6881</a></span><span class="preprocessor">#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos) </span></div>
|
||
<div class="line"><a id="l06882" name="l06882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb898dd74f16687db438fac87e762e40"> 6882</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06883" name="l06883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae33aa677769879cad328db0ee92829df"> 6883</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos) </span></div>
|
||
<div class="line"><a id="l06884" name="l06884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c2bbd885cff2e6c16662a014f3125e1"> 6884</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk </span></div>
|
||
<div class="line"><a id="l06885" name="l06885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga823e5c42b89e152a8394c3fa6c8811ca"> 6885</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_0 0x00010000U </span></div>
|
||
<div class="line"><a id="l06886" name="l06886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d0ef7c876b297706a26dda017441f9c"> 6886</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_1 0x00020000U </span></div>
|
||
<div class="line"><a id="l06887" name="l06887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96c5b96918f1871febfb31a026028522"> 6887</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_2 0x00040000U </span></div>
|
||
<div class="line"><a id="l06888" name="l06888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb0fa51cc0e95dcc79b74f451898f634"> 6888</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_3 0x00080000U </span></div>
|
||
<div class="line"><a id="l06889" name="l06889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad936542dd4c587babd790e92783d90fb"> 6889</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_4 0x00100000U </span></div>
|
||
<div class="line"><a id="l06890" name="l06890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae20268ac71dad90ee983642bb328e8ca"> 6890</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_5 0x00200000U </span></div>
|
||
<div class="line"><a id="l06891" name="l06891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga947616eac2be3f26ae1a3d748e70cac8"> 6891</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_6 0x00400000U </span></div>
|
||
<div class="line"><a id="l06892" name="l06892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4d248e42a97e1c852cbea42b25598e1"> 6892</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_7 0x00800000U </span></div>
|
||
<div class="line"><a id="l06893" name="l06893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb38a3c5a67d67160a33d1762ed0f51f"> 6893</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_8 0x01000000U </span></div>
|
||
<div class="line"><a id="l06894" name="l06894"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e186dbacd1587760b167b9ae4166c5c"> 6894</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_9 0x02000000U </span></div>
|
||
<div class="line"><a id="l06895" name="l06895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38f22bae03f31d60f0c6aded7cd29ead"> 6895</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_10 0x04000000U </span></div>
|
||
<div class="line"><a id="l06896" name="l06896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac11ce7f6df6922142fc54fb8d376e239"> 6896</a></span><span class="preprocessor">#define FLASH_OPTCR_nWRP_11 0x08000000U </span></div>
|
||
<div class="line"><a id="l06897" name="l06897"></a><span class="lineno"> 6897</span> </div>
|
||
<div class="line"><a id="l06898" name="l06898"></a><span class="lineno"> 6898</span><span class="comment">/****************** Bits definition for FLASH_OPTCR1 register ***************/</span></div>
|
||
<div class="line"><a id="l06899" name="l06899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b"> 6899</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06900" name="l06900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga584b3c849783bc64b9fde5f4f15090b6"> 6900</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos) </span></div>
|
||
<div class="line"><a id="l06901" name="l06901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga166b108d44b55fef7da25bb1a9696d4a"> 6901</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk </span></div>
|
||
<div class="line"><a id="l06902" name="l06902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8704f7d9b4f2ed666a36fd524200393"> 6902</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos) </span></div>
|
||
<div class="line"><a id="l06903" name="l06903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5dbe2ea161a6b8f8f9410097b56e7f37"> 6903</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos) </span></div>
|
||
<div class="line"><a id="l06904" name="l06904"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95055e7aee08960157182164896ab53e"> 6904</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos) </span></div>
|
||
<div class="line"><a id="l06905" name="l06905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga215ec5e70d6f8e9bcfc23e808720b7b5"> 6905</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos) </span></div>
|
||
<div class="line"><a id="l06906" name="l06906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga552186f19bc88ebbceb4b20fd17fa15c"> 6906</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos) </span></div>
|
||
<div class="line"><a id="l06907" name="l06907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4370733a7b56759492f1af72272d086"> 6907</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos) </span></div>
|
||
<div class="line"><a id="l06908" name="l06908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeecb61b8efdc36c40fce01e4cd1d5907"> 6908</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos) </span></div>
|
||
<div class="line"><a id="l06909" name="l06909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e3446bcd7be06c230bc6cbceadae5cf"> 6909</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos) </span></div>
|
||
<div class="line"><a id="l06910" name="l06910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97aac6b31d856505401e3bef486df10f"> 6910</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos) </span></div>
|
||
<div class="line"><a id="l06911" name="l06911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ab067bd8ab9645c93e6acf3b839dd8d"> 6911</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos) </span></div>
|
||
<div class="line"><a id="l06912" name="l06912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf08f9db2b0ca30861faac54b6df672e"> 6912</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos) </span></div>
|
||
<div class="line"><a id="l06913" name="l06913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga244656eb3ca465d38aba14e92f8c5870"> 6913</a></span><span class="preprocessor">#define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos) </span></div>
|
||
<div class="line"><a id="l06915" name="l06915"></a><span class="lineno"> 6915</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l06916" name="l06916"></a><span class="lineno"> 6916</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l06917" name="l06917"></a><span class="lineno"> 6917</span><span class="comment">/* Flexible Static Memory Controller */</span></div>
|
||
<div class="line"><a id="l06918" name="l06918"></a><span class="lineno"> 6918</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l06919" name="l06919"></a><span class="lineno"> 6919</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l06920" name="l06920"></a><span class="lineno"> 6920</span><span class="comment">/****************** Bit definition for FSMC_BCR1 register *******************/</span></div>
|
||
<div class="line"><a id="l06921" name="l06921"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdb4fdc15ea8091df00881c342b88eda"> 6921</a></span><span class="preprocessor">#define FSMC_BCR1_MBKEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06922" name="l06922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fb54a74314811fa88d317a79004527c"> 6922</a></span><span class="preprocessor">#define FSMC_BCR1_MBKEN_Msk (0x1UL << FSMC_BCR1_MBKEN_Pos) </span></div>
|
||
<div class="line"><a id="l06923" name="l06923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad154cab86ce34cebfe1f76e5c2f78e61"> 6923</a></span><span class="preprocessor">#define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk </span></div>
|
||
<div class="line"><a id="l06924" name="l06924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13b709c2443de9ab40dadc6830f31158"> 6924</a></span><span class="preprocessor">#define FSMC_BCR1_MUXEN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l06925" name="l06925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1346d0cf99bad4d9863fd777d1930d6c"> 6925</a></span><span class="preprocessor">#define FSMC_BCR1_MUXEN_Msk (0x1UL << FSMC_BCR1_MUXEN_Pos) </span></div>
|
||
<div class="line"><a id="l06926" name="l06926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28dd9f93d8687cdc08745df9fcc38e89"> 6926</a></span><span class="preprocessor">#define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk </span></div>
|
||
<div class="line"><a id="l06928" name="l06928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf7fa08d310f1b3d957f0600375b3c87"> 6928</a></span><span class="preprocessor">#define FSMC_BCR1_MTYP_Pos (2U) </span></div>
|
||
<div class="line"><a id="l06929" name="l06929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76cf34bfdd2f5d9a7959fee17050319f"> 6929</a></span><span class="preprocessor">#define FSMC_BCR1_MTYP_Msk (0x3UL << FSMC_BCR1_MTYP_Pos) </span></div>
|
||
<div class="line"><a id="l06930" name="l06930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9bab7a47703902d187502ac765ebb05d"> 6930</a></span><span class="preprocessor">#define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk </span></div>
|
||
<div class="line"><a id="l06931" name="l06931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29b921567bd5a422c51f9a0f426ac3f6"> 6931</a></span><span class="preprocessor">#define FSMC_BCR1_MTYP_0 (0x1UL << FSMC_BCR1_MTYP_Pos) </span></div>
|
||
<div class="line"><a id="l06932" name="l06932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3fe2fd14b3c0d88aecfb9cf5b44995a0"> 6932</a></span><span class="preprocessor">#define FSMC_BCR1_MTYP_1 (0x2UL << FSMC_BCR1_MTYP_Pos) </span></div>
|
||
<div class="line"><a id="l06934" name="l06934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ec03e929628fb56d95403641ec23ac0"> 6934</a></span><span class="preprocessor">#define FSMC_BCR1_MWID_Pos (4U) </span></div>
|
||
<div class="line"><a id="l06935" name="l06935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e42eb74853897be5a39fe4e8549d166"> 6935</a></span><span class="preprocessor">#define FSMC_BCR1_MWID_Msk (0x3UL << FSMC_BCR1_MWID_Pos) </span></div>
|
||
<div class="line"><a id="l06936" name="l06936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa12297787a0580fedbd5244f0caa0a76"> 6936</a></span><span class="preprocessor">#define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk </span></div>
|
||
<div class="line"><a id="l06937" name="l06937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a6fe3b4b28a31c4bbf26a838695fd0c"> 6937</a></span><span class="preprocessor">#define FSMC_BCR1_MWID_0 (0x1UL << FSMC_BCR1_MWID_Pos) </span></div>
|
||
<div class="line"><a id="l06938" name="l06938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65592a6a20efa6aed5b59fe1eba508d8"> 6938</a></span><span class="preprocessor">#define FSMC_BCR1_MWID_1 (0x2UL << FSMC_BCR1_MWID_Pos) </span></div>
|
||
<div class="line"><a id="l06940" name="l06940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga955890b4486255e510806f000bb44f43"> 6940</a></span><span class="preprocessor">#define FSMC_BCR1_FACCEN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l06941" name="l06941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5822754c7aa0947d0b6623d884438f0e"> 6941</a></span><span class="preprocessor">#define FSMC_BCR1_FACCEN_Msk (0x1UL << FSMC_BCR1_FACCEN_Pos) </span></div>
|
||
<div class="line"><a id="l06942" name="l06942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14aaca2a8bccab73c7726cf73ee9be16"> 6942</a></span><span class="preprocessor">#define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk </span></div>
|
||
<div class="line"><a id="l06943" name="l06943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd79d1d9b9be97259d21184a38b79e78"> 6943</a></span><span class="preprocessor">#define FSMC_BCR1_BURSTEN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l06944" name="l06944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga093941fc5df6f3d174d23a4863be87c3"> 6944</a></span><span class="preprocessor">#define FSMC_BCR1_BURSTEN_Msk (0x1UL << FSMC_BCR1_BURSTEN_Pos) </span></div>
|
||
<div class="line"><a id="l06945" name="l06945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94857a0177ae12f1172da65d8708ae97"> 6945</a></span><span class="preprocessor">#define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk </span></div>
|
||
<div class="line"><a id="l06946" name="l06946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa688dcd0dc2b3c072f353941a5cb8c63"> 6946</a></span><span class="preprocessor">#define FSMC_BCR1_WAITPOL_Pos (9U) </span></div>
|
||
<div class="line"><a id="l06947" name="l06947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66ec261e040de2455880252747ec2954"> 6947</a></span><span class="preprocessor">#define FSMC_BCR1_WAITPOL_Msk (0x1UL << FSMC_BCR1_WAITPOL_Pos) </span></div>
|
||
<div class="line"><a id="l06948" name="l06948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57dbc565fbc7d8ec20fda7ef0da30df4"> 6948</a></span><span class="preprocessor">#define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk </span></div>
|
||
<div class="line"><a id="l06949" name="l06949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81d2d47d639ff73b641182d78e5388cc"> 6949</a></span><span class="preprocessor">#define FSMC_BCR1_WRAPMOD_Pos (10U) </span></div>
|
||
<div class="line"><a id="l06950" name="l06950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae07f435df040041ae6b196ebc57e5038"> 6950</a></span><span class="preprocessor">#define FSMC_BCR1_WRAPMOD_Msk (0x1UL << FSMC_BCR1_WRAPMOD_Pos) </span></div>
|
||
<div class="line"><a id="l06951" name="l06951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad215e95feee8339393bd93a2bcea11f1"> 6951</a></span><span class="preprocessor">#define FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk </span></div>
|
||
<div class="line"><a id="l06952" name="l06952"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa37e744f19838aaaaa33e3184d68904e"> 6952</a></span><span class="preprocessor">#define FSMC_BCR1_WAITCFG_Pos (11U) </span></div>
|
||
<div class="line"><a id="l06953" name="l06953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacccfccbca149c2df3ec50918bcb5822e"> 6953</a></span><span class="preprocessor">#define FSMC_BCR1_WAITCFG_Msk (0x1UL << FSMC_BCR1_WAITCFG_Pos) </span></div>
|
||
<div class="line"><a id="l06954" name="l06954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga141a337e3f1479e79d62b567ba685bcf"> 6954</a></span><span class="preprocessor">#define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk </span></div>
|
||
<div class="line"><a id="l06955" name="l06955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa816e36a3fdd330c2f0ce4e4cceabf43"> 6955</a></span><span class="preprocessor">#define FSMC_BCR1_WREN_Pos (12U) </span></div>
|
||
<div class="line"><a id="l06956" name="l06956"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d6049a6f86dcc5df8daaaa481e6927d"> 6956</a></span><span class="preprocessor">#define FSMC_BCR1_WREN_Msk (0x1UL << FSMC_BCR1_WREN_Pos) </span></div>
|
||
<div class="line"><a id="l06957" name="l06957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7349a91da7ba38277a068f4e8eea314"> 6957</a></span><span class="preprocessor">#define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk </span></div>
|
||
<div class="line"><a id="l06958" name="l06958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a3407dc3470cd1ced7fd05ffb11159b"> 6958</a></span><span class="preprocessor">#define FSMC_BCR1_WAITEN_Pos (13U) </span></div>
|
||
<div class="line"><a id="l06959" name="l06959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga423ede6efc2a21e6a832faf9154df8a0"> 6959</a></span><span class="preprocessor">#define FSMC_BCR1_WAITEN_Msk (0x1UL << FSMC_BCR1_WAITEN_Pos) </span></div>
|
||
<div class="line"><a id="l06960" name="l06960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe4611a02a4fa635b66d5b5e52328fc5"> 6960</a></span><span class="preprocessor">#define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk </span></div>
|
||
<div class="line"><a id="l06961" name="l06961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b6b842527b6be91baf209d302c0dcb2"> 6961</a></span><span class="preprocessor">#define FSMC_BCR1_EXTMOD_Pos (14U) </span></div>
|
||
<div class="line"><a id="l06962" name="l06962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59c8fad26fdda8528641ccde63012333"> 6962</a></span><span class="preprocessor">#define FSMC_BCR1_EXTMOD_Msk (0x1UL << FSMC_BCR1_EXTMOD_Pos) </span></div>
|
||
<div class="line"><a id="l06963" name="l06963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7936ff74a1cfba880a9b5bc943dc8661"> 6963</a></span><span class="preprocessor">#define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk </span></div>
|
||
<div class="line"><a id="l06964" name="l06964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49520648ee432b57ad212494763df6f0"> 6964</a></span><span class="preprocessor">#define FSMC_BCR1_ASYNCWAIT_Pos (15U) </span></div>
|
||
<div class="line"><a id="l06965" name="l06965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2587d2fc09a87653afa500cc77ce010"> 6965</a></span><span class="preprocessor">#define FSMC_BCR1_ASYNCWAIT_Msk (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos) </span></div>
|
||
<div class="line"><a id="l06966" name="l06966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5673d96c0fb27c7faed335e05ad41c1"> 6966</a></span><span class="preprocessor">#define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk </span></div>
|
||
<div class="line"><a id="l06967" name="l06967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga150c6b16ddf3ab16470062b3aa651c42"> 6967</a></span><span class="preprocessor">#define FSMC_BCR1_CPSIZE_Pos (16U) </span></div>
|
||
<div class="line"><a id="l06968" name="l06968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10293af49314e88488ceb0d3e0faa53a"> 6968</a></span><span class="preprocessor">#define FSMC_BCR1_CPSIZE_Msk (0x7UL << FSMC_BCR1_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l06969" name="l06969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga192791b6dc4c25e4992b07f098006a4e"> 6969</a></span><span class="preprocessor">#define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk </span></div>
|
||
<div class="line"><a id="l06970" name="l06970"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90f6d13b70b5cadaf0325336ffa204c2"> 6970</a></span><span class="preprocessor">#define FSMC_BCR1_CPSIZE_0 (0x1UL << FSMC_BCR1_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l06971" name="l06971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23f9cde76aa0df2b76bec396614542d2"> 6971</a></span><span class="preprocessor">#define FSMC_BCR1_CPSIZE_1 (0x2UL << FSMC_BCR1_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l06972" name="l06972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b7e96850fe4f75e4ad878696ef94356"> 6972</a></span><span class="preprocessor">#define FSMC_BCR1_CPSIZE_2 (0x4UL << FSMC_BCR1_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l06973" name="l06973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92b8ede1953ab41ab13d6a6d62953ffa"> 6973</a></span><span class="preprocessor">#define FSMC_BCR1_CBURSTRW_Pos (19U) </span></div>
|
||
<div class="line"><a id="l06974" name="l06974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56ae50002811cf51dce4cb26da2a18bb"> 6974</a></span><span class="preprocessor">#define FSMC_BCR1_CBURSTRW_Msk (0x1UL << FSMC_BCR1_CBURSTRW_Pos) </span></div>
|
||
<div class="line"><a id="l06975" name="l06975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga015672f5aa2132a55e316f5b7a577174"> 6975</a></span><span class="preprocessor">#define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk </span></div>
|
||
<div class="line"><a id="l06977" name="l06977"></a><span class="lineno"> 6977</span><span class="comment">/****************** Bit definition for FSMC_BCR2 register *******************/</span></div>
|
||
<div class="line"><a id="l06978" name="l06978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ad7fd4c0644328d6b50f1af802ec2f8"> 6978</a></span><span class="preprocessor">#define FSMC_BCR2_MBKEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l06979" name="l06979"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6ef33bf632e3d9fbe345050be4f322a"> 6979</a></span><span class="preprocessor">#define FSMC_BCR2_MBKEN_Msk (0x1UL << FSMC_BCR2_MBKEN_Pos) </span></div>
|
||
<div class="line"><a id="l06980" name="l06980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9c99df3c6cebc68f6695ad7bc13f717"> 6980</a></span><span class="preprocessor">#define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk </span></div>
|
||
<div class="line"><a id="l06981" name="l06981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ac9fba61cf9cc72921d4f428738826c"> 6981</a></span><span class="preprocessor">#define FSMC_BCR2_MUXEN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l06982" name="l06982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bf9eb6b6bdd6af3179dddcaabca890a"> 6982</a></span><span class="preprocessor">#define FSMC_BCR2_MUXEN_Msk (0x1UL << FSMC_BCR2_MUXEN_Pos) </span></div>
|
||
<div class="line"><a id="l06983" name="l06983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f65c4348ab55c12695730bde8be8986"> 6983</a></span><span class="preprocessor">#define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk </span></div>
|
||
<div class="line"><a id="l06985" name="l06985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7789cdcc69a54e451f419b3d5266edac"> 6985</a></span><span class="preprocessor">#define FSMC_BCR2_MTYP_Pos (2U) </span></div>
|
||
<div class="line"><a id="l06986" name="l06986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga166ddafe3e417b6bb11f233e4e2dedf3"> 6986</a></span><span class="preprocessor">#define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) </span></div>
|
||
<div class="line"><a id="l06987" name="l06987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdf82247710aaeff72fb37113bff3daf"> 6987</a></span><span class="preprocessor">#define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk </span></div>
|
||
<div class="line"><a id="l06988" name="l06988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac595e1e3045aad0b379367f47bf10a84"> 6988</a></span><span class="preprocessor">#define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) </span></div>
|
||
<div class="line"><a id="l06989" name="l06989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b9e5b00171ea739ba67a627a2484f47"> 6989</a></span><span class="preprocessor">#define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) </span></div>
|
||
<div class="line"><a id="l06991" name="l06991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5a899fbf4b3ed1a7fa6ee26cea383b4"> 6991</a></span><span class="preprocessor">#define FSMC_BCR2_MWID_Pos (4U) </span></div>
|
||
<div class="line"><a id="l06992" name="l06992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a1f1c8878a8d8a6680537bf0c5ae926"> 6992</a></span><span class="preprocessor">#define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) </span></div>
|
||
<div class="line"><a id="l06993" name="l06993"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4099746e30f71a98ea71d1048a5d028a"> 6993</a></span><span class="preprocessor">#define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk </span></div>
|
||
<div class="line"><a id="l06994" name="l06994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8501d3ce728f6a074061294a9e5a54cf"> 6994</a></span><span class="preprocessor">#define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) </span></div>
|
||
<div class="line"><a id="l06995" name="l06995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74276c5828d545cf4b2db2d568c60627"> 6995</a></span><span class="preprocessor">#define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) </span></div>
|
||
<div class="line"><a id="l06997" name="l06997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5111c287808eaefab515193e2bfe738e"> 6997</a></span><span class="preprocessor">#define FSMC_BCR2_FACCEN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l06998" name="l06998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga182a7aed98f38419b4d55f4e746ddb78"> 6998</a></span><span class="preprocessor">#define FSMC_BCR2_FACCEN_Msk (0x1UL << FSMC_BCR2_FACCEN_Pos) </span></div>
|
||
<div class="line"><a id="l06999" name="l06999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a4e1ad30533ab54b45987cab30d51a0"> 6999</a></span><span class="preprocessor">#define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk </span></div>
|
||
<div class="line"><a id="l07000" name="l07000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga061b10b005a1fddca182f8df1a520fbd"> 7000</a></span><span class="preprocessor">#define FSMC_BCR2_BURSTEN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07001" name="l07001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04ef7898a3300a0e437e98e0f3e266e3"> 7001</a></span><span class="preprocessor">#define FSMC_BCR2_BURSTEN_Msk (0x1UL << FSMC_BCR2_BURSTEN_Pos) </span></div>
|
||
<div class="line"><a id="l07002" name="l07002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d8202b9b40d3912a6294fe2a0e28ebf"> 7002</a></span><span class="preprocessor">#define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk </span></div>
|
||
<div class="line"><a id="l07003" name="l07003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf39e91bdf996e863420c7e8fc1e5590e"> 7003</a></span><span class="preprocessor">#define FSMC_BCR2_WAITPOL_Pos (9U) </span></div>
|
||
<div class="line"><a id="l07004" name="l07004"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga363eda93ed7acbb8f0d18a3a291730c7"> 7004</a></span><span class="preprocessor">#define FSMC_BCR2_WAITPOL_Msk (0x1UL << FSMC_BCR2_WAITPOL_Pos) </span></div>
|
||
<div class="line"><a id="l07005" name="l07005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0f59e7aa2664f9c767ce22bec369698"> 7005</a></span><span class="preprocessor">#define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk </span></div>
|
||
<div class="line"><a id="l07006" name="l07006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga789e78a6f20dfc6d81c80f6f1c6c52a6"> 7006</a></span><span class="preprocessor">#define FSMC_BCR2_WRAPMOD_Pos (10U) </span></div>
|
||
<div class="line"><a id="l07007" name="l07007"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3424ec4e7bd6b62133ca3427cc80293c"> 7007</a></span><span class="preprocessor">#define FSMC_BCR2_WRAPMOD_Msk (0x1UL << FSMC_BCR2_WRAPMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07008" name="l07008"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e93e4e902a636d4d75a1fd7e884afea"> 7008</a></span><span class="preprocessor">#define FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk </span></div>
|
||
<div class="line"><a id="l07009" name="l07009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e9aee1a917ef0b27eb9b5734f853670"> 7009</a></span><span class="preprocessor">#define FSMC_BCR2_WAITCFG_Pos (11U) </span></div>
|
||
<div class="line"><a id="l07010" name="l07010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0200789ac85e6c5e1e481c3df1446e18"> 7010</a></span><span class="preprocessor">#define FSMC_BCR2_WAITCFG_Msk (0x1UL << FSMC_BCR2_WAITCFG_Pos) </span></div>
|
||
<div class="line"><a id="l07011" name="l07011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5141640b4dcb78a524740b681819f9f1"> 7011</a></span><span class="preprocessor">#define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk </span></div>
|
||
<div class="line"><a id="l07012" name="l07012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c00df8248fceccd441d5d4b73b86622"> 7012</a></span><span class="preprocessor">#define FSMC_BCR2_WREN_Pos (12U) </span></div>
|
||
<div class="line"><a id="l07013" name="l07013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33a8ad888dead565af3852d70b3ad6b9"> 7013</a></span><span class="preprocessor">#define FSMC_BCR2_WREN_Msk (0x1UL << FSMC_BCR2_WREN_Pos) </span></div>
|
||
<div class="line"><a id="l07014" name="l07014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad446f2fcb7909b80a8c1731141be5186"> 7014</a></span><span class="preprocessor">#define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk </span></div>
|
||
<div class="line"><a id="l07015" name="l07015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f4660e60da72244831d66378c76b627"> 7015</a></span><span class="preprocessor">#define FSMC_BCR2_WAITEN_Pos (13U) </span></div>
|
||
<div class="line"><a id="l07016" name="l07016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8c82d9bdf8bfef070bc96dcfe7e3d8d"> 7016</a></span><span class="preprocessor">#define FSMC_BCR2_WAITEN_Msk (0x1UL << FSMC_BCR2_WAITEN_Pos) </span></div>
|
||
<div class="line"><a id="l07017" name="l07017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad015d2aa1c58b48681f35a4f92eaf7f7"> 7017</a></span><span class="preprocessor">#define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk </span></div>
|
||
<div class="line"><a id="l07018" name="l07018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7799a975be4610d90af7d63aff4eb8f6"> 7018</a></span><span class="preprocessor">#define FSMC_BCR2_EXTMOD_Pos (14U) </span></div>
|
||
<div class="line"><a id="l07019" name="l07019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0d624c95c3930043d2561545ecfd5a5"> 7019</a></span><span class="preprocessor">#define FSMC_BCR2_EXTMOD_Msk (0x1UL << FSMC_BCR2_EXTMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07020" name="l07020"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76d3e5d899ba2399d3318da577d58ac6"> 7020</a></span><span class="preprocessor">#define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk </span></div>
|
||
<div class="line"><a id="l07021" name="l07021"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca3661a377838f2fcd8d13def99b2bfe"> 7021</a></span><span class="preprocessor">#define FSMC_BCR2_ASYNCWAIT_Pos (15U) </span></div>
|
||
<div class="line"><a id="l07022" name="l07022"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5afee4a8591dcaaa4161fbb6ca509c68"> 7022</a></span><span class="preprocessor">#define FSMC_BCR2_ASYNCWAIT_Msk (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos) </span></div>
|
||
<div class="line"><a id="l07023" name="l07023"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad45d1b552ba61ccbb1dc4ebfc556285a"> 7023</a></span><span class="preprocessor">#define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk </span></div>
|
||
<div class="line"><a id="l07024" name="l07024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29b50188ab8dd06a8dcea1db253c43d3"> 7024</a></span><span class="preprocessor">#define FSMC_BCR2_CPSIZE_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07025" name="l07025"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga379d9cd3ddb5ad5c73a6aaecd6a39842"> 7025</a></span><span class="preprocessor">#define FSMC_BCR2_CPSIZE_Msk (0x7UL << FSMC_BCR2_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l07026" name="l07026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4546f80f34121d6700fbb8389f69854a"> 7026</a></span><span class="preprocessor">#define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk </span></div>
|
||
<div class="line"><a id="l07027" name="l07027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bd12d2e7ea6f99a6fb5c2519d3f7a48"> 7027</a></span><span class="preprocessor">#define FSMC_BCR2_CPSIZE_0 (0x1UL << FSMC_BCR2_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l07028" name="l07028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2db6a0901e5f500c9c907a8fa2304c4d"> 7028</a></span><span class="preprocessor">#define FSMC_BCR2_CPSIZE_1 (0x2UL << FSMC_BCR2_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l07029" name="l07029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga983f7ba781deff462208b000d0749d42"> 7029</a></span><span class="preprocessor">#define FSMC_BCR2_CPSIZE_2 (0x4UL << FSMC_BCR2_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l07030" name="l07030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4234ff44107642d57fc60bb1b4986d5"> 7030</a></span><span class="preprocessor">#define FSMC_BCR2_CBURSTRW_Pos (19U) </span></div>
|
||
<div class="line"><a id="l07031" name="l07031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga354accac428f799c4156a56f43d81c5e"> 7031</a></span><span class="preprocessor">#define FSMC_BCR2_CBURSTRW_Msk (0x1UL << FSMC_BCR2_CBURSTRW_Pos) </span></div>
|
||
<div class="line"><a id="l07032" name="l07032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae64b1874f1ab83a1d0224cb66e504dff"> 7032</a></span><span class="preprocessor">#define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk </span></div>
|
||
<div class="line"><a id="l07034" name="l07034"></a><span class="lineno"> 7034</span><span class="comment">/****************** Bit definition for FSMC_BCR3 register *******************/</span></div>
|
||
<div class="line"><a id="l07035" name="l07035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5eb6d03fe467aad546d992b73194cb27"> 7035</a></span><span class="preprocessor">#define FSMC_BCR3_MBKEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07036" name="l07036"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga969d8a0800e499c8cfaae30766673baf"> 7036</a></span><span class="preprocessor">#define FSMC_BCR3_MBKEN_Msk (0x1UL << FSMC_BCR3_MBKEN_Pos) </span></div>
|
||
<div class="line"><a id="l07037" name="l07037"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d7810ad338086a1ec9b15f339ed6f4d"> 7037</a></span><span class="preprocessor">#define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk </span></div>
|
||
<div class="line"><a id="l07038" name="l07038"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga257d8fa0925c2a6e4ca3c71724a1c727"> 7038</a></span><span class="preprocessor">#define FSMC_BCR3_MUXEN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l07039" name="l07039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade598d66e7b6ff96d1cc42e78566291b"> 7039</a></span><span class="preprocessor">#define FSMC_BCR3_MUXEN_Msk (0x1UL << FSMC_BCR3_MUXEN_Pos) </span></div>
|
||
<div class="line"><a id="l07040" name="l07040"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadaae648c8591e7650cba828910638d3d"> 7040</a></span><span class="preprocessor">#define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk </span></div>
|
||
<div class="line"><a id="l07042" name="l07042"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab67e61d2783a793ef984e897897212fa"> 7042</a></span><span class="preprocessor">#define FSMC_BCR3_MTYP_Pos (2U) </span></div>
|
||
<div class="line"><a id="l07043" name="l07043"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga988d00e68c4a63b1fc0b575bd9297db2"> 7043</a></span><span class="preprocessor">#define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) </span></div>
|
||
<div class="line"><a id="l07044" name="l07044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga319fb6069b651eb947b4d0ba3c9f6196"> 7044</a></span><span class="preprocessor">#define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk </span></div>
|
||
<div class="line"><a id="l07045" name="l07045"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf33b80510e653dd32de2ae1ec1a1dfb5"> 7045</a></span><span class="preprocessor">#define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) </span></div>
|
||
<div class="line"><a id="l07046" name="l07046"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a038553e3a30df4b6e331cad504069b"> 7046</a></span><span class="preprocessor">#define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) </span></div>
|
||
<div class="line"><a id="l07048" name="l07048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17b5f1b6b3101230c49e90176f430673"> 7048</a></span><span class="preprocessor">#define FSMC_BCR3_MWID_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07049" name="l07049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cd430671ae5969640d73b758ffdf612"> 7049</a></span><span class="preprocessor">#define FSMC_BCR3_MWID_Msk (0x3UL << FSMC_BCR3_MWID_Pos) </span></div>
|
||
<div class="line"><a id="l07050" name="l07050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51097cfe8d4263a30d292e7e9dc73cd2"> 7050</a></span><span class="preprocessor">#define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk </span></div>
|
||
<div class="line"><a id="l07051" name="l07051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga373b764c1a4104300eb587aa4510c1f1"> 7051</a></span><span class="preprocessor">#define FSMC_BCR3_MWID_0 (0x1UL << FSMC_BCR3_MWID_Pos) </span></div>
|
||
<div class="line"><a id="l07052" name="l07052"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43c7292c185269cc11d986f3ae0ceb24"> 7052</a></span><span class="preprocessor">#define FSMC_BCR3_MWID_1 (0x2UL << FSMC_BCR3_MWID_Pos) </span></div>
|
||
<div class="line"><a id="l07054" name="l07054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70b916af09f1553cb63363b748b1f027"> 7054</a></span><span class="preprocessor">#define FSMC_BCR3_FACCEN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l07055" name="l07055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38db506ff5f00d90249a3a8521df490b"> 7055</a></span><span class="preprocessor">#define FSMC_BCR3_FACCEN_Msk (0x1UL << FSMC_BCR3_FACCEN_Pos) </span></div>
|
||
<div class="line"><a id="l07056" name="l07056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga380c39b95426ac9a18c70e3f56016c81"> 7056</a></span><span class="preprocessor">#define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk </span></div>
|
||
<div class="line"><a id="l07057" name="l07057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga334b4a9ae7115924ece63694dcb6ee37"> 7057</a></span><span class="preprocessor">#define FSMC_BCR3_BURSTEN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07058" name="l07058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga633d9f36439fa9f12c12c2a46152624b"> 7058</a></span><span class="preprocessor">#define FSMC_BCR3_BURSTEN_Msk (0x1UL << FSMC_BCR3_BURSTEN_Pos) </span></div>
|
||
<div class="line"><a id="l07059" name="l07059"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9badf60f5caa010e041d66d40af596a"> 7059</a></span><span class="preprocessor">#define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk </span></div>
|
||
<div class="line"><a id="l07060" name="l07060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8ca3bf2ec7e7869de4f702e2781df26"> 7060</a></span><span class="preprocessor">#define FSMC_BCR3_WAITPOL_Pos (9U) </span></div>
|
||
<div class="line"><a id="l07061" name="l07061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76308f3761147bead10be8690363ba75"> 7061</a></span><span class="preprocessor">#define FSMC_BCR3_WAITPOL_Msk (0x1UL << FSMC_BCR3_WAITPOL_Pos) </span></div>
|
||
<div class="line"><a id="l07062" name="l07062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbca3d0aa315f3e9bc6bacf244bdb747"> 7062</a></span><span class="preprocessor">#define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk </span></div>
|
||
<div class="line"><a id="l07063" name="l07063"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad89219171643f908db3cfa28eee4d5e9"> 7063</a></span><span class="preprocessor">#define FSMC_BCR3_WRAPMOD_Pos (10U) </span></div>
|
||
<div class="line"><a id="l07064" name="l07064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae03d16e63e73b02834d26f33cc91dc64"> 7064</a></span><span class="preprocessor">#define FSMC_BCR3_WRAPMOD_Msk (0x1UL << FSMC_BCR3_WRAPMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07065" name="l07065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44fc6e205695d39b63c0f5b18c3cd214"> 7065</a></span><span class="preprocessor">#define FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk </span></div>
|
||
<div class="line"><a id="l07066" name="l07066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6429581833534bce92d223e08c93eb32"> 7066</a></span><span class="preprocessor">#define FSMC_BCR3_WAITCFG_Pos (11U) </span></div>
|
||
<div class="line"><a id="l07067" name="l07067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86ce7ee19c1952a2cd3a7dd07988d404"> 7067</a></span><span class="preprocessor">#define FSMC_BCR3_WAITCFG_Msk (0x1UL << FSMC_BCR3_WAITCFG_Pos) </span></div>
|
||
<div class="line"><a id="l07068" name="l07068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab845515c37adae28d0e1452596cca7ea"> 7068</a></span><span class="preprocessor">#define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk </span></div>
|
||
<div class="line"><a id="l07069" name="l07069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga704d37df498bac515b6ec4c5e4f94462"> 7069</a></span><span class="preprocessor">#define FSMC_BCR3_WREN_Pos (12U) </span></div>
|
||
<div class="line"><a id="l07070" name="l07070"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe425cfa93902161f696ee0d9b26e9c5"> 7070</a></span><span class="preprocessor">#define FSMC_BCR3_WREN_Msk (0x1UL << FSMC_BCR3_WREN_Pos) </span></div>
|
||
<div class="line"><a id="l07071" name="l07071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22c9b0145aa62cafd915a4c7da1931b5"> 7071</a></span><span class="preprocessor">#define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk </span></div>
|
||
<div class="line"><a id="l07072" name="l07072"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabb86a849ca798041db570103d48155c"> 7072</a></span><span class="preprocessor">#define FSMC_BCR3_WAITEN_Pos (13U) </span></div>
|
||
<div class="line"><a id="l07073" name="l07073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga955ff9500147df62bd5e71fd46ab399c"> 7073</a></span><span class="preprocessor">#define FSMC_BCR3_WAITEN_Msk (0x1UL << FSMC_BCR3_WAITEN_Pos) </span></div>
|
||
<div class="line"><a id="l07074" name="l07074"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9665b36b791862c464f07ad49dea315c"> 7074</a></span><span class="preprocessor">#define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk </span></div>
|
||
<div class="line"><a id="l07075" name="l07075"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac15a809e2405d3853528319668a81ef7"> 7075</a></span><span class="preprocessor">#define FSMC_BCR3_EXTMOD_Pos (14U) </span></div>
|
||
<div class="line"><a id="l07076" name="l07076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f660417a9ec23815a2d362dea91b1e3"> 7076</a></span><span class="preprocessor">#define FSMC_BCR3_EXTMOD_Msk (0x1UL << FSMC_BCR3_EXTMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07077" name="l07077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ab23550b17dca7ede57f8b5ef05f2e7"> 7077</a></span><span class="preprocessor">#define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk </span></div>
|
||
<div class="line"><a id="l07078" name="l07078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7bf971e9566cc6a9e6638e0bca989f6c"> 7078</a></span><span class="preprocessor">#define FSMC_BCR3_ASYNCWAIT_Pos (15U) </span></div>
|
||
<div class="line"><a id="l07079" name="l07079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84c1483478667f1f1121b1b53aaf5bbc"> 7079</a></span><span class="preprocessor">#define FSMC_BCR3_ASYNCWAIT_Msk (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos) </span></div>
|
||
<div class="line"><a id="l07080" name="l07080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e16fb6b68a8adb7722871ccdd2d9a44"> 7080</a></span><span class="preprocessor">#define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk </span></div>
|
||
<div class="line"><a id="l07081" name="l07081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecac8e30310435e28ad6456946b63ceb"> 7081</a></span><span class="preprocessor">#define FSMC_BCR3_CPSIZE_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07082" name="l07082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31e584400d48bf2a9f09b16d93e9aab4"> 7082</a></span><span class="preprocessor">#define FSMC_BCR3_CPSIZE_Msk (0x7UL << FSMC_BCR3_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l07083" name="l07083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49e7953ee4991f90a96c3b6a72315731"> 7083</a></span><span class="preprocessor">#define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk </span></div>
|
||
<div class="line"><a id="l07084" name="l07084"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbe607c14de8dfcce9919fecba70f4b4"> 7084</a></span><span class="preprocessor">#define FSMC_BCR3_CPSIZE_0 (0x1UL << FSMC_BCR3_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l07085" name="l07085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6790c025341fd005cee64fb8a4a231d8"> 7085</a></span><span class="preprocessor">#define FSMC_BCR3_CPSIZE_1 (0x2UL << FSMC_BCR3_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l07086" name="l07086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad77d43cb841e9374c76e93ea443630ad"> 7086</a></span><span class="preprocessor">#define FSMC_BCR3_CPSIZE_2 (0x4UL << FSMC_BCR3_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l07087" name="l07087"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07716de72f0cdc426b9c6989d680e05e"> 7087</a></span><span class="preprocessor">#define FSMC_BCR3_CBURSTRW_Pos (19U) </span></div>
|
||
<div class="line"><a id="l07088" name="l07088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad14301188370a35a883fbd2c29fbfab7"> 7088</a></span><span class="preprocessor">#define FSMC_BCR3_CBURSTRW_Msk (0x1UL << FSMC_BCR3_CBURSTRW_Pos) </span></div>
|
||
<div class="line"><a id="l07089" name="l07089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70c6da37696af84767f82efd0df3a7da"> 7089</a></span><span class="preprocessor">#define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk </span></div>
|
||
<div class="line"><a id="l07091" name="l07091"></a><span class="lineno"> 7091</span><span class="comment">/****************** Bit definition for FSMC_BCR4 register *******************/</span></div>
|
||
<div class="line"><a id="l07092" name="l07092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae79298022ec557019f4b238bc0a1c93e"> 7092</a></span><span class="preprocessor">#define FSMC_BCR4_MBKEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07093" name="l07093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b3f9e5b69de79c42b203113832b8767"> 7093</a></span><span class="preprocessor">#define FSMC_BCR4_MBKEN_Msk (0x1UL << FSMC_BCR4_MBKEN_Pos) </span></div>
|
||
<div class="line"><a id="l07094" name="l07094"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a1ea2c2967cda7ef1597c4fb1a9dd9a"> 7094</a></span><span class="preprocessor">#define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk </span></div>
|
||
<div class="line"><a id="l07095" name="l07095"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga241a30edf0f4403c5154c249277443a8"> 7095</a></span><span class="preprocessor">#define FSMC_BCR4_MUXEN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l07096" name="l07096"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1556380a7357a40ef14a0e064adb39ef"> 7096</a></span><span class="preprocessor">#define FSMC_BCR4_MUXEN_Msk (0x1UL << FSMC_BCR4_MUXEN_Pos) </span></div>
|
||
<div class="line"><a id="l07097" name="l07097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92d644d34b59762d0b48f7784d3aed4b"> 7097</a></span><span class="preprocessor">#define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk </span></div>
|
||
<div class="line"><a id="l07099" name="l07099"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96c0fdb70786e0c784a5a4c002ca41db"> 7099</a></span><span class="preprocessor">#define FSMC_BCR4_MTYP_Pos (2U) </span></div>
|
||
<div class="line"><a id="l07100" name="l07100"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f4900e19f018d5deee5bbbd8605ccc9"> 7100</a></span><span class="preprocessor">#define FSMC_BCR4_MTYP_Msk (0x3UL << FSMC_BCR4_MTYP_Pos) </span></div>
|
||
<div class="line"><a id="l07101" name="l07101"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f9bf2c236b772e76174aff4388a1b6f"> 7101</a></span><span class="preprocessor">#define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk </span></div>
|
||
<div class="line"><a id="l07102" name="l07102"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66d358ec27a34fe13131d852b950643e"> 7102</a></span><span class="preprocessor">#define FSMC_BCR4_MTYP_0 (0x1UL << FSMC_BCR4_MTYP_Pos) </span></div>
|
||
<div class="line"><a id="l07103" name="l07103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac5abffefdc124215182346aba701183"> 7103</a></span><span class="preprocessor">#define FSMC_BCR4_MTYP_1 (0x2UL << FSMC_BCR4_MTYP_Pos) </span></div>
|
||
<div class="line"><a id="l07105" name="l07105"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab06a48e2793af3cce3d0a32ee5622339"> 7105</a></span><span class="preprocessor">#define FSMC_BCR4_MWID_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07106" name="l07106"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad01b905b7a139494a1577694bb6401f"> 7106</a></span><span class="preprocessor">#define FSMC_BCR4_MWID_Msk (0x3UL << FSMC_BCR4_MWID_Pos) </span></div>
|
||
<div class="line"><a id="l07107" name="l07107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c4ce32ca454c42344cfe73f71abd274"> 7107</a></span><span class="preprocessor">#define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk </span></div>
|
||
<div class="line"><a id="l07108" name="l07108"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c8f397cfb1f07421abeaf3060f7a329"> 7108</a></span><span class="preprocessor">#define FSMC_BCR4_MWID_0 (0x1UL << FSMC_BCR4_MWID_Pos) </span></div>
|
||
<div class="line"><a id="l07109" name="l07109"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5cd3a31190eb0cea8a72b55d8369970"> 7109</a></span><span class="preprocessor">#define FSMC_BCR4_MWID_1 (0x2UL << FSMC_BCR4_MWID_Pos) </span></div>
|
||
<div class="line"><a id="l07111" name="l07111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga576f29ec9b1d7afa35bcecd8b974d8af"> 7111</a></span><span class="preprocessor">#define FSMC_BCR4_FACCEN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l07112" name="l07112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga887e51078b00ac24b3ac8a5ff1d2290c"> 7112</a></span><span class="preprocessor">#define FSMC_BCR4_FACCEN_Msk (0x1UL << FSMC_BCR4_FACCEN_Pos) </span></div>
|
||
<div class="line"><a id="l07113" name="l07113"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf769d7958a8c610ccca912600e61f30"> 7113</a></span><span class="preprocessor">#define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk </span></div>
|
||
<div class="line"><a id="l07114" name="l07114"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61065b18069c91ca4a92acba5d8e2815"> 7114</a></span><span class="preprocessor">#define FSMC_BCR4_BURSTEN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07115" name="l07115"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0adae69dfd0ea81a4e50501b4e71dcf1"> 7115</a></span><span class="preprocessor">#define FSMC_BCR4_BURSTEN_Msk (0x1UL << FSMC_BCR4_BURSTEN_Pos) </span></div>
|
||
<div class="line"><a id="l07116" name="l07116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c6ffdcee5dc3de1402bd8b644d6ecf4"> 7116</a></span><span class="preprocessor">#define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk </span></div>
|
||
<div class="line"><a id="l07117" name="l07117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0716fa00c0b7d9e694f1e4faa3b463af"> 7117</a></span><span class="preprocessor">#define FSMC_BCR4_WAITPOL_Pos (9U) </span></div>
|
||
<div class="line"><a id="l07118" name="l07118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf12e7172887f85904c50033b9d8b78fd"> 7118</a></span><span class="preprocessor">#define FSMC_BCR4_WAITPOL_Msk (0x1UL << FSMC_BCR4_WAITPOL_Pos) </span></div>
|
||
<div class="line"><a id="l07119" name="l07119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga485976f8857949064d060374031cad3d"> 7119</a></span><span class="preprocessor">#define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk </span></div>
|
||
<div class="line"><a id="l07120" name="l07120"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a74bbc78956ddc94627b5b987b05169"> 7120</a></span><span class="preprocessor">#define FSMC_BCR4_WRAPMOD_Pos (10U) </span></div>
|
||
<div class="line"><a id="l07121" name="l07121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6f39d62a63c9708594f0d9819d3ad2a"> 7121</a></span><span class="preprocessor">#define FSMC_BCR4_WRAPMOD_Msk (0x1UL << FSMC_BCR4_WRAPMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07122" name="l07122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa35333cfffc35c7948ee0aa0e5672c3c"> 7122</a></span><span class="preprocessor">#define FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk </span></div>
|
||
<div class="line"><a id="l07123" name="l07123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23b0e2f296dd78ec57b8f166cc59bf6b"> 7123</a></span><span class="preprocessor">#define FSMC_BCR4_WAITCFG_Pos (11U) </span></div>
|
||
<div class="line"><a id="l07124" name="l07124"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fe8c8ee1b76354cdd74bb024e2b036d"> 7124</a></span><span class="preprocessor">#define FSMC_BCR4_WAITCFG_Msk (0x1UL << FSMC_BCR4_WAITCFG_Pos) </span></div>
|
||
<div class="line"><a id="l07125" name="l07125"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11c35ab0ee9ee23a5352218b4b84a258"> 7125</a></span><span class="preprocessor">#define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk </span></div>
|
||
<div class="line"><a id="l07126" name="l07126"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee04969322aa460220249296cbecbc07"> 7126</a></span><span class="preprocessor">#define FSMC_BCR4_WREN_Pos (12U) </span></div>
|
||
<div class="line"><a id="l07127" name="l07127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3879a08367749ad58d7f17708998f28"> 7127</a></span><span class="preprocessor">#define FSMC_BCR4_WREN_Msk (0x1UL << FSMC_BCR4_WREN_Pos) </span></div>
|
||
<div class="line"><a id="l07128" name="l07128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf2eef4eb8e6bb99cace5145b6ad09ee"> 7128</a></span><span class="preprocessor">#define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk </span></div>
|
||
<div class="line"><a id="l07129" name="l07129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab597ed53b04db4a4f13b57a727b5624c"> 7129</a></span><span class="preprocessor">#define FSMC_BCR4_WAITEN_Pos (13U) </span></div>
|
||
<div class="line"><a id="l07130" name="l07130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55ba3588b86b81122eb8da69f0593741"> 7130</a></span><span class="preprocessor">#define FSMC_BCR4_WAITEN_Msk (0x1UL << FSMC_BCR4_WAITEN_Pos) </span></div>
|
||
<div class="line"><a id="l07131" name="l07131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga458727d27c2bc7cede05f6537bfc1bd8"> 7131</a></span><span class="preprocessor">#define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk </span></div>
|
||
<div class="line"><a id="l07132" name="l07132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63db0c5c207a432ae87a5881b163f000"> 7132</a></span><span class="preprocessor">#define FSMC_BCR4_EXTMOD_Pos (14U) </span></div>
|
||
<div class="line"><a id="l07133" name="l07133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8d523e6b38ea3647b831b65a596faca"> 7133</a></span><span class="preprocessor">#define FSMC_BCR4_EXTMOD_Msk (0x1UL << FSMC_BCR4_EXTMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07134" name="l07134"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6794966a05855913923294f5c2ab69ed"> 7134</a></span><span class="preprocessor">#define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk </span></div>
|
||
<div class="line"><a id="l07135" name="l07135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdb1dd068a4d2b956aef4fb973342e53"> 7135</a></span><span class="preprocessor">#define FSMC_BCR4_ASYNCWAIT_Pos (15U) </span></div>
|
||
<div class="line"><a id="l07136" name="l07136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga486c5a22b57dba36a2010257c92514ca"> 7136</a></span><span class="preprocessor">#define FSMC_BCR4_ASYNCWAIT_Msk (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos) </span></div>
|
||
<div class="line"><a id="l07137" name="l07137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga158eeaca2258bc25beae918d01e01dd8"> 7137</a></span><span class="preprocessor">#define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk </span></div>
|
||
<div class="line"><a id="l07138" name="l07138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6efaac5bbbd151e85dbb22176550eb75"> 7138</a></span><span class="preprocessor">#define FSMC_BCR4_CPSIZE_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07139" name="l07139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a79495e98a82e6895d4b51c66b9af59"> 7139</a></span><span class="preprocessor">#define FSMC_BCR4_CPSIZE_Msk (0x7UL << FSMC_BCR4_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l07140" name="l07140"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad40c68c7a7806c531d78af3ba712f0cd"> 7140</a></span><span class="preprocessor">#define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk </span></div>
|
||
<div class="line"><a id="l07141" name="l07141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga801fee8ca2fcd5c881f95fa7eb319160"> 7141</a></span><span class="preprocessor">#define FSMC_BCR4_CPSIZE_0 (0x1UL << FSMC_BCR4_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l07142" name="l07142"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7615f0150d36affdecdb05bdff084020"> 7142</a></span><span class="preprocessor">#define FSMC_BCR4_CPSIZE_1 (0x2UL << FSMC_BCR4_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l07143" name="l07143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59bdb0695f948fa7369451fc38380c12"> 7143</a></span><span class="preprocessor">#define FSMC_BCR4_CPSIZE_2 (0x4UL << FSMC_BCR4_CPSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l07144" name="l07144"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad81ccd2059e86d3108e3c71e5075f936"> 7144</a></span><span class="preprocessor">#define FSMC_BCR4_CBURSTRW_Pos (19U) </span></div>
|
||
<div class="line"><a id="l07145" name="l07145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e8b3d5023ae64207d965b9d26816b72"> 7145</a></span><span class="preprocessor">#define FSMC_BCR4_CBURSTRW_Msk (0x1UL << FSMC_BCR4_CBURSTRW_Pos) </span></div>
|
||
<div class="line"><a id="l07146" name="l07146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19293300b8230e38afa1c16c526b3f29"> 7146</a></span><span class="preprocessor">#define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk </span></div>
|
||
<div class="line"><a id="l07148" name="l07148"></a><span class="lineno"> 7148</span><span class="comment">/****************** Bit definition for FSMC_BTR1 register ******************/</span></div>
|
||
<div class="line"><a id="l07149" name="l07149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2b6109a964212ec400829faa37e113a"> 7149</a></span><span class="preprocessor">#define FSMC_BTR1_ADDSET_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07150" name="l07150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b91cf869f5ab06c40ad7620ae59ffa8"> 7150</a></span><span class="preprocessor">#define FSMC_BTR1_ADDSET_Msk (0xFUL << FSMC_BTR1_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07151" name="l07151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab457e5d3a33d80db3ad070b1cf57669a"> 7151</a></span><span class="preprocessor">#define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk </span></div>
|
||
<div class="line"><a id="l07152" name="l07152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae29ca17c63df62cc12c06e6cfa3429e3"> 7152</a></span><span class="preprocessor">#define FSMC_BTR1_ADDSET_0 (0x1UL << FSMC_BTR1_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07153" name="l07153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefb98ce348ba665f122e44ddc0390b45"> 7153</a></span><span class="preprocessor">#define FSMC_BTR1_ADDSET_1 (0x2UL << FSMC_BTR1_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07154" name="l07154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5e5c5b00c91aca1cc266622d3f30bf0"> 7154</a></span><span class="preprocessor">#define FSMC_BTR1_ADDSET_2 (0x4UL << FSMC_BTR1_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07155" name="l07155"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f0105afe671cd62730cf879072c80f3"> 7155</a></span><span class="preprocessor">#define FSMC_BTR1_ADDSET_3 (0x8UL << FSMC_BTR1_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07157" name="l07157"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8d311b7f571c7f1b55638b62da5a5a1"> 7157</a></span><span class="preprocessor">#define FSMC_BTR1_ADDHLD_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07158" name="l07158"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d1abafea7ca6c3eecc720b4e9e15b3e"> 7158</a></span><span class="preprocessor">#define FSMC_BTR1_ADDHLD_Msk (0xFUL << FSMC_BTR1_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07159" name="l07159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc4a3860c48a62ff0290622e1937072d"> 7159</a></span><span class="preprocessor">#define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk </span></div>
|
||
<div class="line"><a id="l07160" name="l07160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga222a16d5a1a8deebaf39a96d94d3c3f0"> 7160</a></span><span class="preprocessor">#define FSMC_BTR1_ADDHLD_0 (0x1UL << FSMC_BTR1_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07161" name="l07161"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ad1f9164644c4ff4c6ae5a655478abc"> 7161</a></span><span class="preprocessor">#define FSMC_BTR1_ADDHLD_1 (0x2UL << FSMC_BTR1_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07162" name="l07162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f9d68df0fd84b77342a565e9faad929"> 7162</a></span><span class="preprocessor">#define FSMC_BTR1_ADDHLD_2 (0x4UL << FSMC_BTR1_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07163" name="l07163"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e88e45163e76f529b5a94937526f45c"> 7163</a></span><span class="preprocessor">#define FSMC_BTR1_ADDHLD_3 (0x8UL << FSMC_BTR1_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07165" name="l07165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c6cf527aad7fcdb2e57ef4483cd4e91"> 7165</a></span><span class="preprocessor">#define FSMC_BTR1_DATAST_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07166" name="l07166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0a503b09190898423d53534300bf397"> 7166</a></span><span class="preprocessor">#define FSMC_BTR1_DATAST_Msk (0xFFUL << FSMC_BTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07167" name="l07167"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae39175370a991b500962fd084230e389"> 7167</a></span><span class="preprocessor">#define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk </span></div>
|
||
<div class="line"><a id="l07168" name="l07168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4488a428f33d96263a00a30af42b849b"> 7168</a></span><span class="preprocessor">#define FSMC_BTR1_DATAST_0 (0x01UL << FSMC_BTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07169" name="l07169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad53bd6a1decfafdb420a37453b3b5545"> 7169</a></span><span class="preprocessor">#define FSMC_BTR1_DATAST_1 (0x02UL << FSMC_BTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07170" name="l07170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacce8f6cf5a9ba24943b3e762bde00aee"> 7170</a></span><span class="preprocessor">#define FSMC_BTR1_DATAST_2 (0x04UL << FSMC_BTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07171" name="l07171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99638cc2cbe0dead029c201e5f30c3a8"> 7171</a></span><span class="preprocessor">#define FSMC_BTR1_DATAST_3 (0x08UL << FSMC_BTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07172" name="l07172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46c64dd27460218f4398f84f8a1eb050"> 7172</a></span><span class="preprocessor">#define FSMC_BTR1_DATAST_4 (0x10UL << FSMC_BTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07173" name="l07173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d19491b3e729c6aac0fea41cc62b695"> 7173</a></span><span class="preprocessor">#define FSMC_BTR1_DATAST_5 (0x20UL << FSMC_BTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07174" name="l07174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50c28cb325d28369d1a9ef764c63887b"> 7174</a></span><span class="preprocessor">#define FSMC_BTR1_DATAST_6 (0x40UL << FSMC_BTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07175" name="l07175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f54453aa732f52cbb5a1562d2eddd23"> 7175</a></span><span class="preprocessor">#define FSMC_BTR1_DATAST_7 (0x80UL << FSMC_BTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07177" name="l07177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga164a173346248449423d03e8d1d40a31"> 7177</a></span><span class="preprocessor">#define FSMC_BTR1_BUSTURN_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07178" name="l07178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedd0e3c6b2b476a6e6c0578a2bdf3d5d"> 7178</a></span><span class="preprocessor">#define FSMC_BTR1_BUSTURN_Msk (0xFUL << FSMC_BTR1_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07179" name="l07179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ec9346bbaf845f1dffe33c4a625c0ac"> 7179</a></span><span class="preprocessor">#define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk </span></div>
|
||
<div class="line"><a id="l07180" name="l07180"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c1578a85c4f2cef9e034c7b5da6d454"> 7180</a></span><span class="preprocessor">#define FSMC_BTR1_BUSTURN_0 (0x1UL << FSMC_BTR1_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07181" name="l07181"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf873cbfe4827496215eb08bb33ae4784"> 7181</a></span><span class="preprocessor">#define FSMC_BTR1_BUSTURN_1 (0x2UL << FSMC_BTR1_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07182" name="l07182"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad768d3ff0a5159e552663c9489b977f6"> 7182</a></span><span class="preprocessor">#define FSMC_BTR1_BUSTURN_2 (0x4UL << FSMC_BTR1_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07183" name="l07183"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3ecfd25fb64efb3745ee96b2877a017"> 7183</a></span><span class="preprocessor">#define FSMC_BTR1_BUSTURN_3 (0x8UL << FSMC_BTR1_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07185" name="l07185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga514bdebcbaf4a3e4d0ede4fef6bb0dd7"> 7185</a></span><span class="preprocessor">#define FSMC_BTR1_CLKDIV_Pos (20U) </span></div>
|
||
<div class="line"><a id="l07186" name="l07186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c720b329720574b2c8d30c072f78716"> 7186</a></span><span class="preprocessor">#define FSMC_BTR1_CLKDIV_Msk (0xFUL << FSMC_BTR1_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07187" name="l07187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7c4dbd43df84559e30a9c332b265ad5"> 7187</a></span><span class="preprocessor">#define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk </span></div>
|
||
<div class="line"><a id="l07188" name="l07188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe9c9e09de00afad666ace28c608032f"> 7188</a></span><span class="preprocessor">#define FSMC_BTR1_CLKDIV_0 (0x1UL << FSMC_BTR1_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07189" name="l07189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafffebd7a0cf6e6d80b65804c2c50ce62"> 7189</a></span><span class="preprocessor">#define FSMC_BTR1_CLKDIV_1 (0x2UL << FSMC_BTR1_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07190" name="l07190"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43afa754305cc1a7ff3075cdd4309990"> 7190</a></span><span class="preprocessor">#define FSMC_BTR1_CLKDIV_2 (0x4UL << FSMC_BTR1_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07191" name="l07191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68a146aec5d723a84945ae6da6c0692f"> 7191</a></span><span class="preprocessor">#define FSMC_BTR1_CLKDIV_3 (0x8UL << FSMC_BTR1_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07193" name="l07193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bc0aee3036c6ddba4a1e66b92b0913c"> 7193</a></span><span class="preprocessor">#define FSMC_BTR1_DATLAT_Pos (24U) </span></div>
|
||
<div class="line"><a id="l07194" name="l07194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19c7f2d933e94d7f60c22027558f2a23"> 7194</a></span><span class="preprocessor">#define FSMC_BTR1_DATLAT_Msk (0xFUL << FSMC_BTR1_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07195" name="l07195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ef6dcccdb11a1b094966be0c019124b"> 7195</a></span><span class="preprocessor">#define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk </span></div>
|
||
<div class="line"><a id="l07196" name="l07196"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2d832593697ba108d99a97e4fdfd159"> 7196</a></span><span class="preprocessor">#define FSMC_BTR1_DATLAT_0 (0x1UL << FSMC_BTR1_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07197" name="l07197"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a7e4efc546c1c9d16c750a4542e1c55"> 7197</a></span><span class="preprocessor">#define FSMC_BTR1_DATLAT_1 (0x2UL << FSMC_BTR1_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07198" name="l07198"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22e7d41e0f94ab896c6eea199eb0aef1"> 7198</a></span><span class="preprocessor">#define FSMC_BTR1_DATLAT_2 (0x4UL << FSMC_BTR1_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07199" name="l07199"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b42f22fc488e0ed0d06832118773123"> 7199</a></span><span class="preprocessor">#define FSMC_BTR1_DATLAT_3 (0x8UL << FSMC_BTR1_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07201" name="l07201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabfe73fd49dee3d6123e7be78f49e8dce"> 7201</a></span><span class="preprocessor">#define FSMC_BTR1_ACCMOD_Pos (28U) </span></div>
|
||
<div class="line"><a id="l07202" name="l07202"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97f35ab9565eeb82324ab5015237cdbd"> 7202</a></span><span class="preprocessor">#define FSMC_BTR1_ACCMOD_Msk (0x3UL << FSMC_BTR1_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07203" name="l07203"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga027548b6b5971a2c56558932c956fa4c"> 7203</a></span><span class="preprocessor">#define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk </span></div>
|
||
<div class="line"><a id="l07204" name="l07204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf77aa4936dc4f35d1b426d147c643c80"> 7204</a></span><span class="preprocessor">#define FSMC_BTR1_ACCMOD_0 (0x1UL << FSMC_BTR1_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07205" name="l07205"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b336cf3ae23cfda19895927b63af558"> 7205</a></span><span class="preprocessor">#define FSMC_BTR1_ACCMOD_1 (0x2UL << FSMC_BTR1_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07207" name="l07207"></a><span class="lineno"> 7207</span><span class="comment">/****************** Bit definition for FSMC_BTR2 register *******************/</span></div>
|
||
<div class="line"><a id="l07208" name="l07208"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58b9a54aabd6cc507c6ab1b5fb134727"> 7208</a></span><span class="preprocessor">#define FSMC_BTR2_ADDSET_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07209" name="l07209"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga903bf76eee82e88b1cefc9d1ed1aa4c7"> 7209</a></span><span class="preprocessor">#define FSMC_BTR2_ADDSET_Msk (0xFUL << FSMC_BTR2_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07210" name="l07210"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23697810b99730ddf52834a5066c1ba5"> 7210</a></span><span class="preprocessor">#define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk </span></div>
|
||
<div class="line"><a id="l07211" name="l07211"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga827398dc098f2d08bb77a04b2e7d6ba3"> 7211</a></span><span class="preprocessor">#define FSMC_BTR2_ADDSET_0 (0x1UL << FSMC_BTR2_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07212" name="l07212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b40f47f2db0db78de6fe2df58b5d591"> 7212</a></span><span class="preprocessor">#define FSMC_BTR2_ADDSET_1 (0x2UL << FSMC_BTR2_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07213" name="l07213"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga558185a28aeedbb098890348a041a74d"> 7213</a></span><span class="preprocessor">#define FSMC_BTR2_ADDSET_2 (0x4UL << FSMC_BTR2_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07214" name="l07214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbd4d42459a990825b61962d9118cd7b"> 7214</a></span><span class="preprocessor">#define FSMC_BTR2_ADDSET_3 (0x8UL << FSMC_BTR2_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07216" name="l07216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2be5c64e803c9fe4378275e2acd1b095"> 7216</a></span><span class="preprocessor">#define FSMC_BTR2_ADDHLD_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07217" name="l07217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe23e10bb28cb59dced9d9db5a4106db"> 7217</a></span><span class="preprocessor">#define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07218" name="l07218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac37c974d0260ba1dbd1acaf6fceb425c"> 7218</a></span><span class="preprocessor">#define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk </span></div>
|
||
<div class="line"><a id="l07219" name="l07219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbf56fc3a549d1e68d56e1587123bd27"> 7219</a></span><span class="preprocessor">#define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07220" name="l07220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b7d19f02444ce8b3286d44258c6caef"> 7220</a></span><span class="preprocessor">#define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07221" name="l07221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e9433e15e301d5d3f0dd6b73c9db2f7"> 7221</a></span><span class="preprocessor">#define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07222" name="l07222"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc538e46145ed4947194f3ad63e211b7"> 7222</a></span><span class="preprocessor">#define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07224" name="l07224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b6e90fc9b165365c147924675deb339"> 7224</a></span><span class="preprocessor">#define FSMC_BTR2_DATAST_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07225" name="l07225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35f2c0de6b8e42c44f1006a29507ce07"> 7225</a></span><span class="preprocessor">#define FSMC_BTR2_DATAST_Msk (0xFFUL << FSMC_BTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07226" name="l07226"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe1d3fe096ea53ea073b78bd6ddbff58"> 7226</a></span><span class="preprocessor">#define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk </span></div>
|
||
<div class="line"><a id="l07227" name="l07227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa066dab45a22ebd3a7102b92dcd251bd"> 7227</a></span><span class="preprocessor">#define FSMC_BTR2_DATAST_0 (0x01UL << FSMC_BTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07228" name="l07228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68c15ca5fdd13efb5499f0e86bd5bc88"> 7228</a></span><span class="preprocessor">#define FSMC_BTR2_DATAST_1 (0x02UL << FSMC_BTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07229" name="l07229"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36cfe553d431ca6976f0d36c73045836"> 7229</a></span><span class="preprocessor">#define FSMC_BTR2_DATAST_2 (0x04UL << FSMC_BTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07230" name="l07230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga874499b29d2b72a75265f16a2d8ed834"> 7230</a></span><span class="preprocessor">#define FSMC_BTR2_DATAST_3 (0x08UL << FSMC_BTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07231" name="l07231"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4856fb97d7d04d612f24d7267e6c9b76"> 7231</a></span><span class="preprocessor">#define FSMC_BTR2_DATAST_4 (0x10UL << FSMC_BTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07232" name="l07232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb50ada649984a8bde5535cc3163344c"> 7232</a></span><span class="preprocessor">#define FSMC_BTR2_DATAST_5 (0x20UL << FSMC_BTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07233" name="l07233"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac4784549001168b5ab21a93852100d0"> 7233</a></span><span class="preprocessor">#define FSMC_BTR2_DATAST_6 (0x40UL << FSMC_BTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07234" name="l07234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bdd6994cb33a10447cbce5c563746da"> 7234</a></span><span class="preprocessor">#define FSMC_BTR2_DATAST_7 (0x80UL << FSMC_BTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07236" name="l07236"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4f38b835e2730a7d9e817474b4a304c"> 7236</a></span><span class="preprocessor">#define FSMC_BTR2_BUSTURN_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07237" name="l07237"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92af3fcfa317680d6fc598faa951d8e9"> 7237</a></span><span class="preprocessor">#define FSMC_BTR2_BUSTURN_Msk (0xFUL << FSMC_BTR2_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07238" name="l07238"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ae7c94522af51d2f96a0fa715dfa9b0"> 7238</a></span><span class="preprocessor">#define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk </span></div>
|
||
<div class="line"><a id="l07239" name="l07239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2617a99e5eab8b31ff168557f93852a3"> 7239</a></span><span class="preprocessor">#define FSMC_BTR2_BUSTURN_0 (0x1UL << FSMC_BTR2_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07240" name="l07240"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83871fa5cde9d72ec840d29d43aa2e57"> 7240</a></span><span class="preprocessor">#define FSMC_BTR2_BUSTURN_1 (0x2UL << FSMC_BTR2_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07241" name="l07241"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacada2902f8612df1e5ac6e224bcf8d3c"> 7241</a></span><span class="preprocessor">#define FSMC_BTR2_BUSTURN_2 (0x4UL << FSMC_BTR2_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07242" name="l07242"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66ad543195f36fdb3efdf7550381f982"> 7242</a></span><span class="preprocessor">#define FSMC_BTR2_BUSTURN_3 (0x8UL << FSMC_BTR2_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07244" name="l07244"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f1719a782602f2ad5737abd57bc866a"> 7244</a></span><span class="preprocessor">#define FSMC_BTR2_CLKDIV_Pos (20U) </span></div>
|
||
<div class="line"><a id="l07245" name="l07245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe9c74d5bceaaa34ce11040cff130c7c"> 7245</a></span><span class="preprocessor">#define FSMC_BTR2_CLKDIV_Msk (0xFUL << FSMC_BTR2_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07246" name="l07246"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37fdb25c494cf314cb680f84c5e0a503"> 7246</a></span><span class="preprocessor">#define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk </span></div>
|
||
<div class="line"><a id="l07247" name="l07247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ac8729c8ac330f6ade93a6a15a4ba70"> 7247</a></span><span class="preprocessor">#define FSMC_BTR2_CLKDIV_0 (0x1UL << FSMC_BTR2_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07248" name="l07248"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31920e8bf2d83ad3c2849f8e942bb6e4"> 7248</a></span><span class="preprocessor">#define FSMC_BTR2_CLKDIV_1 (0x2UL << FSMC_BTR2_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07249" name="l07249"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5ba3172687049c687e3a38ec08d6c5a"> 7249</a></span><span class="preprocessor">#define FSMC_BTR2_CLKDIV_2 (0x4UL << FSMC_BTR2_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07250" name="l07250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga453c2a90dc3340596c9d34672cede6a0"> 7250</a></span><span class="preprocessor">#define FSMC_BTR2_CLKDIV_3 (0x8UL << FSMC_BTR2_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07252" name="l07252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3766782905697c6b350ed00bc873baa9"> 7252</a></span><span class="preprocessor">#define FSMC_BTR2_DATLAT_Pos (24U) </span></div>
|
||
<div class="line"><a id="l07253" name="l07253"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3518166716c8654e8c0ad881bf0d2c66"> 7253</a></span><span class="preprocessor">#define FSMC_BTR2_DATLAT_Msk (0xFUL << FSMC_BTR2_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07254" name="l07254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3247db1653b31df0c34ab7898400bb5"> 7254</a></span><span class="preprocessor">#define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk </span></div>
|
||
<div class="line"><a id="l07255" name="l07255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0510047c932d2833f6cbe0a4a5d7b9b5"> 7255</a></span><span class="preprocessor">#define FSMC_BTR2_DATLAT_0 (0x1UL << FSMC_BTR2_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07256" name="l07256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e1852b706b3c719c0eab8ef863b39e0"> 7256</a></span><span class="preprocessor">#define FSMC_BTR2_DATLAT_1 (0x2UL << FSMC_BTR2_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07257" name="l07257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ace24f50d1c51c978af55d47c13c0e9"> 7257</a></span><span class="preprocessor">#define FSMC_BTR2_DATLAT_2 (0x4UL << FSMC_BTR2_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07258" name="l07258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99389b63c4dee3c54aa1de36a4119add"> 7258</a></span><span class="preprocessor">#define FSMC_BTR2_DATLAT_3 (0x8UL << FSMC_BTR2_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07260" name="l07260"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9cba11e01cd8e90b1e56a3d52c44025"> 7260</a></span><span class="preprocessor">#define FSMC_BTR2_ACCMOD_Pos (28U) </span></div>
|
||
<div class="line"><a id="l07261" name="l07261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad11258e9138b98bf6387167f0a2645f9"> 7261</a></span><span class="preprocessor">#define FSMC_BTR2_ACCMOD_Msk (0x3UL << FSMC_BTR2_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07262" name="l07262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07b93600977cde6e31a9464f87606043"> 7262</a></span><span class="preprocessor">#define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk </span></div>
|
||
<div class="line"><a id="l07263" name="l07263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9383d89d5e557a166f6b8290892b89b3"> 7263</a></span><span class="preprocessor">#define FSMC_BTR2_ACCMOD_0 (0x1UL << FSMC_BTR2_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07264" name="l07264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad200e1dc2d1835e3dc0fa8f0483eb2c0"> 7264</a></span><span class="preprocessor">#define FSMC_BTR2_ACCMOD_1 (0x2UL << FSMC_BTR2_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07266" name="l07266"></a><span class="lineno"> 7266</span><span class="comment">/******************* Bit definition for FSMC_BTR3 register *******************/</span></div>
|
||
<div class="line"><a id="l07267" name="l07267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f6c91220bbb34e5cb90903df17cfd63"> 7267</a></span><span class="preprocessor">#define FSMC_BTR3_ADDSET_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07268" name="l07268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a2fd577c6b176ec1d1ed35f4230ea74"> 7268</a></span><span class="preprocessor">#define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07269" name="l07269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3e55daf436a25fadae7384611aa0f89"> 7269</a></span><span class="preprocessor">#define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk </span></div>
|
||
<div class="line"><a id="l07270" name="l07270"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6a21211dd7a3445e944af0fe1a4b600"> 7270</a></span><span class="preprocessor">#define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07271" name="l07271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51c23d36fa8e7e38048d94830bf0f74f"> 7271</a></span><span class="preprocessor">#define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07272" name="l07272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93be4171cb7d0b66d8d4d12e61b07b88"> 7272</a></span><span class="preprocessor">#define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07273" name="l07273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab01cf0b1c88857669d10fee8d7ba4d85"> 7273</a></span><span class="preprocessor">#define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07275" name="l07275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4fb45db8d202b537ad7ca41ed70f459"> 7275</a></span><span class="preprocessor">#define FSMC_BTR3_ADDHLD_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07276" name="l07276"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bf5884c4cc7c453908e3ac5272244b7"> 7276</a></span><span class="preprocessor">#define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07277" name="l07277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7833ee760b2400e6fb483b1d83cbdff3"> 7277</a></span><span class="preprocessor">#define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk </span></div>
|
||
<div class="line"><a id="l07278" name="l07278"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad417ccae1c4018d0ff5c76c942aeb2ca"> 7278</a></span><span class="preprocessor">#define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07279" name="l07279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60d0ae6af13ef088367cef06c7f207d3"> 7279</a></span><span class="preprocessor">#define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07280" name="l07280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac029aaed48e2a3e2eedf767fe0ce0b92"> 7280</a></span><span class="preprocessor">#define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07281" name="l07281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b6aab5907bc42e140ca5a4d60fcd64c"> 7281</a></span><span class="preprocessor">#define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07283" name="l07283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga524942cc9d0eaf2095a6598db32db389"> 7283</a></span><span class="preprocessor">#define FSMC_BTR3_DATAST_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07284" name="l07284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf38dfdbab53cbef7b90eb2503114f121"> 7284</a></span><span class="preprocessor">#define FSMC_BTR3_DATAST_Msk (0xFFUL << FSMC_BTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07285" name="l07285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e9ac671a510ee06e86c41d7876ffe10"> 7285</a></span><span class="preprocessor">#define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk </span></div>
|
||
<div class="line"><a id="l07286" name="l07286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65fe87d29c1a4ee0b08014ed8e0423e1"> 7286</a></span><span class="preprocessor">#define FSMC_BTR3_DATAST_0 (0x01UL << FSMC_BTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07287" name="l07287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad33e3df5c80255cb5e11ba427e9c224f"> 7287</a></span><span class="preprocessor">#define FSMC_BTR3_DATAST_1 (0x02UL << FSMC_BTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07288" name="l07288"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a31f070e41c6785ebc606d4f25d103a"> 7288</a></span><span class="preprocessor">#define FSMC_BTR3_DATAST_2 (0x04UL << FSMC_BTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07289" name="l07289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad220fbd264261a37eac09d4f6c0b79a2"> 7289</a></span><span class="preprocessor">#define FSMC_BTR3_DATAST_3 (0x08UL << FSMC_BTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07290" name="l07290"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab78ca925e07c24a308b1e603ed42aae1"> 7290</a></span><span class="preprocessor">#define FSMC_BTR3_DATAST_4 (0x10UL << FSMC_BTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07291" name="l07291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b61775591ffb8faef03a13435fd98b8"> 7291</a></span><span class="preprocessor">#define FSMC_BTR3_DATAST_5 (0x20UL << FSMC_BTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07292" name="l07292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d58607a3de993f0f7227a14b81ab56c"> 7292</a></span><span class="preprocessor">#define FSMC_BTR3_DATAST_6 (0x40UL << FSMC_BTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07293" name="l07293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10dc7226824fa6ad00380417b3ba095d"> 7293</a></span><span class="preprocessor">#define FSMC_BTR3_DATAST_7 (0x80UL << FSMC_BTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07295" name="l07295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b7b831c25c61676309f80788ec1a9e9"> 7295</a></span><span class="preprocessor">#define FSMC_BTR3_BUSTURN_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07296" name="l07296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a87c9110d709faefbf2d08ee49ca874"> 7296</a></span><span class="preprocessor">#define FSMC_BTR3_BUSTURN_Msk (0xFUL << FSMC_BTR3_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07297" name="l07297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8a3ad9f940c6942682d8d97b1eb0ca4"> 7297</a></span><span class="preprocessor">#define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk </span></div>
|
||
<div class="line"><a id="l07298" name="l07298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga739f2db66e52626aa9a5ee02c11d7a34"> 7298</a></span><span class="preprocessor">#define FSMC_BTR3_BUSTURN_0 (0x1UL << FSMC_BTR3_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07299" name="l07299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e4c4102ea6e6cf2082e78168edfc18e"> 7299</a></span><span class="preprocessor">#define FSMC_BTR3_BUSTURN_1 (0x2UL << FSMC_BTR3_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07300" name="l07300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5eab2601ae3cd040bf44feb3e70c459"> 7300</a></span><span class="preprocessor">#define FSMC_BTR3_BUSTURN_2 (0x4UL << FSMC_BTR3_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07301" name="l07301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf61e23804e0fa3ca45f851ca98de371"> 7301</a></span><span class="preprocessor">#define FSMC_BTR3_BUSTURN_3 (0x8UL << FSMC_BTR3_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07303" name="l07303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada052eafe7f4ee032f364b82040350a9"> 7303</a></span><span class="preprocessor">#define FSMC_BTR3_CLKDIV_Pos (20U) </span></div>
|
||
<div class="line"><a id="l07304" name="l07304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga050d3fd57381342b9c5d1153623e5d64"> 7304</a></span><span class="preprocessor">#define FSMC_BTR3_CLKDIV_Msk (0xFUL << FSMC_BTR3_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07305" name="l07305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47a8d8e279c50995143ecf4124580703"> 7305</a></span><span class="preprocessor">#define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk </span></div>
|
||
<div class="line"><a id="l07306" name="l07306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd9c93b0ee64856981394a63d6a3a964"> 7306</a></span><span class="preprocessor">#define FSMC_BTR3_CLKDIV_0 (0x1UL << FSMC_BTR3_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07307" name="l07307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98fa7611b4ae197ab25cdf1cae9f8ee1"> 7307</a></span><span class="preprocessor">#define FSMC_BTR3_CLKDIV_1 (0x2UL << FSMC_BTR3_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07308" name="l07308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf806c044b2a3d1417acc79907dcaef4b"> 7308</a></span><span class="preprocessor">#define FSMC_BTR3_CLKDIV_2 (0x4UL << FSMC_BTR3_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07309" name="l07309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9bf0683d046f9bcfb0d55a065ae69ab"> 7309</a></span><span class="preprocessor">#define FSMC_BTR3_CLKDIV_3 (0x8UL << FSMC_BTR3_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07311" name="l07311"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga949454e87f17316a0253839e17ebacc6"> 7311</a></span><span class="preprocessor">#define FSMC_BTR3_DATLAT_Pos (24U) </span></div>
|
||
<div class="line"><a id="l07312" name="l07312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e8b7682eb997746f807814f4d41ca6b"> 7312</a></span><span class="preprocessor">#define FSMC_BTR3_DATLAT_Msk (0xFUL << FSMC_BTR3_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07313" name="l07313"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa88a80458ddd56b0dfa7cf3599b986dd"> 7313</a></span><span class="preprocessor">#define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk </span></div>
|
||
<div class="line"><a id="l07314" name="l07314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga655083fdb0e563b9a4d6ea589194ba02"> 7314</a></span><span class="preprocessor">#define FSMC_BTR3_DATLAT_0 (0x1UL << FSMC_BTR3_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07315" name="l07315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga486280713c8f07d7033bce4e74825130"> 7315</a></span><span class="preprocessor">#define FSMC_BTR3_DATLAT_1 (0x2UL << FSMC_BTR3_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07316" name="l07316"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8314e30c84dccd983de04fdeeb57c360"> 7316</a></span><span class="preprocessor">#define FSMC_BTR3_DATLAT_2 (0x4UL << FSMC_BTR3_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07317" name="l07317"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7e7da5269a2dac164c9d1d01da2bc28"> 7317</a></span><span class="preprocessor">#define FSMC_BTR3_DATLAT_3 (0x8UL << FSMC_BTR3_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07319" name="l07319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61e6d33a30b831902487e19a9d79bed0"> 7319</a></span><span class="preprocessor">#define FSMC_BTR3_ACCMOD_Pos (28U) </span></div>
|
||
<div class="line"><a id="l07320" name="l07320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02766e5c7ca9549655ea80d68267062e"> 7320</a></span><span class="preprocessor">#define FSMC_BTR3_ACCMOD_Msk (0x3UL << FSMC_BTR3_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07321" name="l07321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56c8f213e437ceed2140f2c16a0416cd"> 7321</a></span><span class="preprocessor">#define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk </span></div>
|
||
<div class="line"><a id="l07322" name="l07322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d50e71940995d42c5f9fadcb7cd61f2"> 7322</a></span><span class="preprocessor">#define FSMC_BTR3_ACCMOD_0 (0x1UL << FSMC_BTR3_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07323" name="l07323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8bbfd5e08b73d1c5de53ee0ff0ddb9a"> 7323</a></span><span class="preprocessor">#define FSMC_BTR3_ACCMOD_1 (0x2UL << FSMC_BTR3_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07325" name="l07325"></a><span class="lineno"> 7325</span><span class="comment">/****************** Bit definition for FSMC_BTR4 register *******************/</span></div>
|
||
<div class="line"><a id="l07326" name="l07326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabeff2f8b714d12899beab5530219676b"> 7326</a></span><span class="preprocessor">#define FSMC_BTR4_ADDSET_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07327" name="l07327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ffb05b35bc25ca9f5f8629e241482c2"> 7327</a></span><span class="preprocessor">#define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07328" name="l07328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab44cc2146b4cf6bc8f43292512fd8cf8"> 7328</a></span><span class="preprocessor">#define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk </span></div>
|
||
<div class="line"><a id="l07329" name="l07329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0ee1ab3716b0ab1a4e7b51234af7c63"> 7329</a></span><span class="preprocessor">#define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07330" name="l07330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd427c001c5b17a3e083c81f6b228a50"> 7330</a></span><span class="preprocessor">#define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07331" name="l07331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae722fdaa69bfb7622aa80c82e3772949"> 7331</a></span><span class="preprocessor">#define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07332" name="l07332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f8ab4a1c7fe6e7dc2b093add88c274e"> 7332</a></span><span class="preprocessor">#define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07334" name="l07334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3d440dee3fe200e9aaeaa5ca74c7cda"> 7334</a></span><span class="preprocessor">#define FSMC_BTR4_ADDHLD_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07335" name="l07335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaabb5da557aa89d3f786f2bae2fb3bf0"> 7335</a></span><span class="preprocessor">#define FSMC_BTR4_ADDHLD_Msk (0xFUL << FSMC_BTR4_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07336" name="l07336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e52ae9a5d59507bdf9f4f9da19444ed"> 7336</a></span><span class="preprocessor">#define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk </span></div>
|
||
<div class="line"><a id="l07337" name="l07337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf6200f13c3eed1e9646750897a987a2"> 7337</a></span><span class="preprocessor">#define FSMC_BTR4_ADDHLD_0 (0x1UL << FSMC_BTR4_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07338" name="l07338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0803bc2ad60138e0eef53a53ca5bf537"> 7338</a></span><span class="preprocessor">#define FSMC_BTR4_ADDHLD_1 (0x2UL << FSMC_BTR4_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07339" name="l07339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga893711250b9d3ea2e5e48ca53d1e0147"> 7339</a></span><span class="preprocessor">#define FSMC_BTR4_ADDHLD_2 (0x4UL << FSMC_BTR4_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07340" name="l07340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75c73d4bb0ddcac383ca610a604d95b3"> 7340</a></span><span class="preprocessor">#define FSMC_BTR4_ADDHLD_3 (0x8UL << FSMC_BTR4_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07342" name="l07342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66d0e68db7568649671e7b0338acb688"> 7342</a></span><span class="preprocessor">#define FSMC_BTR4_DATAST_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07343" name="l07343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab99647a6ac8c924ad739bc5cc7244c01"> 7343</a></span><span class="preprocessor">#define FSMC_BTR4_DATAST_Msk (0xFFUL << FSMC_BTR4_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07344" name="l07344"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c28625ee031527a29f7cb7db1bb97cf"> 7344</a></span><span class="preprocessor">#define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk </span></div>
|
||
<div class="line"><a id="l07345" name="l07345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdb0212604c6c58c9524adc7931e2897"> 7345</a></span><span class="preprocessor">#define FSMC_BTR4_DATAST_0 (0x01UL << FSMC_BTR4_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07346" name="l07346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2353d753ca5532703b4f822b7d2a7382"> 7346</a></span><span class="preprocessor">#define FSMC_BTR4_DATAST_1 (0x02UL << FSMC_BTR4_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07347" name="l07347"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d82a6f3fcf69d6b96968118db7b8216"> 7347</a></span><span class="preprocessor">#define FSMC_BTR4_DATAST_2 (0x04UL << FSMC_BTR4_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07348" name="l07348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e0860f92bb204c4b5902d3e34b8b30a"> 7348</a></span><span class="preprocessor">#define FSMC_BTR4_DATAST_3 (0x08UL << FSMC_BTR4_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07349" name="l07349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d6f871ca941d2beed194d2fc5190183"> 7349</a></span><span class="preprocessor">#define FSMC_BTR4_DATAST_4 (0x10UL << FSMC_BTR4_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07350" name="l07350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa798a7170769793b25d5cc37e9eff679"> 7350</a></span><span class="preprocessor">#define FSMC_BTR4_DATAST_5 (0x20UL << FSMC_BTR4_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07351" name="l07351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4c89f39ac5a74bdd3fc406da173fe79"> 7351</a></span><span class="preprocessor">#define FSMC_BTR4_DATAST_6 (0x40UL << FSMC_BTR4_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07352" name="l07352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga633b76f7fce6507cf044dcb3d82a0d8d"> 7352</a></span><span class="preprocessor">#define FSMC_BTR4_DATAST_7 (0x80UL << FSMC_BTR4_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07354" name="l07354"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98966c488a394376e2b3bff182317cf6"> 7354</a></span><span class="preprocessor">#define FSMC_BTR4_BUSTURN_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07355" name="l07355"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa72c6ff1ec6f4fb7dee9a109ddc9835f"> 7355</a></span><span class="preprocessor">#define FSMC_BTR4_BUSTURN_Msk (0xFUL << FSMC_BTR4_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07356" name="l07356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga207a9eedfc1b244c393be3c34ea60a15"> 7356</a></span><span class="preprocessor">#define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk </span></div>
|
||
<div class="line"><a id="l07357" name="l07357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dec1fa50fca6639be7179d445aacfe4"> 7357</a></span><span class="preprocessor">#define FSMC_BTR4_BUSTURN_0 (0x1UL << FSMC_BTR4_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07358" name="l07358"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1db211382068251dc5cfe44a175e639"> 7358</a></span><span class="preprocessor">#define FSMC_BTR4_BUSTURN_1 (0x2UL << FSMC_BTR4_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07359" name="l07359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5391a8c2a1e8cd6abb81fa5b2836464"> 7359</a></span><span class="preprocessor">#define FSMC_BTR4_BUSTURN_2 (0x4UL << FSMC_BTR4_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07360" name="l07360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbfd74790a1e25339151de440e3a93e5"> 7360</a></span><span class="preprocessor">#define FSMC_BTR4_BUSTURN_3 (0x8UL << FSMC_BTR4_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07362" name="l07362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97a0c80d8b160a03fb4276150054be56"> 7362</a></span><span class="preprocessor">#define FSMC_BTR4_CLKDIV_Pos (20U) </span></div>
|
||
<div class="line"><a id="l07363" name="l07363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20d19a8021d7c397928886a751546a0f"> 7363</a></span><span class="preprocessor">#define FSMC_BTR4_CLKDIV_Msk (0xFUL << FSMC_BTR4_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07364" name="l07364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ac39964e3792653e454538407b11504"> 7364</a></span><span class="preprocessor">#define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk </span></div>
|
||
<div class="line"><a id="l07365" name="l07365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacee394c98ac568fe1d6df61c887ed53"> 7365</a></span><span class="preprocessor">#define FSMC_BTR4_CLKDIV_0 (0x1UL << FSMC_BTR4_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07366" name="l07366"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c7cd1d1a4954d494bd107400925f86f"> 7366</a></span><span class="preprocessor">#define FSMC_BTR4_CLKDIV_1 (0x2UL << FSMC_BTR4_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07367" name="l07367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93b0ab3235ffacca24e6b285460c5dd3"> 7367</a></span><span class="preprocessor">#define FSMC_BTR4_CLKDIV_2 (0x4UL << FSMC_BTR4_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07368" name="l07368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga931463443390c5a706303e87a538d1ce"> 7368</a></span><span class="preprocessor">#define FSMC_BTR4_CLKDIV_3 (0x8UL << FSMC_BTR4_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l07370" name="l07370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa90d3bce2e4d950c80022117b564cb2c"> 7370</a></span><span class="preprocessor">#define FSMC_BTR4_DATLAT_Pos (24U) </span></div>
|
||
<div class="line"><a id="l07371" name="l07371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga737ae8e9d7fbf9906256a03e24d498aa"> 7371</a></span><span class="preprocessor">#define FSMC_BTR4_DATLAT_Msk (0xFUL << FSMC_BTR4_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07372" name="l07372"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa53cb7c299e794915d3aba803374adca"> 7372</a></span><span class="preprocessor">#define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk </span></div>
|
||
<div class="line"><a id="l07373" name="l07373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2315f17d1cd7dd9da1b0ee2f7e4ea29"> 7373</a></span><span class="preprocessor">#define FSMC_BTR4_DATLAT_0 (0x1UL << FSMC_BTR4_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07374" name="l07374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga808a7d758e6ca75c573d08ee92228745"> 7374</a></span><span class="preprocessor">#define FSMC_BTR4_DATLAT_1 (0x2UL << FSMC_BTR4_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07375" name="l07375"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac376a62779292d64bfac24d572b743e9"> 7375</a></span><span class="preprocessor">#define FSMC_BTR4_DATLAT_2 (0x4UL << FSMC_BTR4_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07376" name="l07376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfc558894dcb263451dbac13f48fffe1"> 7376</a></span><span class="preprocessor">#define FSMC_BTR4_DATLAT_3 (0x8UL << FSMC_BTR4_DATLAT_Pos) </span></div>
|
||
<div class="line"><a id="l07378" name="l07378"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88757eb5c47614f56b9fb13646b437e8"> 7378</a></span><span class="preprocessor">#define FSMC_BTR4_ACCMOD_Pos (28U) </span></div>
|
||
<div class="line"><a id="l07379" name="l07379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37535c8d3cc7d4388312e6640d513f6a"> 7379</a></span><span class="preprocessor">#define FSMC_BTR4_ACCMOD_Msk (0x3UL << FSMC_BTR4_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07380" name="l07380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbf731d99007936586f9e15f17c3c771"> 7380</a></span><span class="preprocessor">#define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk </span></div>
|
||
<div class="line"><a id="l07381" name="l07381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e69759ab89b16573bafd2f6ded95bfb"> 7381</a></span><span class="preprocessor">#define FSMC_BTR4_ACCMOD_0 (0x1UL << FSMC_BTR4_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07382" name="l07382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e486b11f6af0f566f8843a5c95c6a6c"> 7382</a></span><span class="preprocessor">#define FSMC_BTR4_ACCMOD_1 (0x2UL << FSMC_BTR4_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07384" name="l07384"></a><span class="lineno"> 7384</span><span class="comment">/****************** Bit definition for FSMC_BWTR1 register ******************/</span></div>
|
||
<div class="line"><a id="l07385" name="l07385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52ddd50ef2636a8e0bb45957d72b6a49"> 7385</a></span><span class="preprocessor">#define FSMC_BWTR1_ADDSET_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07386" name="l07386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga513a9612a5c7c61086b2f85d83e2653f"> 7386</a></span><span class="preprocessor">#define FSMC_BWTR1_ADDSET_Msk (0xFUL << FSMC_BWTR1_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07387" name="l07387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4aa5ee153cb4bf79f0d4ae2c47f365c4"> 7387</a></span><span class="preprocessor">#define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk </span></div>
|
||
<div class="line"><a id="l07388" name="l07388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacb80aeedb6d0d9cb09e7b4d3ff8b541"> 7388</a></span><span class="preprocessor">#define FSMC_BWTR1_ADDSET_0 (0x1UL << FSMC_BWTR1_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07389" name="l07389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20dbbdff1e2f1d57727dabbc4b03c840"> 7389</a></span><span class="preprocessor">#define FSMC_BWTR1_ADDSET_1 (0x2UL << FSMC_BWTR1_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07390" name="l07390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga411f0d164c26dda8132ff22856757470"> 7390</a></span><span class="preprocessor">#define FSMC_BWTR1_ADDSET_2 (0x4UL << FSMC_BWTR1_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07391" name="l07391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e2bc67999e8d2b63771fa223ffa8e4d"> 7391</a></span><span class="preprocessor">#define FSMC_BWTR1_ADDSET_3 (0x8UL << FSMC_BWTR1_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07393" name="l07393"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6e3be36c874835e8d5b50c546a6e5ce"> 7393</a></span><span class="preprocessor">#define FSMC_BWTR1_ADDHLD_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07394" name="l07394"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4772c530938b9f655bb0a807b9cd0f9d"> 7394</a></span><span class="preprocessor">#define FSMC_BWTR1_ADDHLD_Msk (0xFUL << FSMC_BWTR1_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07395" name="l07395"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa3d8ff62f87ab6aeb5170dd67de15cf"> 7395</a></span><span class="preprocessor">#define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk </span></div>
|
||
<div class="line"><a id="l07396" name="l07396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e24880c23375636d7504d42077a400a"> 7396</a></span><span class="preprocessor">#define FSMC_BWTR1_ADDHLD_0 (0x1UL << FSMC_BWTR1_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07397" name="l07397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb90dec93198b1d3077feb5fe508f004"> 7397</a></span><span class="preprocessor">#define FSMC_BWTR1_ADDHLD_1 (0x2UL << FSMC_BWTR1_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07398" name="l07398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26ef7d6cd5ec547a349462e4f31963b6"> 7398</a></span><span class="preprocessor">#define FSMC_BWTR1_ADDHLD_2 (0x4UL << FSMC_BWTR1_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07399" name="l07399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4a961ecd844e14a90d1b2f6c5d59196"> 7399</a></span><span class="preprocessor">#define FSMC_BWTR1_ADDHLD_3 (0x8UL << FSMC_BWTR1_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07401" name="l07401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga816436841706a81e91cc1627906c7e64"> 7401</a></span><span class="preprocessor">#define FSMC_BWTR1_DATAST_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07402" name="l07402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3de71f2a794f4e7a5e3135c715f644cc"> 7402</a></span><span class="preprocessor">#define FSMC_BWTR1_DATAST_Msk (0xFFUL << FSMC_BWTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07403" name="l07403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee2641a6f415d03df324667662bd3dcf"> 7403</a></span><span class="preprocessor">#define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk </span></div>
|
||
<div class="line"><a id="l07404" name="l07404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga162800452847dd98d27a4078370518b2"> 7404</a></span><span class="preprocessor">#define FSMC_BWTR1_DATAST_0 (0x01UL << FSMC_BWTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07405" name="l07405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16476bfbbcb9726c1fbc593d3568a514"> 7405</a></span><span class="preprocessor">#define FSMC_BWTR1_DATAST_1 (0x02UL << FSMC_BWTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07406" name="l07406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga623de376d9f5189d73068d0865a5049e"> 7406</a></span><span class="preprocessor">#define FSMC_BWTR1_DATAST_2 (0x04UL << FSMC_BWTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07407" name="l07407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade0627f53e3df25fdaa973db6159bd70"> 7407</a></span><span class="preprocessor">#define FSMC_BWTR1_DATAST_3 (0x08UL << FSMC_BWTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07408" name="l07408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39b5d7ddf6673ff23684c147c192f61b"> 7408</a></span><span class="preprocessor">#define FSMC_BWTR1_DATAST_4 (0x10UL << FSMC_BWTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07409" name="l07409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga211042c480c7d87941b584a591f7d0ab"> 7409</a></span><span class="preprocessor">#define FSMC_BWTR1_DATAST_5 (0x20UL << FSMC_BWTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07410" name="l07410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62232d4ec2bbbf375cfa555f947345fa"> 7410</a></span><span class="preprocessor">#define FSMC_BWTR1_DATAST_6 (0x40UL << FSMC_BWTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07411" name="l07411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7768908f2843432c6e4a4eb8e5153539"> 7411</a></span><span class="preprocessor">#define FSMC_BWTR1_DATAST_7 (0x80UL << FSMC_BWTR1_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07413" name="l07413"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade809e856484f40f6e54001fd88c7c80"> 7413</a></span><span class="preprocessor">#define FSMC_BWTR1_BUSTURN_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07414" name="l07414"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60c9f9abbf9f8110e9d7d5b729932af0"> 7414</a></span><span class="preprocessor">#define FSMC_BWTR1_BUSTURN_Msk (0xFUL << FSMC_BWTR1_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07415" name="l07415"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01289633ae20e7face5cb85cc031b532"> 7415</a></span><span class="preprocessor">#define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk </span></div>
|
||
<div class="line"><a id="l07416" name="l07416"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98fad3a30bdcb37dadcf7a443798e202"> 7416</a></span><span class="preprocessor">#define FSMC_BWTR1_BUSTURN_0 (0x1UL << FSMC_BWTR1_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07417" name="l07417"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c0dc053a9639673abb045e1d50756fa"> 7417</a></span><span class="preprocessor">#define FSMC_BWTR1_BUSTURN_1 (0x2UL << FSMC_BWTR1_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07418" name="l07418"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafafcc625222c5be36a617572881d6704"> 7418</a></span><span class="preprocessor">#define FSMC_BWTR1_BUSTURN_2 (0x4UL << FSMC_BWTR1_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07419" name="l07419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd830ff4d12444139479977ee13c730b"> 7419</a></span><span class="preprocessor">#define FSMC_BWTR1_BUSTURN_3 (0x8UL << FSMC_BWTR1_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07421" name="l07421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1339ee30e40045b01377267cdcdf2e42"> 7421</a></span><span class="preprocessor">#define FSMC_BWTR1_ACCMOD_Pos (28U) </span></div>
|
||
<div class="line"><a id="l07422" name="l07422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb84768b1b7f99be132fd7fabf109710"> 7422</a></span><span class="preprocessor">#define FSMC_BWTR1_ACCMOD_Msk (0x3UL << FSMC_BWTR1_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07423" name="l07423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa676b8e4f48602c27ea8edab61ce5db0"> 7423</a></span><span class="preprocessor">#define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk </span></div>
|
||
<div class="line"><a id="l07424" name="l07424"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae87cae14e6bb4403b420fc9e4084d6e2"> 7424</a></span><span class="preprocessor">#define FSMC_BWTR1_ACCMOD_0 (0x1UL << FSMC_BWTR1_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07425" name="l07425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0cddde5db2e0bb09f1c8938afd6ac98"> 7425</a></span><span class="preprocessor">#define FSMC_BWTR1_ACCMOD_1 (0x2UL << FSMC_BWTR1_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07427" name="l07427"></a><span class="lineno"> 7427</span><span class="comment">/****************** Bit definition for FSMC_BWTR2 register ******************/</span></div>
|
||
<div class="line"><a id="l07428" name="l07428"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf19233630fc32a605d2a4898cb93a7b"> 7428</a></span><span class="preprocessor">#define FSMC_BWTR2_ADDSET_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07429" name="l07429"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga124ca65a19ddd2bf11faba48c98f3e84"> 7429</a></span><span class="preprocessor">#define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07430" name="l07430"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b6553bd9ad305aa42341e08b1736260"> 7430</a></span><span class="preprocessor">#define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk </span></div>
|
||
<div class="line"><a id="l07431" name="l07431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga593fe1987e8c6052cdb992e629f1d059"> 7431</a></span><span class="preprocessor">#define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07432" name="l07432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6dc23a2314a44b6ad9f293716f0c8a11"> 7432</a></span><span class="preprocessor">#define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07433" name="l07433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e9c799b36f45cad86a3f98d262baa6d"> 7433</a></span><span class="preprocessor">#define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07434" name="l07434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95abc246eb528275d894346c0665e930"> 7434</a></span><span class="preprocessor">#define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07436" name="l07436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71f8b02d43d99e0de2b34cc269d85d60"> 7436</a></span><span class="preprocessor">#define FSMC_BWTR2_ADDHLD_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07437" name="l07437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a432338fb1c54a6d09a5646556dc1a0"> 7437</a></span><span class="preprocessor">#define FSMC_BWTR2_ADDHLD_Msk (0xFUL << FSMC_BWTR2_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07438" name="l07438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae879db1879650f99b1c75635884bda17"> 7438</a></span><span class="preprocessor">#define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk </span></div>
|
||
<div class="line"><a id="l07439" name="l07439"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5826c5d5c544cd59210c071358fb8e9"> 7439</a></span><span class="preprocessor">#define FSMC_BWTR2_ADDHLD_0 (0x1UL << FSMC_BWTR2_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07440" name="l07440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga258acf47f7706a1cd0b0a914e63cbe17"> 7440</a></span><span class="preprocessor">#define FSMC_BWTR2_ADDHLD_1 (0x2UL << FSMC_BWTR2_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07441" name="l07441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39f1a9ccc80d1218935936539a000b84"> 7441</a></span><span class="preprocessor">#define FSMC_BWTR2_ADDHLD_2 (0x4UL << FSMC_BWTR2_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07442" name="l07442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81de376a21fc25a7e1c31db341dfcd3f"> 7442</a></span><span class="preprocessor">#define FSMC_BWTR2_ADDHLD_3 (0x8UL << FSMC_BWTR2_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07444" name="l07444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f1969ba212c34f57a767b158e6f80ed"> 7444</a></span><span class="preprocessor">#define FSMC_BWTR2_DATAST_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07445" name="l07445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a8e67d5ff1e02c745ce4db92a251e7f"> 7445</a></span><span class="preprocessor">#define FSMC_BWTR2_DATAST_Msk (0xFFUL << FSMC_BWTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07446" name="l07446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab280652524006fbb3820597112136f14"> 7446</a></span><span class="preprocessor">#define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk </span></div>
|
||
<div class="line"><a id="l07447" name="l07447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78a0f0466162848135313296ebf44890"> 7447</a></span><span class="preprocessor">#define FSMC_BWTR2_DATAST_0 (0x01UL << FSMC_BWTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07448" name="l07448"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51e43e17e99141c9009c779cc359323a"> 7448</a></span><span class="preprocessor">#define FSMC_BWTR2_DATAST_1 (0x02UL << FSMC_BWTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07449" name="l07449"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f8791c2a33f740f905d45e3754e3353"> 7449</a></span><span class="preprocessor">#define FSMC_BWTR2_DATAST_2 (0x04UL << FSMC_BWTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07450" name="l07450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a2a5797dd14b5b89581c5fb08872fae"> 7450</a></span><span class="preprocessor">#define FSMC_BWTR2_DATAST_3 (0x08UL << FSMC_BWTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07451" name="l07451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59727cc45244014c0837b63b79787ef8"> 7451</a></span><span class="preprocessor">#define FSMC_BWTR2_DATAST_4 (0x10UL << FSMC_BWTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07452" name="l07452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7bb34356cc805ef2354194307e4119c"> 7452</a></span><span class="preprocessor">#define FSMC_BWTR2_DATAST_5 (0x20UL << FSMC_BWTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07453" name="l07453"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga348a18f1a4b0c5463a8692a9f12464a9"> 7453</a></span><span class="preprocessor">#define FSMC_BWTR2_DATAST_6 (0x40UL << FSMC_BWTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07454" name="l07454"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6497892b70d765d6f54b43351140d9c8"> 7454</a></span><span class="preprocessor">#define FSMC_BWTR2_DATAST_7 (0x80UL << FSMC_BWTR2_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07456" name="l07456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf50bc4030068335c54e73016b0e72d37"> 7456</a></span><span class="preprocessor">#define FSMC_BWTR2_BUSTURN_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07457" name="l07457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02edb530ab2bf59ff2d2c1339177dc5b"> 7457</a></span><span class="preprocessor">#define FSMC_BWTR2_BUSTURN_Msk (0xFUL << FSMC_BWTR2_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07458" name="l07458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46c9ba35109d12ff41e5d40f16911546"> 7458</a></span><span class="preprocessor">#define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk </span></div>
|
||
<div class="line"><a id="l07459" name="l07459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2e0a32552e1d57efa9ecacb5121a685"> 7459</a></span><span class="preprocessor">#define FSMC_BWTR2_BUSTURN_0 (0x1UL << FSMC_BWTR2_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07460" name="l07460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec6ea37fe04083cee9202e3b814095cd"> 7460</a></span><span class="preprocessor">#define FSMC_BWTR2_BUSTURN_1 (0x2UL << FSMC_BWTR2_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07461" name="l07461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff765b875a7e16a849d6019e1af147f0"> 7461</a></span><span class="preprocessor">#define FSMC_BWTR2_BUSTURN_2 (0x4UL << FSMC_BWTR2_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07462" name="l07462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a0684d050236cdf6c0a1b6e99c523fd"> 7462</a></span><span class="preprocessor">#define FSMC_BWTR2_BUSTURN_3 (0x8UL << FSMC_BWTR2_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07464" name="l07464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab50bf8884bd5bfd9845932225b058333"> 7464</a></span><span class="preprocessor">#define FSMC_BWTR2_ACCMOD_Pos (28U) </span></div>
|
||
<div class="line"><a id="l07465" name="l07465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cebbf681a61a82429105f62eff22230"> 7465</a></span><span class="preprocessor">#define FSMC_BWTR2_ACCMOD_Msk (0x3UL << FSMC_BWTR2_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07466" name="l07466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga320be3e2e266dc25bd02e10787b2ba0d"> 7466</a></span><span class="preprocessor">#define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk </span></div>
|
||
<div class="line"><a id="l07467" name="l07467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabe5419d99a7ad4d4eb761c82077d958"> 7467</a></span><span class="preprocessor">#define FSMC_BWTR2_ACCMOD_0 (0x1UL << FSMC_BWTR2_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07468" name="l07468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6cdd284ad94abfef0f24fcb813b4558"> 7468</a></span><span class="preprocessor">#define FSMC_BWTR2_ACCMOD_1 (0x2UL << FSMC_BWTR2_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07470" name="l07470"></a><span class="lineno"> 7470</span><span class="comment">/****************** Bit definition for FSMC_BWTR3 register ******************/</span></div>
|
||
<div class="line"><a id="l07471" name="l07471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e8110634778086f551394937f738ff9"> 7471</a></span><span class="preprocessor">#define FSMC_BWTR3_ADDSET_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07472" name="l07472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcc45a7e8a398c8932cd545fb3ed10a6"> 7472</a></span><span class="preprocessor">#define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07473" name="l07473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga455ba53d0f18173b0694d71757a084ff"> 7473</a></span><span class="preprocessor">#define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk </span></div>
|
||
<div class="line"><a id="l07474" name="l07474"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9dddd5ba924b56867c9cb39484ef498d"> 7474</a></span><span class="preprocessor">#define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07475" name="l07475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd242d768da1f9ab4304e91e5dabb5a9"> 7475</a></span><span class="preprocessor">#define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07476" name="l07476"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef99967dc66814cf5d732365c40daebb"> 7476</a></span><span class="preprocessor">#define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07477" name="l07477"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga471ebb2d47fb951340df6ba22b40a788"> 7477</a></span><span class="preprocessor">#define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07479" name="l07479"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae752c10ea876415cf0b54aca8c7d77e7"> 7479</a></span><span class="preprocessor">#define FSMC_BWTR3_ADDHLD_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07480" name="l07480"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1025758662868a34da456a8f3c9600dd"> 7480</a></span><span class="preprocessor">#define FSMC_BWTR3_ADDHLD_Msk (0xFUL << FSMC_BWTR3_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07481" name="l07481"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3d031a0d71677932a68639ba88bd13e"> 7481</a></span><span class="preprocessor">#define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk </span></div>
|
||
<div class="line"><a id="l07482" name="l07482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b3948c407a5a4be6a21cccad0a8d12d"> 7482</a></span><span class="preprocessor">#define FSMC_BWTR3_ADDHLD_0 (0x1UL << FSMC_BWTR3_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07483" name="l07483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea21d05228f7771c6306726af5da5a4a"> 7483</a></span><span class="preprocessor">#define FSMC_BWTR3_ADDHLD_1 (0x2UL << FSMC_BWTR3_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07484" name="l07484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa574b3a1efe581d195789dcc8bba01f8"> 7484</a></span><span class="preprocessor">#define FSMC_BWTR3_ADDHLD_2 (0x4UL << FSMC_BWTR3_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07485" name="l07485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae8216cf865785468af58dbce0002a7c"> 7485</a></span><span class="preprocessor">#define FSMC_BWTR3_ADDHLD_3 (0x8UL << FSMC_BWTR3_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07487" name="l07487"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfc2a85d6970397944903ed17252a68d"> 7487</a></span><span class="preprocessor">#define FSMC_BWTR3_DATAST_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07488" name="l07488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51d5ed2f485b7b92825e4677e11e095a"> 7488</a></span><span class="preprocessor">#define FSMC_BWTR3_DATAST_Msk (0xFFUL << FSMC_BWTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07489" name="l07489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae93d9fee8a67491918526019b439a00f"> 7489</a></span><span class="preprocessor">#define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk </span></div>
|
||
<div class="line"><a id="l07490" name="l07490"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1ec40c6360faeb133cb224a6789bb51"> 7490</a></span><span class="preprocessor">#define FSMC_BWTR3_DATAST_0 (0x01UL << FSMC_BWTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07491" name="l07491"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacaf23316e44d731620f0cbde29ae9a93"> 7491</a></span><span class="preprocessor">#define FSMC_BWTR3_DATAST_1 (0x02UL << FSMC_BWTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07492" name="l07492"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31686e755ef0f98078d96c08891cf8f4"> 7492</a></span><span class="preprocessor">#define FSMC_BWTR3_DATAST_2 (0x04UL << FSMC_BWTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07493" name="l07493"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a291f74abf021a7fe66ce8afd714c39"> 7493</a></span><span class="preprocessor">#define FSMC_BWTR3_DATAST_3 (0x08UL << FSMC_BWTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07494" name="l07494"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd5b6e11c52314eb07772d72353002fa"> 7494</a></span><span class="preprocessor">#define FSMC_BWTR3_DATAST_4 (0x10UL << FSMC_BWTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07495" name="l07495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga590322c15eb3fb579edec41fd4a86ea5"> 7495</a></span><span class="preprocessor">#define FSMC_BWTR3_DATAST_5 (0x20UL << FSMC_BWTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07496" name="l07496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3aec6604821cd38fafbceeaf81556d63"> 7496</a></span><span class="preprocessor">#define FSMC_BWTR3_DATAST_6 (0x40UL << FSMC_BWTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07497" name="l07497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79e7035f0bb60e6082f699ee98d2ffc2"> 7497</a></span><span class="preprocessor">#define FSMC_BWTR3_DATAST_7 (0x80UL << FSMC_BWTR3_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07499" name="l07499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b60d7fbc787a9d6df78fbc5fea4c206"> 7499</a></span><span class="preprocessor">#define FSMC_BWTR3_BUSTURN_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07500" name="l07500"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4922c75c6b3c2baf134ad5119a97a098"> 7500</a></span><span class="preprocessor">#define FSMC_BWTR3_BUSTURN_Msk (0xFUL << FSMC_BWTR3_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07501" name="l07501"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga333004366913e1c938f2efb57c259c39"> 7501</a></span><span class="preprocessor">#define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk </span></div>
|
||
<div class="line"><a id="l07502" name="l07502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga966a4bb7d0878efc320d50457c26749d"> 7502</a></span><span class="preprocessor">#define FSMC_BWTR3_BUSTURN_0 (0x1UL << FSMC_BWTR3_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07503" name="l07503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44b560ff9aaa44e2f4a18ac548c8d65e"> 7503</a></span><span class="preprocessor">#define FSMC_BWTR3_BUSTURN_1 (0x2UL << FSMC_BWTR3_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07504" name="l07504"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89448c3668da87fe261d575166325f3d"> 7504</a></span><span class="preprocessor">#define FSMC_BWTR3_BUSTURN_2 (0x4UL << FSMC_BWTR3_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07505" name="l07505"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86e615ef161c836eb338cc410f474cf6"> 7505</a></span><span class="preprocessor">#define FSMC_BWTR3_BUSTURN_3 (0x8UL << FSMC_BWTR3_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07507" name="l07507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacad6fb10201c4c9c3e022b8551143f1f"> 7507</a></span><span class="preprocessor">#define FSMC_BWTR3_ACCMOD_Pos (28U) </span></div>
|
||
<div class="line"><a id="l07508" name="l07508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcc2c37152b55b3c8c5e178778567261"> 7508</a></span><span class="preprocessor">#define FSMC_BWTR3_ACCMOD_Msk (0x3UL << FSMC_BWTR3_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07509" name="l07509"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa32a792c0c93d854a90bfbc36fa1329b"> 7509</a></span><span class="preprocessor">#define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk </span></div>
|
||
<div class="line"><a id="l07510" name="l07510"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64d4e414ea73b47e07364e1a121af6a4"> 7510</a></span><span class="preprocessor">#define FSMC_BWTR3_ACCMOD_0 (0x1UL << FSMC_BWTR3_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07511" name="l07511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada733b2bda718299345fd0191b25b49f"> 7511</a></span><span class="preprocessor">#define FSMC_BWTR3_ACCMOD_1 (0x2UL << FSMC_BWTR3_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07513" name="l07513"></a><span class="lineno"> 7513</span><span class="comment">/****************** Bit definition for FSMC_BWTR4 register ******************/</span></div>
|
||
<div class="line"><a id="l07514" name="l07514"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46344b3ec4032b5a520833b6ba553b8f"> 7514</a></span><span class="preprocessor">#define FSMC_BWTR4_ADDSET_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07515" name="l07515"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac9acf4808b842bc735479c137aceb01"> 7515</a></span><span class="preprocessor">#define FSMC_BWTR4_ADDSET_Msk (0xFUL << FSMC_BWTR4_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07516" name="l07516"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8c3c14faf87768beced4e297edc7bfd"> 7516</a></span><span class="preprocessor">#define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk </span></div>
|
||
<div class="line"><a id="l07517" name="l07517"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65ba73495f6192e409cc00f3e26e27e0"> 7517</a></span><span class="preprocessor">#define FSMC_BWTR4_ADDSET_0 (0x1UL << FSMC_BWTR4_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07518" name="l07518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cc9fa3c1ceae0724f5005bb1e101775"> 7518</a></span><span class="preprocessor">#define FSMC_BWTR4_ADDSET_1 (0x2UL << FSMC_BWTR4_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07519" name="l07519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2007941f4869504bfef23edbcc18bfa"> 7519</a></span><span class="preprocessor">#define FSMC_BWTR4_ADDSET_2 (0x4UL << FSMC_BWTR4_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07520" name="l07520"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabcde23639f64241d95b02f5b950ef3cc"> 7520</a></span><span class="preprocessor">#define FSMC_BWTR4_ADDSET_3 (0x8UL << FSMC_BWTR4_ADDSET_Pos) </span></div>
|
||
<div class="line"><a id="l07522" name="l07522"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac40aa70101334a56d6ce4cb52d9a64bc"> 7522</a></span><span class="preprocessor">#define FSMC_BWTR4_ADDHLD_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07523" name="l07523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7cf1485c80e4326e49ab8dc889e5537"> 7523</a></span><span class="preprocessor">#define FSMC_BWTR4_ADDHLD_Msk (0xFUL << FSMC_BWTR4_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07524" name="l07524"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafe1198e70d843c883260d354b7ce7b5"> 7524</a></span><span class="preprocessor">#define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk </span></div>
|
||
<div class="line"><a id="l07525" name="l07525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac62786f538820baa3f0f8edb17ef1b74"> 7525</a></span><span class="preprocessor">#define FSMC_BWTR4_ADDHLD_0 (0x1UL << FSMC_BWTR4_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07526" name="l07526"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa69aa2d9cafe8f952721c88083c8a94e"> 7526</a></span><span class="preprocessor">#define FSMC_BWTR4_ADDHLD_1 (0x2UL << FSMC_BWTR4_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07527" name="l07527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c6d991498c385991b461832fb093399"> 7527</a></span><span class="preprocessor">#define FSMC_BWTR4_ADDHLD_2 (0x4UL << FSMC_BWTR4_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07528" name="l07528"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac744bdeb5b9ae048b1fa1a07ce9ce9d1"> 7528</a></span><span class="preprocessor">#define FSMC_BWTR4_ADDHLD_3 (0x8UL << FSMC_BWTR4_ADDHLD_Pos) </span></div>
|
||
<div class="line"><a id="l07530" name="l07530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab82ad4f36968e5609b1adc15bc1d0dd5"> 7530</a></span><span class="preprocessor">#define FSMC_BWTR4_DATAST_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07531" name="l07531"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae370408fcf34c2db09d389102c249b1e"> 7531</a></span><span class="preprocessor">#define FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos) </span></div>
|
||
<div class="line"><a id="l07532" name="l07532"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6656c89aac87fc226c0e80f8f753abeb"> 7532</a></span><span class="preprocessor">#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk </span></div>
|
||
<div class="line"><a id="l07533" name="l07533"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5636aaec144530e1c46e819b62c95f09"> 7533</a></span><span class="preprocessor">#define FSMC_BWTR4_DATAST_0 0x00000100U </span></div>
|
||
<div class="line"><a id="l07534" name="l07534"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19eb9fccff444a00caf75b9d20a143ed"> 7534</a></span><span class="preprocessor">#define FSMC_BWTR4_DATAST_1 0x00000200U </span></div>
|
||
<div class="line"><a id="l07535" name="l07535"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa40f9fa60ddb69fdcdcdface743f2c26"> 7535</a></span><span class="preprocessor">#define FSMC_BWTR4_DATAST_2 0x00000400U </span></div>
|
||
<div class="line"><a id="l07536" name="l07536"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa173c5ff9a7d316cd67897f8e36dbf5"> 7536</a></span><span class="preprocessor">#define FSMC_BWTR4_DATAST_3 0x00000800U </span></div>
|
||
<div class="line"><a id="l07537" name="l07537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c8dde48be5fa0ea0e920d72e7b43ad0"> 7537</a></span><span class="preprocessor">#define FSMC_BWTR4_DATAST_4 0x00001000U </span></div>
|
||
<div class="line"><a id="l07538" name="l07538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ff7e92fad8d55c205ee1225868c54a4"> 7538</a></span><span class="preprocessor">#define FSMC_BWTR4_DATAST_5 0x00002000U </span></div>
|
||
<div class="line"><a id="l07539" name="l07539"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2dbfd952e906c67ec6bb813d220638f9"> 7539</a></span><span class="preprocessor">#define FSMC_BWTR4_DATAST_6 0x00004000U </span></div>
|
||
<div class="line"><a id="l07540" name="l07540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67a7e379e49efcdb4a42ed45eb20c620"> 7540</a></span><span class="preprocessor">#define FSMC_BWTR4_DATAST_7 0x00008000U </span></div>
|
||
<div class="line"><a id="l07542" name="l07542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5ff326880c026bb2a70e39e7ce48074"> 7542</a></span><span class="preprocessor">#define FSMC_BWTR4_BUSTURN_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07543" name="l07543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga152a5383e408f7ec2e000fcf40f335df"> 7543</a></span><span class="preprocessor">#define FSMC_BWTR4_BUSTURN_Msk (0xFUL << FSMC_BWTR4_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07544" name="l07544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2251ad4a30e8fd743b5ee0cf1f64b479"> 7544</a></span><span class="preprocessor">#define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk </span></div>
|
||
<div class="line"><a id="l07545" name="l07545"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc959ee76e0bf42eca48b4cc8ddb5bf6"> 7545</a></span><span class="preprocessor">#define FSMC_BWTR4_BUSTURN_0 (0x1UL << FSMC_BWTR4_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07546" name="l07546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e77325faba8acb512b97a5bfac186df"> 7546</a></span><span class="preprocessor">#define FSMC_BWTR4_BUSTURN_1 (0x2UL << FSMC_BWTR4_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07547" name="l07547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc92938093fc0c4da4b3e82b0ac0f440"> 7547</a></span><span class="preprocessor">#define FSMC_BWTR4_BUSTURN_2 (0x4UL << FSMC_BWTR4_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07548" name="l07548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c239a600bcaa8addc11ef97c5c6248c"> 7548</a></span><span class="preprocessor">#define FSMC_BWTR4_BUSTURN_3 (0x8UL << FSMC_BWTR4_BUSTURN_Pos) </span></div>
|
||
<div class="line"><a id="l07550" name="l07550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fc1deea073ae82799fcda8073bdeccb"> 7550</a></span><span class="preprocessor">#define FSMC_BWTR4_ACCMOD_Pos (28U) </span></div>
|
||
<div class="line"><a id="l07551" name="l07551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9daae3a3b8aaafa7afc2069debd8d14"> 7551</a></span><span class="preprocessor">#define FSMC_BWTR4_ACCMOD_Msk (0x3UL << FSMC_BWTR4_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07552" name="l07552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d13f46a945d5daf6ec339781d3926a9"> 7552</a></span><span class="preprocessor">#define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk </span></div>
|
||
<div class="line"><a id="l07553" name="l07553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e30f51c68b4ac4f9efee2cd5a45943c"> 7553</a></span><span class="preprocessor">#define FSMC_BWTR4_ACCMOD_0 (0x1UL << FSMC_BWTR4_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07554" name="l07554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7ba26fb09f035addbe1e4c3b0d093c9"> 7554</a></span><span class="preprocessor">#define FSMC_BWTR4_ACCMOD_1 (0x2UL << FSMC_BWTR4_ACCMOD_Pos) </span></div>
|
||
<div class="line"><a id="l07556" name="l07556"></a><span class="lineno"> 7556</span><span class="comment">/****************** Bit definition for FSMC_PCR2 register *******************/</span></div>
|
||
<div class="line"><a id="l07557" name="l07557"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa09c72741deafe6d443fd0f25299480"> 7557</a></span><span class="preprocessor">#define FSMC_PCR2_PWAITEN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l07558" name="l07558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga427ff4cc50d76345ee3d8885f7f09863"> 7558</a></span><span class="preprocessor">#define FSMC_PCR2_PWAITEN_Msk (0x1UL << FSMC_PCR2_PWAITEN_Pos) </span></div>
|
||
<div class="line"><a id="l07559" name="l07559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26f3ae80c9bbede6929c20004804476d"> 7559</a></span><span class="preprocessor">#define FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk </span></div>
|
||
<div class="line"><a id="l07560" name="l07560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa44a48baf82f718ea68a8f49f41a7197"> 7560</a></span><span class="preprocessor">#define FSMC_PCR2_PBKEN_Pos (2U) </span></div>
|
||
<div class="line"><a id="l07561" name="l07561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23ca7d9404f38c74f54c617779417247"> 7561</a></span><span class="preprocessor">#define FSMC_PCR2_PBKEN_Msk (0x1UL << FSMC_PCR2_PBKEN_Pos) </span></div>
|
||
<div class="line"><a id="l07562" name="l07562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a2bfd8de14f8c726439ba8f494b38a1"> 7562</a></span><span class="preprocessor">#define FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk </span></div>
|
||
<div class="line"><a id="l07563" name="l07563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56ca1be84472397c7e7c0e72e45f69c9"> 7563</a></span><span class="preprocessor">#define FSMC_PCR2_PTYP_Pos (3U) </span></div>
|
||
<div class="line"><a id="l07564" name="l07564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcf702c34178ab9c91c1e5e31c5b6b8f"> 7564</a></span><span class="preprocessor">#define FSMC_PCR2_PTYP_Msk (0x1UL << FSMC_PCR2_PTYP_Pos) </span></div>
|
||
<div class="line"><a id="l07565" name="l07565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga175ab8f61bbc0bb5692fb62691db1ce3"> 7565</a></span><span class="preprocessor">#define FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk </span></div>
|
||
<div class="line"><a id="l07567" name="l07567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga786bd3b30640e57e85ccd8faeb812c73"> 7567</a></span><span class="preprocessor">#define FSMC_PCR2_PWID_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07568" name="l07568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeaeb0bbbb281a4cc378e1ac5c0af401b"> 7568</a></span><span class="preprocessor">#define FSMC_PCR2_PWID_Msk (0x3UL << FSMC_PCR2_PWID_Pos) </span></div>
|
||
<div class="line"><a id="l07569" name="l07569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga656155275dc1c2f690687d07717e017a"> 7569</a></span><span class="preprocessor">#define FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk </span></div>
|
||
<div class="line"><a id="l07570" name="l07570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae36f67be67a473c318fa937246c6de17"> 7570</a></span><span class="preprocessor">#define FSMC_PCR2_PWID_0 (0x1UL << FSMC_PCR2_PWID_Pos) </span></div>
|
||
<div class="line"><a id="l07571" name="l07571"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6180d3899a37f7e518b1e4b8bf935baa"> 7571</a></span><span class="preprocessor">#define FSMC_PCR2_PWID_1 (0x2UL << FSMC_PCR2_PWID_Pos) </span></div>
|
||
<div class="line"><a id="l07573" name="l07573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ca16b5cf800c2fb594a8a06fa0ea883"> 7573</a></span><span class="preprocessor">#define FSMC_PCR2_ECCEN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l07574" name="l07574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga050ab1ee23d46eb34ed79f22bde35200"> 7574</a></span><span class="preprocessor">#define FSMC_PCR2_ECCEN_Msk (0x1UL << FSMC_PCR2_ECCEN_Pos) </span></div>
|
||
<div class="line"><a id="l07575" name="l07575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa528d578aec8bc0f77a2550d4e48438"> 7575</a></span><span class="preprocessor">#define FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk </span></div>
|
||
<div class="line"><a id="l07577" name="l07577"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c24b437e7873367aa3db5fe3f9526e5"> 7577</a></span><span class="preprocessor">#define FSMC_PCR2_TCLR_Pos (9U) </span></div>
|
||
<div class="line"><a id="l07578" name="l07578"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f526b241c14b7292561799c4e824e76"> 7578</a></span><span class="preprocessor">#define FSMC_PCR2_TCLR_Msk (0xFUL << FSMC_PCR2_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07579" name="l07579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4f2c6c5ed8cd459a0822c35ea9e6800"> 7579</a></span><span class="preprocessor">#define FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk </span></div>
|
||
<div class="line"><a id="l07580" name="l07580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1edc7eec1b5a76a851175e5a7caa6c5c"> 7580</a></span><span class="preprocessor">#define FSMC_PCR2_TCLR_0 (0x1UL << FSMC_PCR2_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07581" name="l07581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8baae9949bd0f294a698721da24808f"> 7581</a></span><span class="preprocessor">#define FSMC_PCR2_TCLR_1 (0x2UL << FSMC_PCR2_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07582" name="l07582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01ba36d067efffcfe5ecea3af1411675"> 7582</a></span><span class="preprocessor">#define FSMC_PCR2_TCLR_2 (0x4UL << FSMC_PCR2_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07583" name="l07583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4999b81ed8783cca5f3b25500183ff9a"> 7583</a></span><span class="preprocessor">#define FSMC_PCR2_TCLR_3 (0x8UL << FSMC_PCR2_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07585" name="l07585"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c4fe782dd038165f42f57ebac4721bf"> 7585</a></span><span class="preprocessor">#define FSMC_PCR2_TAR_Pos (13U) </span></div>
|
||
<div class="line"><a id="l07586" name="l07586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb912af6630ca178d706e72bfeafe4e5"> 7586</a></span><span class="preprocessor">#define FSMC_PCR2_TAR_Msk (0xFUL << FSMC_PCR2_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07587" name="l07587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6513b62e23afdbadc4b25697378a0f2"> 7587</a></span><span class="preprocessor">#define FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk </span></div>
|
||
<div class="line"><a id="l07588" name="l07588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd7e456c24f5978e8cb1078c633f0d23"> 7588</a></span><span class="preprocessor">#define FSMC_PCR2_TAR_0 (0x1UL << FSMC_PCR2_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07589" name="l07589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f0b2191750ab21af10f009e1a97ca13"> 7589</a></span><span class="preprocessor">#define FSMC_PCR2_TAR_1 (0x2UL << FSMC_PCR2_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07590" name="l07590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3de27b9eb559156b7ed87407206b7a17"> 7590</a></span><span class="preprocessor">#define FSMC_PCR2_TAR_2 (0x4UL << FSMC_PCR2_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07591" name="l07591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c70f852bb8809e8ea4800a7dd616266"> 7591</a></span><span class="preprocessor">#define FSMC_PCR2_TAR_3 (0x8UL << FSMC_PCR2_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07593" name="l07593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga252ebef1000455631c4839f64fe943c2"> 7593</a></span><span class="preprocessor">#define FSMC_PCR2_ECCPS_Pos (17U) </span></div>
|
||
<div class="line"><a id="l07594" name="l07594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga481ae62d08b68ae47e76399a3db6f343"> 7594</a></span><span class="preprocessor">#define FSMC_PCR2_ECCPS_Msk (0x7UL << FSMC_PCR2_ECCPS_Pos) </span></div>
|
||
<div class="line"><a id="l07595" name="l07595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2adbc7b4149193452b69bc55a968cd1"> 7595</a></span><span class="preprocessor">#define FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk </span></div>
|
||
<div class="line"><a id="l07596" name="l07596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0e06e76b0dd7cc1f6b765b4c3ecfacb"> 7596</a></span><span class="preprocessor">#define FSMC_PCR2_ECCPS_0 (0x1UL << FSMC_PCR2_ECCPS_Pos) </span></div>
|
||
<div class="line"><a id="l07597" name="l07597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b947299d05921085b531f12db860f41"> 7597</a></span><span class="preprocessor">#define FSMC_PCR2_ECCPS_1 (0x2UL << FSMC_PCR2_ECCPS_Pos) </span></div>
|
||
<div class="line"><a id="l07598" name="l07598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga199db72eae8707aba0b22ff18bd8bcd0"> 7598</a></span><span class="preprocessor">#define FSMC_PCR2_ECCPS_2 (0x4UL << FSMC_PCR2_ECCPS_Pos) </span></div>
|
||
<div class="line"><a id="l07600" name="l07600"></a><span class="lineno"> 7600</span><span class="comment">/****************** Bit definition for FSMC_PCR3 register *******************/</span></div>
|
||
<div class="line"><a id="l07601" name="l07601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga349eaf51ed38a2cde231d53a0701c961"> 7601</a></span><span class="preprocessor">#define FSMC_PCR3_PWAITEN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l07602" name="l07602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a95cabc9c10687663e8d26706a5a012"> 7602</a></span><span class="preprocessor">#define FSMC_PCR3_PWAITEN_Msk (0x1UL << FSMC_PCR3_PWAITEN_Pos) </span></div>
|
||
<div class="line"><a id="l07603" name="l07603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae3f15324eb8692ddf3f294f358b1d8c"> 7603</a></span><span class="preprocessor">#define FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk </span></div>
|
||
<div class="line"><a id="l07604" name="l07604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ca0936c38ad7fe990f148f58bb1adff"> 7604</a></span><span class="preprocessor">#define FSMC_PCR3_PBKEN_Pos (2U) </span></div>
|
||
<div class="line"><a id="l07605" name="l07605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad82453ed7e868ba250086608f62fc27c"> 7605</a></span><span class="preprocessor">#define FSMC_PCR3_PBKEN_Msk (0x1UL << FSMC_PCR3_PBKEN_Pos) </span></div>
|
||
<div class="line"><a id="l07606" name="l07606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac1334587ebb2f313078aab2c2f76cf7"> 7606</a></span><span class="preprocessor">#define FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk </span></div>
|
||
<div class="line"><a id="l07607" name="l07607"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63ea560efa8bf6aabab0f0e552844ca6"> 7607</a></span><span class="preprocessor">#define FSMC_PCR3_PTYP_Pos (3U) </span></div>
|
||
<div class="line"><a id="l07608" name="l07608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga698eaa08d2ec1dedfceb558efe404a83"> 7608</a></span><span class="preprocessor">#define FSMC_PCR3_PTYP_Msk (0x1UL << FSMC_PCR3_PTYP_Pos) </span></div>
|
||
<div class="line"><a id="l07609" name="l07609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade562589d0572ba223d2f6df265fe5b8"> 7609</a></span><span class="preprocessor">#define FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk </span></div>
|
||
<div class="line"><a id="l07611" name="l07611"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1002927e92f1e32f4430eee6387493c5"> 7611</a></span><span class="preprocessor">#define FSMC_PCR3_PWID_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07612" name="l07612"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga292dbafb10a606fcee46e2ed5a6465fc"> 7612</a></span><span class="preprocessor">#define FSMC_PCR3_PWID_Msk (0x3UL << FSMC_PCR3_PWID_Pos) </span></div>
|
||
<div class="line"><a id="l07613" name="l07613"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6f9b4e4449f105aa9bd3630f0466b9f"> 7613</a></span><span class="preprocessor">#define FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk </span></div>
|
||
<div class="line"><a id="l07614" name="l07614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae07191f4d5e3c3ec38b271b30cd1ee07"> 7614</a></span><span class="preprocessor">#define FSMC_PCR3_PWID_0 (0x1UL << FSMC_PCR3_PWID_Pos) </span></div>
|
||
<div class="line"><a id="l07615" name="l07615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8819a742324c0523f3dc6b8959bcdd5"> 7615</a></span><span class="preprocessor">#define FSMC_PCR3_PWID_1 (0x2UL << FSMC_PCR3_PWID_Pos) </span></div>
|
||
<div class="line"><a id="l07617" name="l07617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf427fbfd20e6142aa46d625037c67fbe"> 7617</a></span><span class="preprocessor">#define FSMC_PCR3_ECCEN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l07618" name="l07618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62b7f1f808fa00fda792439b9c0f10df"> 7618</a></span><span class="preprocessor">#define FSMC_PCR3_ECCEN_Msk (0x1UL << FSMC_PCR3_ECCEN_Pos) </span></div>
|
||
<div class="line"><a id="l07619" name="l07619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga723c4c8c3b97cd1ce18c3b5c888e5b4e"> 7619</a></span><span class="preprocessor">#define FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk </span></div>
|
||
<div class="line"><a id="l07621" name="l07621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d8b78bf2fb85e57fcd42e1dbbd7d0cb"> 7621</a></span><span class="preprocessor">#define FSMC_PCR3_TCLR_Pos (9U) </span></div>
|
||
<div class="line"><a id="l07622" name="l07622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf9f398e720fdb04a1c5cdecc91cd857"> 7622</a></span><span class="preprocessor">#define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07623" name="l07623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga478e4371d8baf2a0b2675b3113edb071"> 7623</a></span><span class="preprocessor">#define FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk </span></div>
|
||
<div class="line"><a id="l07624" name="l07624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadedb0d10b5b53656dc152b9264faffbd"> 7624</a></span><span class="preprocessor">#define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07625" name="l07625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5536285f03b1732aed999d20c0e25aa"> 7625</a></span><span class="preprocessor">#define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07626" name="l07626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7d40ba9c0f0da58948ee2cc546b634c"> 7626</a></span><span class="preprocessor">#define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07627" name="l07627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63f96a640afa85d7521b05458f590a19"> 7627</a></span><span class="preprocessor">#define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07629" name="l07629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2a4166c7fb1ca933148a90ded54588c"> 7629</a></span><span class="preprocessor">#define FSMC_PCR3_TAR_Pos (13U) </span></div>
|
||
<div class="line"><a id="l07630" name="l07630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba49396ea8498e090556ab597f1a4964"> 7630</a></span><span class="preprocessor">#define FSMC_PCR3_TAR_Msk (0xFUL << FSMC_PCR3_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07631" name="l07631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga199c4b0e690f0da0de46e372183da642"> 7631</a></span><span class="preprocessor">#define FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk </span></div>
|
||
<div class="line"><a id="l07632" name="l07632"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada0f17bcc683a5a6249348a63004e225"> 7632</a></span><span class="preprocessor">#define FSMC_PCR3_TAR_0 (0x1UL << FSMC_PCR3_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07633" name="l07633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4afb373f6f1cb1bedd653d8ea1dca78"> 7633</a></span><span class="preprocessor">#define FSMC_PCR3_TAR_1 (0x2UL << FSMC_PCR3_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07634" name="l07634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga597698c6059f70f61310456e83353738"> 7634</a></span><span class="preprocessor">#define FSMC_PCR3_TAR_2 (0x4UL << FSMC_PCR3_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07635" name="l07635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bd7aaf7ffcad9f4477ac4f2927a0912"> 7635</a></span><span class="preprocessor">#define FSMC_PCR3_TAR_3 (0x8UL << FSMC_PCR3_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07637" name="l07637"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga102ae2695e494e32ba3a88386da61aaf"> 7637</a></span><span class="preprocessor">#define FSMC_PCR3_ECCPS_Pos (17U) </span></div>
|
||
<div class="line"><a id="l07638" name="l07638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5c4fa241bbfe5cce0debcb6ad2052ce"> 7638</a></span><span class="preprocessor">#define FSMC_PCR3_ECCPS_Msk (0x7UL << FSMC_PCR3_ECCPS_Pos) </span></div>
|
||
<div class="line"><a id="l07639" name="l07639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8d92853ca6f97f72682c2f53f686998"> 7639</a></span><span class="preprocessor">#define FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk </span></div>
|
||
<div class="line"><a id="l07640" name="l07640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga506daa911151e1b9de3ed2b5030d1a5a"> 7640</a></span><span class="preprocessor">#define FSMC_PCR3_ECCPS_0 (0x1UL << FSMC_PCR3_ECCPS_Pos) </span></div>
|
||
<div class="line"><a id="l07641" name="l07641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6403c557bd93b5297fa7fbbf8dc49cc9"> 7641</a></span><span class="preprocessor">#define FSMC_PCR3_ECCPS_1 (0x2UL << FSMC_PCR3_ECCPS_Pos) </span></div>
|
||
<div class="line"><a id="l07642" name="l07642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf041e921fb9af07e9c709d79bbfaec89"> 7642</a></span><span class="preprocessor">#define FSMC_PCR3_ECCPS_2 (0x4UL << FSMC_PCR3_ECCPS_Pos) </span></div>
|
||
<div class="line"><a id="l07644" name="l07644"></a><span class="lineno"> 7644</span><span class="comment">/****************** Bit definition for FSMC_PCR4 register *******************/</span></div>
|
||
<div class="line"><a id="l07645" name="l07645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf0bbe752661c9c0cad5f84f067d4714"> 7645</a></span><span class="preprocessor">#define FSMC_PCR4_PWAITEN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l07646" name="l07646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8766498d3b50a9c490695d777713d492"> 7646</a></span><span class="preprocessor">#define FSMC_PCR4_PWAITEN_Msk (0x1UL << FSMC_PCR4_PWAITEN_Pos) </span></div>
|
||
<div class="line"><a id="l07647" name="l07647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab07ce7c785eb296a615b2c50415de21b"> 7647</a></span><span class="preprocessor">#define FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk </span></div>
|
||
<div class="line"><a id="l07648" name="l07648"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33cf4873210ab762fd32b654eb055e4a"> 7648</a></span><span class="preprocessor">#define FSMC_PCR4_PBKEN_Pos (2U) </span></div>
|
||
<div class="line"><a id="l07649" name="l07649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36baaaa99b92a8eb95f34e111e7b1129"> 7649</a></span><span class="preprocessor">#define FSMC_PCR4_PBKEN_Msk (0x1UL << FSMC_PCR4_PBKEN_Pos) </span></div>
|
||
<div class="line"><a id="l07650" name="l07650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f4a72bae5da27f8da23c13a54fe9622"> 7650</a></span><span class="preprocessor">#define FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk </span></div>
|
||
<div class="line"><a id="l07651" name="l07651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02a9e81721d3a6940da19547e32f5542"> 7651</a></span><span class="preprocessor">#define FSMC_PCR4_PTYP_Pos (3U) </span></div>
|
||
<div class="line"><a id="l07652" name="l07652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3a1ef73cc660cb04c99fc409bfc75b7"> 7652</a></span><span class="preprocessor">#define FSMC_PCR4_PTYP_Msk (0x1UL << FSMC_PCR4_PTYP_Pos) </span></div>
|
||
<div class="line"><a id="l07653" name="l07653"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe2d6f4e9bdef35436d521ebbdca5e40"> 7653</a></span><span class="preprocessor">#define FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk </span></div>
|
||
<div class="line"><a id="l07655" name="l07655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabea06d1f6a4648fefdc3939c115d6459"> 7655</a></span><span class="preprocessor">#define FSMC_PCR4_PWID_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07656" name="l07656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga487f41300b79f8833d468b64195315f9"> 7656</a></span><span class="preprocessor">#define FSMC_PCR4_PWID_Msk (0x3UL << FSMC_PCR4_PWID_Pos) </span></div>
|
||
<div class="line"><a id="l07657" name="l07657"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9486b2b7346570ecc5715f1d551c168a"> 7657</a></span><span class="preprocessor">#define FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk </span></div>
|
||
<div class="line"><a id="l07658" name="l07658"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0995cb320e6293ea435df275ce67359f"> 7658</a></span><span class="preprocessor">#define FSMC_PCR4_PWID_0 (0x1UL << FSMC_PCR4_PWID_Pos) </span></div>
|
||
<div class="line"><a id="l07659" name="l07659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b6be32b3844a299a2c92089e81e27e9"> 7659</a></span><span class="preprocessor">#define FSMC_PCR4_PWID_1 (0x2UL << FSMC_PCR4_PWID_Pos) </span></div>
|
||
<div class="line"><a id="l07661" name="l07661"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga424cf5e2f1981675d26adf2196f885fb"> 7661</a></span><span class="preprocessor">#define FSMC_PCR4_ECCEN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l07662" name="l07662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6bee93c8682a87840c8b437c174eb13b"> 7662</a></span><span class="preprocessor">#define FSMC_PCR4_ECCEN_Msk (0x1UL << FSMC_PCR4_ECCEN_Pos) </span></div>
|
||
<div class="line"><a id="l07663" name="l07663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga646509f8bebb0d662c730ed4cabe741f"> 7663</a></span><span class="preprocessor">#define FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk </span></div>
|
||
<div class="line"><a id="l07665" name="l07665"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2db09770ae63805a9a06c0382b66c640"> 7665</a></span><span class="preprocessor">#define FSMC_PCR4_TCLR_Pos (9U) </span></div>
|
||
<div class="line"><a id="l07666" name="l07666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9971f1f3806a65aee5a5993f687c582"> 7666</a></span><span class="preprocessor">#define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07667" name="l07667"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c7164974019263cacbc7dda2fc14126"> 7667</a></span><span class="preprocessor">#define FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk </span></div>
|
||
<div class="line"><a id="l07668" name="l07668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0dd78ad0c755190a69b37ebac75a11dd"> 7668</a></span><span class="preprocessor">#define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07669" name="l07669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0ea2e2287999d3c7d6583aab492514d"> 7669</a></span><span class="preprocessor">#define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07670" name="l07670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34dd56ee892fc187e105e4d820ce3b9a"> 7670</a></span><span class="preprocessor">#define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07671" name="l07671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0eb8dc60a469cfa96b3b3b7fad25ac92"> 7671</a></span><span class="preprocessor">#define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos) </span></div>
|
||
<div class="line"><a id="l07673" name="l07673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf67899acb4972b2feffc057c69460dc2"> 7673</a></span><span class="preprocessor">#define FSMC_PCR4_TAR_Pos (13U) </span></div>
|
||
<div class="line"><a id="l07674" name="l07674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77f6431c476681f6a4e72f807eba2e41"> 7674</a></span><span class="preprocessor">#define FSMC_PCR4_TAR_Msk (0xFUL << FSMC_PCR4_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07675" name="l07675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c583f305906f19b15ce3dc177fa21bd"> 7675</a></span><span class="preprocessor">#define FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk </span></div>
|
||
<div class="line"><a id="l07676" name="l07676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62fe4ede4c658b788596e8ea6f325c9f"> 7676</a></span><span class="preprocessor">#define FSMC_PCR4_TAR_0 (0x1UL << FSMC_PCR4_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07677" name="l07677"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a9958cbf815ac97c3500a46aaf573f5"> 7677</a></span><span class="preprocessor">#define FSMC_PCR4_TAR_1 (0x2UL << FSMC_PCR4_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07678" name="l07678"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga669e16ecd48c92f65bd66f2da63fe53f"> 7678</a></span><span class="preprocessor">#define FSMC_PCR4_TAR_2 (0x4UL << FSMC_PCR4_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07679" name="l07679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad298ef64d36721696517ed0d4ac12d32"> 7679</a></span><span class="preprocessor">#define FSMC_PCR4_TAR_3 (0x8UL << FSMC_PCR4_TAR_Pos) </span></div>
|
||
<div class="line"><a id="l07681" name="l07681"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d07f92979ed4e7985b86118ccf71d9d"> 7681</a></span><span class="preprocessor">#define FSMC_PCR4_ECCPS_Pos (17U) </span></div>
|
||
<div class="line"><a id="l07682" name="l07682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07b5adc339bceccfa581082c73978949"> 7682</a></span><span class="preprocessor">#define FSMC_PCR4_ECCPS_Msk (0x7UL << FSMC_PCR4_ECCPS_Pos) </span></div>
|
||
<div class="line"><a id="l07683" name="l07683"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2308baba97f307b8beb6239702471038"> 7683</a></span><span class="preprocessor">#define FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk </span></div>
|
||
<div class="line"><a id="l07684" name="l07684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76514698225c0734c1e9be46b6dbd298"> 7684</a></span><span class="preprocessor">#define FSMC_PCR4_ECCPS_0 (0x1UL << FSMC_PCR4_ECCPS_Pos) </span></div>
|
||
<div class="line"><a id="l07685" name="l07685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c43076003bbf01f95765125e19ab94d"> 7685</a></span><span class="preprocessor">#define FSMC_PCR4_ECCPS_1 (0x2UL << FSMC_PCR4_ECCPS_Pos) </span></div>
|
||
<div class="line"><a id="l07686" name="l07686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4ba96304e6618d4eb7672cdc3bd8f01"> 7686</a></span><span class="preprocessor">#define FSMC_PCR4_ECCPS_2 (0x4UL << FSMC_PCR4_ECCPS_Pos) </span></div>
|
||
<div class="line"><a id="l07688" name="l07688"></a><span class="lineno"> 7688</span><span class="comment">/******************* Bit definition for FSMC_SR2 register *******************/</span></div>
|
||
<div class="line"><a id="l07689" name="l07689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06ebb4b8d85407f96dcbdf67f4a99cb9"> 7689</a></span><span class="preprocessor">#define FSMC_SR2_IRS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07690" name="l07690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad134a6cdb6d9df958be6f45ea4f952a7"> 7690</a></span><span class="preprocessor">#define FSMC_SR2_IRS_Msk (0x1UL << FSMC_SR2_IRS_Pos) </span></div>
|
||
<div class="line"><a id="l07691" name="l07691"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19f1b90b2da89b68aa754d0a89d60de9"> 7691</a></span><span class="preprocessor">#define FSMC_SR2_IRS FSMC_SR2_IRS_Msk </span></div>
|
||
<div class="line"><a id="l07692" name="l07692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga640c5b0f263676b6d0e5934916f6613d"> 7692</a></span><span class="preprocessor">#define FSMC_SR2_ILS_Pos (1U) </span></div>
|
||
<div class="line"><a id="l07693" name="l07693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88ea643e2a899e222e2c9166f0b47af9"> 7693</a></span><span class="preprocessor">#define FSMC_SR2_ILS_Msk (0x1UL << FSMC_SR2_ILS_Pos) </span></div>
|
||
<div class="line"><a id="l07694" name="l07694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga664d6e1440c12e76dfa34f716af85ed1"> 7694</a></span><span class="preprocessor">#define FSMC_SR2_ILS FSMC_SR2_ILS_Msk </span></div>
|
||
<div class="line"><a id="l07695" name="l07695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45cd1c374a43ee088640e33e95dc5688"> 7695</a></span><span class="preprocessor">#define FSMC_SR2_IFS_Pos (2U) </span></div>
|
||
<div class="line"><a id="l07696" name="l07696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga892a452cb80f67fc2c5f4a0ff775ff5b"> 7696</a></span><span class="preprocessor">#define FSMC_SR2_IFS_Msk (0x1UL << FSMC_SR2_IFS_Pos) </span></div>
|
||
<div class="line"><a id="l07697" name="l07697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6492ad6afe175283d07de38978936dc"> 7697</a></span><span class="preprocessor">#define FSMC_SR2_IFS FSMC_SR2_IFS_Msk </span></div>
|
||
<div class="line"><a id="l07698" name="l07698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64ac90a6d11f1b83eaaba0bbe76225a6"> 7698</a></span><span class="preprocessor">#define FSMC_SR2_IREN_Pos (3U) </span></div>
|
||
<div class="line"><a id="l07699" name="l07699"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99bc457a07a274821c92d025bee142b2"> 7699</a></span><span class="preprocessor">#define FSMC_SR2_IREN_Msk (0x1UL << FSMC_SR2_IREN_Pos) </span></div>
|
||
<div class="line"><a id="l07700" name="l07700"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3216bd665a118239e6ef0b58ec5e8a8e"> 7700</a></span><span class="preprocessor">#define FSMC_SR2_IREN FSMC_SR2_IREN_Msk </span></div>
|
||
<div class="line"><a id="l07701" name="l07701"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada9faf7f03a84292d12b91b59ecc6e8e"> 7701</a></span><span class="preprocessor">#define FSMC_SR2_ILEN_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07702" name="l07702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae59b87df9b2b879f3c6228b44f8e67ec"> 7702</a></span><span class="preprocessor">#define FSMC_SR2_ILEN_Msk (0x1UL << FSMC_SR2_ILEN_Pos) </span></div>
|
||
<div class="line"><a id="l07703" name="l07703"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e9df0edd35d0ad6a35ff3a3b045b47c"> 7703</a></span><span class="preprocessor">#define FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk </span></div>
|
||
<div class="line"><a id="l07704" name="l07704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19ce3774c409a6824a03414035807696"> 7704</a></span><span class="preprocessor">#define FSMC_SR2_IFEN_Pos (5U) </span></div>
|
||
<div class="line"><a id="l07705" name="l07705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b3607ef98ac617609731f96d63a6d8c"> 7705</a></span><span class="preprocessor">#define FSMC_SR2_IFEN_Msk (0x1UL << FSMC_SR2_IFEN_Pos) </span></div>
|
||
<div class="line"><a id="l07706" name="l07706"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga755c088c58b27f79108675f56ea9d196"> 7706</a></span><span class="preprocessor">#define FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk </span></div>
|
||
<div class="line"><a id="l07707" name="l07707"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39d0ccd9fb1c6c802201f0d5b2497892"> 7707</a></span><span class="preprocessor">#define FSMC_SR2_FEMPT_Pos (6U) </span></div>
|
||
<div class="line"><a id="l07708" name="l07708"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa95bc00b8c686ad2b0078d28b0f4830"> 7708</a></span><span class="preprocessor">#define FSMC_SR2_FEMPT_Msk (0x1UL << FSMC_SR2_FEMPT_Pos) </span></div>
|
||
<div class="line"><a id="l07709" name="l07709"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ae2e544a4a515303f49815cdbd5ebbb"> 7709</a></span><span class="preprocessor">#define FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk </span></div>
|
||
<div class="line"><a id="l07711" name="l07711"></a><span class="lineno"> 7711</span><span class="comment">/******************* Bit definition for FSMC_SR3 register *******************/</span></div>
|
||
<div class="line"><a id="l07712" name="l07712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88805716c1271a441d94a540f00d941b"> 7712</a></span><span class="preprocessor">#define FSMC_SR3_IRS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07713" name="l07713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38a4f74813da2200db8d8f7254742593"> 7713</a></span><span class="preprocessor">#define FSMC_SR3_IRS_Msk (0x1UL << FSMC_SR3_IRS_Pos) </span></div>
|
||
<div class="line"><a id="l07714" name="l07714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad929e4a8c1fdb49ee6f690121336afea"> 7714</a></span><span class="preprocessor">#define FSMC_SR3_IRS FSMC_SR3_IRS_Msk </span></div>
|
||
<div class="line"><a id="l07715" name="l07715"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9d20d9eb15db67e6195c83c6bfeba1a"> 7715</a></span><span class="preprocessor">#define FSMC_SR3_ILS_Pos (1U) </span></div>
|
||
<div class="line"><a id="l07716" name="l07716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90c83ca70c1030e39babd809c181301b"> 7716</a></span><span class="preprocessor">#define FSMC_SR3_ILS_Msk (0x1UL << FSMC_SR3_ILS_Pos) </span></div>
|
||
<div class="line"><a id="l07717" name="l07717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9803b4ab5b8cce213a80abc11c751d21"> 7717</a></span><span class="preprocessor">#define FSMC_SR3_ILS FSMC_SR3_ILS_Msk </span></div>
|
||
<div class="line"><a id="l07718" name="l07718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6149a6b31cbb1e18378e183cdbfa7cb6"> 7718</a></span><span class="preprocessor">#define FSMC_SR3_IFS_Pos (2U) </span></div>
|
||
<div class="line"><a id="l07719" name="l07719"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a6b22553c9ad5a974bb1e8288932a54"> 7719</a></span><span class="preprocessor">#define FSMC_SR3_IFS_Msk (0x1UL << FSMC_SR3_IFS_Pos) </span></div>
|
||
<div class="line"><a id="l07720" name="l07720"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafadff6b6f9e6430ada2f56bc9921dd7d"> 7720</a></span><span class="preprocessor">#define FSMC_SR3_IFS FSMC_SR3_IFS_Msk </span></div>
|
||
<div class="line"><a id="l07721" name="l07721"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02bbc52ce42d56880369709c4f256dd3"> 7721</a></span><span class="preprocessor">#define FSMC_SR3_IREN_Pos (3U) </span></div>
|
||
<div class="line"><a id="l07722" name="l07722"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b1cab2aa1407a79d66c5c85029ea815"> 7722</a></span><span class="preprocessor">#define FSMC_SR3_IREN_Msk (0x1UL << FSMC_SR3_IREN_Pos) </span></div>
|
||
<div class="line"><a id="l07723" name="l07723"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12baad15533ecbc57db95ea4939bc782"> 7723</a></span><span class="preprocessor">#define FSMC_SR3_IREN FSMC_SR3_IREN_Msk </span></div>
|
||
<div class="line"><a id="l07724" name="l07724"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2b3bd94d6eddc0cdd3911ad580fa541"> 7724</a></span><span class="preprocessor">#define FSMC_SR3_ILEN_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07725" name="l07725"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafec67196217e783676f157212cfc7976"> 7725</a></span><span class="preprocessor">#define FSMC_SR3_ILEN_Msk (0x1UL << FSMC_SR3_ILEN_Pos) </span></div>
|
||
<div class="line"><a id="l07726" name="l07726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86ac8f1f9f99c81a26fb54b597b57f12"> 7726</a></span><span class="preprocessor">#define FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk </span></div>
|
||
<div class="line"><a id="l07727" name="l07727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c78f3e87e892640e79917b97a58ae0d"> 7727</a></span><span class="preprocessor">#define FSMC_SR3_IFEN_Pos (5U) </span></div>
|
||
<div class="line"><a id="l07728" name="l07728"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65588f7ae2e908af340e5ff1bfb18671"> 7728</a></span><span class="preprocessor">#define FSMC_SR3_IFEN_Msk (0x1UL << FSMC_SR3_IFEN_Pos) </span></div>
|
||
<div class="line"><a id="l07729" name="l07729"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7355e5368013759dbfabfec8b609ca8"> 7729</a></span><span class="preprocessor">#define FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk </span></div>
|
||
<div class="line"><a id="l07730" name="l07730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76a834622c16170caf9cb2e1fb14c452"> 7730</a></span><span class="preprocessor">#define FSMC_SR3_FEMPT_Pos (6U) </span></div>
|
||
<div class="line"><a id="l07731" name="l07731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6436500aea203033a62f7ddcbad814a3"> 7731</a></span><span class="preprocessor">#define FSMC_SR3_FEMPT_Msk (0x1UL << FSMC_SR3_FEMPT_Pos) </span></div>
|
||
<div class="line"><a id="l07732" name="l07732"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga230562cf231dc79cd9354933b39ae7de"> 7732</a></span><span class="preprocessor">#define FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk </span></div>
|
||
<div class="line"><a id="l07734" name="l07734"></a><span class="lineno"> 7734</span><span class="comment">/******************* Bit definition for FSMC_SR4 register *******************/</span></div>
|
||
<div class="line"><a id="l07735" name="l07735"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fd0b4be91d7fa754929c96bb772e40d"> 7735</a></span><span class="preprocessor">#define FSMC_SR4_IRS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07736" name="l07736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga359dc66df56e053e76cf0c8d8b1228f3"> 7736</a></span><span class="preprocessor">#define FSMC_SR4_IRS_Msk (0x1UL << FSMC_SR4_IRS_Pos) </span></div>
|
||
<div class="line"><a id="l07737" name="l07737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga163f7143d51b516af0d46b142222957f"> 7737</a></span><span class="preprocessor">#define FSMC_SR4_IRS FSMC_SR4_IRS_Msk </span></div>
|
||
<div class="line"><a id="l07738" name="l07738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35d76d1ef37af831006e517f4c495b39"> 7738</a></span><span class="preprocessor">#define FSMC_SR4_ILS_Pos (1U) </span></div>
|
||
<div class="line"><a id="l07739" name="l07739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9f640a57868933823d67ed24baae3cd"> 7739</a></span><span class="preprocessor">#define FSMC_SR4_ILS_Msk (0x1UL << FSMC_SR4_ILS_Pos) </span></div>
|
||
<div class="line"><a id="l07740" name="l07740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e19feccd1553911d08be673c4af72ad"> 7740</a></span><span class="preprocessor">#define FSMC_SR4_ILS FSMC_SR4_ILS_Msk </span></div>
|
||
<div class="line"><a id="l07741" name="l07741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaba60426f9ebd437c2fe600929f17b9b"> 7741</a></span><span class="preprocessor">#define FSMC_SR4_IFS_Pos (2U) </span></div>
|
||
<div class="line"><a id="l07742" name="l07742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38930113868c959a3661b7296be4f3b4"> 7742</a></span><span class="preprocessor">#define FSMC_SR4_IFS_Msk (0x1UL << FSMC_SR4_IFS_Pos) </span></div>
|
||
<div class="line"><a id="l07743" name="l07743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1e7d71b32a0b70d772fbdc85f7053fc"> 7743</a></span><span class="preprocessor">#define FSMC_SR4_IFS FSMC_SR4_IFS_Msk </span></div>
|
||
<div class="line"><a id="l07744" name="l07744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7345c2e21921244fde94badae4cb6084"> 7744</a></span><span class="preprocessor">#define FSMC_SR4_IREN_Pos (3U) </span></div>
|
||
<div class="line"><a id="l07745" name="l07745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7026294e98de80663d4530e07ae1777c"> 7745</a></span><span class="preprocessor">#define FSMC_SR4_IREN_Msk (0x1UL << FSMC_SR4_IREN_Pos) </span></div>
|
||
<div class="line"><a id="l07746" name="l07746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f5f17d22e07bb6674cbd68740b9708a"> 7746</a></span><span class="preprocessor">#define FSMC_SR4_IREN FSMC_SR4_IREN_Msk </span></div>
|
||
<div class="line"><a id="l07747" name="l07747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb2544b2d75f937bc0ff66eaa824c8fa"> 7747</a></span><span class="preprocessor">#define FSMC_SR4_ILEN_Pos (4U) </span></div>
|
||
<div class="line"><a id="l07748" name="l07748"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d2d4242df3e464630c5723bf8ce62f9"> 7748</a></span><span class="preprocessor">#define FSMC_SR4_ILEN_Msk (0x1UL << FSMC_SR4_ILEN_Pos) </span></div>
|
||
<div class="line"><a id="l07749" name="l07749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9b8d7c7b68723a4ef01843d547d95bc"> 7749</a></span><span class="preprocessor">#define FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk </span></div>
|
||
<div class="line"><a id="l07750" name="l07750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72c86dadfbc92cb71ada1b69afaf0422"> 7750</a></span><span class="preprocessor">#define FSMC_SR4_IFEN_Pos (5U) </span></div>
|
||
<div class="line"><a id="l07751" name="l07751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf050b0a4e3500f081929ef8893f3a01c"> 7751</a></span><span class="preprocessor">#define FSMC_SR4_IFEN_Msk (0x1UL << FSMC_SR4_IFEN_Pos) </span></div>
|
||
<div class="line"><a id="l07752" name="l07752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf97394e42be634cb441204f6bfffb504"> 7752</a></span><span class="preprocessor">#define FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk </span></div>
|
||
<div class="line"><a id="l07753" name="l07753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2927e164634b8377d7f5de607ffa8aae"> 7753</a></span><span class="preprocessor">#define FSMC_SR4_FEMPT_Pos (6U) </span></div>
|
||
<div class="line"><a id="l07754" name="l07754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad85d7dabbc8635c7fbcf55e18c1b38c7"> 7754</a></span><span class="preprocessor">#define FSMC_SR4_FEMPT_Msk (0x1UL << FSMC_SR4_FEMPT_Pos) </span></div>
|
||
<div class="line"><a id="l07755" name="l07755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae7081cdf26e75bccfac1b6a29c04124"> 7755</a></span><span class="preprocessor">#define FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk </span></div>
|
||
<div class="line"><a id="l07757" name="l07757"></a><span class="lineno"> 7757</span><span class="comment">/****************** Bit definition for FSMC_PMEM2 register ******************/</span></div>
|
||
<div class="line"><a id="l07758" name="l07758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57fea4182c63e845dfaaeffe67d7dcf8"> 7758</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMSET2_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07759" name="l07759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b57a52f74837d3aa9b7731a1a33159b"> 7759</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMSET2_Msk (0xFFUL << FSMC_PMEM2_MEMSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07760" name="l07760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50a34195ddb7ab7aebc2acac39b27536"> 7760</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk </span></div>
|
||
<div class="line"><a id="l07761" name="l07761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga529858550113070878ce680da0a6bf7d"> 7761</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMSET2_0 (0x01UL << FSMC_PMEM2_MEMSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07762" name="l07762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28517c1f5aeded21b3f0326247b0bbe1"> 7762</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMSET2_1 (0x02UL << FSMC_PMEM2_MEMSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07763" name="l07763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f59339df091ad8a00d75c32b335b711"> 7763</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMSET2_2 (0x04UL << FSMC_PMEM2_MEMSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07764" name="l07764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7715c089272c9709e8f94590b46be609"> 7764</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMSET2_3 (0x08UL << FSMC_PMEM2_MEMSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07765" name="l07765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31a0e44106c1ec87375054be15b1cb84"> 7765</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMSET2_4 (0x10UL << FSMC_PMEM2_MEMSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07766" name="l07766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga221edf50060c5dad91de3c0b877fdbfc"> 7766</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMSET2_5 (0x20UL << FSMC_PMEM2_MEMSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07767" name="l07767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5dc6beefe3ea22a84dbc44fd30843778"> 7767</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMSET2_6 (0x40UL << FSMC_PMEM2_MEMSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07768" name="l07768"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae14181cbd85100c2b3b104525c42ee6c"> 7768</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMSET2_7 (0x80UL << FSMC_PMEM2_MEMSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07770" name="l07770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0072f7fa82f3fb4ca184511738fc4d30"> 7770</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07771" name="l07771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90343ef2f0e0433265e721aeba552f3f"> 7771</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07772" name="l07772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7affee760cfe5d04a58bda9cd7fc5f72"> 7772</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk </span></div>
|
||
<div class="line"><a id="l07773" name="l07773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ee1c7f3347678dff204e6ac8c6eaf4f"> 7773</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_0 (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07774" name="l07774"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56de464fa3f895e75f0ec2ff3f9e1e1e"> 7774</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_1 (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07775" name="l07775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga922a823292054746923fb13b8f4c1b5c"> 7775</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_2 (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07776" name="l07776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44f9c0141f457b0ef0ff42c1645d7337"> 7776</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_3 (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07777" name="l07777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d15645ffe422f3e35cc03efd93361cb"> 7777</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_4 (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07778" name="l07778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga640d5866b22b11924b7e4c9bfc608624"> 7778</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_5 (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07779" name="l07779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51d69f501306eae03db719cb52065b3c"> 7779</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_6 (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07780" name="l07780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga127b0e01d15f1007cfa67247a99da26f"> 7780</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_7 (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07782" name="l07782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e62ae5b193c0df1b570af7489ad9e78"> 7782</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07783" name="l07783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f1e5661bbb15ad918a6e2f7d09fcfe6"> 7783</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07784" name="l07784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad2c79ef9df8b619e93c15b506f4fd7d"> 7784</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk </span></div>
|
||
<div class="line"><a id="l07785" name="l07785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd16a720c69fcac1f6b798cf6f9bbb7e"> 7785</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_0 (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07786" name="l07786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4630e2bdb842914d0f7b53d4ed610122"> 7786</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_1 (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07787" name="l07787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf699fd414971d0c52159c21652f5e58"> 7787</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_2 (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07788" name="l07788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3e1f50389b82f8737a12ef6d1683c4f"> 7788</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_3 (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07789" name="l07789"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00c7b1a8cbcbcbcc0495ebd7c877ca9e"> 7789</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_4 (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07790" name="l07790"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9cd7c5637824522c2bd0f2cd165ca218"> 7790</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_5 (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07791" name="l07791"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52ee3806d174025ab98d6c9148f17ae2"> 7791</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_6 (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07792" name="l07792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1afae5788b827aebc3df92c74754b38"> 7792</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_7 (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07794" name="l07794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1964483dae67a5aff01ddd046583acb7"> 7794</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_Pos (24U) </span></div>
|
||
<div class="line"><a id="l07795" name="l07795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6155f1c3280ce295a8c90bb5e3dfba9"> 7795</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07796" name="l07796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a7783e155a688bf79e68ebf570421c4"> 7796</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk </span></div>
|
||
<div class="line"><a id="l07797" name="l07797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8bb51ecefa94c1ab3b91c7a14705b8c8"> 7797</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_0 (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07798" name="l07798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c0d8bf861d9918763b7391d4ad287b0"> 7798</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_1 (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07799" name="l07799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebd6a4457fa0ac4f1b98fdc58bef9999"> 7799</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_2 (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07800" name="l07800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaded9a6b1b516fa2595988c84c5465f9b"> 7800</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_3 (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07801" name="l07801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9b1831fb25422c7a126a7d029223394"> 7801</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_4 (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07802" name="l07802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae828a4dde56e15f78ab156feeb329af9"> 7802</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_5 (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07803" name="l07803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf5464a2e8aeec6eb06c58283168ef97"> 7803</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_6 (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07804" name="l07804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c5ca1880a516478e1b8f1142066c004"> 7804</a></span><span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_7 (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07806" name="l07806"></a><span class="lineno"> 7806</span><span class="comment">/****************** Bit definition for FSMC_PMEM3 register ******************/</span></div>
|
||
<div class="line"><a id="l07807" name="l07807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2db6b5656145efa4ae5c03d5932a5abf"> 7807</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMSET3_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07808" name="l07808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa58775ce9ebda0e97d4bf481c7bd53e"> 7808</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMSET3_Msk (0xFFUL << FSMC_PMEM3_MEMSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07809" name="l07809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf69ac574f9be3c11ada1e2dc4c3abe4f"> 7809</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk </span></div>
|
||
<div class="line"><a id="l07810" name="l07810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee68bc7ff3e4cf11c2ca826541858c6a"> 7810</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMSET3_0 (0x01UL << FSMC_PMEM3_MEMSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07811" name="l07811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa10132605ec4a4be1ab48ee6b36080e"> 7811</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMSET3_1 (0x02UL << FSMC_PMEM3_MEMSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07812" name="l07812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd867b06de7c7a49244b6a35570d2cd2"> 7812</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMSET3_2 (0x04UL << FSMC_PMEM3_MEMSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07813" name="l07813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga292a8826723614aa2504a376f4a2e5d5"> 7813</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMSET3_3 (0x08UL << FSMC_PMEM3_MEMSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07814" name="l07814"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98703fee6465ba580b052ef76f2c63f2"> 7814</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMSET3_4 (0x10UL << FSMC_PMEM3_MEMSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07815" name="l07815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaea28a64fc9a7e0df35826b4ec372361"> 7815</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMSET3_5 (0x20UL << FSMC_PMEM3_MEMSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07816" name="l07816"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea51bbe866574be10bdc1d2d16bb9810"> 7816</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMSET3_6 (0x40UL << FSMC_PMEM3_MEMSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07817" name="l07817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga702eeb8c3930ea564af728cc3bb9044b"> 7817</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMSET3_7 (0x80UL << FSMC_PMEM3_MEMSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07819" name="l07819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fae8d256e50724a047b115add6b6f8c"> 7819</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07820" name="l07820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57e03075040da97e636158721615ca93"> 7820</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07821" name="l07821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4243cb8b53a10143621872c0d0ed318b"> 7821</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk </span></div>
|
||
<div class="line"><a id="l07822" name="l07822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30d8aad77f584d1c380b6d04d4984ac5"> 7822</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_0 (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07823" name="l07823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacf4638838e3cf2dfa076ef795596967"> 7823</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_1 (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07824" name="l07824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1c65a1027062f3fff04dfdd24c33e64"> 7824</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_2 (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07825" name="l07825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae23146168ddc8e06defd6e75390dde1d"> 7825</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_3 (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07826" name="l07826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79640d63c03f94bd4f38859c46bad820"> 7826</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_4 (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07827" name="l07827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d36841fa1730bbbc825278cffd623f3"> 7827</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_5 (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07828" name="l07828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bd34f98ee23b7a58ac63cd195c00d70"> 7828</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_6 (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07829" name="l07829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f485579592b7fdf2e480523ee220418"> 7829</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_7 (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07831" name="l07831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6130db15261d3342f1f6882fabccb590"> 7831</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07832" name="l07832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1dba6050327dc9b2282e64e8236e6725"> 7832</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07833" name="l07833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8ef1e0f4db1e2792b0939f9058a149b"> 7833</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk </span></div>
|
||
<div class="line"><a id="l07834" name="l07834"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1abd4698bb45c784b23b8d431eb90f1"> 7834</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_0 (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07835" name="l07835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a93e71d784bdb1cd115805feac42d6b"> 7835</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_1 (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07836" name="l07836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20a5443b5236e71b8dfe0620abffbd68"> 7836</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_2 (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07837" name="l07837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b330eabb266b26cf6aa93b12bfe7b38"> 7837</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_3 (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07838" name="l07838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6d1864268bb87124d127d92e8db54dc"> 7838</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_4 (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07839" name="l07839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8968569a91c0b5d6c456074ddfc98aa3"> 7839</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_5 (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07840" name="l07840"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf40967f9e19b41e2692b7fe1177b8629"> 7840</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_6 (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07841" name="l07841"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0da29e1e300e47aebb0bd47bf5f0563"> 7841</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_7 (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07843" name="l07843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14b9bedec189a62c563088a91e1a4a0e"> 7843</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_Pos (24U) </span></div>
|
||
<div class="line"><a id="l07844" name="l07844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0dfe7b65ecc252eca58b04156dbd4c32"> 7844</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07845" name="l07845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a77d54c66589f233792d30fc83e7f12"> 7845</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk </span></div>
|
||
<div class="line"><a id="l07846" name="l07846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d8453ab8a7488ff13c681154bfd293c"> 7846</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_0 (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07847" name="l07847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf023951ad4fd31a691cc26fc3c27ec46"> 7847</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_1 (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07848" name="l07848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf8d790834161e0224c878cd8eab190e"> 7848</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_2 (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07849" name="l07849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26daeb039123824e2de5fdd64cb3a1ff"> 7849</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_3 (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07850" name="l07850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd06d96e44933ce665b2af8c2a4098e4"> 7850</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_4 (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07851" name="l07851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef1254b2e2251da2b30aa297d1d0a1f8"> 7851</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_5 (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07852" name="l07852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf33c72c5ab0747d587a801835cf1a897"> 7852</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_6 (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07853" name="l07853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7304d0d28edd32a70be474e656fbf8e"> 7853</a></span><span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_7 (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07855" name="l07855"></a><span class="lineno"> 7855</span><span class="comment">/****************** Bit definition for FSMC_PMEM4 register ******************/</span></div>
|
||
<div class="line"><a id="l07856" name="l07856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeec8eeb3ff3a51842b4bc3a0f01315c0"> 7856</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMSET4_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07857" name="l07857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6506768173e0734a59f62d527f3f0a4"> 7857</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMSET4_Msk (0xFFUL << FSMC_PMEM4_MEMSET4_Pos) </span></div>
|
||
<div class="line"><a id="l07858" name="l07858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b5cb5385ce2cef772ee4493c25617aa"> 7858</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk </span></div>
|
||
<div class="line"><a id="l07859" name="l07859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6df1a1190522593b71da113c7ea8cfab"> 7859</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMSET4_0 (0x01UL << FSMC_PMEM4_MEMSET4_Pos) </span></div>
|
||
<div class="line"><a id="l07860" name="l07860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fa76a9c077f40e973df8fe6903c69c4"> 7860</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMSET4_1 (0x02UL << FSMC_PMEM4_MEMSET4_Pos) </span></div>
|
||
<div class="line"><a id="l07861" name="l07861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03ddc1ecb61313593976bf70aec06e9f"> 7861</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMSET4_2 (0x04UL << FSMC_PMEM4_MEMSET4_Pos) </span></div>
|
||
<div class="line"><a id="l07862" name="l07862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4280253a6049c7739c6b70a6d7940998"> 7862</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMSET4_3 (0x08UL << FSMC_PMEM4_MEMSET4_Pos) </span></div>
|
||
<div class="line"><a id="l07863" name="l07863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga153d7b557dc40b797f93bf5593808279"> 7863</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMSET4_4 (0x10UL << FSMC_PMEM4_MEMSET4_Pos) </span></div>
|
||
<div class="line"><a id="l07864" name="l07864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc8fc6eadc2e952227c121b6d6114834"> 7864</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMSET4_5 (0x20UL << FSMC_PMEM4_MEMSET4_Pos) </span></div>
|
||
<div class="line"><a id="l07865" name="l07865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecce633b6da6db82000f1d39dc23bb3b"> 7865</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMSET4_6 (0x40UL << FSMC_PMEM4_MEMSET4_Pos) </span></div>
|
||
<div class="line"><a id="l07866" name="l07866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04c68698ff6f47551244ae5a26893059"> 7866</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMSET4_7 (0x80UL << FSMC_PMEM4_MEMSET4_Pos) </span></div>
|
||
<div class="line"><a id="l07868" name="l07868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga265881544d02839df4b2a9b03be04358"> 7868</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07869" name="l07869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb6d7917d078c6ccdc62cd80e9578513"> 7869</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l07870" name="l07870"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9673f81abf15ad70d09520db9ddfc58d"> 7870</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk </span></div>
|
||
<div class="line"><a id="l07871" name="l07871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c88b294c963e5be76da4bf3048af411"> 7871</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_0 (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l07872" name="l07872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24d45891fa0a503d81f68f62f5fd18e5"> 7872</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_1 (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l07873" name="l07873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1fa35a7722b6339a7cef85b5be2280d"> 7873</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_2 (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l07874" name="l07874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga929f7f1066e3f2d69c72126615d06cb0"> 7874</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_3 (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l07875" name="l07875"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5282e3d9205f778b67ef00c27beb2918"> 7875</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_4 (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l07876" name="l07876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1eed44a0b89a9f14b08c4ab2578ca5cc"> 7876</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_5 (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l07877" name="l07877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2429913d3b7993dfda75413f0a72bf4"> 7877</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_6 (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l07878" name="l07878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga247eb296ad16d1c7f2ebea0ca85619f9"> 7878</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_7 (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l07880" name="l07880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa288ec797541c772dfd1ce78ef63335e"> 7880</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07881" name="l07881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0cf6a3b9e83d5785668a232f179922b"> 7881</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l07882" name="l07882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5028f0c2a642b7faedf602f0b2c0d64c"> 7882</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk </span></div>
|
||
<div class="line"><a id="l07883" name="l07883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf07eef15a372886fda3182f49e2e912e"> 7883</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_0 (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l07884" name="l07884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa05a691ca81b6fe6df07adb1c5142597"> 7884</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_1 (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l07885" name="l07885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafd4f50c33f4ec69e878983fb6065c73"> 7885</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_2 (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l07886" name="l07886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3cf67d6699d41fc042aed2be6d6aef0"> 7886</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_3 (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l07887" name="l07887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga963acb8aef1a1e3f7f369421a3f9bfd9"> 7887</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_4 (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l07888" name="l07888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3ca8c6eb5fde2be7d38bde8aedb5522"> 7888</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_5 (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l07889" name="l07889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0352f9aa02c4037d690b516d7385d27"> 7889</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_6 (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l07890" name="l07890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga880aa86c933687f7565b7ab79776923e"> 7890</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_7 (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l07892" name="l07892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab27dd74b58a232a823408c58277b19ef"> 7892</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_Pos (24U) </span></div>
|
||
<div class="line"><a id="l07893" name="l07893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa99cb02c3b57623c92d17f68b44f84a4"> 7893</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l07894" name="l07894"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b194500112e61e5dd41ded843bb08c6"> 7894</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk </span></div>
|
||
<div class="line"><a id="l07895" name="l07895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9298e847d13d24cbe87a3c477af9f02c"> 7895</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_0 (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l07896" name="l07896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga591eb0822bbb91c4ba12f80d35424c4c"> 7896</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_1 (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l07897" name="l07897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6db858408154b3694bb1fdc995f7e069"> 7897</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_2 (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l07898" name="l07898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e38ef7ec628928bea867de00af9b206"> 7898</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_3 (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l07899" name="l07899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81a86c24f41bd5363793953df972d941"> 7899</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_4 (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l07900" name="l07900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08a6ec2df1aa20cfcfacaed7e60417a0"> 7900</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_5 (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l07901" name="l07901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga443fff9e0a661cce0d3fe96886eceb0b"> 7901</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_6 (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l07902" name="l07902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90cf92af2475f9f7cadbb9553225260d"> 7902</a></span><span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_7 (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l07904" name="l07904"></a><span class="lineno"> 7904</span><span class="comment">/****************** Bit definition for FSMC_PATT2 register ******************/</span></div>
|
||
<div class="line"><a id="l07905" name="l07905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc7a654ded670713a8926626faad19db"> 7905</a></span><span class="preprocessor">#define FSMC_PATT2_ATTSET2_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07906" name="l07906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc4ae266a174a451c7eff4c6e82a08d6"> 7906</a></span><span class="preprocessor">#define FSMC_PATT2_ATTSET2_Msk (0xFFUL << FSMC_PATT2_ATTSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07907" name="l07907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab6cd1418de73ee3b214be589912e45f"> 7907</a></span><span class="preprocessor">#define FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk </span></div>
|
||
<div class="line"><a id="l07908" name="l07908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab4718770edfb1b9b96df7410a58f79b"> 7908</a></span><span class="preprocessor">#define FSMC_PATT2_ATTSET2_0 (0x01UL << FSMC_PATT2_ATTSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07909" name="l07909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4cde8c8360b22a3fb63615b4274653c9"> 7909</a></span><span class="preprocessor">#define FSMC_PATT2_ATTSET2_1 (0x02UL << FSMC_PATT2_ATTSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07910" name="l07910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae80034b8760da9dd1faaf7e326b6002a"> 7910</a></span><span class="preprocessor">#define FSMC_PATT2_ATTSET2_2 (0x04UL << FSMC_PATT2_ATTSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07911" name="l07911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11924ff951b3e939d2d20807901a82bf"> 7911</a></span><span class="preprocessor">#define FSMC_PATT2_ATTSET2_3 (0x08UL << FSMC_PATT2_ATTSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07912" name="l07912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1b81efbb998d5e86685075396fd83b0"> 7912</a></span><span class="preprocessor">#define FSMC_PATT2_ATTSET2_4 (0x10UL << FSMC_PATT2_ATTSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07913" name="l07913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e89896b03049ad636484b44c7ecd670"> 7913</a></span><span class="preprocessor">#define FSMC_PATT2_ATTSET2_5 (0x20UL << FSMC_PATT2_ATTSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07914" name="l07914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac751391f5acb1f3229ca65a3424d316d"> 7914</a></span><span class="preprocessor">#define FSMC_PATT2_ATTSET2_6 (0x40UL << FSMC_PATT2_ATTSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07915" name="l07915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb0f3115642332e5aef5cfa1b6b719d8"> 7915</a></span><span class="preprocessor">#define FSMC_PATT2_ATTSET2_7 (0x80UL << FSMC_PATT2_ATTSET2_Pos) </span></div>
|
||
<div class="line"><a id="l07917" name="l07917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae092c85efe222aa5d2788335544ab0f1"> 7917</a></span><span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07918" name="l07918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91b82eb626e2249b2365749e2ddd5b82"> 7918</a></span><span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_Msk (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07919" name="l07919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fda97184969b04e909ac97d31da48e6"> 7919</a></span><span class="preprocessor">#define FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk </span></div>
|
||
<div class="line"><a id="l07920" name="l07920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf43a2874230fbe9b87f9495a736b9363"> 7920</a></span><span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_0 (0x01UL << FSMC_PATT2_ATTWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07921" name="l07921"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad30fbb45343ced8deb9bbc062dba46b"> 7921</a></span><span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_1 (0x02UL << FSMC_PATT2_ATTWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07922" name="l07922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae78c7794f66cd2063464ab2e6ef2bd07"> 7922</a></span><span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_2 (0x04UL << FSMC_PATT2_ATTWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07923" name="l07923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82c2de9009c75560a342122937b25853"> 7923</a></span><span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_3 (0x08UL << FSMC_PATT2_ATTWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07924" name="l07924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae80b6a2fc197435f6b50b4ba035fb5fe"> 7924</a></span><span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_4 (0x10UL << FSMC_PATT2_ATTWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07925" name="l07925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac924773c5fcbee73186600247618d10b"> 7925</a></span><span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_5 (0x20UL << FSMC_PATT2_ATTWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07926" name="l07926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70b22c0b9a32e473f0eb56952ba58d95"> 7926</a></span><span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_6 (0x40UL << FSMC_PATT2_ATTWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07927" name="l07927"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ade8feb15ddcef159ccf3ff55fb0c24"> 7927</a></span><span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_7 (0x80UL << FSMC_PATT2_ATTWAIT2_Pos) </span></div>
|
||
<div class="line"><a id="l07929" name="l07929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82a9f758e7aac1ee2529a904e5ae7e62"> 7929</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07930" name="l07930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga836b8150e0ee69c3acc4e1330ad8c9f2"> 7930</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_Msk (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07931" name="l07931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad007c3c6fbef432a5e6bb08bd6e0b1ce"> 7931</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk </span></div>
|
||
<div class="line"><a id="l07932" name="l07932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b5e19eb38592e84b9c0f3f57df51892"> 7932</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_0 (0x01UL << FSMC_PATT2_ATTHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07933" name="l07933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13dface112bf1300689a4f00ba31abac"> 7933</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_1 (0x02UL << FSMC_PATT2_ATTHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07934" name="l07934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea0e1b34ac27f20c85db0f96eaeff994"> 7934</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_2 (0x04UL << FSMC_PATT2_ATTHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07935" name="l07935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1582860673c5e72f9441095d5af7b8ad"> 7935</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_3 (0x08UL << FSMC_PATT2_ATTHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07936" name="l07936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdd679f3b80617291639cafcdd8f77d1"> 7936</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_4 (0x10UL << FSMC_PATT2_ATTHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07937" name="l07937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34e89cd935ec26279bc9876d9dd07b07"> 7937</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_5 (0x20UL << FSMC_PATT2_ATTHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07938" name="l07938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12c42d6d5746ef8d763d36b04f6e4644"> 7938</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_6 (0x40UL << FSMC_PATT2_ATTHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07939" name="l07939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93558ba1372a3709316b4734160b3874"> 7939</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_7 (0x80UL << FSMC_PATT2_ATTHOLD2_Pos) </span></div>
|
||
<div class="line"><a id="l07941" name="l07941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a79c090eb6e9372f579f1912d266a51"> 7941</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_Pos (24U) </span></div>
|
||
<div class="line"><a id="l07942" name="l07942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68a00587d76421282a4c27b05ab794e4"> 7942</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_Msk (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07943" name="l07943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2726cd505612675158551fd9eed763f"> 7943</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk </span></div>
|
||
<div class="line"><a id="l07944" name="l07944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1ff9b8faa8372116ca931826d18a9c7"> 7944</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_0 (0x01UL << FSMC_PATT2_ATTHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07945" name="l07945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac4081b55783073164985488c9d4d6b8"> 7945</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_1 (0x02UL << FSMC_PATT2_ATTHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07946" name="l07946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3cc10b4217452bae11c69ed9f6f1844"> 7946</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_2 (0x04UL << FSMC_PATT2_ATTHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07947" name="l07947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93e2929a1bcde578f374bbebaa9482d1"> 7947</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_3 (0x08UL << FSMC_PATT2_ATTHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07948" name="l07948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac536419b5ef258fa3f9140387e2f134f"> 7948</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_4 (0x10UL << FSMC_PATT2_ATTHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07949" name="l07949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5deab3153671ff06832dd651372f9ca7"> 7949</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_5 (0x20UL << FSMC_PATT2_ATTHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07950" name="l07950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga047723a357976aca5bdf6575327986d2"> 7950</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_6 (0x40UL << FSMC_PATT2_ATTHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07951" name="l07951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga859a5af02e12a11e7548085e9e186547"> 7951</a></span><span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_7 (0x80UL << FSMC_PATT2_ATTHIZ2_Pos) </span></div>
|
||
<div class="line"><a id="l07953" name="l07953"></a><span class="lineno"> 7953</span><span class="comment">/****************** Bit definition for FSMC_PATT3 register ******************/</span></div>
|
||
<div class="line"><a id="l07954" name="l07954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ec2d77c99acc018d13e3f95ef8072b4"> 7954</a></span><span class="preprocessor">#define FSMC_PATT3_ATTSET3_Pos (0U) </span></div>
|
||
<div class="line"><a id="l07955" name="l07955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ea2296ea7aafbc8aadd589669dfb638"> 7955</a></span><span class="preprocessor">#define FSMC_PATT3_ATTSET3_Msk (0xFFUL << FSMC_PATT3_ATTSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07956" name="l07956"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0487c57e948411f16c3a35927e60dd5"> 7956</a></span><span class="preprocessor">#define FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk </span></div>
|
||
<div class="line"><a id="l07957" name="l07957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e68a5b1bb5996422eac084d586359d4"> 7957</a></span><span class="preprocessor">#define FSMC_PATT3_ATTSET3_0 (0x01UL << FSMC_PATT3_ATTSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07958" name="l07958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d8bd09ad36ab8cae67f87cb930ea428"> 7958</a></span><span class="preprocessor">#define FSMC_PATT3_ATTSET3_1 (0x02UL << FSMC_PATT3_ATTSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07959" name="l07959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29b9389601899ce2731c612ad05d9a96"> 7959</a></span><span class="preprocessor">#define FSMC_PATT3_ATTSET3_2 (0x04UL << FSMC_PATT3_ATTSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07960" name="l07960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97893656a7b65ec5420382de0b264a11"> 7960</a></span><span class="preprocessor">#define FSMC_PATT3_ATTSET3_3 (0x08UL << FSMC_PATT3_ATTSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07961" name="l07961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a6993a1cc304b9300bdc365c2827d43"> 7961</a></span><span class="preprocessor">#define FSMC_PATT3_ATTSET3_4 (0x10UL << FSMC_PATT3_ATTSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07962" name="l07962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cf65f61ce823183c3866607cab6bd09"> 7962</a></span><span class="preprocessor">#define FSMC_PATT3_ATTSET3_5 (0x20UL << FSMC_PATT3_ATTSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07963" name="l07963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2d5a3dd16094a6279766692694aa16b"> 7963</a></span><span class="preprocessor">#define FSMC_PATT3_ATTSET3_6 (0x40UL << FSMC_PATT3_ATTSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07964" name="l07964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7668853b7956cdb13fd73ed10faf4526"> 7964</a></span><span class="preprocessor">#define FSMC_PATT3_ATTSET3_7 (0x80UL << FSMC_PATT3_ATTSET3_Pos) </span></div>
|
||
<div class="line"><a id="l07966" name="l07966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9a5135aee8bd8f89325962d2598aaae"> 7966</a></span><span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_Pos (8U) </span></div>
|
||
<div class="line"><a id="l07967" name="l07967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93f4da8f79e8595a22f0089aa1a3085b"> 7967</a></span><span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_Msk (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07968" name="l07968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8aaf4c77a663cab07ac6c365a271599"> 7968</a></span><span class="preprocessor">#define FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk </span></div>
|
||
<div class="line"><a id="l07969" name="l07969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5c5500a07e7885de5c372c55f147836"> 7969</a></span><span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_0 (0x01UL << FSMC_PATT3_ATTWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07970" name="l07970"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddddbd0a403b2aeefcfdb28a7da56bf0"> 7970</a></span><span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_1 (0x02UL << FSMC_PATT3_ATTWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07971" name="l07971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac34cbe7e282e1074e6c4b9645e48db2f"> 7971</a></span><span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_2 (0x04UL << FSMC_PATT3_ATTWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07972" name="l07972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga771f2a5acde98a9760eb8a1338f416a3"> 7972</a></span><span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_3 (0x08UL << FSMC_PATT3_ATTWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07973" name="l07973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bcc944836a379b2b878d5129ff94ddb"> 7973</a></span><span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_4 (0x10UL << FSMC_PATT3_ATTWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07974" name="l07974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf722482193ca6a1bf90f17af567e019"> 7974</a></span><span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_5 (0x20UL << FSMC_PATT3_ATTWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07975" name="l07975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2cc3ce135f309f7574f0c3d1a0ffe88"> 7975</a></span><span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_6 (0x40UL << FSMC_PATT3_ATTWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07976" name="l07976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa66342cc1db5dcad99153b5a2f22140e"> 7976</a></span><span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_7 (0x80UL << FSMC_PATT3_ATTWAIT3_Pos) </span></div>
|
||
<div class="line"><a id="l07978" name="l07978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05923158d59d724b0beec495f7ea9fcf"> 7978</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_Pos (16U) </span></div>
|
||
<div class="line"><a id="l07979" name="l07979"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9cd55c17fa5ff544f7d19482034dd6de"> 7979</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_Msk (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07980" name="l07980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3a2e634d0f5e3c9716c0910e1efda60"> 7980</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk </span></div>
|
||
<div class="line"><a id="l07981" name="l07981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad34a9f1b84d670c4132c56fa30ca26f0"> 7981</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_0 (0x01UL << FSMC_PATT3_ATTHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07982" name="l07982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b2ed392d654694fc330c6721bed5728"> 7982</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_1 (0x02UL << FSMC_PATT3_ATTHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07983" name="l07983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga679d3ea50788981dac810ec62bc372f0"> 7983</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_2 (0x04UL << FSMC_PATT3_ATTHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07984" name="l07984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75d74cf52f238826e87d3a3c27b52acc"> 7984</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_3 (0x08UL << FSMC_PATT3_ATTHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07985" name="l07985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8d656d40279e1655a6682dcc2762e92"> 7985</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_4 (0x10UL << FSMC_PATT3_ATTHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07986" name="l07986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafee75f2fcf37e20e983732f258f85371"> 7986</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_5 (0x20UL << FSMC_PATT3_ATTHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07987" name="l07987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga777b93e1e3c802ede605644d3ff3bba7"> 7987</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_6 (0x40UL << FSMC_PATT3_ATTHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07988" name="l07988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39acada8d54a7a14d3838d042397bd74"> 7988</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_7 (0x80UL << FSMC_PATT3_ATTHOLD3_Pos) </span></div>
|
||
<div class="line"><a id="l07990" name="l07990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaae5fdcc70300b0e9c7b69d31c9173b5"> 7990</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_Pos (24U) </span></div>
|
||
<div class="line"><a id="l07991" name="l07991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbbd7b49755e0e7052d77f774d72ca18"> 7991</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_Msk (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07992" name="l07992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea9d34b131aa7db353eef060ca37788c"> 7992</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_Msk </span></div>
|
||
<div class="line"><a id="l07993" name="l07993"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bc6736af23f6f033568e0085cd19964"> 7993</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_0 (0x01UL << FSMC_PATT3_ATTHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07994" name="l07994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41270d0ae8670f39b886b49e47e8195b"> 7994</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_1 (0x02UL << FSMC_PATT3_ATTHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07995" name="l07995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga988ec453492aafacf205895c5398caf2"> 7995</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_2 (0x04UL << FSMC_PATT3_ATTHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07996" name="l07996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48885375147c060687bbccc6a234ce39"> 7996</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_3 (0x08UL << FSMC_PATT3_ATTHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07997" name="l07997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ea193881223470d7b6a6ca3e3474a84"> 7997</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_4 (0x10UL << FSMC_PATT3_ATTHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07998" name="l07998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ab1f4cb68cfb8717d2b29e3a84987b1"> 7998</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_5 (0x20UL << FSMC_PATT3_ATTHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l07999" name="l07999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44fd348b342ec248b821123f3310f475"> 7999</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_6 (0x40UL << FSMC_PATT3_ATTHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l08000" name="l08000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ff1a3acc9bbab229000d48845ea1863"> 8000</a></span><span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_7 (0x80UL << FSMC_PATT3_ATTHIZ3_Pos) </span></div>
|
||
<div class="line"><a id="l08002" name="l08002"></a><span class="lineno"> 8002</span><span class="comment">/****************** Bit definition for FSMC_PATT4 register ******************/</span></div>
|
||
<div class="line"><a id="l08003" name="l08003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02c498b211356b2ff396a8f793ae1f88"> 8003</a></span><span class="preprocessor">#define FSMC_PATT4_ATTSET4_Pos (0U) </span></div>
|
||
<div class="line"><a id="l08004" name="l08004"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8ee09881a3a83d040c49e7ec91e16f8"> 8004</a></span><span class="preprocessor">#define FSMC_PATT4_ATTSET4_Msk (0xFFUL << FSMC_PATT4_ATTSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08005" name="l08005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f4d8fb0d47b4a3fddf55c2532dd3159"> 8005</a></span><span class="preprocessor">#define FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_Msk </span></div>
|
||
<div class="line"><a id="l08006" name="l08006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1dac8bcf03610eb2d43b557f4d81532a"> 8006</a></span><span class="preprocessor">#define FSMC_PATT4_ATTSET4_0 (0x01UL << FSMC_PATT4_ATTSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08007" name="l08007"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac2576c2a95871cbf9babd0778372571"> 8007</a></span><span class="preprocessor">#define FSMC_PATT4_ATTSET4_1 (0x02UL << FSMC_PATT4_ATTSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08008" name="l08008"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88e760bbe9714ac07f381de3af0abc36"> 8008</a></span><span class="preprocessor">#define FSMC_PATT4_ATTSET4_2 (0x04UL << FSMC_PATT4_ATTSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08009" name="l08009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b472fd4848733a921998f0305b5bc02"> 8009</a></span><span class="preprocessor">#define FSMC_PATT4_ATTSET4_3 (0x08UL << FSMC_PATT4_ATTSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08010" name="l08010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7d0c69190a0d78fedc875c3dc6b9037"> 8010</a></span><span class="preprocessor">#define FSMC_PATT4_ATTSET4_4 (0x10UL << FSMC_PATT4_ATTSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08011" name="l08011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga168c6f16be9721a5ea0e31230bd1939b"> 8011</a></span><span class="preprocessor">#define FSMC_PATT4_ATTSET4_5 (0x20UL << FSMC_PATT4_ATTSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08012" name="l08012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72fe744c036b2acc4fff8733ac48b0ae"> 8012</a></span><span class="preprocessor">#define FSMC_PATT4_ATTSET4_6 (0x40UL << FSMC_PATT4_ATTSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08013" name="l08013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4529b17de7cb4eeeff25496620978adc"> 8013</a></span><span class="preprocessor">#define FSMC_PATT4_ATTSET4_7 (0x80UL << FSMC_PATT4_ATTSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08015" name="l08015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11a97fde0b98868526b7ea722e3185d3"> 8015</a></span><span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_Pos (8U) </span></div>
|
||
<div class="line"><a id="l08016" name="l08016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9b0b756ec9357585c52037f88e87c00"> 8016</a></span><span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_Msk (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08017" name="l08017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01edeaedc31867997a188fa89cab2ec0"> 8017</a></span><span class="preprocessor">#define FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_Msk </span></div>
|
||
<div class="line"><a id="l08018" name="l08018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5da7db34cd23f3126f224a0b845a66a8"> 8018</a></span><span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_0 (0x01UL << FSMC_PATT4_ATTWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08019" name="l08019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14644aa2ed55afe2094015d74843a994"> 8019</a></span><span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_1 (0x02UL << FSMC_PATT4_ATTWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08020" name="l08020"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1023d5ae8fab70e7fdfbaff4ed46657"> 8020</a></span><span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_2 (0x04UL << FSMC_PATT4_ATTWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08021" name="l08021"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga906c9684ffcd8f0f9222cbfd0e21885a"> 8021</a></span><span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_3 (0x08UL << FSMC_PATT4_ATTWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08022" name="l08022"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8d341a7448f645a2f849e591515f020"> 8022</a></span><span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_4 (0x10UL << FSMC_PATT4_ATTWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08023" name="l08023"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf278272c5fdaa8fa7c84e1c095690632"> 8023</a></span><span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_5 (0x20UL << FSMC_PATT4_ATTWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08024" name="l08024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3126347e126717a761af0b6e44b9d72d"> 8024</a></span><span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_6 (0x40UL << FSMC_PATT4_ATTWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08025" name="l08025"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34afb78710ca450ac7065f0bc263075c"> 8025</a></span><span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_7 (0x80UL << FSMC_PATT4_ATTWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08027" name="l08027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga443220812626d4a02edc701390f33a3d"> 8027</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_Pos (16U) </span></div>
|
||
<div class="line"><a id="l08028" name="l08028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0108d421a275b527d8cb978b6d9685ce"> 8028</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_Msk (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08029" name="l08029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bf06c395d55c775b4fbe202bac517a6"> 8029</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_Msk </span></div>
|
||
<div class="line"><a id="l08030" name="l08030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5c97b102bd1f2b61dcfb793c0d61d66"> 8030</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_0 (0x01UL << FSMC_PATT4_ATTHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08031" name="l08031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga738c8d87ebcdff68725a54ff7f39675d"> 8031</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_1 (0x02UL << FSMC_PATT4_ATTHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08032" name="l08032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d9610198e4710ca394e3aeb32aa229f"> 8032</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_2 (0x04UL << FSMC_PATT4_ATTHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08033" name="l08033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd14059e9f658f37b3a1f18786395717"> 8033</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_3 (0x08UL << FSMC_PATT4_ATTHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08034" name="l08034"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a39fa40e2d4990097e31b47ad85283a"> 8034</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_4 (0x10UL << FSMC_PATT4_ATTHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08035" name="l08035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga239e412f20305d58416f10a79e253a87"> 8035</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_5 (0x20UL << FSMC_PATT4_ATTHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08036" name="l08036"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff1aac62acdf71077ee4a9e8e9e6d2d6"> 8036</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_6 (0x40UL << FSMC_PATT4_ATTHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08037" name="l08037"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga836fd2ad42b0c9f6d0eb651589d04123"> 8037</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_7 (0x80UL << FSMC_PATT4_ATTHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08039" name="l08039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7e76eb10b9d92b8d3d88d4d026679fb"> 8039</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_Pos (24U) </span></div>
|
||
<div class="line"><a id="l08040" name="l08040"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac10548dc39d989f970e3397287096126"> 8040</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_Msk (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08041" name="l08041"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35948e4e9e5ce9d674e9e70ca2aeafe3"> 8041</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_Msk </span></div>
|
||
<div class="line"><a id="l08042" name="l08042"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b746d7b655f6379af4dd4d5ba842492"> 8042</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_0 (0x01UL << FSMC_PATT4_ATTHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08043" name="l08043"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2dd87929111fc0c888dd7c311f8eba3"> 8043</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_1 (0x02UL << FSMC_PATT4_ATTHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08044" name="l08044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga353c0709e22a06998f05b908a597f525"> 8044</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_2 (0x04UL << FSMC_PATT4_ATTHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08045" name="l08045"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa777a5d42ac1e36044d7b18ffdd61a21"> 8045</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_3 (0x08UL << FSMC_PATT4_ATTHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08046" name="l08046"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65c1778d08bfe2a40961f6acf023b9d4"> 8046</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_4 (0x10UL << FSMC_PATT4_ATTHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08047" name="l08047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadb7001986c9a4c28052b46657ad7a7e"> 8047</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_5 (0x20UL << FSMC_PATT4_ATTHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08048" name="l08048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa11a8d896354bd1c6645ac096db8e065"> 8048</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_6 (0x40UL << FSMC_PATT4_ATTHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08049" name="l08049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a054f48705ec3fef0686c576f414f29"> 8049</a></span><span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_7 (0x80UL << FSMC_PATT4_ATTHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08051" name="l08051"></a><span class="lineno"> 8051</span><span class="comment">/****************** Bit definition for FSMC_PIO4 register *******************/</span></div>
|
||
<div class="line"><a id="l08052" name="l08052"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9972446feb353b113f1c31cf6be894e5"> 8052</a></span><span class="preprocessor">#define FSMC_PIO4_IOSET4_Pos (0U) </span></div>
|
||
<div class="line"><a id="l08053" name="l08053"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3358c18b8b82cd13305ec60101187b5c"> 8053</a></span><span class="preprocessor">#define FSMC_PIO4_IOSET4_Msk (0xFFUL << FSMC_PIO4_IOSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08054" name="l08054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf14b77f09f496a1325b5384eef54dd4a"> 8054</a></span><span class="preprocessor">#define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk </span></div>
|
||
<div class="line"><a id="l08055" name="l08055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29c07a816f3065ae0c9287b6e3e0e967"> 8055</a></span><span class="preprocessor">#define FSMC_PIO4_IOSET4_0 (0x01UL << FSMC_PIO4_IOSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08056" name="l08056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac31898a52e172935f354819c50d3ef8d"> 8056</a></span><span class="preprocessor">#define FSMC_PIO4_IOSET4_1 (0x02UL << FSMC_PIO4_IOSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08057" name="l08057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf35797347825725faef495c676269927"> 8057</a></span><span class="preprocessor">#define FSMC_PIO4_IOSET4_2 (0x04UL << FSMC_PIO4_IOSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08058" name="l08058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae45109e3dcc3c3a15efd13eddffdd8c9"> 8058</a></span><span class="preprocessor">#define FSMC_PIO4_IOSET4_3 (0x08UL << FSMC_PIO4_IOSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08059" name="l08059"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga349e3a58f832fbc9de16955521355c29"> 8059</a></span><span class="preprocessor">#define FSMC_PIO4_IOSET4_4 (0x10UL << FSMC_PIO4_IOSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08060" name="l08060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3304545838a6e20742b0203e0cb023a"> 8060</a></span><span class="preprocessor">#define FSMC_PIO4_IOSET4_5 (0x20UL << FSMC_PIO4_IOSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08061" name="l08061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga800ab779078734ca86eedb6c9e77bc57"> 8061</a></span><span class="preprocessor">#define FSMC_PIO4_IOSET4_6 (0x40UL << FSMC_PIO4_IOSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08062" name="l08062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e29b066726c486c6503d417d18904b1"> 8062</a></span><span class="preprocessor">#define FSMC_PIO4_IOSET4_7 (0x80UL << FSMC_PIO4_IOSET4_Pos) </span></div>
|
||
<div class="line"><a id="l08064" name="l08064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7003102b5d51a06d74a8176ca1299099"> 8064</a></span><span class="preprocessor">#define FSMC_PIO4_IOWAIT4_Pos (8U) </span></div>
|
||
<div class="line"><a id="l08065" name="l08065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4594c1e3df3d2345bf1207cab2de430"> 8065</a></span><span class="preprocessor">#define FSMC_PIO4_IOWAIT4_Msk (0xFFUL << FSMC_PIO4_IOWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08066" name="l08066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga035a0645caab3851714123302dd0af1c"> 8066</a></span><span class="preprocessor">#define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk </span></div>
|
||
<div class="line"><a id="l08067" name="l08067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb868a5bf3d33997c782f296440cabf7"> 8067</a></span><span class="preprocessor">#define FSMC_PIO4_IOWAIT4_0 (0x01UL << FSMC_PIO4_IOWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08068" name="l08068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa48c96fedf31c6ab444828d60e471da"> 8068</a></span><span class="preprocessor">#define FSMC_PIO4_IOWAIT4_1 (0x02UL << FSMC_PIO4_IOWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08069" name="l08069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga342e42235a123ea11544b1a230b07a75"> 8069</a></span><span class="preprocessor">#define FSMC_PIO4_IOWAIT4_2 (0x04UL << FSMC_PIO4_IOWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08070" name="l08070"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c012d7c41f51516580766d6ac36d82f"> 8070</a></span><span class="preprocessor">#define FSMC_PIO4_IOWAIT4_3 (0x08UL << FSMC_PIO4_IOWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08071" name="l08071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5331b528505a31a2b39deca7a5ddba02"> 8071</a></span><span class="preprocessor">#define FSMC_PIO4_IOWAIT4_4 (0x10UL << FSMC_PIO4_IOWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08072" name="l08072"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabbfbc377efde5170ac484795a0a4215"> 8072</a></span><span class="preprocessor">#define FSMC_PIO4_IOWAIT4_5 (0x20UL << FSMC_PIO4_IOWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08073" name="l08073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0be64ff24a6ccb7eef471ad2ad0e283b"> 8073</a></span><span class="preprocessor">#define FSMC_PIO4_IOWAIT4_6 (0x40UL << FSMC_PIO4_IOWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08074" name="l08074"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e3fc1b8cfa57116c0521cafd7e733cc"> 8074</a></span><span class="preprocessor">#define FSMC_PIO4_IOWAIT4_7 (0x80UL << FSMC_PIO4_IOWAIT4_Pos) </span></div>
|
||
<div class="line"><a id="l08076" name="l08076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga162d7f97cc7753670f748753357fafd2"> 8076</a></span><span class="preprocessor">#define FSMC_PIO4_IOHOLD4_Pos (16U) </span></div>
|
||
<div class="line"><a id="l08077" name="l08077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cfbf79cf550a6d25af660a9b78ae382"> 8077</a></span><span class="preprocessor">#define FSMC_PIO4_IOHOLD4_Msk (0xFFUL << FSMC_PIO4_IOHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08078" name="l08078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab55064df0d9fab8a072da6baa7b85878"> 8078</a></span><span class="preprocessor">#define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk </span></div>
|
||
<div class="line"><a id="l08079" name="l08079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc1a288b385fcf83bfa95da479d387a4"> 8079</a></span><span class="preprocessor">#define FSMC_PIO4_IOHOLD4_0 (0x01UL << FSMC_PIO4_IOHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08080" name="l08080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga402d7221ee27ce71d1b8bb18539d8307"> 8080</a></span><span class="preprocessor">#define FSMC_PIO4_IOHOLD4_1 (0x02UL << FSMC_PIO4_IOHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08081" name="l08081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga274c5b835ec95c97c4f1c6ebbf72a096"> 8081</a></span><span class="preprocessor">#define FSMC_PIO4_IOHOLD4_2 (0x04UL << FSMC_PIO4_IOHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08082" name="l08082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga519b9b4ae5b136769278eb98eb10c3a6"> 8082</a></span><span class="preprocessor">#define FSMC_PIO4_IOHOLD4_3 (0x08UL << FSMC_PIO4_IOHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08083" name="l08083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2d013be2823d9ea9b81f8f76331c11d"> 8083</a></span><span class="preprocessor">#define FSMC_PIO4_IOHOLD4_4 (0x10UL << FSMC_PIO4_IOHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08084" name="l08084"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a14c965f1ff993e0976aaefe638e2f6"> 8084</a></span><span class="preprocessor">#define FSMC_PIO4_IOHOLD4_5 (0x20UL << FSMC_PIO4_IOHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08085" name="l08085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49411f21445032ad8eaca19e89d204bc"> 8085</a></span><span class="preprocessor">#define FSMC_PIO4_IOHOLD4_6 (0x40UL << FSMC_PIO4_IOHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08086" name="l08086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga323dcc3be986d57d14b794cca0038953"> 8086</a></span><span class="preprocessor">#define FSMC_PIO4_IOHOLD4_7 (0x80UL << FSMC_PIO4_IOHOLD4_Pos) </span></div>
|
||
<div class="line"><a id="l08088" name="l08088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeaac653ebed9641460a4275d30047630"> 8088</a></span><span class="preprocessor">#define FSMC_PIO4_IOHIZ4_Pos (24U) </span></div>
|
||
<div class="line"><a id="l08089" name="l08089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b36d517941428d62268b10e8058abf4"> 8089</a></span><span class="preprocessor">#define FSMC_PIO4_IOHIZ4_Msk (0xFFUL << FSMC_PIO4_IOHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08090" name="l08090"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4cce93379430df64fd697ad772bc477d"> 8090</a></span><span class="preprocessor">#define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk </span></div>
|
||
<div class="line"><a id="l08091" name="l08091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf3b5c59e3eb4e259ddb722b1e536e5c"> 8091</a></span><span class="preprocessor">#define FSMC_PIO4_IOHIZ4_0 (0x01UL << FSMC_PIO4_IOHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08092" name="l08092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e8c66264d4ec7b69de613cb528cfee2"> 8092</a></span><span class="preprocessor">#define FSMC_PIO4_IOHIZ4_1 (0x02UL << FSMC_PIO4_IOHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08093" name="l08093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab943b8acd274a8892e691ffab36a6a21"> 8093</a></span><span class="preprocessor">#define FSMC_PIO4_IOHIZ4_2 (0x04UL << FSMC_PIO4_IOHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08094" name="l08094"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4184c40fd57a850605ac12c73553b6ba"> 8094</a></span><span class="preprocessor">#define FSMC_PIO4_IOHIZ4_3 (0x08UL << FSMC_PIO4_IOHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08095" name="l08095"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f966bdf26f7fa0f52076438219df7ee"> 8095</a></span><span class="preprocessor">#define FSMC_PIO4_IOHIZ4_4 (0x10UL << FSMC_PIO4_IOHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08096" name="l08096"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ba68883e73a331543a2990a76d1e91a"> 8096</a></span><span class="preprocessor">#define FSMC_PIO4_IOHIZ4_5 (0x20UL << FSMC_PIO4_IOHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08097" name="l08097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b2c084a1dfbf7fb7bd922faa48bad8a"> 8097</a></span><span class="preprocessor">#define FSMC_PIO4_IOHIZ4_6 (0x40UL << FSMC_PIO4_IOHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08098" name="l08098"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc8aef29e6eaecd3ff2c13bae143b8b4"> 8098</a></span><span class="preprocessor">#define FSMC_PIO4_IOHIZ4_7 (0x80UL << FSMC_PIO4_IOHIZ4_Pos) </span></div>
|
||
<div class="line"><a id="l08100" name="l08100"></a><span class="lineno"> 8100</span><span class="comment">/****************** Bit definition for FSMC_ECCR2 register ******************/</span></div>
|
||
<div class="line"><a id="l08101" name="l08101"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29ff399335d0f733c9c1476a5231bd92"> 8101</a></span><span class="preprocessor">#define FSMC_ECCR2_ECC2_Pos (0U) </span></div>
|
||
<div class="line"><a id="l08102" name="l08102"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga263cd31cea7c03124b24b94bec2ba751"> 8102</a></span><span class="preprocessor">#define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos) </span></div>
|
||
<div class="line"><a id="l08103" name="l08103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43da355ad2eb7d974488a02921b1b2ba"> 8103</a></span><span class="preprocessor">#define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk </span></div>
|
||
<div class="line"><a id="l08105" name="l08105"></a><span class="lineno"> 8105</span><span class="comment">/****************** Bit definition for FSMC_ECCR3 register ******************/</span></div>
|
||
<div class="line"><a id="l08106" name="l08106"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad671bdabc43e3a5cdebc69d006e7227f"> 8106</a></span><span class="preprocessor">#define FSMC_ECCR3_ECC3_Pos (0U) </span></div>
|
||
<div class="line"><a id="l08107" name="l08107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8f7ec32f0cb28be8c241bf487fdc8c3"> 8107</a></span><span class="preprocessor">#define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos) </span></div>
|
||
<div class="line"><a id="l08108" name="l08108"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga798b288a17d84edc99ff1f5f81cf70be"> 8108</a></span><span class="preprocessor">#define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk </span></div>
|
||
<div class="line"><a id="l08110" name="l08110"></a><span class="lineno"> 8110</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l08111" name="l08111"></a><span class="lineno"> 8111</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l08112" name="l08112"></a><span class="lineno"> 8112</span><span class="comment">/* General Purpose I/O */</span></div>
|
||
<div class="line"><a id="l08113" name="l08113"></a><span class="lineno"> 8113</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l08114" name="l08114"></a><span class="lineno"> 8114</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l08115" name="l08115"></a><span class="lineno"> 8115</span><span class="comment">/****************** Bits definition for GPIO_MODER register *****************/</span></div>
|
||
<div class="line"><a id="l08116" name="l08116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2244aa753f0340359098d15944602258"> 8116</a></span><span class="preprocessor">#define GPIO_MODER_MODER0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l08117" name="l08117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44c7a73f891cc60cb11c8dc122fde9bd"> 8117</a></span><span class="preprocessor">#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) </span></div>
|
||
<div class="line"><a id="l08118" name="l08118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b64d47643f8d3c08c2be0722ff23b93"> 8118</a></span><span class="preprocessor">#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk </span></div>
|
||
<div class="line"><a id="l08119" name="l08119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9547fc54057db093f9ee4b846fcc4723"> 8119</a></span><span class="preprocessor">#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) </span></div>
|
||
<div class="line"><a id="l08120" name="l08120"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e77a3bc750fe2ea8e06da301c65d6ef"> 8120</a></span><span class="preprocessor">#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) </span></div>
|
||
<div class="line"><a id="l08121" name="l08121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1030dee3583ca3e42adbdfe515ff542"> 8121</a></span><span class="preprocessor">#define GPIO_MODER_MODER1_Pos (2U) </span></div>
|
||
<div class="line"><a id="l08122" name="l08122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b96dc64bbedb58b5a6fdcc3c97eab1d"> 8122</a></span><span class="preprocessor">#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) </span></div>
|
||
<div class="line"><a id="l08123" name="l08123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e0597b084c911728ee92b5fc4a2ae5a"> 8123</a></span><span class="preprocessor">#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk </span></div>
|
||
<div class="line"><a id="l08124" name="l08124"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d85123ad7c77e052b542f2df47a1371"> 8124</a></span><span class="preprocessor">#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) </span></div>
|
||
<div class="line"><a id="l08125" name="l08125"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9f16759689b9ac61d9c68842ac49746"> 8125</a></span><span class="preprocessor">#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) </span></div>
|
||
<div class="line"><a id="l08126" name="l08126"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga945f52c8af561a1c9a3358b0e8605ffc"> 8126</a></span><span class="preprocessor">#define GPIO_MODER_MODER2_Pos (4U) </span></div>
|
||
<div class="line"><a id="l08127" name="l08127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6c01a65d00f6b648984e34f71ce0b83"> 8127</a></span><span class="preprocessor">#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) </span></div>
|
||
<div class="line"><a id="l08128" name="l08128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06865341707bb4dd9671ce464d99ab2c"> 8128</a></span><span class="preprocessor">#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk </span></div>
|
||
<div class="line"><a id="l08129" name="l08129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06e9f9713b7a822784cd2c0fa79dcff0"> 8129</a></span><span class="preprocessor">#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) </span></div>
|
||
<div class="line"><a id="l08130" name="l08130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97f7959265384b2621288c8340990665"> 8130</a></span><span class="preprocessor">#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) </span></div>
|
||
<div class="line"><a id="l08131" name="l08131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0df2c02569d6b84757d70cd5ab99d262"> 8131</a></span><span class="preprocessor">#define GPIO_MODER_MODER3_Pos (6U) </span></div>
|
||
<div class="line"><a id="l08132" name="l08132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga053851b8f1df3d358a7b07fe8f720a25"> 8132</a></span><span class="preprocessor">#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) </span></div>
|
||
<div class="line"><a id="l08133" name="l08133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae06c9d07a091fb64ab53d0c899a9dda5"> 8133</a></span><span class="preprocessor">#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk </span></div>
|
||
<div class="line"><a id="l08134" name="l08134"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4aeeac804c07e25aeff31bebf3a639f6"> 8134</a></span><span class="preprocessor">#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) </span></div>
|
||
<div class="line"><a id="l08135" name="l08135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc09e4958f306ddcb6107942504b45e0"> 8135</a></span><span class="preprocessor">#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) </span></div>
|
||
<div class="line"><a id="l08136" name="l08136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7866ff150289c04d52c808607dabbf9e"> 8136</a></span><span class="preprocessor">#define GPIO_MODER_MODER4_Pos (8U) </span></div>
|
||
<div class="line"><a id="l08137" name="l08137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0678135cc7fb1e00fe0de880d822fde5"> 8137</a></span><span class="preprocessor">#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) </span></div>
|
||
<div class="line"><a id="l08138" name="l08138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52cf9361d90c863c107cdeb859bd8b41"> 8138</a></span><span class="preprocessor">#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk </span></div>
|
||
<div class="line"><a id="l08139" name="l08139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67276f1aa615d1af388fef7232483795"> 8139</a></span><span class="preprocessor">#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) </span></div>
|
||
<div class="line"><a id="l08140" name="l08140"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5203150980865199911d58af22f49567"> 8140</a></span><span class="preprocessor">#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) </span></div>
|
||
<div class="line"><a id="l08141" name="l08141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84f88cbf25e1defb5f9b99c95797f7ab"> 8141</a></span><span class="preprocessor">#define GPIO_MODER_MODER5_Pos (10U) </span></div>
|
||
<div class="line"><a id="l08142" name="l08142"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f1827fce38f560f895e4486f1aacaac"> 8142</a></span><span class="preprocessor">#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) </span></div>
|
||
<div class="line"><a id="l08143" name="l08143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae94ab55c126ff24572bbff0da5a3f360"> 8143</a></span><span class="preprocessor">#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk </span></div>
|
||
<div class="line"><a id="l08144" name="l08144"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62665be9bddb711eedf99c85e37bb5ad"> 8144</a></span><span class="preprocessor">#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) </span></div>
|
||
<div class="line"><a id="l08145" name="l08145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5096355e22b25bd4e6324399d5764630"> 8145</a></span><span class="preprocessor">#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) </span></div>
|
||
<div class="line"><a id="l08146" name="l08146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81c3fdecd37cce14983b42d28fc46d27"> 8146</a></span><span class="preprocessor">#define GPIO_MODER_MODER6_Pos (12U) </span></div>
|
||
<div class="line"><a id="l08147" name="l08147"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83a6d2a5dbd3f6f8447e0082c0e8d6ab"> 8147</a></span><span class="preprocessor">#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) </span></div>
|
||
<div class="line"><a id="l08148" name="l08148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97a85a1bb88cf8f730e0de38cb664282"> 8148</a></span><span class="preprocessor">#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk </span></div>
|
||
<div class="line"><a id="l08149" name="l08149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf45f41af21a000ab66da5b99b998deb3"> 8149</a></span><span class="preprocessor">#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) </span></div>
|
||
<div class="line"><a id="l08150" name="l08150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41dfd1f39fe849fe3707ebf2ac0d8371"> 8150</a></span><span class="preprocessor">#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) </span></div>
|
||
<div class="line"><a id="l08151" name="l08151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf586709481b1450208dae7d9e53b9057"> 8151</a></span><span class="preprocessor">#define GPIO_MODER_MODER7_Pos (14U) </span></div>
|
||
<div class="line"><a id="l08152" name="l08152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae685da5b1c5c085e69be64ecf0b65ec5"> 8152</a></span><span class="preprocessor">#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) </span></div>
|
||
<div class="line"><a id="l08153" name="l08153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22dc08ecc39bceba020d8e5949b658e0"> 8153</a></span><span class="preprocessor">#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk </span></div>
|
||
<div class="line"><a id="l08154" name="l08154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga585ab6cb29e3763ab8c1e997c55f2b43"> 8154</a></span><span class="preprocessor">#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) </span></div>
|
||
<div class="line"><a id="l08155" name="l08155"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b5cca014fc55f64cdbbb42ea0515e05"> 8155</a></span><span class="preprocessor">#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) </span></div>
|
||
<div class="line"><a id="l08156" name="l08156"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80e5f1f7c986ee7f31178901cab442ab"> 8156</a></span><span class="preprocessor">#define GPIO_MODER_MODER8_Pos (16U) </span></div>
|
||
<div class="line"><a id="l08157" name="l08157"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaddfeb2d4f139bd00fdcd2ce538f2087"> 8157</a></span><span class="preprocessor">#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) </span></div>
|
||
<div class="line"><a id="l08158" name="l08158"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac41f2174ef4444c685ea92da1258c678"> 8158</a></span><span class="preprocessor">#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk </span></div>
|
||
<div class="line"><a id="l08159" name="l08159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cdb8e55aa223af568ae12d316a22f8d"> 8159</a></span><span class="preprocessor">#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) </span></div>
|
||
<div class="line"><a id="l08160" name="l08160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0729411ccd74a91cdd0f23adada25782"> 8160</a></span><span class="preprocessor">#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) </span></div>
|
||
<div class="line"><a id="l08161" name="l08161"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf310164aef074cbdda2af5b0af223139"> 8161</a></span><span class="preprocessor">#define GPIO_MODER_MODER9_Pos (18U) </span></div>
|
||
<div class="line"><a id="l08162" name="l08162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdcb7c58d623c51ababeb5917430132b"> 8162</a></span><span class="preprocessor">#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) </span></div>
|
||
<div class="line"><a id="l08163" name="l08163"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d4ed9018bf72565bab1d08c476fed20"> 8163</a></span><span class="preprocessor">#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk </span></div>
|
||
<div class="line"><a id="l08164" name="l08164"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea7c7ec787b1ee1ae7e0b4da216eb418"> 8164</a></span><span class="preprocessor">#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) </span></div>
|
||
<div class="line"><a id="l08165" name="l08165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5cd33689071b7af70ece64a371645df"> 8165</a></span><span class="preprocessor">#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) </span></div>
|
||
<div class="line"><a id="l08166" name="l08166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf36ddfa8971a143e722ca9897d6a554"> 8166</a></span><span class="preprocessor">#define GPIO_MODER_MODER10_Pos (20U) </span></div>
|
||
<div class="line"><a id="l08167" name="l08167"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9af602f158627d6d61a2fcf7149a6178"> 8167</a></span><span class="preprocessor">#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) </span></div>
|
||
<div class="line"><a id="l08168" name="l08168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacbdb241d7bebde85d7d0b42c2f35563"> 8168</a></span><span class="preprocessor">#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk </span></div>
|
||
<div class="line"><a id="l08169" name="l08169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f4d2b18e57e7b2f600e4f5d9b17bd95"> 8169</a></span><span class="preprocessor">#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) </span></div>
|
||
<div class="line"><a id="l08170" name="l08170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9dcae08e0f7afc002658a4ef4a764dc4"> 8170</a></span><span class="preprocessor">#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) </span></div>
|
||
<div class="line"><a id="l08171" name="l08171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac60a554e688d63d15bce7240549d2ccb"> 8171</a></span><span class="preprocessor">#define GPIO_MODER_MODER11_Pos (22U) </span></div>
|
||
<div class="line"><a id="l08172" name="l08172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82a8fa719e9f98d2a7b4fd00ad41927d"> 8172</a></span><span class="preprocessor">#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) </span></div>
|
||
<div class="line"><a id="l08173" name="l08173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf18bc295f7195fc050221287c4564474"> 8173</a></span><span class="preprocessor">#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk </span></div>
|
||
<div class="line"><a id="l08174" name="l08174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4082cd576f50cd2687e45557b70d458"> 8174</a></span><span class="preprocessor">#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) </span></div>
|
||
<div class="line"><a id="l08175" name="l08175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b2f611ae75f3441bad03866550f6263"> 8175</a></span><span class="preprocessor">#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) </span></div>
|
||
<div class="line"><a id="l08176" name="l08176"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec7b868a25af299e046b49b017c1114f"> 8176</a></span><span class="preprocessor">#define GPIO_MODER_MODER12_Pos (24U) </span></div>
|
||
<div class="line"><a id="l08177" name="l08177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd6d6390219a23c8420cc152901ca9bd"> 8177</a></span><span class="preprocessor">#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) </span></div>
|
||
<div class="line"><a id="l08178" name="l08178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63101c5c410b55b668ec190422dc3597"> 8178</a></span><span class="preprocessor">#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk </span></div>
|
||
<div class="line"><a id="l08179" name="l08179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa89cd8ed328ed0116cbf51810fcd8788"> 8179</a></span><span class="preprocessor">#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) </span></div>
|
||
<div class="line"><a id="l08180" name="l08180"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74f91bdd676e477e4c19d30d3ea5c4c8"> 8180</a></span><span class="preprocessor">#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) </span></div>
|
||
<div class="line"><a id="l08181" name="l08181"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e91d26a428aa90b419bf51324491246"> 8181</a></span><span class="preprocessor">#define GPIO_MODER_MODER13_Pos (26U) </span></div>
|
||
<div class="line"><a id="l08182" name="l08182"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ae7344fb7e360c013ae484a7b3ce06e"> 8182</a></span><span class="preprocessor">#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) </span></div>
|
||
<div class="line"><a id="l08183" name="l08183"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga353af246bef5dca5aadfe6fe3fd695c3"> 8183</a></span><span class="preprocessor">#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk </span></div>
|
||
<div class="line"><a id="l08184" name="l08184"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc01e2e6cf45e8ec27d3a66ff36c2cfa"> 8184</a></span><span class="preprocessor">#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) </span></div>
|
||
<div class="line"><a id="l08185" name="l08185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71a30088f5475ae8774404ae7d41872e"> 8185</a></span><span class="preprocessor">#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) </span></div>
|
||
<div class="line"><a id="l08186" name="l08186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac67c9470dc741033d3254a4041e3d320"> 8186</a></span><span class="preprocessor">#define GPIO_MODER_MODER14_Pos (28U) </span></div>
|
||
<div class="line"><a id="l08187" name="l08187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fd4d1526a36e0838bc8c9bab621aba0"> 8187</a></span><span class="preprocessor">#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) </span></div>
|
||
<div class="line"><a id="l08188" name="l08188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18a722f9682045c1d2460fedf32b02b1"> 8188</a></span><span class="preprocessor">#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk </span></div>
|
||
<div class="line"><a id="l08189" name="l08189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad295063c22bd981239bc1b26f2e7f9c0"> 8189</a></span><span class="preprocessor">#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) </span></div>
|
||
<div class="line"><a id="l08190" name="l08190"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ff3a914796db9625d86996b6f6f5288"> 8190</a></span><span class="preprocessor">#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) </span></div>
|
||
<div class="line"><a id="l08191" name="l08191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8c4f0c2ee0dbf7761c9acf9f4d9fa8b"> 8191</a></span><span class="preprocessor">#define GPIO_MODER_MODER15_Pos (30U) </span></div>
|
||
<div class="line"><a id="l08192" name="l08192"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97ba0885b9dda0bec8202305bf9cf0ad"> 8192</a></span><span class="preprocessor">#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) </span></div>
|
||
<div class="line"><a id="l08193" name="l08193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefc40e6fae78c1c5c857346793f9d4c8"> 8193</a></span><span class="preprocessor">#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk </span></div>
|
||
<div class="line"><a id="l08194" name="l08194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c4b7f270eb99d851b84b9917fe49564"> 8194</a></span><span class="preprocessor">#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) </span></div>
|
||
<div class="line"><a id="l08195" name="l08195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9297c041f5f74aec73e6f4dd89ad819c"> 8195</a></span><span class="preprocessor">#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) </span></div>
|
||
<div class="line"><a id="l08197" name="l08197"></a><span class="lineno"> 8197</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l08198" name="l08198"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f3903d8ae31585af4d8e0a4a980a53f"> 8198</a></span><span class="preprocessor">#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos </span></div>
|
||
<div class="line"><a id="l08199" name="l08199"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9cff105dfdd73e5a1705a3a52bfe4953"> 8199</a></span><span class="preprocessor">#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk</span></div>
|
||
<div class="line"><a id="l08200" name="l08200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabad45500839e6f801c64ee9474e4da33"> 8200</a></span><span class="preprocessor">#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 </span></div>
|
||
<div class="line"><a id="l08201" name="l08201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac21859652224406f970f4c99d5198d16"> 8201</a></span><span class="preprocessor">#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0</span></div>
|
||
<div class="line"><a id="l08202" name="l08202"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7a47a04b8e25a1de3250bd4921eeddc"> 8202</a></span><span class="preprocessor">#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1</span></div>
|
||
<div class="line"><a id="l08203" name="l08203"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcd114563c35dd9bc117884af80acda8"> 8203</a></span><span class="preprocessor">#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos </span></div>
|
||
<div class="line"><a id="l08204" name="l08204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30d7601c96266dc29ab8d67804154b3f"> 8204</a></span><span class="preprocessor">#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk</span></div>
|
||
<div class="line"><a id="l08205" name="l08205"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76d7c80c5afbf9bf5aada55d91d59ecb"> 8205</a></span><span class="preprocessor">#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 </span></div>
|
||
<div class="line"><a id="l08206" name="l08206"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdd2690fbea56b2d7dd8af222370cc95"> 8206</a></span><span class="preprocessor">#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0</span></div>
|
||
<div class="line"><a id="l08207" name="l08207"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a240f6f0b335fe9595019531b4607b9"> 8207</a></span><span class="preprocessor">#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1</span></div>
|
||
<div class="line"><a id="l08208" name="l08208"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6405d97990f322ac711f5d50d69c41f"> 8208</a></span><span class="preprocessor">#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos</span></div>
|
||
<div class="line"><a id="l08209" name="l08209"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a188e7809bffb5a963302debcc602bf"> 8209</a></span><span class="preprocessor">#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk</span></div>
|
||
<div class="line"><a id="l08210" name="l08210"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90970df916fe323664322ecbe516993d"> 8210</a></span><span class="preprocessor">#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 </span></div>
|
||
<div class="line"><a id="l08211" name="l08211"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66a90c798fa54047f30b83f3eec1821b"> 8211</a></span><span class="preprocessor">#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0</span></div>
|
||
<div class="line"><a id="l08212" name="l08212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae88847b33d3c78142f99e5d1753451e"> 8212</a></span><span class="preprocessor">#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1</span></div>
|
||
<div class="line"><a id="l08213" name="l08213"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3d6572d265c72f92e2005c141202422"> 8213</a></span><span class="preprocessor">#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos </span></div>
|
||
<div class="line"><a id="l08214" name="l08214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4eaea23a16c4fb39e27d295ce0e5b94"> 8214</a></span><span class="preprocessor">#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk</span></div>
|
||
<div class="line"><a id="l08215" name="l08215"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9062e2f2d10271c05e5f963be522db96"> 8215</a></span><span class="preprocessor">#define GPIO_MODER_MODE3 GPIO_MODER_MODER3</span></div>
|
||
<div class="line"><a id="l08216" name="l08216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga908f28256ab03cf88ed6e2fce3a2a70d"> 8216</a></span><span class="preprocessor">#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0</span></div>
|
||
<div class="line"><a id="l08217" name="l08217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99db34fd563915c2fc4eb16ef2505c98"> 8217</a></span><span class="preprocessor">#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1</span></div>
|
||
<div class="line"><a id="l08218" name="l08218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab14bbd003834724332b11c3a33eba1a6"> 8218</a></span><span class="preprocessor">#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos</span></div>
|
||
<div class="line"><a id="l08219" name="l08219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9b416b464e6bcd73aa11bf0ef734b47"> 8219</a></span><span class="preprocessor">#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk</span></div>
|
||
<div class="line"><a id="l08220" name="l08220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae11faa17747d422f5d88ced879e09bb6"> 8220</a></span><span class="preprocessor">#define GPIO_MODER_MODE4 GPIO_MODER_MODER4</span></div>
|
||
<div class="line"><a id="l08221" name="l08221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2336f60fe03642339cbfd4e994812875"> 8221</a></span><span class="preprocessor">#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0</span></div>
|
||
<div class="line"><a id="l08222" name="l08222"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae946375c36dfb3b3669864ee62002e62"> 8222</a></span><span class="preprocessor">#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1</span></div>
|
||
<div class="line"><a id="l08223" name="l08223"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3db08d5515fb6203ea8c2cf83d5ccd9"> 8223</a></span><span class="preprocessor">#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos</span></div>
|
||
<div class="line"><a id="l08224" name="l08224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ecdacbc580acb1d0045366bab0605a3"> 8224</a></span><span class="preprocessor">#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk</span></div>
|
||
<div class="line"><a id="l08225" name="l08225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b40ba8ed0964516f512bb55a7783425"> 8225</a></span><span class="preprocessor">#define GPIO_MODER_MODE5 GPIO_MODER_MODER5</span></div>
|
||
<div class="line"><a id="l08226" name="l08226"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9fbe729f8b1780ef0a6a24ce46a5dc9"> 8226</a></span><span class="preprocessor">#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0</span></div>
|
||
<div class="line"><a id="l08227" name="l08227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85fd33570c7059e94708cb99a1d88e55"> 8227</a></span><span class="preprocessor">#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1</span></div>
|
||
<div class="line"><a id="l08228" name="l08228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1605f3cdb581e59663fd9fb0bab17d74"> 8228</a></span><span class="preprocessor">#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos</span></div>
|
||
<div class="line"><a id="l08229" name="l08229"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga923f7562b497aa9e864872e6314aec8b"> 8229</a></span><span class="preprocessor">#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk</span></div>
|
||
<div class="line"><a id="l08230" name="l08230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad09b263a1b49cc5db86e5e6fe5d0d59c"> 8230</a></span><span class="preprocessor">#define GPIO_MODER_MODE6 GPIO_MODER_MODER6</span></div>
|
||
<div class="line"><a id="l08231" name="l08231"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9fe86e9e52f1ba692d5ea66c2e43678"> 8231</a></span><span class="preprocessor">#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0</span></div>
|
||
<div class="line"><a id="l08232" name="l08232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ef7f24d9e982418baef863fbe1ffe5f"> 8232</a></span><span class="preprocessor">#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1</span></div>
|
||
<div class="line"><a id="l08233" name="l08233"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd7bb459725ad9a92adb58341f64c5db"> 8233</a></span><span class="preprocessor">#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos</span></div>
|
||
<div class="line"><a id="l08234" name="l08234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga395417bce21078a26c0930132c9853ee"> 8234</a></span><span class="preprocessor">#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk</span></div>
|
||
<div class="line"><a id="l08235" name="l08235"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafff70c209574ca7023aa0a853a341e2b"> 8235</a></span><span class="preprocessor">#define GPIO_MODER_MODE7 GPIO_MODER_MODER7</span></div>
|
||
<div class="line"><a id="l08236" name="l08236"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac77ebcfb844a2b8893641ee9de058178"> 8236</a></span><span class="preprocessor">#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0</span></div>
|
||
<div class="line"><a id="l08237" name="l08237"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f64e364157865520082d72aa98ab0ee"> 8237</a></span><span class="preprocessor">#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1</span></div>
|
||
<div class="line"><a id="l08238" name="l08238"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga962ec8cd96b449ed7cc142b491db4e0c"> 8238</a></span><span class="preprocessor">#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos</span></div>
|
||
<div class="line"><a id="l08239" name="l08239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe7b281c031a88069e827a6ac710e0c5"> 8239</a></span><span class="preprocessor">#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk</span></div>
|
||
<div class="line"><a id="l08240" name="l08240"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d7027e90da284883872b827f78fbc26"> 8240</a></span><span class="preprocessor">#define GPIO_MODER_MODE8 GPIO_MODER_MODER8</span></div>
|
||
<div class="line"><a id="l08241" name="l08241"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac1715680209944bc7593cedf31f491b"> 8241</a></span><span class="preprocessor">#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0</span></div>
|
||
<div class="line"><a id="l08242" name="l08242"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3197ca6a90d936e5a564d377bd4126fd"> 8242</a></span><span class="preprocessor">#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1</span></div>
|
||
<div class="line"><a id="l08243" name="l08243"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1093b1b58d8a8b51f204fc78239cbbb0"> 8243</a></span><span class="preprocessor">#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos</span></div>
|
||
<div class="line"><a id="l08244" name="l08244"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0acba3f02fb730df350c2d938792fd74"> 8244</a></span><span class="preprocessor">#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk</span></div>
|
||
<div class="line"><a id="l08245" name="l08245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf81e4a6121d0fe0ee5bc3fbe0f245572"> 8245</a></span><span class="preprocessor">#define GPIO_MODER_MODE9 GPIO_MODER_MODER9</span></div>
|
||
<div class="line"><a id="l08246" name="l08246"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga659899030e816750c2e4ecbf4250cc91"> 8246</a></span><span class="preprocessor">#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0</span></div>
|
||
<div class="line"><a id="l08247" name="l08247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15a408c473d172282468a1fccad482bb"> 8247</a></span><span class="preprocessor">#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1</span></div>
|
||
<div class="line"><a id="l08248" name="l08248"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga034f78f504f81a1ed9a3d457792f4197"> 8248</a></span><span class="preprocessor">#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos</span></div>
|
||
<div class="line"><a id="l08249" name="l08249"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc0dafc52e2eb8562733153c8658e8f4"> 8249</a></span><span class="preprocessor">#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk</span></div>
|
||
<div class="line"><a id="l08250" name="l08250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10461308203bd8e510c3205e6a499c20"> 8250</a></span><span class="preprocessor">#define GPIO_MODER_MODE10 GPIO_MODER_MODER10</span></div>
|
||
<div class="line"><a id="l08251" name="l08251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7aa2a41e913180598b59b20ffafc4a47"> 8251</a></span><span class="preprocessor">#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0</span></div>
|
||
<div class="line"><a id="l08252" name="l08252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad59d8ec1da352c55b9cb65b751f193e1"> 8252</a></span><span class="preprocessor">#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1</span></div>
|
||
<div class="line"><a id="l08253" name="l08253"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3c361d8935e5c043775a1dbf77b4530"> 8253</a></span><span class="preprocessor">#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos</span></div>
|
||
<div class="line"><a id="l08254" name="l08254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga313382ddc024a2cde3a1a3bb6ff1fc4d"> 8254</a></span><span class="preprocessor">#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk</span></div>
|
||
<div class="line"><a id="l08255" name="l08255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4d968b108aa28b20cd40a7746004d2c"> 8255</a></span><span class="preprocessor">#define GPIO_MODER_MODE11 GPIO_MODER_MODER11</span></div>
|
||
<div class="line"><a id="l08256" name="l08256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadeb4ecb54a0dc7f304007367e112725d"> 8256</a></span><span class="preprocessor">#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0</span></div>
|
||
<div class="line"><a id="l08257" name="l08257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a7b954225f0a664d602cba0ed1e03d4"> 8257</a></span><span class="preprocessor">#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1</span></div>
|
||
<div class="line"><a id="l08258" name="l08258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8967fa759f57e187e4b87b9723a12e05"> 8258</a></span><span class="preprocessor">#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos</span></div>
|
||
<div class="line"><a id="l08259" name="l08259"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bab0d5ff031fcff49dedb0c36073008"> 8259</a></span><span class="preprocessor">#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk</span></div>
|
||
<div class="line"><a id="l08260" name="l08260"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac09cecc889ead7bc7a079d4889da0578"> 8260</a></span><span class="preprocessor">#define GPIO_MODER_MODE12 GPIO_MODER_MODER12</span></div>
|
||
<div class="line"><a id="l08261" name="l08261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dc7e3ea6e86a627d7697dafbb7feab6"> 8261</a></span><span class="preprocessor">#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0</span></div>
|
||
<div class="line"><a id="l08262" name="l08262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a2313be3f7d3fb0f2203456beaa4efe"> 8262</a></span><span class="preprocessor">#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1</span></div>
|
||
<div class="line"><a id="l08263" name="l08263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4895814d5aa1829b1abfbd2d4df8b66"> 8263</a></span><span class="preprocessor">#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos</span></div>
|
||
<div class="line"><a id="l08264" name="l08264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02c48c21d983bab6115b056239d84217"> 8264</a></span><span class="preprocessor">#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk</span></div>
|
||
<div class="line"><a id="l08265" name="l08265"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf38e8e70d58b97d462d45e6e116115be"> 8265</a></span><span class="preprocessor">#define GPIO_MODER_MODE13 GPIO_MODER_MODER13</span></div>
|
||
<div class="line"><a id="l08266" name="l08266"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga575519f151a9dda7c8e24d7c9e625b0f"> 8266</a></span><span class="preprocessor">#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0</span></div>
|
||
<div class="line"><a id="l08267" name="l08267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad93a355f773bc67b68b0a665c5a15136"> 8267</a></span><span class="preprocessor">#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1</span></div>
|
||
<div class="line"><a id="l08268" name="l08268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab23c1a3d555305265fe00c4a2f25d705"> 8268</a></span><span class="preprocessor">#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos</span></div>
|
||
<div class="line"><a id="l08269" name="l08269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ee9ecd8c12612d429efa6b2694b8a25"> 8269</a></span><span class="preprocessor">#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk</span></div>
|
||
<div class="line"><a id="l08270" name="l08270"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e67512a90147ccad6991e5b16821811"> 8270</a></span><span class="preprocessor">#define GPIO_MODER_MODE14 GPIO_MODER_MODER14</span></div>
|
||
<div class="line"><a id="l08271" name="l08271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa664199b48953065ec3b16e7de90d9b"> 8271</a></span><span class="preprocessor">#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0</span></div>
|
||
<div class="line"><a id="l08272" name="l08272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e8638837bc4e6d69cd7635296a51730"> 8272</a></span><span class="preprocessor">#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1</span></div>
|
||
<div class="line"><a id="l08273" name="l08273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga040b83bff88d237d447bfe658913f2e7"> 8273</a></span><span class="preprocessor">#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos</span></div>
|
||
<div class="line"><a id="l08274" name="l08274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbdbb728d5db2fb68bbedd6e4374827b"> 8274</a></span><span class="preprocessor">#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk</span></div>
|
||
<div class="line"><a id="l08275" name="l08275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8027405e42e74b5065861c067e0b9f77"> 8275</a></span><span class="preprocessor">#define GPIO_MODER_MODE15 GPIO_MODER_MODER15</span></div>
|
||
<div class="line"><a id="l08276" name="l08276"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace9ec013afbf2e01286ca61726e92332"> 8276</a></span><span class="preprocessor">#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0</span></div>
|
||
<div class="line"><a id="l08277" name="l08277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7055ea8ec31fe604f1b5f04e2b194c4"> 8277</a></span><span class="preprocessor">#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1</span></div>
|
||
<div class="line"><a id="l08278" name="l08278"></a><span class="lineno"> 8278</span> </div>
|
||
<div class="line"><a id="l08279" name="l08279"></a><span class="lineno"> 8279</span><span class="comment">/****************** Bits definition for GPIO_OTYPER register ****************/</span></div>
|
||
<div class="line"><a id="l08280" name="l08280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d59a7c3218b146d61516cabb81588d1"> 8280</a></span><span class="preprocessor">#define GPIO_OTYPER_OT0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l08281" name="l08281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1dbf22f662367e7f4033c6ef85f69162"> 8281</a></span><span class="preprocessor">#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) </span></div>
|
||
<div class="line"><a id="l08282" name="l08282"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2aebd85688999595239036bd63eac4a3"> 8282</a></span><span class="preprocessor">#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk </span></div>
|
||
<div class="line"><a id="l08283" name="l08283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga592defc7541ea5c2463d0a5c9566a337"> 8283</a></span><span class="preprocessor">#define GPIO_OTYPER_OT1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l08284" name="l08284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d6d2752a99a69a1ed6fde751477f65e"> 8284</a></span><span class="preprocessor">#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) </span></div>
|
||
<div class="line"><a id="l08285" name="l08285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c2e6db60417e319c9a8de701ab4d93d"> 8285</a></span><span class="preprocessor">#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk </span></div>
|
||
<div class="line"><a id="l08286" name="l08286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3a3f4f3a5a9a13e74861ada55fe8373"> 8286</a></span><span class="preprocessor">#define GPIO_OTYPER_OT2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l08287" name="l08287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90c1021a385b3e3ad84b5c3f55dcd2bd"> 8287</a></span><span class="preprocessor">#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) </span></div>
|
||
<div class="line"><a id="l08288" name="l08288"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5478c1782217eec4b8d09fcc930a55c1"> 8288</a></span><span class="preprocessor">#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk </span></div>
|
||
<div class="line"><a id="l08289" name="l08289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad678ac2b9b55a718f1e81237ee4a5b30"> 8289</a></span><span class="preprocessor">#define GPIO_OTYPER_OT3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l08290" name="l08290"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac467eaf271fc0abc674a0f1657b754b9"> 8290</a></span><span class="preprocessor">#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) </span></div>
|
||
<div class="line"><a id="l08291" name="l08291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52cbd557435c2173e390b534cc6a893b"> 8291</a></span><span class="preprocessor">#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk </span></div>
|
||
<div class="line"><a id="l08292" name="l08292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9104ccbb9f57282217df7a4af2fa149"> 8292</a></span><span class="preprocessor">#define GPIO_OTYPER_OT4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l08293" name="l08293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab826bfea8ea3e5500900e31d24603a3f"> 8293</a></span><span class="preprocessor">#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) </span></div>
|
||
<div class="line"><a id="l08294" name="l08294"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedd72ae7a6ef61cb01d7b31e7ac3f02f"> 8294</a></span><span class="preprocessor">#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk </span></div>
|
||
<div class="line"><a id="l08295" name="l08295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffcd8be7000a751ac97b432e6f8febcd"> 8295</a></span><span class="preprocessor">#define GPIO_OTYPER_OT5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l08296" name="l08296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa41f6d81f21b5d4c984d318c3d5ea5fc"> 8296</a></span><span class="preprocessor">#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) </span></div>
|
||
<div class="line"><a id="l08297" name="l08297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabfa602db904a1c4ac0bfe2f57e044f03"> 8297</a></span><span class="preprocessor">#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk </span></div>
|
||
<div class="line"><a id="l08298" name="l08298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5673f4acd1ca97723538455ce2ad8fa5"> 8298</a></span><span class="preprocessor">#define GPIO_OTYPER_OT6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l08299" name="l08299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf04845f8e00f58279129c9d7cbc40340"> 8299</a></span><span class="preprocessor">#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) </span></div>
|
||
<div class="line"><a id="l08300" name="l08300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga872f2008be45e90a2663c31f5e3858ee"> 8300</a></span><span class="preprocessor">#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk </span></div>
|
||
<div class="line"><a id="l08301" name="l08301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5567f31bc7165b0a55e42a392306faf5"> 8301</a></span><span class="preprocessor">#define GPIO_OTYPER_OT7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l08302" name="l08302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c4371991d169bbce9043ef03eebc3e7"> 8302</a></span><span class="preprocessor">#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) </span></div>
|
||
<div class="line"><a id="l08303" name="l08303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac22a8999bf349459af4bd58fe319d03"> 8303</a></span><span class="preprocessor">#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk </span></div>
|
||
<div class="line"><a id="l08304" name="l08304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2df4811f95aae5d25c63d1e6645914e4"> 8304</a></span><span class="preprocessor">#define GPIO_OTYPER_OT8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l08305" name="l08305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88986ea0ef6829d98ea063355ed574bd"> 8305</a></span><span class="preprocessor">#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) </span></div>
|
||
<div class="line"><a id="l08306" name="l08306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b89d7c4cc8986895b4e4cbc8455f912"> 8306</a></span><span class="preprocessor">#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk </span></div>
|
||
<div class="line"><a id="l08307" name="l08307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a517c02253d8081d006ba12b939ddb7"> 8307</a></span><span class="preprocessor">#define GPIO_OTYPER_OT9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l08308" name="l08308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23374263ed146dfa55de5e09a9984520"> 8308</a></span><span class="preprocessor">#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) </span></div>
|
||
<div class="line"><a id="l08309" name="l08309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae53d4f666ee3410123ab941ee29fc886"> 8309</a></span><span class="preprocessor">#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk </span></div>
|
||
<div class="line"><a id="l08310" name="l08310"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ae2d866e0737d3b40919d877a321dbe"> 8310</a></span><span class="preprocessor">#define GPIO_OTYPER_OT10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l08311" name="l08311"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga108993b457894e46ee48421cf847d6b6"> 8311</a></span><span class="preprocessor">#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) </span></div>
|
||
<div class="line"><a id="l08312" name="l08312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6bc9516ce236e7d3429066b16a7dfa9a"> 8312</a></span><span class="preprocessor">#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk </span></div>
|
||
<div class="line"><a id="l08313" name="l08313"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72764b8f1eaca4407ddce7f3313d045d"> 8313</a></span><span class="preprocessor">#define GPIO_OTYPER_OT11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l08314" name="l08314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f833cf9e36cd48b282a838ee5d4d269"> 8314</a></span><span class="preprocessor">#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) </span></div>
|
||
<div class="line"><a id="l08315" name="l08315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d842d0b79b54cd990a819197a0ecc6f"> 8315</a></span><span class="preprocessor">#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk </span></div>
|
||
<div class="line"><a id="l08316" name="l08316"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9cbdcf0cf8146de12cb5ff36c6cbdc35"> 8316</a></span><span class="preprocessor">#define GPIO_OTYPER_OT12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l08317" name="l08317"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac138e0a10703e6da87ff724a9e8314e6"> 8317</a></span><span class="preprocessor">#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) </span></div>
|
||
<div class="line"><a id="l08318" name="l08318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ab821f1edc7c879a34e51d85be89927"> 8318</a></span><span class="preprocessor">#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk </span></div>
|
||
<div class="line"><a id="l08319" name="l08319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25fc93b49714517d14b95c51496f4dde"> 8319</a></span><span class="preprocessor">#define GPIO_OTYPER_OT13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l08320" name="l08320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc65a535136ed14fbaba9d5557d766a9"> 8320</a></span><span class="preprocessor">#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) </span></div>
|
||
<div class="line"><a id="l08321" name="l08321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84f78f6726211e6183ec7fcd3a40d2a8"> 8321</a></span><span class="preprocessor">#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk </span></div>
|
||
<div class="line"><a id="l08322" name="l08322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed656d73e74d6e4dc451d61cdd4529f9"> 8322</a></span><span class="preprocessor">#define GPIO_OTYPER_OT14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l08323" name="l08323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7a50883c2c1f5f71ffed16b182b4690"> 8323</a></span><span class="preprocessor">#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) </span></div>
|
||
<div class="line"><a id="l08324" name="l08324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1323319e1db0678046b6f77c45bfee8b"> 8324</a></span><span class="preprocessor">#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk </span></div>
|
||
<div class="line"><a id="l08325" name="l08325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5efa1dc79a92b77579d2fd7fe2612c1b"> 8325</a></span><span class="preprocessor">#define GPIO_OTYPER_OT15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l08326" name="l08326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe5d4eaffe4617f72cc460127fc20cf5"> 8326</a></span><span class="preprocessor">#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) </span></div>
|
||
<div class="line"><a id="l08327" name="l08327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c309a7ab680e01fcb7d001ea0a98c70"> 8327</a></span><span class="preprocessor">#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk </span></div>
|
||
<div class="line"><a id="l08328" name="l08328"></a><span class="lineno"> 8328</span> </div>
|
||
<div class="line"><a id="l08329" name="l08329"></a><span class="lineno"> 8329</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l08330" name="l08330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2f02eab04f88423789f532370680305"> 8330</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0</span></div>
|
||
<div class="line"><a id="l08331" name="l08331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a842ad8f83c21f019f2e1e08f104a7f"> 8331</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1</span></div>
|
||
<div class="line"><a id="l08332" name="l08332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d3a246b6320fc51b39123249e1e6817"> 8332</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2</span></div>
|
||
<div class="line"><a id="l08333" name="l08333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef881bb4fa6b2dd9cecd4ee1385b6361"> 8333</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3</span></div>
|
||
<div class="line"><a id="l08334" name="l08334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c3cc7a0b2c9b99212879cc8d7455258"> 8334</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4</span></div>
|
||
<div class="line"><a id="l08335" name="l08335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa0dd76857b25ae35a785cee97c8403d"> 8335</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5</span></div>
|
||
<div class="line"><a id="l08336" name="l08336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1dbea639fd4ffe59a706a11fb1ee104b"> 8336</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6</span></div>
|
||
<div class="line"><a id="l08337" name="l08337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaacead96dc3377342af4aa18adf6453e"> 8337</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7</span></div>
|
||
<div class="line"><a id="l08338" name="l08338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a1f64fdf2ab84c634c0fa8cb060a65f"> 8338</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8</span></div>
|
||
<div class="line"><a id="l08339" name="l08339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5c7deea3d764bb3999578030e3158aa"> 8339</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9</span></div>
|
||
<div class="line"><a id="l08340" name="l08340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc1ef9cbe4226f9616c64bb641b44b3b"> 8340</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10</span></div>
|
||
<div class="line"><a id="l08341" name="l08341"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd4fc33a12439fdf4ada19c04227dea7"> 8341</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11</span></div>
|
||
<div class="line"><a id="l08342" name="l08342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24e978fcc3d4e87bed919511e1226f0c"> 8342</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12</span></div>
|
||
<div class="line"><a id="l08343" name="l08343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c5d7751cfdfaf58782f01692d8c88e8"> 8343</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13</span></div>
|
||
<div class="line"><a id="l08344" name="l08344"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c26938a0e8c03d90a966fc33f186e50"> 8344</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14</span></div>
|
||
<div class="line"><a id="l08345" name="l08345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51f153263d58a45fc2ef0734fc3f73eb"> 8345</a></span><span class="preprocessor">#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15</span></div>
|
||
<div class="line"><a id="l08346" name="l08346"></a><span class="lineno"> 8346</span> </div>
|
||
<div class="line"><a id="l08347" name="l08347"></a><span class="lineno"> 8347</span><span class="comment">/****************** Bits definition for GPIO_OSPEEDR register ***************/</span></div>
|
||
<div class="line"><a id="l08348" name="l08348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga129f816361ac723f130c2757ab606de2"> 8348</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l08349" name="l08349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab411afa3d01185fcac7de1834855b03b"> 8349</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) </span></div>
|
||
<div class="line"><a id="l08350" name="l08350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25d567c6d24df0adb6402498fd5eb582"> 8350</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk </span></div>
|
||
<div class="line"><a id="l08351" name="l08351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae999b23bc1e7f750599e3919db67bba7"> 8351</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) </span></div>
|
||
<div class="line"><a id="l08352" name="l08352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa211d91a2e8fa199d4d1c64e20c2283c"> 8352</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) </span></div>
|
||
<div class="line"><a id="l08353" name="l08353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8253e839d2f456baf264cc3639876b25"> 8353</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED1_Pos (2U) </span></div>
|
||
<div class="line"><a id="l08354" name="l08354"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga788188c5bf4669f2b316aa0c6b723e9e"> 8354</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) </span></div>
|
||
<div class="line"><a id="l08355" name="l08355"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8996628496af3a04fb060e7be6b4af6"> 8355</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk </span></div>
|
||
<div class="line"><a id="l08356" name="l08356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08097ab565c4771df00762e15e93642c"> 8356</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) </span></div>
|
||
<div class="line"><a id="l08357" name="l08357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cb2eaafcac4ea42ea17c030512fd59d"> 8357</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) </span></div>
|
||
<div class="line"><a id="l08358" name="l08358"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcc5a8e431eddf53ff110e3cabcf84a9"> 8358</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED2_Pos (4U) </span></div>
|
||
<div class="line"><a id="l08359" name="l08359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a287b69df598692ea5425ac903ee934"> 8359</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) </span></div>
|
||
<div class="line"><a id="l08360" name="l08360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00c3e1150ff05598e93fdee8dd68936e"> 8360</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk </span></div>
|
||
<div class="line"><a id="l08361" name="l08361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e96818c186656af3af439dcfa16528b"> 8361</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) </span></div>
|
||
<div class="line"><a id="l08362" name="l08362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2548db9b2371c3502f92f75566344141"> 8362</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) </span></div>
|
||
<div class="line"><a id="l08363" name="l08363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b5205a128da01cee0bf8911e6deeba3"> 8363</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED3_Pos (6U) </span></div>
|
||
<div class="line"><a id="l08364" name="l08364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1932d5de59094f3b77d1c38c3363e022"> 8364</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) </span></div>
|
||
<div class="line"><a id="l08365" name="l08365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70a77f985b46c258894f35dd089b0d20"> 8365</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk </span></div>
|
||
<div class="line"><a id="l08366" name="l08366"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2d54448afbd578a80e745bf88141f15"> 8366</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) </span></div>
|
||
<div class="line"><a id="l08367" name="l08367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7445a434c85d73f0343f07e4b1abd2e"> 8367</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) </span></div>
|
||
<div class="line"><a id="l08368" name="l08368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8965c0a99fbe9052bf008a4da714b84b"> 8368</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED4_Pos (8U) </span></div>
|
||
<div class="line"><a id="l08369" name="l08369"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91182962d406df7459584b8cb9646e9e"> 8369</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) </span></div>
|
||
<div class="line"><a id="l08370" name="l08370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44b7462b3a8eac83a6190a9d4ed94733"> 8370</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk </span></div>
|
||
<div class="line"><a id="l08371" name="l08371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7bc92d4bc48eb29f15eeda3b4f2b7729"> 8371</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) </span></div>
|
||
<div class="line"><a id="l08372" name="l08372"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1074b9afc9555d005eed1283990ee2e"> 8372</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) </span></div>
|
||
<div class="line"><a id="l08373" name="l08373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3dbca74e2ddaa85108e7326cd681c345"> 8373</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED5_Pos (10U) </span></div>
|
||
<div class="line"><a id="l08374" name="l08374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fe5071dcf994ca5836756cd44c7df76"> 8374</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) </span></div>
|
||
<div class="line"><a id="l08375" name="l08375"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39a76e505a04bac8df5b801bc759d9cf"> 8375</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk </span></div>
|
||
<div class="line"><a id="l08376" name="l08376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51db6938ff53112b1546ea2955c6bec8"> 8376</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) </span></div>
|
||
<div class="line"><a id="l08377" name="l08377"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33507bcb6d4a5f11748cd0f81483e900"> 8377</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) </span></div>
|
||
<div class="line"><a id="l08378" name="l08378"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2559ea5b8212d7799d95c5a67593826"> 8378</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED6_Pos (12U) </span></div>
|
||
<div class="line"><a id="l08379" name="l08379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f07ebb84c0aa6967ca9057d75f3d5cc"> 8379</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) </span></div>
|
||
<div class="line"><a id="l08380" name="l08380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga220c76017b851a0861252cdc19e5ad8e"> 8380</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk </span></div>
|
||
<div class="line"><a id="l08381" name="l08381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab28c483d24d4f8aefdf89578af2a66a5"> 8381</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) </span></div>
|
||
<div class="line"><a id="l08382" name="l08382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2d7d80ccb16466efc06dc08334539fe"> 8382</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) </span></div>
|
||
<div class="line"><a id="l08383" name="l08383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e1d68c48b823f2ddcbc19f9472b71e0"> 8383</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED7_Pos (14U) </span></div>
|
||
<div class="line"><a id="l08384" name="l08384"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab238b715009a8081e4299a04464f8fba"> 8384</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) </span></div>
|
||
<div class="line"><a id="l08385" name="l08385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada868726c50880ee3f5e3cf35bf7be07"> 8385</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk </span></div>
|
||
<div class="line"><a id="l08386" name="l08386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga241f032a5afcf9fbaf7a03ca6756dae3"> 8386</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) </span></div>
|
||
<div class="line"><a id="l08387" name="l08387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55510fcf6f51a1badbd0507b0174ca82"> 8387</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) </span></div>
|
||
<div class="line"><a id="l08388" name="l08388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga752447edb6283f5ab3639ea160311702"> 8388</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED8_Pos (16U) </span></div>
|
||
<div class="line"><a id="l08389" name="l08389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b220cadf1c6f35a7a5ee9141b353361"> 8389</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) </span></div>
|
||
<div class="line"><a id="l08390" name="l08390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48fc91b25c5e9b44cb2c5281e430b530"> 8390</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk </span></div>
|
||
<div class="line"><a id="l08391" name="l08391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9cc347eada649f592544fe46a60d61f"> 8391</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) </span></div>
|
||
<div class="line"><a id="l08392" name="l08392"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga001e0393d3563dce9de7822581d99f74"> 8392</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) </span></div>
|
||
<div class="line"><a id="l08393" name="l08393"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05c5c757f8ec338edbbf08bf5d8d68c5"> 8393</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED9_Pos (18U) </span></div>
|
||
<div class="line"><a id="l08394" name="l08394"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaaf713561b3fe73574b8566e54dbb7da"> 8394</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) </span></div>
|
||
<div class="line"><a id="l08395" name="l08395"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa18d29dd7797e82889241af2394d9bac"> 8395</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk </span></div>
|
||
<div class="line"><a id="l08396" name="l08396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79c3d503027ce61ba59f5362579c8c75"> 8396</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) </span></div>
|
||
<div class="line"><a id="l08397" name="l08397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cf1f4b8620e0003ea2ee281c4d1a86e"> 8397</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) </span></div>
|
||
<div class="line"><a id="l08398" name="l08398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4fbf963f1c171fe8902f5b81b6e45e6e"> 8398</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED10_Pos (20U) </span></div>
|
||
<div class="line"><a id="l08399" name="l08399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7aa2187e9c9634216889077d878c85ae"> 8399</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) </span></div>
|
||
<div class="line"><a id="l08400" name="l08400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0d96748028e1d2c05fb5a12d6ec6148"> 8400</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk </span></div>
|
||
<div class="line"><a id="l08401" name="l08401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4af74162b730df90c198dd5375c93db"> 8401</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) </span></div>
|
||
<div class="line"><a id="l08402" name="l08402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac42c58e1c4f708bb1702b980d7335481"> 8402</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) </span></div>
|
||
<div class="line"><a id="l08403" name="l08403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab897b530b59c6f2f54305fb9db56fa9d"> 8403</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED11_Pos (22U) </span></div>
|
||
<div class="line"><a id="l08404" name="l08404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffc4df43b3ca66616ef75c75d828031f"> 8404</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) </span></div>
|
||
<div class="line"><a id="l08405" name="l08405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae71fee4a9fee0076207522f7b05d3e7b"> 8405</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk </span></div>
|
||
<div class="line"><a id="l08406" name="l08406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac1765e06791c8f44a8ab2771ce6e3e0"> 8406</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) </span></div>
|
||
<div class="line"><a id="l08407" name="l08407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad48d309936025096bfc6cb30fa37464c"> 8407</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) </span></div>
|
||
<div class="line"><a id="l08408" name="l08408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7326dbd78a260f065b3df743fbea3054"> 8408</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED12_Pos (24U) </span></div>
|
||
<div class="line"><a id="l08409" name="l08409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga941e03858f17e677f54ee229faacdeaa"> 8409</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) </span></div>
|
||
<div class="line"><a id="l08410" name="l08410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91c0b6ceee5147b85871df78f1b7ae38"> 8410</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk </span></div>
|
||
<div class="line"><a id="l08411" name="l08411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga227ef84ae7d0d0ed7f2e01c26804ad0b"> 8411</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) </span></div>
|
||
<div class="line"><a id="l08412" name="l08412"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42e694529900596202d4cdd7ba188427"> 8412</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) </span></div>
|
||
<div class="line"><a id="l08413" name="l08413"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8362c7b2a216297bbf58ea02b3df434d"> 8413</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED13_Pos (26U) </span></div>
|
||
<div class="line"><a id="l08414" name="l08414"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga087816fdc310c1d74fa885b608c620c9"> 8414</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) </span></div>
|
||
<div class="line"><a id="l08415" name="l08415"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabec7c4b2c0464c31b94d819b458294bc"> 8415</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk </span></div>
|
||
<div class="line"><a id="l08416" name="l08416"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27d214e42ae822601fe8469c5310337d"> 8416</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) </span></div>
|
||
<div class="line"><a id="l08417" name="l08417"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2ce26af8af11b3592c5e70fddf24a1a"> 8417</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) </span></div>
|
||
<div class="line"><a id="l08418" name="l08418"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga542445998ee4d4e0a1ecc80f96415769"> 8418</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED14_Pos (28U) </span></div>
|
||
<div class="line"><a id="l08419" name="l08419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fb875fe73210c3a4e1c269e030a357b"> 8419</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) </span></div>
|
||
<div class="line"><a id="l08420" name="l08420"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa27efa359dedf4559a0cae3b4ccbb866"> 8420</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk </span></div>
|
||
<div class="line"><a id="l08421" name="l08421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf32f167e31bfe8d231d99369cad3a932"> 8421</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) </span></div>
|
||
<div class="line"><a id="l08422" name="l08422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e7a469a29270897c6a7f44e94fca1f2"> 8422</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) </span></div>
|
||
<div class="line"><a id="l08423" name="l08423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e98a82b548dbb52cb0d16d6c9b68da9"> 8423</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED15_Pos (30U) </span></div>
|
||
<div class="line"><a id="l08424" name="l08424"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45c126130830699c993c2d790c31f5e6"> 8424</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) </span></div>
|
||
<div class="line"><a id="l08425" name="l08425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62066038e31f29b2d96a9c9756b47007"> 8425</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk </span></div>
|
||
<div class="line"><a id="l08426" name="l08426"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4114c96c51d3cee45535ff5265b47b2"> 8426</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) </span></div>
|
||
<div class="line"><a id="l08427" name="l08427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01afd6d3720d359e6b8c76d03e6c5eb9"> 8427</a></span><span class="preprocessor">#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) </span></div>
|
||
<div class="line"><a id="l08429" name="l08429"></a><span class="lineno"> 8429</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l08430" name="l08430"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86a137cc8e566a0da86e2fd4778938a6"> 8430</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0</span></div>
|
||
<div class="line"><a id="l08431" name="l08431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95ff622f2b5941ce7202fe97a6e8c730"> 8431</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0</span></div>
|
||
<div class="line"><a id="l08432" name="l08432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a8e561180cdfcb7440a017d2aa10f59"> 8432</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1</span></div>
|
||
<div class="line"><a id="l08433" name="l08433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9aca2c7cf73dd7a08fee8ae9a675c1d5"> 8433</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1</span></div>
|
||
<div class="line"><a id="l08434" name="l08434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5dd10c0d3419e2d2fda1af77fbc28156"> 8434</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0</span></div>
|
||
<div class="line"><a id="l08435" name="l08435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ebe740312db53a7d49ff7f78436bcb6"> 8435</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1</span></div>
|
||
<div class="line"><a id="l08436" name="l08436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f3dd6eabaf2dee10a45718bf9214bff"> 8436</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2</span></div>
|
||
<div class="line"><a id="l08437" name="l08437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga285b9f4328a29f624945f8fc57daab0e"> 8437</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0</span></div>
|
||
<div class="line"><a id="l08438" name="l08438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb41ac1ecdc620a7888e9714f36611c2"> 8438</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1</span></div>
|
||
<div class="line"><a id="l08439" name="l08439"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bd77104c298e2cc79608954ed8a81e6"> 8439</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3</span></div>
|
||
<div class="line"><a id="l08440" name="l08440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86ad8f39a6399526c2a06f5e481b7edd"> 8440</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0</span></div>
|
||
<div class="line"><a id="l08441" name="l08441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4cbbc6c634d9f64d2959bfce25e475e3"> 8441</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1</span></div>
|
||
<div class="line"><a id="l08442" name="l08442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae993f7764c1e10e2f5022cba2a081f97"> 8442</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4</span></div>
|
||
<div class="line"><a id="l08443" name="l08443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e6579b81f162ca8d4b8ee6690b258e9"> 8443</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0</span></div>
|
||
<div class="line"><a id="l08444" name="l08444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56650b0113cbb5ed50903e684abfdabc"> 8444</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1</span></div>
|
||
<div class="line"><a id="l08445" name="l08445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6e84a83dd64be450a33a67c9ba44add"> 8445</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5</span></div>
|
||
<div class="line"><a id="l08446" name="l08446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ee63c65224da433a0f588bdd579c88d"> 8446</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0</span></div>
|
||
<div class="line"><a id="l08447" name="l08447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9feeadb829cbfbcc7f5ff5aa614e35de"> 8447</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1</span></div>
|
||
<div class="line"><a id="l08448" name="l08448"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa153220faa507b53170bd49dcffcfc76"> 8448</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6</span></div>
|
||
<div class="line"><a id="l08449" name="l08449"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga314fae4f204824abf26545482246eb46"> 8449</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0</span></div>
|
||
<div class="line"><a id="l08450" name="l08450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5502c629c3894c58a5e3e5e4398f92b"> 8450</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1</span></div>
|
||
<div class="line"><a id="l08451" name="l08451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga187b9c0a07272ef24ff4e579c2c724a9"> 8451</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7</span></div>
|
||
<div class="line"><a id="l08452" name="l08452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa351c9cc66134dd2077fe4936e10068e"> 8452</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0</span></div>
|
||
<div class="line"><a id="l08453" name="l08453"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5824b9a56d3ab570c90c02e959f8e8a3"> 8453</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1</span></div>
|
||
<div class="line"><a id="l08454" name="l08454"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57fdec64829712f410b7099168d03335"> 8454</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8</span></div>
|
||
<div class="line"><a id="l08455" name="l08455"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00e257135823303b40c2dfe2054c72e6"> 8455</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0</span></div>
|
||
<div class="line"><a id="l08456" name="l08456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab026b036652fcab5dbec7fcccd8ec117"> 8456</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1</span></div>
|
||
<div class="line"><a id="l08457" name="l08457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2974e9de8b939e683976d3244f946c5"> 8457</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9</span></div>
|
||
<div class="line"><a id="l08458" name="l08458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga922dc2241064ba91a32163b52dc979a1"> 8458</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0</span></div>
|
||
<div class="line"><a id="l08459" name="l08459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8958bf41efda58bc0c216496c3523a95"> 8459</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1</span></div>
|
||
<div class="line"><a id="l08460" name="l08460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f368a4fe9f84a2a1f75127cd92de706"> 8460</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10</span></div>
|
||
<div class="line"><a id="l08461" name="l08461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad24e2db3605c0510221a5d6cc18de45d"> 8461</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0</span></div>
|
||
<div class="line"><a id="l08462" name="l08462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0b5fe166b79464e9419092b50a216e8"> 8462</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1</span></div>
|
||
<div class="line"><a id="l08463" name="l08463"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f6fbff92ca95c7b4b49b773993af08f"> 8463</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11</span></div>
|
||
<div class="line"><a id="l08464" name="l08464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7413457e1249fedd60208f6d1fe66fec"> 8464</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0</span></div>
|
||
<div class="line"><a id="l08465" name="l08465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5a0177db55f86818a42240bf188c0bc"> 8465</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1</span></div>
|
||
<div class="line"><a id="l08466" name="l08466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9928dcdc592ee959941c97aed702a99"> 8466</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12</span></div>
|
||
<div class="line"><a id="l08467" name="l08467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68d9034e325bf95773f70a9cc94598af"> 8467</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0</span></div>
|
||
<div class="line"><a id="l08468" name="l08468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga225f0a354cd3c2391ed922b08dbc0cae"> 8468</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1</span></div>
|
||
<div class="line"><a id="l08469" name="l08469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09d3845b5e708a7636cddf01c5a30468"> 8469</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13</span></div>
|
||
<div class="line"><a id="l08470" name="l08470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93ce0e08aefefa639657d0ca1a169557"> 8470</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0</span></div>
|
||
<div class="line"><a id="l08471" name="l08471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fee18398176eeceef1a6a0229d81029"> 8471</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1</span></div>
|
||
<div class="line"><a id="l08472" name="l08472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae956b8918d07e914a3f9861de501623f"> 8472</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14</span></div>
|
||
<div class="line"><a id="l08473" name="l08473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcec6386ada8c016b4696b853a6d1ff1"> 8473</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0</span></div>
|
||
<div class="line"><a id="l08474" name="l08474"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8fb23e47faf2dd2b69a22e36c4ea56d"> 8474</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1</span></div>
|
||
<div class="line"><a id="l08475" name="l08475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b405fe1beed00abecfb3d83b9f94b65"> 8475</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15</span></div>
|
||
<div class="line"><a id="l08476" name="l08476"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga782862d03460b05a56d3287c971aabc8"> 8476</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0</span></div>
|
||
<div class="line"><a id="l08477" name="l08477"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga929ae0a4ff8f30c45042715a73ab1ad7"> 8477</a></span><span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1</span></div>
|
||
<div class="line"><a id="l08478" name="l08478"></a><span class="lineno"> 8478</span> </div>
|
||
<div class="line"><a id="l08479" name="l08479"></a><span class="lineno"> 8479</span><span class="comment">/****************** Bits definition for GPIO_PUPDR register *****************/</span></div>
|
||
<div class="line"><a id="l08480" name="l08480"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada27513a02562dc3e44c361eb96d8d60"> 8480</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l08481" name="l08481"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0be0e927e30b38360486e4d57854c20"> 8481</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) </span></div>
|
||
<div class="line"><a id="l08482" name="l08482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga757af1d9f0ba5f4ed76320b6932e3741"> 8482</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk </span></div>
|
||
<div class="line"><a id="l08483" name="l08483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ecb6eae6b933d78446834bf320cc235"> 8483</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) </span></div>
|
||
<div class="line"><a id="l08484" name="l08484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d8177954b7806374d1cbba3bbbfe034"> 8484</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) </span></div>
|
||
<div class="line"><a id="l08485" name="l08485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2dc73dd62120c9617e25ccbf4b038991"> 8485</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD1_Pos (2U) </span></div>
|
||
<div class="line"><a id="l08486" name="l08486"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac529eb9b34ed26a9fb436c230cbad882"> 8486</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) </span></div>
|
||
<div class="line"><a id="l08487" name="l08487"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8da0bf95f1973c18a4a4b7c0aa3d1404"> 8487</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk </span></div>
|
||
<div class="line"><a id="l08488" name="l08488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6512d7fee2b400279ebd0843a5e481c"> 8488</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) </span></div>
|
||
<div class="line"><a id="l08489" name="l08489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb010cc75a60effd883969c35611f5c8"> 8489</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) </span></div>
|
||
<div class="line"><a id="l08490" name="l08490"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga586d58e70155a838a7607fa1d209e367"> 8490</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD2_Pos (4U) </span></div>
|
||
<div class="line"><a id="l08491" name="l08491"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa71a5ea0b0b124a1af187ef2160b412a"> 8491</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) </span></div>
|
||
<div class="line"><a id="l08492" name="l08492"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e8cc32256e605234ec8bfba9ebbe2d2"> 8492</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk </span></div>
|
||
<div class="line"><a id="l08493" name="l08493"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga044bf572e114a7746127135a3f38caef"> 8493</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) </span></div>
|
||
<div class="line"><a id="l08494" name="l08494"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06efd822240e0026cb83e661b88a9e3c"> 8494</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) </span></div>
|
||
<div class="line"><a id="l08495" name="l08495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16874909048265725250c4d8b3d1fe16"> 8495</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD3_Pos (6U) </span></div>
|
||
<div class="line"><a id="l08496" name="l08496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4fbaf3b066dac1e0986a5b68ce30b0d3"> 8496</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) </span></div>
|
||
<div class="line"><a id="l08497" name="l08497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c6217b6d33bf54771323d7f55e6fa9c"> 8497</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk </span></div>
|
||
<div class="line"><a id="l08498" name="l08498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f885f83700f6710d75e8a23135e4449"> 8498</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) </span></div>
|
||
<div class="line"><a id="l08499" name="l08499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga713dc2ffd7e76239f05399299043538a"> 8499</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) </span></div>
|
||
<div class="line"><a id="l08500" name="l08500"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffa6624f76681ba96183f8ea998da581"> 8500</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD4_Pos (8U) </span></div>
|
||
<div class="line"><a id="l08501" name="l08501"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f0de7c586465d6dfb0e50d1194271cf"> 8501</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) </span></div>
|
||
<div class="line"><a id="l08502" name="l08502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf02aa5885737e111d98770d67b858d8e"> 8502</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk </span></div>
|
||
<div class="line"><a id="l08503" name="l08503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa25af0133be08cc46bd64d19913f090c"> 8503</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) </span></div>
|
||
<div class="line"><a id="l08504" name="l08504"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac699c89b1b15ad635a1a1109cbe2963e"> 8504</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) </span></div>
|
||
<div class="line"><a id="l08505" name="l08505"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17c1aea5321b3308171bc9b813fccf02"> 8505</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD5_Pos (10U) </span></div>
|
||
<div class="line"><a id="l08506" name="l08506"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2dca8d52990a63a4185d8185d3100222"> 8506</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) </span></div>
|
||
<div class="line"><a id="l08507" name="l08507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe54b8696e32251e874a821819d7c94d"> 8507</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk </span></div>
|
||
<div class="line"><a id="l08508" name="l08508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31e7a8da20fb184d4bca472726c98058"> 8508</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) </span></div>
|
||
<div class="line"><a id="l08509" name="l08509"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c3f4ba96ad50d3d5230fa8fb89f637d"> 8509</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) </span></div>
|
||
<div class="line"><a id="l08510" name="l08510"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5cfdcc6b1779a517c19516429c6666b"> 8510</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD6_Pos (12U) </span></div>
|
||
<div class="line"><a id="l08511" name="l08511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga841c8e128f84ac7451f431d24a222072"> 8511</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) </span></div>
|
||
<div class="line"><a id="l08512" name="l08512"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa52d8b944af9bb59f52c2fd46559abdb"> 8512</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk </span></div>
|
||
<div class="line"><a id="l08513" name="l08513"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6aa2ea03e1632d3dfe812911bfd97f0b"> 8513</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) </span></div>
|
||
<div class="line"><a id="l08514" name="l08514"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b5d490177e16ae30cd5264012feaa87"> 8514</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) </span></div>
|
||
<div class="line"><a id="l08515" name="l08515"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3de6729553a81ba44a7d1b93378d9536"> 8515</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD7_Pos (14U) </span></div>
|
||
<div class="line"><a id="l08516" name="l08516"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga268436f429d673b3b39ea443656997ad"> 8516</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) </span></div>
|
||
<div class="line"><a id="l08517" name="l08517"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18557333a95ca1a26bcd1d7f9fe207be"> 8517</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk </span></div>
|
||
<div class="line"><a id="l08518" name="l08518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2954be6ab54a7d922b2d0f9e5d173f4"> 8518</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) </span></div>
|
||
<div class="line"><a id="l08519" name="l08519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb959dd401c4890303c5c7fd962bcc08"> 8519</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) </span></div>
|
||
<div class="line"><a id="l08520" name="l08520"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55b1f4d9f5e3bedd3c6af387409e5eba"> 8520</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD8_Pos (16U) </span></div>
|
||
<div class="line"><a id="l08521" name="l08521"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga750db53344fb2cc3fb432ff0d7faa85c"> 8521</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) </span></div>
|
||
<div class="line"><a id="l08522" name="l08522"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e71b61abf42a76033e458460793f940"> 8522</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk </span></div>
|
||
<div class="line"><a id="l08523" name="l08523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga430de706497b304d9821b50b3a51ac49"> 8523</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) </span></div>
|
||
<div class="line"><a id="l08524" name="l08524"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9a687c70a3cd5ef5ccef3a13e431b89"> 8524</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) </span></div>
|
||
<div class="line"><a id="l08525" name="l08525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0e83ee550967747ec5a38f064031b3e"> 8525</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD9_Pos (18U) </span></div>
|
||
<div class="line"><a id="l08526" name="l08526"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae60c0e898107eed9a832cc445d00e8f8"> 8526</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) </span></div>
|
||
<div class="line"><a id="l08527" name="l08527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c7ece6fe1df8b61fd7f11f6751693a9"> 8527</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk </span></div>
|
||
<div class="line"><a id="l08528" name="l08528"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b6a86ea34af6c236caa23893d34e6d2"> 8528</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) </span></div>
|
||
<div class="line"><a id="l08529" name="l08529"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07fb1faf433996b633d49c8307ce9bb2"> 8529</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) </span></div>
|
||
<div class="line"><a id="l08530" name="l08530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19ff590a0540fab5751f0f0b36ea3ac8"> 8530</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD10_Pos (20U) </span></div>
|
||
<div class="line"><a id="l08531" name="l08531"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94f8b1bfa375b95aa586d4e657d810c1"> 8531</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) </span></div>
|
||
<div class="line"><a id="l08532" name="l08532"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53f1c72b27ac3f18d6e8c7b366416ba6"> 8532</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk </span></div>
|
||
<div class="line"><a id="l08533" name="l08533"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71dc18b0db03b06216a30e15bb08c81f"> 8533</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) </span></div>
|
||
<div class="line"><a id="l08534" name="l08534"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga955fdb4da04d3702e3566d5068d9fd0a"> 8534</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) </span></div>
|
||
<div class="line"><a id="l08535" name="l08535"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab55094695264b5c3342f623dec206815"> 8535</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD11_Pos (22U) </span></div>
|
||
<div class="line"><a id="l08536" name="l08536"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd0f388b7d8039e4b3d8dd573bc8f429"> 8536</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) </span></div>
|
||
<div class="line"><a id="l08537" name="l08537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85596aa60b034d0de6ecb98f94a8d036"> 8537</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk </span></div>
|
||
<div class="line"><a id="l08538" name="l08538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5acc6eda43958a03426815a0db4a494b"> 8538</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) </span></div>
|
||
<div class="line"><a id="l08539" name="l08539"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2666e7ba5f50abf8502ba8e0f0f57430"> 8539</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) </span></div>
|
||
<div class="line"><a id="l08540" name="l08540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2f7ab8ad7a8ac91e877e24f8119a783"> 8540</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD12_Pos (24U) </span></div>
|
||
<div class="line"><a id="l08541" name="l08541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30a14d0a21b413ff9c5ff1efdec903bc"> 8541</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) </span></div>
|
||
<div class="line"><a id="l08542" name="l08542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga834911368392a16ff6b7e051a7e7ae9c"> 8542</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk </span></div>
|
||
<div class="line"><a id="l08543" name="l08543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabac3dea5943de3917f93772936539e74"> 8543</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) </span></div>
|
||
<div class="line"><a id="l08544" name="l08544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90f8b6c555a779ed1bef06e7ab1a0600"> 8544</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) </span></div>
|
||
<div class="line"><a id="l08545" name="l08545"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb87a27f5193bc33e7b553faa006086b"> 8545</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD13_Pos (26U) </span></div>
|
||
<div class="line"><a id="l08546" name="l08546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadebe9101a2f2de81d563e9e982c186cd"> 8546</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) </span></div>
|
||
<div class="line"><a id="l08547" name="l08547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga746478979825dcad6323b002906581b9"> 8547</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk </span></div>
|
||
<div class="line"><a id="l08548" name="l08548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4f37903148418084e6059041ac2d3c8"> 8548</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) </span></div>
|
||
<div class="line"><a id="l08549" name="l08549"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4dd950825a4c5bb9e89e44f4398f050"> 8549</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) </span></div>
|
||
<div class="line"><a id="l08550" name="l08550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4405ac26d78b02793fc695d410bd7b88"> 8550</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD14_Pos (28U) </span></div>
|
||
<div class="line"><a id="l08551" name="l08551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7e0dc8ebc4e7c81e65265cae3b23aa4"> 8551</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) </span></div>
|
||
<div class="line"><a id="l08552" name="l08552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga398c010d45105e8e37b1995430a52a94"> 8552</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk </span></div>
|
||
<div class="line"><a id="l08553" name="l08553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2312d606bfcd3b62e9885d7d7b316b39"> 8553</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) </span></div>
|
||
<div class="line"><a id="l08554" name="l08554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88f904affe99bf7a5045c1c3704d1146"> 8554</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) </span></div>
|
||
<div class="line"><a id="l08555" name="l08555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9596e5ba318ea6eb9d0de839e5125f7e"> 8555</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD15_Pos (30U) </span></div>
|
||
<div class="line"><a id="l08556" name="l08556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae63e9b1d8c9e5f92cbb3f8ad67304f67"> 8556</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) </span></div>
|
||
<div class="line"><a id="l08557" name="l08557"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd5cdc50a6f6ee671aa1ac39c9048241"> 8557</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk </span></div>
|
||
<div class="line"><a id="l08558" name="l08558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39538a30aef08d4bbf9ce88ee22d1b46"> 8558</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) </span></div>
|
||
<div class="line"><a id="l08559" name="l08559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24352127803f5fbe718ff22e7a1062b4"> 8559</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) </span></div>
|
||
<div class="line"><a id="l08561" name="l08561"></a><span class="lineno"> 8561</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l08562" name="l08562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04d9e85c6ccb1c915142139b2fd40277"> 8562</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0</span></div>
|
||
<div class="line"><a id="l08563" name="l08563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90ce7d30e6ae0b2faca4a6861ecc4cc6"> 8563</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0</span></div>
|
||
<div class="line"><a id="l08564" name="l08564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafce37884b3fefd13f415d3d0e86cba54"> 8564</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1</span></div>
|
||
<div class="line"><a id="l08565" name="l08565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fc992293f3aea2c0bfb5a04524a0f29"> 8565</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1</span></div>
|
||
<div class="line"><a id="l08566" name="l08566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf102b1b4f826fdc1febfeaf42a7d8a7f"> 8566</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0</span></div>
|
||
<div class="line"><a id="l08567" name="l08567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33e13010f729b9a9555c1af45ee42bf7"> 8567</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1</span></div>
|
||
<div class="line"><a id="l08568" name="l08568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga719f6a7905af1965aeb1d22053819ea4"> 8568</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2</span></div>
|
||
<div class="line"><a id="l08569" name="l08569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae53f1f88362bc9d12367842b2c41ac5f"> 8569</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0</span></div>
|
||
<div class="line"><a id="l08570" name="l08570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad00c76742cc343b8be0aef2b7a552b21"> 8570</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1</span></div>
|
||
<div class="line"><a id="l08571" name="l08571"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaae9d69d2db60b442144cc0f7427455d"> 8571</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3</span></div>
|
||
<div class="line"><a id="l08572" name="l08572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fa0a8d6a6bfc0dd9d6cd2cf26a736a9"> 8572</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0</span></div>
|
||
<div class="line"><a id="l08573" name="l08573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9bd409075d0271cfcf5f2a382f55af83"> 8573</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1</span></div>
|
||
<div class="line"><a id="l08574" name="l08574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46b83340a77ca8575458294e095a1b3e"> 8574</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4</span></div>
|
||
<div class="line"><a id="l08575" name="l08575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaaa42ab206386a753e8d57b76761d787"> 8575</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0</span></div>
|
||
<div class="line"><a id="l08576" name="l08576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7c19b72c8d4ebff81d9e7a6bb292d9e"> 8576</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1</span></div>
|
||
<div class="line"><a id="l08577" name="l08577"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga184f05795320c61aac7d5f99875aaaf3"> 8577</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5</span></div>
|
||
<div class="line"><a id="l08578" name="l08578"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga407f836cfe9440c0a9346bae50593324"> 8578</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0</span></div>
|
||
<div class="line"><a id="l08579" name="l08579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e969eee59eb13d03cecb10296f3cba3"> 8579</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1</span></div>
|
||
<div class="line"><a id="l08580" name="l08580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga867aff49673e9c790a7c07ffc94c9426"> 8580</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6</span></div>
|
||
<div class="line"><a id="l08581" name="l08581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa74c5941b0d588bfd8334c97dd16871e"> 8581</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0</span></div>
|
||
<div class="line"><a id="l08582" name="l08582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84fe57689233ae16b9b38b3db0f8b31b"> 8582</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1</span></div>
|
||
<div class="line"><a id="l08583" name="l08583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa747a73c564fc74b1b7cf597b4df2e2f"> 8583</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7</span></div>
|
||
<div class="line"><a id="l08584" name="l08584"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b75312f187bed2ef764a0f244b8cd1b"> 8584</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0</span></div>
|
||
<div class="line"><a id="l08585" name="l08585"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga284ea60cb769d74a000af43ddebfdbeb"> 8585</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1</span></div>
|
||
<div class="line"><a id="l08586" name="l08586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c9d14950ed3985ab81c13047ac0df81"> 8586</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8</span></div>
|
||
<div class="line"><a id="l08587" name="l08587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76b3b97a4a27a8bb2e942c0f95f7af31"> 8587</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0</span></div>
|
||
<div class="line"><a id="l08588" name="l08588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9963e91e82f1059ec170793cbf32986"> 8588</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1</span></div>
|
||
<div class="line"><a id="l08589" name="l08589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35b41b7cab641de2538e1e1d21562bc8"> 8589</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9</span></div>
|
||
<div class="line"><a id="l08590" name="l08590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45a4501a9b4ff20e5404a97031e02537"> 8590</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0</span></div>
|
||
<div class="line"><a id="l08591" name="l08591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef8b9bad1bc1bb219f6b51bb12c48e67"> 8591</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1</span></div>
|
||
<div class="line"><a id="l08592" name="l08592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3ea3497ce2e90ac0e709e7a99088b09"> 8592</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10</span></div>
|
||
<div class="line"><a id="l08593" name="l08593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67fd34cdbc389ee49f5a9bf1271d7dd9"> 8593</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0</span></div>
|
||
<div class="line"><a id="l08594" name="l08594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08ac8e25da27d1b6c97647fd18b3a335"> 8594</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1</span></div>
|
||
<div class="line"><a id="l08595" name="l08595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa93fd3e658c07a9daf9c8016fb4cf46"> 8595</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11</span></div>
|
||
<div class="line"><a id="l08596" name="l08596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18b3ea6ccb52b072cb19d6677b610831"> 8596</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0</span></div>
|
||
<div class="line"><a id="l08597" name="l08597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78a3508e309b9acfa99c3a4301dfb0d8"> 8597</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1</span></div>
|
||
<div class="line"><a id="l08598" name="l08598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ae4262e6f46de65ce93149a20e0d006"> 8598</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12</span></div>
|
||
<div class="line"><a id="l08599" name="l08599"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a0cd6d85037a7ae0d19806a7dc428a0"> 8599</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0</span></div>
|
||
<div class="line"><a id="l08600" name="l08600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga460b8f9029d8703782110e118fd6ccdb"> 8600</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1</span></div>
|
||
<div class="line"><a id="l08601" name="l08601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa63ee70f61bc9df40d9b38af69f93a7e"> 8601</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13</span></div>
|
||
<div class="line"><a id="l08602" name="l08602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae29eccc9daf15c787ebfc26af3fb3194"> 8602</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0</span></div>
|
||
<div class="line"><a id="l08603" name="l08603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80eddbf0106ccf71413851269315125d"> 8603</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1</span></div>
|
||
<div class="line"><a id="l08604" name="l08604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62f533a38f324be7e3e68f5c0f2b3570"> 8604</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14</span></div>
|
||
<div class="line"><a id="l08605" name="l08605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8521ddc4fa71b57540b61ec7803e77f"> 8605</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0</span></div>
|
||
<div class="line"><a id="l08606" name="l08606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5bcc6307af9a6e5f578dfcb4fda49b3"> 8606</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1</span></div>
|
||
<div class="line"><a id="l08607" name="l08607"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac266bda493b96f1200bc0f7ae05a7475"> 8607</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15</span></div>
|
||
<div class="line"><a id="l08608" name="l08608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b6f6a720852e3791433148aab8b722c"> 8608</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0</span></div>
|
||
<div class="line"><a id="l08609" name="l08609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d827196cbbdebdf82554c8c04a1db6f"> 8609</a></span><span class="preprocessor">#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1</span></div>
|
||
<div class="line"><a id="l08610" name="l08610"></a><span class="lineno"> 8610</span> </div>
|
||
<div class="line"><a id="l08611" name="l08611"></a><span class="lineno"> 8611</span><span class="comment">/****************** Bits definition for GPIO_IDR register *******************/</span></div>
|
||
<div class="line"><a id="l08612" name="l08612"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1069cfa20fb4680057c8f9b91826ebe1"> 8612</a></span><span class="preprocessor">#define GPIO_IDR_ID0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l08613" name="l08613"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fe6424f42570902856737fb45f7d321"> 8613</a></span><span class="preprocessor">#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) </span></div>
|
||
<div class="line"><a id="l08614" name="l08614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64aa379a4bcfe84ae33383d689373096"> 8614</a></span><span class="preprocessor">#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk </span></div>
|
||
<div class="line"><a id="l08615" name="l08615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38320698cffb50138c8438a860030cb9"> 8615</a></span><span class="preprocessor">#define GPIO_IDR_ID1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l08616" name="l08616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00dbb77370754ad461600ed3cf418dba"> 8616</a></span><span class="preprocessor">#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) </span></div>
|
||
<div class="line"><a id="l08617" name="l08617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e44bbc1d39579b027765f259dc897ea"> 8617</a></span><span class="preprocessor">#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk </span></div>
|
||
<div class="line"><a id="l08618" name="l08618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1720532896734b3e5ffaccd76834fdef"> 8618</a></span><span class="preprocessor">#define GPIO_IDR_ID2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l08619" name="l08619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b48dad5247c404dda274ab5e5fde340"> 8619</a></span><span class="preprocessor">#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) </span></div>
|
||
<div class="line"><a id="l08620" name="l08620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2b06b287f35a0b048d8f5fbe4a06a9c"> 8620</a></span><span class="preprocessor">#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk </span></div>
|
||
<div class="line"><a id="l08621" name="l08621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9ea4291861a56bb8901653b2c148ccd"> 8621</a></span><span class="preprocessor">#define GPIO_IDR_ID3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l08622" name="l08622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ca640e7db8f27244ae9515a58910ae3"> 8622</a></span><span class="preprocessor">#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) </span></div>
|
||
<div class="line"><a id="l08623" name="l08623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0c3adefa4cafaf0455139b4e80b70eb"> 8623</a></span><span class="preprocessor">#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk </span></div>
|
||
<div class="line"><a id="l08624" name="l08624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3acb4b4ccaae63ec98c19fbe056c74ae"> 8624</a></span><span class="preprocessor">#define GPIO_IDR_ID4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l08625" name="l08625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1d6c2b8346744bc456ea65d4365c207"> 8625</a></span><span class="preprocessor">#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) </span></div>
|
||
<div class="line"><a id="l08626" name="l08626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7454dab87916ca6076b287a21c2e4cd7"> 8626</a></span><span class="preprocessor">#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk </span></div>
|
||
<div class="line"><a id="l08627" name="l08627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f45f4603706510827aa92d39fd4bb45"> 8627</a></span><span class="preprocessor">#define GPIO_IDR_ID5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l08628" name="l08628"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b44907427286bcb72189dbef6fc0148"> 8628</a></span><span class="preprocessor">#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) </span></div>
|
||
<div class="line"><a id="l08629" name="l08629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cbfa2ff564030d912ce8f327850a3bf"> 8629</a></span><span class="preprocessor">#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk </span></div>
|
||
<div class="line"><a id="l08630" name="l08630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbd6ccece5d47d40c929af5cf9973203"> 8630</a></span><span class="preprocessor">#define GPIO_IDR_ID6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l08631" name="l08631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb18ccf8bb22161f83ad929a18d4c4aa"> 8631</a></span><span class="preprocessor">#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) </span></div>
|
||
<div class="line"><a id="l08632" name="l08632"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac933b9235cae5f9fccbd2fc41f9a2dc4"> 8632</a></span><span class="preprocessor">#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk </span></div>
|
||
<div class="line"><a id="l08633" name="l08633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23669c60b1baa1d95dac788cff2a0eb8"> 8633</a></span><span class="preprocessor">#define GPIO_IDR_ID7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l08634" name="l08634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45c9835db5c12b661eae0c5a0a69af5a"> 8634</a></span><span class="preprocessor">#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) </span></div>
|
||
<div class="line"><a id="l08635" name="l08635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09ce75fcb48ac0db30f99ba312e8538a"> 8635</a></span><span class="preprocessor">#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk </span></div>
|
||
<div class="line"><a id="l08636" name="l08636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaba7afe6abb55e6a80fb0ace5d46c883"> 8636</a></span><span class="preprocessor">#define GPIO_IDR_ID8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l08637" name="l08637"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08a268c98dea54059f48bbda7edd8e74"> 8637</a></span><span class="preprocessor">#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) </span></div>
|
||
<div class="line"><a id="l08638" name="l08638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa193633720d142ceca6c6b27c4e87f02"> 8638</a></span><span class="preprocessor">#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk </span></div>
|
||
<div class="line"><a id="l08639" name="l08639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad46ff99f2017c2a5eeab2fdeebfb1012"> 8639</a></span><span class="preprocessor">#define GPIO_IDR_ID9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l08640" name="l08640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dad9a902a8200c53d60ba02de858315"> 8640</a></span><span class="preprocessor">#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) </span></div>
|
||
<div class="line"><a id="l08641" name="l08641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga888325b6581f9ae181f3e4fe904b0c44"> 8641</a></span><span class="preprocessor">#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk </span></div>
|
||
<div class="line"><a id="l08642" name="l08642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6842601dbe73734e8058a6858fa7078"> 8642</a></span><span class="preprocessor">#define GPIO_IDR_ID10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l08643" name="l08643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa33d3d411ebb4a1009e148df02d2ac54"> 8643</a></span><span class="preprocessor">#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) </span></div>
|
||
<div class="line"><a id="l08644" name="l08644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cd53d2742d0ace30b835bd0f44f5ebf"> 8644</a></span><span class="preprocessor">#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk </span></div>
|
||
<div class="line"><a id="l08645" name="l08645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga117cc21fe4de69983c2444c7f8587687"> 8645</a></span><span class="preprocessor">#define GPIO_IDR_ID11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l08646" name="l08646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad068577edb9af03083fcd0f4de0f8758"> 8646</a></span><span class="preprocessor">#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) </span></div>
|
||
<div class="line"><a id="l08647" name="l08647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade5e087b267f95733cc4328522b7890d"> 8647</a></span><span class="preprocessor">#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk </span></div>
|
||
<div class="line"><a id="l08648" name="l08648"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bc8d6bc8dd7654ccb18d936a3efe79f"> 8648</a></span><span class="preprocessor">#define GPIO_IDR_ID12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l08649" name="l08649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04a2965de2040e7c131ca5ab24a6724c"> 8649</a></span><span class="preprocessor">#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) </span></div>
|
||
<div class="line"><a id="l08650" name="l08650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33564d1679db8201389f806595d000d9"> 8650</a></span><span class="preprocessor">#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk </span></div>
|
||
<div class="line"><a id="l08651" name="l08651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada649f077b81777a8ba7ae97160e9fe4"> 8651</a></span><span class="preprocessor">#define GPIO_IDR_ID13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l08652" name="l08652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38255de273b95c94e29c1bdaa637579e"> 8652</a></span><span class="preprocessor">#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) </span></div>
|
||
<div class="line"><a id="l08653" name="l08653"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82e0ce0fca46443e3cbaf887a3a35713"> 8653</a></span><span class="preprocessor">#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk </span></div>
|
||
<div class="line"><a id="l08654" name="l08654"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0921a37817bff3c30f5e4c019b6a4084"> 8654</a></span><span class="preprocessor">#define GPIO_IDR_ID14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l08655" name="l08655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacba67a5c308fb3b335dcd8979625b1b3"> 8655</a></span><span class="preprocessor">#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) </span></div>
|
||
<div class="line"><a id="l08656" name="l08656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac716fc8a3853431b69697ea5ee0aa8d2"> 8656</a></span><span class="preprocessor">#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk </span></div>
|
||
<div class="line"><a id="l08657" name="l08657"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga631021cf3bab4864fdc505ceee8a6c4f"> 8657</a></span><span class="preprocessor">#define GPIO_IDR_ID15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l08658" name="l08658"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18c156b5eb9356ecd1ba66c96864d5a5"> 8658</a></span><span class="preprocessor">#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) </span></div>
|
||
<div class="line"><a id="l08659" name="l08659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae72c80e97c41b8143cf299c078459ea4"> 8659</a></span><span class="preprocessor">#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk </span></div>
|
||
<div class="line"><a id="l08660" name="l08660"></a><span class="lineno"> 8660</span> </div>
|
||
<div class="line"><a id="l08661" name="l08661"></a><span class="lineno"> 8661</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l08662" name="l08662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7691154d734ec08089eb3dc28a369726"> 8662</a></span><span class="preprocessor">#define GPIO_IDR_IDR_0 GPIO_IDR_ID0</span></div>
|
||
<div class="line"><a id="l08663" name="l08663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4b3e9ceaa683b7cbc89f2507ef0f110"> 8663</a></span><span class="preprocessor">#define GPIO_IDR_IDR_1 GPIO_IDR_ID1</span></div>
|
||
<div class="line"><a id="l08664" name="l08664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf32691b8213a6b9c7ddb164bcc66af7f"> 8664</a></span><span class="preprocessor">#define GPIO_IDR_IDR_2 GPIO_IDR_ID2</span></div>
|
||
<div class="line"><a id="l08665" name="l08665"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga172dc9a76f772c8e386ac0162e0a52fa"> 8665</a></span><span class="preprocessor">#define GPIO_IDR_IDR_3 GPIO_IDR_ID3</span></div>
|
||
<div class="line"><a id="l08666" name="l08666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5aded5247a4fa0834a311679c593fcd7"> 8666</a></span><span class="preprocessor">#define GPIO_IDR_IDR_4 GPIO_IDR_ID4</span></div>
|
||
<div class="line"><a id="l08667" name="l08667"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e7bf44f34ab51218a24b6b9467e9166"> 8667</a></span><span class="preprocessor">#define GPIO_IDR_IDR_5 GPIO_IDR_ID5</span></div>
|
||
<div class="line"><a id="l08668" name="l08668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6aa5a3c8353ab0ce15d6500baf902e8b"> 8668</a></span><span class="preprocessor">#define GPIO_IDR_IDR_6 GPIO_IDR_ID6</span></div>
|
||
<div class="line"><a id="l08669" name="l08669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeccc9232d1758570c7dd9d8733d9f5b6"> 8669</a></span><span class="preprocessor">#define GPIO_IDR_IDR_7 GPIO_IDR_ID7</span></div>
|
||
<div class="line"><a id="l08670" name="l08670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b5f3c629daa6d4dd3ace095a127f9e1"> 8670</a></span><span class="preprocessor">#define GPIO_IDR_IDR_8 GPIO_IDR_ID8</span></div>
|
||
<div class="line"><a id="l08671" name="l08671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd452f85fa151363ffbf1d263185ef0d"> 8671</a></span><span class="preprocessor">#define GPIO_IDR_IDR_9 GPIO_IDR_ID9</span></div>
|
||
<div class="line"><a id="l08672" name="l08672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff38e1078878bdd79375295e7ab829b5"> 8672</a></span><span class="preprocessor">#define GPIO_IDR_IDR_10 GPIO_IDR_ID10</span></div>
|
||
<div class="line"><a id="l08673" name="l08673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84c3f48e386abf1f6d97e4fb86cbaa7c"> 8673</a></span><span class="preprocessor">#define GPIO_IDR_IDR_11 GPIO_IDR_ID11</span></div>
|
||
<div class="line"><a id="l08674" name="l08674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec151d78711f0274d3ab5b239884e645"> 8674</a></span><span class="preprocessor">#define GPIO_IDR_IDR_12 GPIO_IDR_ID12</span></div>
|
||
<div class="line"><a id="l08675" name="l08675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6771a14a3c52f397295737e509633b05"> 8675</a></span><span class="preprocessor">#define GPIO_IDR_IDR_13 GPIO_IDR_ID13</span></div>
|
||
<div class="line"><a id="l08676" name="l08676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0b8882f4473b5d65266792ed631f0bb"> 8676</a></span><span class="preprocessor">#define GPIO_IDR_IDR_14 GPIO_IDR_ID14</span></div>
|
||
<div class="line"><a id="l08677" name="l08677"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fa9b2bca3451f0be4560333692fb5a4"> 8677</a></span><span class="preprocessor">#define GPIO_IDR_IDR_15 GPIO_IDR_ID15</span></div>
|
||
<div class="line"><a id="l08678" name="l08678"></a><span class="lineno"> 8678</span> </div>
|
||
<div class="line"><a id="l08679" name="l08679"></a><span class="lineno"> 8679</span><span class="comment">/****************** Bits definition for GPIO_ODR register *******************/</span></div>
|
||
<div class="line"><a id="l08680" name="l08680"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade6bff88e55b2428269c90ebde121d31"> 8680</a></span><span class="preprocessor">#define GPIO_ODR_OD0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l08681" name="l08681"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c08637123e42a30fbf4e9e49feb650f"> 8681</a></span><span class="preprocessor">#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) </span></div>
|
||
<div class="line"><a id="l08682" name="l08682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e7937b0a505e771361804a211c7656f"> 8682</a></span><span class="preprocessor">#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk </span></div>
|
||
<div class="line"><a id="l08683" name="l08683"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60dfdab58aa53c6790eb545f50f92722"> 8683</a></span><span class="preprocessor">#define GPIO_ODR_OD1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l08684" name="l08684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga284902fc92059f740dc599945071d767"> 8684</a></span><span class="preprocessor">#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) </span></div>
|
||
<div class="line"><a id="l08685" name="l08685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga104dff849ee2c6a0b58777a336912583"> 8685</a></span><span class="preprocessor">#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk </span></div>
|
||
<div class="line"><a id="l08686" name="l08686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ea388b190f9040a9657d9b395471596"> 8686</a></span><span class="preprocessor">#define GPIO_ODR_OD2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l08687" name="l08687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b7c3794b7948875eea27a4b09bac063"> 8687</a></span><span class="preprocessor">#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) </span></div>
|
||
<div class="line"><a id="l08688" name="l08688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff3ff4b6fa52aac52991053b26d8dd80"> 8688</a></span><span class="preprocessor">#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk </span></div>
|
||
<div class="line"><a id="l08689" name="l08689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a4ae35ae856330bc937251fd9ccf01c"> 8689</a></span><span class="preprocessor">#define GPIO_ODR_OD3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l08690" name="l08690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b3312000af1016c233b04590b8c054c"> 8690</a></span><span class="preprocessor">#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) </span></div>
|
||
<div class="line"><a id="l08691" name="l08691"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba5790d50582befba7f91037df94b159"> 8691</a></span><span class="preprocessor">#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk </span></div>
|
||
<div class="line"><a id="l08692" name="l08692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91e0a70767add938306339ea3f3c8df5"> 8692</a></span><span class="preprocessor">#define GPIO_ODR_OD4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l08693" name="l08693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab27b415dc46e3832b021eb0d697f1b13"> 8693</a></span><span class="preprocessor">#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) </span></div>
|
||
<div class="line"><a id="l08694" name="l08694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd275e221a79cf7a3ac0c98ee15af3c5"> 8694</a></span><span class="preprocessor">#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk </span></div>
|
||
<div class="line"><a id="l08695" name="l08695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada7f2c3690272b52bde0c22223d39dff"> 8695</a></span><span class="preprocessor">#define GPIO_ODR_OD5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l08696" name="l08696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga530c4cdcbeb559b2f990a237b4765631"> 8696</a></span><span class="preprocessor">#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) </span></div>
|
||
<div class="line"><a id="l08697" name="l08697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4046ad484b858f3c49eb0449f45e3af5"> 8697</a></span><span class="preprocessor">#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk </span></div>
|
||
<div class="line"><a id="l08698" name="l08698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeaffa5b5eec9c90b552ebef5fc13828a"> 8698</a></span><span class="preprocessor">#define GPIO_ODR_OD6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l08699" name="l08699"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga965661d93777219b16fee1d210831622"> 8699</a></span><span class="preprocessor">#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) </span></div>
|
||
<div class="line"><a id="l08700" name="l08700"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34550e0c5098cf24a2ab86e2ecc67c14"> 8700</a></span><span class="preprocessor">#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk </span></div>
|
||
<div class="line"><a id="l08701" name="l08701"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34bf70d7723a8e809a7ec2baba5583b1"> 8701</a></span><span class="preprocessor">#define GPIO_ODR_OD7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l08702" name="l08702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad697f4e743a67aad8ad37560a176ed25"> 8702</a></span><span class="preprocessor">#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) </span></div>
|
||
<div class="line"><a id="l08703" name="l08703"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba7559603648f95b76d128f0a637675c"> 8703</a></span><span class="preprocessor">#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk </span></div>
|
||
<div class="line"><a id="l08704" name="l08704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad52cedd015ac8e511f7f2cdda0e6c4ca"> 8704</a></span><span class="preprocessor">#define GPIO_ODR_OD8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l08705" name="l08705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacad5442c3f20d25fdb0b24d78d1eab5b"> 8705</a></span><span class="preprocessor">#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) </span></div>
|
||
<div class="line"><a id="l08706" name="l08706"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60a61ea7de95ccdcb674e8b972969a1f"> 8706</a></span><span class="preprocessor">#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk </span></div>
|
||
<div class="line"><a id="l08707" name="l08707"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41b713787d20ffacdc2c2b4f6fe05e4e"> 8707</a></span><span class="preprocessor">#define GPIO_ODR_OD9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l08708" name="l08708"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga871215a04902f7abbc8e4753aa523d87"> 8708</a></span><span class="preprocessor">#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) </span></div>
|
||
<div class="line"><a id="l08709" name="l08709"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3bfdb1e3526890736b0c1238adda99c"> 8709</a></span><span class="preprocessor">#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk </span></div>
|
||
<div class="line"><a id="l08710" name="l08710"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa47f67a9087ba57c2144a8a19d597bf5"> 8710</a></span><span class="preprocessor">#define GPIO_ODR_OD10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l08711" name="l08711"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5e3aca353a76254fd8d02debede2fae"> 8711</a></span><span class="preprocessor">#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) </span></div>
|
||
<div class="line"><a id="l08712" name="l08712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5c6ba137db2753434a1253e111ff6a2"> 8712</a></span><span class="preprocessor">#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk </span></div>
|
||
<div class="line"><a id="l08713" name="l08713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4f6824376eb5f7f0185580a780d5ecf"> 8713</a></span><span class="preprocessor">#define GPIO_ODR_OD11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l08714" name="l08714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5432eff2238e4c6adf1f5c5cda9a797d"> 8714</a></span><span class="preprocessor">#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) </span></div>
|
||
<div class="line"><a id="l08715" name="l08715"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e7e487eb914e276c92534eab7b1efdc"> 8715</a></span><span class="preprocessor">#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk </span></div>
|
||
<div class="line"><a id="l08716" name="l08716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a3eca32e4b8eca5b984c371fc118c44"> 8716</a></span><span class="preprocessor">#define GPIO_ODR_OD12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l08717" name="l08717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae85ad24a6fcfac506e330e0f896b1e23"> 8717</a></span><span class="preprocessor">#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) </span></div>
|
||
<div class="line"><a id="l08718" name="l08718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac42a77f0ced79d51a5952d929a7e0528"> 8718</a></span><span class="preprocessor">#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk </span></div>
|
||
<div class="line"><a id="l08719" name="l08719"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29598cda6568737ee82992f76d07c45c"> 8719</a></span><span class="preprocessor">#define GPIO_ODR_OD13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l08720" name="l08720"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93481785eb62b6669b8aceb1907b8e13"> 8720</a></span><span class="preprocessor">#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) </span></div>
|
||
<div class="line"><a id="l08721" name="l08721"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga582584ba2995b3b9993728b02a98f2c1"> 8721</a></span><span class="preprocessor">#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk </span></div>
|
||
<div class="line"><a id="l08722" name="l08722"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd02d3bb351676e31027d8bad0c8eb70"> 8722</a></span><span class="preprocessor">#define GPIO_ODR_OD14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l08723" name="l08723"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf028b3836cb425dab56d38dd1df17062"> 8723</a></span><span class="preprocessor">#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) </span></div>
|
||
<div class="line"><a id="l08724" name="l08724"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c2ec83ded91512630244d2d1e1c300b"> 8724</a></span><span class="preprocessor">#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk </span></div>
|
||
<div class="line"><a id="l08725" name="l08725"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3bac5a39dda0f70c8fb9de38450eb21"> 8725</a></span><span class="preprocessor">#define GPIO_ODR_OD15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l08726" name="l08726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26a07f39cf1e55d17f56df37cd875288"> 8726</a></span><span class="preprocessor">#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) </span></div>
|
||
<div class="line"><a id="l08727" name="l08727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e411f3d6f91e5218dc9ca1b6739f053"> 8727</a></span><span class="preprocessor">#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk </span></div>
|
||
<div class="line"><a id="l08728" name="l08728"></a><span class="lineno"> 8728</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l08729" name="l08729"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42386f40895bc86ff49eefe80708bbc6"> 8729</a></span><span class="preprocessor">#define GPIO_ODR_ODR_0 GPIO_ODR_OD0</span></div>
|
||
<div class="line"><a id="l08730" name="l08730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7680b11616859cd0f462703224511fb2"> 8730</a></span><span class="preprocessor">#define GPIO_ODR_ODR_1 GPIO_ODR_OD1</span></div>
|
||
<div class="line"><a id="l08731" name="l08731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae93b86fd4c1bfcfafc42bf820c17c019"> 8731</a></span><span class="preprocessor">#define GPIO_ODR_ODR_2 GPIO_ODR_OD2</span></div>
|
||
<div class="line"><a id="l08732" name="l08732"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3fffcd41fa6347ce4b61e6abbae55c7a"> 8732</a></span><span class="preprocessor">#define GPIO_ODR_ODR_3 GPIO_ODR_OD3</span></div>
|
||
<div class="line"><a id="l08733" name="l08733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9b5f55a1f9dda2285576a276d0fb0e2"> 8733</a></span><span class="preprocessor">#define GPIO_ODR_ODR_4 GPIO_ODR_OD4</span></div>
|
||
<div class="line"><a id="l08734" name="l08734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6723e4adf0b6b333f74e15e00a60a4db"> 8734</a></span><span class="preprocessor">#define GPIO_ODR_ODR_5 GPIO_ODR_OD5</span></div>
|
||
<div class="line"><a id="l08735" name="l08735"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga202234d8f40086f6343e30597b52c838"> 8735</a></span><span class="preprocessor">#define GPIO_ODR_ODR_6 GPIO_ODR_OD6</span></div>
|
||
<div class="line"><a id="l08736" name="l08736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c713b846aa56d5a31b2e4525d705679"> 8736</a></span><span class="preprocessor">#define GPIO_ODR_ODR_7 GPIO_ODR_OD7</span></div>
|
||
<div class="line"><a id="l08737" name="l08737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabe9c0b33000bbfe71f107cce0af0eb2"> 8737</a></span><span class="preprocessor">#define GPIO_ODR_ODR_8 GPIO_ODR_OD8</span></div>
|
||
<div class="line"><a id="l08738" name="l08738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25f53481a7575ebb0eb5477950673188"> 8738</a></span><span class="preprocessor">#define GPIO_ODR_ODR_9 GPIO_ODR_OD9</span></div>
|
||
<div class="line"><a id="l08739" name="l08739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e2817e62685ec81d3ca6674d8e75187"> 8739</a></span><span class="preprocessor">#define GPIO_ODR_ODR_10 GPIO_ODR_OD10</span></div>
|
||
<div class="line"><a id="l08740" name="l08740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6022058342e528d097d2d352ccb3210c"> 8740</a></span><span class="preprocessor">#define GPIO_ODR_ODR_11 GPIO_ODR_OD11</span></div>
|
||
<div class="line"><a id="l08741" name="l08741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6df2c7bfa97e4536c3c112fa6dc00992"> 8741</a></span><span class="preprocessor">#define GPIO_ODR_ODR_12 GPIO_ODR_OD12</span></div>
|
||
<div class="line"><a id="l08742" name="l08742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7a51e706f1931e6ac3ddd117242da23"> 8742</a></span><span class="preprocessor">#define GPIO_ODR_ODR_13 GPIO_ODR_OD13</span></div>
|
||
<div class="line"><a id="l08743" name="l08743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga090cea405c38fd8c48f77e561deaaa07"> 8743</a></span><span class="preprocessor">#define GPIO_ODR_ODR_14 GPIO_ODR_OD14</span></div>
|
||
<div class="line"><a id="l08744" name="l08744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga527b7d78707f17edfe826be72aa59fdc"> 8744</a></span><span class="preprocessor">#define GPIO_ODR_ODR_15 GPIO_ODR_OD15</span></div>
|
||
<div class="line"><a id="l08745" name="l08745"></a><span class="lineno"> 8745</span> </div>
|
||
<div class="line"><a id="l08746" name="l08746"></a><span class="lineno"> 8746</span><span class="comment">/****************** Bits definition for GPIO_BSRR register ******************/</span></div>
|
||
<div class="line"><a id="l08747" name="l08747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga409d8650af1aa0e1958cc1ed2f96acda"> 8747</a></span><span class="preprocessor">#define GPIO_BSRR_BS0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l08748" name="l08748"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga758aadb3c036759a162542216f98fcbc"> 8748</a></span><span class="preprocessor">#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) </span></div>
|
||
<div class="line"><a id="l08749" name="l08749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bdfbe2a618de42c420de923b2f8507d"> 8749</a></span><span class="preprocessor">#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk </span></div>
|
||
<div class="line"><a id="l08750" name="l08750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7457f610b20ffdd73c97d90724ed4d4e"> 8750</a></span><span class="preprocessor">#define GPIO_BSRR_BS1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l08751" name="l08751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga875bc62855425da548fa2f68d3be0f49"> 8751</a></span><span class="preprocessor">#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) </span></div>
|
||
<div class="line"><a id="l08752" name="l08752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga316604d9223fee0c0591b58bd42b5f51"> 8752</a></span><span class="preprocessor">#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk </span></div>
|
||
<div class="line"><a id="l08753" name="l08753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3af1acce0c96a515284b6f8bd12b8436"> 8753</a></span><span class="preprocessor">#define GPIO_BSRR_BS2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l08754" name="l08754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0d718587115b4b07190c9ade21789ac"> 8754</a></span><span class="preprocessor">#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) </span></div>
|
||
<div class="line"><a id="l08755" name="l08755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc89617a25217236b94eec1fd93891cb"> 8755</a></span><span class="preprocessor">#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk </span></div>
|
||
<div class="line"><a id="l08756" name="l08756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0837604e1baac4b8b86fc3e660b17ad"> 8756</a></span><span class="preprocessor">#define GPIO_BSRR_BS3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l08757" name="l08757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8d8114b4db83d01096d0337750d3099"> 8757</a></span><span class="preprocessor">#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) </span></div>
|
||
<div class="line"><a id="l08758" name="l08758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79e5ac9ace2d797ecfcc3d633c7ca52f"> 8758</a></span><span class="preprocessor">#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk </span></div>
|
||
<div class="line"><a id="l08759" name="l08759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae421b6676ce8b2865cbb6e15fc45d495"> 8759</a></span><span class="preprocessor">#define GPIO_BSRR_BS4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l08760" name="l08760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0331d270ba3fe6bad1f3353ed09194bf"> 8760</a></span><span class="preprocessor">#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) </span></div>
|
||
<div class="line"><a id="l08761" name="l08761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga692f3966c5260fd55f3bb09829f69e75"> 8761</a></span><span class="preprocessor">#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk </span></div>
|
||
<div class="line"><a id="l08762" name="l08762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad686100d76807920229b49d233cbd96d"> 8762</a></span><span class="preprocessor">#define GPIO_BSRR_BS5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l08763" name="l08763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga502f44e296cddc2c4099ab7e7e9b11d8"> 8763</a></span><span class="preprocessor">#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) </span></div>
|
||
<div class="line"><a id="l08764" name="l08764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ea824455e136eee60ec17f42dabab0b"> 8764</a></span><span class="preprocessor">#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk </span></div>
|
||
<div class="line"><a id="l08765" name="l08765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91f4268de41bba2e411879d3fa900af7"> 8765</a></span><span class="preprocessor">#define GPIO_BSRR_BS6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l08766" name="l08766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8d6a22635cfd41987e341af34b87a63"> 8766</a></span><span class="preprocessor">#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) </span></div>
|
||
<div class="line"><a id="l08767" name="l08767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69b3333e39824fde00bc36b181de3929"> 8767</a></span><span class="preprocessor">#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk </span></div>
|
||
<div class="line"><a id="l08768" name="l08768"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d1dd4ddac06be768bb7727bcb657081"> 8768</a></span><span class="preprocessor">#define GPIO_BSRR_BS7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l08769" name="l08769"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga635b08b445669748e8fadbcb0d2481e6"> 8769</a></span><span class="preprocessor">#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) </span></div>
|
||
<div class="line"><a id="l08770" name="l08770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9836771d1c021b9b7350fd3c3d544b0"> 8770</a></span><span class="preprocessor">#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk </span></div>
|
||
<div class="line"><a id="l08771" name="l08771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga595b5fd07dcafd23fd6ed6e23cb43b5a"> 8771</a></span><span class="preprocessor">#define GPIO_BSRR_BS8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l08772" name="l08772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga765d016146d30e6112499598959a948a"> 8772</a></span><span class="preprocessor">#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) </span></div>
|
||
<div class="line"><a id="l08773" name="l08773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c295b6482aa91ef51198e570166f60f"> 8773</a></span><span class="preprocessor">#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk </span></div>
|
||
<div class="line"><a id="l08774" name="l08774"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab415c303400428fa585419e57aa2513d"> 8774</a></span><span class="preprocessor">#define GPIO_BSRR_BS9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l08775" name="l08775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e1f12d75678bb5d295b8f77d5db15a0"> 8775</a></span><span class="preprocessor">#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) </span></div>
|
||
<div class="line"><a id="l08776" name="l08776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49258fbb201ec8e332b248bbd0370b07"> 8776</a></span><span class="preprocessor">#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk </span></div>
|
||
<div class="line"><a id="l08777" name="l08777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf85195c9fb5642687151366b0f363441"> 8777</a></span><span class="preprocessor">#define GPIO_BSRR_BS10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l08778" name="l08778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a8f9979581623c5ee8a3b16be563cd1"> 8778</a></span><span class="preprocessor">#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) </span></div>
|
||
<div class="line"><a id="l08779" name="l08779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbe42933da56edaa62f89d6fb5093b32"> 8779</a></span><span class="preprocessor">#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk </span></div>
|
||
<div class="line"><a id="l08780" name="l08780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f79cf6b45de75813ed9d2af64f0d91b"> 8780</a></span><span class="preprocessor">#define GPIO_BSRR_BS11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l08781" name="l08781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d224601eb9ec2476451efe136693769"> 8781</a></span><span class="preprocessor">#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) </span></div>
|
||
<div class="line"><a id="l08782" name="l08782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71b06aba868da67827335c823cde772c"> 8782</a></span><span class="preprocessor">#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk </span></div>
|
||
<div class="line"><a id="l08783" name="l08783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4302c8e25dd2711d37262b73865f3c19"> 8783</a></span><span class="preprocessor">#define GPIO_BSRR_BS12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l08784" name="l08784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cc01661d2dec2e9dd4b02528e271393"> 8784</a></span><span class="preprocessor">#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) </span></div>
|
||
<div class="line"><a id="l08785" name="l08785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34dec3bc91096fccb3339f2d6d181846"> 8785</a></span><span class="preprocessor">#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk </span></div>
|
||
<div class="line"><a id="l08786" name="l08786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fe11d923932261f904c089da78e7ebc"> 8786</a></span><span class="preprocessor">#define GPIO_BSRR_BS13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l08787" name="l08787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed57c94725261a35387ef04c9675cdbe"> 8787</a></span><span class="preprocessor">#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) </span></div>
|
||
<div class="line"><a id="l08788" name="l08788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ea853befe5a2a238f0e0fe5d6c41b9c"> 8788</a></span><span class="preprocessor">#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk </span></div>
|
||
<div class="line"><a id="l08789" name="l08789"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c86de2a9b2e7394040a65bf114131bc"> 8789</a></span><span class="preprocessor">#define GPIO_BSRR_BS14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l08790" name="l08790"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeaaedec226989e8048f5cbde2de6c1c5"> 8790</a></span><span class="preprocessor">#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) </span></div>
|
||
<div class="line"><a id="l08791" name="l08791"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24e32d8f8af43a171ed1a4c7eb202d17"> 8791</a></span><span class="preprocessor">#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk </span></div>
|
||
<div class="line"><a id="l08792" name="l08792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae93dccdbf7e8ef41da1b847975cf0eac"> 8792</a></span><span class="preprocessor">#define GPIO_BSRR_BS15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l08793" name="l08793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab40b26153e5c50ae45ebc6deb06cc0fb"> 8793</a></span><span class="preprocessor">#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) </span></div>
|
||
<div class="line"><a id="l08794" name="l08794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8427fb5c9074e51fbf27480a6a65a80"> 8794</a></span><span class="preprocessor">#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk </span></div>
|
||
<div class="line"><a id="l08795" name="l08795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b9e4440bb44a4ab919e9a0171af788b"> 8795</a></span><span class="preprocessor">#define GPIO_BSRR_BR0_Pos (16U) </span></div>
|
||
<div class="line"><a id="l08796" name="l08796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6ca69cbc7e23bf313dda10288ce21f5"> 8796</a></span><span class="preprocessor">#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) </span></div>
|
||
<div class="line"><a id="l08797" name="l08797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44316fb208a551d63550ab435a65faaf"> 8797</a></span><span class="preprocessor">#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk </span></div>
|
||
<div class="line"><a id="l08798" name="l08798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga075d239db694cea8f30c70534ddf7be9"> 8798</a></span><span class="preprocessor">#define GPIO_BSRR_BR1_Pos (17U) </span></div>
|
||
<div class="line"><a id="l08799" name="l08799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9890be2a151b0b31119eba03b36b9df"> 8799</a></span><span class="preprocessor">#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) </span></div>
|
||
<div class="line"><a id="l08800" name="l08800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga855ce6a1019d453bd1fbe9f61b5531b8"> 8800</a></span><span class="preprocessor">#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk </span></div>
|
||
<div class="line"><a id="l08801" name="l08801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c5825e38ef02071bf0d888ab636d241"> 8801</a></span><span class="preprocessor">#define GPIO_BSRR_BR2_Pos (18U) </span></div>
|
||
<div class="line"><a id="l08802" name="l08802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca8d1db9b985749bcdcc4f83d80e25b1"> 8802</a></span><span class="preprocessor">#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) </span></div>
|
||
<div class="line"><a id="l08803" name="l08803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ac2103861a8ab0c8c8fed5e3bf7db0a"> 8803</a></span><span class="preprocessor">#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk </span></div>
|
||
<div class="line"><a id="l08804" name="l08804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ef6b53609ca5d188a6916d8574d6030"> 8804</a></span><span class="preprocessor">#define GPIO_BSRR_BR3_Pos (19U) </span></div>
|
||
<div class="line"><a id="l08805" name="l08805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7045c8361aeed94f72ed591c604d1f1"> 8805</a></span><span class="preprocessor">#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) </span></div>
|
||
<div class="line"><a id="l08806" name="l08806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf256a26094e33026f7f575f04d0e05c9"> 8806</a></span><span class="preprocessor">#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk </span></div>
|
||
<div class="line"><a id="l08807" name="l08807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71bbd49dad3b3dcd6ecb60b0fb1fa8eb"> 8807</a></span><span class="preprocessor">#define GPIO_BSRR_BR4_Pos (20U) </span></div>
|
||
<div class="line"><a id="l08808" name="l08808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94341de3b04731a0df5c530c572dad7f"> 8808</a></span><span class="preprocessor">#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) </span></div>
|
||
<div class="line"><a id="l08809" name="l08809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac84f66118397bb661ad9edfdd50432f0"> 8809</a></span><span class="preprocessor">#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk </span></div>
|
||
<div class="line"><a id="l08810" name="l08810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa565b7acd495e70be1b68204ef2910db"> 8810</a></span><span class="preprocessor">#define GPIO_BSRR_BR5_Pos (21U) </span></div>
|
||
<div class="line"><a id="l08811" name="l08811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d366ba8f09d9211e25c5e76b56a91af"> 8811</a></span><span class="preprocessor">#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) </span></div>
|
||
<div class="line"><a id="l08812" name="l08812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09a777f006ef68641e80110f20117a8d"> 8812</a></span><span class="preprocessor">#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk </span></div>
|
||
<div class="line"><a id="l08813" name="l08813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafce8dd4c2ed3764a234fc40ad192ae03"> 8813</a></span><span class="preprocessor">#define GPIO_BSRR_BR6_Pos (22U) </span></div>
|
||
<div class="line"><a id="l08814" name="l08814"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga354a942cded8f779316613b5a73b71ad"> 8814</a></span><span class="preprocessor">#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) </span></div>
|
||
<div class="line"><a id="l08815" name="l08815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8695c8bfcc32bda2806805339db1e8ce"> 8815</a></span><span class="preprocessor">#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk </span></div>
|
||
<div class="line"><a id="l08816" name="l08816"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34e114c3d131dbb2abc05837b9c20fff"> 8816</a></span><span class="preprocessor">#define GPIO_BSRR_BR7_Pos (23U) </span></div>
|
||
<div class="line"><a id="l08817" name="l08817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b90d1d54ad1a0def096663cfe9cbd74"> 8817</a></span><span class="preprocessor">#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) </span></div>
|
||
<div class="line"><a id="l08818" name="l08818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba577e8f2650976f219ad7ad93244f8a"> 8818</a></span><span class="preprocessor">#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk </span></div>
|
||
<div class="line"><a id="l08819" name="l08819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadebc6e8a656a3adbff46f398b5bcb3d4"> 8819</a></span><span class="preprocessor">#define GPIO_BSRR_BR8_Pos (24U) </span></div>
|
||
<div class="line"><a id="l08820" name="l08820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5460b708647c1a9f742c0ff0d5bcb17b"> 8820</a></span><span class="preprocessor">#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) </span></div>
|
||
<div class="line"><a id="l08821" name="l08821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaedbc146cc7659d51bc5f472d3a405ee"> 8821</a></span><span class="preprocessor">#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk </span></div>
|
||
<div class="line"><a id="l08822" name="l08822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13d98b977fc86581e566299bd363176d"> 8822</a></span><span class="preprocessor">#define GPIO_BSRR_BR9_Pos (25U) </span></div>
|
||
<div class="line"><a id="l08823" name="l08823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4aa6d3943ec6a8d96dd855f436ab8e19"> 8823</a></span><span class="preprocessor">#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) </span></div>
|
||
<div class="line"><a id="l08824" name="l08824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3e0c779115c59cb98e021ede5605df3"> 8824</a></span><span class="preprocessor">#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk </span></div>
|
||
<div class="line"><a id="l08825" name="l08825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga968f494c3928ba28bfa7c87da5f2cbaa"> 8825</a></span><span class="preprocessor">#define GPIO_BSRR_BR10_Pos (26U) </span></div>
|
||
<div class="line"><a id="l08826" name="l08826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3f93f6e94ae0d842e5b0cda9ba6a1cd"> 8826</a></span><span class="preprocessor">#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) </span></div>
|
||
<div class="line"><a id="l08827" name="l08827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98581ac23be9f4fa003686d2ea523a81"> 8827</a></span><span class="preprocessor">#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk </span></div>
|
||
<div class="line"><a id="l08828" name="l08828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b421b338b145649e8937806472a59c6"> 8828</a></span><span class="preprocessor">#define GPIO_BSRR_BR11_Pos (27U) </span></div>
|
||
<div class="line"><a id="l08829" name="l08829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f483f67fbc5614c010aa147e9ce6b3f"> 8829</a></span><span class="preprocessor">#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) </span></div>
|
||
<div class="line"><a id="l08830" name="l08830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacedacd6c3e840a8172269cac3dbb550b"> 8830</a></span><span class="preprocessor">#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk </span></div>
|
||
<div class="line"><a id="l08831" name="l08831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79f141572b1c065dcabbc7ddfe4092f2"> 8831</a></span><span class="preprocessor">#define GPIO_BSRR_BR12_Pos (28U) </span></div>
|
||
<div class="line"><a id="l08832" name="l08832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa10f5ee9aeb2eefb25fd195e472c0de8"> 8832</a></span><span class="preprocessor">#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) </span></div>
|
||
<div class="line"><a id="l08833" name="l08833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4622e78de418b59cd4199928801b6958"> 8833</a></span><span class="preprocessor">#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk </span></div>
|
||
<div class="line"><a id="l08834" name="l08834"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53a07a77a4bb0457b13abfee48ed3e39"> 8834</a></span><span class="preprocessor">#define GPIO_BSRR_BR13_Pos (29U) </span></div>
|
||
<div class="line"><a id="l08835" name="l08835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d000805bb6f4ad68ec73159df771422"> 8835</a></span><span class="preprocessor">#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) </span></div>
|
||
<div class="line"><a id="l08836" name="l08836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga292c1d0172620e0454ccc36f91f0c6ea"> 8836</a></span><span class="preprocessor">#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk </span></div>
|
||
<div class="line"><a id="l08837" name="l08837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e6b3f0c1a866cd39319f28cacbb768e"> 8837</a></span><span class="preprocessor">#define GPIO_BSRR_BR14_Pos (30U) </span></div>
|
||
<div class="line"><a id="l08838" name="l08838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ad1816ec382b6ef6e952cef1408933f"> 8838</a></span><span class="preprocessor">#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) </span></div>
|
||
<div class="line"><a id="l08839" name="l08839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32477ac5ab4f5c7257ca332bb691b7cf"> 8839</a></span><span class="preprocessor">#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk </span></div>
|
||
<div class="line"><a id="l08840" name="l08840"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30d885f9a72889c6f1070b6da4d4d782"> 8840</a></span><span class="preprocessor">#define GPIO_BSRR_BR15_Pos (31U) </span></div>
|
||
<div class="line"><a id="l08841" name="l08841"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8c00dff452eea9a285e36a81c5abd79"> 8841</a></span><span class="preprocessor">#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) </span></div>
|
||
<div class="line"><a id="l08842" name="l08842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c6d612adeaae9b26d0ea4af74ffe1cd"> 8842</a></span><span class="preprocessor">#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk </span></div>
|
||
<div class="line"><a id="l08843" name="l08843"></a><span class="lineno"> 8843</span> </div>
|
||
<div class="line"><a id="l08844" name="l08844"></a><span class="lineno"> 8844</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l08845" name="l08845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b69748fd2f5e2890e784bc0970b31d5"> 8845</a></span><span class="preprocessor">#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0</span></div>
|
||
<div class="line"><a id="l08846" name="l08846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa887cd170c757a2954ae8384908d030a"> 8846</a></span><span class="preprocessor">#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1</span></div>
|
||
<div class="line"><a id="l08847" name="l08847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa59c6fcfc63587ebe3cbf640cc74776a"> 8847</a></span><span class="preprocessor">#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2</span></div>
|
||
<div class="line"><a id="l08848" name="l08848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac41aaeaf32b8837f8f6e29e09ed92152"> 8848</a></span><span class="preprocessor">#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3</span></div>
|
||
<div class="line"><a id="l08849" name="l08849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga002773af2697ddca1bac26831cfbf231"> 8849</a></span><span class="preprocessor">#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4</span></div>
|
||
<div class="line"><a id="l08850" name="l08850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9f2671eae81f28d0054b62ca5e2f763"> 8850</a></span><span class="preprocessor">#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5</span></div>
|
||
<div class="line"><a id="l08851" name="l08851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5dab92d27518649b3807aa4c8ef376b6"> 8851</a></span><span class="preprocessor">#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6</span></div>
|
||
<div class="line"><a id="l08852" name="l08852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac4945b022950bdb9570e744279a0dd6"> 8852</a></span><span class="preprocessor">#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7</span></div>
|
||
<div class="line"><a id="l08853" name="l08853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga648026b2f11d992bb0e3383644be4eb9"> 8853</a></span><span class="preprocessor">#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8</span></div>
|
||
<div class="line"><a id="l08854" name="l08854"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9db2ccea6361f65c6bf156aa57cd4b88"> 8854</a></span><span class="preprocessor">#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9</span></div>
|
||
<div class="line"><a id="l08855" name="l08855"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa58e335b962fc81af70d19dbd09d9137"> 8855</a></span><span class="preprocessor">#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10</span></div>
|
||
<div class="line"><a id="l08856" name="l08856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5744153a68c73330e2ebe9a9a0ef8036"> 8856</a></span><span class="preprocessor">#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11</span></div>
|
||
<div class="line"><a id="l08857" name="l08857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78652a72a05249db1d343735d1764208"> 8857</a></span><span class="preprocessor">#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12</span></div>
|
||
<div class="line"><a id="l08858" name="l08858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6367e64393bc954efa6fdce80e94f1be"> 8858</a></span><span class="preprocessor">#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13</span></div>
|
||
<div class="line"><a id="l08859" name="l08859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8c5c56ab4bc16dd7341203c73899e41"> 8859</a></span><span class="preprocessor">#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14</span></div>
|
||
<div class="line"><a id="l08860" name="l08860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66c0c77c304415bdccf47a0f08b58e4d"> 8860</a></span><span class="preprocessor">#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15</span></div>
|
||
<div class="line"><a id="l08861" name="l08861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga831554de814ae2941c7f527ed6b0a742"> 8861</a></span><span class="preprocessor">#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0</span></div>
|
||
<div class="line"><a id="l08862" name="l08862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cf488fcb38fc660f7e3d1820a12ae07"> 8862</a></span><span class="preprocessor">#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1</span></div>
|
||
<div class="line"><a id="l08863" name="l08863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fe0f9386b50b899fdf1f9008c54f893"> 8863</a></span><span class="preprocessor">#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2</span></div>
|
||
<div class="line"><a id="l08864" name="l08864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42b377f0c5f564fb39480afe43ee8796"> 8864</a></span><span class="preprocessor">#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3</span></div>
|
||
<div class="line"><a id="l08865" name="l08865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab723c0327da5fb41fe366416b7d61d88"> 8865</a></span><span class="preprocessor">#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4</span></div>
|
||
<div class="line"><a id="l08866" name="l08866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d6d8644953029e183eda4404fe9bd27"> 8866</a></span><span class="preprocessor">#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5</span></div>
|
||
<div class="line"><a id="l08867" name="l08867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59e4a03667e8a750fd2e775edc44ecbe"> 8867</a></span><span class="preprocessor">#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6</span></div>
|
||
<div class="line"><a id="l08868" name="l08868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafca85d377fe820e5099d870342d634a8"> 8868</a></span><span class="preprocessor">#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7</span></div>
|
||
<div class="line"><a id="l08869" name="l08869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab02c6e6e879085fd8912facf86d822cd"> 8869</a></span><span class="preprocessor">#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8</span></div>
|
||
<div class="line"><a id="l08870" name="l08870"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47ff03b3d52a7f40ae15cc167b34cc58"> 8870</a></span><span class="preprocessor">#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9</span></div>
|
||
<div class="line"><a id="l08871" name="l08871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c14a1c84cc91ff1d21b6802cda7d7ef"> 8871</a></span><span class="preprocessor">#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10</span></div>
|
||
<div class="line"><a id="l08872" name="l08872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga498185a76dcc2305113c5d168c2844d9"> 8872</a></span><span class="preprocessor">#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11</span></div>
|
||
<div class="line"><a id="l08873" name="l08873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga222460b26eaba7d333bb4d4ae9426aff"> 8873</a></span><span class="preprocessor">#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12</span></div>
|
||
<div class="line"><a id="l08874" name="l08874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca2dc3bd09745f8de6c6788fb1d106af"> 8874</a></span><span class="preprocessor">#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13</span></div>
|
||
<div class="line"><a id="l08875" name="l08875"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67c96f72bdd15516e22097a3a3dad5f1"> 8875</a></span><span class="preprocessor">#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14</span></div>
|
||
<div class="line"><a id="l08876" name="l08876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6eaa59f6afa3fcebaf2a27c31ae38544"> 8876</a></span><span class="preprocessor">#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15</span></div>
|
||
<div class="line"><a id="l08877" name="l08877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8acd11feb4223a7ca438effb3d926fc"> 8877</a></span><span class="preprocessor">#define GPIO_BRR_BR0 GPIO_BSRR_BR0</span></div>
|
||
<div class="line"><a id="l08878" name="l08878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4adfe8c79c3cf7e0fb7e8714ae15adf"> 8878</a></span><span class="preprocessor">#define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos</span></div>
|
||
<div class="line"><a id="l08879" name="l08879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8094099cbec15df24976405da11376f"> 8879</a></span><span class="preprocessor">#define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk</span></div>
|
||
<div class="line"><a id="l08880" name="l08880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68f94e96c502467ad528983494cb6645"> 8880</a></span><span class="preprocessor">#define GPIO_BRR_BR1 GPIO_BSRR_BR1</span></div>
|
||
<div class="line"><a id="l08881" name="l08881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga483e475a913145601000fc57ef63afcd"> 8881</a></span><span class="preprocessor">#define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos</span></div>
|
||
<div class="line"><a id="l08882" name="l08882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad742debac1d7e18afd61fda41eda1454"> 8882</a></span><span class="preprocessor">#define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk</span></div>
|
||
<div class="line"><a id="l08883" name="l08883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeebe4dddede0f14e00885b70c09bbd09"> 8883</a></span><span class="preprocessor">#define GPIO_BRR_BR2 GPIO_BSRR_BR2</span></div>
|
||
<div class="line"><a id="l08884" name="l08884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb13164bb973d1a4591ca626903e66b7"> 8884</a></span><span class="preprocessor">#define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos</span></div>
|
||
<div class="line"><a id="l08885" name="l08885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91d9b343fe4038316557b5665ad90895"> 8885</a></span><span class="preprocessor">#define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk</span></div>
|
||
<div class="line"><a id="l08886" name="l08886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95b3047fcdfe9269f5a94b6412ec6a3c"> 8886</a></span><span class="preprocessor">#define GPIO_BRR_BR3 GPIO_BSRR_BR3</span></div>
|
||
<div class="line"><a id="l08887" name="l08887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac814288cc968b01d3e7ee1b6d340a8dd"> 8887</a></span><span class="preprocessor">#define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos</span></div>
|
||
<div class="line"><a id="l08888" name="l08888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59b86cdd805087a6aa27886a1c8f3f64"> 8888</a></span><span class="preprocessor">#define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk</span></div>
|
||
<div class="line"><a id="l08889" name="l08889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fc7d79f0103f892f8c3a87d8038525a"> 8889</a></span><span class="preprocessor">#define GPIO_BRR_BR4 GPIO_BSRR_BR4</span></div>
|
||
<div class="line"><a id="l08890" name="l08890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9f7fabe9e3187ac070c2ed6e4ae7725"> 8890</a></span><span class="preprocessor">#define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos</span></div>
|
||
<div class="line"><a id="l08891" name="l08891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84709afb9f2b311db9916987f5b62803"> 8891</a></span><span class="preprocessor">#define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk</span></div>
|
||
<div class="line"><a id="l08892" name="l08892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cc7663eaa1496185041af93b4ff808b"> 8892</a></span><span class="preprocessor">#define GPIO_BRR_BR5 GPIO_BSRR_BR5</span></div>
|
||
<div class="line"><a id="l08893" name="l08893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b24f01f67db366ff6adf86f5f940669"> 8893</a></span><span class="preprocessor">#define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos</span></div>
|
||
<div class="line"><a id="l08894" name="l08894"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50fd21ca329283e8f79675f8195d6a7e"> 8894</a></span><span class="preprocessor">#define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk</span></div>
|
||
<div class="line"><a id="l08895" name="l08895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa84d5cb9d0a0a945389ad0fef07eb2a"> 8895</a></span><span class="preprocessor">#define GPIO_BRR_BR6 GPIO_BSRR_BR6</span></div>
|
||
<div class="line"><a id="l08896" name="l08896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22e8aaa7e05c2f824d6fc1ae83f04913"> 8896</a></span><span class="preprocessor">#define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos</span></div>
|
||
<div class="line"><a id="l08897" name="l08897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae29f8525d511f39db8b6ac9efbae9ecc"> 8897</a></span><span class="preprocessor">#define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk</span></div>
|
||
<div class="line"><a id="l08898" name="l08898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5110afe1f5bda4fde7983b447ce162c4"> 8898</a></span><span class="preprocessor">#define GPIO_BRR_BR7 GPIO_BSRR_BR7</span></div>
|
||
<div class="line"><a id="l08899" name="l08899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga321d9cc2bc9fd4601694780ac4fcc7f6"> 8899</a></span><span class="preprocessor">#define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos</span></div>
|
||
<div class="line"><a id="l08900" name="l08900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae40c636136e51fffad265559938cb9f0"> 8900</a></span><span class="preprocessor">#define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk</span></div>
|
||
<div class="line"><a id="l08901" name="l08901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1560a3457fcec47c6f1871cf225557e"> 8901</a></span><span class="preprocessor">#define GPIO_BRR_BR8 GPIO_BSRR_BR8</span></div>
|
||
<div class="line"><a id="l08902" name="l08902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf45a746e5bb2a1c132093a2844d22683"> 8902</a></span><span class="preprocessor">#define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos</span></div>
|
||
<div class="line"><a id="l08903" name="l08903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9cd1191844e03a1aa271bd08e608e77"> 8903</a></span><span class="preprocessor">#define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk</span></div>
|
||
<div class="line"><a id="l08904" name="l08904"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga248ac798aa8fdd42573fa6ff4762ba58"> 8904</a></span><span class="preprocessor">#define GPIO_BRR_BR9 GPIO_BSRR_BR9</span></div>
|
||
<div class="line"><a id="l08905" name="l08905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84ae3878f9088d349453430a79e26810"> 8905</a></span><span class="preprocessor">#define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos</span></div>
|
||
<div class="line"><a id="l08906" name="l08906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0621db455e4164529a8e632bb413055d"> 8906</a></span><span class="preprocessor">#define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk</span></div>
|
||
<div class="line"><a id="l08907" name="l08907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fe20398333e9f7e5c247e0bcfcd1d31"> 8907</a></span><span class="preprocessor">#define GPIO_BRR_BR10 GPIO_BSRR_BR10</span></div>
|
||
<div class="line"><a id="l08908" name="l08908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08c89c18c00e1747d1392245f4fdeb19"> 8908</a></span><span class="preprocessor">#define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos</span></div>
|
||
<div class="line"><a id="l08909" name="l08909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga079add3e90617726dd8748c74abaf023"> 8909</a></span><span class="preprocessor">#define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk</span></div>
|
||
<div class="line"><a id="l08910" name="l08910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac65c4bf495800254168edce220f12294"> 8910</a></span><span class="preprocessor">#define GPIO_BRR_BR11 GPIO_BSRR_BR11</span></div>
|
||
<div class="line"><a id="l08911" name="l08911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a92027f04f25fd1b7ec7ad660052b42"> 8911</a></span><span class="preprocessor">#define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos</span></div>
|
||
<div class="line"><a id="l08912" name="l08912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad2be9a16fb6670ebb3492795bf6866a"> 8912</a></span><span class="preprocessor">#define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk</span></div>
|
||
<div class="line"><a id="l08913" name="l08913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga443c4943581f7590d706b183fb47250e"> 8913</a></span><span class="preprocessor">#define GPIO_BRR_BR12 GPIO_BSRR_BR12</span></div>
|
||
<div class="line"><a id="l08914" name="l08914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga372754b6a71cbf3d09b959b2eef5fa7f"> 8914</a></span><span class="preprocessor">#define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos</span></div>
|
||
<div class="line"><a id="l08915" name="l08915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed3507b082d551500536f8c0c3929dca"> 8915</a></span><span class="preprocessor">#define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk</span></div>
|
||
<div class="line"><a id="l08916" name="l08916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41f1e586a459fe54089921daed6b99cc"> 8916</a></span><span class="preprocessor">#define GPIO_BRR_BR13 GPIO_BSRR_BR13</span></div>
|
||
<div class="line"><a id="l08917" name="l08917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2dd4f25b9a855fb50ddc394a2384ccf2"> 8917</a></span><span class="preprocessor">#define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos</span></div>
|
||
<div class="line"><a id="l08918" name="l08918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53217d2a5609f35d6b029a5e1eaf2e5f"> 8918</a></span><span class="preprocessor">#define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk</span></div>
|
||
<div class="line"><a id="l08919" name="l08919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a77aa07922b7541f1e1c936a6651713"> 8919</a></span><span class="preprocessor">#define GPIO_BRR_BR14 GPIO_BSRR_BR14</span></div>
|
||
<div class="line"><a id="l08920" name="l08920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10e2ac4dac68a55a7c574736a2964312"> 8920</a></span><span class="preprocessor">#define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos</span></div>
|
||
<div class="line"><a id="l08921" name="l08921"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga239abb28695da394a23f119ddd5aa724"> 8921</a></span><span class="preprocessor">#define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk</span></div>
|
||
<div class="line"><a id="l08922" name="l08922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2ab1e0d0902e871836ae13d70c566df"> 8922</a></span><span class="preprocessor">#define GPIO_BRR_BR15 GPIO_BSRR_BR15</span></div>
|
||
<div class="line"><a id="l08923" name="l08923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d13b2c8e758203e32008267734f961f"> 8923</a></span><span class="preprocessor">#define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos</span></div>
|
||
<div class="line"><a id="l08924" name="l08924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga032413396d570a1f3041385e84ab009e"> 8924</a></span><span class="preprocessor">#define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk </span></div>
|
||
<div class="line"><a id="l08925" name="l08925"></a><span class="lineno"> 8925</span><span class="comment">/****************** Bit definition for GPIO_LCKR register *********************/</span></div>
|
||
<div class="line"><a id="l08926" name="l08926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a97048a23afc262b30fc9d0a4cb65bc"> 8926</a></span><span class="preprocessor">#define GPIO_LCKR_LCK0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l08927" name="l08927"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b01ced29f1324ec2711a784f35504dd"> 8927</a></span><span class="preprocessor">#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) </span></div>
|
||
<div class="line"><a id="l08928" name="l08928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6ae6b6d787a6af758bfde54b6ae934f"> 8928</a></span><span class="preprocessor">#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk </span></div>
|
||
<div class="line"><a id="l08929" name="l08929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94100a3d7d43a5b8718aea76e31279a7"> 8929</a></span><span class="preprocessor">#define GPIO_LCKR_LCK1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l08930" name="l08930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4780ec15743062227ad0808efb16d633"> 8930</a></span><span class="preprocessor">#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) </span></div>
|
||
<div class="line"><a id="l08931" name="l08931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga627d088ded79e6da761eaa880582372a"> 8931</a></span><span class="preprocessor">#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk </span></div>
|
||
<div class="line"><a id="l08932" name="l08932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96d48b0834c3898e74309980020f88a3"> 8932</a></span><span class="preprocessor">#define GPIO_LCKR_LCK2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l08933" name="l08933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc8315e9687b2a21a55a2abe39d42fdf"> 8933</a></span><span class="preprocessor">#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) </span></div>
|
||
<div class="line"><a id="l08934" name="l08934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5a17a7348d45dbe2b2ea41a0908d7de"> 8934</a></span><span class="preprocessor">#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk </span></div>
|
||
<div class="line"><a id="l08935" name="l08935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga348f1d0358ea70f6a7dc2a00a1c519bf"> 8935</a></span><span class="preprocessor">#define GPIO_LCKR_LCK3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l08936" name="l08936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f2a02d88e51b603d4b80078ccf691e0"> 8936</a></span><span class="preprocessor">#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) </span></div>
|
||
<div class="line"><a id="l08937" name="l08937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1597c1b50d32ed0229c38811656ba402"> 8937</a></span><span class="preprocessor">#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk </span></div>
|
||
<div class="line"><a id="l08938" name="l08938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fd29e0757ed2bc8e3935d17960b68df"> 8938</a></span><span class="preprocessor">#define GPIO_LCKR_LCK4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l08939" name="l08939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6c6dff29eb48ca0a5f6da2bc0bf3639"> 8939</a></span><span class="preprocessor">#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) </span></div>
|
||
<div class="line"><a id="l08940" name="l08940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga723577475747d2405d86b1ab28767cb5"> 8940</a></span><span class="preprocessor">#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk </span></div>
|
||
<div class="line"><a id="l08941" name="l08941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07f73a37145ff6709a20081d329900c2"> 8941</a></span><span class="preprocessor">#define GPIO_LCKR_LCK5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l08942" name="l08942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc6ac7aca22480f300049102d2b1c4be"> 8942</a></span><span class="preprocessor">#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) </span></div>
|
||
<div class="line"><a id="l08943" name="l08943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c2446bfe50cbd04617496c30eda6c18"> 8943</a></span><span class="preprocessor">#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk </span></div>
|
||
<div class="line"><a id="l08944" name="l08944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga456193c04a296b05ad87aa0f8e51c144"> 8944</a></span><span class="preprocessor">#define GPIO_LCKR_LCK6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l08945" name="l08945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga083a590c26723e38ae5d7fd77e23809c"> 8945</a></span><span class="preprocessor">#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) </span></div>
|
||
<div class="line"><a id="l08946" name="l08946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga606249f4cc3ac14cf8133b76f3c7edd7"> 8946</a></span><span class="preprocessor">#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk </span></div>
|
||
<div class="line"><a id="l08947" name="l08947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9c741b163a1b1e23b05432f866544f4"> 8947</a></span><span class="preprocessor">#define GPIO_LCKR_LCK7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l08948" name="l08948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b322ee1833e0c7d369127406b5ea90e"> 8948</a></span><span class="preprocessor">#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) </span></div>
|
||
<div class="line"><a id="l08949" name="l08949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf998da536594af780718084cee0d22a4"> 8949</a></span><span class="preprocessor">#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk </span></div>
|
||
<div class="line"><a id="l08950" name="l08950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9a02f2ef3023a1c82f04391fcb79859"> 8950</a></span><span class="preprocessor">#define GPIO_LCKR_LCK8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l08951" name="l08951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0e44a9155de4980cdb0f8c4d3afc43e"> 8951</a></span><span class="preprocessor">#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) </span></div>
|
||
<div class="line"><a id="l08952" name="l08952"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab00a81afcf4d92f6f5644724803b7404"> 8952</a></span><span class="preprocessor">#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk </span></div>
|
||
<div class="line"><a id="l08953" name="l08953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga821f9dc79420f84e79fe2697addf1d42"> 8953</a></span><span class="preprocessor">#define GPIO_LCKR_LCK9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l08954" name="l08954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga551c1ad8749c8ddb6785c06c1461338f"> 8954</a></span><span class="preprocessor">#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) </span></div>
|
||
<div class="line"><a id="l08955" name="l08955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9aa0442c88bc17eaf07c55dd84910ea"> 8955</a></span><span class="preprocessor">#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk </span></div>
|
||
<div class="line"><a id="l08956" name="l08956"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8eeb57953118508685e74055da9d6348"> 8956</a></span><span class="preprocessor">#define GPIO_LCKR_LCK10_Pos (10U) </span></div>
|
||
<div class="line"><a id="l08957" name="l08957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1373c9d71b76f466fd817823e64e7aae"> 8957</a></span><span class="preprocessor">#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) </span></div>
|
||
<div class="line"><a id="l08958" name="l08958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae055f5848967c7929f47e848b2ed812"> 8958</a></span><span class="preprocessor">#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk </span></div>
|
||
<div class="line"><a id="l08959" name="l08959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a19305a39f7bd02815a39c998c34216"> 8959</a></span><span class="preprocessor">#define GPIO_LCKR_LCK11_Pos (11U) </span></div>
|
||
<div class="line"><a id="l08960" name="l08960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1aea84ab5cf33a4b62cdb3af4a819bde"> 8960</a></span><span class="preprocessor">#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) </span></div>
|
||
<div class="line"><a id="l08961" name="l08961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4de971426a1248621733a9b78ef552ab"> 8961</a></span><span class="preprocessor">#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk </span></div>
|
||
<div class="line"><a id="l08962" name="l08962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81e8901ea395cd0a1b56c4118670fa0e"> 8962</a></span><span class="preprocessor">#define GPIO_LCKR_LCK12_Pos (12U) </span></div>
|
||
<div class="line"><a id="l08963" name="l08963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf21271b45020769396b2980a02a4c309"> 8963</a></span><span class="preprocessor">#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) </span></div>
|
||
<div class="line"><a id="l08964" name="l08964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38e8685790aea3fb09194683d1f58508"> 8964</a></span><span class="preprocessor">#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk </span></div>
|
||
<div class="line"><a id="l08965" name="l08965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5dd0ccab863e23880863f0d431fdee11"> 8965</a></span><span class="preprocessor">#define GPIO_LCKR_LCK13_Pos (13U) </span></div>
|
||
<div class="line"><a id="l08966" name="l08966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64171a6f566fed1f9ea7418d6a00871c"> 8966</a></span><span class="preprocessor">#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) </span></div>
|
||
<div class="line"><a id="l08967" name="l08967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0279fa554731160a9115c21d95312a5"> 8967</a></span><span class="preprocessor">#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk </span></div>
|
||
<div class="line"><a id="l08968" name="l08968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5686e00f4e40771a31eb18d88e1ca1e9"> 8968</a></span><span class="preprocessor">#define GPIO_LCKR_LCK14_Pos (14U) </span></div>
|
||
<div class="line"><a id="l08969" name="l08969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac42b591ea761bd0ee23287ff8d508714"> 8969</a></span><span class="preprocessor">#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) </span></div>
|
||
<div class="line"><a id="l08970" name="l08970"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8bf290cecb54b6b68ac42a544b87dcee"> 8970</a></span><span class="preprocessor">#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk </span></div>
|
||
<div class="line"><a id="l08971" name="l08971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ba6d99e256f344ea2d8a4ba9278a0e3"> 8971</a></span><span class="preprocessor">#define GPIO_LCKR_LCK15_Pos (15U) </span></div>
|
||
<div class="line"><a id="l08972" name="l08972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3841ea86b5a8200485ab90c2c6511cec"> 8972</a></span><span class="preprocessor">#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) </span></div>
|
||
<div class="line"><a id="l08973" name="l08973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47c3114c8cd603d8aee022d0b426bf04"> 8973</a></span><span class="preprocessor">#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk </span></div>
|
||
<div class="line"><a id="l08974" name="l08974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40eb2db1c2df544774f41995d029565d"> 8974</a></span><span class="preprocessor">#define GPIO_LCKR_LCKK_Pos (16U) </span></div>
|
||
<div class="line"><a id="l08975" name="l08975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9312bf35ddbae593f8e94b3ea7dce9b5"> 8975</a></span><span class="preprocessor">#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) </span></div>
|
||
<div class="line"><a id="l08976" name="l08976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa2a83bf31ef76ee3857c7cb0a90c4d9"> 8976</a></span><span class="preprocessor">#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk </span></div>
|
||
<div class="line"><a id="l08977" name="l08977"></a><span class="lineno"> 8977</span><span class="comment">/****************** Bit definition for GPIO_AFRL register *********************/</span></div>
|
||
<div class="line"><a id="l08978" name="l08978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac06dd36e2c8c90fe9502bad271b2ee60"> 8978</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l08979" name="l08979"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga214860438ba3256833543e2f5018922f"> 8979</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) </span></div>
|
||
<div class="line"><a id="l08980" name="l08980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ec251e186471ae09aeb3cb0aa788594"> 8980</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk </span></div>
|
||
<div class="line"><a id="l08981" name="l08981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d64770b98ab6db5eee36068d6e0c45a"> 8981</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) </span></div>
|
||
<div class="line"><a id="l08982" name="l08982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabf16f4a3f9458d9576accc1695bed4a"> 8982</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) </span></div>
|
||
<div class="line"><a id="l08983" name="l08983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab872e44f9df01f18e4f78cee45d5cf43"> 8983</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) </span></div>
|
||
<div class="line"><a id="l08984" name="l08984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a83a0eb943535ea970419f7bb87fa52"> 8984</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) </span></div>
|
||
<div class="line"><a id="l08985" name="l08985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga313ba8093d5a511430908d9adc90dc6a"> 8985</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL1_Pos (4U) </span></div>
|
||
<div class="line"><a id="l08986" name="l08986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5aac45598b88539da585e098fc93d68b"> 8986</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) </span></div>
|
||
<div class="line"><a id="l08987" name="l08987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fbd174222a013c9a0e222fdd0888de2"> 8987</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk </span></div>
|
||
<div class="line"><a id="l08988" name="l08988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6834a1a64ce4c42bd71cdb0bc685f06"> 8988</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) </span></div>
|
||
<div class="line"><a id="l08989" name="l08989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4f1e8fe3cf48f2dcdd6cd96c88b5754"> 8989</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) </span></div>
|
||
<div class="line"><a id="l08990" name="l08990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac38c620ad920142f38db8ef78674df56"> 8990</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) </span></div>
|
||
<div class="line"><a id="l08991" name="l08991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ee3c6fd5280247ff5cb1e4c139ab85d"> 8991</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) </span></div>
|
||
<div class="line"><a id="l08992" name="l08992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae132b28ab4f67a9e90e7d15302aad49b"> 8992</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL2_Pos (8U) </span></div>
|
||
<div class="line"><a id="l08993" name="l08993"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga729f1e6b663a55ce7f5cfbe1c71489a4"> 8993</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) </span></div>
|
||
<div class="line"><a id="l08994" name="l08994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9bc63205b8a09bd2ae7fb066058f3da"> 8994</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk </span></div>
|
||
<div class="line"><a id="l08995" name="l08995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga566eef02569b14ba89745698e4c7f4cb"> 8995</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) </span></div>
|
||
<div class="line"><a id="l08996" name="l08996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99704f0bd6543a391b934faae9f86c0e"> 8996</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) </span></div>
|
||
<div class="line"><a id="l08997" name="l08997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e90655a95edd288bda4552137310e7c"> 8997</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) </span></div>
|
||
<div class="line"><a id="l08998" name="l08998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a2b8fe31b1620d99caaa0d5b00214fc"> 8998</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) </span></div>
|
||
<div class="line"><a id="l08999" name="l08999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d9325a035cc3d6962d660d3f54a8df4"> 8999</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL3_Pos (12U) </span></div>
|
||
<div class="line"><a id="l09000" name="l09000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf34ee7b30defbcad60d167a279a8c17d"> 9000</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) </span></div>
|
||
<div class="line"><a id="l09001" name="l09001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0fb36c07eac3809b6a5baaee74ee426"> 9001</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk </span></div>
|
||
<div class="line"><a id="l09002" name="l09002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0eb39bec095e2b4661141b20c1bd80d"> 9002</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) </span></div>
|
||
<div class="line"><a id="l09003" name="l09003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97101a6c182091257d9a86f38bbf8015"> 9003</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) </span></div>
|
||
<div class="line"><a id="l09004" name="l09004"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf97dd08bfd9439ae9a8be2aae31572ab"> 9004</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) </span></div>
|
||
<div class="line"><a id="l09005" name="l09005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga640b17198ae3a4dca834c93941bb459e"> 9005</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) </span></div>
|
||
<div class="line"><a id="l09006" name="l09006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga723fbe4b28093f1837001110d8d44d36"> 9006</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL4_Pos (16U) </span></div>
|
||
<div class="line"><a id="l09007" name="l09007"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47cfab1b5c3a37414bc4a6ac2cbd746a"> 9007</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) </span></div>
|
||
<div class="line"><a id="l09008" name="l09008"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga728e20cadadaa3c5aa1c42c25356a9f4"> 9008</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk </span></div>
|
||
<div class="line"><a id="l09009" name="l09009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga958dcb0150574251c77490397469d443"> 9009</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) </span></div>
|
||
<div class="line"><a id="l09010" name="l09010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89f30587f699e9b28347b41b1752d846"> 9010</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) </span></div>
|
||
<div class="line"><a id="l09011" name="l09011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafeb379dcb35516d7744e8a7467aa9ddf"> 9011</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) </span></div>
|
||
<div class="line"><a id="l09012" name="l09012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c7a684490eaf01f5e1bd29f89bebfb8"> 9012</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) </span></div>
|
||
<div class="line"><a id="l09013" name="l09013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf35270d71f53047d2a14d1047478c0ba"> 9013</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL5_Pos (20U) </span></div>
|
||
<div class="line"><a id="l09014" name="l09014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf514d5f0c3456e2f7fc6d82f2b392051"> 9014</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) </span></div>
|
||
<div class="line"><a id="l09015" name="l09015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad158052aa17b4bf12f9ad20b6e0c6d0c"> 9015</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk </span></div>
|
||
<div class="line"><a id="l09016" name="l09016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4fba4a0c264295148200fdbea3645efb"> 9016</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) </span></div>
|
||
<div class="line"><a id="l09017" name="l09017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf532421a6d6665eb9dd82752aa71bda6"> 9017</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) </span></div>
|
||
<div class="line"><a id="l09018" name="l09018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga600caf3a081a223a0c9bbd22c1d65fd7"> 9018</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) </span></div>
|
||
<div class="line"><a id="l09019" name="l09019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cf281224f66730f522948ce2f16a9dc"> 9019</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) </span></div>
|
||
<div class="line"><a id="l09020" name="l09020"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9943c5aeeb649ab6bf33fde0d844803"> 9020</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL6_Pos (24U) </span></div>
|
||
<div class="line"><a id="l09021" name="l09021"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb4e272e9b14944740fbe643542f0ade"> 9021</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) </span></div>
|
||
<div class="line"><a id="l09022" name="l09022"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga893c83ab521d1bf15e71b20309d71503"> 9022</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk </span></div>
|
||
<div class="line"><a id="l09023" name="l09023"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4eb2b4e77d1338ae80e889bb7f98159"> 9023</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) </span></div>
|
||
<div class="line"><a id="l09024" name="l09024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87ae4b89cf40e01fc3d0c1cca38db1de"> 9024</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) </span></div>
|
||
<div class="line"><a id="l09025" name="l09025"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace077c57cb72736ef5dca98052403b72"> 9025</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) </span></div>
|
||
<div class="line"><a id="l09026" name="l09026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b1fee857fd7d1b412ed64b1c6572280"> 9026</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) </span></div>
|
||
<div class="line"><a id="l09027" name="l09027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2836c1149e06b2497f1f53518f1151f2"> 9027</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL7_Pos (28U) </span></div>
|
||
<div class="line"><a id="l09028" name="l09028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3248acbb1bea59926db7edb98a245b0"> 9028</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) </span></div>
|
||
<div class="line"><a id="l09029" name="l09029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0128026ab2c8ed18da456aaf82827e11"> 9029</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk </span></div>
|
||
<div class="line"><a id="l09030" name="l09030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35641566dd5e2c3483d8ac494ff9e50d"> 9030</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) </span></div>
|
||
<div class="line"><a id="l09031" name="l09031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a155fcc736492a694dac6b25c803f85"> 9031</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) </span></div>
|
||
<div class="line"><a id="l09032" name="l09032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31a4fdc80b155797db598779ae7a242f"> 9032</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) </span></div>
|
||
<div class="line"><a id="l09033" name="l09033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac11328845c720331b1d6a12003b3f4d3"> 9033</a></span><span class="preprocessor">#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) </span></div>
|
||
<div class="line"><a id="l09035" name="l09035"></a><span class="lineno"> 9035</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l09036" name="l09036"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4af89daf61c25562733d281e9acde3d"> 9036</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0</span></div>
|
||
<div class="line"><a id="l09037" name="l09037"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3f152d808e8aa43362b108b1160c128"> 9037</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0</span></div>
|
||
<div class="line"><a id="l09038" name="l09038"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd77c2da1b416d80c239a024c8e4ef61"> 9038</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1</span></div>
|
||
<div class="line"><a id="l09039" name="l09039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga693446d17258b95fafb2685a5fe868ab"> 9039</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2</span></div>
|
||
<div class="line"><a id="l09040" name="l09040"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac17d2fbadcaab82ce79836839278642c"> 9040</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3</span></div>
|
||
<div class="line"><a id="l09041" name="l09041"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga122cbed720d27776f0cfa6dab1fbc84c"> 9041</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1</span></div>
|
||
<div class="line"><a id="l09042" name="l09042"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f2f94b9a8f50f296dd0a20b110b2e93"> 9042</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0</span></div>
|
||
<div class="line"><a id="l09043" name="l09043"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf34ee437f14787a7bc240b13469f8d02"> 9043</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1</span></div>
|
||
<div class="line"><a id="l09044" name="l09044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b9d92f139b6f523c8ece0582caa9205"> 9044</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2</span></div>
|
||
<div class="line"><a id="l09045" name="l09045"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga385ae9713490b8a47c63fb3f1d92eecf"> 9045</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3</span></div>
|
||
<div class="line"><a id="l09046" name="l09046"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafda8ce333741832561e1e3e76abcee7a"> 9046</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2</span></div>
|
||
<div class="line"><a id="l09047" name="l09047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ae4ecfdc6739da7658d5618f949b4f0"> 9047</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0</span></div>
|
||
<div class="line"><a id="l09048" name="l09048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6105e47f03d5c714f52753c721848e2"> 9048</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1</span></div>
|
||
<div class="line"><a id="l09049" name="l09049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d392ca99cf444404f329d5419febb1d"> 9049</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2</span></div>
|
||
<div class="line"><a id="l09050" name="l09050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08baef06281ebf48156f43cd6727bd7f"> 9050</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3</span></div>
|
||
<div class="line"><a id="l09051" name="l09051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee969704e28b7b0159838a8aec5f1e65"> 9051</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3</span></div>
|
||
<div class="line"><a id="l09052" name="l09052"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95865001c230cb9d6794a1a8faa53464"> 9052</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0</span></div>
|
||
<div class="line"><a id="l09053" name="l09053"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8669f979e8cde27c80e8b33fb5cc4f96"> 9053</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1</span></div>
|
||
<div class="line"><a id="l09054" name="l09054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c4a49fa8bb4a4e2cd8613be0fe8a4e3"> 9054</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2</span></div>
|
||
<div class="line"><a id="l09055" name="l09055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14278231a30cffd346762047a69f4cc2"> 9055</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3</span></div>
|
||
<div class="line"><a id="l09056" name="l09056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac862d4f115fd881871356418943a4446"> 9056</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4</span></div>
|
||
<div class="line"><a id="l09057" name="l09057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2138d6628f63ceff1b9340fe143e4309"> 9057</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0</span></div>
|
||
<div class="line"><a id="l09058" name="l09058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa691f7acdc66a2d79e128264a7bd1a63"> 9058</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1</span></div>
|
||
<div class="line"><a id="l09059" name="l09059"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b2c314441cd3d4841bdb1e3d5de9db5"> 9059</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2</span></div>
|
||
<div class="line"><a id="l09060" name="l09060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacab260848c23e7b1ea2777f0e4a40fc1"> 9060</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3</span></div>
|
||
<div class="line"><a id="l09061" name="l09061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga481f4065077c16365632e6a647cdcb4e"> 9061</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5</span></div>
|
||
<div class="line"><a id="l09062" name="l09062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe45d3ec4c0a71d968112e7a65b5510d"> 9062</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0</span></div>
|
||
<div class="line"><a id="l09063" name="l09063"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6372195804d3e61723030fb0d9a2268f"> 9063</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1</span></div>
|
||
<div class="line"><a id="l09064" name="l09064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf383c494976eda7fad4006b937a6f359"> 9064</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2</span></div>
|
||
<div class="line"><a id="l09065" name="l09065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01dfdf9aa650eb4d3c06c6f7a4e79e44"> 9065</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3</span></div>
|
||
<div class="line"><a id="l09066" name="l09066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac87a55d05f6d16cbfbce6e04a2c6888e"> 9066</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6</span></div>
|
||
<div class="line"><a id="l09067" name="l09067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa94adf1532fc4188a926ba7d366cc13e"> 9067</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0</span></div>
|
||
<div class="line"><a id="l09068" name="l09068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f5289d6b05cf1ed7959b89dfb4e64a0"> 9068</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1</span></div>
|
||
<div class="line"><a id="l09069" name="l09069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf8dff68b61d57bf6cbe6f22d76c5629"> 9069</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2</span></div>
|
||
<div class="line"><a id="l09070" name="l09070"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf05b72714d2577958fa5c2b5e871d223"> 9070</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3</span></div>
|
||
<div class="line"><a id="l09071" name="l09071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97a41237468859702de7ea91dad62ed8"> 9071</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7</span></div>
|
||
<div class="line"><a id="l09072" name="l09072"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga292b5b0e56572245d5c5d72fcdada9fa"> 9072</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0</span></div>
|
||
<div class="line"><a id="l09073" name="l09073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d5348d823ed82075ed48b74a36c9db2"> 9073</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1</span></div>
|
||
<div class="line"><a id="l09074" name="l09074"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf28527531ac7958b1de74f0883a53334"> 9074</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2</span></div>
|
||
<div class="line"><a id="l09075" name="l09075"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1adb4a490f9b5c323dba6e591f4131f6"> 9075</a></span><span class="preprocessor">#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3</span></div>
|
||
<div class="line"><a id="l09076" name="l09076"></a><span class="lineno"> 9076</span> </div>
|
||
<div class="line"><a id="l09077" name="l09077"></a><span class="lineno"> 9077</span><span class="comment">/****************** Bit definition for GPIO_AFRH register *********************/</span></div>
|
||
<div class="line"><a id="l09078" name="l09078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cdfdbcb5332d98e0202f4f86480736f"> 9078</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL8_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09079" name="l09079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5be819e7ca1f69e2d5f6d63aaee056c2"> 9079</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) </span></div>
|
||
<div class="line"><a id="l09080" name="l09080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ed3881740613378329271150088f1b2"> 9080</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk </span></div>
|
||
<div class="line"><a id="l09081" name="l09081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72cc5ca956395dbb409019f45601727d"> 9081</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) </span></div>
|
||
<div class="line"><a id="l09082" name="l09082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23cb04d03ed3fc80a827dd4fcd092e92"> 9082</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) </span></div>
|
||
<div class="line"><a id="l09083" name="l09083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0d2ccbadd52c0de148593218c735ed3"> 9083</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) </span></div>
|
||
<div class="line"><a id="l09084" name="l09084"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd9fc9adc13e5e90df54b8885522f98e"> 9084</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) </span></div>
|
||
<div class="line"><a id="l09085" name="l09085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9aeed0c87696c3a98e7e4fc3dc6dc80"> 9085</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL9_Pos (4U) </span></div>
|
||
<div class="line"><a id="l09086" name="l09086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb779906c49372a9c0d7c8eaf7face71"> 9086</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) </span></div>
|
||
<div class="line"><a id="l09087" name="l09087"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacff5a20b7c9f10be43364ff422bb40ef"> 9087</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk </span></div>
|
||
<div class="line"><a id="l09088" name="l09088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44f61f3cb607268196179fa0a28b051e"> 9088</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) </span></div>
|
||
<div class="line"><a id="l09089" name="l09089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6093967302f540000072f05d3e64bf6f"> 9089</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) </span></div>
|
||
<div class="line"><a id="l09090" name="l09090"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7d91556fe4f170bbd818e6d88f5bc56"> 9090</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) </span></div>
|
||
<div class="line"><a id="l09091" name="l09091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab68b3750a95f3627dea9867fb5cf4689"> 9091</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) </span></div>
|
||
<div class="line"><a id="l09092" name="l09092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga334f2ca0e5684d230cb7788969997f07"> 9092</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL10_Pos (8U) </span></div>
|
||
<div class="line"><a id="l09093" name="l09093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33b875b9713ed4640e400fcf126cf105"> 9093</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) </span></div>
|
||
<div class="line"><a id="l09094" name="l09094"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c41926ac3fc6ec0fb8def28275bbe30"> 9094</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk </span></div>
|
||
<div class="line"><a id="l09095" name="l09095"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d9771de8ec013027f8f26d799e7a3fe"> 9095</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) </span></div>
|
||
<div class="line"><a id="l09096" name="l09096"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8f7170c263301f7b7c55dcdf1acb832"> 9096</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) </span></div>
|
||
<div class="line"><a id="l09097" name="l09097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0b280a9f8a751dcb4a27cf2e9a73598"> 9097</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) </span></div>
|
||
<div class="line"><a id="l09098" name="l09098"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc1431b847bccbc8841d8ab9a6aa36e5"> 9098</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) </span></div>
|
||
<div class="line"><a id="l09099" name="l09099"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f655e646b26d49e38053d9ee9cc064b"> 9099</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL11_Pos (12U) </span></div>
|
||
<div class="line"><a id="l09100" name="l09100"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76888c8d8080e47339e0fd2e69ab42d8"> 9100</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) </span></div>
|
||
<div class="line"><a id="l09101" name="l09101"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47a97a35b9f12ef795aa1ebb3d85c3aa"> 9101</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk </span></div>
|
||
<div class="line"><a id="l09102" name="l09102"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga711beadb293e4ef285bb813b2e9feb6d"> 9102</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) </span></div>
|
||
<div class="line"><a id="l09103" name="l09103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ad64e530b4cf96c745f69ac97d23195"> 9103</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) </span></div>
|
||
<div class="line"><a id="l09104" name="l09104"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ffb839fbc0a35b148f17363553f6647"> 9104</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) </span></div>
|
||
<div class="line"><a id="l09105" name="l09105"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga570aa5e92e75568945191853f0196321"> 9105</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) </span></div>
|
||
<div class="line"><a id="l09106" name="l09106"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0dce1ce501e0b3b5e5e4b4961f7afda3"> 9106</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL12_Pos (16U) </span></div>
|
||
<div class="line"><a id="l09107" name="l09107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae162137694aa110fb89b9afeea1c648f"> 9107</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) </span></div>
|
||
<div class="line"><a id="l09108" name="l09108"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c12c0939e7fcc354e37d55b74afb351"> 9108</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk </span></div>
|
||
<div class="line"><a id="l09109" name="l09109"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffe1b4dcd4e796a2e145df206f35d6ea"> 9109</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) </span></div>
|
||
<div class="line"><a id="l09110" name="l09110"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac5933c2c73fec3d2f3c41d32fb64bfa"> 9110</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) </span></div>
|
||
<div class="line"><a id="l09111" name="l09111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ed0f0c148e3c52bf041ab53af1d88bf"> 9111</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) </span></div>
|
||
<div class="line"><a id="l09112" name="l09112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbd6cfac7c23742a6e1fe120adfe3183"> 9112</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) </span></div>
|
||
<div class="line"><a id="l09113" name="l09113"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65b195db19c1ca62ef95eed10c649180"> 9113</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL13_Pos (20U) </span></div>
|
||
<div class="line"><a id="l09114" name="l09114"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc533ac377beb113777896f0deb0ef91"> 9114</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) </span></div>
|
||
<div class="line"><a id="l09115" name="l09115"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60e9a3a49cdad6cd65d377fb675185da"> 9115</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk </span></div>
|
||
<div class="line"><a id="l09116" name="l09116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab74ce92f856d5f687b069166f211ecaf"> 9116</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) </span></div>
|
||
<div class="line"><a id="l09117" name="l09117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d2985f042e79fb320b402a6e1c425f7"> 9117</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) </span></div>
|
||
<div class="line"><a id="l09118" name="l09118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59cb8d2b8ca336c6c169c0e1a07cb2eb"> 9118</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) </span></div>
|
||
<div class="line"><a id="l09119" name="l09119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2ff66c2036fd651e7ae366db237b76c"> 9119</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) </span></div>
|
||
<div class="line"><a id="l09120" name="l09120"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fcd5b907f7ca9538dffe1aeb00d7942"> 9120</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL14_Pos (24U) </span></div>
|
||
<div class="line"><a id="l09121" name="l09121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae997df2b0bb50f310e7fd17df043e8e8"> 9121</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) </span></div>
|
||
<div class="line"><a id="l09122" name="l09122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3d930c6c5ffa92e461a0190be4bff78"> 9122</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk </span></div>
|
||
<div class="line"><a id="l09123" name="l09123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf5b6ebd9c3a8039b46748dcbd3eda99"> 9123</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) </span></div>
|
||
<div class="line"><a id="l09124" name="l09124"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21985995f6f22d63ba1170ee629bcf02"> 9124</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) </span></div>
|
||
<div class="line"><a id="l09125" name="l09125"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c98e75f198a3d84038029711c3f299f"> 9125</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) </span></div>
|
||
<div class="line"><a id="l09126" name="l09126"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41d1c1c7ac6886975bca9cc8ef57c73d"> 9126</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) </span></div>
|
||
<div class="line"><a id="l09127" name="l09127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a0ed32e0f197da7ea8856a58cebdb46"> 9127</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL15_Pos (28U) </span></div>
|
||
<div class="line"><a id="l09128" name="l09128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf94ca202e9ee8d766a5ee7794dba95b6"> 9128</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) </span></div>
|
||
<div class="line"><a id="l09129" name="l09129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46417b0da710ef512ac4ceb95b3ab44a"> 9129</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk </span></div>
|
||
<div class="line"><a id="l09130" name="l09130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga841bd65d5afd409fd7f2bf5f1e859348"> 9130</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) </span></div>
|
||
<div class="line"><a id="l09131" name="l09131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga233f1ae0a856a18e7b706093c80a6274"> 9131</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) </span></div>
|
||
<div class="line"><a id="l09132" name="l09132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadaae51ed82039c62ec075b42a192c861"> 9132</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) </span></div>
|
||
<div class="line"><a id="l09133" name="l09133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8699f7ff5369b8c20eaa32cfecbe7daf"> 9133</a></span><span class="preprocessor">#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) </span></div>
|
||
<div class="line"><a id="l09135" name="l09135"></a><span class="lineno"> 9135</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l09136" name="l09136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc5bb516e3b29af807cf4772787dfd0d"> 9136</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8</span></div>
|
||
<div class="line"><a id="l09137" name="l09137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga696d2e7fbb6ae2b172f64f9edd5af9b0"> 9137</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0</span></div>
|
||
<div class="line"><a id="l09138" name="l09138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21e5f36c2bf8a8977d72621d93876b0b"> 9138</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1</span></div>
|
||
<div class="line"><a id="l09139" name="l09139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40d8eb06b294389ac37efc69291182ec"> 9139</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2</span></div>
|
||
<div class="line"><a id="l09140" name="l09140"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa177428d840116200ec8e3645cfffbc7"> 9140</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3</span></div>
|
||
<div class="line"><a id="l09141" name="l09141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75ca2458aef597ebfcd1eb6b83035acd"> 9141</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9</span></div>
|
||
<div class="line"><a id="l09142" name="l09142"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5050213115941df4d89f1803ff3dce18"> 9142</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0</span></div>
|
||
<div class="line"><a id="l09143" name="l09143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga413c97129e63fb91bdf0ac8220d9db00"> 9143</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1</span></div>
|
||
<div class="line"><a id="l09144" name="l09144"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b89ccc6c477c0cd8ff857285df07d84"> 9144</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2</span></div>
|
||
<div class="line"><a id="l09145" name="l09145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0ead68cbb1f4aadad0789e8d2bd32e4"> 9145</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3</span></div>
|
||
<div class="line"><a id="l09146" name="l09146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dc39c907cd02befde4b7681b2fa070b"> 9146</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10</span></div>
|
||
<div class="line"><a id="l09147" name="l09147"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bc474910f7c3867c687e3d642dc7f86"> 9147</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0</span></div>
|
||
<div class="line"><a id="l09148" name="l09148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6284f87ff50100a6c3e2cb496be1388a"> 9148</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1</span></div>
|
||
<div class="line"><a id="l09149" name="l09149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa444f8755f374e202cb437a9f202f635"> 9149</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2</span></div>
|
||
<div class="line"><a id="l09150" name="l09150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02b23ce670e6b5a0e87f28d1baa673a2"> 9150</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3</span></div>
|
||
<div class="line"><a id="l09151" name="l09151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7043cbf3ca044ba36d59a8844c50552b"> 9151</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11</span></div>
|
||
<div class="line"><a id="l09152" name="l09152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a0bca51b2c5a8635202590ed61842ab"> 9152</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0</span></div>
|
||
<div class="line"><a id="l09153" name="l09153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace0ca814ed3617d6f520ded8bc05cf3e"> 9153</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1</span></div>
|
||
<div class="line"><a id="l09154" name="l09154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e22f1d39a67e130c29ba1d30d8b0740"> 9154</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2</span></div>
|
||
<div class="line"><a id="l09155" name="l09155"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22d6db61365e1172a8e5d895cbc16f59"> 9155</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3</span></div>
|
||
<div class="line"><a id="l09156" name="l09156"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadae24d162b9e5a99064a81ba6a8d01d8"> 9156</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12</span></div>
|
||
<div class="line"><a id="l09157" name="l09157"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee18ebc3ee54fcf4b049c722aaabd664"> 9157</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0</span></div>
|
||
<div class="line"><a id="l09158" name="l09158"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd4ef3f6843069e21c3474025f9ad452"> 9158</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1</span></div>
|
||
<div class="line"><a id="l09159" name="l09159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23d973c410f46a567dd05719fc60e8b9"> 9159</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2</span></div>
|
||
<div class="line"><a id="l09160" name="l09160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef19c9e546b1d7130244a824a129a86d"> 9160</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3</span></div>
|
||
<div class="line"><a id="l09161" name="l09161"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33b1d2c7b5ed5804798660a3e86214c4"> 9161</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13</span></div>
|
||
<div class="line"><a id="l09162" name="l09162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaccf0f28c6792dcea352d16295a3370e"> 9162</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0</span></div>
|
||
<div class="line"><a id="l09163" name="l09163"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb8de41b0dd5fdb53556acbd27eaffef"> 9163</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1</span></div>
|
||
<div class="line"><a id="l09164" name="l09164"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17d3ee9f02ed784d1f9eafd306c7770b"> 9164</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2</span></div>
|
||
<div class="line"><a id="l09165" name="l09165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaca724f908dbf5ae10fe4721c4bb9a63"> 9165</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3</span></div>
|
||
<div class="line"><a id="l09166" name="l09166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56c388b4718d2257b4af362bec67a74a"> 9166</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14</span></div>
|
||
<div class="line"><a id="l09167" name="l09167"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67bfcdbe201c0d10d6c604a7a77ef2c0"> 9167</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0</span></div>
|
||
<div class="line"><a id="l09168" name="l09168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c262cd0c09affb4b7a8d7fe40cb8737"> 9168</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1</span></div>
|
||
<div class="line"><a id="l09169" name="l09169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37c5f9c67bf086d5d2adf5e894476103"> 9169</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2</span></div>
|
||
<div class="line"><a id="l09170" name="l09170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69f0639cf752be23c3d72c7218a1e179"> 9170</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3</span></div>
|
||
<div class="line"><a id="l09171" name="l09171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga770397420d63cb6e8317ae401e6b2977"> 9171</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15</span></div>
|
||
<div class="line"><a id="l09172" name="l09172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5323b47a92dc55d60b67a8d36049b07"> 9172</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0</span></div>
|
||
<div class="line"><a id="l09173" name="l09173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga133a9bf6920bdf13fbeda9e02c88bab4"> 9173</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1</span></div>
|
||
<div class="line"><a id="l09174" name="l09174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa20fc99964f4f634664e4498869d1ec4"> 9174</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2</span></div>
|
||
<div class="line"><a id="l09175" name="l09175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a6c924c6c54448656df6acfa66b9aae"> 9175</a></span><span class="preprocessor">#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3</span></div>
|
||
<div class="line"><a id="l09176" name="l09176"></a><span class="lineno"> 9176</span> </div>
|
||
<div class="line"><a id="l09177" name="l09177"></a><span class="lineno"> 9177</span> </div>
|
||
<div class="line"><a id="l09178" name="l09178"></a><span class="lineno"> 9178</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l09179" name="l09179"></a><span class="lineno"> 9179</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l09180" name="l09180"></a><span class="lineno"> 9180</span><span class="comment">/* Inter-integrated Circuit Interface */</span></div>
|
||
<div class="line"><a id="l09181" name="l09181"></a><span class="lineno"> 9181</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l09182" name="l09182"></a><span class="lineno"> 9182</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l09183" name="l09183"></a><span class="lineno"> 9183</span><span class="comment">/******************* Bit definition for I2C_CR1 register ********************/</span></div>
|
||
<div class="line"><a id="l09184" name="l09184"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7954738eae12426137b23733f12c7c14"> 9184</a></span><span class="preprocessor">#define I2C_CR1_PE_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09185" name="l09185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga641d1563a97f92a4c5e20dcdd0756986"> 9185</a></span><span class="preprocessor">#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) </span></div>
|
||
<div class="line"><a id="l09186" name="l09186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga953b0d38414808db79da116842ed3262"> 9186</a></span><span class="preprocessor">#define I2C_CR1_PE I2C_CR1_PE_Msk </span></div>
|
||
<div class="line"><a id="l09187" name="l09187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae26dbc9f9c06eb552db052b0603430c0"> 9187</a></span><span class="preprocessor">#define I2C_CR1_SMBUS_Pos (1U) </span></div>
|
||
<div class="line"><a id="l09188" name="l09188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf62afbb725efae2aa5a18c7841cfc51"> 9188</a></span><span class="preprocessor">#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) </span></div>
|
||
<div class="line"><a id="l09189" name="l09189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4cfee7b020a49bd037fa7cf27c796abc"> 9189</a></span><span class="preprocessor">#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk </span></div>
|
||
<div class="line"><a id="l09190" name="l09190"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf03323d716d67da6242e4da7431cd1ea"> 9190</a></span><span class="preprocessor">#define I2C_CR1_SMBTYPE_Pos (3U) </span></div>
|
||
<div class="line"><a id="l09191" name="l09191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67a812813bce3b9996dec37eff310945"> 9191</a></span><span class="preprocessor">#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) </span></div>
|
||
<div class="line"><a id="l09192" name="l09192"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga001198ff898802888edf58f56d5371c9"> 9192</a></span><span class="preprocessor">#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk </span></div>
|
||
<div class="line"><a id="l09193" name="l09193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga183847901bff6ed293ac42cedcd0a00f"> 9193</a></span><span class="preprocessor">#define I2C_CR1_ENARP_Pos (4U) </span></div>
|
||
<div class="line"><a id="l09194" name="l09194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga608ec88f391d4617d8d196acf88ae4c3"> 9194</a></span><span class="preprocessor">#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) </span></div>
|
||
<div class="line"><a id="l09195" name="l09195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4598185d9092edfbf943464bcbb342ac"> 9195</a></span><span class="preprocessor">#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk </span></div>
|
||
<div class="line"><a id="l09196" name="l09196"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6320b277f4eb5ad80869cf46509ab63"> 9196</a></span><span class="preprocessor">#define I2C_CR1_ENPEC_Pos (5U) </span></div>
|
||
<div class="line"><a id="l09197" name="l09197"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga047dbff196b5cc2e0ca679cf09daad7d"> 9197</a></span><span class="preprocessor">#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) </span></div>
|
||
<div class="line"><a id="l09198" name="l09198"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40d2eb849f9d55e6298035b61e84ca42"> 9198</a></span><span class="preprocessor">#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk </span></div>
|
||
<div class="line"><a id="l09199" name="l09199"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54ffd903ba1ddb087e7166a83b30d145"> 9199</a></span><span class="preprocessor">#define I2C_CR1_ENGC_Pos (6U) </span></div>
|
||
<div class="line"><a id="l09200" name="l09200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7eff07d7a774d45f0c0b853be70b1a06"> 9200</a></span><span class="preprocessor">#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) </span></div>
|
||
<div class="line"><a id="l09201" name="l09201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d8c219193b11f8507d7b85831d14912"> 9201</a></span><span class="preprocessor">#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk </span></div>
|
||
<div class="line"><a id="l09202" name="l09202"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57955bf36ff5f4cd6a753e01817bf3b2"> 9202</a></span><span class="preprocessor">#define I2C_CR1_NOSTRETCH_Pos (7U) </span></div>
|
||
<div class="line"><a id="l09203" name="l09203"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e4eb2525f0444cc6320f96cc6c01804"> 9203</a></span><span class="preprocessor">#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) </span></div>
|
||
<div class="line"><a id="l09204" name="l09204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga197aaca79f64e832af3a0a0864c2a08c"> 9204</a></span><span class="preprocessor">#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk </span></div>
|
||
<div class="line"><a id="l09205" name="l09205"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26478428c37301f88c8fe5a27ab7cff0"> 9205</a></span><span class="preprocessor">#define I2C_CR1_START_Pos (8U) </span></div>
|
||
<div class="line"><a id="l09206" name="l09206"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20183fa72a3acfb6eb7cd333569af62b"> 9206</a></span><span class="preprocessor">#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) </span></div>
|
||
<div class="line"><a id="l09207" name="l09207"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ca7f18dd5bc1130dbefae4ff8736143"> 9207</a></span><span class="preprocessor">#define I2C_CR1_START I2C_CR1_START_Msk </span></div>
|
||
<div class="line"><a id="l09208" name="l09208"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1acc4153373e71ad85766145727d751f"> 9208</a></span><span class="preprocessor">#define I2C_CR1_STOP_Pos (9U) </span></div>
|
||
<div class="line"><a id="l09209" name="l09209"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac560445dddd085e2ec78b6c38d290893"> 9209</a></span><span class="preprocessor">#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l09210" name="l09210"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace70293f3dfa24d448b600fc58e45223"> 9210</a></span><span class="preprocessor">#define I2C_CR1_STOP I2C_CR1_STOP_Msk </span></div>
|
||
<div class="line"><a id="l09211" name="l09211"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4d488ef9214c8e156aa5789193b1af2"> 9211</a></span><span class="preprocessor">#define I2C_CR1_ACK_Pos (10U) </span></div>
|
||
<div class="line"><a id="l09212" name="l09212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga901752f0d8d57314c1bf5841b4d15927"> 9212</a></span><span class="preprocessor">#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) </span></div>
|
||
<div class="line"><a id="l09213" name="l09213"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf933b105259a4bc46a957576adb8d96d"> 9213</a></span><span class="preprocessor">#define I2C_CR1_ACK I2C_CR1_ACK_Msk </span></div>
|
||
<div class="line"><a id="l09214" name="l09214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c8ebf2be75a57d79c3963cbb73299e5"> 9214</a></span><span class="preprocessor">#define I2C_CR1_POS_Pos (11U) </span></div>
|
||
<div class="line"><a id="l09215" name="l09215"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44cbb4dfe0bace0e0f63516352cdd686"> 9215</a></span><span class="preprocessor">#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) </span></div>
|
||
<div class="line"><a id="l09216" name="l09216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34721958229a5983f2e95dfeaa8e55c3"> 9216</a></span><span class="preprocessor">#define I2C_CR1_POS I2C_CR1_POS_Msk </span></div>
|
||
<div class="line"><a id="l09217" name="l09217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae27ac08c854b421c8bbef0f91cb02e77"> 9217</a></span><span class="preprocessor">#define I2C_CR1_PEC_Pos (12U) </span></div>
|
||
<div class="line"><a id="l09218" name="l09218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad603ba46a4c90d87755bc21032343a8e"> 9218</a></span><span class="preprocessor">#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) </span></div>
|
||
<div class="line"><a id="l09219" name="l09219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4d0119253d93a106b5ca704e5020c12"> 9219</a></span><span class="preprocessor">#define I2C_CR1_PEC I2C_CR1_PEC_Msk </span></div>
|
||
<div class="line"><a id="l09220" name="l09220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cbad0729b1263ee12efe299c460c7a9"> 9220</a></span><span class="preprocessor">#define I2C_CR1_ALERT_Pos (13U) </span></div>
|
||
<div class="line"><a id="l09221" name="l09221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c1f4432707ef457508aa265173d3ce6"> 9221</a></span><span class="preprocessor">#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) </span></div>
|
||
<div class="line"><a id="l09222" name="l09222"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56729ccf93c5d9f5b5b05002e3a2323c"> 9222</a></span><span class="preprocessor">#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk </span></div>
|
||
<div class="line"><a id="l09223" name="l09223"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f26e1407449ae64fade6b92a5e85bc9"> 9223</a></span><span class="preprocessor">#define I2C_CR1_SWRST_Pos (15U) </span></div>
|
||
<div class="line"><a id="l09224" name="l09224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87f58f075ab791157d5a7f73d61ea4a0"> 9224</a></span><span class="preprocessor">#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) </span></div>
|
||
<div class="line"><a id="l09225" name="l09225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8dc661ef13da02e5bcb943f2003d576d"> 9225</a></span><span class="preprocessor">#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk </span></div>
|
||
<div class="line"><a id="l09227" name="l09227"></a><span class="lineno"> 9227</span><span class="comment">/******************* Bit definition for I2C_CR2 register ********************/</span></div>
|
||
<div class="line"><a id="l09228" name="l09228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae37aa57192c71b1b734815130eeee8cd"> 9228</a></span><span class="preprocessor">#define I2C_CR2_FREQ_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09229" name="l09229"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga409296c2e8ff17ef7633266fad88d5ea"> 9229</a></span><span class="preprocessor">#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) </span></div>
|
||
<div class="line"><a id="l09230" name="l09230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga293fbe15ed5fd1fc95915bd6437859e7"> 9230</a></span><span class="preprocessor">#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk </span></div>
|
||
<div class="line"><a id="l09231" name="l09231"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09d944f5260f40a0eb714d41859e0d23"> 9231</a></span><span class="preprocessor">#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) </span></div>
|
||
<div class="line"><a id="l09232" name="l09232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25ab0ef2a7795e3326900b277479d89c"> 9232</a></span><span class="preprocessor">#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) </span></div>
|
||
<div class="line"><a id="l09233" name="l09233"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga657af5a02534cc900cbddc260319d845"> 9233</a></span><span class="preprocessor">#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) </span></div>
|
||
<div class="line"><a id="l09234" name="l09234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga655214f8327fd1322998c9d8bffe308d"> 9234</a></span><span class="preprocessor">#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) </span></div>
|
||
<div class="line"><a id="l09235" name="l09235"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3382a7262743bc824985af7339449386"> 9235</a></span><span class="preprocessor">#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) </span></div>
|
||
<div class="line"><a id="l09236" name="l09236"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3b1a2b777fcf158c9e4264485682a20"> 9236</a></span><span class="preprocessor">#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) </span></div>
|
||
<div class="line"><a id="l09238" name="l09238"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d664ebaabc46a45c4453e17e5132056"> 9238</a></span><span class="preprocessor">#define I2C_CR2_ITERREN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l09239" name="l09239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cbb0dde5e57765d211af8595a728029"> 9239</a></span><span class="preprocessor">#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) </span></div>
|
||
<div class="line"><a id="l09240" name="l09240"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f14ae48e4609c2b3645211234cba974"> 9240</a></span><span class="preprocessor">#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk </span></div>
|
||
<div class="line"><a id="l09241" name="l09241"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6b73580546ba348cd434416f7729d65"> 9241</a></span><span class="preprocessor">#define I2C_CR2_ITEVTEN_Pos (9U) </span></div>
|
||
<div class="line"><a id="l09242" name="l09242"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4a4a92cd2663c4e4e690fe5f66a1706"> 9242</a></span><span class="preprocessor">#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) </span></div>
|
||
<div class="line"><a id="l09243" name="l09243"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b1ebaf8173090ec469b055b98e585d2"> 9243</a></span><span class="preprocessor">#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk </span></div>
|
||
<div class="line"><a id="l09244" name="l09244"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cf0976d8a817ec970a78137e6bac452"> 9244</a></span><span class="preprocessor">#define I2C_CR2_ITBUFEN_Pos (10U) </span></div>
|
||
<div class="line"><a id="l09245" name="l09245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga765fa0272f4a94eed64fba9b3cdac713"> 9245</a></span><span class="preprocessor">#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) </span></div>
|
||
<div class="line"><a id="l09246" name="l09246"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2efbe5d96ed0ce447a45a62e8317a68a"> 9246</a></span><span class="preprocessor">#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk </span></div>
|
||
<div class="line"><a id="l09247" name="l09247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69b0d5b0217bd628743324b8393bc74a"> 9247</a></span><span class="preprocessor">#define I2C_CR2_DMAEN_Pos (11U) </span></div>
|
||
<div class="line"><a id="l09248" name="l09248"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2987290a42860b8700c2dcfb8eaef399"> 9248</a></span><span class="preprocessor">#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) </span></div>
|
||
<div class="line"><a id="l09249" name="l09249"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb81d5c91486b873bd0bf279a4ffcf69"> 9249</a></span><span class="preprocessor">#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk </span></div>
|
||
<div class="line"><a id="l09250" name="l09250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c908f15a0b4c9e603d17b066fc85b7b"> 9250</a></span><span class="preprocessor">#define I2C_CR2_LAST_Pos (12U) </span></div>
|
||
<div class="line"><a id="l09251" name="l09251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c9c22f3c0a1abb70e0255c765b30382"> 9251</a></span><span class="preprocessor">#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) </span></div>
|
||
<div class="line"><a id="l09252" name="l09252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a0955008cbabbb6b726ba0b4f8da609"> 9252</a></span><span class="preprocessor">#define I2C_CR2_LAST I2C_CR2_LAST_Msk </span></div>
|
||
<div class="line"><a id="l09254" name="l09254"></a><span class="lineno"> 9254</span><span class="comment">/******************* Bit definition for I2C_OAR1 register *******************/</span></div>
|
||
<div class="line"><a id="l09255" name="l09255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8250616a993a5f2bb04cd0f116005864"> 9255</a></span><span class="preprocessor">#define I2C_OAR1_ADD1_7 0x000000FEU </span></div>
|
||
<div class="line"><a id="l09256" name="l09256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8141dcd63a8429a64d488cc78ef3ec1"> 9256</a></span><span class="preprocessor">#define I2C_OAR1_ADD8_9 0x00000300U </span></div>
|
||
<div class="line"><a id="l09258" name="l09258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5025971b93434d9d6c1b47ba93cc4249"> 9258</a></span><span class="preprocessor">#define I2C_OAR1_ADD0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09259" name="l09259"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga315ebd53e115b321f02d945a5a485356"> 9259</a></span><span class="preprocessor">#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) </span></div>
|
||
<div class="line"><a id="l09260" name="l09260"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b7c20c81f79d17921718412b8fca6d7"> 9260</a></span><span class="preprocessor">#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk </span></div>
|
||
<div class="line"><a id="l09261" name="l09261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53aaf5c99387556eb05205972a9fd765"> 9261</a></span><span class="preprocessor">#define I2C_OAR1_ADD1_Pos (1U) </span></div>
|
||
<div class="line"><a id="l09262" name="l09262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedbc5009a53817d14a5b61b81abe47eb"> 9262</a></span><span class="preprocessor">#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) </span></div>
|
||
<div class="line"><a id="l09263" name="l09263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga499a61f0013c5c6fe38b848901f58769"> 9263</a></span><span class="preprocessor">#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk </span></div>
|
||
<div class="line"><a id="l09264" name="l09264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1601f93351d29fd314910972bd4a997"> 9264</a></span><span class="preprocessor">#define I2C_OAR1_ADD2_Pos (2U) </span></div>
|
||
<div class="line"><a id="l09265" name="l09265"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74d6b1ee8556d79db1f804871576381e"> 9265</a></span><span class="preprocessor">#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) </span></div>
|
||
<div class="line"><a id="l09266" name="l09266"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab44a263e36a7f34d922ff124aebd99c3"> 9266</a></span><span class="preprocessor">#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk </span></div>
|
||
<div class="line"><a id="l09267" name="l09267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04c1306ea26d1fde330540af98f2ebaf"> 9267</a></span><span class="preprocessor">#define I2C_OAR1_ADD3_Pos (3U) </span></div>
|
||
<div class="line"><a id="l09268" name="l09268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bd895166f6d0f2b1fe5bdb245495e7c"> 9268</a></span><span class="preprocessor">#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) </span></div>
|
||
<div class="line"><a id="l09269" name="l09269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9584dca3b1b414a63cf7ba75e557155b"> 9269</a></span><span class="preprocessor">#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk </span></div>
|
||
<div class="line"><a id="l09270" name="l09270"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91ebb7dae5c13a499109a9f0089387b2"> 9270</a></span><span class="preprocessor">#define I2C_OAR1_ADD4_Pos (4U) </span></div>
|
||
<div class="line"><a id="l09271" name="l09271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3261bcc4b1d94f2800cc78d26ef6a638"> 9271</a></span><span class="preprocessor">#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) </span></div>
|
||
<div class="line"><a id="l09272" name="l09272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga110b915b907f4bf29ff03da1f077bd97"> 9272</a></span><span class="preprocessor">#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk </span></div>
|
||
<div class="line"><a id="l09273" name="l09273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga863a732cfab0b27034149a5d95c1c978"> 9273</a></span><span class="preprocessor">#define I2C_OAR1_ADD5_Pos (5U) </span></div>
|
||
<div class="line"><a id="l09274" name="l09274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga078a30f84550430baa5ea4ce4b424afd"> 9274</a></span><span class="preprocessor">#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) </span></div>
|
||
<div class="line"><a id="l09275" name="l09275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0856dee2657cf0a04d79084da86988ca"> 9275</a></span><span class="preprocessor">#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk </span></div>
|
||
<div class="line"><a id="l09276" name="l09276"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadeef10580199e2315af15107d03374b6"> 9276</a></span><span class="preprocessor">#define I2C_OAR1_ADD6_Pos (6U) </span></div>
|
||
<div class="line"><a id="l09277" name="l09277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga708c99b9b7c44311be6a91fa01e2603d"> 9277</a></span><span class="preprocessor">#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) </span></div>
|
||
<div class="line"><a id="l09278" name="l09278"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5507af6154f60125dadc4654f57776ca"> 9278</a></span><span class="preprocessor">#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk </span></div>
|
||
<div class="line"><a id="l09279" name="l09279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff51a9d14ec34d35f911c1c4d474db02"> 9279</a></span><span class="preprocessor">#define I2C_OAR1_ADD7_Pos (7U) </span></div>
|
||
<div class="line"><a id="l09280" name="l09280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c9645decd676803bd6a1cb9e5cca0f8"> 9280</a></span><span class="preprocessor">#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) </span></div>
|
||
<div class="line"><a id="l09281" name="l09281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca710515f0aac5abdac02a630e09097c"> 9281</a></span><span class="preprocessor">#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk </span></div>
|
||
<div class="line"><a id="l09282" name="l09282"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15f7918fdb3af6d0c8ade393fb8c8357"> 9282</a></span><span class="preprocessor">#define I2C_OAR1_ADD8_Pos (8U) </span></div>
|
||
<div class="line"><a id="l09283" name="l09283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga484398bbd79662011f8fb6467c127d65"> 9283</a></span><span class="preprocessor">#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) </span></div>
|
||
<div class="line"><a id="l09284" name="l09284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab945eba8b842a253cc64cce722537264"> 9284</a></span><span class="preprocessor">#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk </span></div>
|
||
<div class="line"><a id="l09285" name="l09285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9208eb446047890ea90e2f87f57a8e0"> 9285</a></span><span class="preprocessor">#define I2C_OAR1_ADD9_Pos (9U) </span></div>
|
||
<div class="line"><a id="l09286" name="l09286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf1cdf0196ac2b11475fbf7078a852a2"> 9286</a></span><span class="preprocessor">#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) </span></div>
|
||
<div class="line"><a id="l09287" name="l09287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10cf2dfc6b1ed55413be06acca413430"> 9287</a></span><span class="preprocessor">#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk </span></div>
|
||
<div class="line"><a id="l09289" name="l09289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a9d87efeab027259266521e849cd0f6"> 9289</a></span><span class="preprocessor">#define I2C_OAR1_ADDMODE_Pos (15U) </span></div>
|
||
<div class="line"><a id="l09290" name="l09290"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga465856ef24302471bd5562be5f4d8418"> 9290</a></span><span class="preprocessor">#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) </span></div>
|
||
<div class="line"><a id="l09291" name="l09291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d8df80cd27313c896e887aae81fa639"> 9291</a></span><span class="preprocessor">#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk </span></div>
|
||
<div class="line"><a id="l09293" name="l09293"></a><span class="lineno"> 9293</span><span class="comment">/******************* Bit definition for I2C_OAR2 register *******************/</span></div>
|
||
<div class="line"><a id="l09294" name="l09294"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd1b7689ba1197bb496f7b0042e59ac9"> 9294</a></span><span class="preprocessor">#define I2C_OAR2_ENDUAL_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09295" name="l09295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28fa608f2cec586e6bdb98ae510022d9"> 9295</a></span><span class="preprocessor">#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) </span></div>
|
||
<div class="line"><a id="l09296" name="l09296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab83ed1ee64439cb2734a708445f37e94"> 9296</a></span><span class="preprocessor">#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk </span></div>
|
||
<div class="line"><a id="l09297" name="l09297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga809d88f42d6572f85dd75ab2bb92b243"> 9297</a></span><span class="preprocessor">#define I2C_OAR2_ADD2_Pos (1U) </span></div>
|
||
<div class="line"><a id="l09298" name="l09298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18d179042a15bdc94dd4477b990082c5"> 9298</a></span><span class="preprocessor">#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) </span></div>
|
||
<div class="line"><a id="l09299" name="l09299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd3d8fd1de1f16d051efb52dd3d657c4"> 9299</a></span><span class="preprocessor">#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk </span></div>
|
||
<div class="line"><a id="l09301" name="l09301"></a><span class="lineno"> 9301</span><span class="comment">/******************** Bit definition for I2C_DR register ********************/</span></div>
|
||
<div class="line"><a id="l09302" name="l09302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8168b87f1d876a0cdbafff9f3dd922f5"> 9302</a></span><span class="preprocessor">#define I2C_DR_DR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09303" name="l09303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b487d8e08e84b2ef59c6de0e92316b1"> 9303</a></span><span class="preprocessor">#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) </span></div>
|
||
<div class="line"><a id="l09304" name="l09304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac43021a4a7f79672d27c36a469b301d5"> 9304</a></span><span class="preprocessor">#define I2C_DR_DR I2C_DR_DR_Msk </span></div>
|
||
<div class="line"><a id="l09306" name="l09306"></a><span class="lineno"> 9306</span><span class="comment">/******************* Bit definition for I2C_SR1 register ********************/</span></div>
|
||
<div class="line"><a id="l09307" name="l09307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67ed7d8c3e9dc642c2c70c834aeec6ea"> 9307</a></span><span class="preprocessor">#define I2C_SR1_SB_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09308" name="l09308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9d2227f20b51eda4af2fb9e9dd4f6df"> 9308</a></span><span class="preprocessor">#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) </span></div>
|
||
<div class="line"><a id="l09309" name="l09309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6935c920da59d755d0cf834548a70ec4"> 9309</a></span><span class="preprocessor">#define I2C_SR1_SB I2C_SR1_SB_Msk </span></div>
|
||
<div class="line"><a id="l09310" name="l09310"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4662fc1d4534a406d3e4e417dcaa29c1"> 9310</a></span><span class="preprocessor">#define I2C_SR1_ADDR_Pos (1U) </span></div>
|
||
<div class="line"><a id="l09311" name="l09311"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga387882c1ac38b5af80a88ac6c5c8961f"> 9311</a></span><span class="preprocessor">#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) </span></div>
|
||
<div class="line"><a id="l09312" name="l09312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3db361a4d9dd84b187085a11d933b45d"> 9312</a></span><span class="preprocessor">#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk </span></div>
|
||
<div class="line"><a id="l09313" name="l09313"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c662220a2fc8d437b929ac360b7b6d3"> 9313</a></span><span class="preprocessor">#define I2C_SR1_BTF_Pos (2U) </span></div>
|
||
<div class="line"><a id="l09314" name="l09314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9da3a67ef386eb3c7fc5be2016a1f0b1"> 9314</a></span><span class="preprocessor">#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) </span></div>
|
||
<div class="line"><a id="l09315" name="l09315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb279f85d78cfe5abd3eeb0b40a65ab1"> 9315</a></span><span class="preprocessor">#define I2C_SR1_BTF I2C_SR1_BTF_Msk </span></div>
|
||
<div class="line"><a id="l09316" name="l09316"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57e3e98939884a675f561bd0133c73f7"> 9316</a></span><span class="preprocessor">#define I2C_SR1_ADD10_Pos (3U) </span></div>
|
||
<div class="line"><a id="l09317" name="l09317"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc01a4be991adeeffbdf18b5767ea30b"> 9317</a></span><span class="preprocessor">#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) </span></div>
|
||
<div class="line"><a id="l09318" name="l09318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6faaa55a1e48aa7c1f2b69669901445d"> 9318</a></span><span class="preprocessor">#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk </span></div>
|
||
<div class="line"><a id="l09319" name="l09319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga508dc538aee33bf854cfbe3b7f4a7ba9"> 9319</a></span><span class="preprocessor">#define I2C_SR1_STOPF_Pos (4U) </span></div>
|
||
<div class="line"><a id="l09320" name="l09320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1679ebac13f8ad5aad54acd446f70e4"> 9320</a></span><span class="preprocessor">#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) </span></div>
|
||
<div class="line"><a id="l09321" name="l09321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafcea4cdbe2f6da31566c897fa893a7c"> 9321</a></span><span class="preprocessor">#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk </span></div>
|
||
<div class="line"><a id="l09322" name="l09322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga380b3695a5b03ae70e411ba048a04e49"> 9322</a></span><span class="preprocessor">#define I2C_SR1_RXNE_Pos (6U) </span></div>
|
||
<div class="line"><a id="l09323" name="l09323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf56d0f5cc9b333a2d287baf96e1ca62"> 9323</a></span><span class="preprocessor">#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) </span></div>
|
||
<div class="line"><a id="l09324" name="l09324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6ebe33c992611bc2e25bbb01c1441a5"> 9324</a></span><span class="preprocessor">#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk </span></div>
|
||
<div class="line"><a id="l09325" name="l09325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdceff8db6df40c017f96a5e606ea884"> 9325</a></span><span class="preprocessor">#define I2C_SR1_TXE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l09326" name="l09326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga835a04e1e2c43a4462b9b5cd04b2b4ea"> 9326</a></span><span class="preprocessor">#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) </span></div>
|
||
<div class="line"><a id="l09327" name="l09327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdc4da49c163910203255e384591b6f7"> 9327</a></span><span class="preprocessor">#define I2C_SR1_TXE I2C_SR1_TXE_Msk </span></div>
|
||
<div class="line"><a id="l09328" name="l09328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a1c615024c02d5ea5bcb3717ff6863d"> 9328</a></span><span class="preprocessor">#define I2C_SR1_BERR_Pos (8U) </span></div>
|
||
<div class="line"><a id="l09329" name="l09329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga591f9c02dd6c1b393f295ddd9be5f28d"> 9329</a></span><span class="preprocessor">#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) </span></div>
|
||
<div class="line"><a id="l09330" name="l09330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d12990c90ab0757dcfea150ea50b227"> 9330</a></span><span class="preprocessor">#define I2C_SR1_BERR I2C_SR1_BERR_Msk </span></div>
|
||
<div class="line"><a id="l09331" name="l09331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafab03fd640b6661848addb3cd9d38519"> 9331</a></span><span class="preprocessor">#define I2C_SR1_ARLO_Pos (9U) </span></div>
|
||
<div class="line"><a id="l09332" name="l09332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7859c854cc27fefc075eb3a6d67410da"> 9332</a></span><span class="preprocessor">#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) </span></div>
|
||
<div class="line"><a id="l09333" name="l09333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbc52f6ec6172c71d8b026a22c2f69d2"> 9333</a></span><span class="preprocessor">#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk </span></div>
|
||
<div class="line"><a id="l09334" name="l09334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb0a33028b96b10708bd881b21c17dae"> 9334</a></span><span class="preprocessor">#define I2C_SR1_AF_Pos (10U) </span></div>
|
||
<div class="line"><a id="l09335" name="l09335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae64af2b76c8fc655547f07d0eda3c8d6"> 9335</a></span><span class="preprocessor">#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) </span></div>
|
||
<div class="line"><a id="l09336" name="l09336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62aa2496d4b3955214a16a7bd998fd88"> 9336</a></span><span class="preprocessor">#define I2C_SR1_AF I2C_SR1_AF_Msk </span></div>
|
||
<div class="line"><a id="l09337" name="l09337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga628a0e0ea5fa7dd31b68d2bac80b8b20"> 9337</a></span><span class="preprocessor">#define I2C_SR1_OVR_Pos (11U) </span></div>
|
||
<div class="line"><a id="l09338" name="l09338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeca6c423a2a9d7495c35517b3cc9a9b8"> 9338</a></span><span class="preprocessor">#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) </span></div>
|
||
<div class="line"><a id="l09339" name="l09339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad42d2435d2e64bf710c701c9b17adfb4"> 9339</a></span><span class="preprocessor">#define I2C_SR1_OVR I2C_SR1_OVR_Msk </span></div>
|
||
<div class="line"><a id="l09340" name="l09340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f1e78360bc478a00ca5c8176dcd0b22"> 9340</a></span><span class="preprocessor">#define I2C_SR1_PECERR_Pos (12U) </span></div>
|
||
<div class="line"><a id="l09341" name="l09341"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafd640f94fa388e27d4747c5eb8fc938"> 9341</a></span><span class="preprocessor">#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) </span></div>
|
||
<div class="line"><a id="l09342" name="l09342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b2976279024e832e53ad12796a7bb71"> 9342</a></span><span class="preprocessor">#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk </span></div>
|
||
<div class="line"><a id="l09343" name="l09343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80a7d5a7ab0b5eb4bbbcf59d64e9e58e"> 9343</a></span><span class="preprocessor">#define I2C_SR1_TIMEOUT_Pos (14U) </span></div>
|
||
<div class="line"><a id="l09344" name="l09344"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c0209188a2791eddad0c143ac7f9416"> 9344</a></span><span class="preprocessor">#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) </span></div>
|
||
<div class="line"><a id="l09345" name="l09345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef3a1e4921d7c509d1b639c67882c4c9"> 9345</a></span><span class="preprocessor">#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk </span></div>
|
||
<div class="line"><a id="l09346" name="l09346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0c047e24fefb89f3928b37b7695aa55"> 9346</a></span><span class="preprocessor">#define I2C_SR1_SMBALERT_Pos (15U) </span></div>
|
||
<div class="line"><a id="l09347" name="l09347"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga617464b325a3649c9a36ad80386558b6"> 9347</a></span><span class="preprocessor">#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) </span></div>
|
||
<div class="line"><a id="l09348" name="l09348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8df36c38deb8791d0ac3cb5881298c1c"> 9348</a></span><span class="preprocessor">#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk </span></div>
|
||
<div class="line"><a id="l09350" name="l09350"></a><span class="lineno"> 9350</span><span class="comment">/******************* Bit definition for I2C_SR2 register ********************/</span></div>
|
||
<div class="line"><a id="l09351" name="l09351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada5253dbcd3c7d67d0fad31d938f4b5b"> 9351</a></span><span class="preprocessor">#define I2C_SR2_MSL_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09352" name="l09352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad723df35fcda84431aefaace405b62b2"> 9352</a></span><span class="preprocessor">#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) </span></div>
|
||
<div class="line"><a id="l09353" name="l09353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75cc361adf0e72e33d6771ebfa17b52d"> 9353</a></span><span class="preprocessor">#define I2C_SR2_MSL I2C_SR2_MSL_Msk </span></div>
|
||
<div class="line"><a id="l09354" name="l09354"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9b4a60a8e919cfe14e222976859b1cd"> 9354</a></span><span class="preprocessor">#define I2C_SR2_BUSY_Pos (1U) </span></div>
|
||
<div class="line"><a id="l09355" name="l09355"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43693f4a5b2f232a145eee42f26a1110"> 9355</a></span><span class="preprocessor">#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) </span></div>
|
||
<div class="line"><a id="l09356" name="l09356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b1e75a82da73ae2873cff1cd27c3179"> 9356</a></span><span class="preprocessor">#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk </span></div>
|
||
<div class="line"><a id="l09357" name="l09357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91e4b3f7e5bff2ea65eefeadbc0a2e2a"> 9357</a></span><span class="preprocessor">#define I2C_SR2_TRA_Pos (2U) </span></div>
|
||
<div class="line"><a id="l09358" name="l09358"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga260f5bfa56cd55a6e25ae1585fc1381e"> 9358</a></span><span class="preprocessor">#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) </span></div>
|
||
<div class="line"><a id="l09359" name="l09359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga288b20416b42a79e591aa80d9a690fca"> 9359</a></span><span class="preprocessor">#define I2C_SR2_TRA I2C_SR2_TRA_Msk </span></div>
|
||
<div class="line"><a id="l09360" name="l09360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26e3032167b56ec310c7b81945dc76a4"> 9360</a></span><span class="preprocessor">#define I2C_SR2_GENCALL_Pos (4U) </span></div>
|
||
<div class="line"><a id="l09361" name="l09361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada42e3c3d8e62bfab1117a382def5383"> 9361</a></span><span class="preprocessor">#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) </span></div>
|
||
<div class="line"><a id="l09362" name="l09362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3aeb79cbe04f7ec1e3c2615921c4fab"> 9362</a></span><span class="preprocessor">#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk </span></div>
|
||
<div class="line"><a id="l09363" name="l09363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4be26fe6702a976b50628c3df1b352c"> 9363</a></span><span class="preprocessor">#define I2C_SR2_SMBDEFAULT_Pos (5U) </span></div>
|
||
<div class="line"><a id="l09364" name="l09364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa390034d42a7873287b68e9ae3935a26"> 9364</a></span><span class="preprocessor">#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) </span></div>
|
||
<div class="line"><a id="l09365" name="l09365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcf50334903013177a8c6f4e36b8d6fe"> 9365</a></span><span class="preprocessor">#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk </span></div>
|
||
<div class="line"><a id="l09366" name="l09366"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3da82932b239f193ac2f57f87c3b1f0"> 9366</a></span><span class="preprocessor">#define I2C_SR2_SMBHOST_Pos (6U) </span></div>
|
||
<div class="line"><a id="l09367" name="l09367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6bd5daae1a83a7a62584be9f601ec52d"> 9367</a></span><span class="preprocessor">#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) </span></div>
|
||
<div class="line"><a id="l09368" name="l09368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa07cf3e404f9f57e98d1ba3793079c80"> 9368</a></span><span class="preprocessor">#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk </span></div>
|
||
<div class="line"><a id="l09369" name="l09369"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga546ae463133d2c719996689e24e61e1f"> 9369</a></span><span class="preprocessor">#define I2C_SR2_DUALF_Pos (7U) </span></div>
|
||
<div class="line"><a id="l09370" name="l09370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga338ddbff50ca2b01dacc4b8e93014f30"> 9370</a></span><span class="preprocessor">#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) </span></div>
|
||
<div class="line"><a id="l09371" name="l09371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79a6a21835e06d9bc48009f4269b7798"> 9371</a></span><span class="preprocessor">#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk </span></div>
|
||
<div class="line"><a id="l09372" name="l09372"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga332f5e12ed830e7d99b241549220a3c0"> 9372</a></span><span class="preprocessor">#define I2C_SR2_PEC_Pos (8U) </span></div>
|
||
<div class="line"><a id="l09373" name="l09373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a9dceb742f98aa0f27e5ae8dc427a88"> 9373</a></span><span class="preprocessor">#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) </span></div>
|
||
<div class="line"><a id="l09374" name="l09374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a4fd5d9c9e2593be920d19a5f6ae732"> 9374</a></span><span class="preprocessor">#define I2C_SR2_PEC I2C_SR2_PEC_Msk </span></div>
|
||
<div class="line"><a id="l09376" name="l09376"></a><span class="lineno"> 9376</span><span class="comment">/******************* Bit definition for I2C_CCR register ********************/</span></div>
|
||
<div class="line"><a id="l09377" name="l09377"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga908f5b1edffdedba90f8bbb141eedb8a"> 9377</a></span><span class="preprocessor">#define I2C_CCR_CCR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09378" name="l09378"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3f68b672f4ff2fa9a6ba3e79e9e302b"> 9378</a></span><span class="preprocessor">#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) </span></div>
|
||
<div class="line"><a id="l09379" name="l09379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c8cb2bd83dd7dbdcf6ca4bbf4a841de"> 9379</a></span><span class="preprocessor">#define I2C_CCR_CCR I2C_CCR_CCR_Msk </span></div>
|
||
<div class="line"><a id="l09380" name="l09380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga152abc0c5a01abf887e702cbc9fe4f49"> 9380</a></span><span class="preprocessor">#define I2C_CCR_DUTY_Pos (14U) </span></div>
|
||
<div class="line"><a id="l09381" name="l09381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e91ff511dab94ae774aaa9c3052fbc6"> 9381</a></span><span class="preprocessor">#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) </span></div>
|
||
<div class="line"><a id="l09382" name="l09382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga851c8a6b598d54c1a805b1632a4078e5"> 9382</a></span><span class="preprocessor">#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk </span></div>
|
||
<div class="line"><a id="l09383" name="l09383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga017a81aea2e87d24a49e078079d72313"> 9383</a></span><span class="preprocessor">#define I2C_CCR_FS_Pos (15U) </span></div>
|
||
<div class="line"><a id="l09384" name="l09384"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1823d70e520da08c5b40320ed2f8331e"> 9384</a></span><span class="preprocessor">#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) </span></div>
|
||
<div class="line"><a id="l09385" name="l09385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea64e5d7eba609ac9a84964bc0bc2def"> 9385</a></span><span class="preprocessor">#define I2C_CCR_FS I2C_CCR_FS_Msk </span></div>
|
||
<div class="line"><a id="l09387" name="l09387"></a><span class="lineno"> 9387</span><span class="comment">/****************** Bit definition for I2C_TRISE register *******************/</span></div>
|
||
<div class="line"><a id="l09388" name="l09388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb08ecb9599f81e5112a25142cb0e98f"> 9388</a></span><span class="preprocessor">#define I2C_TRISE_TRISE_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09389" name="l09389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a3152b3f16c453126cc1cef41b765fe"> 9389</a></span><span class="preprocessor">#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) </span></div>
|
||
<div class="line"><a id="l09390" name="l09390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff77a39aba630647af62dc7f1a5dc218"> 9390</a></span><span class="preprocessor">#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk </span></div>
|
||
<div class="line"><a id="l09393" name="l09393"></a><span class="lineno"> 9393</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l09394" name="l09394"></a><span class="lineno"> 9394</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l09395" name="l09395"></a><span class="lineno"> 9395</span><span class="comment">/* Independent WATCHDOG */</span></div>
|
||
<div class="line"><a id="l09396" name="l09396"></a><span class="lineno"> 9396</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l09397" name="l09397"></a><span class="lineno"> 9397</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l09398" name="l09398"></a><span class="lineno"> 9398</span><span class="comment">/******************* Bit definition for IWDG_KR register ********************/</span></div>
|
||
<div class="line"><a id="l09399" name="l09399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a5d1982414442435695ce911fc91b3c"> 9399</a></span><span class="preprocessor">#define IWDG_KR_KEY_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09400" name="l09400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ccb19a688f8e5b1c41626d3718db07e"> 9400</a></span><span class="preprocessor">#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) </span></div>
|
||
<div class="line"><a id="l09401" name="l09401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga957f7d5f8a0ec1a6956a7f05cfbd97c2"> 9401</a></span><span class="preprocessor">#define IWDG_KR_KEY IWDG_KR_KEY_Msk </span></div>
|
||
<div class="line"><a id="l09403" name="l09403"></a><span class="lineno"> 9403</span><span class="comment">/******************* Bit definition for IWDG_PR register ********************/</span></div>
|
||
<div class="line"><a id="l09404" name="l09404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25d9c482d27bbc46b08d321c79d058e7"> 9404</a></span><span class="preprocessor">#define IWDG_PR_PR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09405" name="l09405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75390b0bbc7eb3073a88536fe7f1c5ff"> 9405</a></span><span class="preprocessor">#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) </span></div>
|
||
<div class="line"><a id="l09406" name="l09406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4de39c5672f17d326fceb5adc9adc090"> 9406</a></span><span class="preprocessor">#define IWDG_PR_PR IWDG_PR_PR_Msk </span></div>
|
||
<div class="line"><a id="l09407" name="l09407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b727e7882603df1684cbf230520ca76"> 9407</a></span><span class="preprocessor">#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) </span></div>
|
||
<div class="line"><a id="l09408" name="l09408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafba2551b90c68d95c736a116224b473e"> 9408</a></span><span class="preprocessor">#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) </span></div>
|
||
<div class="line"><a id="l09409" name="l09409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55a1d7fde4e3e724a8644652ba9bb2b9"> 9409</a></span><span class="preprocessor">#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) </span></div>
|
||
<div class="line"><a id="l09411" name="l09411"></a><span class="lineno"> 9411</span><span class="comment">/******************* Bit definition for IWDG_RLR register *******************/</span></div>
|
||
<div class="line"><a id="l09412" name="l09412"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57519650f213ae6a72cf9983d64b8618"> 9412</a></span><span class="preprocessor">#define IWDG_RLR_RL_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09413" name="l09413"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga797562ce090da2d4b6576ba3ec62ad12"> 9413</a></span><span class="preprocessor">#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) </span></div>
|
||
<div class="line"><a id="l09414" name="l09414"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87024bbb19f26def4c4c1510b22d3033"> 9414</a></span><span class="preprocessor">#define IWDG_RLR_RL IWDG_RLR_RL_Msk </span></div>
|
||
<div class="line"><a id="l09416" name="l09416"></a><span class="lineno"> 9416</span><span class="comment">/******************* Bit definition for IWDG_SR register ********************/</span></div>
|
||
<div class="line"><a id="l09417" name="l09417"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8174d249dcd092b42f36a09e5e04def1"> 9417</a></span><span class="preprocessor">#define IWDG_SR_PVU_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09418" name="l09418"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e966837f97df9cde2383682f0234a96"> 9418</a></span><span class="preprocessor">#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) </span></div>
|
||
<div class="line"><a id="l09419" name="l09419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga269bd5618ba773d32275b93be004c554"> 9419</a></span><span class="preprocessor">#define IWDG_SR_PVU IWDG_SR_PVU_Msk </span></div>
|
||
<div class="line"><a id="l09420" name="l09420"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4aeb9bcef7e84f6760608f5fcd052fec"> 9420</a></span><span class="preprocessor">#define IWDG_SR_RVU_Pos (1U) </span></div>
|
||
<div class="line"><a id="l09421" name="l09421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab984dca55296c6bc7aef24d356909c28"> 9421</a></span><span class="preprocessor">#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) </span></div>
|
||
<div class="line"><a id="l09422" name="l09422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadffb8339e556a3b10120b15f0dacc232"> 9422</a></span><span class="preprocessor">#define IWDG_SR_RVU IWDG_SR_RVU_Msk </span></div>
|
||
<div class="line"><a id="l09426" name="l09426"></a><span class="lineno"> 9426</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l09427" name="l09427"></a><span class="lineno"> 9427</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l09428" name="l09428"></a><span class="lineno"> 9428</span><span class="comment">/* Power Control */</span></div>
|
||
<div class="line"><a id="l09429" name="l09429"></a><span class="lineno"> 9429</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l09430" name="l09430"></a><span class="lineno"> 9430</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l09431" name="l09431"></a><span class="lineno"> 9431</span><span class="comment">/******************** Bit definition for PWR_CR register ********************/</span></div>
|
||
<div class="line"><a id="l09432" name="l09432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeff985ca572b03cb2b8fb57d72f04163"> 9432</a></span><span class="preprocessor">#define PWR_CR_LPDS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09433" name="l09433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15a3e5d29f5816a97918b938fe9882d8"> 9433</a></span><span class="preprocessor">#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) </span></div>
|
||
<div class="line"><a id="l09434" name="l09434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3aeb8d6f2539b0a3a4b851aeba0eea66"> 9434</a></span><span class="preprocessor">#define PWR_CR_LPDS PWR_CR_LPDS_Msk </span></div>
|
||
<div class="line"><a id="l09435" name="l09435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1038bf2ac726320cfe05865bda0a07e"> 9435</a></span><span class="preprocessor">#define PWR_CR_PDDS_Pos (1U) </span></div>
|
||
<div class="line"><a id="l09436" name="l09436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc8e1dc6252707c24412500e6695fd05"> 9436</a></span><span class="preprocessor">#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) </span></div>
|
||
<div class="line"><a id="l09437" name="l09437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c8075e98772470804c9e3fe74984115"> 9437</a></span><span class="preprocessor">#define PWR_CR_PDDS PWR_CR_PDDS_Msk </span></div>
|
||
<div class="line"><a id="l09438" name="l09438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8725c4a6e67a667c4de1087c9639221f"> 9438</a></span><span class="preprocessor">#define PWR_CR_CWUF_Pos (2U) </span></div>
|
||
<div class="line"><a id="l09439" name="l09439"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b3f54b99913b0d6413df2b3d2e4790a"> 9439</a></span><span class="preprocessor">#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) </span></div>
|
||
<div class="line"><a id="l09440" name="l09440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3928de64f633b84770b1cfecea702fa7"> 9440</a></span><span class="preprocessor">#define PWR_CR_CWUF PWR_CR_CWUF_Msk </span></div>
|
||
<div class="line"><a id="l09441" name="l09441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga657c1dc4aa1d976d5cb8870ad7791a09"> 9441</a></span><span class="preprocessor">#define PWR_CR_CSBF_Pos (3U) </span></div>
|
||
<div class="line"><a id="l09442" name="l09442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e25040e042ac06128a8cd5f858d8912"> 9442</a></span><span class="preprocessor">#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) </span></div>
|
||
<div class="line"><a id="l09443" name="l09443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab44484cacc35c80cf82eb011d6cbe13a"> 9443</a></span><span class="preprocessor">#define PWR_CR_CSBF PWR_CR_CSBF_Msk </span></div>
|
||
<div class="line"><a id="l09444" name="l09444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb4073cd8adfdba51b106072bab82fc3"> 9444</a></span><span class="preprocessor">#define PWR_CR_PVDE_Pos (4U) </span></div>
|
||
<div class="line"><a id="l09445" name="l09445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f556d56181a41dc59ba75be574155ad"> 9445</a></span><span class="preprocessor">#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) </span></div>
|
||
<div class="line"><a id="l09446" name="l09446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05d5c39759e69a294c0ab9bea8f142e5"> 9446</a></span><span class="preprocessor">#define PWR_CR_PVDE PWR_CR_PVDE_Msk </span></div>
|
||
<div class="line"><a id="l09448" name="l09448"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73dc96cce80c352f7bda9a3919023eef"> 9448</a></span><span class="preprocessor">#define PWR_CR_PLS_Pos (5U) </span></div>
|
||
<div class="line"><a id="l09449" name="l09449"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c4e8550b3c0d62156604ce5cdb659a7"> 9449</a></span><span class="preprocessor">#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) </span></div>
|
||
<div class="line"><a id="l09450" name="l09450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac73c24d43953c7598e42acdd4c4e7435"> 9450</a></span><span class="preprocessor">#define PWR_CR_PLS PWR_CR_PLS_Msk </span></div>
|
||
<div class="line"><a id="l09451" name="l09451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacef447510818c468c202e3b4991ea08e"> 9451</a></span><span class="preprocessor">#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) </span></div>
|
||
<div class="line"><a id="l09452" name="l09452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcd19d78943514a2f695a39b45594623"> 9452</a></span><span class="preprocessor">#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) </span></div>
|
||
<div class="line"><a id="l09453" name="l09453"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a8986ee557f443d4a8eebf68026bd52"> 9453</a></span><span class="preprocessor">#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) </span></div>
|
||
<div class="line"><a id="l09456" name="l09456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb6b904b20d7e4fff958c75748861216"> 9456</a></span><span class="preprocessor">#define PWR_CR_PLS_LEV0 0x00000000U </span></div>
|
||
<div class="line"><a id="l09457" name="l09457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15b71263f73f0c4e53ca91fc8d096818"> 9457</a></span><span class="preprocessor">#define PWR_CR_PLS_LEV1 0x00000020U </span></div>
|
||
<div class="line"><a id="l09458" name="l09458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ea128abc2fc4252b53d09ca2850e69e"> 9458</a></span><span class="preprocessor">#define PWR_CR_PLS_LEV2 0x00000040U </span></div>
|
||
<div class="line"><a id="l09459" name="l09459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c1782980a2fb12de80058729a74f174"> 9459</a></span><span class="preprocessor">#define PWR_CR_PLS_LEV3 0x00000060U </span></div>
|
||
<div class="line"><a id="l09460" name="l09460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fe79f097ea6c30a4ccf69ed3e177f85"> 9460</a></span><span class="preprocessor">#define PWR_CR_PLS_LEV4 0x00000080U </span></div>
|
||
<div class="line"><a id="l09461" name="l09461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga326781d09a07b4d215424fbbae11b7b2"> 9461</a></span><span class="preprocessor">#define PWR_CR_PLS_LEV5 0x000000A0U </span></div>
|
||
<div class="line"><a id="l09462" name="l09462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaff17e9c7fe7d837523b1e9a2f4e9baf"> 9462</a></span><span class="preprocessor">#define PWR_CR_PLS_LEV6 0x000000C0U </span></div>
|
||
<div class="line"><a id="l09463" name="l09463"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95e3b301b5470ae94d32c53a9fbdfc8b"> 9463</a></span><span class="preprocessor">#define PWR_CR_PLS_LEV7 0x000000E0U </span></div>
|
||
<div class="line"><a id="l09464" name="l09464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3c90e817e3ccc0031b20014ef7d434e"> 9464</a></span><span class="preprocessor">#define PWR_CR_DBP_Pos (8U) </span></div>
|
||
<div class="line"><a id="l09465" name="l09465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4dc0f910dd014d87bdb0259f89de5f8"> 9465</a></span><span class="preprocessor">#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) </span></div>
|
||
<div class="line"><a id="l09466" name="l09466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5c65ab845794ef48f09faa2ee44f718"> 9466</a></span><span class="preprocessor">#define PWR_CR_DBP PWR_CR_DBP_Msk </span></div>
|
||
<div class="line"><a id="l09467" name="l09467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7d09308d258629a5feea487cf8746c3"> 9467</a></span><span class="preprocessor">#define PWR_CR_FPDS_Pos (9U) </span></div>
|
||
<div class="line"><a id="l09468" name="l09468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86e13d0b0eb3f05a11893752cc372677"> 9468</a></span><span class="preprocessor">#define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos) </span></div>
|
||
<div class="line"><a id="l09469" name="l09469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc01f8b6d4bd0294f745fde6d8e57002"> 9469</a></span><span class="preprocessor">#define PWR_CR_FPDS PWR_CR_FPDS_Msk </span></div>
|
||
<div class="line"><a id="l09470" name="l09470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f4f27bd20dad692917746ce1f184d28"> 9470</a></span><span class="preprocessor">#define PWR_CR_VOS_Pos (14U) </span></div>
|
||
<div class="line"><a id="l09471" name="l09471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e94ecdd78a53924cc35417d24fc974a"> 9471</a></span><span class="preprocessor">#define PWR_CR_VOS_Msk (0x1UL << PWR_CR_VOS_Pos) </span></div>
|
||
<div class="line"><a id="l09472" name="l09472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccc33f1ba4e374e116ffa50f3a503030"> 9472</a></span><span class="preprocessor">#define PWR_CR_VOS PWR_CR_VOS_Msk </span></div>
|
||
<div class="line"><a id="l09474" name="l09474"></a><span class="lineno"> 9474</span><span class="comment">/* Legacy define */</span></div>
|
||
<div class="line"><a id="l09475" name="l09475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56b78f2f76a841d2e8ddd56299b8d3e2"> 9475</a></span><span class="preprocessor">#define PWR_CR_PMODE PWR_CR_VOS</span></div>
|
||
<div class="line"><a id="l09476" name="l09476"></a><span class="lineno"> 9476</span> </div>
|
||
<div class="line"><a id="l09477" name="l09477"></a><span class="lineno"> 9477</span><span class="comment">/******************* Bit definition for PWR_CSR register ********************/</span></div>
|
||
<div class="line"><a id="l09478" name="l09478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7e519f8bd84379dc4a94dd5acaff305"> 9478</a></span><span class="preprocessor">#define PWR_CSR_WUF_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09479" name="l09479"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga506641083e85de1202465b9be1712c24"> 9479</a></span><span class="preprocessor">#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) </span></div>
|
||
<div class="line"><a id="l09480" name="l09480"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9465bb7ad9ca936688344e2a077539e6"> 9480</a></span><span class="preprocessor">#define PWR_CSR_WUF PWR_CSR_WUF_Msk </span></div>
|
||
<div class="line"><a id="l09481" name="l09481"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28df9eb1abdd9d2f29b3f471f9aa096f"> 9481</a></span><span class="preprocessor">#define PWR_CSR_SBF_Pos (1U) </span></div>
|
||
<div class="line"><a id="l09482" name="l09482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab46cab51c4455b5ab8264684e0ca5783"> 9482</a></span><span class="preprocessor">#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) </span></div>
|
||
<div class="line"><a id="l09483" name="l09483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4fd42f153660593cad6f4fe22ff76bb"> 9483</a></span><span class="preprocessor">#define PWR_CSR_SBF PWR_CSR_SBF_Msk </span></div>
|
||
<div class="line"><a id="l09484" name="l09484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdec9406a561d29e05ca2e2f69fd4532"> 9484</a></span><span class="preprocessor">#define PWR_CSR_PVDO_Pos (2U) </span></div>
|
||
<div class="line"><a id="l09485" name="l09485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c27c44a96fdf582f2b25d00666a9548"> 9485</a></span><span class="preprocessor">#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) </span></div>
|
||
<div class="line"><a id="l09486" name="l09486"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3535ce181895cc00afeb28dcac68d04c"> 9486</a></span><span class="preprocessor">#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk </span></div>
|
||
<div class="line"><a id="l09487" name="l09487"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa51171d8f6200d89b50ebd63f678b7c1"> 9487</a></span><span class="preprocessor">#define PWR_CSR_BRR_Pos (3U) </span></div>
|
||
<div class="line"><a id="l09488" name="l09488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06752058548d6fbcc57dbc032fdde76d"> 9488</a></span><span class="preprocessor">#define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos) </span></div>
|
||
<div class="line"><a id="l09489" name="l09489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga939410de980c5bc297ff04bcf30875cc"> 9489</a></span><span class="preprocessor">#define PWR_CSR_BRR PWR_CSR_BRR_Msk </span></div>
|
||
<div class="line"><a id="l09490" name="l09490"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20d629ea754e9d5942a97e037d515816"> 9490</a></span><span class="preprocessor">#define PWR_CSR_EWUP_Pos (8U) </span></div>
|
||
<div class="line"><a id="l09491" name="l09491"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0b862445449f084acf74d1105f687da"> 9491</a></span><span class="preprocessor">#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) </span></div>
|
||
<div class="line"><a id="l09492" name="l09492"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ac8c15a08bbee754ea720b0d4a4f580"> 9492</a></span><span class="preprocessor">#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk </span></div>
|
||
<div class="line"><a id="l09493" name="l09493"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa593af0ab76fabc71e48dce7b04f8acf"> 9493</a></span><span class="preprocessor">#define PWR_CSR_BRE_Pos (9U) </span></div>
|
||
<div class="line"><a id="l09494" name="l09494"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacaed35bfe3de356d9e6def115ef87b9d"> 9494</a></span><span class="preprocessor">#define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos) </span></div>
|
||
<div class="line"><a id="l09495" name="l09495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f99becaceb185431dbf46fb22718d0a"> 9495</a></span><span class="preprocessor">#define PWR_CSR_BRE PWR_CSR_BRE_Msk </span></div>
|
||
<div class="line"><a id="l09496" name="l09496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2938c00bca7b4425b8289498e781b48"> 9496</a></span><span class="preprocessor">#define PWR_CSR_VOSRDY_Pos (14U) </span></div>
|
||
<div class="line"><a id="l09497" name="l09497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac90d2b7cd8836e014ee405815273ba9"> 9497</a></span><span class="preprocessor">#define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos) </span></div>
|
||
<div class="line"><a id="l09498" name="l09498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4126ed19cce54a5411ff8dd440171695"> 9498</a></span><span class="preprocessor">#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk </span></div>
|
||
<div class="line"><a id="l09500" name="l09500"></a><span class="lineno"> 9500</span><span class="comment">/* Legacy define */</span></div>
|
||
<div class="line"><a id="l09501" name="l09501"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga017220a84cc5ab813eee18edd6309827"> 9501</a></span><span class="preprocessor">#define PWR_CSR_REGRDY PWR_CSR_VOSRDY</span></div>
|
||
<div class="line"><a id="l09502" name="l09502"></a><span class="lineno"> 9502</span> </div>
|
||
<div class="line"><a id="l09503" name="l09503"></a><span class="lineno"> 9503</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l09504" name="l09504"></a><span class="lineno"> 9504</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l09505" name="l09505"></a><span class="lineno"> 9505</span><span class="comment">/* Reset and Clock Control */</span></div>
|
||
<div class="line"><a id="l09506" name="l09506"></a><span class="lineno"> 9506</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l09507" name="l09507"></a><span class="lineno"> 9507</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l09508" name="l09508"></a><span class="lineno"> 9508</span><span class="comment">/******************** Bit definition for RCC_CR register ********************/</span></div>
|
||
<div class="line"><a id="l09509" name="l09509"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24995a185bfa02f4ed0624e1a5921585"> 9509</a></span><span class="preprocessor">#define RCC_CR_HSION_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09510" name="l09510"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21adcb31640b6407baff549c0e7d1af0"> 9510</a></span><span class="preprocessor">#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) </span></div>
|
||
<div class="line"><a id="l09511" name="l09511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4fcacf94a97f7d49a70e089b39cf474"> 9511</a></span><span class="preprocessor">#define RCC_CR_HSION RCC_CR_HSION_Msk </span></div>
|
||
<div class="line"><a id="l09512" name="l09512"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77c32f27431ef9437aa34fb0f1d41da9"> 9512</a></span><span class="preprocessor">#define RCC_CR_HSIRDY_Pos (1U) </span></div>
|
||
<div class="line"><a id="l09513" name="l09513"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55c613573a83b8399c228dca39063947"> 9513</a></span><span class="preprocessor">#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) </span></div>
|
||
<div class="line"><a id="l09514" name="l09514"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9dbac3f2bc04f04ebafe1e66ae3fcf0d"> 9514</a></span><span class="preprocessor">#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk </span></div>
|
||
<div class="line"><a id="l09515" name="l09515"></a><span class="lineno"> 9515</span> </div>
|
||
<div class="line"><a id="l09516" name="l09516"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1eb6ab7cdd2569af23f9688384d577bb"> 9516</a></span><span class="preprocessor">#define RCC_CR_HSITRIM_Pos (3U) </span></div>
|
||
<div class="line"><a id="l09517" name="l09517"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47c875ded980268c8d87803fde1d3add"> 9517</a></span><span class="preprocessor">#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) </span></div>
|
||
<div class="line"><a id="l09518" name="l09518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5cb4397b2095c31660a01b748386aa70"> 9518</a></span><span class="preprocessor">#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk </span></div>
|
||
<div class="line"><a id="l09519" name="l09519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab999bbbc1d365d0100d34eaa9f426eb"> 9519</a></span><span class="preprocessor">#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) </span></div>
|
||
<div class="line"><a id="l09520" name="l09520"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga569d6a29d774e0f125b0c2b3671fae3c"> 9520</a></span><span class="preprocessor">#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) </span></div>
|
||
<div class="line"><a id="l09521" name="l09521"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10d80d64137e36f5183f6aa7002de6f5"> 9521</a></span><span class="preprocessor">#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) </span></div>
|
||
<div class="line"><a id="l09522" name="l09522"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe20245d2d971238dba9ee371a299ba9"> 9522</a></span><span class="preprocessor">#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) </span></div>
|
||
<div class="line"><a id="l09523" name="l09523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f9ab2e93a0b9b70d33812bcc5e920c1"> 9523</a></span><span class="preprocessor">#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) </span></div>
|
||
<div class="line"><a id="l09525" name="l09525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaca19ae5be8263a15a6122f80820ddab"> 9525</a></span><span class="preprocessor">#define RCC_CR_HSICAL_Pos (8U) </span></div>
|
||
<div class="line"><a id="l09526" name="l09526"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b0cd0084e6349428abdb91755f0a3d3"> 9526</a></span><span class="preprocessor">#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) </span></div>
|
||
<div class="line"><a id="l09527" name="l09527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67ae770db9851f14ad7c14a693f0f6d3"> 9527</a></span><span class="preprocessor">#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk </span></div>
|
||
<div class="line"><a id="l09528" name="l09528"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7daa7754e54d65916ddc54f37274d3a"> 9528</a></span><span class="preprocessor">#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) </span></div>
|
||
<div class="line"><a id="l09529" name="l09529"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78054087161dee567cadbb4b4b96fb08"> 9529</a></span><span class="preprocessor">#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) </span></div>
|
||
<div class="line"><a id="l09530" name="l09530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0c4bac85beb7de5916897f88150dc3f"> 9530</a></span><span class="preprocessor">#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) </span></div>
|
||
<div class="line"><a id="l09531" name="l09531"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03f71cd53f075e9d35fcbfe7ed3f6e12"> 9531</a></span><span class="preprocessor">#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) </span></div>
|
||
<div class="line"><a id="l09532" name="l09532"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf26eb00e1872a3754f200a3c32019e50"> 9532</a></span><span class="preprocessor">#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) </span></div>
|
||
<div class="line"><a id="l09533" name="l09533"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c5b733061a3c4c6d69a7a15cbcb0b87"> 9533</a></span><span class="preprocessor">#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) </span></div>
|
||
<div class="line"><a id="l09534" name="l09534"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee2d6b30ee4bf41d2b171adf273a6ee7"> 9534</a></span><span class="preprocessor">#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) </span></div>
|
||
<div class="line"><a id="l09535" name="l09535"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab42d5e412867df093ec2ea4b8dc2bf29"> 9535</a></span><span class="preprocessor">#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) </span></div>
|
||
<div class="line"><a id="l09537" name="l09537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf45a431682229e7131fab4a9df6bb8a"> 9537</a></span><span class="preprocessor">#define RCC_CR_HSEON_Pos (16U) </span></div>
|
||
<div class="line"><a id="l09538" name="l09538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71f5167bea85df0b393de9d3846ea8d1"> 9538</a></span><span class="preprocessor">#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) </span></div>
|
||
<div class="line"><a id="l09539" name="l09539"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb8228c9020595b4cf9995137b8c9a7d"> 9539</a></span><span class="preprocessor">#define RCC_CR_HSEON RCC_CR_HSEON_Msk </span></div>
|
||
<div class="line"><a id="l09540" name="l09540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b35f100d3353d0d73ef1f9099a70285"> 9540</a></span><span class="preprocessor">#define RCC_CR_HSERDY_Pos (17U) </span></div>
|
||
<div class="line"><a id="l09541" name="l09541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga993e8ee50d7049e18ec9ee1e5ddcaa64"> 9541</a></span><span class="preprocessor">#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) </span></div>
|
||
<div class="line"><a id="l09542" name="l09542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86a34e00182c83409d89ff566cb02cc4"> 9542</a></span><span class="preprocessor">#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk </span></div>
|
||
<div class="line"><a id="l09543" name="l09543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac11714ac23d6cbef2f25c8b6c38e07f9"> 9543</a></span><span class="preprocessor">#define RCC_CR_HSEBYP_Pos (18U) </span></div>
|
||
<div class="line"><a id="l09544" name="l09544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac04d2021b54bf9a1b66578c67a436b45"> 9544</a></span><span class="preprocessor">#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) </span></div>
|
||
<div class="line"><a id="l09545" name="l09545"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3288090671af5a959aae4d7f7696d55"> 9545</a></span><span class="preprocessor">#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk </span></div>
|
||
<div class="line"><a id="l09546" name="l09546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf8f4f358e06d0c2b8a040474c0c75aa"> 9546</a></span><span class="preprocessor">#define RCC_CR_CSSON_Pos (19U) </span></div>
|
||
<div class="line"><a id="l09547" name="l09547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf02f4983b7cd9e1b664729cf6abb1f5"> 9547</a></span><span class="preprocessor">#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) </span></div>
|
||
<div class="line"><a id="l09548" name="l09548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc05308869ad055e1e6f2c32d738aecd"> 9548</a></span><span class="preprocessor">#define RCC_CR_CSSON RCC_CR_CSSON_Msk </span></div>
|
||
<div class="line"><a id="l09549" name="l09549"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9969597c000e9ed714c2472e019f7df3"> 9549</a></span><span class="preprocessor">#define RCC_CR_PLLON_Pos (24U) </span></div>
|
||
<div class="line"><a id="l09550" name="l09550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60dd7c471ec3ba4587e0cecdc8238f87"> 9550</a></span><span class="preprocessor">#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) </span></div>
|
||
<div class="line"><a id="l09551" name="l09551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0e73d5b0a4883e074d40029b49ee47e"> 9551</a></span><span class="preprocessor">#define RCC_CR_PLLON RCC_CR_PLLON_Msk </span></div>
|
||
<div class="line"><a id="l09552" name="l09552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa99ebf56183320b517b804fbc76e8ce4"> 9552</a></span><span class="preprocessor">#define RCC_CR_PLLRDY_Pos (25U) </span></div>
|
||
<div class="line"><a id="l09553" name="l09553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga237ae9216a3ae5c1f6833a52995413df"> 9553</a></span><span class="preprocessor">#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) </span></div>
|
||
<div class="line"><a id="l09554" name="l09554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa12d7ac6a7f0f91d066aeb2c6071888"> 9554</a></span><span class="preprocessor">#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk </span></div>
|
||
<div class="line"><a id="l09555" name="l09555"></a><span class="lineno"> 9555</span><span class="comment">/*</span></div>
|
||
<div class="line"><a id="l09556" name="l09556"></a><span class="lineno"> 9556</span><span class="comment"> * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)</span></div>
|
||
<div class="line"><a id="l09557" name="l09557"></a><span class="lineno"> 9557</span><span class="comment"> */</span></div>
|
||
<div class="line"><a id="l09558" name="l09558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac48c0893e590b49fa8079830a0ae8abb"> 9558</a></span><span class="preprocessor">#define RCC_PLLI2S_SUPPORT </span></div>
|
||
<div class="line"><a id="l09560" name="l09560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c0b3e1822ce926499c6912929b96733"> 9560</a></span><span class="preprocessor">#define RCC_CR_PLLI2SON_Pos (26U) </span></div>
|
||
<div class="line"><a id="l09561" name="l09561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82caf73e368dd6e0af79ffff40c4c158"> 9561</a></span><span class="preprocessor">#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos) </span></div>
|
||
<div class="line"><a id="l09562" name="l09562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ccb8964b640530f1080f9ea549d8133"> 9562</a></span><span class="preprocessor">#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk </span></div>
|
||
<div class="line"><a id="l09563" name="l09563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcd54f910af8002a097dd8f827960112"> 9563</a></span><span class="preprocessor">#define RCC_CR_PLLI2SRDY_Pos (27U) </span></div>
|
||
<div class="line"><a id="l09564" name="l09564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac102f1739d82c9f002f6d107e37c6d63"> 9564</a></span><span class="preprocessor">#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos) </span></div>
|
||
<div class="line"><a id="l09565" name="l09565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7354703f289244a71753debf3ae26e46"> 9565</a></span><span class="preprocessor">#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk </span></div>
|
||
<div class="line"><a id="l09566" name="l09566"></a><span class="lineno"> 9566</span> </div>
|
||
<div class="line"><a id="l09567" name="l09567"></a><span class="lineno"> 9567</span><span class="comment">/******************** Bit definition for RCC_PLLCFGR register ***************/</span></div>
|
||
<div class="line"><a id="l09568" name="l09568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga681f0ec251dffb419df8fa23137fe810"> 9568</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09569" name="l09569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04d893187396788d18a3eb1cc7028686"> 9569</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos) </span></div>
|
||
<div class="line"><a id="l09570" name="l09570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a42e8b9ee60126976d9be056e5e66b1"> 9570</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk </span></div>
|
||
<div class="line"><a id="l09571" name="l09571"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga813e3d6b41b4338ae5aea47a2bdbab01"> 9571</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos) </span></div>
|
||
<div class="line"><a id="l09572" name="l09572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84ae6e7405926717249a9852acda1f10"> 9572</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos) </span></div>
|
||
<div class="line"><a id="l09573" name="l09573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga989f5ea1ac0275a2c15bf09408c8a4c6"> 9573</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos) </span></div>
|
||
<div class="line"><a id="l09574" name="l09574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9cdeab6a08889692656228ab1186e28c"> 9574</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos) </span></div>
|
||
<div class="line"><a id="l09575" name="l09575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20af5f07ceef21b957db9391fd8bd898"> 9575</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos) </span></div>
|
||
<div class="line"><a id="l09576" name="l09576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga195dfe1b9b158aa00996867bebd9c225"> 9576</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos) </span></div>
|
||
<div class="line"><a id="l09578" name="l09578"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78a5913e3fc53a740fe874ece04b2d84"> 9578</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l09579" name="l09579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc41ec903faa2ebee1356f88451a70be"> 9579</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos) </span></div>
|
||
<div class="line"><a id="l09580" name="l09580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b571901d7cdc93ca1ecc1531f26ba6a"> 9580</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk </span></div>
|
||
<div class="line"><a id="l09581" name="l09581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade84dfb497ed82c0cbbc40049ef3da2c"> 9581</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos) </span></div>
|
||
<div class="line"><a id="l09582" name="l09582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad54b80f8edb3a1f34d390382580edaf3"> 9582</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos) </span></div>
|
||
<div class="line"><a id="l09583" name="l09583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c165a47d134f31f9dff12d1e6f709f3"> 9583</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos) </span></div>
|
||
<div class="line"><a id="l09584" name="l09584"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b19e3e1f2dbe4c2327ebee7e9647365"> 9584</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos) </span></div>
|
||
<div class="line"><a id="l09585" name="l09585"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb4707942496f45d3cf85acfdeb37475"> 9585</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos) </span></div>
|
||
<div class="line"><a id="l09586" name="l09586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefb9ac3678faab95ddc7d42b2316b8ab"> 9586</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos) </span></div>
|
||
<div class="line"><a id="l09587" name="l09587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddfba8f0f4b9b772986a0d214dcced39"> 9587</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos) </span></div>
|
||
<div class="line"><a id="l09588" name="l09588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0df4b12cec2263d6acec32015035fe54"> 9588</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos) </span></div>
|
||
<div class="line"><a id="l09589" name="l09589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff473b6dc417ef6fa361017b2f107c06"> 9589</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos) </span></div>
|
||
<div class="line"><a id="l09591" name="l09591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa67d9c488f8ce7cc078b2c7ca607d742"> 9591</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLP_Pos (16U) </span></div>
|
||
<div class="line"><a id="l09592" name="l09592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga944643170311f50335c87c581ee11eca"> 9592</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos) </span></div>
|
||
<div class="line"><a id="l09593" name="l09593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2561745be271ee828e26de601f72162d"> 9593</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk </span></div>
|
||
<div class="line"><a id="l09594" name="l09594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46e5cb0fc1122e12425c26b5ed91bcfd"> 9594</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos) </span></div>
|
||
<div class="line"><a id="l09595" name="l09595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba4ddc9eb3b629852127551eeae77f73"> 9595</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos) </span></div>
|
||
<div class="line"><a id="l09597" name="l09597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae44f5b0b3eaa9d6f11eac2a8b1328cd7"> 9597</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLSRC_Pos (22U) </span></div>
|
||
<div class="line"><a id="l09598" name="l09598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30516f483e85323f76dab980af3be393"> 9598</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) </span></div>
|
||
<div class="line"><a id="l09599" name="l09599"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92cb53ea81d2c47537eb217cc6659a2e"> 9599</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk </span></div>
|
||
<div class="line"><a id="l09600" name="l09600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21e65d80de700a9c5f202f1c7c777679"> 9600</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U) </span></div>
|
||
<div class="line"><a id="l09601" name="l09601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga858f2c21bc43e423136f370f6c410909"> 9601</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) </span></div>
|
||
<div class="line"><a id="l09602" name="l09602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3a86c3918526efe2258ecbb34b91587"> 9602</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk </span></div>
|
||
<div class="line"><a id="l09603" name="l09603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf688c4f038f29247cc0280dbdda24a7"> 9603</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U </span></div>
|
||
<div class="line"><a id="l09604" name="l09604"></a><span class="lineno"> 9604</span> </div>
|
||
<div class="line"><a id="l09605" name="l09605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac574324eee39c3dcee75b37d7728c9ae"> 9605</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLQ_Pos (24U) </span></div>
|
||
<div class="line"><a id="l09606" name="l09606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61e97c300a1e833572204b270398158f"> 9606</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos) </span></div>
|
||
<div class="line"><a id="l09607" name="l09607"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga546495f69f570cb4b81d4a59054c7ed1"> 9607</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk </span></div>
|
||
<div class="line"><a id="l09608" name="l09608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56fe140a22f66d2dd7250bb1f39ab451"> 9608</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) </span></div>
|
||
<div class="line"><a id="l09609" name="l09609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7703def670b8ef3ec634f8f09a56ce00"> 9609</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) </span></div>
|
||
<div class="line"><a id="l09610" name="l09610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45ab5c1d1a26d34915a53de7013f6cf6"> 9610</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos) </span></div>
|
||
<div class="line"><a id="l09611" name="l09611"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga182a9e6e5d5e1c63a1d20daf9b1874b5"> 9611</a></span><span class="preprocessor">#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos) </span></div>
|
||
<div class="line"><a id="l09614" name="l09614"></a><span class="lineno"> 9614</span><span class="comment">/******************** Bit definition for RCC_CFGR register ******************/</span></div>
|
||
<div class="line"><a id="l09616" name="l09616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cf9dd749ab13a3b9d55308e24f60160"> 9616</a></span><span class="preprocessor">#define RCC_CFGR_SW_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09617" name="l09617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06ad7777386bbf5555ef8b02939197aa"> 9617</a></span><span class="preprocessor">#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) </span></div>
|
||
<div class="line"><a id="l09618" name="l09618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0eea5e5f7743a7e8995b8beeb18355c1"> 9618</a></span><span class="preprocessor">#define RCC_CFGR_SW RCC_CFGR_SW_Msk </span></div>
|
||
<div class="line"><a id="l09619" name="l09619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99f08d86fd41824058a7fdf817f7e2fd"> 9619</a></span><span class="preprocessor">#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) </span></div>
|
||
<div class="line"><a id="l09620" name="l09620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72d51cb5d66ee1aa4d2c6f14796a072f"> 9620</a></span><span class="preprocessor">#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) </span></div>
|
||
<div class="line"><a id="l09622" name="l09622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbac8bae4f0808b3c3a5185aa10081fb"> 9622</a></span><span class="preprocessor">#define RCC_CFGR_SW_HSI 0x00000000U </span></div>
|
||
<div class="line"><a id="l09623" name="l09623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb563f217242d969f4355d0818fde705"> 9623</a></span><span class="preprocessor">#define RCC_CFGR_SW_HSE 0x00000001U </span></div>
|
||
<div class="line"><a id="l09624" name="l09624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87389cacb2eaf53730da13a2a33cd487"> 9624</a></span><span class="preprocessor">#define RCC_CFGR_SW_PLL 0x00000002U </span></div>
|
||
<div class="line"><a id="l09627" name="l09627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab79d13a977d5b0c2e132b4939663158d"> 9627</a></span><span class="preprocessor">#define RCC_CFGR_SWS_Pos (2U) </span></div>
|
||
<div class="line"><a id="l09628" name="l09628"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef0b6cd7629c047bcc4ac3e88d920e25"> 9628</a></span><span class="preprocessor">#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) </span></div>
|
||
<div class="line"><a id="l09629" name="l09629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15bf2269500dc97e137315f44aa015c9"> 9629</a></span><span class="preprocessor">#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk </span></div>
|
||
<div class="line"><a id="l09630" name="l09630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1eae59112c51def51979e31e8695b39f"> 9630</a></span><span class="preprocessor">#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) </span></div>
|
||
<div class="line"><a id="l09631" name="l09631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad3a5718999d7259f216137a23c2a379"> 9631</a></span><span class="preprocessor">#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) </span></div>
|
||
<div class="line"><a id="l09633" name="l09633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6764639cf221e1ebc0b5448dcaed590a"> 9633</a></span><span class="preprocessor">#define RCC_CFGR_SWS_HSI 0x00000000U </span></div>
|
||
<div class="line"><a id="l09634" name="l09634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae09a0202f441c1a43e69c62331d50a08"> 9634</a></span><span class="preprocessor">#define RCC_CFGR_SWS_HSE 0x00000004U </span></div>
|
||
<div class="line"><a id="l09635" name="l09635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c67e2279804a83ef24438267d9d4a6c"> 9635</a></span><span class="preprocessor">#define RCC_CFGR_SWS_PLL 0x00000008U </span></div>
|
||
<div class="line"><a id="l09638" name="l09638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2447eb7ab6388f0446e7550df8f50d90"> 9638</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_Pos (4U) </span></div>
|
||
<div class="line"><a id="l09639" name="l09639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65804e0ce7ec3204e9a56bb848428460"> 9639</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) </span></div>
|
||
<div class="line"><a id="l09640" name="l09640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe10e66938644ee8054a2426ff23efea"> 9640</a></span><span class="preprocessor">#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk </span></div>
|
||
<div class="line"><a id="l09641" name="l09641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88ece6ca270b3ecf6f63bf20893bc172"> 9641</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) </span></div>
|
||
<div class="line"><a id="l09642" name="l09642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbdd3a02814178ba02b8ebbaccd91599"> 9642</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) </span></div>
|
||
<div class="line"><a id="l09643" name="l09643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadac734bddb507eed4a62a0af4cef74a3"> 9643</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) </span></div>
|
||
<div class="line"><a id="l09644" name="l09644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a1180512cc5f3dde7895040a9037286"> 9644</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) </span></div>
|
||
<div class="line"><a id="l09646" name="l09646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b7d7f29b09a49c31404fc0d44645c84"> 9646</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_DIV1 0x00000000U </span></div>
|
||
<div class="line"><a id="l09647" name="l09647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9eeb5e38e53e79b08a4ac438497ebea"> 9647</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_DIV2 0x00000080U </span></div>
|
||
<div class="line"><a id="l09648" name="l09648"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffe860867ae4b1b6d28473ded1546d91"> 9648</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_DIV4 0x00000090U </span></div>
|
||
<div class="line"><a id="l09649" name="l09649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca71d6b42bdb83b5ff5320578869a058"> 9649</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_DIV8 0x000000A0U </span></div>
|
||
<div class="line"><a id="l09650" name="l09650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3806da4f1afc9e5be0fca001c8c57815"> 9650</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_DIV16 0x000000B0U </span></div>
|
||
<div class="line"><a id="l09651" name="l09651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1caeba8dc2b4c0bb11be600e983e3370"> 9651</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_DIV64 0x000000C0U </span></div>
|
||
<div class="line"><a id="l09652" name="l09652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga280da821f0da1bec1f4c0e132ddf8eab"> 9652</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_DIV128 0x000000D0U </span></div>
|
||
<div class="line"><a id="l09653" name="l09653"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga089930cedd5b2cb201e717438f29d25b"> 9653</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_DIV256 0x000000E0U </span></div>
|
||
<div class="line"><a id="l09654" name="l09654"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5088dcbaefc55d4b6693e9b1e595ed0"> 9654</a></span><span class="preprocessor">#define RCC_CFGR_HPRE_DIV512 0x000000F0U </span></div>
|
||
<div class="line"><a id="l09657" name="l09657"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0f0825acc89712f58b97844fbac93ca"> 9657</a></span><span class="preprocessor">#define RCC_CFGR_PPRE1_Pos (10U) </span></div>
|
||
<div class="line"><a id="l09658" name="l09658"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48842716ad7c2280b8ddbac071cdc773"> 9658</a></span><span class="preprocessor">#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) </span></div>
|
||
<div class="line"><a id="l09659" name="l09659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50b2423a5fea74a47b9eb8ab51869412"> 9659</a></span><span class="preprocessor">#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk </span></div>
|
||
<div class="line"><a id="l09660" name="l09660"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d37c20686faa340a77021117f5908b7"> 9660</a></span><span class="preprocessor">#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) </span></div>
|
||
<div class="line"><a id="l09661" name="l09661"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad41049f8a28fdced6bb4d9267845ffa2"> 9661</a></span><span class="preprocessor">#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) </span></div>
|
||
<div class="line"><a id="l09662" name="l09662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fcb524f6ca203ddff1862c124d4f89f"> 9662</a></span><span class="preprocessor">#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) </span></div>
|
||
<div class="line"><a id="l09664" name="l09664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8f6562bb2ecf65055a2f42cbb48ef11"> 9664</a></span><span class="preprocessor">#define RCC_CFGR_PPRE1_DIV1 0x00000000U </span></div>
|
||
<div class="line"><a id="l09665" name="l09665"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf832ad6844c907d9bb37c1536defcb0d"> 9665</a></span><span class="preprocessor">#define RCC_CFGR_PPRE1_DIV2 0x00001000U </span></div>
|
||
<div class="line"><a id="l09666" name="l09666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e340725f46e9462d9b02a079b9fa8ae"> 9666</a></span><span class="preprocessor">#define RCC_CFGR_PPRE1_DIV4 0x00001400U </span></div>
|
||
<div class="line"><a id="l09667" name="l09667"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ddd6d657837e1971bb86e3bf1c15e72"> 9667</a></span><span class="preprocessor">#define RCC_CFGR_PPRE1_DIV8 0x00001800U </span></div>
|
||
<div class="line"><a id="l09668" name="l09668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c38ba326bde7c7a18c4f7f2aacf823f"> 9668</a></span><span class="preprocessor">#define RCC_CFGR_PPRE1_DIV16 0x00001C00U </span></div>
|
||
<div class="line"><a id="l09671" name="l09671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga562db8b1e75fa862a3652b56a29b9fb6"> 9671</a></span><span class="preprocessor">#define RCC_CFGR_PPRE2_Pos (13U) </span></div>
|
||
<div class="line"><a id="l09672" name="l09672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga489e055e843ee5090c0174bbb9af9a67"> 9672</a></span><span class="preprocessor">#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) </span></div>
|
||
<div class="line"><a id="l09673" name="l09673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad61bd4f9f345ba41806813b0bfff1311"> 9673</a></span><span class="preprocessor">#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk </span></div>
|
||
<div class="line"><a id="l09674" name="l09674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82ca63155494ed59eb5e34bec1e5f4e9"> 9674</a></span><span class="preprocessor">#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) </span></div>
|
||
<div class="line"><a id="l09675" name="l09675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdb19c9e76fe8e8a7c991714c92e937f"> 9675</a></span><span class="preprocessor">#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) </span></div>
|
||
<div class="line"><a id="l09676" name="l09676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9adc802687eab5b6ece99a20793219db"> 9676</a></span><span class="preprocessor">#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) </span></div>
|
||
<div class="line"><a id="l09678" name="l09678"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga247aebf1999a38ea07785558d277bb1a"> 9678</a></span><span class="preprocessor">#define RCC_CFGR_PPRE2_DIV1 0x00000000U </span></div>
|
||
<div class="line"><a id="l09679" name="l09679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99d9c91eaad122460d324a71cc939d1b"> 9679</a></span><span class="preprocessor">#define RCC_CFGR_PPRE2_DIV2 0x00008000U </span></div>
|
||
<div class="line"><a id="l09680" name="l09680"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4340fc3fc52eca36eb302959fbecb715"> 9680</a></span><span class="preprocessor">#define RCC_CFGR_PPRE2_DIV4 0x0000A000U </span></div>
|
||
<div class="line"><a id="l09681" name="l09681"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga412b382a1134e0ee5614e0f4bcf97552"> 9681</a></span><span class="preprocessor">#define RCC_CFGR_PPRE2_DIV8 0x0000C000U </span></div>
|
||
<div class="line"><a id="l09682" name="l09682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaece3ee58d4138f7452733bfa1ad37eb9"> 9682</a></span><span class="preprocessor">#define RCC_CFGR_PPRE2_DIV16 0x0000E000U </span></div>
|
||
<div class="line"><a id="l09685" name="l09685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2eaafc6a34ae561f23f1139a746cbfd8"> 9685</a></span><span class="preprocessor">#define RCC_CFGR_RTCPRE_Pos (16U) </span></div>
|
||
<div class="line"><a id="l09686" name="l09686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga850304b36d321ade71b90ca011ee5f74"> 9686</a></span><span class="preprocessor">#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos) </span></div>
|
||
<div class="line"><a id="l09687" name="l09687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7c067c52ecd135252c691aad32c0b83"> 9687</a></span><span class="preprocessor">#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk </span></div>
|
||
<div class="line"><a id="l09688" name="l09688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga702f887571365eeb42d74b9b9cc6fe0d"> 9688</a></span><span class="preprocessor">#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) </span></div>
|
||
<div class="line"><a id="l09689" name="l09689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1191ba4a2e089f9921d77be57394dec4"> 9689</a></span><span class="preprocessor">#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) </span></div>
|
||
<div class="line"><a id="l09690" name="l09690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae62885f29418cc83a57964fe631282cb"> 9690</a></span><span class="preprocessor">#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) </span></div>
|
||
<div class="line"><a id="l09691" name="l09691"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c703b8d9827f58e7ea783c6a9b74e41"> 9691</a></span><span class="preprocessor">#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) </span></div>
|
||
<div class="line"><a id="l09692" name="l09692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02b93e5154259a1a201bbb9c9b903c0a"> 9692</a></span><span class="preprocessor">#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) </span></div>
|
||
<div class="line"><a id="l09695" name="l09695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf44071a1145774e7c5a5ea41cc709c42"> 9695</a></span><span class="preprocessor">#define RCC_CFGR_MCO1_Pos (21U) </span></div>
|
||
<div class="line"><a id="l09696" name="l09696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83b21a49230470856ce978e05fb9c47b"> 9696</a></span><span class="preprocessor">#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos) </span></div>
|
||
<div class="line"><a id="l09697" name="l09697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26eb4a66eeff0ba17e9d2a06cf937ca4"> 9697</a></span><span class="preprocessor">#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk </span></div>
|
||
<div class="line"><a id="l09698" name="l09698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe73b3ad484eeecfa1556021677ecf4a"> 9698</a></span><span class="preprocessor">#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) </span></div>
|
||
<div class="line"><a id="l09699" name="l09699"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c7e8d1da534f052ce835f06227a9b7a"> 9699</a></span><span class="preprocessor">#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) </span></div>
|
||
<div class="line"><a id="l09701" name="l09701"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3345cb612da061eb09e7f41b42409e42"> 9701</a></span><span class="preprocessor">#define RCC_CFGR_I2SSRC_Pos (23U) </span></div>
|
||
<div class="line"><a id="l09702" name="l09702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadaa5cae9d2b4ddc11fbe5a1858ead900"> 9702</a></span><span class="preprocessor">#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos) </span></div>
|
||
<div class="line"><a id="l09703" name="l09703"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d43413fd6b17bd988ccae9e34296412"> 9703</a></span><span class="preprocessor">#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk </span></div>
|
||
<div class="line"><a id="l09704" name="l09704"></a><span class="lineno"> 9704</span> </div>
|
||
<div class="line"><a id="l09705" name="l09705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12578e7f44e1e03ec5c4fd5987303b1e"> 9705</a></span><span class="preprocessor">#define RCC_CFGR_MCO1PRE_Pos (24U) </span></div>
|
||
<div class="line"><a id="l09706" name="l09706"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada571dab4e704e380153b6e901b60ba8"> 9706</a></span><span class="preprocessor">#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos) </span></div>
|
||
<div class="line"><a id="l09707" name="l09707"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23171ca70972a106109a6e0804385ec5"> 9707</a></span><span class="preprocessor">#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk </span></div>
|
||
<div class="line"><a id="l09708" name="l09708"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8007a9d6ee3fd88912aaf290746ae0e"> 9708</a></span><span class="preprocessor">#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) </span></div>
|
||
<div class="line"><a id="l09709" name="l09709"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf7c1280f61d56b4897f9c876987e092"> 9709</a></span><span class="preprocessor">#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) </span></div>
|
||
<div class="line"><a id="l09710" name="l09710"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11e1d10d1b55e0d88d24212ea2c8ba6e"> 9710</a></span><span class="preprocessor">#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) </span></div>
|
||
<div class="line"><a id="l09712" name="l09712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d6ccde3c82ee001935b7cf3d5273923"> 9712</a></span><span class="preprocessor">#define RCC_CFGR_MCO2PRE_Pos (27U) </span></div>
|
||
<div class="line"><a id="l09713" name="l09713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56af08fd6ae55e0047d84c2e5cb44877"> 9713</a></span><span class="preprocessor">#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos) </span></div>
|
||
<div class="line"><a id="l09714" name="l09714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae387252f29b6f98cc1fffc4fa0719b6e"> 9714</a></span><span class="preprocessor">#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk </span></div>
|
||
<div class="line"><a id="l09715" name="l09715"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83dfcd5a1ce89869c82723f7eb9223ed"> 9715</a></span><span class="preprocessor">#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) </span></div>
|
||
<div class="line"><a id="l09716" name="l09716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e8d7cb746efc7511fa97ddfef2df793"> 9716</a></span><span class="preprocessor">#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) </span></div>
|
||
<div class="line"><a id="l09717" name="l09717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8773dfae91e6576d490fbee4aa2a639"> 9717</a></span><span class="preprocessor">#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) </span></div>
|
||
<div class="line"><a id="l09719" name="l09719"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06b28dad6a8c9bd84cf1f659ddb976a8"> 9719</a></span><span class="preprocessor">#define RCC_CFGR_MCO2_Pos (30U) </span></div>
|
||
<div class="line"><a id="l09720" name="l09720"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga193bf927828d92f9249975a792c738d5"> 9720</a></span><span class="preprocessor">#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos) </span></div>
|
||
<div class="line"><a id="l09721" name="l09721"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga022248a1167714f4d847b89243dc5244"> 9721</a></span><span class="preprocessor">#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk </span></div>
|
||
<div class="line"><a id="l09722" name="l09722"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga203156a3f57e2c4498999c7901e0defd"> 9722</a></span><span class="preprocessor">#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) </span></div>
|
||
<div class="line"><a id="l09723" name="l09723"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fdba9682ff474255248f84e6851932a"> 9723</a></span><span class="preprocessor">#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) </span></div>
|
||
<div class="line"><a id="l09725" name="l09725"></a><span class="lineno"> 9725</span><span class="comment">/******************** Bit definition for RCC_CIR register *******************/</span></div>
|
||
<div class="line"><a id="l09726" name="l09726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e24ddcd9380a97107db8d483fdd9cb2"> 9726</a></span><span class="preprocessor">#define RCC_CIR_LSIRDYF_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09727" name="l09727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2542dd9dbe634971278d2f4e24c3091"> 9727</a></span><span class="preprocessor">#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) </span></div>
|
||
<div class="line"><a id="l09728" name="l09728"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb94ccfe6a212f020e732d1dd787a6fb"> 9728</a></span><span class="preprocessor">#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk </span></div>
|
||
<div class="line"><a id="l09729" name="l09729"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a2be1b77680f922f877e6d1b56287f3"> 9729</a></span><span class="preprocessor">#define RCC_CIR_LSERDYF_Pos (1U) </span></div>
|
||
<div class="line"><a id="l09730" name="l09730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58e246b3d87483bf3ca4a55d470acf4f"> 9730</a></span><span class="preprocessor">#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) </span></div>
|
||
<div class="line"><a id="l09731" name="l09731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabfc100e7ae673dfcec7be79af0d91dfe"> 9731</a></span><span class="preprocessor">#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk </span></div>
|
||
<div class="line"><a id="l09732" name="l09732"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8f2d94fb254c9a2fe2c9aadcef7e147"> 9732</a></span><span class="preprocessor">#define RCC_CIR_HSIRDYF_Pos (2U) </span></div>
|
||
<div class="line"><a id="l09733" name="l09733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c72d692b99c4539982fea718b2ba8a6"> 9733</a></span><span class="preprocessor">#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) </span></div>
|
||
<div class="line"><a id="l09734" name="l09734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad38877547c4cbbb94659d5726f377163"> 9734</a></span><span class="preprocessor">#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk </span></div>
|
||
<div class="line"><a id="l09735" name="l09735"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37a0fe34b1b1c44c6982a69fa082f6c0"> 9735</a></span><span class="preprocessor">#define RCC_CIR_HSERDYF_Pos (3U) </span></div>
|
||
<div class="line"><a id="l09736" name="l09736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cbcd4b04177bd2420126b0de418de2e"> 9736</a></span><span class="preprocessor">#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) </span></div>
|
||
<div class="line"><a id="l09737" name="l09737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11ea196450aac9ac35e283a66afc3da6"> 9737</a></span><span class="preprocessor">#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk </span></div>
|
||
<div class="line"><a id="l09738" name="l09738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4be890d102ccff40b4e370d575940af5"> 9738</a></span><span class="preprocessor">#define RCC_CIR_PLLRDYF_Pos (4U) </span></div>
|
||
<div class="line"><a id="l09739" name="l09739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88d53f154b50703f3ab18f017b7ace1c"> 9739</a></span><span class="preprocessor">#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) </span></div>
|
||
<div class="line"><a id="l09740" name="l09740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f007895a17e668f22f7b8b24ca90aec"> 9740</a></span><span class="preprocessor">#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk </span></div>
|
||
<div class="line"><a id="l09741" name="l09741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23921a147e121d49592e590f773f3c6c"> 9741</a></span><span class="preprocessor">#define RCC_CIR_PLLI2SRDYF_Pos (5U) </span></div>
|
||
<div class="line"><a id="l09742" name="l09742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61e88621c6cbc397e6c0872c98f11151"> 9742</a></span><span class="preprocessor">#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos) </span></div>
|
||
<div class="line"><a id="l09743" name="l09743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad338d8663c078cf3d73e4bfaa44da093"> 9743</a></span><span class="preprocessor">#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk </span></div>
|
||
<div class="line"><a id="l09744" name="l09744"></a><span class="lineno"> 9744</span> </div>
|
||
<div class="line"><a id="l09745" name="l09745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab82aae1efb70d76f85bcad7ec0632d4c"> 9745</a></span><span class="preprocessor">#define RCC_CIR_CSSF_Pos (7U) </span></div>
|
||
<div class="line"><a id="l09746" name="l09746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8eb3ec455be7a5e4ffbe0abc9e2a77eb"> 9746</a></span><span class="preprocessor">#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) </span></div>
|
||
<div class="line"><a id="l09747" name="l09747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad66b719e4061294de35af58cc27aba7f"> 9747</a></span><span class="preprocessor">#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk </span></div>
|
||
<div class="line"><a id="l09748" name="l09748"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga085c2d83db641a456df4a5f67582bff5"> 9748</a></span><span class="preprocessor">#define RCC_CIR_LSIRDYIE_Pos (8U) </span></div>
|
||
<div class="line"><a id="l09749" name="l09749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ba1782e2e14efd1bd9feabf1608fd5a"> 9749</a></span><span class="preprocessor">#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) </span></div>
|
||
<div class="line"><a id="l09750" name="l09750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga872ba937149a7372138df06f8188ab56"> 9750</a></span><span class="preprocessor">#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk </span></div>
|
||
<div class="line"><a id="l09751" name="l09751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7eabf777f7d12a95038d5408cd9a3225"> 9751</a></span><span class="preprocessor">#define RCC_CIR_LSERDYIE_Pos (9U) </span></div>
|
||
<div class="line"><a id="l09752" name="l09752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24446323cbae3ab353f248d23655b822"> 9752</a></span><span class="preprocessor">#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) </span></div>
|
||
<div class="line"><a id="l09753" name="l09753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a0ad2672c9ba1b26012cbc6d423dff8"> 9753</a></span><span class="preprocessor">#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk </span></div>
|
||
<div class="line"><a id="l09754" name="l09754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc61d466aac29f7fbd88b0245d6cf8c1"> 9754</a></span><span class="preprocessor">#define RCC_CIR_HSIRDYIE_Pos (10U) </span></div>
|
||
<div class="line"><a id="l09755" name="l09755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7aeb42d0a5ef8e7bac1876e0689814e"> 9755</a></span><span class="preprocessor">#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) </span></div>
|
||
<div class="line"><a id="l09756" name="l09756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac714351a6f9dab4741354fb017638580"> 9756</a></span><span class="preprocessor">#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk </span></div>
|
||
<div class="line"><a id="l09757" name="l09757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a258b8f9041e6a3e30a12f371e1e289"> 9757</a></span><span class="preprocessor">#define RCC_CIR_HSERDYIE_Pos (11U) </span></div>
|
||
<div class="line"><a id="l09758" name="l09758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f6db5519f1bbb1d42ee0f43367e7fd9"> 9758</a></span><span class="preprocessor">#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) </span></div>
|
||
<div class="line"><a id="l09759" name="l09759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5492f9b58600cf66616eb931b48b3c11"> 9759</a></span><span class="preprocessor">#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk </span></div>
|
||
<div class="line"><a id="l09760" name="l09760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54f619655facb49336e0baf439ef130b"> 9760</a></span><span class="preprocessor">#define RCC_CIR_PLLRDYIE_Pos (12U) </span></div>
|
||
<div class="line"><a id="l09761" name="l09761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fdb478ae8c7d99d780c78bb68830dd5"> 9761</a></span><span class="preprocessor">#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) </span></div>
|
||
<div class="line"><a id="l09762" name="l09762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b70927cab2ba9cf82d1620cf88b0f95"> 9762</a></span><span class="preprocessor">#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk </span></div>
|
||
<div class="line"><a id="l09763" name="l09763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac69e15926ecae3167dfbc860e784e7f3"> 9763</a></span><span class="preprocessor">#define RCC_CIR_PLLI2SRDYIE_Pos (13U) </span></div>
|
||
<div class="line"><a id="l09764" name="l09764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6af4a5b0b017c2dde04fa660950578cc"> 9764</a></span><span class="preprocessor">#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos) </span></div>
|
||
<div class="line"><a id="l09765" name="l09765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ca3cbf69c7cce53e974316dbf38d3dc"> 9765</a></span><span class="preprocessor">#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk </span></div>
|
||
<div class="line"><a id="l09766" name="l09766"></a><span class="lineno"> 9766</span> </div>
|
||
<div class="line"><a id="l09767" name="l09767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1baeac3a2504113deb0a65d46d7314e2"> 9767</a></span><span class="preprocessor">#define RCC_CIR_LSIRDYC_Pos (16U) </span></div>
|
||
<div class="line"><a id="l09768" name="l09768"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11edf191b118ca860e0eca011f113ad9"> 9768</a></span><span class="preprocessor">#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) </span></div>
|
||
<div class="line"><a id="l09769" name="l09769"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga982989563f1a95c89bf7f4a25d99f704"> 9769</a></span><span class="preprocessor">#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk </span></div>
|
||
<div class="line"><a id="l09770" name="l09770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f106e06b78f78c5a520faa1b180de2e"> 9770</a></span><span class="preprocessor">#define RCC_CIR_LSERDYC_Pos (17U) </span></div>
|
||
<div class="line"><a id="l09771" name="l09771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba1367e36a992aae85f9e8f9921e9426"> 9771</a></span><span class="preprocessor">#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) </span></div>
|
||
<div class="line"><a id="l09772" name="l09772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga144b5147f3a8d0bfda04618e301986aa"> 9772</a></span><span class="preprocessor">#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk </span></div>
|
||
<div class="line"><a id="l09773" name="l09773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2ccc89ed1b4d16c5f2804c216c5adc3"> 9773</a></span><span class="preprocessor">#define RCC_CIR_HSIRDYC_Pos (18U) </span></div>
|
||
<div class="line"><a id="l09774" name="l09774"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga657cffa4be41e26f7b5383719dd7781a"> 9774</a></span><span class="preprocessor">#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) </span></div>
|
||
<div class="line"><a id="l09775" name="l09775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1b58377908e5c31a684747d0a80ecb2"> 9775</a></span><span class="preprocessor">#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk </span></div>
|
||
<div class="line"><a id="l09776" name="l09776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34e713e2755ef1c9210e3b8c8f2c718e"> 9776</a></span><span class="preprocessor">#define RCC_CIR_HSERDYC_Pos (19U) </span></div>
|
||
<div class="line"><a id="l09777" name="l09777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2211dd40005f6152d0e8258d380a6713"> 9777</a></span><span class="preprocessor">#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) </span></div>
|
||
<div class="line"><a id="l09778" name="l09778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9464e8188d717902990b467a9396d238"> 9778</a></span><span class="preprocessor">#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk </span></div>
|
||
<div class="line"><a id="l09779" name="l09779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2884b24e49761690cfc68a9929c7b10d"> 9779</a></span><span class="preprocessor">#define RCC_CIR_PLLRDYC_Pos (20U) </span></div>
|
||
<div class="line"><a id="l09780" name="l09780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ee90d2a5649fe386ba87eeead64ada1"> 9780</a></span><span class="preprocessor">#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) </span></div>
|
||
<div class="line"><a id="l09781" name="l09781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga245af864b194f0c2b2389ea1ee49a396"> 9781</a></span><span class="preprocessor">#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk </span></div>
|
||
<div class="line"><a id="l09782" name="l09782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadca4503c3752588bd3efeea2b5f0c99a"> 9782</a></span><span class="preprocessor">#define RCC_CIR_PLLI2SRDYC_Pos (21U) </span></div>
|
||
<div class="line"><a id="l09783" name="l09783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6a1a17873c5e712e9ed47d92fbc99cd"> 9783</a></span><span class="preprocessor">#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos) </span></div>
|
||
<div class="line"><a id="l09784" name="l09784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73e79cc7236f5f76cb97c8012771e6bb"> 9784</a></span><span class="preprocessor">#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk </span></div>
|
||
<div class="line"><a id="l09785" name="l09785"></a><span class="lineno"> 9785</span> </div>
|
||
<div class="line"><a id="l09786" name="l09786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c7cf29f8c4b46a59751e6fdc44f8153"> 9786</a></span><span class="preprocessor">#define RCC_CIR_CSSC_Pos (23U) </span></div>
|
||
<div class="line"><a id="l09787" name="l09787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66a9cf76bbf90f432815527965cb5c3e"> 9787</a></span><span class="preprocessor">#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) </span></div>
|
||
<div class="line"><a id="l09788" name="l09788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46edb2b9568f002feba7b4312ed92c1f"> 9788</a></span><span class="preprocessor">#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk </span></div>
|
||
<div class="line"><a id="l09789" name="l09789"></a><span class="lineno"> 9789</span> </div>
|
||
<div class="line"><a id="l09790" name="l09790"></a><span class="lineno"> 9790</span><span class="comment">/******************** Bit definition for RCC_AHB1RSTR register **************/</span></div>
|
||
<div class="line"><a id="l09791" name="l09791"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1a30c30184844a5d3a71f73669375e7"> 9791</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOARST_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09792" name="l09792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ca733a89ed0ddeb8c6ad7d4df334baf"> 9792</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) </span></div>
|
||
<div class="line"><a id="l09793" name="l09793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c171937e46c2b9a58f16ee82010509e"> 9793</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk </span></div>
|
||
<div class="line"><a id="l09794" name="l09794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3154d462e29e472394d62113b4a3fadc"> 9794</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOBRST_Pos (1U) </span></div>
|
||
<div class="line"><a id="l09795" name="l09795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70a227671a2b417929ad0959d9e899c8"> 9795</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) </span></div>
|
||
<div class="line"><a id="l09796" name="l09796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e60d32cb67768339fc47a2ba11b7a97"> 9796</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk </span></div>
|
||
<div class="line"><a id="l09797" name="l09797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23de6a59e935f9e205e35aa713204d77"> 9797</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOCRST_Pos (2U) </span></div>
|
||
<div class="line"><a id="l09798" name="l09798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f25d081a1bb38f34f8d11fc32bdc7d7"> 9798</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) </span></div>
|
||
<div class="line"><a id="l09799" name="l09799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d02a09e1dafda744c7b27dca99fa3ef"> 9799</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk </span></div>
|
||
<div class="line"><a id="l09800" name="l09800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga296b1b5d6eaac638fc714115bb8fb79b"> 9800</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIODRST_Pos (3U) </span></div>
|
||
<div class="line"><a id="l09801" name="l09801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45e4b57d9e0d9c72055b51a222d388f5"> 9801</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) </span></div>
|
||
<div class="line"><a id="l09802" name="l09802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad16f3ce75bba03d8de4f5bc89c561337"> 9802</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk </span></div>
|
||
<div class="line"><a id="l09803" name="l09803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9d31d86453dfa221ced7ff4668a4b40"> 9803</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOERST_Pos (4U) </span></div>
|
||
<div class="line"><a id="l09804" name="l09804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2330cc824d6e097fc95f311730778243"> 9804</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) </span></div>
|
||
<div class="line"><a id="l09805" name="l09805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9baeb0fd247300501274a9259a4b184"> 9805</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk </span></div>
|
||
<div class="line"><a id="l09806" name="l09806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc279604f2a9a7f4bc29702d784cf22c"> 9806</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOFRST_Pos (5U) </span></div>
|
||
<div class="line"><a id="l09807" name="l09807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5758110647b39258af5b6c4259a59c0"> 9807</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) </span></div>
|
||
<div class="line"><a id="l09808" name="l09808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab00b21dc4408295d374a4970ea5ae751"> 9808</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk </span></div>
|
||
<div class="line"><a id="l09809" name="l09809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b38704ba9c53025641de7d5ed93add4"> 9809</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOGRST_Pos (6U) </span></div>
|
||
<div class="line"><a id="l09810" name="l09810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ca12c8d01be2d47518003a30d836a68"> 9810</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) </span></div>
|
||
<div class="line"><a id="l09811" name="l09811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50322b0db25b2204aa114c4c29847051"> 9811</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk </span></div>
|
||
<div class="line"><a id="l09812" name="l09812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada3768676df15e5d248404ba29df27ce"> 9812</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOHRST_Pos (7U) </span></div>
|
||
<div class="line"><a id="l09813" name="l09813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6853aabc577ec17d0d7f894e520a693"> 9813</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) </span></div>
|
||
<div class="line"><a id="l09814" name="l09814"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga587e3e32701cbd127d2afb19b9bff5fd"> 9814</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk </span></div>
|
||
<div class="line"><a id="l09815" name="l09815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf265743558660a1035f0456bede8322"> 9815</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOIRST_Pos (8U) </span></div>
|
||
<div class="line"><a id="l09816" name="l09816"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad771106a6653644a43c7d3d572d70220"> 9816</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) </span></div>
|
||
<div class="line"><a id="l09817" name="l09817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5180658a02a87b501ab3f250593905b"> 9817</a></span><span class="preprocessor">#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk </span></div>
|
||
<div class="line"><a id="l09818" name="l09818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga250ad2c8a4d0fbfd4360afcdce858075"> 9818</a></span><span class="preprocessor">#define RCC_AHB1RSTR_CRCRST_Pos (12U) </span></div>
|
||
<div class="line"><a id="l09819" name="l09819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf0f9e76b934af78155abddaacf568e4"> 9819</a></span><span class="preprocessor">#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) </span></div>
|
||
<div class="line"><a id="l09820" name="l09820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94f45f591e5e217833c6ab36a958543b"> 9820</a></span><span class="preprocessor">#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk </span></div>
|
||
<div class="line"><a id="l09821" name="l09821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga577ac0ee66f5e320ea4450234e709a03"> 9821</a></span><span class="preprocessor">#define RCC_AHB1RSTR_DMA1RST_Pos (21U) </span></div>
|
||
<div class="line"><a id="l09822" name="l09822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c336fca84fc656b8412d0a0dab8317e"> 9822</a></span><span class="preprocessor">#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) </span></div>
|
||
<div class="line"><a id="l09823" name="l09823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d1655ddfb777fce28b1d6b9a9c2d0e0"> 9823</a></span><span class="preprocessor">#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk </span></div>
|
||
<div class="line"><a id="l09824" name="l09824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16e38f17a99cc2e1f91d622f11ac8c89"> 9824</a></span><span class="preprocessor">#define RCC_AHB1RSTR_DMA2RST_Pos (22U) </span></div>
|
||
<div class="line"><a id="l09825" name="l09825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5e2d5af9f21f5df26e53863392f46ce"> 9825</a></span><span class="preprocessor">#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) </span></div>
|
||
<div class="line"><a id="l09826" name="l09826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga827aea44c35a0c3eb815a5d7d8546c7b"> 9826</a></span><span class="preprocessor">#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk </span></div>
|
||
<div class="line"><a id="l09827" name="l09827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e5a9384f957af95226d03414e7500e3"> 9827</a></span><span class="preprocessor">#define RCC_AHB1RSTR_ETHMACRST_Pos (25U) </span></div>
|
||
<div class="line"><a id="l09828" name="l09828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c088bbef40582644da68cebbce2c455"> 9828</a></span><span class="preprocessor">#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) </span></div>
|
||
<div class="line"><a id="l09829" name="l09829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e1dca7f08a971d2c3bf39a928c49586"> 9829</a></span><span class="preprocessor">#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk </span></div>
|
||
<div class="line"><a id="l09830" name="l09830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga355532707d1260d362e518e645be8753"> 9830</a></span><span class="preprocessor">#define RCC_AHB1RSTR_OTGHRST_Pos (29U) </span></div>
|
||
<div class="line"><a id="l09831" name="l09831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga351abffe0a0e32b6e74378a5e4b82a9e"> 9831</a></span><span class="preprocessor">#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos) </span></div>
|
||
<div class="line"><a id="l09832" name="l09832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga236682929d2641e851f175ab3aa1f520"> 9832</a></span><span class="preprocessor">#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk </span></div>
|
||
<div class="line"><a id="l09833" name="l09833"></a><span class="lineno"> 9833</span> </div>
|
||
<div class="line"><a id="l09834" name="l09834"></a><span class="lineno"> 9834</span><span class="comment">/******************** Bit definition for RCC_AHB2RSTR register **************/</span></div>
|
||
<div class="line"><a id="l09835" name="l09835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga457063d004551e2cce80472b190372c2"> 9835</a></span><span class="preprocessor">#define RCC_AHB2RSTR_DCMIRST_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09836" name="l09836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad65d3d99d10ccb38170740b9dbc30f0f"> 9836</a></span><span class="preprocessor">#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) </span></div>
|
||
<div class="line"><a id="l09837" name="l09837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae909f90338c129e116b7d49bebfb31c5"> 9837</a></span><span class="preprocessor">#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk </span></div>
|
||
<div class="line"><a id="l09838" name="l09838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadeefbc7de6773eedfba70fb6cd83890"> 9838</a></span><span class="preprocessor">#define RCC_AHB2RSTR_RNGRST_Pos (6U) </span></div>
|
||
<div class="line"><a id="l09839" name="l09839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ac557e9b39e599539fb5cc2a100de60"> 9839</a></span><span class="preprocessor">#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) </span></div>
|
||
<div class="line"><a id="l09840" name="l09840"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace46c6461c8b4ddd78510bc2c529c91b"> 9840</a></span><span class="preprocessor">#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk </span></div>
|
||
<div class="line"><a id="l09841" name="l09841"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f5fe9c74c695fe79917ce4828d2e24b"> 9841</a></span><span class="preprocessor">#define RCC_AHB2RSTR_OTGFSRST_Pos (7U) </span></div>
|
||
<div class="line"><a id="l09842" name="l09842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacba439d5c37535fc904630d55dd8d204"> 9842</a></span><span class="preprocessor">#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) </span></div>
|
||
<div class="line"><a id="l09843" name="l09843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1b8b894a2f1ea24b4799c7a30abbb5a"> 9843</a></span><span class="preprocessor">#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk </span></div>
|
||
<div class="line"><a id="l09844" name="l09844"></a><span class="lineno"> 9844</span><span class="comment">/******************** Bit definition for RCC_AHB3RSTR register **************/</span></div>
|
||
<div class="line"><a id="l09845" name="l09845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3aa38c40a38fe2a2e7d7bb26cdbfff36"> 9845</a></span><span class="preprocessor">#define RCC_AHB3RSTR_FSMCRST_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09846" name="l09846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab498285653979d8739b94dcbe1a32048"> 9846</a></span><span class="preprocessor">#define RCC_AHB3RSTR_FSMCRST_Msk (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos) </span></div>
|
||
<div class="line"><a id="l09847" name="l09847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga915aa42b819649f5ee7abdf5319d6bb8"> 9847</a></span><span class="preprocessor">#define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk </span></div>
|
||
<div class="line"><a id="l09848" name="l09848"></a><span class="lineno"> 9848</span> </div>
|
||
<div class="line"><a id="l09849" name="l09849"></a><span class="lineno"> 9849</span> </div>
|
||
<div class="line"><a id="l09850" name="l09850"></a><span class="lineno"> 9850</span><span class="comment">/******************** Bit definition for RCC_APB1RSTR register **************/</span></div>
|
||
<div class="line"><a id="l09851" name="l09851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef7278dbd9406107fbccefa358501f2c"> 9851</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM2RST_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09852" name="l09852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4b0f4bc33ed5d6d5806e5074349bedb"> 9852</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) </span></div>
|
||
<div class="line"><a id="l09853" name="l09853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51ca4659706d0e00333d4abff049dc0d"> 9853</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk </span></div>
|
||
<div class="line"><a id="l09854" name="l09854"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28531a8d644672fa950cce78175c3fc0"> 9854</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM3RST_Pos (1U) </span></div>
|
||
<div class="line"><a id="l09855" name="l09855"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f1a098d575d81ac443b3d6f837a09e1"> 9855</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) </span></div>
|
||
<div class="line"><a id="l09856" name="l09856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8680c562fd372b494a160594525d7ce9"> 9856</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk </span></div>
|
||
<div class="line"><a id="l09857" name="l09857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfd941245012a7ff32409d3858a0c369"> 9857</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM4RST_Pos (2U) </span></div>
|
||
<div class="line"><a id="l09858" name="l09858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1adc26ee7ca9aeb6316ca372633c95e"> 9858</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) </span></div>
|
||
<div class="line"><a id="l09859" name="l09859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a720364de988965b6d2f91ed6519570"> 9859</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk </span></div>
|
||
<div class="line"><a id="l09860" name="l09860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ec5440469b072778617b76dd55faf23"> 9860</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM5RST_Pos (3U) </span></div>
|
||
<div class="line"><a id="l09861" name="l09861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a5cfd79c37096bf00916e7bda1df220"> 9861</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) </span></div>
|
||
<div class="line"><a id="l09862" name="l09862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d1233dd5266ba55d9951e3b1a334552"> 9862</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk </span></div>
|
||
<div class="line"><a id="l09863" name="l09863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f910529f471272ed5218c5067115cc8"> 9863</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM6RST_Pos (4U) </span></div>
|
||
<div class="line"><a id="l09864" name="l09864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f222bd16fca5ae0a0475a83f9a69d0f"> 9864</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) </span></div>
|
||
<div class="line"><a id="l09865" name="l09865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d64bd82cf47a209afebc7d663e28383"> 9865</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk </span></div>
|
||
<div class="line"><a id="l09866" name="l09866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga033243ec3d5cdaa7030b8b38d39e9989"> 9866</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM7RST_Pos (5U) </span></div>
|
||
<div class="line"><a id="l09867" name="l09867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9af08f1ff685c0027708d909086b748"> 9867</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) </span></div>
|
||
<div class="line"><a id="l09868" name="l09868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40b1d355ee76ad9a044ad37f1629e760"> 9868</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk </span></div>
|
||
<div class="line"><a id="l09869" name="l09869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5874ca2fef163308e575153b945eaa53"> 9869</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM12RST_Pos (6U) </span></div>
|
||
<div class="line"><a id="l09870" name="l09870"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91170571df0e2ed7675a5b3091736507"> 9870</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) </span></div>
|
||
<div class="line"><a id="l09871" name="l09871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga067deb756dd4100c901c6b25229678e4"> 9871</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk </span></div>
|
||
<div class="line"><a id="l09872" name="l09872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4a9d1c4213a8dc4484ba58f49433806"> 9872</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM13RST_Pos (7U) </span></div>
|
||
<div class="line"><a id="l09873" name="l09873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1b75cafab3889092a34ddfb502c5d6a"> 9873</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) </span></div>
|
||
<div class="line"><a id="l09874" name="l09874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad59f66b35bdc0953428eb8c345397a7f"> 9874</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk </span></div>
|
||
<div class="line"><a id="l09875" name="l09875"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafced8b214c9803f4961f1f4f1324f28f"> 9875</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM14RST_Pos (8U) </span></div>
|
||
<div class="line"><a id="l09876" name="l09876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1887a28578dd003746b62f95b48d06a"> 9876</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) </span></div>
|
||
<div class="line"><a id="l09877" name="l09877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga773e6d5b419eb2d4b6291c862e04b002"> 9877</a></span><span class="preprocessor">#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk </span></div>
|
||
<div class="line"><a id="l09878" name="l09878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9d96e880c3040ba8dbe155a6129ca69"> 9878</a></span><span class="preprocessor">#define RCC_APB1RSTR_WWDGRST_Pos (11U) </span></div>
|
||
<div class="line"><a id="l09879" name="l09879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga919c04abb655aa94b244dcebbf647748"> 9879</a></span><span class="preprocessor">#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) </span></div>
|
||
<div class="line"><a id="l09880" name="l09880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d2591ac0655a8798f4c16cef97e6f94"> 9880</a></span><span class="preprocessor">#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk </span></div>
|
||
<div class="line"><a id="l09881" name="l09881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga148b63aa15907eac1bd4894a7c157100"> 9881</a></span><span class="preprocessor">#define RCC_APB1RSTR_SPI2RST_Pos (14U) </span></div>
|
||
<div class="line"><a id="l09882" name="l09882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae378c28cf590c56f5487bd92705d6d54"> 9882</a></span><span class="preprocessor">#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) </span></div>
|
||
<div class="line"><a id="l09883" name="l09883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a6289a35547cf0d5300706f9baa18ea"> 9883</a></span><span class="preprocessor">#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk </span></div>
|
||
<div class="line"><a id="l09884" name="l09884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9458442b1f7afb7bb8c858eceb8a7e22"> 9884</a></span><span class="preprocessor">#define RCC_APB1RSTR_SPI3RST_Pos (15U) </span></div>
|
||
<div class="line"><a id="l09885" name="l09885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0566a08a6cbd33046ff893d7c3b7bf1"> 9885</a></span><span class="preprocessor">#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) </span></div>
|
||
<div class="line"><a id="l09886" name="l09886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga261e0f1b39cd1cab41ec6bf40c21867b"> 9886</a></span><span class="preprocessor">#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk </span></div>
|
||
<div class="line"><a id="l09887" name="l09887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2ca9ee6dbf794ec18d25721123a1119"> 9887</a></span><span class="preprocessor">#define RCC_APB1RSTR_USART2RST_Pos (17U) </span></div>
|
||
<div class="line"><a id="l09888" name="l09888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0beb24842078f8a070ba7f96ca579f43"> 9888</a></span><span class="preprocessor">#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) </span></div>
|
||
<div class="line"><a id="l09889" name="l09889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga195c39f08384ca1fa13b53a31d65d0a5"> 9889</a></span><span class="preprocessor">#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk </span></div>
|
||
<div class="line"><a id="l09890" name="l09890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d88961277f1aaaaa0088ee671319522"> 9890</a></span><span class="preprocessor">#define RCC_APB1RSTR_USART3RST_Pos (18U) </span></div>
|
||
<div class="line"><a id="l09891" name="l09891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafe9da843ef3eb19c556b8eeed4e56bf"> 9891</a></span><span class="preprocessor">#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) </span></div>
|
||
<div class="line"><a id="l09892" name="l09892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga766478ebdcbb647eb3f32962543bd194"> 9892</a></span><span class="preprocessor">#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk </span></div>
|
||
<div class="line"><a id="l09893" name="l09893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff8420398d7b2ac7a1845643b0e2010b"> 9893</a></span><span class="preprocessor">#define RCC_APB1RSTR_UART4RST_Pos (19U) </span></div>
|
||
<div class="line"><a id="l09894" name="l09894"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c84c3ac04f075c4571c4518e9dc6f5d"> 9894</a></span><span class="preprocessor">#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) </span></div>
|
||
<div class="line"><a id="l09895" name="l09895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0802e99fa9eb9388393af3135ca2cb2b"> 9895</a></span><span class="preprocessor">#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk </span></div>
|
||
<div class="line"><a id="l09896" name="l09896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddedfda3a5db9ea42104b43d23a64495"> 9896</a></span><span class="preprocessor">#define RCC_APB1RSTR_UART5RST_Pos (20U) </span></div>
|
||
<div class="line"><a id="l09897" name="l09897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5aaecac95d9e201eb6a3ee127881381b"> 9897</a></span><span class="preprocessor">#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) </span></div>
|
||
<div class="line"><a id="l09898" name="l09898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e4d54359192c58725e5ece2b539f8ee"> 9898</a></span><span class="preprocessor">#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk </span></div>
|
||
<div class="line"><a id="l09899" name="l09899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3f6df08a3eae853a3fc8b2d0fcc0882"> 9899</a></span><span class="preprocessor">#define RCC_APB1RSTR_I2C1RST_Pos (21U) </span></div>
|
||
<div class="line"><a id="l09900" name="l09900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95fda0adab6e9d4daa6417c17d905214"> 9900</a></span><span class="preprocessor">#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) </span></div>
|
||
<div class="line"><a id="l09901" name="l09901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcd25346a7d7b0009090adfbca899b93"> 9901</a></span><span class="preprocessor">#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk </span></div>
|
||
<div class="line"><a id="l09902" name="l09902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a1c1f07b2b2cc274c0b297d779b936f"> 9902</a></span><span class="preprocessor">#define RCC_APB1RSTR_I2C2RST_Pos (22U) </span></div>
|
||
<div class="line"><a id="l09903" name="l09903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga914a46fcb3b028610d9badb471c82bd3"> 9903</a></span><span class="preprocessor">#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) </span></div>
|
||
<div class="line"><a id="l09904" name="l09904"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga412d59407e5dad43cf8ae1ea6f8bc5c3"> 9904</a></span><span class="preprocessor">#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk </span></div>
|
||
<div class="line"><a id="l09905" name="l09905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53079edbe7a089db7497d49b242b7e53"> 9905</a></span><span class="preprocessor">#define RCC_APB1RSTR_I2C3RST_Pos (23U) </span></div>
|
||
<div class="line"><a id="l09906" name="l09906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49214147f146965ef75c3bfa906cd3d9"> 9906</a></span><span class="preprocessor">#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) </span></div>
|
||
<div class="line"><a id="l09907" name="l09907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8dd6bd89cdf6b6b7affee5594bda87f"> 9907</a></span><span class="preprocessor">#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk </span></div>
|
||
<div class="line"><a id="l09908" name="l09908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ac1f35767bba5fa2ab823d17dcf9b31"> 9908</a></span><span class="preprocessor">#define RCC_APB1RSTR_CAN1RST_Pos (25U) </span></div>
|
||
<div class="line"><a id="l09909" name="l09909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91aa2d3e18674c6f02c7112da9a2e30c"> 9909</a></span><span class="preprocessor">#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) </span></div>
|
||
<div class="line"><a id="l09910" name="l09910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23f9a8bfc02baedd992d13e489234242"> 9910</a></span><span class="preprocessor">#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk </span></div>
|
||
<div class="line"><a id="l09911" name="l09911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5695d6d01e07d1aba83edb9614fd108"> 9911</a></span><span class="preprocessor">#define RCC_APB1RSTR_CAN2RST_Pos (26U) </span></div>
|
||
<div class="line"><a id="l09912" name="l09912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86dc2776b9926f9335e72b433290bb8a"> 9912</a></span><span class="preprocessor">#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos) </span></div>
|
||
<div class="line"><a id="l09913" name="l09913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86b5d7042e23d54c7ecfcef2fbedad6e"> 9913</a></span><span class="preprocessor">#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk </span></div>
|
||
<div class="line"><a id="l09914" name="l09914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48d1ad283fb0cc11c6394cc28e4da4d0"> 9914</a></span><span class="preprocessor">#define RCC_APB1RSTR_PWRRST_Pos (28U) </span></div>
|
||
<div class="line"><a id="l09915" name="l09915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe9ed6c6cee6df40b16793fe7479ea7a"> 9915</a></span><span class="preprocessor">#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) </span></div>
|
||
<div class="line"><a id="l09916" name="l09916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga274d8cb48f0e89831efabea66d64af2a"> 9916</a></span><span class="preprocessor">#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk </span></div>
|
||
<div class="line"><a id="l09917" name="l09917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0612cbad1c01508c2c3acd8502a16f76"> 9917</a></span><span class="preprocessor">#define RCC_APB1RSTR_DACRST_Pos (29U) </span></div>
|
||
<div class="line"><a id="l09918" name="l09918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09759c3881f10d9210653490a651f995"> 9918</a></span><span class="preprocessor">#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) </span></div>
|
||
<div class="line"><a id="l09919" name="l09919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fb9c125237cfe5b6436ca795e7f3564"> 9919</a></span><span class="preprocessor">#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk </span></div>
|
||
<div class="line"><a id="l09920" name="l09920"></a><span class="lineno"> 9920</span> </div>
|
||
<div class="line"><a id="l09921" name="l09921"></a><span class="lineno"> 9921</span><span class="comment">/******************** Bit definition for RCC_APB2RSTR register **************/</span></div>
|
||
<div class="line"><a id="l09922" name="l09922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3439757d01e0c351ad8bc0193e3d90e"> 9922</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM1RST_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09923" name="l09923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fc9f88241816d51a87a8b4a537c5a2e"> 9923</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) </span></div>
|
||
<div class="line"><a id="l09924" name="l09924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bd060cbefaef05487963bbd6c48d7c6"> 9924</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk </span></div>
|
||
<div class="line"><a id="l09925" name="l09925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaab98fc817a93527229f575e6b642969"> 9925</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM8RST_Pos (1U) </span></div>
|
||
<div class="line"><a id="l09926" name="l09926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab14242f5f656c5860137bd75f2a0515e"> 9926</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) </span></div>
|
||
<div class="line"><a id="l09927" name="l09927"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa129b34dbaf6c5301f751410ab4668ca"> 9927</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk </span></div>
|
||
<div class="line"><a id="l09928" name="l09928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac07b0f4aae1366a80486993aa71c6237"> 9928</a></span><span class="preprocessor">#define RCC_APB2RSTR_USART1RST_Pos (4U) </span></div>
|
||
<div class="line"><a id="l09929" name="l09929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49f18e05ca4a63d5b8fe937eb8613005"> 9929</a></span><span class="preprocessor">#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) </span></div>
|
||
<div class="line"><a id="l09930" name="l09930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7ae8e338b3b42ad037e9e5b6eeb2c41"> 9930</a></span><span class="preprocessor">#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk </span></div>
|
||
<div class="line"><a id="l09931" name="l09931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1aa2e760b59afddec0efc53fd80e60bf"> 9931</a></span><span class="preprocessor">#define RCC_APB2RSTR_USART6RST_Pos (5U) </span></div>
|
||
<div class="line"><a id="l09932" name="l09932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63e37e8ac731047e3df29ca5c7e553cc"> 9932</a></span><span class="preprocessor">#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) </span></div>
|
||
<div class="line"><a id="l09933" name="l09933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada1df682293e15ed44b081d626220178"> 9933</a></span><span class="preprocessor">#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk </span></div>
|
||
<div class="line"><a id="l09934" name="l09934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb93c28e2b44e753d961ee83fb829ad0"> 9934</a></span><span class="preprocessor">#define RCC_APB2RSTR_ADCRST_Pos (8U) </span></div>
|
||
<div class="line"><a id="l09935" name="l09935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a4836f2cd9be43193d6eb4d19d5dde6"> 9935</a></span><span class="preprocessor">#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) </span></div>
|
||
<div class="line"><a id="l09936" name="l09936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1374d6eae8e7d02d1ad457b65f374a67"> 9936</a></span><span class="preprocessor">#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk </span></div>
|
||
<div class="line"><a id="l09937" name="l09937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga964b8835939769ac1b9bd4984854757d"> 9937</a></span><span class="preprocessor">#define RCC_APB2RSTR_SDIORST_Pos (11U) </span></div>
|
||
<div class="line"><a id="l09938" name="l09938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae67f4f982e0636f1d86be7d4223cdaf1"> 9938</a></span><span class="preprocessor">#define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos) </span></div>
|
||
<div class="line"><a id="l09939" name="l09939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga754451a96f4c4faf63a29ca1a132c64d"> 9939</a></span><span class="preprocessor">#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk </span></div>
|
||
<div class="line"><a id="l09940" name="l09940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f284f64839f82231c3e375e01105946"> 9940</a></span><span class="preprocessor">#define RCC_APB2RSTR_SPI1RST_Pos (12U) </span></div>
|
||
<div class="line"><a id="l09941" name="l09941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4fb7fb16a3052da4a7d11cbdbe838689"> 9941</a></span><span class="preprocessor">#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) </span></div>
|
||
<div class="line"><a id="l09942" name="l09942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga345f05d3508a9fd5128208761feb29fb"> 9942</a></span><span class="preprocessor">#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk </span></div>
|
||
<div class="line"><a id="l09943" name="l09943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga613a32917030cbb38e7897bdec0cad47"> 9943</a></span><span class="preprocessor">#define RCC_APB2RSTR_SYSCFGRST_Pos (14U) </span></div>
|
||
<div class="line"><a id="l09944" name="l09944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89f656408c45d2f67a99cc1c093d3e45"> 9944</a></span><span class="preprocessor">#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) </span></div>
|
||
<div class="line"><a id="l09945" name="l09945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga813d42b8d48ae6379c053a44870af49d"> 9945</a></span><span class="preprocessor">#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk </span></div>
|
||
<div class="line"><a id="l09946" name="l09946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed9b13161f4dbf0f960abe15c7f9f045"> 9946</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM9RST_Pos (16U) </span></div>
|
||
<div class="line"><a id="l09947" name="l09947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad71d516052c6afded3292ada76c392a2"> 9947</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) </span></div>
|
||
<div class="line"><a id="l09948" name="l09948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3aa588d4814a289d939e111492724af"> 9948</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk </span></div>
|
||
<div class="line"><a id="l09949" name="l09949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01379fcaf1119cd7a25cdf930fe10458"> 9949</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM10RST_Pos (17U) </span></div>
|
||
<div class="line"><a id="l09950" name="l09950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga077ef7ed92b0241e49f2ecad1a8bd241"> 9950</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) </span></div>
|
||
<div class="line"><a id="l09951" name="l09951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac76155acdc99c8c6502ba3beba818f42"> 9951</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk </span></div>
|
||
<div class="line"><a id="l09952" name="l09952"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d1b402b6082b891cf838cc69119b2a1"> 9952</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM11RST_Pos (18U) </span></div>
|
||
<div class="line"><a id="l09953" name="l09953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ffe8d460fb9abc55ec65d00d39564b3"> 9953</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) </span></div>
|
||
<div class="line"><a id="l09954" name="l09954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9651c8201d42ba03bb1bf89d9d39e60c"> 9954</a></span><span class="preprocessor">#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk </span></div>
|
||
<div class="line"><a id="l09955" name="l09955"></a><span class="lineno"> 9955</span> </div>
|
||
<div class="line"><a id="l09956" name="l09956"></a><span class="lineno"> 9956</span><span class="comment">/* Old SPI1RST bit definition, maintained for legacy purpose */</span></div>
|
||
<div class="line"><a id="l09957" name="l09957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38f676c6c842fc9471d51a50584fbe91"> 9957</a></span><span class="preprocessor">#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST</span></div>
|
||
<div class="line"><a id="l09958" name="l09958"></a><span class="lineno"> 9958</span> </div>
|
||
<div class="line"><a id="l09959" name="l09959"></a><span class="lineno"> 9959</span><span class="comment">/******************** Bit definition for RCC_AHB1ENR register ***************/</span></div>
|
||
<div class="line"><a id="l09960" name="l09960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46ac0ea3dfd9fd9dc25a6fc974c0b2e7"> 9960</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOAEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l09961" name="l09961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1610c0bcc3f778000c9ffe4ceaaf7a8"> 9961</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos) </span></div>
|
||
<div class="line"><a id="l09962" name="l09962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ff46fb3b30fc6792e4fd18fcb0941b5"> 9962</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk </span></div>
|
||
<div class="line"><a id="l09963" name="l09963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e283561bd4c7f47c8ba5a3affae294a"> 9963</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOBEN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l09964" name="l09964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79f6e5e212dee1b54f1103aa6c5b63c8"> 9964</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos) </span></div>
|
||
<div class="line"><a id="l09965" name="l09965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7f408f92e7fd49b0957b8cb4ff31ca5"> 9965</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk </span></div>
|
||
<div class="line"><a id="l09966" name="l09966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b008be82ceb7ff8fc8b5b89c42d5956"> 9966</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOCEN_Pos (2U) </span></div>
|
||
<div class="line"><a id="l09967" name="l09967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d7e8d23a1214b25dca4d0838324371b"> 9967</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos) </span></div>
|
||
<div class="line"><a id="l09968" name="l09968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8a8b42e33aef2a7bc2d41ad9d231733"> 9968</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk </span></div>
|
||
<div class="line"><a id="l09969" name="l09969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57c3badb1f83e08ab09719c58d70e1b4"> 9969</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIODEN_Pos (3U) </span></div>
|
||
<div class="line"><a id="l09970" name="l09970"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5da72a3a599290c99b251cf0e40d579a"> 9970</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos) </span></div>
|
||
<div class="line"><a id="l09971" name="l09971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebd8146e91c76f14af8dfe78a1c2d916"> 9971</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk </span></div>
|
||
<div class="line"><a id="l09972" name="l09972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2313a0beb0ceb64be0c3c2906c9d11c1"> 9972</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOEEN_Pos (4U) </span></div>
|
||
<div class="line"><a id="l09973" name="l09973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga574a0ff2d711679c81d62a365efe9b25"> 9973</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos) </span></div>
|
||
<div class="line"><a id="l09974" name="l09974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67a9094e0e464eaa8e25f854f90abfc6"> 9974</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk </span></div>
|
||
<div class="line"><a id="l09975" name="l09975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga086e36c7f473c1290b8b837dbb6cefbd"> 9975</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOFEN_Pos (5U) </span></div>
|
||
<div class="line"><a id="l09976" name="l09976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac40bd7a86de787e99ecf69881e8d8803"> 9976</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) </span></div>
|
||
<div class="line"><a id="l09977" name="l09977"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefa8e0fbecedb4167a4d7ef51e2a48b5"> 9977</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk </span></div>
|
||
<div class="line"><a id="l09978" name="l09978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga746fd16f381b86d549e73d73977b408d"> 9978</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOGEN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l09979" name="l09979"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84f85f90ddfceebacab190e14cf0de75"> 9979</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos) </span></div>
|
||
<div class="line"><a id="l09980" name="l09980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5304e897036391c916ef82258919a08b"> 9980</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk </span></div>
|
||
<div class="line"><a id="l09981" name="l09981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37d856370c08a4704127d615939510e8"> 9981</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOHEN_Pos (7U) </span></div>
|
||
<div class="line"><a id="l09982" name="l09982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee11e4e6ddeff9db3ddd22873d1ca8d5"> 9982</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos) </span></div>
|
||
<div class="line"><a id="l09983" name="l09983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb16afc550121895822ebb22108196b6"> 9983</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk </span></div>
|
||
<div class="line"><a id="l09984" name="l09984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea6afabe8b46415f972a1e54a605decf"> 9984</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOIEN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l09985" name="l09985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d542abb9e4477f575afe1066062ce34"> 9985</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos) </span></div>
|
||
<div class="line"><a id="l09986" name="l09986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadee44347a6a62429ee74753fe1dea5d7"> 9986</a></span><span class="preprocessor">#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk </span></div>
|
||
<div class="line"><a id="l09987" name="l09987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf0c26180146aedeec41861fd765a05c"> 9987</a></span><span class="preprocessor">#define RCC_AHB1ENR_CRCEN_Pos (12U) </span></div>
|
||
<div class="line"><a id="l09988" name="l09988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b467a2c6329ecb8ca42c1d9e1116035"> 9988</a></span><span class="preprocessor">#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) </span></div>
|
||
<div class="line"><a id="l09989" name="l09989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa3d41f31401e812f839defee241df83"> 9989</a></span><span class="preprocessor">#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk </span></div>
|
||
<div class="line"><a id="l09990" name="l09990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6732dcee9b2bf278527a55f9c14d703c"> 9990</a></span><span class="preprocessor">#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U) </span></div>
|
||
<div class="line"><a id="l09991" name="l09991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67735d069e447a3cbd8b1cf0ac1e69ca"> 9991</a></span><span class="preprocessor">#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) </span></div>
|
||
<div class="line"><a id="l09992" name="l09992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee10e5e11a2043e4ff865c3d7b804233"> 9992</a></span><span class="preprocessor">#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk </span></div>
|
||
<div class="line"><a id="l09993" name="l09993"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac74e8dc5505978a1b2cb109d0c77c559"> 9993</a></span><span class="preprocessor">#define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U) </span></div>
|
||
<div class="line"><a id="l09994" name="l09994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae56a123a2131232460f2a1d4d7b5fb87"> 9994</a></span><span class="preprocessor">#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos) </span></div>
|
||
<div class="line"><a id="l09995" name="l09995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29bbdcc191708a9e6a46ef197a3b2c65"> 9995</a></span><span class="preprocessor">#define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk </span></div>
|
||
<div class="line"><a id="l09996" name="l09996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0114d8249d989c5ab3feac252e30509e"> 9996</a></span><span class="preprocessor">#define RCC_AHB1ENR_DMA1EN_Pos (21U) </span></div>
|
||
<div class="line"><a id="l09997" name="l09997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab04b66dc0d69d098db894416722e9871"> 9997</a></span><span class="preprocessor">#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) </span></div>
|
||
<div class="line"><a id="l09998" name="l09998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae07b00778a51a4e52b911aeccb897aba"> 9998</a></span><span class="preprocessor">#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk </span></div>
|
||
<div class="line"><a id="l09999" name="l09999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf754f312ede73c0d5d35e1a08b614f94"> 9999</a></span><span class="preprocessor">#define RCC_AHB1ENR_DMA2EN_Pos (22U) </span></div>
|
||
<div class="line"><a id="l10000" name="l10000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb95b569d5ea1d4c9483fbfd7df37f3a">10000</a></span><span class="preprocessor">#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) </span></div>
|
||
<div class="line"><a id="l10001" name="l10001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga664a5d572a39a0c084e4ee7c1cf7df0d">10001</a></span><span class="preprocessor">#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk </span></div>
|
||
<div class="line"><a id="l10002" name="l10002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43785491862d48d7a9f0651f6e94a388">10002</a></span><span class="preprocessor">#define RCC_AHB1ENR_ETHMACEN_Pos (25U) </span></div>
|
||
<div class="line"><a id="l10003" name="l10003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7f4087101bf2a82c3ac9ea31ca3504f">10003</a></span><span class="preprocessor">#define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos) </span></div>
|
||
<div class="line"><a id="l10004" name="l10004"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga507020c3c3945dfbf3d628ffa42afdba">10004</a></span><span class="preprocessor">#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk </span></div>
|
||
<div class="line"><a id="l10005" name="l10005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab032942ed246f6386d792915da6519e7">10005</a></span><span class="preprocessor">#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U) </span></div>
|
||
<div class="line"><a id="l10006" name="l10006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7e9fa8c5b341bd2c8e1354ea0452990">10006</a></span><span class="preprocessor">#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) </span></div>
|
||
<div class="line"><a id="l10007" name="l10007"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga001f617c29d950ee1aa91773331ae6f6">10007</a></span><span class="preprocessor">#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk </span></div>
|
||
<div class="line"><a id="l10008" name="l10008"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac12dfc1c179aa47c0bf97a005974182e">10008</a></span><span class="preprocessor">#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U) </span></div>
|
||
<div class="line"><a id="l10009" name="l10009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9872ba78cf86d347267020336489be40">10009</a></span><span class="preprocessor">#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) </span></div>
|
||
<div class="line"><a id="l10010" name="l10010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8933482a90a769d0cdd332b170132b77">10010</a></span><span class="preprocessor">#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk </span></div>
|
||
<div class="line"><a id="l10011" name="l10011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9bedafca82770123ee737720df26612e">10011</a></span><span class="preprocessor">#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U) </span></div>
|
||
<div class="line"><a id="l10012" name="l10012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41c39ec61603f15cf1916d743f1e3673">10012</a></span><span class="preprocessor">#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10013" name="l10013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bf11a8d105bc59e4f509d91cbf05e0e">10013</a></span><span class="preprocessor">#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk </span></div>
|
||
<div class="line"><a id="l10014" name="l10014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd0aa66629d449a07dea64c30ca67c5e">10014</a></span><span class="preprocessor">#define RCC_AHB1ENR_OTGHSEN_Pos (29U) </span></div>
|
||
<div class="line"><a id="l10015" name="l10015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44e119c40f74b0caf89d18b8e784d7cd">10015</a></span><span class="preprocessor">#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos) </span></div>
|
||
<div class="line"><a id="l10016" name="l10016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab18d15ea68876f7a42ee7350074b05f4">10016</a></span><span class="preprocessor">#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk </span></div>
|
||
<div class="line"><a id="l10017" name="l10017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga073b5e5498b3a169555570dc126d11fb">10017</a></span><span class="preprocessor">#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U) </span></div>
|
||
<div class="line"><a id="l10018" name="l10018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga162543647ebac3ea7cf992bf229acb56">10018</a></span><span class="preprocessor">#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) </span></div>
|
||
<div class="line"><a id="l10019" name="l10019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga784be313f54862d3670723f2334fa51f">10019</a></span><span class="preprocessor">#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk </span></div>
|
||
<div class="line"><a id="l10020" name="l10020"></a><span class="lineno">10020</span><span class="comment">/******************** Bit definition for RCC_AHB2ENR register ***************/</span></div>
|
||
<div class="line"><a id="l10021" name="l10021"></a><span class="lineno">10021</span><span class="comment">/*</span></div>
|
||
<div class="line"><a id="l10022" name="l10022"></a><span class="lineno">10022</span><span class="comment"> * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)</span></div>
|
||
<div class="line"><a id="l10023" name="l10023"></a><span class="lineno">10023</span><span class="comment"> */</span></div>
|
||
<div class="line"><a id="l10024" name="l10024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad47614352bcc5025572abc4277cf28e9">10024</a></span><span class="preprocessor">#define RCC_AHB2_SUPPORT </span></div>
|
||
<div class="line"><a id="l10026" name="l10026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2491b75f6353ed39e93a2c9e8ea81052">10026</a></span><span class="preprocessor">#define RCC_AHB2ENR_DCMIEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10027" name="l10027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga392371f5ae1fc6417aa8111e46184b17">10027</a></span><span class="preprocessor">#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) </span></div>
|
||
<div class="line"><a id="l10028" name="l10028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe6b7edde44307072327fcae3c15c8d0">10028</a></span><span class="preprocessor">#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk </span></div>
|
||
<div class="line"><a id="l10029" name="l10029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf92e60b54c63999846b0e8392131a6c">10029</a></span><span class="preprocessor">#define RCC_AHB2ENR_RNGEN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l10030" name="l10030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe2170ecd918ffe5d888e76c3dcd5cab">10030</a></span><span class="preprocessor">#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) </span></div>
|
||
<div class="line"><a id="l10031" name="l10031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadea5123ece7df53e695697e3a7d11a6b">10031</a></span><span class="preprocessor">#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk </span></div>
|
||
<div class="line"><a id="l10032" name="l10032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80a6b042ea1a1362cba76f697a2b941c">10032</a></span><span class="preprocessor">#define RCC_AHB2ENR_OTGFSEN_Pos (7U) </span></div>
|
||
<div class="line"><a id="l10033" name="l10033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c92c5e4271a2a493a92fb41fbc7e3fd">10033</a></span><span class="preprocessor">#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos) </span></div>
|
||
<div class="line"><a id="l10034" name="l10034"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22576caeba7c7a1e6afdd0b90394c76d">10034</a></span><span class="preprocessor">#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk </span></div>
|
||
<div class="line"><a id="l10035" name="l10035"></a><span class="lineno">10035</span> </div>
|
||
<div class="line"><a id="l10036" name="l10036"></a><span class="lineno">10036</span><span class="comment">/******************** Bit definition for RCC_AHB3ENR register ***************/</span></div>
|
||
<div class="line"><a id="l10037" name="l10037"></a><span class="lineno">10037</span><span class="comment">/*</span></div>
|
||
<div class="line"><a id="l10038" name="l10038"></a><span class="lineno">10038</span><span class="comment"> * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)</span></div>
|
||
<div class="line"><a id="l10039" name="l10039"></a><span class="lineno">10039</span><span class="comment"> */</span></div>
|
||
<div class="line"><a id="l10040" name="l10040"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab59e70532c57e0a7917acac00de9db57">10040</a></span><span class="preprocessor">#define RCC_AHB3_SUPPORT </span></div>
|
||
<div class="line"><a id="l10042" name="l10042"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa90ab430537857e2683deb2c628a4ca7">10042</a></span><span class="preprocessor">#define RCC_AHB3ENR_FSMCEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10043" name="l10043"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga518c0730a8f98a8b8ed6f75f0101f7fb">10043</a></span><span class="preprocessor">#define RCC_AHB3ENR_FSMCEN_Msk (0x1UL << RCC_AHB3ENR_FSMCEN_Pos) </span></div>
|
||
<div class="line"><a id="l10044" name="l10044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30d723abc39a230a71760dff91bb6d7b">10044</a></span><span class="preprocessor">#define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk </span></div>
|
||
<div class="line"><a id="l10045" name="l10045"></a><span class="lineno">10045</span> </div>
|
||
<div class="line"><a id="l10046" name="l10046"></a><span class="lineno">10046</span><span class="comment">/******************** Bit definition for RCC_APB1ENR register ***************/</span></div>
|
||
<div class="line"><a id="l10047" name="l10047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7c1e030bdf85faeae65b74850497e29">10047</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM2EN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10048" name="l10048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ed542e8a186c731ad3221c61b4aa81a">10048</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) </span></div>
|
||
<div class="line"><a id="l10049" name="l10049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd3966a4d6ae47f06b3c095eaf26a610">10049</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk </span></div>
|
||
<div class="line"><a id="l10050" name="l10050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga512bf591e0527e83b8ae823c42da2f1e">10050</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM3EN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l10051" name="l10051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39d58d377cd38e5685344b7d9a88ce1c">10051</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) </span></div>
|
||
<div class="line"><a id="l10052" name="l10052"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75bfa33eb00ee30c6e22f7ceea464ac7">10052</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk </span></div>
|
||
<div class="line"><a id="l10053" name="l10053"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad32ced9621c44cd74f36cbfdec22582e">10053</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM4EN_Pos (2U) </span></div>
|
||
<div class="line"><a id="l10054" name="l10054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef489da1fe7bd776d2fc27eb689fd9c4">10054</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) </span></div>
|
||
<div class="line"><a id="l10055" name="l10055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4fbbf6b1beeec92c7d80e9e05bd1461">10055</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk </span></div>
|
||
<div class="line"><a id="l10056" name="l10056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9022ea1b9729864c70216a4f04326f22">10056</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM5EN_Pos (3U) </span></div>
|
||
<div class="line"><a id="l10057" name="l10057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50e3f7f788191131f045cd40594e5c15">10057</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) </span></div>
|
||
<div class="line"><a id="l10058" name="l10058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49abbbc8fd297c544df2d337b28f80e4">10058</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk </span></div>
|
||
<div class="line"><a id="l10059" name="l10059"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae48475ae28539f1a2ce3852fbd7c1e71">10059</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM6EN_Pos (4U) </span></div>
|
||
<div class="line"><a id="l10060" name="l10060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34240ad1a5f4eb5ed19e7104da631d1e">10060</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) </span></div>
|
||
<div class="line"><a id="l10061" name="l10061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb0279b1f0ff35c2df728d9653cabc0c">10061</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk </span></div>
|
||
<div class="line"><a id="l10062" name="l10062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c3d0403cb8a2a9daa5f789e3547d27d">10062</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM7EN_Pos (5U) </span></div>
|
||
<div class="line"><a id="l10063" name="l10063"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d3160c7aa3480db783e4cc7f50ed721">10063</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) </span></div>
|
||
<div class="line"><a id="l10064" name="l10064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab595fbaf4167297d8fe2825e41f41990">10064</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk </span></div>
|
||
<div class="line"><a id="l10065" name="l10065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec84991ddba58f7037cd8113725a26f7">10065</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM12EN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l10066" name="l10066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabca933b42794cadbf3580851e625779e">10066</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos) </span></div>
|
||
<div class="line"><a id="l10067" name="l10067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecd88b56485ee4ee3e406b1d6c062081">10067</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk </span></div>
|
||
<div class="line"><a id="l10068" name="l10068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3865266fac7bea00e89cd1c19eb3b39f">10068</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM13EN_Pos (7U) </span></div>
|
||
<div class="line"><a id="l10069" name="l10069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c6f74911cd1852c3a58e969e48013d8">10069</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos) </span></div>
|
||
<div class="line"><a id="l10070" name="l10070"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a95079e68e7c76584ef0b3de371288a">10070</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk </span></div>
|
||
<div class="line"><a id="l10071" name="l10071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3341bca36df7d92a24e7e1355265421c">10071</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM14EN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l10072" name="l10072"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecb332ea40285657d968307a8cef8951">10072</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) </span></div>
|
||
<div class="line"><a id="l10073" name="l10073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca040bd66d4a54d4d9e9b261c8102799">10073</a></span><span class="preprocessor">#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk </span></div>
|
||
<div class="line"><a id="l10074" name="l10074"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3fd18a8801d86093018dfe2ea3b2b4a">10074</a></span><span class="preprocessor">#define RCC_APB1ENR_WWDGEN_Pos (11U) </span></div>
|
||
<div class="line"><a id="l10075" name="l10075"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09ad274a2f953fdb7c7ce0e6d69e8798">10075</a></span><span class="preprocessor">#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) </span></div>
|
||
<div class="line"><a id="l10076" name="l10076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf712b922ee776a972d2efa3da0ea4733">10076</a></span><span class="preprocessor">#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk </span></div>
|
||
<div class="line"><a id="l10077" name="l10077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea7eb0710266a43edcd813440b159f8e">10077</a></span><span class="preprocessor">#define RCC_APB1ENR_SPI2EN_Pos (14U) </span></div>
|
||
<div class="line"><a id="l10078" name="l10078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fd0ff191b4b6253b499258e4625cc65">10078</a></span><span class="preprocessor">#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) </span></div>
|
||
<div class="line"><a id="l10079" name="l10079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdce64692c44bf95efbf2fed054e59be">10079</a></span><span class="preprocessor">#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk </span></div>
|
||
<div class="line"><a id="l10080" name="l10080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59915518ddf7e60fc5da8072b3ce6dd9">10080</a></span><span class="preprocessor">#define RCC_APB1ENR_SPI3EN_Pos (15U) </span></div>
|
||
<div class="line"><a id="l10081" name="l10081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3852cf58a863e5b0133d5bc84bcede3f">10081</a></span><span class="preprocessor">#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) </span></div>
|
||
<div class="line"><a id="l10082" name="l10082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8757f8d1e1ff1447e08e5abea4615083">10082</a></span><span class="preprocessor">#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk </span></div>
|
||
<div class="line"><a id="l10083" name="l10083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a410d2ae7f9133227d2a35cde9188d6">10083</a></span><span class="preprocessor">#define RCC_APB1ENR_USART2EN_Pos (17U) </span></div>
|
||
<div class="line"><a id="l10084" name="l10084"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga510e179108a8914b0830b1ff30951caf">10084</a></span><span class="preprocessor">#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) </span></div>
|
||
<div class="line"><a id="l10085" name="l10085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab840af4f735ec36419d61c7db3cfa00d">10085</a></span><span class="preprocessor">#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk </span></div>
|
||
<div class="line"><a id="l10086" name="l10086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bfba28e5987744972af99c83dfd0a68">10086</a></span><span class="preprocessor">#define RCC_APB1ENR_USART3EN_Pos (18U) </span></div>
|
||
<div class="line"><a id="l10087" name="l10087"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac98f52fa1ae42a405334a2cc84f993b2">10087</a></span><span class="preprocessor">#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) </span></div>
|
||
<div class="line"><a id="l10088" name="l10088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8033e0312aea02ae7eb2d57da13e8298">10088</a></span><span class="preprocessor">#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk </span></div>
|
||
<div class="line"><a id="l10089" name="l10089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadad62b6567db40949d10c876718780f6">10089</a></span><span class="preprocessor">#define RCC_APB1ENR_UART4EN_Pos (19U) </span></div>
|
||
<div class="line"><a id="l10090" name="l10090"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33f02158e2eaba91c9cbc6e499aa4471">10090</a></span><span class="preprocessor">#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) </span></div>
|
||
<div class="line"><a id="l10091" name="l10091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6b0fe571aa29ed30389f87bdbf37b46">10091</a></span><span class="preprocessor">#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk </span></div>
|
||
<div class="line"><a id="l10092" name="l10092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99f56067e63f26f0ecb64bdf36be19df">10092</a></span><span class="preprocessor">#define RCC_APB1ENR_UART5EN_Pos (20U) </span></div>
|
||
<div class="line"><a id="l10093" name="l10093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab01815c1b0ced6d002d1b7590e9b8b15">10093</a></span><span class="preprocessor">#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) </span></div>
|
||
<div class="line"><a id="l10094" name="l10094"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24a9eea153892405f53007f521efee2e">10094</a></span><span class="preprocessor">#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk </span></div>
|
||
<div class="line"><a id="l10095" name="l10095"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f1cab341f8320372dfd95bce3d2d918">10095</a></span><span class="preprocessor">#define RCC_APB1ENR_I2C1EN_Pos (21U) </span></div>
|
||
<div class="line"><a id="l10096" name="l10096"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b2a4e92cb0eba09a147ee9770195eee">10096</a></span><span class="preprocessor">#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) </span></div>
|
||
<div class="line"><a id="l10097" name="l10097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ca3afe0c517702b2d1366b692c8db0e">10097</a></span><span class="preprocessor">#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk </span></div>
|
||
<div class="line"><a id="l10098" name="l10098"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94ad0c869b4e644dacba6b170797fcf6">10098</a></span><span class="preprocessor">#define RCC_APB1ENR_I2C2EN_Pos (22U) </span></div>
|
||
<div class="line"><a id="l10099" name="l10099"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb344f4fbe0d1286860e8c47f73339ce">10099</a></span><span class="preprocessor">#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) </span></div>
|
||
<div class="line"><a id="l10100" name="l10100"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd7d1c3c7dbe20aea87a694ae15840f6">10100</a></span><span class="preprocessor">#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk </span></div>
|
||
<div class="line"><a id="l10101" name="l10101"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga007431fc8e6cbe66fff71273e9245ad3">10101</a></span><span class="preprocessor">#define RCC_APB1ENR_I2C3EN_Pos (23U) </span></div>
|
||
<div class="line"><a id="l10102" name="l10102"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3287ea960eceb4499698cfc8e4ffbf36">10102</a></span><span class="preprocessor">#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) </span></div>
|
||
<div class="line"><a id="l10103" name="l10103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96621806b8fb96891efa9364e370f3f7">10103</a></span><span class="preprocessor">#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk </span></div>
|
||
<div class="line"><a id="l10104" name="l10104"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1a9a8c0f5081081046044070e17d93b">10104</a></span><span class="preprocessor">#define RCC_APB1ENR_CAN1EN_Pos (25U) </span></div>
|
||
<div class="line"><a id="l10105" name="l10105"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8adf13f0648b09c215dfd69d3ef933b5">10105</a></span><span class="preprocessor">#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) </span></div>
|
||
<div class="line"><a id="l10106" name="l10106"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66b5172158cf0170d29091064ea63a29">10106</a></span><span class="preprocessor">#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk </span></div>
|
||
<div class="line"><a id="l10107" name="l10107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace880a61cc0e55b67c8d4bf47374cf49">10107</a></span><span class="preprocessor">#define RCC_APB1ENR_CAN2EN_Pos (26U) </span></div>
|
||
<div class="line"><a id="l10108" name="l10108"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bffa56c0080897dc6cbe28ad888f22b">10108</a></span><span class="preprocessor">#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos) </span></div>
|
||
<div class="line"><a id="l10109" name="l10109"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae64f792b7a3401cff4d95e31d3867422">10109</a></span><span class="preprocessor">#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk </span></div>
|
||
<div class="line"><a id="l10110" name="l10110"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d869630ea19b70ec5c740cc6b37f49c">10110</a></span><span class="preprocessor">#define RCC_APB1ENR_PWREN_Pos (28U) </span></div>
|
||
<div class="line"><a id="l10111" name="l10111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ba08580eae539419497cdd62c530bad">10111</a></span><span class="preprocessor">#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) </span></div>
|
||
<div class="line"><a id="l10112" name="l10112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c19997ccd28464b80a7c3325da0ca60">10112</a></span><span class="preprocessor">#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk </span></div>
|
||
<div class="line"><a id="l10113" name="l10113"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7982505dca41bc51c29dcdcc03eb789">10113</a></span><span class="preprocessor">#define RCC_APB1ENR_DACEN_Pos (29U) </span></div>
|
||
<div class="line"><a id="l10114" name="l10114"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd51394bb1f7c10cef36c5dd2e19766d">10114</a></span><span class="preprocessor">#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) </span></div>
|
||
<div class="line"><a id="l10115" name="l10115"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga087968e2786321fb8645c46b22eea132">10115</a></span><span class="preprocessor">#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk </span></div>
|
||
<div class="line"><a id="l10116" name="l10116"></a><span class="lineno">10116</span> </div>
|
||
<div class="line"><a id="l10117" name="l10117"></a><span class="lineno">10117</span><span class="comment">/******************** Bit definition for RCC_APB2ENR register ***************/</span></div>
|
||
<div class="line"><a id="l10118" name="l10118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b330cc86756aa87e3f7466e82eaf64b">10118</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM1EN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10119" name="l10119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1216bf89d48094b55a4abcc859b037fa">10119</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) </span></div>
|
||
<div class="line"><a id="l10120" name="l10120"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25852ad4ebc09edc724814de967816bc">10120</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk </span></div>
|
||
<div class="line"><a id="l10121" name="l10121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadddecaa60d969169a1ba2944371b2414">10121</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM8EN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l10122" name="l10122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace08df04fccb33baccbda0fa4697dc04">10122</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) </span></div>
|
||
<div class="line"><a id="l10123" name="l10123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3669393b3538bc4543184d4bccd0b292">10123</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk </span></div>
|
||
<div class="line"><a id="l10124" name="l10124"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga603eb3c42e7ee50f31fb6fade0b4e43b">10124</a></span><span class="preprocessor">#define RCC_APB2ENR_USART1EN_Pos (4U) </span></div>
|
||
<div class="line"><a id="l10125" name="l10125"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a185f9bf1e72599fc7d2e02716ee40b">10125</a></span><span class="preprocessor">#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) </span></div>
|
||
<div class="line"><a id="l10126" name="l10126"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4666bb90842e8134b32e6a34a0f165f3">10126</a></span><span class="preprocessor">#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk </span></div>
|
||
<div class="line"><a id="l10127" name="l10127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e600f524eab6bd8a909babd0dde5466">10127</a></span><span class="preprocessor">#define RCC_APB2ENR_USART6EN_Pos (5U) </span></div>
|
||
<div class="line"><a id="l10128" name="l10128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d196a71620aa24b125657dfdc9c85bf">10128</a></span><span class="preprocessor">#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) </span></div>
|
||
<div class="line"><a id="l10129" name="l10129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0569d91f3b18ae130b7a09e0100c4459">10129</a></span><span class="preprocessor">#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk </span></div>
|
||
<div class="line"><a id="l10130" name="l10130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabad54999d05c830541de19027fb92c97">10130</a></span><span class="preprocessor">#define RCC_APB2ENR_ADC1EN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l10131" name="l10131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11c50e2378b7a8d15c9a2eb89f561efe">10131</a></span><span class="preprocessor">#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) </span></div>
|
||
<div class="line"><a id="l10132" name="l10132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57b9f50cb96a2e4ceba37728b4a32a42">10132</a></span><span class="preprocessor">#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk </span></div>
|
||
<div class="line"><a id="l10133" name="l10133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa0ab86ac5dc8b87216901e91c950cc0">10133</a></span><span class="preprocessor">#define RCC_APB2ENR_ADC2EN_Pos (9U) </span></div>
|
||
<div class="line"><a id="l10134" name="l10134"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55e486391860d774ac8613c6848b62de">10134</a></span><span class="preprocessor">#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) </span></div>
|
||
<div class="line"><a id="l10135" name="l10135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11a9732e1cef24f107e815caecdbb445">10135</a></span><span class="preprocessor">#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk </span></div>
|
||
<div class="line"><a id="l10136" name="l10136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a7fff458c028a5b1d43cd3a5e299121">10136</a></span><span class="preprocessor">#define RCC_APB2ENR_ADC3EN_Pos (10U) </span></div>
|
||
<div class="line"><a id="l10137" name="l10137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3126f80244d91d2d13c1a40e5f64df0">10137</a></span><span class="preprocessor">#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos) </span></div>
|
||
<div class="line"><a id="l10138" name="l10138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5df23f931ddad97274ce7e2050b90a5a">10138</a></span><span class="preprocessor">#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk </span></div>
|
||
<div class="line"><a id="l10139" name="l10139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4fd687b860d719def07032d6cfd1cc3a">10139</a></span><span class="preprocessor">#define RCC_APB2ENR_SDIOEN_Pos (11U) </span></div>
|
||
<div class="line"><a id="l10140" name="l10140"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06f570456b6725105e600c0700cdc0bd">10140</a></span><span class="preprocessor">#define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos) </span></div>
|
||
<div class="line"><a id="l10141" name="l10141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf714bbe5b378910693dbfe824b70de8">10141</a></span><span class="preprocessor">#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk </span></div>
|
||
<div class="line"><a id="l10142" name="l10142"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77b08db44a4ccc823a4ecaf89c3b4309">10142</a></span><span class="preprocessor">#define RCC_APB2ENR_SPI1EN_Pos (12U) </span></div>
|
||
<div class="line"><a id="l10143" name="l10143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefba87e52830d0d82cd94eb11089aa1b">10143</a></span><span class="preprocessor">#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) </span></div>
|
||
<div class="line"><a id="l10144" name="l10144"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae08a3510371b9234eb96369c91d3552f">10144</a></span><span class="preprocessor">#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk </span></div>
|
||
<div class="line"><a id="l10145" name="l10145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e61727e044998a6ebee3dcf48614554">10145</a></span><span class="preprocessor">#define RCC_APB2ENR_SYSCFGEN_Pos (14U) </span></div>
|
||
<div class="line"><a id="l10146" name="l10146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga781c030e54df45c8f190c9f03d20f4a5">10146</a></span><span class="preprocessor">#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) </span></div>
|
||
<div class="line"><a id="l10147" name="l10147"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a9d56a8aa1fa0f519ecbdf0d19dd4da">10147</a></span><span class="preprocessor">#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk </span></div>
|
||
<div class="line"><a id="l10148" name="l10148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1023b40804156535a7fd0b0fd17da26">10148</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM9EN_Pos (16U) </span></div>
|
||
<div class="line"><a id="l10149" name="l10149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7973b960b45268bd0160c1f5f21acf2">10149</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) </span></div>
|
||
<div class="line"><a id="l10150" name="l10150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga987ebd8255dc8f9c09127e1d608d1065">10150</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk </span></div>
|
||
<div class="line"><a id="l10151" name="l10151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga595f4318939fac8cef4cfb6a886a0811">10151</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM10EN_Pos (17U) </span></div>
|
||
<div class="line"><a id="l10152" name="l10152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga539dc20498c8b8abdf208bd2b98a46c6">10152</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) </span></div>
|
||
<div class="line"><a id="l10153" name="l10153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa98e28e157787e24b93af95273ab3055">10153</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk </span></div>
|
||
<div class="line"><a id="l10154" name="l10154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4175c4afc573a7bdd6fa19faaaf9f735">10154</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM11EN_Pos (18U) </span></div>
|
||
<div class="line"><a id="l10155" name="l10155"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5273bcf1abc8db0bf1617c747bab5ec">10155</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) </span></div>
|
||
<div class="line"><a id="l10156" name="l10156"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1d2aeebc8ccf4e2ee18f4d924a35188">10156</a></span><span class="preprocessor">#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk </span></div>
|
||
<div class="line"><a id="l10157" name="l10157"></a><span class="lineno">10157</span> </div>
|
||
<div class="line"><a id="l10158" name="l10158"></a><span class="lineno">10158</span><span class="comment">/******************** Bit definition for RCC_AHB1LPENR register *************/</span></div>
|
||
<div class="line"><a id="l10159" name="l10159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacded6b0f52a7b9ef3bde81ce8d4cd657">10159</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10160" name="l10160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab01076ddb6708e4c0ff9d6c4f22fa809">10160</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10161" name="l10161"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1076b0644c026ab480efdb6aa8c74fb">10161</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk </span></div>
|
||
<div class="line"><a id="l10162" name="l10162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1408e65a8ca8d481d713a171adb4a8b9">10162</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l10163" name="l10163"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad765dcf02bb5f215ff3a77a63c16f746">10163</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10164" name="l10164"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55f6ff35a37c4b9106c9e8aa18ab4545">10164</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10165" name="l10165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30cd4b8a99bb64ebbcac917ea64ccacc">10165</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U) </span></div>
|
||
<div class="line"><a id="l10166" name="l10166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26ff370d6adef4823a87bd98c5767a42">10166</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10167" name="l10167"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac86ad592684edae0ba2cafd22a4f04d1">10167</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10168" name="l10168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaceb2e30709973666017a04023286fb71">10168</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U) </span></div>
|
||
<div class="line"><a id="l10169" name="l10169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b81052c9334056e60b2b47e12d8ccef">10169</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10170" name="l10170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89002894839d323b05c4b3f674b54470">10170</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10171" name="l10171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76748b3f35e4bc4481110d4be1ebdef9">10171</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U) </span></div>
|
||
<div class="line"><a id="l10172" name="l10172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga379b06aa2db224e0e6e2812e33e5bc88">10172</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10173" name="l10173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2980a6e02550369d05e121ff6f16505c">10173</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk </span></div>
|
||
<div class="line"><a id="l10174" name="l10174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bdc53d83d3aec2d5c5fb2ae6a97b268">10174</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U) </span></div>
|
||
<div class="line"><a id="l10175" name="l10175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1d321cff7127cb7bee72a680b40bcaf">10175</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10176" name="l10176"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7a50c0506b1014d89224933c6c42e6f">10176</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10177" name="l10177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2050b38f2df4a69119c402d384e5b862">10177</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l10178" name="l10178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8cbc273b51b62d59dbe58f68a330231">10178</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10179" name="l10179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1dc004ecb0a2950100a062cda47586f">10179</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10180" name="l10180"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64e54771be85afdd10ad93c3acdef080">10180</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U) </span></div>
|
||
<div class="line"><a id="l10181" name="l10181"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5420182a12449790d9316927e05bab4b">10181</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10182" name="l10182"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga197be77b89e9eae127a536bd2601ded9">10182</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10183" name="l10183"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6334fbcfede5da166dab8b2e15d69d9">10183</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l10184" name="l10184"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga285f894641272c773dac56c0eb5d14cc">10184</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10185" name="l10185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70d927cfb1d110133bd64989b216a375">10185</a></span><span class="preprocessor">#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk </span></div>
|
||
<div class="line"><a id="l10186" name="l10186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fb1b796b4ad84e3dd60b14b958d6f98">10186</a></span><span class="preprocessor">#define RCC_AHB1LPENR_CRCLPEN_Pos (12U) </span></div>
|
||
<div class="line"><a id="l10187" name="l10187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87b177e8246a207541fbce277d4f48ab">10187</a></span><span class="preprocessor">#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10188" name="l10188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7333e14b5ccf6d608232ea52a10f7052">10188</a></span><span class="preprocessor">#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10189" name="l10189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07b410fb7c23f0ee3f8d100c5a409078">10189</a></span><span class="preprocessor">#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U) </span></div>
|
||
<div class="line"><a id="l10190" name="l10190"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafb7485a44d40e2da16270de53aa8171">10190</a></span><span class="preprocessor">#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10191" name="l10191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga378f6e2ad9fef59f28db829d2074e796">10191</a></span><span class="preprocessor">#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10192" name="l10192"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1719fa2c00b2554e679b7bd52e648b3">10192</a></span><span class="preprocessor">#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U) </span></div>
|
||
<div class="line"><a id="l10193" name="l10193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3165c825e9a88a606803cd08a85d9dd9">10193</a></span><span class="preprocessor">#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10194" name="l10194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4cd1fbd9113809a6a3c904617647219c">10194</a></span><span class="preprocessor">#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10195" name="l10195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14b6f62bdc1eeab17de120a32d3ef25e">10195</a></span><span class="preprocessor">#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U) </span></div>
|
||
<div class="line"><a id="l10196" name="l10196"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54ed7528aecee29c5498e649bb9851eb">10196</a></span><span class="preprocessor">#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10197" name="l10197"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf7a4c822fa3073035a04487c4cca320">10197</a></span><span class="preprocessor">#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10198" name="l10198"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3100beebfa0db32c2c193e8fbad16cec">10198</a></span><span class="preprocessor">#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U) </span></div>
|
||
<div class="line"><a id="l10199" name="l10199"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga192203e1375323694da43336c59f036e">10199</a></span><span class="preprocessor">#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10200" name="l10200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga777dc76d2a216f8b51b360e8054342e4">10200</a></span><span class="preprocessor">#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10201" name="l10201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga014095a10051377b3cbdd6e5392d4625">10201</a></span><span class="preprocessor">#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U) </span></div>
|
||
<div class="line"><a id="l10202" name="l10202"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c9b77b3b402f07fd5196bc6ced33032">10202</a></span><span class="preprocessor">#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10203" name="l10203"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d6c8ae1441d545d18c54b30c6a0da77">10203</a></span><span class="preprocessor">#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10204" name="l10204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b8cac0542554d72d2b230feed936194">10204</a></span><span class="preprocessor">#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U) </span></div>
|
||
<div class="line"><a id="l10205" name="l10205"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a4daa369b439dbff3744661225897bc">10205</a></span><span class="preprocessor">#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10206" name="l10206"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e2d376f6c7db4266a5b039a3aa6c207">10206</a></span><span class="preprocessor">#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10207" name="l10207"></a><span class="lineno">10207</span> </div>
|
||
<div class="line"><a id="l10208" name="l10208"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05fd12d343bf91b0cb39a9db295f1c72">10208</a></span><span class="preprocessor">#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U) </span></div>
|
||
<div class="line"><a id="l10209" name="l10209"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1da28307db95580ebba7ee61b0a8f9cb">10209</a></span><span class="preprocessor">#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10210" name="l10210"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga421fd0aec3671e054ef18cd290bc164e">10210</a></span><span class="preprocessor">#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10211" name="l10211"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga748b751a0809106ddb4c874b11bf36fa">10211</a></span><span class="preprocessor">#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U) </span></div>
|
||
<div class="line"><a id="l10212" name="l10212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a38ff160774afae91d03db40b2cfde1">10212</a></span><span class="preprocessor">#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10213" name="l10213"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09935984b92821f18c3e00f7e4fbeb62">10213</a></span><span class="preprocessor">#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10214" name="l10214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe363b3bbbef9025b6b05d007d8e3423">10214</a></span><span class="preprocessor">#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U) </span></div>
|
||
<div class="line"><a id="l10215" name="l10215"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga793010bfe42e5e13b9ebed488352b3b3">10215</a></span><span class="preprocessor">#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10216" name="l10216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28dc3cec4693215c0db36dcfd8a55ee8">10216</a></span><span class="preprocessor">#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10217" name="l10217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea2001b38e0bac5fd64303d9bb8df6a5">10217</a></span><span class="preprocessor">#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U) </span></div>
|
||
<div class="line"><a id="l10218" name="l10218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9db17131964299ee8997a3bd9f4d5544">10218</a></span><span class="preprocessor">#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10219" name="l10219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa04c4dfda05aebb5efe66518a28e29de">10219</a></span><span class="preprocessor">#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10220" name="l10220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f86b4c6131db2afce3db43a4b5242c9">10220</a></span><span class="preprocessor">#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U) </span></div>
|
||
<div class="line"><a id="l10221" name="l10221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf645b65fa1f722e0909ea5768f5e39d1">10221</a></span><span class="preprocessor">#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10222" name="l10222"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga934a7c19bd6f6b34941058c5c3552b91">10222</a></span><span class="preprocessor">#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10223" name="l10223"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7f913b7278276c84700eba1ab154d16">10223</a></span><span class="preprocessor">#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U) </span></div>
|
||
<div class="line"><a id="l10224" name="l10224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9468c1e5269479e8009174e2dbdfd871">10224</a></span><span class="preprocessor">#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10225" name="l10225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9567cabb8058c53bae64ed4b77c05dd">10225</a></span><span class="preprocessor">#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk </span></div>
|
||
<div class="line"><a id="l10226" name="l10226"></a><span class="lineno">10226</span> </div>
|
||
<div class="line"><a id="l10227" name="l10227"></a><span class="lineno">10227</span><span class="comment">/******************** Bit definition for RCC_AHB2LPENR register *************/</span></div>
|
||
<div class="line"><a id="l10228" name="l10228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88eed976ee3304bdf4ba0a514d2f9d17">10228</a></span><span class="preprocessor">#define RCC_AHB2LPENR_DCMILPEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10229" name="l10229"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e9e48b4b6b730a3fc71ecc7bad6f4c7">10229</a></span><span class="preprocessor">#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10230" name="l10230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51ec4f41dcfdedeedef75a64ec65863a">10230</a></span><span class="preprocessor">#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk </span></div>
|
||
<div class="line"><a id="l10231" name="l10231"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad53ba64643a3daa4220a3515ae089822">10231</a></span><span class="preprocessor">#define RCC_AHB2LPENR_RNGLPEN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l10232" name="l10232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga082f00df13212bc37c2528b69330a304">10232</a></span><span class="preprocessor">#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10233" name="l10233"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab54623c517f1450a7fde279c2cae864">10233</a></span><span class="preprocessor">#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10234" name="l10234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3383a619f30eef365e0f6031aaf2423">10234</a></span><span class="preprocessor">#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U) </span></div>
|
||
<div class="line"><a id="l10235" name="l10235"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga235d86e1b22afa92651c1cb0c31660cd">10235</a></span><span class="preprocessor">#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10236" name="l10236"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0fd858d073b14216ae0d716ba4f1dd3">10236</a></span><span class="preprocessor">#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10237" name="l10237"></a><span class="lineno">10237</span> </div>
|
||
<div class="line"><a id="l10238" name="l10238"></a><span class="lineno">10238</span><span class="comment">/******************** Bit definition for RCC_AHB3LPENR register *************/</span></div>
|
||
<div class="line"><a id="l10239" name="l10239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25502d2b4fe408f7fb0238bbe4595754">10239</a></span><span class="preprocessor">#define RCC_AHB3LPENR_FSMCLPEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10240" name="l10240"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d006571ef2ef5c0fb68621fdb5835b7">10240</a></span><span class="preprocessor">#define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10241" name="l10241"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf56147909fa8e7f8629c7fd7349ecb3">10241</a></span><span class="preprocessor">#define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10242" name="l10242"></a><span class="lineno">10242</span> </div>
|
||
<div class="line"><a id="l10243" name="l10243"></a><span class="lineno">10243</span><span class="comment">/******************** Bit definition for RCC_APB1LPENR register *************/</span></div>
|
||
<div class="line"><a id="l10244" name="l10244"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66d7d011a4a85de1091644162d0fea68">10244</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM2LPEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10245" name="l10245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ef88837af2b396c012ec1225a4d8a65">10245</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10246" name="l10246"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f561f8bfc556b52335ec2a32ba81c44">10246</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10247" name="l10247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00f72d8c0899d67b6a428e4ed6167630">10247</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM3LPEN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l10248" name="l10248"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0231e0f1fbb26813e6a67b4e17d2578">10248</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10249" name="l10249"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9391d99885a0a6fbaf3447117ac0f7aa">10249</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10250" name="l10250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafaff851f048550c86bb301ed2e1dac9d">10250</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM4LPEN_Pos (2U) </span></div>
|
||
<div class="line"><a id="l10251" name="l10251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a807ed1ed77d84c24ad990e689b1600">10251</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10252" name="l10252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f04aff278b72fbf6acbe0ad947b06ae">10252</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10253" name="l10253"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93219e40400c9b6541b633c0412ac43c">10253</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM5LPEN_Pos (3U) </span></div>
|
||
<div class="line"><a id="l10254" name="l10254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73c7205ba8d0f5e12584ccf932efbc74">10254</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10255" name="l10255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5741a6c45b9de1d0c927beb87f399dd9">10255</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10256" name="l10256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36d3ba67d01b7993c45c0888a25ba77c">10256</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM6LPEN_Pos (4U) </span></div>
|
||
<div class="line"><a id="l10257" name="l10257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec6b200cfb1a2c2d2dd473b4d19213b7">10257</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10258" name="l10258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga439a5998fd60c3375411c7db2129ac89">10258</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10259" name="l10259"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32da6d7364c7a5e303c22098fd748078">10259</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM7LPEN_Pos (5U) </span></div>
|
||
<div class="line"><a id="l10260" name="l10260"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e9c974f3ef148d502bb9898a230dd71">10260</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10261" name="l10261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7867dc2695855fa9084a13d06a4299f">10261</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10262" name="l10262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5108a41416096f47d46c7fd69e810e50">10262</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM12LPEN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l10263" name="l10263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe9cf962cc29a62ff4cc27ac9984f1d1">10263</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10264" name="l10264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b47fde44967a5a600a042398a9cf3c6">10264</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10265" name="l10265"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2d2664523f65db375f5883e6fba692c">10265</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM13LPEN_Pos (7U) </span></div>
|
||
<div class="line"><a id="l10266" name="l10266"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5df15d5e47024a72fe127a81d8a2e3cf">10266</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10267" name="l10267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9897d5f0033623a05997ca222d3a132b">10267</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10268" name="l10268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a961758cd246c0ef98ffbb703feef88">10268</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM14LPEN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l10269" name="l10269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e28132e6a8eb793e4e21b4334c56ee7">10269</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10270" name="l10270"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd1af8912fedadb9edead5b31167a310">10270</a></span><span class="preprocessor">#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10271" name="l10271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96ef3e58ec8ebab942b958e1efc365a2">10271</a></span><span class="preprocessor">#define RCC_APB1LPENR_WWDGLPEN_Pos (11U) </span></div>
|
||
<div class="line"><a id="l10272" name="l10272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24b3760635c135839bffebcdce62aa90">10272</a></span><span class="preprocessor">#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10273" name="l10273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13f3db4ac67bf32c994364cc43f4fe8b">10273</a></span><span class="preprocessor">#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10274" name="l10274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c7bc3dcdc95f9245977cc4de874bb1f">10274</a></span><span class="preprocessor">#define RCC_APB1LPENR_SPI2LPEN_Pos (14U) </span></div>
|
||
<div class="line"><a id="l10275" name="l10275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada9dd21c62e16d73115a855bffc5a98a">10275</a></span><span class="preprocessor">#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10276" name="l10276"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41dcbf845448cbb1b75c0ad7e83b77cb">10276</a></span><span class="preprocessor">#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10277" name="l10277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf82b15d2ca1965ca72eb372345bb4dc1">10277</a></span><span class="preprocessor">#define RCC_APB1LPENR_SPI3LPEN_Pos (15U) </span></div>
|
||
<div class="line"><a id="l10278" name="l10278"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a00b05657ebd904eb04349ce6625799">10278</a></span><span class="preprocessor">#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10279" name="l10279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8acbff235a15b58d1be0f065cdb5472">10279</a></span><span class="preprocessor">#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10280" name="l10280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36666e20226da8c9ddb2cbeb2aef1330">10280</a></span><span class="preprocessor">#define RCC_APB1LPENR_USART2LPEN_Pos (17U) </span></div>
|
||
<div class="line"><a id="l10281" name="l10281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaffb3fa84a480055b7b9547cc09ed8cb">10281</a></span><span class="preprocessor">#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10282" name="l10282"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6055c39af369463e14d6ff2017043671">10282</a></span><span class="preprocessor">#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10283" name="l10283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga215925022960bd4c07052109c70bc999">10283</a></span><span class="preprocessor">#define RCC_APB1LPENR_USART3LPEN_Pos (18U) </span></div>
|
||
<div class="line"><a id="l10284" name="l10284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabeccde78822839765663f2482e0fd3f2">10284</a></span><span class="preprocessor">#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10285" name="l10285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae11baa29f4e6d122dabdd54c6b4be052">10285</a></span><span class="preprocessor">#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10286" name="l10286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8a9e913d67a5976a41240ccacbe6e14">10286</a></span><span class="preprocessor">#define RCC_APB1LPENR_UART4LPEN_Pos (19U) </span></div>
|
||
<div class="line"><a id="l10287" name="l10287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff134f37108abd0d043c9f62eb250bbc">10287</a></span><span class="preprocessor">#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10288" name="l10288"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88fe1e9cf93caa4e02de35e92e55834d">10288</a></span><span class="preprocessor">#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10289" name="l10289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c9f855673b672b235461f4cc6480beb">10289</a></span><span class="preprocessor">#define RCC_APB1LPENR_UART5LPEN_Pos (20U) </span></div>
|
||
<div class="line"><a id="l10290" name="l10290"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab22aca4251bd69be2f39c31e27344975">10290</a></span><span class="preprocessor">#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10291" name="l10291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3de908135d9c9e74c598f7bf1e88fb34">10291</a></span><span class="preprocessor">#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10292" name="l10292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a099cd3cde1ab16cb0a8805d15df425">10292</a></span><span class="preprocessor">#define RCC_APB1LPENR_I2C1LPEN_Pos (21U) </span></div>
|
||
<div class="line"><a id="l10293" name="l10293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1afe0c2a2e36921403357bb10f168790">10293</a></span><span class="preprocessor">#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10294" name="l10294"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33286469d0a9b9fedbc2b60aa6cd7da7">10294</a></span><span class="preprocessor">#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10295" name="l10295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaede8bc79a31bfe414f4c9bb6829b5804">10295</a></span><span class="preprocessor">#define RCC_APB1LPENR_I2C2LPEN_Pos (22U) </span></div>
|
||
<div class="line"><a id="l10296" name="l10296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76e2c1200c865395531d57931327097d">10296</a></span><span class="preprocessor">#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10297" name="l10297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6a53d37df11a56412ae06f73626f637">10297</a></span><span class="preprocessor">#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10298" name="l10298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59cb6740257f6c8f1a40b9ce6e5bf498">10298</a></span><span class="preprocessor">#define RCC_APB1LPENR_I2C3LPEN_Pos (23U) </span></div>
|
||
<div class="line"><a id="l10299" name="l10299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga336e724329c3f2adaba3ed13af63de09">10299</a></span><span class="preprocessor">#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10300" name="l10300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5abf01e4149d71e8427eefcd2e429fe9">10300</a></span><span class="preprocessor">#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10301" name="l10301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f780db5faed548d72f11abf461502e6">10301</a></span><span class="preprocessor">#define RCC_APB1LPENR_CAN1LPEN_Pos (25U) </span></div>
|
||
<div class="line"><a id="l10302" name="l10302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b99fe06fe55b8c9df8e192df0caf4fa">10302</a></span><span class="preprocessor">#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10303" name="l10303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb93b42a94b988f4a03bed9ea78b4519">10303</a></span><span class="preprocessor">#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10304" name="l10304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee1a0ced3d5d4088ba28a34e150ffaee">10304</a></span><span class="preprocessor">#define RCC_APB1LPENR_CAN2LPEN_Pos (26U) </span></div>
|
||
<div class="line"><a id="l10305" name="l10305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6da195ab0281bf251ae19040f072b8ac">10305</a></span><span class="preprocessor">#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10306" name="l10306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga167ad9fc43674d6993a9550ac3b6e70f">10306</a></span><span class="preprocessor">#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10307" name="l10307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67fd356139c695e461be99af8aafa297">10307</a></span><span class="preprocessor">#define RCC_APB1LPENR_PWRLPEN_Pos (28U) </span></div>
|
||
<div class="line"><a id="l10308" name="l10308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga653ef9d97213f971b3ace653a8f7f4f0">10308</a></span><span class="preprocessor">#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10309" name="l10309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga274fa282ad1ff40b747644bf9360feb4">10309</a></span><span class="preprocessor">#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10310" name="l10310"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad83f868ee37a8885c4ff2e293e4df4f6">10310</a></span><span class="preprocessor">#define RCC_APB1LPENR_DACLPEN_Pos (29U) </span></div>
|
||
<div class="line"><a id="l10311" name="l10311"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecbfaa2f91227a9bdb7c6dcabddb75c7">10311</a></span><span class="preprocessor">#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10312" name="l10312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf36a11e89644548702385d548f3f9ec4">10312</a></span><span class="preprocessor">#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10313" name="l10313"></a><span class="lineno">10313</span> </div>
|
||
<div class="line"><a id="l10314" name="l10314"></a><span class="lineno">10314</span><span class="comment">/******************** Bit definition for RCC_APB2LPENR register *************/</span></div>
|
||
<div class="line"><a id="l10315" name="l10315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ac0ea3808afc94624b680e8b3749a66">10315</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM1LPEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10316" name="l10316"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga858c7e6effbead8e2953c8af89451f05">10316</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10317" name="l10317"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82580245686c32761e8354fb174ba5dd">10317</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10318" name="l10318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04afe23491647fcdf2a0cfeadce36cf0">10318</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM8LPEN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l10319" name="l10319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga193680b82d9cdcefad8ff2ac9e7ed2da">10319</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10320" name="l10320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a1a808f511ff563f05f32ad3ae6d7c1">10320</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10321" name="l10321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bcb3fc3f4b2e68f667724cdd2e04ce8">10321</a></span><span class="preprocessor">#define RCC_APB2LPENR_USART1LPEN_Pos (4U) </span></div>
|
||
<div class="line"><a id="l10322" name="l10322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga294b9579075d948ff613d153a7a3c3ca">10322</a></span><span class="preprocessor">#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10323" name="l10323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8b429bc8d52abd1ba3818a82542bb98">10323</a></span><span class="preprocessor">#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10324" name="l10324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa70231e7e2fbbac64535106f4aa48e3f">10324</a></span><span class="preprocessor">#define RCC_APB2LPENR_USART6LPEN_Pos (5U) </span></div>
|
||
<div class="line"><a id="l10325" name="l10325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4262d6ef04c2c0ebe14c133021f0ae03">10325</a></span><span class="preprocessor">#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10326" name="l10326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b82eb1986da9ed32e6701d01fffe55d">10326</a></span><span class="preprocessor">#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10327" name="l10327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae30aac03ac0c319cc528d35e7f459997">10327</a></span><span class="preprocessor">#define RCC_APB2LPENR_ADC1LPEN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l10328" name="l10328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga116ac44e1a83643de5be822458c9f42b">10328</a></span><span class="preprocessor">#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10329" name="l10329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga126a8791f77cecc599e32d2c882a4dab">10329</a></span><span class="preprocessor">#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10330" name="l10330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20aaf3952e7679b2535befd5db14781b">10330</a></span><span class="preprocessor">#define RCC_APB2LPENR_ADC2LPEN_Pos (9U) </span></div>
|
||
<div class="line"><a id="l10331" name="l10331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6de7661abce7e5d9b3d9d47938095b0">10331</a></span><span class="preprocessor">#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10332" name="l10332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7d578d9d9a12e3f0b4246e196040c13">10332</a></span><span class="preprocessor">#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10333" name="l10333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga287cf6c970a88095bdabcb50dbebd196">10333</a></span><span class="preprocessor">#define RCC_APB2LPENR_ADC3LPEN_Pos (10U) </span></div>
|
||
<div class="line"><a id="l10334" name="l10334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94f89563dfe984830b279fe3d358ca27">10334</a></span><span class="preprocessor">#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10335" name="l10335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12c8300ba9b1ce9b14fc8e0f3ec4c127">10335</a></span><span class="preprocessor">#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10336" name="l10336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e852d24cc37b0873db77eec05211616">10336</a></span><span class="preprocessor">#define RCC_APB2LPENR_SDIOLPEN_Pos (11U) </span></div>
|
||
<div class="line"><a id="l10337" name="l10337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga407fda261b548cac4ba4f70d13250a0e">10337</a></span><span class="preprocessor">#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10338" name="l10338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a740fdf8313fbdd00dd97eb73afc4dc">10338</a></span><span class="preprocessor">#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10339" name="l10339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ddb35d5536b1e28be09ba48b0726721">10339</a></span><span class="preprocessor">#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) </span></div>
|
||
<div class="line"><a id="l10340" name="l10340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3b71e51ae5bffdaf53ceb522f147892">10340</a></span><span class="preprocessor">#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10341" name="l10341"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c6729058e54f4b8f8ae01d5b3586aaa">10341</a></span><span class="preprocessor">#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10342" name="l10342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4bb28885c56bf8b04da2633393c5b47">10342</a></span><span class="preprocessor">#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U) </span></div>
|
||
<div class="line"><a id="l10343" name="l10343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4d070a25b830752decd55b74a452cda">10343</a></span><span class="preprocessor">#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10344" name="l10344"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa82cfc33f0cf71220398bbe1c4b412e">10344</a></span><span class="preprocessor">#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk </span></div>
|
||
<div class="line"><a id="l10345" name="l10345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae087736e445764bceba754d1d424f8d1">10345</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM9LPEN_Pos (16U) </span></div>
|
||
<div class="line"><a id="l10346" name="l10346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3d30a083acde66ba393ef2e7e2d3424">10346</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10347" name="l10347"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91b882f3dc2b939a53ed3f4caa537de1">10347</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10348" name="l10348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf74626f4a9c7d80ee37c80c18b76c9af">10348</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM10LPEN_Pos (17U) </span></div>
|
||
<div class="line"><a id="l10349" name="l10349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8e04154247e0db474da2cc8eccac1f2">10349</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10350" name="l10350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7999e2ebeb1300d0cf6a59ad92c41b6">10350</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10351" name="l10351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabcc3b8ef34620fa6f4e82cbbf527fc27">10351</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM11LPEN_Pos (18U) </span></div>
|
||
<div class="line"><a id="l10352" name="l10352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4cabf028115d0694b1bba23610d23da8">10352</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) </span></div>
|
||
<div class="line"><a id="l10353" name="l10353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad43fcaa4f4d6fb2b590a6ffee31f8c94">10353</a></span><span class="preprocessor">#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk </span></div>
|
||
<div class="line"><a id="l10354" name="l10354"></a><span class="lineno">10354</span> </div>
|
||
<div class="line"><a id="l10355" name="l10355"></a><span class="lineno">10355</span><span class="comment">/******************** Bit definition for RCC_BDCR register ******************/</span></div>
|
||
<div class="line"><a id="l10356" name="l10356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga016de845d59f61611054d27511a3fa68">10356</a></span><span class="preprocessor">#define RCC_BDCR_LSEON_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10357" name="l10357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85556465021c4272f4788d52251b29f4">10357</a></span><span class="preprocessor">#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) </span></div>
|
||
<div class="line"><a id="l10358" name="l10358"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00145f8814cb9a5b180d76499d97aead">10358</a></span><span class="preprocessor">#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk </span></div>
|
||
<div class="line"><a id="l10359" name="l10359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d373419116fa0446eee779da5292b02">10359</a></span><span class="preprocessor">#define RCC_BDCR_LSERDY_Pos (1U) </span></div>
|
||
<div class="line"><a id="l10360" name="l10360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35093bcccacfeda073a2fb815687549c">10360</a></span><span class="preprocessor">#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) </span></div>
|
||
<div class="line"><a id="l10361" name="l10361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafca81172ed857ce6b94582fcaada87c">10361</a></span><span class="preprocessor">#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk </span></div>
|
||
<div class="line"><a id="l10362" name="l10362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8900b556c097b54266370f197517c2b4">10362</a></span><span class="preprocessor">#define RCC_BDCR_LSEBYP_Pos (2U) </span></div>
|
||
<div class="line"><a id="l10363" name="l10363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e5eba5220ddabddf14901a8d44abaf2">10363</a></span><span class="preprocessor">#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) </span></div>
|
||
<div class="line"><a id="l10364" name="l10364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga542dffd7f8dc4da5401b54d822a22af0">10364</a></span><span class="preprocessor">#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk </span></div>
|
||
<div class="line"><a id="l10365" name="l10365"></a><span class="lineno">10365</span> </div>
|
||
<div class="line"><a id="l10366" name="l10366"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ba11e8b21a7165e4b8e9a2cbf5a323d">10366</a></span><span class="preprocessor">#define RCC_BDCR_RTCSEL_Pos (8U) </span></div>
|
||
<div class="line"><a id="l10367" name="l10367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57377b1880634589201dfe8887287e0e">10367</a></span><span class="preprocessor">#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10368" name="l10368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe30dbd38f6456990ee641648bc05d40">10368</a></span><span class="preprocessor">#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk </span></div>
|
||
<div class="line"><a id="l10369" name="l10369"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6701d58e40e4c16e9be49436fcbe23d0">10369</a></span><span class="preprocessor">#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10370" name="l10370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac4e378027f3293ec520ed6d18c633f4">10370</a></span><span class="preprocessor">#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10372" name="l10372"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad32e3fd78eebb6ac9bb446a9fdda3d0d">10372</a></span><span class="preprocessor">#define RCC_BDCR_RTCEN_Pos (15U) </span></div>
|
||
<div class="line"><a id="l10373" name="l10373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4b2e482dc6f5c75861f08de8057d1e2">10373</a></span><span class="preprocessor">#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) </span></div>
|
||
<div class="line"><a id="l10374" name="l10374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79ea6f2df75f09b17df9582037ed6a53">10374</a></span><span class="preprocessor">#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk </span></div>
|
||
<div class="line"><a id="l10375" name="l10375"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac787de49ce5fa9a2e0123ddf33f4e26e">10375</a></span><span class="preprocessor">#define RCC_BDCR_BDRST_Pos (16U) </span></div>
|
||
<div class="line"><a id="l10376" name="l10376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a3b3c81018daa0d5b80480a86bc7a17">10376</a></span><span class="preprocessor">#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) </span></div>
|
||
<div class="line"><a id="l10377" name="l10377"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b85b3ab656dfa2809b15e6e530c17a2">10377</a></span><span class="preprocessor">#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk </span></div>
|
||
<div class="line"><a id="l10378" name="l10378"></a><span class="lineno">10378</span> </div>
|
||
<div class="line"><a id="l10379" name="l10379"></a><span class="lineno">10379</span><span class="comment">/******************** Bit definition for RCC_CSR register *******************/</span></div>
|
||
<div class="line"><a id="l10380" name="l10380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc156654e34b1b6206760ba8d864c6c8">10380</a></span><span class="preprocessor">#define RCC_CSR_LSION_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10381" name="l10381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe63b332158f8886948205ff9edcf248">10381</a></span><span class="preprocessor">#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) </span></div>
|
||
<div class="line"><a id="l10382" name="l10382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga803cbf97bda1ebaf9afee2a3c9f0851b">10382</a></span><span class="preprocessor">#define RCC_CSR_LSION RCC_CSR_LSION_Msk </span></div>
|
||
<div class="line"><a id="l10383" name="l10383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68272a20b7fe83a0e08b1deb4aeacf55">10383</a></span><span class="preprocessor">#define RCC_CSR_LSIRDY_Pos (1U) </span></div>
|
||
<div class="line"><a id="l10384" name="l10384"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49a5c93576efd3e5d284351db6125373">10384</a></span><span class="preprocessor">#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) </span></div>
|
||
<div class="line"><a id="l10385" name="l10385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab569110e757aee573ebf9ad80812e8bb">10385</a></span><span class="preprocessor">#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk </span></div>
|
||
<div class="line"><a id="l10386" name="l10386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae97ee308ed96cdb97bc991b34aa95be4">10386</a></span><span class="preprocessor">#define RCC_CSR_RMVF_Pos (24U) </span></div>
|
||
<div class="line"><a id="l10387" name="l10387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82a7f8a2897bcc1313d58389fc18ad4c">10387</a></span><span class="preprocessor">#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) </span></div>
|
||
<div class="line"><a id="l10388" name="l10388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc26c5996b14005a70afbeaa29aae716">10388</a></span><span class="preprocessor">#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk </span></div>
|
||
<div class="line"><a id="l10389" name="l10389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c08aed9f0628271098706c4b46be813">10389</a></span><span class="preprocessor">#define RCC_CSR_BORRSTF_Pos (25U) </span></div>
|
||
<div class="line"><a id="l10390" name="l10390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55345f6a3e5c36cad82d85c3c7c9114c">10390</a></span><span class="preprocessor">#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) </span></div>
|
||
<div class="line"><a id="l10391" name="l10391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6685c7bd94a46c82c7ca69afa1707c39">10391</a></span><span class="preprocessor">#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk </span></div>
|
||
<div class="line"><a id="l10392" name="l10392"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47a45faed934912e57c0dea6d6af8227">10392</a></span><span class="preprocessor">#define RCC_CSR_PINRSTF_Pos (26U)</span></div>
|
||
<div class="line"><a id="l10393" name="l10393"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13e888e00c5b2226b70179c6c69b77a6">10393</a></span><span class="preprocessor">#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) </span></div>
|
||
<div class="line"><a id="l10394" name="l10394"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e26d2902d11e638cd0b702332f53ab1">10394</a></span><span class="preprocessor">#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk</span></div>
|
||
<div class="line"><a id="l10395" name="l10395"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8d531dd5cf68eb67b1bce22ceddaac4">10395</a></span><span class="preprocessor">#define RCC_CSR_PORRSTF_Pos (27U) </span></div>
|
||
<div class="line"><a id="l10396" name="l10396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ea00bd02372ecbc60c5fa71a37dc8dd">10396</a></span><span class="preprocessor">#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) </span></div>
|
||
<div class="line"><a id="l10397" name="l10397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga837e2d7e2395ac45ebe2aea95ecde9bf">10397</a></span><span class="preprocessor">#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk </span></div>
|
||
<div class="line"><a id="l10398" name="l10398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02078fdb0a3610702b75d5e05dbb92af">10398</a></span><span class="preprocessor">#define RCC_CSR_SFTRSTF_Pos (28U) </span></div>
|
||
<div class="line"><a id="l10399" name="l10399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7217efb6cbdb6fbf39721fe496249225">10399</a></span><span class="preprocessor">#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) </span></div>
|
||
<div class="line"><a id="l10400" name="l10400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16e89534934436ee8958440882b71e6f">10400</a></span><span class="preprocessor">#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk </span></div>
|
||
<div class="line"><a id="l10401" name="l10401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fbb93c907ec9ca631e6657eb22b85a3">10401</a></span><span class="preprocessor">#define RCC_CSR_IWDGRSTF_Pos (29U)</span></div>
|
||
<div class="line"><a id="l10402" name="l10402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb81cb1777e6e846b6199b64132bcb97">10402</a></span><span class="preprocessor">#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) </span></div>
|
||
<div class="line"><a id="l10403" name="l10403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22a7079ba87dd7acd5ed7fe7b704e85f">10403</a></span><span class="preprocessor">#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk</span></div>
|
||
<div class="line"><a id="l10404" name="l10404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3b146c508145d8e03143a991615ed81">10404</a></span><span class="preprocessor">#define RCC_CSR_WWDGRSTF_Pos (30U) </span></div>
|
||
<div class="line"><a id="l10405" name="l10405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d9afc0a5d27d08ef63dde9f0a39514d">10405</a></span><span class="preprocessor">#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) </span></div>
|
||
<div class="line"><a id="l10406" name="l10406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacabd7bbde7e78c9c8f5fd46e34771826">10406</a></span><span class="preprocessor">#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk </span></div>
|
||
<div class="line"><a id="l10407" name="l10407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2761b43e9b00d52102efb7375a86e6e0">10407</a></span><span class="preprocessor">#define RCC_CSR_LPWRRSTF_Pos (31U) </span></div>
|
||
<div class="line"><a id="l10408" name="l10408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b42e835fb77d45779cdf4d22a0ea22a">10408</a></span><span class="preprocessor">#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) </span></div>
|
||
<div class="line"><a id="l10409" name="l10409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga675455250b91f125d52f5d347c2c0fbf">10409</a></span><span class="preprocessor">#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk</span></div>
|
||
<div class="line"><a id="l10410" name="l10410"></a><span class="lineno">10410</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l10411" name="l10411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf600bc53fc80265347f6c76c6b8b728a">10411</a></span><span class="preprocessor">#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF</span></div>
|
||
<div class="line"><a id="l10412" name="l10412"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1507e79ffc475547f2a9c9238965b57f">10412</a></span><span class="preprocessor">#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF</span></div>
|
||
<div class="line"><a id="l10413" name="l10413"></a><span class="lineno">10413</span> </div>
|
||
<div class="line"><a id="l10414" name="l10414"></a><span class="lineno">10414</span><span class="comment">/******************** Bit definition for RCC_SSCGR register *****************/</span></div>
|
||
<div class="line"><a id="l10415" name="l10415"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76dd9dc93a74d66a6cb8241d11fb2bf5">10415</a></span><span class="preprocessor">#define RCC_SSCGR_MODPER_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10416" name="l10416"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4446b54ba7ada897a42e3311b946182">10416</a></span><span class="preprocessor">#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos) </span></div>
|
||
<div class="line"><a id="l10417" name="l10417"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6fd9fde5cf03700de4c304b9c5dfb7c">10417</a></span><span class="preprocessor">#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk </span></div>
|
||
<div class="line"><a id="l10418" name="l10418"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0dee22588439c5aa7bc9ee69cb89cce9">10418</a></span><span class="preprocessor">#define RCC_SSCGR_INCSTEP_Pos (13U) </span></div>
|
||
<div class="line"><a id="l10419" name="l10419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea77ceb4a2430c2d297ac24a7ad9303d">10419</a></span><span class="preprocessor">#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos) </span></div>
|
||
<div class="line"><a id="l10420" name="l10420"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f801e25eb841262467f54e7325b7806">10420</a></span><span class="preprocessor">#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk </span></div>
|
||
<div class="line"><a id="l10421" name="l10421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25f92667802ad9c8dc1549d65666a03f">10421</a></span><span class="preprocessor">#define RCC_SSCGR_SPREADSEL_Pos (30U) </span></div>
|
||
<div class="line"><a id="l10422" name="l10422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a8dce731d21ecb6c8bcb873023b979b">10422</a></span><span class="preprocessor">#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10423" name="l10423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga392689f6486224a7f19d7ad0cd195687">10423</a></span><span class="preprocessor">#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk </span></div>
|
||
<div class="line"><a id="l10424" name="l10424"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae934eed92c2081acbeee062e1932943d">10424</a></span><span class="preprocessor">#define RCC_SSCGR_SSCGEN_Pos (31U) </span></div>
|
||
<div class="line"><a id="l10425" name="l10425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77656e179e5741014ea95703f65a4f99">10425</a></span><span class="preprocessor">#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos) </span></div>
|
||
<div class="line"><a id="l10426" name="l10426"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8885c04bcb786b89e26f066f4ccf06e0">10426</a></span><span class="preprocessor">#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk </span></div>
|
||
<div class="line"><a id="l10427" name="l10427"></a><span class="lineno">10427</span> </div>
|
||
<div class="line"><a id="l10428" name="l10428"></a><span class="lineno">10428</span><span class="comment">/******************** Bit definition for RCC_PLLI2SCFGR register ************/</span></div>
|
||
<div class="line"><a id="l10429" name="l10429"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3cf5415c0debb40f8932d59677103a2">10429</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U) </span></div>
|
||
<div class="line"><a id="l10430" name="l10430"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb8781000aaf194d241cee23a637e95e">10430</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) </span></div>
|
||
<div class="line"><a id="l10431" name="l10431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68db5b1d90f9b62359888ed1175a0cef">10431</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk </span></div>
|
||
<div class="line"><a id="l10432" name="l10432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee6ea60de76e294b8ba23d229b2c8a1d">10432</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) </span></div>
|
||
<div class="line"><a id="l10433" name="l10433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60eec842a298febfaadd7b5f79898b00">10433</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) </span></div>
|
||
<div class="line"><a id="l10434" name="l10434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2be70f723d8e89b4566a9438a671f49">10434</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) </span></div>
|
||
<div class="line"><a id="l10435" name="l10435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63743438e947f632c0757a6daf2838af">10435</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) </span></div>
|
||
<div class="line"><a id="l10436" name="l10436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1f94003cdc00380b298b54c485ca743">10436</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) </span></div>
|
||
<div class="line"><a id="l10437" name="l10437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03c368d0e6199b212e7c185663dd2aa8">10437</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) </span></div>
|
||
<div class="line"><a id="l10438" name="l10438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32d9931c3638779af7042d901a01aabf">10438</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) </span></div>
|
||
<div class="line"><a id="l10439" name="l10439"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8dc32ee35e426332598db98b5e0b230b">10439</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) </span></div>
|
||
<div class="line"><a id="l10440" name="l10440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ec1c1bad2b7126f36b2ba26e657e84a">10440</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) </span></div>
|
||
<div class="line"><a id="l10442" name="l10442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93e7478c8a17f7d07b937e180f8f13f4">10442</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U) </span></div>
|
||
<div class="line"><a id="l10443" name="l10443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8ab724070f564a647a4a1ef4e46183e">10443</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) </span></div>
|
||
<div class="line"><a id="l10444" name="l10444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c599fc84dcde859974ed5b334e90f50">10444</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk </span></div>
|
||
<div class="line"><a id="l10445" name="l10445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2b9c8dc6b0e853ace99e16818d55d12">10445</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) </span></div>
|
||
<div class="line"><a id="l10446" name="l10446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb49236fe3c41edb56f8ffb8ab505d86">10446</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) </span></div>
|
||
<div class="line"><a id="l10447" name="l10447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03e58dd5ac710e271fc6ca9113b7e846">10447</a></span><span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) </span></div>
|
||
<div class="line"><a id="l10450" name="l10450"></a><span class="lineno">10450</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l10451" name="l10451"></a><span class="lineno">10451</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l10452" name="l10452"></a><span class="lineno">10452</span><span class="comment">/* RNG */</span></div>
|
||
<div class="line"><a id="l10453" name="l10453"></a><span class="lineno">10453</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l10454" name="l10454"></a><span class="lineno">10454</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l10455" name="l10455"></a><span class="lineno">10455</span><span class="comment">/******************** Bits definition for RNG_CR register *******************/</span></div>
|
||
<div class="line"><a id="l10456" name="l10456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2013ef5a17240897df5b7bf00b7b290">10456</a></span><span class="preprocessor">#define RNG_CR_RNGEN_Pos (2U) </span></div>
|
||
<div class="line"><a id="l10457" name="l10457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeee66d4dd5c33fa16a98b001dd63bd73">10457</a></span><span class="preprocessor">#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) </span></div>
|
||
<div class="line"><a id="l10458" name="l10458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ee81827bb1d78e84e78a74449c8d56a">10458</a></span><span class="preprocessor">#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk </span></div>
|
||
<div class="line"><a id="l10459" name="l10459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d1a529728903ae8659aa26f869f6537">10459</a></span><span class="preprocessor">#define RNG_CR_IE_Pos (3U) </span></div>
|
||
<div class="line"><a id="l10460" name="l10460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8253017bd1f0d7652f107266ffb0297b">10460</a></span><span class="preprocessor">#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) </span></div>
|
||
<div class="line"><a id="l10461" name="l10461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27424b682bcee7fff22f92a2dbcea57a">10461</a></span><span class="preprocessor">#define RNG_CR_IE RNG_CR_IE_Msk </span></div>
|
||
<div class="line"><a id="l10462" name="l10462"></a><span class="lineno">10462</span> </div>
|
||
<div class="line"><a id="l10463" name="l10463"></a><span class="lineno">10463</span><span class="comment">/******************** Bits definition for RNG_SR register *******************/</span></div>
|
||
<div class="line"><a id="l10464" name="l10464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17cb7add2587efeea18a208c76d73727">10464</a></span><span class="preprocessor">#define RNG_SR_DRDY_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10465" name="l10465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd19bcfa8894faf2ac5f57d287f00a8b">10465</a></span><span class="preprocessor">#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) </span></div>
|
||
<div class="line"><a id="l10466" name="l10466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54434ed74bdb00fd0f13422d3e85a2fc">10466</a></span><span class="preprocessor">#define RNG_SR_DRDY RNG_SR_DRDY_Msk </span></div>
|
||
<div class="line"><a id="l10467" name="l10467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga164b5050473dff67a5cd6ca400bb5a89">10467</a></span><span class="preprocessor">#define RNG_SR_CECS_Pos (1U) </span></div>
|
||
<div class="line"><a id="l10468" name="l10468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga699d24eb133814c5be46fe6e588cc093">10468</a></span><span class="preprocessor">#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) </span></div>
|
||
<div class="line"><a id="l10469" name="l10469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bb49d327474c3c61877bb20290f51d0">10469</a></span><span class="preprocessor">#define RNG_SR_CECS RNG_SR_CECS_Msk </span></div>
|
||
<div class="line"><a id="l10470" name="l10470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51e0238194c400f9c6ac0b34826e55eb">10470</a></span><span class="preprocessor">#define RNG_SR_SECS_Pos (2U) </span></div>
|
||
<div class="line"><a id="l10471" name="l10471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a312837097b7b3c2528e17a2cfc5f7d">10471</a></span><span class="preprocessor">#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) </span></div>
|
||
<div class="line"><a id="l10472" name="l10472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5562bc13afe295893dc3997a4917fee2">10472</a></span><span class="preprocessor">#define RNG_SR_SECS RNG_SR_SECS_Msk </span></div>
|
||
<div class="line"><a id="l10473" name="l10473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga341c152f61c352b96fb0c3c245e3d958">10473</a></span><span class="preprocessor">#define RNG_SR_CEIS_Pos (5U) </span></div>
|
||
<div class="line"><a id="l10474" name="l10474"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3efcca0c0381982a8044d09aaa6b6df9">10474</a></span><span class="preprocessor">#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) </span></div>
|
||
<div class="line"><a id="l10475" name="l10475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b89a08bcc8a7a6078bd9f5f2f34bb53">10475</a></span><span class="preprocessor">#define RNG_SR_CEIS RNG_SR_CEIS_Msk </span></div>
|
||
<div class="line"><a id="l10476" name="l10476"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecf22f4de968dc9aa29d55760ebdb980">10476</a></span><span class="preprocessor">#define RNG_SR_SEIS_Pos (6U) </span></div>
|
||
<div class="line"><a id="l10477" name="l10477"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d78e80e064c7746b98ed89304aab367">10477</a></span><span class="preprocessor">#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) </span></div>
|
||
<div class="line"><a id="l10478" name="l10478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6b0e11930f20484f0d0aca79959d9b2">10478</a></span><span class="preprocessor">#define RNG_SR_SEIS RNG_SR_SEIS_Msk </span></div>
|
||
<div class="line"><a id="l10479" name="l10479"></a><span class="lineno">10479</span> </div>
|
||
<div class="line"><a id="l10480" name="l10480"></a><span class="lineno">10480</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l10481" name="l10481"></a><span class="lineno">10481</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l10482" name="l10482"></a><span class="lineno">10482</span><span class="comment">/* Real-Time Clock (RTC) */</span></div>
|
||
<div class="line"><a id="l10483" name="l10483"></a><span class="lineno">10483</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l10484" name="l10484"></a><span class="lineno">10484</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l10485" name="l10485"></a><span class="lineno">10485</span><span class="comment">/*</span></div>
|
||
<div class="line"><a id="l10486" name="l10486"></a><span class="lineno">10486</span><span class="comment"> * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)</span></div>
|
||
<div class="line"><a id="l10487" name="l10487"></a><span class="lineno">10487</span><span class="comment"> */</span></div>
|
||
<div class="line"><a id="l10488" name="l10488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c33bacdb5372bad482df029d77a9e5e">10488</a></span><span class="preprocessor">#define RTC_TAMPER2_SUPPORT </span></div>
|
||
<div class="line"><a id="l10489" name="l10489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b082d5bb4b8d9801fc7370e813b1b3c">10489</a></span><span class="preprocessor">#define RTC_AF2_SUPPORT </span></div>
|
||
<div class="line"><a id="l10490" name="l10490"></a><span class="lineno">10490</span><span class="comment">/******************** Bits definition for RTC_TR register *******************/</span></div>
|
||
<div class="line"><a id="l10491" name="l10491"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2920dc4e941e569491e856c74f655a73">10491</a></span><span class="preprocessor">#define RTC_TR_PM_Pos (22U) </span></div>
|
||
<div class="line"><a id="l10492" name="l10492"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa98be62b42b64aa8dee5df4f84ec1679">10492</a></span><span class="preprocessor">#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) </span></div>
|
||
<div class="line"><a id="l10493" name="l10493"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3152952ac385ee1ce8dd868978d3fce9">10493</a></span><span class="preprocessor">#define RTC_TR_PM RTC_TR_PM_Msk </span></div>
|
||
<div class="line"><a id="l10494" name="l10494"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26458edfa3da49a421547e540b7fef0c">10494</a></span><span class="preprocessor">#define RTC_TR_HT_Pos (20U) </span></div>
|
||
<div class="line"><a id="l10495" name="l10495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3f00fc20610b447daa4b2fcf4730e94">10495</a></span><span class="preprocessor">#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) </span></div>
|
||
<div class="line"><a id="l10496" name="l10496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad42435e015e9f5052245c366ae08d655">10496</a></span><span class="preprocessor">#define RTC_TR_HT RTC_TR_HT_Msk </span></div>
|
||
<div class="line"><a id="l10497" name="l10497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c9af54381689d893ba1b11eb33cd866">10497</a></span><span class="preprocessor">#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) </span></div>
|
||
<div class="line"><a id="l10498" name="l10498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b3ba2cc471b86d041df3c2a1a9ef121">10498</a></span><span class="preprocessor">#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) </span></div>
|
||
<div class="line"><a id="l10499" name="l10499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1412e72836e362ccfe5a927b7760fd14">10499</a></span><span class="preprocessor">#define RTC_TR_HU_Pos (16U) </span></div>
|
||
<div class="line"><a id="l10500" name="l10500"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4be6ca68f00b9467ddad84d37f1b6a63">10500</a></span><span class="preprocessor">#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10501" name="l10501"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8211df481853649722383e0d8fb06d5">10501</a></span><span class="preprocessor">#define RTC_TR_HU RTC_TR_HU_Msk </span></div>
|
||
<div class="line"><a id="l10502" name="l10502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddad920d5681960fa702b988ef1f82be">10502</a></span><span class="preprocessor">#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10503" name="l10503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6206d385d3b3e127b1e63be48f83a63">10503</a></span><span class="preprocessor">#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10504" name="l10504"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e264504542ec2d9b06036e938f7f79d">10504</a></span><span class="preprocessor">#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10505" name="l10505"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40763d3ed48e9f707784bdfd65a9c3ca">10505</a></span><span class="preprocessor">#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10506" name="l10506"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf169c6a3845063073e546f372e90a61a">10506</a></span><span class="preprocessor">#define RTC_TR_MNT_Pos (12U) </span></div>
|
||
<div class="line"><a id="l10507" name="l10507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87978332f15306d7db05c3bce2df2c7f">10507</a></span><span class="preprocessor">#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10508" name="l10508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64cf91576871a8108d6ee2f48970bb4a">10508</a></span><span class="preprocessor">#define RTC_TR_MNT RTC_TR_MNT_Msk </span></div>
|
||
<div class="line"><a id="l10509" name="l10509"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga752747aa90bf35bd57b16bffc7294dfc">10509</a></span><span class="preprocessor">#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10510" name="l10510"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1837f65a11192dd9b8bf249c31ccef7">10510</a></span><span class="preprocessor">#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10511" name="l10511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f27fb43718df0797664acd2d9c95c1a">10511</a></span><span class="preprocessor">#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10512" name="l10512"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5d682cf0198141f2a323981ec266173">10512</a></span><span class="preprocessor">#define RTC_TR_MNU_Pos (8U) </span></div>
|
||
<div class="line"><a id="l10513" name="l10513"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8240cd693ae8c3bf069e10ab08f3adcd">10513</a></span><span class="preprocessor">#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10514" name="l10514"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84e86f4fc04232fd0294966434708e06">10514</a></span><span class="preprocessor">#define RTC_TR_MNU RTC_TR_MNU_Msk </span></div>
|
||
<div class="line"><a id="l10515" name="l10515"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad91d7700822050a352e53aff372a697b">10515</a></span><span class="preprocessor">#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10516" name="l10516"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9c3087e3d4cd490af8334e99467f1dc">10516</a></span><span class="preprocessor">#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10517" name="l10517"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac01a9e4b358ea062bf1c66069a28c126">10517</a></span><span class="preprocessor">#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10518" name="l10518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75b76249e63af249061c0c5532a2a4e5">10518</a></span><span class="preprocessor">#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10519" name="l10519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga641ca04f0ccdab58ac9fe27211719a66">10519</a></span><span class="preprocessor">#define RTC_TR_ST_Pos (4U) </span></div>
|
||
<div class="line"><a id="l10520" name="l10520"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3ae841c3e4f90face971c95f1228419">10520</a></span><span class="preprocessor">#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10521" name="l10521"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae39b22025a36d1e4e185e4be2bf326f">10521</a></span><span class="preprocessor">#define RTC_TR_ST RTC_TR_ST_Msk </span></div>
|
||
<div class="line"><a id="l10522" name="l10522"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0a53dc60816e0790ba69eaff3e87cb0">10522</a></span><span class="preprocessor">#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10523" name="l10523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga948beb7166b70f1fa9e9148a8b6bd3f9">10523</a></span><span class="preprocessor">#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10524" name="l10524"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d5f0413990c26a5cf9a857d10243e9b">10524</a></span><span class="preprocessor">#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10525" name="l10525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a5251e75005627144d7a044045484ca">10525</a></span><span class="preprocessor">#define RTC_TR_SU_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10526" name="l10526"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac65138b7d68cf4db6e391a5e3d31d4a5">10526</a></span><span class="preprocessor">#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10527" name="l10527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga747711823db36121b78c0eebb6140ca1">10527</a></span><span class="preprocessor">#define RTC_TR_SU RTC_TR_SU_Msk </span></div>
|
||
<div class="line"><a id="l10528" name="l10528"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4132b0e9d72ff72df7e0062a1e081ca3">10528</a></span><span class="preprocessor">#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10529" name="l10529"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6eef03c1de3719d801c970eec53e7500">10529</a></span><span class="preprocessor">#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10530" name="l10530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbe7e738c8adaaf24f6faca467d6fde2">10530</a></span><span class="preprocessor">#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10531" name="l10531"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab44e19720b6691f63ba4f0c38a1fd7f3">10531</a></span><span class="preprocessor">#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10533" name="l10533"></a><span class="lineno">10533</span><span class="comment">/******************** Bits definition for RTC_DR register *******************/</span></div>
|
||
<div class="line"><a id="l10534" name="l10534"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee7ed9c50764bdf02c200c9acf963609">10534</a></span><span class="preprocessor">#define RTC_DR_YT_Pos (20U) </span></div>
|
||
<div class="line"><a id="l10535" name="l10535"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ad13d2dbed87fd51194b4d7b080f759">10535</a></span><span class="preprocessor">#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) </span></div>
|
||
<div class="line"><a id="l10536" name="l10536"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14d55b6d841825ec65736e08c09b1d83">10536</a></span><span class="preprocessor">#define RTC_DR_YT RTC_DR_YT_Msk </span></div>
|
||
<div class="line"><a id="l10537" name="l10537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a733698a85cc8f26d346ec8c61c7937">10537</a></span><span class="preprocessor">#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) </span></div>
|
||
<div class="line"><a id="l10538" name="l10538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa48c7c9f31a74b6d3b04443ce0414ce9">10538</a></span><span class="preprocessor">#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) </span></div>
|
||
<div class="line"><a id="l10539" name="l10539"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c15cd22daf2ef6f9ea6f7341897a435">10539</a></span><span class="preprocessor">#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) </span></div>
|
||
<div class="line"><a id="l10540" name="l10540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e7cf7875d489f89d949178e0294d555">10540</a></span><span class="preprocessor">#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) </span></div>
|
||
<div class="line"><a id="l10541" name="l10541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2a117731b1eddef15cf9fa4f3c7a062">10541</a></span><span class="preprocessor">#define RTC_DR_YU_Pos (16U) </span></div>
|
||
<div class="line"><a id="l10542" name="l10542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga261de093e10c99df510d650bea7b65bb">10542</a></span><span class="preprocessor">#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) </span></div>
|
||
<div class="line"><a id="l10543" name="l10543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd1bdc8fad3fdeb14058c9158f39ae9e">10543</a></span><span class="preprocessor">#define RTC_DR_YU RTC_DR_YU_Msk </span></div>
|
||
<div class="line"><a id="l10544" name="l10544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeda03e9857e9009b6212df5f97a5d09f">10544</a></span><span class="preprocessor">#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) </span></div>
|
||
<div class="line"><a id="l10545" name="l10545"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb0b5f7684e31cb1665a848b91601249">10545</a></span><span class="preprocessor">#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) </span></div>
|
||
<div class="line"><a id="l10546" name="l10546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01f200469dbc8159adc3b4f25375b601">10546</a></span><span class="preprocessor">#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) </span></div>
|
||
<div class="line"><a id="l10547" name="l10547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga592372ccddc93b10e81ed705c9c0f9bc">10547</a></span><span class="preprocessor">#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) </span></div>
|
||
<div class="line"><a id="l10548" name="l10548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga751a29a9ead0d70b6104bd366b7ab6af">10548</a></span><span class="preprocessor">#define RTC_DR_WDU_Pos (13U) </span></div>
|
||
<div class="line"><a id="l10549" name="l10549"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacaa60c7147ae02cf5d6e2ee2c87fb5e7">10549</a></span><span class="preprocessor">#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) </span></div>
|
||
<div class="line"><a id="l10550" name="l10550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f46c349f75a31973e094729fe96543f">10550</a></span><span class="preprocessor">#define RTC_DR_WDU RTC_DR_WDU_Msk </span></div>
|
||
<div class="line"><a id="l10551" name="l10551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30cb803b191670a41aea89a91e53fe61">10551</a></span><span class="preprocessor">#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) </span></div>
|
||
<div class="line"><a id="l10552" name="l10552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd26d3601bf8b119af8f96a65a1de60e">10552</a></span><span class="preprocessor">#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) </span></div>
|
||
<div class="line"><a id="l10553" name="l10553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77e907e5efced7628e9933e7cfb4cac6">10553</a></span><span class="preprocessor">#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) </span></div>
|
||
<div class="line"><a id="l10554" name="l10554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d26f621d89bd024ff988b5ecab316ab">10554</a></span><span class="preprocessor">#define RTC_DR_MT_Pos (12U) </span></div>
|
||
<div class="line"><a id="l10555" name="l10555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5358d94c842b122b8bd260a855afb483">10555</a></span><span class="preprocessor">#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) </span></div>
|
||
<div class="line"><a id="l10556" name="l10556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26f0d3ce1c6c6785bd8fbae556f68b31">10556</a></span><span class="preprocessor">#define RTC_DR_MT RTC_DR_MT_Msk </span></div>
|
||
<div class="line"><a id="l10557" name="l10557"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5781bd4d99f08d25b2741a43c0e694a4">10557</a></span><span class="preprocessor">#define RTC_DR_MU_Pos (8U) </span></div>
|
||
<div class="line"><a id="l10558" name="l10558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga614964ed52cb7da4ee76a0f3d16e57bb">10558</a></span><span class="preprocessor">#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) </span></div>
|
||
<div class="line"><a id="l10559" name="l10559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9221f60ccf3581f3c543fdedddf4372">10559</a></span><span class="preprocessor">#define RTC_DR_MU RTC_DR_MU_Msk </span></div>
|
||
<div class="line"><a id="l10560" name="l10560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54f64678df9fe08a2afd732c275ae7a0">10560</a></span><span class="preprocessor">#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) </span></div>
|
||
<div class="line"><a id="l10561" name="l10561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7845ded502c4cc9faeeb6215955f6f1">10561</a></span><span class="preprocessor">#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) </span></div>
|
||
<div class="line"><a id="l10562" name="l10562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47a14479cfe6791d300b9a556d158abe">10562</a></span><span class="preprocessor">#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) </span></div>
|
||
<div class="line"><a id="l10563" name="l10563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a420b221dec229c053295c44bcac1b1">10563</a></span><span class="preprocessor">#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) </span></div>
|
||
<div class="line"><a id="l10564" name="l10564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab12b2bb2b80f5a17c4d6717708cf9d5a">10564</a></span><span class="preprocessor">#define RTC_DR_DT_Pos (4U) </span></div>
|
||
<div class="line"><a id="l10565" name="l10565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47c3834615b1c186a5122c0735e03e09">10565</a></span><span class="preprocessor">#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) </span></div>
|
||
<div class="line"><a id="l10566" name="l10566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52e40cec8161ee20176d92d547fef350">10566</a></span><span class="preprocessor">#define RTC_DR_DT RTC_DR_DT_Msk </span></div>
|
||
<div class="line"><a id="l10567" name="l10567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8823ee9be7a191912aeef8252517b8a6">10567</a></span><span class="preprocessor">#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) </span></div>
|
||
<div class="line"><a id="l10568" name="l10568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga546b218e45c1297e39a586204268cf9d">10568</a></span><span class="preprocessor">#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) </span></div>
|
||
<div class="line"><a id="l10569" name="l10569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4689a554a699f3df0a5939efdbebb94d">10569</a></span><span class="preprocessor">#define RTC_DR_DU_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10570" name="l10570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4549c0127eff71ac5e1e3b7ef07bf158">10570</a></span><span class="preprocessor">#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10571" name="l10571"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba04cbc99cf442c7e6155bef625c5663">10571</a></span><span class="preprocessor">#define RTC_DR_DU RTC_DR_DU_Msk </span></div>
|
||
<div class="line"><a id="l10572" name="l10572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ffd9b610a0ba3f1caad707ff2fb0a3f">10572</a></span><span class="preprocessor">#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10573" name="l10573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79b5d9f674be2ecf85c964da6ac0a2a4">10573</a></span><span class="preprocessor">#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10574" name="l10574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1668f84ec4ddec10f6bcff65983df05b">10574</a></span><span class="preprocessor">#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10575" name="l10575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad54e249241aebdda778618f35dce9f66">10575</a></span><span class="preprocessor">#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10577" name="l10577"></a><span class="lineno">10577</span><span class="comment">/******************** Bits definition for RTC_CR register *******************/</span></div>
|
||
<div class="line"><a id="l10578" name="l10578"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12e2706cb9754f06d60cb87d3ec364ac">10578</a></span><span class="preprocessor">#define RTC_CR_COE_Pos (23U) </span></div>
|
||
<div class="line"><a id="l10579" name="l10579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35471924ed2a9a83b6af8bd8e2251f8b">10579</a></span><span class="preprocessor">#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) </span></div>
|
||
<div class="line"><a id="l10580" name="l10580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cdfa862acfa6068b7ba847f77269d60">10580</a></span><span class="preprocessor">#define RTC_CR_COE RTC_CR_COE_Msk </span></div>
|
||
<div class="line"><a id="l10581" name="l10581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6513acc17cb4c17769ed5dcd03ebde8c">10581</a></span><span class="preprocessor">#define RTC_CR_OSEL_Pos (21U) </span></div>
|
||
<div class="line"><a id="l10582" name="l10582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb684c910bd8e726378e0b51732f952f">10582</a></span><span class="preprocessor">#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10583" name="l10583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f81115ef3fd366de73e84ab667d369b">10583</a></span><span class="preprocessor">#define RTC_CR_OSEL RTC_CR_OSEL_Msk </span></div>
|
||
<div class="line"><a id="l10584" name="l10584"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe506838823e3b172a9ed4a3fec7321a">10584</a></span><span class="preprocessor">#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10585" name="l10585"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15fb33aaad62c71bbba2f96652eefb8c">10585</a></span><span class="preprocessor">#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10586" name="l10586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga013304c1d6002a7c9ec57de637def511">10586</a></span><span class="preprocessor">#define RTC_CR_POL_Pos (20U) </span></div>
|
||
<div class="line"><a id="l10587" name="l10587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga717b2d78f96be49ba9d262f3a0eb09e4">10587</a></span><span class="preprocessor">#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) </span></div>
|
||
<div class="line"><a id="l10588" name="l10588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53f21b5adadbcc5eb255683d5decc9cb">10588</a></span><span class="preprocessor">#define RTC_CR_POL RTC_CR_POL_Msk </span></div>
|
||
<div class="line"><a id="l10589" name="l10589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3ae962f1f8c748682a3136ea5ab76e1">10589</a></span><span class="preprocessor">#define RTC_CR_COSEL_Pos (19U) </span></div>
|
||
<div class="line"><a id="l10590" name="l10590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8dc824636e99382fcd50b39a6fce8dc">10590</a></span><span class="preprocessor">#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10591" name="l10591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga197c587884b9c1dcb2970e9ec2589b41">10591</a></span><span class="preprocessor">#define RTC_CR_COSEL RTC_CR_COSEL_Msk </span></div>
|
||
<div class="line"><a id="l10592" name="l10592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd9f44a96fafedd6c89600a0a14fe87f">10592</a></span><span class="preprocessor">#define RTC_CR_BKP_Pos (18U) </span></div>
|
||
<div class="line"><a id="l10593" name="l10593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3675c7d64de46ab9f1cf279d7abaffe2">10593</a></span><span class="preprocessor">#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) </span></div>
|
||
<div class="line"><a id="l10594" name="l10594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e7a474de1a01816bc9d9b6fa7272289">10594</a></span><span class="preprocessor">#define RTC_CR_BKP RTC_CR_BKP_Msk </span></div>
|
||
<div class="line"><a id="l10595" name="l10595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7614f35a94291525f1dd8cc8f41f960f">10595</a></span><span class="preprocessor">#define RTC_CR_SUB1H_Pos (17U) </span></div>
|
||
<div class="line"><a id="l10596" name="l10596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62402c843252c70670b4b6c9ffec5880">10596</a></span><span class="preprocessor">#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) </span></div>
|
||
<div class="line"><a id="l10597" name="l10597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga220cf6237eac208acc8ae4c55e0b5e6f">10597</a></span><span class="preprocessor">#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk </span></div>
|
||
<div class="line"><a id="l10598" name="l10598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab04a33865dc30af95c633750711fc6d0">10598</a></span><span class="preprocessor">#define RTC_CR_ADD1H_Pos (16U) </span></div>
|
||
<div class="line"><a id="l10599" name="l10599"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01aac32ee74fbafd54de75ee53bf1417">10599</a></span><span class="preprocessor">#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) </span></div>
|
||
<div class="line"><a id="l10600" name="l10600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae1a8439d08e28289398dcf3c2b4b47b">10600</a></span><span class="preprocessor">#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk </span></div>
|
||
<div class="line"><a id="l10601" name="l10601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82db8f745799c761201a13235132a700">10601</a></span><span class="preprocessor">#define RTC_CR_TSIE_Pos (15U) </span></div>
|
||
<div class="line"><a id="l10602" name="l10602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b81fdfb0dbd9719e0eee7b39450bb31">10602</a></span><span class="preprocessor">#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) </span></div>
|
||
<div class="line"><a id="l10603" name="l10603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf376dffb9f2777ef275f23410e35600d">10603</a></span><span class="preprocessor">#define RTC_CR_TSIE RTC_CR_TSIE_Msk </span></div>
|
||
<div class="line"><a id="l10604" name="l10604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1432b0a0a031fe1143d153fe3073d7d2">10604</a></span><span class="preprocessor">#define RTC_CR_WUTIE_Pos (14U) </span></div>
|
||
<div class="line"><a id="l10605" name="l10605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83d862c5a5e56813b86246d22821ac9b">10605</a></span><span class="preprocessor">#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) </span></div>
|
||
<div class="line"><a id="l10606" name="l10606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e0a1419830a16667cea4f6454913226">10606</a></span><span class="preprocessor">#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk </span></div>
|
||
<div class="line"><a id="l10607" name="l10607"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad21245a52288246fbca5b954f38c65e8">10607</a></span><span class="preprocessor">#define RTC_CR_ALRBIE_Pos (13U) </span></div>
|
||
<div class="line"><a id="l10608" name="l10608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e79f603f18cfbc266cc55162b739260">10608</a></span><span class="preprocessor">#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) </span></div>
|
||
<div class="line"><a id="l10609" name="l10609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6269c9dd5cee650024ede0b0c42e87d">10609</a></span><span class="preprocessor">#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk </span></div>
|
||
<div class="line"><a id="l10610" name="l10610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd69cebbc7fc4a81655a7e53a7284b70">10610</a></span><span class="preprocessor">#define RTC_CR_ALRAIE_Pos (12U) </span></div>
|
||
<div class="line"><a id="l10611" name="l10611"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0efcbd64f981117d73fe6d631c48f45e">10611</a></span><span class="preprocessor">#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) </span></div>
|
||
<div class="line"><a id="l10612" name="l10612"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9138f75267bd93f8de6738225217d583">10612</a></span><span class="preprocessor">#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk </span></div>
|
||
<div class="line"><a id="l10613" name="l10613"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf95c6afbdb29aa5241dc3e52d28ce884">10613</a></span><span class="preprocessor">#define RTC_CR_TSE_Pos (11U) </span></div>
|
||
<div class="line"><a id="l10614" name="l10614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2675d723ea5e54a4e6a7c7bd975efcc">10614</a></span><span class="preprocessor">#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) </span></div>
|
||
<div class="line"><a id="l10615" name="l10615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94fa98ca8cac9078b9bb82c89593d3c0">10615</a></span><span class="preprocessor">#define RTC_CR_TSE RTC_CR_TSE_Msk </span></div>
|
||
<div class="line"><a id="l10616" name="l10616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf919254119ed634798f3b936dc01e66d">10616</a></span><span class="preprocessor">#define RTC_CR_WUTE_Pos (10U) </span></div>
|
||
<div class="line"><a id="l10617" name="l10617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5b45d595cd44d31a7f34609b6e7bf1a">10617</a></span><span class="preprocessor">#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) </span></div>
|
||
<div class="line"><a id="l10618" name="l10618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga061be0d3cdea721e5cb695cda0699bc3">10618</a></span><span class="preprocessor">#define RTC_CR_WUTE RTC_CR_WUTE_Msk </span></div>
|
||
<div class="line"><a id="l10619" name="l10619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae534f6bb5933c05bc2b63aa70907bfb2">10619</a></span><span class="preprocessor">#define RTC_CR_ALRBE_Pos (9U) </span></div>
|
||
<div class="line"><a id="l10620" name="l10620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae811bd5a731a4d12d5fabc1c1701e7a">10620</a></span><span class="preprocessor">#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) </span></div>
|
||
<div class="line"><a id="l10621" name="l10621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17d0850002ed42742ff75a82dc4e8586">10621</a></span><span class="preprocessor">#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk </span></div>
|
||
<div class="line"><a id="l10622" name="l10622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54e3cfdf0409a6e26568fa59c9b5283b">10622</a></span><span class="preprocessor">#define RTC_CR_ALRAE_Pos (8U) </span></div>
|
||
<div class="line"><a id="l10623" name="l10623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1adc6f86be463291c228b8a2bd3cfa40">10623</a></span><span class="preprocessor">#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) </span></div>
|
||
<div class="line"><a id="l10624" name="l10624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a8cdeac61f06e4737800b64a901d584">10624</a></span><span class="preprocessor">#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk </span></div>
|
||
<div class="line"><a id="l10625" name="l10625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab362e94b8e99714082eb0981045a28b7">10625</a></span><span class="preprocessor">#define RTC_CR_DCE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l10626" name="l10626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga005e60bfb5de91f5d9635d1e8e63f6d3">10626</a></span><span class="preprocessor">#define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos) </span></div>
|
||
<div class="line"><a id="l10627" name="l10627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ce7cb8b575142e125863d61ea4765ba">10627</a></span><span class="preprocessor">#define RTC_CR_DCE RTC_CR_DCE_Msk </span></div>
|
||
<div class="line"><a id="l10628" name="l10628"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga262f18e12c214c9f172860b3a1234f0e">10628</a></span><span class="preprocessor">#define RTC_CR_FMT_Pos (6U) </span></div>
|
||
<div class="line"><a id="l10629" name="l10629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6634873135b509b3a483abcbd1e0f347">10629</a></span><span class="preprocessor">#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) </span></div>
|
||
<div class="line"><a id="l10630" name="l10630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2706e31a1bc8d95b682fe47611e0dd3">10630</a></span><span class="preprocessor">#define RTC_CR_FMT RTC_CR_FMT_Msk </span></div>
|
||
<div class="line"><a id="l10631" name="l10631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace008c8514db9131ae301e7577979130">10631</a></span><span class="preprocessor">#define RTC_CR_BYPSHAD_Pos (5U) </span></div>
|
||
<div class="line"><a id="l10632" name="l10632"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93e690c1dc87dff6f36fea71cf6bb57c">10632</a></span><span class="preprocessor">#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) </span></div>
|
||
<div class="line"><a id="l10633" name="l10633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34d50a3eff3364e6da4fefed9962a054">10633</a></span><span class="preprocessor">#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk </span></div>
|
||
<div class="line"><a id="l10634" name="l10634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae970d1c321c777685111e4a4f70ce44c">10634</a></span><span class="preprocessor">#define RTC_CR_REFCKON_Pos (4U) </span></div>
|
||
<div class="line"><a id="l10635" name="l10635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd611d89bc17e379525602d5ea3a7d54">10635</a></span><span class="preprocessor">#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) </span></div>
|
||
<div class="line"><a id="l10636" name="l10636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga646ef1071cacc2d30bbef5597c817021">10636</a></span><span class="preprocessor">#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk </span></div>
|
||
<div class="line"><a id="l10637" name="l10637"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18a34610d5a2a22e66b027341ac6191b">10637</a></span><span class="preprocessor">#define RTC_CR_TSEDGE_Pos (3U) </span></div>
|
||
<div class="line"><a id="l10638" name="l10638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ea0c6b68ad8797d97693cbc7fe76d8e">10638</a></span><span class="preprocessor">#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) </span></div>
|
||
<div class="line"><a id="l10639" name="l10639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad076bde34be7d24f088fd2c003b7a7f7">10639</a></span><span class="preprocessor">#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk </span></div>
|
||
<div class="line"><a id="l10640" name="l10640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad30da1c2029c23889c4dd29ee8fa7eea">10640</a></span><span class="preprocessor">#define RTC_CR_WUCKSEL_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10641" name="l10641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1961b22823e4f592ac8d1733e079e2a">10641</a></span><span class="preprocessor">#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10642" name="l10642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54a2d55571417d9dfb05826b40d997b0">10642</a></span><span class="preprocessor">#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk </span></div>
|
||
<div class="line"><a id="l10643" name="l10643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f03056e9aa78c133af90b60af72ba79">10643</a></span><span class="preprocessor">#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10644" name="l10644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga360f7ccf7a89c5091f4affe6d1019215">10644</a></span><span class="preprocessor">#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10645" name="l10645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad247ac722f6900744cdc16f8f45ed923">10645</a></span><span class="preprocessor">#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10647" name="l10647"></a><span class="lineno">10647</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l10648" name="l10648"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a793580db48c66a98e44cbda6e0daef">10648</a></span><span class="preprocessor">#define RTC_CR_BCK RTC_CR_BKP</span></div>
|
||
<div class="line"><a id="l10649" name="l10649"></a><span class="lineno">10649</span> </div>
|
||
<div class="line"><a id="l10650" name="l10650"></a><span class="lineno">10650</span><span class="comment">/******************** Bits definition for RTC_ISR register ******************/</span></div>
|
||
<div class="line"><a id="l10651" name="l10651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa59397ca25b1fc9fbc43cfca986c14e4">10651</a></span><span class="preprocessor">#define RTC_ISR_RECALPF_Pos (16U) </span></div>
|
||
<div class="line"><a id="l10652" name="l10652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ab18f49ac6ab32322ebb58131a456ea">10652</a></span><span class="preprocessor">#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) </span></div>
|
||
<div class="line"><a id="l10653" name="l10653"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05189137cfd0e73903d9b70d071656b9">10653</a></span><span class="preprocessor">#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk </span></div>
|
||
<div class="line"><a id="l10654" name="l10654"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf18fa672ae72db52c7a6c5a2658a5190">10654</a></span><span class="preprocessor">#define RTC_ISR_TAMP1F_Pos (13U) </span></div>
|
||
<div class="line"><a id="l10655" name="l10655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84bbb84dba6aef26a16b2410c3a3ec5d">10655</a></span><span class="preprocessor">#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) </span></div>
|
||
<div class="line"><a id="l10656" name="l10656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae738b22f6a8123026921a1d14f9547c0">10656</a></span><span class="preprocessor">#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk </span></div>
|
||
<div class="line"><a id="l10657" name="l10657"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0347e70fa9f25a6a52d3ceac1713ccee">10657</a></span><span class="preprocessor">#define RTC_ISR_TAMP2F_Pos (14U) </span></div>
|
||
<div class="line"><a id="l10658" name="l10658"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga436cbba9b17ad91735e876596c8a6914">10658</a></span><span class="preprocessor">#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) </span></div>
|
||
<div class="line"><a id="l10659" name="l10659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdb176578e53b2d8e24a94c8d0212845">10659</a></span><span class="preprocessor">#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk </span></div>
|
||
<div class="line"><a id="l10660" name="l10660"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa38f2ee43244798276792a0c5a64f41e">10660</a></span><span class="preprocessor">#define RTC_ISR_TSOVF_Pos (12U) </span></div>
|
||
<div class="line"><a id="l10661" name="l10661"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a44c6cf950526be3f768c9175e3e62e">10661</a></span><span class="preprocessor">#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) </span></div>
|
||
<div class="line"><a id="l10662" name="l10662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga766c238f964072decba204c7fce850ff">10662</a></span><span class="preprocessor">#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk </span></div>
|
||
<div class="line"><a id="l10663" name="l10663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09bb6ceebab0b76cd2121816e787749a">10663</a></span><span class="preprocessor">#define RTC_ISR_TSF_Pos (11U) </span></div>
|
||
<div class="line"><a id="l10664" name="l10664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f5151d79a2761d423ddbc0b6c3cca1f">10664</a></span><span class="preprocessor">#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) </span></div>
|
||
<div class="line"><a id="l10665" name="l10665"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68c0a60dbfc5f1570a48afe450395484">10665</a></span><span class="preprocessor">#define RTC_ISR_TSF RTC_ISR_TSF_Msk </span></div>
|
||
<div class="line"><a id="l10666" name="l10666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6c5050a881336d0a8710d096fe4b01a">10666</a></span><span class="preprocessor">#define RTC_ISR_WUTF_Pos (10U) </span></div>
|
||
<div class="line"><a id="l10667" name="l10667"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53360cc2baf2a2142289493b2a16c372">10667</a></span><span class="preprocessor">#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) </span></div>
|
||
<div class="line"><a id="l10668" name="l10668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4eb5960300a402210e5378d78ce22766">10668</a></span><span class="preprocessor">#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk </span></div>
|
||
<div class="line"><a id="l10669" name="l10669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4891bf442ab59fa4488bc0ed308c56c2">10669</a></span><span class="preprocessor">#define RTC_ISR_ALRBF_Pos (9U) </span></div>
|
||
<div class="line"><a id="l10670" name="l10670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac80e30a64a34bd547229f68b76d63a87">10670</a></span><span class="preprocessor">#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) </span></div>
|
||
<div class="line"><a id="l10671" name="l10671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7976972a5fc6705fede85536520367d6">10671</a></span><span class="preprocessor">#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk </span></div>
|
||
<div class="line"><a id="l10672" name="l10672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bbb887fab178f2ad6c26fe28bd16cd6">10672</a></span><span class="preprocessor">#define RTC_ISR_ALRAF_Pos (8U) </span></div>
|
||
<div class="line"><a id="l10673" name="l10673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5aeb3a57686a3bca74ebce43559161e">10673</a></span><span class="preprocessor">#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) </span></div>
|
||
<div class="line"><a id="l10674" name="l10674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96605e50a347507b7f274e9cd894a02c">10674</a></span><span class="preprocessor">#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk </span></div>
|
||
<div class="line"><a id="l10675" name="l10675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9a0e0b639b59be3c662267184bddf69">10675</a></span><span class="preprocessor">#define RTC_ISR_INIT_Pos (7U) </span></div>
|
||
<div class="line"><a id="l10676" name="l10676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5e864e670cc4643c1e65b21da150c74">10676</a></span><span class="preprocessor">#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) </span></div>
|
||
<div class="line"><a id="l10677" name="l10677"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0eb2f998cd3e7325974347cb2a3d25a">10677</a></span><span class="preprocessor">#define RTC_ISR_INIT RTC_ISR_INIT_Msk </span></div>
|
||
<div class="line"><a id="l10678" name="l10678"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga601564e925eefdbde3aafdcbf0a978c5">10678</a></span><span class="preprocessor">#define RTC_ISR_INITF_Pos (6U) </span></div>
|
||
<div class="line"><a id="l10679" name="l10679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a29ce1f3e261024726679c17f42a9b1">10679</a></span><span class="preprocessor">#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) </span></div>
|
||
<div class="line"><a id="l10680" name="l10680"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab16dcc6973c611e087030cdb15203972">10680</a></span><span class="preprocessor">#define RTC_ISR_INITF RTC_ISR_INITF_Msk </span></div>
|
||
<div class="line"><a id="l10681" name="l10681"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8dd0bed53ed3cc1bbc70efa82bcac846">10681</a></span><span class="preprocessor">#define RTC_ISR_RSF_Pos (5U) </span></div>
|
||
<div class="line"><a id="l10682" name="l10682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f87ecd7737391a4ff0c236a17dbfd32">10682</a></span><span class="preprocessor">#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) </span></div>
|
||
<div class="line"><a id="l10683" name="l10683"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9bd683e789841f7d3f138709ffdbfbf8">10683</a></span><span class="preprocessor">#define RTC_ISR_RSF RTC_ISR_RSF_Msk </span></div>
|
||
<div class="line"><a id="l10684" name="l10684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6f7e11d89c6480d68013ce7c0478045">10684</a></span><span class="preprocessor">#define RTC_ISR_INITS_Pos (4U) </span></div>
|
||
<div class="line"><a id="l10685" name="l10685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25131777233cef2dfffdc178667559e4">10685</a></span><span class="preprocessor">#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) </span></div>
|
||
<div class="line"><a id="l10686" name="l10686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b229bace5ba0c0b48bfeb5efc445292">10686</a></span><span class="preprocessor">#define RTC_ISR_INITS RTC_ISR_INITS_Msk </span></div>
|
||
<div class="line"><a id="l10687" name="l10687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4312f68d569942ac8d1b6abfb0f5aad">10687</a></span><span class="preprocessor">#define RTC_ISR_SHPF_Pos (3U) </span></div>
|
||
<div class="line"><a id="l10688" name="l10688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36cc41c7b626c5047f97fac12337395d">10688</a></span><span class="preprocessor">#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) </span></div>
|
||
<div class="line"><a id="l10689" name="l10689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c4536a874336778ac11109f14573eb9">10689</a></span><span class="preprocessor">#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk </span></div>
|
||
<div class="line"><a id="l10690" name="l10690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d75a29fa323d93d3d0bb2cb60b24474">10690</a></span><span class="preprocessor">#define RTC_ISR_WUTWF_Pos (2U) </span></div>
|
||
<div class="line"><a id="l10691" name="l10691"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga673f0ff6267142391ca1d37289b305f2">10691</a></span><span class="preprocessor">#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) </span></div>
|
||
<div class="line"><a id="l10692" name="l10692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e753321211e19bc48736fe0d30a7f40">10692</a></span><span class="preprocessor">#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk </span></div>
|
||
<div class="line"><a id="l10693" name="l10693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga011f9bc215e39c91f33f0472e0b59643">10693</a></span><span class="preprocessor">#define RTC_ISR_ALRBWF_Pos (1U) </span></div>
|
||
<div class="line"><a id="l10694" name="l10694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cf9f3b0159c2f29749babdc55ef1a1b">10694</a></span><span class="preprocessor">#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) </span></div>
|
||
<div class="line"><a id="l10695" name="l10695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a0c34bff6dc9fce29e2be35d32d9d05">10695</a></span><span class="preprocessor">#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk </span></div>
|
||
<div class="line"><a id="l10696" name="l10696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab296f795ad4fa25ad0cb3c92967f9565">10696</a></span><span class="preprocessor">#define RTC_ISR_ALRAWF_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10697" name="l10697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4d96dae4fdd343fe6e9ebc7c5f7d80d">10697</a></span><span class="preprocessor">#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) </span></div>
|
||
<div class="line"><a id="l10698" name="l10698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d420b5c3f8623cf1116d42fa164be7e">10698</a></span><span class="preprocessor">#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk </span></div>
|
||
<div class="line"><a id="l10699" name="l10699"></a><span class="lineno">10699</span> </div>
|
||
<div class="line"><a id="l10700" name="l10700"></a><span class="lineno">10700</span><span class="comment">/******************** Bits definition for RTC_PRER register *****************/</span></div>
|
||
<div class="line"><a id="l10701" name="l10701"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8240c029696ad91531c3fec1ef1e7fe">10701</a></span><span class="preprocessor">#define RTC_PRER_PREDIV_A_Pos (16U) </span></div>
|
||
<div class="line"><a id="l10702" name="l10702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f883861bb963a097885c5773f3c0b15">10702</a></span><span class="preprocessor">#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) </span></div>
|
||
<div class="line"><a id="l10703" name="l10703"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad248dca1e9532ba31f98d3ec9d2f8711">10703</a></span><span class="preprocessor">#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk </span></div>
|
||
<div class="line"><a id="l10704" name="l10704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga234f46098c91b34aa12502d70cdb93bf">10704</a></span><span class="preprocessor">#define RTC_PRER_PREDIV_S_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10705" name="l10705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga776acde6c1789c37371eb440492825ab">10705</a></span><span class="preprocessor">#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) </span></div>
|
||
<div class="line"><a id="l10706" name="l10706"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17bbd4e569a76446df089752cb41b1cb">10706</a></span><span class="preprocessor">#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk </span></div>
|
||
<div class="line"><a id="l10707" name="l10707"></a><span class="lineno">10707</span> </div>
|
||
<div class="line"><a id="l10708" name="l10708"></a><span class="lineno">10708</span><span class="comment">/******************** Bits definition for RTC_WUTR register *****************/</span></div>
|
||
<div class="line"><a id="l10709" name="l10709"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae50a0fcd154d36aa0b506a875e8d100e">10709</a></span><span class="preprocessor">#define RTC_WUTR_WUT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10710" name="l10710"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c2d178daf42c0febdbf67583a83b6a0">10710</a></span><span class="preprocessor">#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) </span></div>
|
||
<div class="line"><a id="l10711" name="l10711"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e412c1448a7e20974f5b46129799eeb">10711</a></span><span class="preprocessor">#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk </span></div>
|
||
<div class="line"><a id="l10712" name="l10712"></a><span class="lineno">10712</span> </div>
|
||
<div class="line"><a id="l10713" name="l10713"></a><span class="lineno">10713</span><span class="comment">/******************** Bits definition for RTC_CALIBR register ***************/</span></div>
|
||
<div class="line"><a id="l10714" name="l10714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79b734efd7f580384b76364f8159ce2a">10714</a></span><span class="preprocessor">#define RTC_CALIBR_DCS_Pos (7U) </span></div>
|
||
<div class="line"><a id="l10715" name="l10715"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac975f6abc1ae98deb38d1c523a564431">10715</a></span><span class="preprocessor">#define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos) </span></div>
|
||
<div class="line"><a id="l10716" name="l10716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa63841fd7262fd307f211ee8e9e8a6f0">10716</a></span><span class="preprocessor">#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk </span></div>
|
||
<div class="line"><a id="l10717" name="l10717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga612c3ec0e88f91fd34cfb4910b5b46fb">10717</a></span><span class="preprocessor">#define RTC_CALIBR_DC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10718" name="l10718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb0820dbde8c1188a5c045e6e264c1f8">10718</a></span><span class="preprocessor">#define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos) </span></div>
|
||
<div class="line"><a id="l10719" name="l10719"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5523cf582ebc0a987c6a2c2007bc10d">10719</a></span><span class="preprocessor">#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk </span></div>
|
||
<div class="line"><a id="l10720" name="l10720"></a><span class="lineno">10720</span> </div>
|
||
<div class="line"><a id="l10721" name="l10721"></a><span class="lineno">10721</span><span class="comment">/******************** Bits definition for RTC_ALRMAR register ***************/</span></div>
|
||
<div class="line"><a id="l10722" name="l10722"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4c443ed6c81b3ce75dd5e8dd97939fb">10722</a></span><span class="preprocessor">#define RTC_ALRMAR_MSK4_Pos (31U) </span></div>
|
||
<div class="line"><a id="l10723" name="l10723"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ade8f686276ed4761f3741cd928b500">10723</a></span><span class="preprocessor">#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) </span></div>
|
||
<div class="line"><a id="l10724" name="l10724"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ed557e4451ffd3e869bb9ca393d47f9">10724</a></span><span class="preprocessor">#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk </span></div>
|
||
<div class="line"><a id="l10725" name="l10725"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd589f750a310c033dafdab213642649">10725</a></span><span class="preprocessor">#define RTC_ALRMAR_WDSEL_Pos (30U) </span></div>
|
||
<div class="line"><a id="l10726" name="l10726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccf0424c522933862730917c9c79f81b">10726</a></span><span class="preprocessor">#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10727" name="l10727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a7fdc1719b3159e099c3979da26dd92">10727</a></span><span class="preprocessor">#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk </span></div>
|
||
<div class="line"><a id="l10728" name="l10728"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4d605cd74901b7544c8a6cc9f446436">10728</a></span><span class="preprocessor">#define RTC_ALRMAR_DT_Pos (28U) </span></div>
|
||
<div class="line"><a id="l10729" name="l10729"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b864018e7de62c954d6fff34bde926f">10729</a></span><span class="preprocessor">#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) </span></div>
|
||
<div class="line"><a id="l10730" name="l10730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga934ea7910b5f5988f6c46ae4703dc29b">10730</a></span><span class="preprocessor">#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk </span></div>
|
||
<div class="line"><a id="l10731" name="l10731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cb880cece843ba5314120abcf14e9fc">10731</a></span><span class="preprocessor">#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) </span></div>
|
||
<div class="line"><a id="l10732" name="l10732"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e2e76ce2645d0c9d2587d4172edcd58">10732</a></span><span class="preprocessor">#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) </span></div>
|
||
<div class="line"><a id="l10733" name="l10733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab5a8a73b82a0e8c16f7f5dc35166622">10733</a></span><span class="preprocessor">#define RTC_ALRMAR_DU_Pos (24U) </span></div>
|
||
<div class="line"><a id="l10734" name="l10734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f818fa2666247ad93611752020097b1">10734</a></span><span class="preprocessor">#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10735" name="l10735"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga784589946bdf3ca0d675cc22d9bafbbf">10735</a></span><span class="preprocessor">#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk </span></div>
|
||
<div class="line"><a id="l10736" name="l10736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga687a85ed4e7623bdb60196f706ab62e9">10736</a></span><span class="preprocessor">#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10737" name="l10737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d2ec65de047fdece20083f030cc6cfd">10737</a></span><span class="preprocessor">#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10738" name="l10738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb0050d5e8d64e4f684e325446ea173a">10738</a></span><span class="preprocessor">#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10739" name="l10739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79a55db963d0707fc0ae14bffc51c297">10739</a></span><span class="preprocessor">#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10740" name="l10740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4744abec80afe01487c6133d9325f47b">10740</a></span><span class="preprocessor">#define RTC_ALRMAR_MSK3_Pos (23U) </span></div>
|
||
<div class="line"><a id="l10741" name="l10741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b72eca3af2788a6df2aab8efdf48c7e">10741</a></span><span class="preprocessor">#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) </span></div>
|
||
<div class="line"><a id="l10742" name="l10742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga337fba397cab4beb204f4f6e6ddc4bf3">10742</a></span><span class="preprocessor">#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk </span></div>
|
||
<div class="line"><a id="l10743" name="l10743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85bfa4c2296c553269373a411323b21f">10743</a></span><span class="preprocessor">#define RTC_ALRMAR_PM_Pos (22U) </span></div>
|
||
<div class="line"><a id="l10744" name="l10744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ed4ff622a2ac83edfaadc596995c61a">10744</a></span><span class="preprocessor">#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) </span></div>
|
||
<div class="line"><a id="l10745" name="l10745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab68dc30427951b19aecf399b0ae2900">10745</a></span><span class="preprocessor">#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk </span></div>
|
||
<div class="line"><a id="l10746" name="l10746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadeb1eb233c192d56b4a4f106b3fb4be2">10746</a></span><span class="preprocessor">#define RTC_ALRMAR_HT_Pos (20U) </span></div>
|
||
<div class="line"><a id="l10747" name="l10747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfbc262cd63d3a1c5cdf4937cc57ec37">10747</a></span><span class="preprocessor">#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) </span></div>
|
||
<div class="line"><a id="l10748" name="l10748"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55bc04190e9eaa916144fa2d1777cbfb">10748</a></span><span class="preprocessor">#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk </span></div>
|
||
<div class="line"><a id="l10749" name="l10749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4165b904cdf6bdf4ed6c892d73953453">10749</a></span><span class="preprocessor">#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) </span></div>
|
||
<div class="line"><a id="l10750" name="l10750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab50f98903ad0183c52c40375d45d4d77">10750</a></span><span class="preprocessor">#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) </span></div>
|
||
<div class="line"><a id="l10751" name="l10751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga914c62bbd3ce817fd1d6f871ed894222">10751</a></span><span class="preprocessor">#define RTC_ALRMAR_HU_Pos (16U) </span></div>
|
||
<div class="line"><a id="l10752" name="l10752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d3da70f04ca3c7c2f90ee0d0d3c9201">10752</a></span><span class="preprocessor">#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10753" name="l10753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga491fda42cfad244596737347fe157142">10753</a></span><span class="preprocessor">#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk </span></div>
|
||
<div class="line"><a id="l10754" name="l10754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga756c2c137f6d1f89bba95347245b014c">10754</a></span><span class="preprocessor">#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10755" name="l10755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2068b4116fca73a63b1c98f51902acef">10755</a></span><span class="preprocessor">#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10756" name="l10756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7642e83ff425a1fe2695d1100ce7c35">10756</a></span><span class="preprocessor">#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10757" name="l10757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f516916142b3ea6110619e8dc600d2a">10757</a></span><span class="preprocessor">#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10758" name="l10758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae87ea1c4a907654aa4565047647afa30">10758</a></span><span class="preprocessor">#define RTC_ALRMAR_MSK2_Pos (15U) </span></div>
|
||
<div class="line"><a id="l10759" name="l10759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe0fda62acb0b820b859291e4b45e409">10759</a></span><span class="preprocessor">#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) </span></div>
|
||
<div class="line"><a id="l10760" name="l10760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga478d62d55a42779c558e9ba16aec74cc">10760</a></span><span class="preprocessor">#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk </span></div>
|
||
<div class="line"><a id="l10761" name="l10761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee274022f516021cba28dede0ff60450">10761</a></span><span class="preprocessor">#define RTC_ALRMAR_MNT_Pos (12U) </span></div>
|
||
<div class="line"><a id="l10762" name="l10762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac320cc91348b22f3e5c0d6106594c09e">10762</a></span><span class="preprocessor">#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10763" name="l10763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02edb2d87b7fe9936a0cffa96d4a7297">10763</a></span><span class="preprocessor">#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk </span></div>
|
||
<div class="line"><a id="l10764" name="l10764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0dab36fbc475b7ec4442020f159601c6">10764</a></span><span class="preprocessor">#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10765" name="l10765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6782f11cc7f8edf401dec2ff436d7968">10765</a></span><span class="preprocessor">#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10766" name="l10766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf766f39637efe114b38a1aceb352328d">10766</a></span><span class="preprocessor">#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10767" name="l10767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4fd9dea59596ad989af2bce818b1b93">10767</a></span><span class="preprocessor">#define RTC_ALRMAR_MNU_Pos (8U) </span></div>
|
||
<div class="line"><a id="l10768" name="l10768"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac05e67cdb4da1882dd5b8f5a8fe51bb2">10768</a></span><span class="preprocessor">#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10769" name="l10769"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22d67ff770aa27509d79afde1865c845">10769</a></span><span class="preprocessor">#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk </span></div>
|
||
<div class="line"><a id="l10770" name="l10770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb5ead84647f92b0d1efcf8decb0dd8f">10770</a></span><span class="preprocessor">#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10771" name="l10771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga656311cb5632dbc9b4fb5dd2288a6e66">10771</a></span><span class="preprocessor">#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10772" name="l10772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc164d7ff70842858281cfaff5f29374">10772</a></span><span class="preprocessor">#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10773" name="l10773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e1199b4140613e8a1dbe283dd89c772">10773</a></span><span class="preprocessor">#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10774" name="l10774"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbad0bb69a65557c15042154b66eab52">10774</a></span><span class="preprocessor">#define RTC_ALRMAR_MSK1_Pos (7U) </span></div>
|
||
<div class="line"><a id="l10775" name="l10775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga838b33a3595df6fe68152bb31f812beb">10775</a></span><span class="preprocessor">#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) </span></div>
|
||
<div class="line"><a id="l10776" name="l10776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8862250866a358ff3095852f45a160c1">10776</a></span><span class="preprocessor">#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk </span></div>
|
||
<div class="line"><a id="l10777" name="l10777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83d9812296958846b0fd24484b205ebd">10777</a></span><span class="preprocessor">#define RTC_ALRMAR_ST_Pos (4U) </span></div>
|
||
<div class="line"><a id="l10778" name="l10778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f558ae0134c82f7f64c31a4d8bb33f0">10778</a></span><span class="preprocessor">#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10779" name="l10779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b623884457edb89f48a2a100aff183a">10779</a></span><span class="preprocessor">#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk </span></div>
|
||
<div class="line"><a id="l10780" name="l10780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae5c1ad41702da26788f5ef52c0d05ca">10780</a></span><span class="preprocessor">#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10781" name="l10781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e771d8055c52a1186d3f47dd567457a">10781</a></span><span class="preprocessor">#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10782" name="l10782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fdfe4a92c7ab0c326dc9f2638318f97">10782</a></span><span class="preprocessor">#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10783" name="l10783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30f4084231cdc1f72bec8c63dac981a3">10783</a></span><span class="preprocessor">#define RTC_ALRMAR_SU_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10784" name="l10784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37bf69143ae7921782d1baa390c1c866">10784</a></span><span class="preprocessor">#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10785" name="l10785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8ec4171be73457bc3dba78bd246e35b">10785</a></span><span class="preprocessor">#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk </span></div>
|
||
<div class="line"><a id="l10786" name="l10786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaaf99585af681202a201178f8156dffe">10786</a></span><span class="preprocessor">#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10787" name="l10787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d7edbd0609415ca3a328f8498c4a63c">10787</a></span><span class="preprocessor">#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10788" name="l10788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga485a8c274aa56f705dc1363484d7085f">10788</a></span><span class="preprocessor">#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10789" name="l10789"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9d41833996dbd77a0bfbcd9889957a2">10789</a></span><span class="preprocessor">#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10791" name="l10791"></a><span class="lineno">10791</span><span class="comment">/******************** Bits definition for RTC_ALRMBR register ***************/</span></div>
|
||
<div class="line"><a id="l10792" name="l10792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2383d51761039ce9b70e6a33bfde165a">10792</a></span><span class="preprocessor">#define RTC_ALRMBR_MSK4_Pos (31U) </span></div>
|
||
<div class="line"><a id="l10793" name="l10793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6359d5b79cd667e4f7f093e0d0ee8320">10793</a></span><span class="preprocessor">#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) </span></div>
|
||
<div class="line"><a id="l10794" name="l10794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga934df96e83f72268528e62c55c03b50d">10794</a></span><span class="preprocessor">#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk </span></div>
|
||
<div class="line"><a id="l10795" name="l10795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac975a5ed682b832e8600dba67aa9ad37">10795</a></span><span class="preprocessor">#define RTC_ALRMBR_WDSEL_Pos (30U) </span></div>
|
||
<div class="line"><a id="l10796" name="l10796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff53d89da5c55043f8d32e800319b0c0">10796</a></span><span class="preprocessor">#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10797" name="l10797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3acc5db599b055a0c1eca04024bf0285">10797</a></span><span class="preprocessor">#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk </span></div>
|
||
<div class="line"><a id="l10798" name="l10798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade6a75b6e4614f322bf046e07cabc022">10798</a></span><span class="preprocessor">#define RTC_ALRMBR_DT_Pos (28U) </span></div>
|
||
<div class="line"><a id="l10799" name="l10799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf438133a0350e3c1f9e956ea59c165e">10799</a></span><span class="preprocessor">#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) </span></div>
|
||
<div class="line"><a id="l10800" name="l10800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f8662da4b5f9f0dc0cdd8eac037052b">10800</a></span><span class="preprocessor">#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk </span></div>
|
||
<div class="line"><a id="l10801" name="l10801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34531fadcc9d2a702b3b7138831fb4c8">10801</a></span><span class="preprocessor">#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) </span></div>
|
||
<div class="line"><a id="l10802" name="l10802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabeb8410cfd578e600049846a694dc00d">10802</a></span><span class="preprocessor">#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) </span></div>
|
||
<div class="line"><a id="l10803" name="l10803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga553d2edb82ee8d85c71f795276bb4bba">10803</a></span><span class="preprocessor">#define RTC_ALRMBR_DU_Pos (24U) </span></div>
|
||
<div class="line"><a id="l10804" name="l10804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba5234dbab35f4bcc6b1a49b633c9d83">10804</a></span><span class="preprocessor">#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10805" name="l10805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0beeb5e7c9237d688d5784dba0a5c671">10805</a></span><span class="preprocessor">#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk </span></div>
|
||
<div class="line"><a id="l10806" name="l10806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9886cb39e9c89c40ddc33c6e7659db5">10806</a></span><span class="preprocessor">#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10807" name="l10807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga121e8284bdc7ebd634f71e5810dc4f85">10807</a></span><span class="preprocessor">#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10808" name="l10808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78b99f99d3666212ab673dbc9f7f3192">10808</a></span><span class="preprocessor">#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10809" name="l10809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8551995a404be9f58511ea22dca71f1a">10809</a></span><span class="preprocessor">#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10810" name="l10810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2424f9d237a98722a6276d7effa078b7">10810</a></span><span class="preprocessor">#define RTC_ALRMBR_MSK3_Pos (23U) </span></div>
|
||
<div class="line"><a id="l10811" name="l10811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a10ef06416ab43ddcc978f7c484fd30">10811</a></span><span class="preprocessor">#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) </span></div>
|
||
<div class="line"><a id="l10812" name="l10812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca7cd93178102c8769d0874d5b8394c4">10812</a></span><span class="preprocessor">#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk </span></div>
|
||
<div class="line"><a id="l10813" name="l10813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b091bf9f116760614f434cd54a8132e">10813</a></span><span class="preprocessor">#define RTC_ALRMBR_PM_Pos (22U) </span></div>
|
||
<div class="line"><a id="l10814" name="l10814"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb73d11c2f8f01d03b143bf0eb50a3c1">10814</a></span><span class="preprocessor">#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) </span></div>
|
||
<div class="line"><a id="l10815" name="l10815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4fc947f41bd2a091b13ffeff4312b67b">10815</a></span><span class="preprocessor">#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk </span></div>
|
||
<div class="line"><a id="l10816" name="l10816"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbe2cd364c4d4701876832245cf20ce1">10816</a></span><span class="preprocessor">#define RTC_ALRMBR_HT_Pos (20U) </span></div>
|
||
<div class="line"><a id="l10817" name="l10817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1a64e9998a2032590d32d8e93ac89ad">10817</a></span><span class="preprocessor">#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) </span></div>
|
||
<div class="line"><a id="l10818" name="l10818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga552fbb873fbab8cefd1c5c3536d0989d">10818</a></span><span class="preprocessor">#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk </span></div>
|
||
<div class="line"><a id="l10819" name="l10819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbddfb1b1ff41f1b76f5ccfb6eb29362">10819</a></span><span class="preprocessor">#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) </span></div>
|
||
<div class="line"><a id="l10820" name="l10820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3219c5b314ca459c8dcb93c140b210cb">10820</a></span><span class="preprocessor">#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) </span></div>
|
||
<div class="line"><a id="l10821" name="l10821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5880949c342cf52cc4596e73dc1f84e">10821</a></span><span class="preprocessor">#define RTC_ALRMBR_HU_Pos (16U) </span></div>
|
||
<div class="line"><a id="l10822" name="l10822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16f950667f6001e8b23b88b355cc072a">10822</a></span><span class="preprocessor">#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10823" name="l10823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a01e42db93b9bc9097766d7ccf2d21d">10823</a></span><span class="preprocessor">#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk </span></div>
|
||
<div class="line"><a id="l10824" name="l10824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0223058b7ae0a4ae57a7a7997440385e">10824</a></span><span class="preprocessor">#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10825" name="l10825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a7c34c4e83f374790e3ed27a3e23443">10825</a></span><span class="preprocessor">#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10826" name="l10826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5e6d673134918e74d9a0f06ca4dc479">10826</a></span><span class="preprocessor">#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10827" name="l10827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae538b44aa24031a294442dc47f6849f5">10827</a></span><span class="preprocessor">#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10828" name="l10828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga757c08763995ee18cb34d7dd04a8f2d0">10828</a></span><span class="preprocessor">#define RTC_ALRMBR_MSK2_Pos (15U) </span></div>
|
||
<div class="line"><a id="l10829" name="l10829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a678de5920eddb36f8edc45c992aa10">10829</a></span><span class="preprocessor">#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) </span></div>
|
||
<div class="line"><a id="l10830" name="l10830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga124c24eb148681777758f1298776f5a1">10830</a></span><span class="preprocessor">#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk </span></div>
|
||
<div class="line"><a id="l10831" name="l10831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga995f7d294d4b202db6a6c06c0c40b325">10831</a></span><span class="preprocessor">#define RTC_ALRMBR_MNT_Pos (12U) </span></div>
|
||
<div class="line"><a id="l10832" name="l10832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4abe6f205a3aafc2fdd5930b06ca5250">10832</a></span><span class="preprocessor">#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10833" name="l10833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05e2ef0960c04023b98a104202f44571">10833</a></span><span class="preprocessor">#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk </span></div>
|
||
<div class="line"><a id="l10834" name="l10834"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1170e6bedeafe4da96568080fe3bbe3">10834</a></span><span class="preprocessor">#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10835" name="l10835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56977652001bc709e4c37fce5647eb40">10835</a></span><span class="preprocessor">#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10836" name="l10836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbdfd2b2b1fc039fe8efdd6df612b220">10836</a></span><span class="preprocessor">#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10837" name="l10837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabec1334e452f9f973603fa7de232ec93">10837</a></span><span class="preprocessor">#define RTC_ALRMBR_MNU_Pos (8U) </span></div>
|
||
<div class="line"><a id="l10838" name="l10838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14ee879ec288fff19824ee589b54972b">10838</a></span><span class="preprocessor">#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10839" name="l10839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ca0feaf431b9f9dde4a9d97cae39056">10839</a></span><span class="preprocessor">#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk </span></div>
|
||
<div class="line"><a id="l10840" name="l10840"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93830709da4736a2e8da1cf3a3596dda">10840</a></span><span class="preprocessor">#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10841" name="l10841"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9cab4a9df6a1e45e2a3212b357e1bef">10841</a></span><span class="preprocessor">#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10842" name="l10842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga869e14a514b3d140a2dcad669e2ab3e0">10842</a></span><span class="preprocessor">#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10843" name="l10843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec666ddc3d2c205d46d4e1e5bdcf9243">10843</a></span><span class="preprocessor">#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10844" name="l10844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46564dcbbf9eec8854fa091155045f90">10844</a></span><span class="preprocessor">#define RTC_ALRMBR_MSK1_Pos (7U) </span></div>
|
||
<div class="line"><a id="l10845" name="l10845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f741db655cf45b9b6b254c491f3738d">10845</a></span><span class="preprocessor">#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) </span></div>
|
||
<div class="line"><a id="l10846" name="l10846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa472193eb2ace80c95874c850236b489">10846</a></span><span class="preprocessor">#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk </span></div>
|
||
<div class="line"><a id="l10847" name="l10847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62ce834a2d4f2d1b2d338b1e8da054d5">10847</a></span><span class="preprocessor">#define RTC_ALRMBR_ST_Pos (4U) </span></div>
|
||
<div class="line"><a id="l10848" name="l10848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c1a51469b2ad8675eeee8a39ea29ff7">10848</a></span><span class="preprocessor">#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10849" name="l10849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7a6c70156cd32b6aa855e4f2e32406c">10849</a></span><span class="preprocessor">#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk </span></div>
|
||
<div class="line"><a id="l10850" name="l10850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2514a54011c9ff7b48939e9cbd13f859">10850</a></span><span class="preprocessor">#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10851" name="l10851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6b6e10efeaeac2898a754e2a360fb27">10851</a></span><span class="preprocessor">#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10852" name="l10852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga423e1673ab928b5e43e9fa9b65d2122c">10852</a></span><span class="preprocessor">#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10853" name="l10853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef14da4012b4e250c549154393537c3b">10853</a></span><span class="preprocessor">#define RTC_ALRMBR_SU_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10854" name="l10854"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b09e067d4a36bd9c6a85ec3193da6d2">10854</a></span><span class="preprocessor">#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10855" name="l10855"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2fdd1ad6a4b7db36ece6145cba49ccf">10855</a></span><span class="preprocessor">#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk </span></div>
|
||
<div class="line"><a id="l10856" name="l10856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1aa325b93084bf6fdc494842e1f0b652">10856</a></span><span class="preprocessor">#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10857" name="l10857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72ed3dd8ae6a59462a99f8c3d8c316e5">10857</a></span><span class="preprocessor">#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10858" name="l10858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac21f97b7b207139ffb0d1e6ede81bb91">10858</a></span><span class="preprocessor">#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10859" name="l10859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b548175b400ee92c11c2c446d6d129b">10859</a></span><span class="preprocessor">#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10861" name="l10861"></a><span class="lineno">10861</span><span class="comment">/******************** Bits definition for RTC_WPR register ******************/</span></div>
|
||
<div class="line"><a id="l10862" name="l10862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8567138f5a3dddde68b6cdda56e41846">10862</a></span><span class="preprocessor">#define RTC_WPR_KEY_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10863" name="l10863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81983eda15eb251ae9e94a8290450cb1">10863</a></span><span class="preprocessor">#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) </span></div>
|
||
<div class="line"><a id="l10864" name="l10864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d21f29da0e92b2744719aab37278b07">10864</a></span><span class="preprocessor">#define RTC_WPR_KEY RTC_WPR_KEY_Msk </span></div>
|
||
<div class="line"><a id="l10865" name="l10865"></a><span class="lineno">10865</span> </div>
|
||
<div class="line"><a id="l10866" name="l10866"></a><span class="lineno">10866</span><span class="comment">/******************** Bits definition for RTC_SSR register ******************/</span></div>
|
||
<div class="line"><a id="l10867" name="l10867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8cf2c5e2058a406fcb12ef8263f4bf7">10867</a></span><span class="preprocessor">#define RTC_SSR_SS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10868" name="l10868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e04530ca01c9863f847c09f51f64304">10868</a></span><span class="preprocessor">#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) </span></div>
|
||
<div class="line"><a id="l10869" name="l10869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3881f27b6c7a5c7609b1393682144aed">10869</a></span><span class="preprocessor">#define RTC_SSR_SS RTC_SSR_SS_Msk </span></div>
|
||
<div class="line"><a id="l10870" name="l10870"></a><span class="lineno">10870</span> </div>
|
||
<div class="line"><a id="l10871" name="l10871"></a><span class="lineno">10871</span><span class="comment">/******************** Bits definition for RTC_SHIFTR register ***************/</span></div>
|
||
<div class="line"><a id="l10872" name="l10872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga043d4cba6c3d17ce136ed8e8fc6ae318">10872</a></span><span class="preprocessor">#define RTC_SHIFTR_SUBFS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10873" name="l10873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58c15ddd7f663060a1e540ded10aab86">10873</a></span><span class="preprocessor">#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) </span></div>
|
||
<div class="line"><a id="l10874" name="l10874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6131eb8c293b98bc5a6c7a4bb1920450">10874</a></span><span class="preprocessor">#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk </span></div>
|
||
<div class="line"><a id="l10875" name="l10875"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0fdeb64a850c9840a1c140203e61d2f">10875</a></span><span class="preprocessor">#define RTC_SHIFTR_ADD1S_Pos (31U) </span></div>
|
||
<div class="line"><a id="l10876" name="l10876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga145edd31d622a96121168d7f54af1f63">10876</a></span><span class="preprocessor">#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) </span></div>
|
||
<div class="line"><a id="l10877" name="l10877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fee932563d21382db9ecad458356af2">10877</a></span><span class="preprocessor">#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk </span></div>
|
||
<div class="line"><a id="l10878" name="l10878"></a><span class="lineno">10878</span> </div>
|
||
<div class="line"><a id="l10879" name="l10879"></a><span class="lineno">10879</span><span class="comment">/******************** Bits definition for RTC_TSTR register *****************/</span></div>
|
||
<div class="line"><a id="l10880" name="l10880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c6a72f9bab0b1783762c3c612d5a0e6">10880</a></span><span class="preprocessor">#define RTC_TSTR_PM_Pos (22U) </span></div>
|
||
<div class="line"><a id="l10881" name="l10881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga844125f323c84655caa5d09de90d676a">10881</a></span><span class="preprocessor">#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) </span></div>
|
||
<div class="line"><a id="l10882" name="l10882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84b3d044be3e63573a5f0d4d14d8e3b0">10882</a></span><span class="preprocessor">#define RTC_TSTR_PM RTC_TSTR_PM_Msk </span></div>
|
||
<div class="line"><a id="l10883" name="l10883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga380cea6fd8d7736ad8d83bce9c6f4379">10883</a></span><span class="preprocessor">#define RTC_TSTR_HT_Pos (20U) </span></div>
|
||
<div class="line"><a id="l10884" name="l10884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1c592f62a64ad486af67101a02badba">10884</a></span><span class="preprocessor">#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) </span></div>
|
||
<div class="line"><a id="l10885" name="l10885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5765274cda5284899563191cb505235a">10885</a></span><span class="preprocessor">#define RTC_TSTR_HT RTC_TSTR_HT_Msk </span></div>
|
||
<div class="line"><a id="l10886" name="l10886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b682daaa79917786d55c2bf44a80325">10886</a></span><span class="preprocessor">#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) </span></div>
|
||
<div class="line"><a id="l10887" name="l10887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a35c1a1f98f2aeb73235d940922f9cf">10887</a></span><span class="preprocessor">#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) </span></div>
|
||
<div class="line"><a id="l10888" name="l10888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab82c3482dd42a99d0a28d52cfb89be11">10888</a></span><span class="preprocessor">#define RTC_TSTR_HU_Pos (16U) </span></div>
|
||
<div class="line"><a id="l10889" name="l10889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bd9c8067bccd2967bbbb5cd3bad9375">10889</a></span><span class="preprocessor">#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10890" name="l10890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf12107fe82e4f9de5ae4fdd6c169a846">10890</a></span><span class="preprocessor">#define RTC_TSTR_HU RTC_TSTR_HU_Msk </span></div>
|
||
<div class="line"><a id="l10891" name="l10891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a235fd8965c706e7f57327f6e5ce72d">10891</a></span><span class="preprocessor">#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10892" name="l10892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56f2bc31a8d01d7621de40d146b15fb7">10892</a></span><span class="preprocessor">#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10893" name="l10893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d848f11cf3130bb6560d117f97b7da3">10893</a></span><span class="preprocessor">#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10894" name="l10894"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga703c813d88b2c9ab350cb0218ff4bbe7">10894</a></span><span class="preprocessor">#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l10895" name="l10895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae41110f902c7d1b538021d157da48a23">10895</a></span><span class="preprocessor">#define RTC_TSTR_MNT_Pos (12U) </span></div>
|
||
<div class="line"><a id="l10896" name="l10896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7eefd1e26e643f63b5550cebcfb7a597">10896</a></span><span class="preprocessor">#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10897" name="l10897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9743a3843868c712945a7c408183ad73">10897</a></span><span class="preprocessor">#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk </span></div>
|
||
<div class="line"><a id="l10898" name="l10898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf04bea9e3f4645257b8bd955f3ba80ce">10898</a></span><span class="preprocessor">#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10899" name="l10899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf30459ae8455ad0fb382dd866446c83">10899</a></span><span class="preprocessor">#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10900" name="l10900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga513f78562b18cfc36f52e80be9cb20d5">10900</a></span><span class="preprocessor">#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) </span></div>
|
||
<div class="line"><a id="l10901" name="l10901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada4e4f24245be3e28d06c606bb1bd9e8">10901</a></span><span class="preprocessor">#define RTC_TSTR_MNU_Pos (8U) </span></div>
|
||
<div class="line"><a id="l10902" name="l10902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga989ebeea3d902970e5189c667f08dd57">10902</a></span><span class="preprocessor">#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10903" name="l10903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64b186af486822cc015cfec613f5cba9">10903</a></span><span class="preprocessor">#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk </span></div>
|
||
<div class="line"><a id="l10904" name="l10904"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8ff1f79f2ab33d00a979979d486bc44">10904</a></span><span class="preprocessor">#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10905" name="l10905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga506d192fef16558c9b0b7ed9e1a9147c">10905</a></span><span class="preprocessor">#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10906" name="l10906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga407a93c758b95a1ebf3c41c36fb6f07e">10906</a></span><span class="preprocessor">#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10907" name="l10907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac55cd85d2e58a819637d15f70f7179a0">10907</a></span><span class="preprocessor">#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) </span></div>
|
||
<div class="line"><a id="l10908" name="l10908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a4e53ced662f212e19f30ccf60fdf74">10908</a></span><span class="preprocessor">#define RTC_TSTR_ST_Pos (4U) </span></div>
|
||
<div class="line"><a id="l10909" name="l10909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga653df3d0cdd6c8235762f5152dda55c9">10909</a></span><span class="preprocessor">#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10910" name="l10910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fbdebcd1da2ea191cca51c222345f15">10910</a></span><span class="preprocessor">#define RTC_TSTR_ST RTC_TSTR_ST_Msk </span></div>
|
||
<div class="line"><a id="l10911" name="l10911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90d733a561ad71ee4c63c4e0a3ed5f32">10911</a></span><span class="preprocessor">#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10912" name="l10912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga807073dc98612721530a79df5b5c265a">10912</a></span><span class="preprocessor">#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10913" name="l10913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee05d278bdd457b4f61d797e45520d13">10913</a></span><span class="preprocessor">#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l10914" name="l10914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24f2a25eab6521118adf40765216cfe4">10914</a></span><span class="preprocessor">#define RTC_TSTR_SU_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10915" name="l10915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf868c2dda50075428856aa7551f712c4">10915</a></span><span class="preprocessor">#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10916" name="l10916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0d8fa76d45faccfe931d6227b29565a">10916</a></span><span class="preprocessor">#define RTC_TSTR_SU RTC_TSTR_SU_Msk </span></div>
|
||
<div class="line"><a id="l10917" name="l10917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8990f4d1d493012289778e854c52e97e">10917</a></span><span class="preprocessor">#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10918" name="l10918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab6f4275d2a15e7307363124c03a64a4">10918</a></span><span class="preprocessor">#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10919" name="l10919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5610b3103a8a6653204f4fe7e9ea8587">10919</a></span><span class="preprocessor">#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10920" name="l10920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28790ae937a50ba6fb4aff5a9f5afbcb">10920</a></span><span class="preprocessor">#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) </span></div>
|
||
<div class="line"><a id="l10922" name="l10922"></a><span class="lineno">10922</span><span class="comment">/******************** Bits definition for RTC_TSDR register *****************/</span></div>
|
||
<div class="line"><a id="l10923" name="l10923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac365337a0d8e54ad40e3d4abeba10d33">10923</a></span><span class="preprocessor">#define RTC_TSDR_WDU_Pos (13U) </span></div>
|
||
<div class="line"><a id="l10924" name="l10924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9022409e82c29cf18da7efe49032caf">10924</a></span><span class="preprocessor">#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) </span></div>
|
||
<div class="line"><a id="l10925" name="l10925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c76ea431470b87f22e7854bd5438d2f">10925</a></span><span class="preprocessor">#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk </span></div>
|
||
<div class="line"><a id="l10926" name="l10926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e9cbf062e41eecacccde522e24452c1">10926</a></span><span class="preprocessor">#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) </span></div>
|
||
<div class="line"><a id="l10927" name="l10927"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44259df3c6dc88e8168c7dcd5e6abf91">10927</a></span><span class="preprocessor">#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) </span></div>
|
||
<div class="line"><a id="l10928" name="l10928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f2add59486679cc53f521c139d72852">10928</a></span><span class="preprocessor">#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) </span></div>
|
||
<div class="line"><a id="l10929" name="l10929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b1a8d81075b72d48e99990de9a22f98">10929</a></span><span class="preprocessor">#define RTC_TSDR_MT_Pos (12U) </span></div>
|
||
<div class="line"><a id="l10930" name="l10930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab11fc35bffeed3dbfb7f08e75f8319da">10930</a></span><span class="preprocessor">#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) </span></div>
|
||
<div class="line"><a id="l10931" name="l10931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7bce43482443f2038a8eebc681067dd7">10931</a></span><span class="preprocessor">#define RTC_TSDR_MT RTC_TSDR_MT_Msk </span></div>
|
||
<div class="line"><a id="l10932" name="l10932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30556fea7362882afb160a1108ef0539">10932</a></span><span class="preprocessor">#define RTC_TSDR_MU_Pos (8U) </span></div>
|
||
<div class="line"><a id="l10933" name="l10933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85638fe2912aec33b38fcfc51e97aa2e">10933</a></span><span class="preprocessor">#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) </span></div>
|
||
<div class="line"><a id="l10934" name="l10934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a5912337df16624b4703d2065c5fdf4">10934</a></span><span class="preprocessor">#define RTC_TSDR_MU RTC_TSDR_MU_Msk </span></div>
|
||
<div class="line"><a id="l10935" name="l10935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9cf9d23d49e121268a25445a7eed2f35">10935</a></span><span class="preprocessor">#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) </span></div>
|
||
<div class="line"><a id="l10936" name="l10936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49093134e4ead8b4990e5e1628db0692">10936</a></span><span class="preprocessor">#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) </span></div>
|
||
<div class="line"><a id="l10937" name="l10937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7f31eb674f5a67402b6a3eb578b70a5">10937</a></span><span class="preprocessor">#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) </span></div>
|
||
<div class="line"><a id="l10938" name="l10938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad67666c54ef1be79a500484a5e755827">10938</a></span><span class="preprocessor">#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) </span></div>
|
||
<div class="line"><a id="l10939" name="l10939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02d8e7630640b836002e20b25726e7f8">10939</a></span><span class="preprocessor">#define RTC_TSDR_DT_Pos (4U) </span></div>
|
||
<div class="line"><a id="l10940" name="l10940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4e5fcdf15ef6bff31a9fa1857f88811">10940</a></span><span class="preprocessor">#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) </span></div>
|
||
<div class="line"><a id="l10941" name="l10941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39c9ff61f3b622b829aa9354ca84e44e">10941</a></span><span class="preprocessor">#define RTC_TSDR_DT RTC_TSDR_DT_Msk </span></div>
|
||
<div class="line"><a id="l10942" name="l10942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81e02a917946bddaa027a04538576533">10942</a></span><span class="preprocessor">#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) </span></div>
|
||
<div class="line"><a id="l10943" name="l10943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga886739ae0e8c0f6144dbd774c203ed5f">10943</a></span><span class="preprocessor">#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) </span></div>
|
||
<div class="line"><a id="l10944" name="l10944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga031ca4fddcc1f40b7db8b46ec32ed60c">10944</a></span><span class="preprocessor">#define RTC_TSDR_DU_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10945" name="l10945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f1e801e7d2a8c93a4ac5272a6037dde">10945</a></span><span class="preprocessor">#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10946" name="l10946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace7ca73ebca21ed3a17315f06757042a">10946</a></span><span class="preprocessor">#define RTC_TSDR_DU RTC_TSDR_DU_Msk </span></div>
|
||
<div class="line"><a id="l10947" name="l10947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08b7eccac0c3cd20a3f3cd8bce1693ad">10947</a></span><span class="preprocessor">#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10948" name="l10948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa43ed53b8109ff32755885127ba987ce">10948</a></span><span class="preprocessor">#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10949" name="l10949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b3d774b7df9cff6e6eecafa7c42a059">10949</a></span><span class="preprocessor">#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10950" name="l10950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga209573a43dd1f21ef569d75593ad03f8">10950</a></span><span class="preprocessor">#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) </span></div>
|
||
<div class="line"><a id="l10952" name="l10952"></a><span class="lineno">10952</span><span class="comment">/******************** Bits definition for RTC_TSSSR register ****************/</span></div>
|
||
<div class="line"><a id="l10953" name="l10953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac381e2fe1c99a95a6a41f1845d6f207f">10953</a></span><span class="preprocessor">#define RTC_TSSSR_SS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10954" name="l10954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d13c3c83f99d3bdf8fc33ea42b3aecd">10954</a></span><span class="preprocessor">#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) </span></div>
|
||
<div class="line"><a id="l10955" name="l10955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fb913ce5f1c0e341b308d9b5858bfa9">10955</a></span><span class="preprocessor">#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk </span></div>
|
||
<div class="line"><a id="l10956" name="l10956"></a><span class="lineno">10956</span> </div>
|
||
<div class="line"><a id="l10957" name="l10957"></a><span class="lineno">10957</span><span class="comment">/******************** Bits definition for RTC_CAL register *****************/</span></div>
|
||
<div class="line"><a id="l10958" name="l10958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5458d41d3893259a7c1adcb12626552d">10958</a></span><span class="preprocessor">#define RTC_CALR_CALP_Pos (15U) </span></div>
|
||
<div class="line"><a id="l10959" name="l10959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5632e54eb1a07b95a3024c2a52665a24">10959</a></span><span class="preprocessor">#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) </span></div>
|
||
<div class="line"><a id="l10960" name="l10960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b13b9724302c25fbca76684f5968528">10960</a></span><span class="preprocessor">#define RTC_CALR_CALP RTC_CALR_CALP_Msk </span></div>
|
||
<div class="line"><a id="l10961" name="l10961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ad4a6054ae32e1332b456d59e0aa36c">10961</a></span><span class="preprocessor">#define RTC_CALR_CALW8_Pos (14U) </span></div>
|
||
<div class="line"><a id="l10962" name="l10962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4a1d426d16a747f07e8d8cf98c7275e">10962</a></span><span class="preprocessor">#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) </span></div>
|
||
<div class="line"><a id="l10963" name="l10963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28f8c7f5f5bf772c81170a2eab055557">10963</a></span><span class="preprocessor">#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk </span></div>
|
||
<div class="line"><a id="l10964" name="l10964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ac54a062e43b815b226acdb30888ca9">10964</a></span><span class="preprocessor">#define RTC_CALR_CALW16_Pos (13U) </span></div>
|
||
<div class="line"><a id="l10965" name="l10965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa75bb89101a1da73b2d78c1486dbf2e2">10965</a></span><span class="preprocessor">#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) </span></div>
|
||
<div class="line"><a id="l10966" name="l10966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70857526590d6f7e25d9551187105583">10966</a></span><span class="preprocessor">#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk </span></div>
|
||
<div class="line"><a id="l10967" name="l10967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga702670ae12e1600fea81ef41ea485fd6">10967</a></span><span class="preprocessor">#define RTC_CALR_CALM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l10968" name="l10968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga347a7b8bed29029bd0d8a78ce03268c8">10968</a></span><span class="preprocessor">#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) </span></div>
|
||
<div class="line"><a id="l10969" name="l10969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44fcacd12e1cfc1fa823c798cb6a7663">10969</a></span><span class="preprocessor">#define RTC_CALR_CALM RTC_CALR_CALM_Msk </span></div>
|
||
<div class="line"><a id="l10970" name="l10970"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeffec95cc4cbbdbc77e907818b8c7ebd">10970</a></span><span class="preprocessor">#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) </span></div>
|
||
<div class="line"><a id="l10971" name="l10971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b908b77786838e5e2e8a1ee2cbbeeff">10971</a></span><span class="preprocessor">#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) </span></div>
|
||
<div class="line"><a id="l10972" name="l10972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad09f14c1ff24a01d51d5b6c0bba220d6">10972</a></span><span class="preprocessor">#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) </span></div>
|
||
<div class="line"><a id="l10973" name="l10973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9146fbef6a53896f3160c89ed651b90">10973</a></span><span class="preprocessor">#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) </span></div>
|
||
<div class="line"><a id="l10974" name="l10974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fe04fc9762d3f680f9145a50898c27b">10974</a></span><span class="preprocessor">#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) </span></div>
|
||
<div class="line"><a id="l10975" name="l10975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc4966c71cab83be4069e0566222d375">10975</a></span><span class="preprocessor">#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) </span></div>
|
||
<div class="line"><a id="l10976" name="l10976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae240b185d0c9c6e314a456627e6e4834">10976</a></span><span class="preprocessor">#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) </span></div>
|
||
<div class="line"><a id="l10977" name="l10977"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8880325073e167137366402f15d5683">10977</a></span><span class="preprocessor">#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) </span></div>
|
||
<div class="line"><a id="l10978" name="l10978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8381cc75166acfc4b4c686ad7e5e599a">10978</a></span><span class="preprocessor">#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) </span></div>
|
||
<div class="line"><a id="l10980" name="l10980"></a><span class="lineno">10980</span><span class="comment">/******************** Bits definition for RTC_TAFCR register ****************/</span></div>
|
||
<div class="line"><a id="l10981" name="l10981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga288c98bc30ac4f55ee038b66deef21eb">10981</a></span><span class="preprocessor">#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U) </span></div>
|
||
<div class="line"><a id="l10982" name="l10982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga070badc7e2d642aeff89371370f5cb7d">10982</a></span><span class="preprocessor">#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) </span></div>
|
||
<div class="line"><a id="l10983" name="l10983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d9515fd74e3bcf03f4e62d8c7e1b070">10983</a></span><span class="preprocessor">#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk </span></div>
|
||
<div class="line"><a id="l10984" name="l10984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5a7a74b471a19d3b24624ed76c9123d">10984</a></span><span class="preprocessor">#define RTC_TAFCR_TSINSEL_Pos (17U) </span></div>
|
||
<div class="line"><a id="l10985" name="l10985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafffa3d4d97beee57ef7c1b80a20fee7e">10985</a></span><span class="preprocessor">#define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10986" name="l10986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga872cbfe2e79e7fe2a4bfad6086f4ac49">10986</a></span><span class="preprocessor">#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk </span></div>
|
||
<div class="line"><a id="l10987" name="l10987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b8c154291563140f9ab1b938b20e39a">10987</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP1INSEL_Pos (16U) </span></div>
|
||
<div class="line"><a id="l10988" name="l10988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6032dc793590fd715ea61340429b1848">10988</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos) </span></div>
|
||
<div class="line"><a id="l10989" name="l10989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5934e2b2ada22a92862a9ea5356a2665">10989</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk </span></div>
|
||
<div class="line"><a id="l10990" name="l10990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad46c537f405a4424f17cf6f47a0bdc7c">10990</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPPUDIS_Pos (15U) </span></div>
|
||
<div class="line"><a id="l10991" name="l10991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabaa57d1e8d33a2b5c8ab6aad4ec6fba0">10991</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) </span></div>
|
||
<div class="line"><a id="l10992" name="l10992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ef294e75771913e4a47386f42a23f72">10992</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk </span></div>
|
||
<div class="line"><a id="l10993" name="l10993"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0650b78abfcc5a3a6b247fb9791b9292">10993</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPPRCH_Pos (13U) </span></div>
|
||
<div class="line"><a id="l10994" name="l10994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76638587b6e5989ffe219851a96e4f8f">10994</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) </span></div>
|
||
<div class="line"><a id="l10995" name="l10995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b73d2b8da78967a6f594dbffe58c222">10995</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk </span></div>
|
||
<div class="line"><a id="l10996" name="l10996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae010ed965c1e968cc14f988d50662546">10996</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) </span></div>
|
||
<div class="line"><a id="l10997" name="l10997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16f0faa59aa4490d696d1fec767aae41">10997</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) </span></div>
|
||
<div class="line"><a id="l10998" name="l10998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga978ec86db46d77d83e1627a563e5a622">10998</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPFLT_Pos (11U) </span></div>
|
||
<div class="line"><a id="l10999" name="l10999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf978c259714ae9072766be91c8d982c">10999</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) </span></div>
|
||
<div class="line"><a id="l11000" name="l11000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1cb37c43747c779f7db2842a2582e67">11000</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk </span></div>
|
||
<div class="line"><a id="l11001" name="l11001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa356fb5db5ab398728afef0ae39214c4">11001</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) </span></div>
|
||
<div class="line"><a id="l11002" name="l11002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga472efa1bd3c9462cbd058d73a7d6525e">11002</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) </span></div>
|
||
<div class="line"><a id="l11003" name="l11003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga487bd3ad7900df341c4fe63fb409d2bd">11003</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPFREQ_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11004" name="l11004"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e169834a26329219aa2271781756dfb">11004</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) </span></div>
|
||
<div class="line"><a id="l11005" name="l11005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ad84446486b8c9f640fa54d50ecc0e1">11005</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk </span></div>
|
||
<div class="line"><a id="l11006" name="l11006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54e7f69e04759d1b0667e56830a6f2ea">11006</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) </span></div>
|
||
<div class="line"><a id="l11007" name="l11007"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb533067640fcf87ad77027ce936e9b7">11007</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) </span></div>
|
||
<div class="line"><a id="l11008" name="l11008"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf532e727bfe6c7fc7822d15f9436e1b5">11008</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) </span></div>
|
||
<div class="line"><a id="l11009" name="l11009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73e4ad22e6610c5c39fbc548b621b244">11009</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPTS_Pos (7U) </span></div>
|
||
<div class="line"><a id="l11010" name="l11010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga195a1c8285f2826479b6afb75576ac3d">11010</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) </span></div>
|
||
<div class="line"><a id="l11011" name="l11011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac929fab94fdca2d1b3b3cf7c93fe6e49">11011</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk </span></div>
|
||
<div class="line"><a id="l11012" name="l11012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d0e27811bd76fcf94c2f802df2a742f">11012</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP2TRG_Pos (4U) </span></div>
|
||
<div class="line"><a id="l11013" name="l11013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92f7e43c7127ffa0dac5c94233360852">11013</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) </span></div>
|
||
<div class="line"><a id="l11014" name="l11014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2c4d227971b56e3160c71b7479c769d">11014</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk </span></div>
|
||
<div class="line"><a id="l11015" name="l11015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac46ab34c29b3dfa1dc0c3866cb52ce9f">11015</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP2E_Pos (3U) </span></div>
|
||
<div class="line"><a id="l11016" name="l11016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad539217084c83e84eb27ec76eca40152">11016</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) </span></div>
|
||
<div class="line"><a id="l11017" name="l11017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e98a0062ef81bcbc790a8d77720a61c">11017</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk </span></div>
|
||
<div class="line"><a id="l11018" name="l11018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b58fa23a2a04d3a4a46d42fa4673ec5">11018</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPIE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l11019" name="l11019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga028b4854bd356dc30a8b02ab5ed1eb48">11019</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) </span></div>
|
||
<div class="line"><a id="l11020" name="l11020"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0fb33b24d2ebc19e7fe52f0661a3085">11020</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk </span></div>
|
||
<div class="line"><a id="l11021" name="l11021"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6904e60d49c241ecb2347a3da9df8054">11021</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP1TRG_Pos (1U) </span></div>
|
||
<div class="line"><a id="l11022" name="l11022"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81d7cfb15da3ed9689baa85471ff2f02">11022</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) </span></div>
|
||
<div class="line"><a id="l11023" name="l11023"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76f85925873bcd3f795417053bfc5f33">11023</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk </span></div>
|
||
<div class="line"><a id="l11024" name="l11024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae207869690b2ec429b0422006ecae9ee">11024</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP1E_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11025" name="l11025"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad775a4255d5762b8871f79826d48e5cb">11025</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) </span></div>
|
||
<div class="line"><a id="l11026" name="l11026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa68c195cf709d18cd426560302b97852">11026</a></span><span class="preprocessor">#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk </span></div>
|
||
<div class="line"><a id="l11027" name="l11027"></a><span class="lineno">11027</span> </div>
|
||
<div class="line"><a id="l11028" name="l11028"></a><span class="lineno">11028</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l11029" name="l11029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga989cde7332b2ec0b3934cb909514938d">11029</a></span><span class="preprocessor">#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL</span></div>
|
||
<div class="line"><a id="l11030" name="l11030"></a><span class="lineno">11030</span> </div>
|
||
<div class="line"><a id="l11031" name="l11031"></a><span class="lineno">11031</span><span class="comment">/******************** Bits definition for RTC_ALRMASSR register *************/</span></div>
|
||
<div class="line"><a id="l11032" name="l11032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97b73051e1ea4d40a4877f9580c2eb63">11032</a></span><span class="preprocessor">#define RTC_ALRMASSR_MASKSS_Pos (24U) </span></div>
|
||
<div class="line"><a id="l11033" name="l11033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77d71d0606814b6d20253a645bdb5936">11033</a></span><span class="preprocessor">#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) </span></div>
|
||
<div class="line"><a id="l11034" name="l11034"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b0550ccc175ff54e560cc5fb96fbb2c">11034</a></span><span class="preprocessor">#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk </span></div>
|
||
<div class="line"><a id="l11035" name="l11035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeebbc0dfc0a20887ef3582feaa5f1c2b">11035</a></span><span class="preprocessor">#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) </span></div>
|
||
<div class="line"><a id="l11036" name="l11036"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbdb202f388835593843f480c3b3af57">11036</a></span><span class="preprocessor">#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) </span></div>
|
||
<div class="line"><a id="l11037" name="l11037"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95feb5de45a74d7c75c1fc6515c32870">11037</a></span><span class="preprocessor">#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) </span></div>
|
||
<div class="line"><a id="l11038" name="l11038"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae94c65876a1baf0984a6f85aa836b8d0">11038</a></span><span class="preprocessor">#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) </span></div>
|
||
<div class="line"><a id="l11039" name="l11039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5c69419fc862f5012e842942dd755be">11039</a></span><span class="preprocessor">#define RTC_ALRMASSR_SS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11040" name="l11040"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadba25e1519a8aa3222912425ae4c4229">11040</a></span><span class="preprocessor">#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) </span></div>
|
||
<div class="line"><a id="l11041" name="l11041"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a6b683531fded4e2a77d047da7eb203">11041</a></span><span class="preprocessor">#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk </span></div>
|
||
<div class="line"><a id="l11042" name="l11042"></a><span class="lineno">11042</span> </div>
|
||
<div class="line"><a id="l11043" name="l11043"></a><span class="lineno">11043</span><span class="comment">/******************** Bits definition for RTC_ALRMBSSR register *************/</span></div>
|
||
<div class="line"><a id="l11044" name="l11044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bedfef79d265b81f561e7f2c5a6249a">11044</a></span><span class="preprocessor">#define RTC_ALRMBSSR_MASKSS_Pos (24U) </span></div>
|
||
<div class="line"><a id="l11045" name="l11045"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54f65537e9a664f30ca7f3099c6fcc5f">11045</a></span><span class="preprocessor">#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) </span></div>
|
||
<div class="line"><a id="l11046" name="l11046"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf287b0ec7dbf8e9d436cb78da287b244">11046</a></span><span class="preprocessor">#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk </span></div>
|
||
<div class="line"><a id="l11047" name="l11047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4d60185d1ac432b24b0a95e2918902f">11047</a></span><span class="preprocessor">#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) </span></div>
|
||
<div class="line"><a id="l11048" name="l11048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9763a1a382e40cc2ebfa6d84369580df">11048</a></span><span class="preprocessor">#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) </span></div>
|
||
<div class="line"><a id="l11049" name="l11049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga598283f8a8926f0dcb7916a2224f79bc">11049</a></span><span class="preprocessor">#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) </span></div>
|
||
<div class="line"><a id="l11050" name="l11050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf017c71fc7eb34519de3945a028677b">11050</a></span><span class="preprocessor">#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) </span></div>
|
||
<div class="line"><a id="l11051" name="l11051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f2a25c58bddba6df25d75825eff3f76">11051</a></span><span class="preprocessor">#define RTC_ALRMBSSR_SS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11052" name="l11052"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaea93544826ca1a8e920ffd0f46c2bbe">11052</a></span><span class="preprocessor">#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) </span></div>
|
||
<div class="line"><a id="l11053" name="l11053"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33ae74f38392431aa631d397a7e7c305">11053</a></span><span class="preprocessor">#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk </span></div>
|
||
<div class="line"><a id="l11054" name="l11054"></a><span class="lineno">11054</span> </div>
|
||
<div class="line"><a id="l11055" name="l11055"></a><span class="lineno">11055</span><span class="comment">/******************** Bits definition for RTC_BKP0R register ****************/</span></div>
|
||
<div class="line"><a id="l11056" name="l11056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d2a1d81a7e8f12510f865312caea186">11056</a></span><span class="preprocessor">#define RTC_BKP0R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11057" name="l11057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65152adac13a55042ab984b782cf785b">11057</a></span><span class="preprocessor">#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) </span></div>
|
||
<div class="line"><a id="l11058" name="l11058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0d7c3115465079f04cfb97a7faabc59">11058</a></span><span class="preprocessor">#define RTC_BKP0R RTC_BKP0R_Msk </span></div>
|
||
<div class="line"><a id="l11059" name="l11059"></a><span class="lineno">11059</span> </div>
|
||
<div class="line"><a id="l11060" name="l11060"></a><span class="lineno">11060</span><span class="comment">/******************** Bits definition for RTC_BKP1R register ****************/</span></div>
|
||
<div class="line"><a id="l11061" name="l11061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2eff670c07a820b705ec3745683dc75">11061</a></span><span class="preprocessor">#define RTC_BKP1R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11062" name="l11062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1232543b3a22da7aac7131e173182686">11062</a></span><span class="preprocessor">#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) </span></div>
|
||
<div class="line"><a id="l11063" name="l11063"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbc4b6dfeff87332124f271b86eb0c56">11063</a></span><span class="preprocessor">#define RTC_BKP1R RTC_BKP1R_Msk </span></div>
|
||
<div class="line"><a id="l11064" name="l11064"></a><span class="lineno">11064</span> </div>
|
||
<div class="line"><a id="l11065" name="l11065"></a><span class="lineno">11065</span><span class="comment">/******************** Bits definition for RTC_BKP2R register ****************/</span></div>
|
||
<div class="line"><a id="l11066" name="l11066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61b179787d35514914d2e103e3cc5388">11066</a></span><span class="preprocessor">#define RTC_BKP2R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11067" name="l11067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe778fc6aa04076af499bfe4eef8f5e1">11067</a></span><span class="preprocessor">#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) </span></div>
|
||
<div class="line"><a id="l11068" name="l11068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34fda9ee6115f0de9588e22c46602d89">11068</a></span><span class="preprocessor">#define RTC_BKP2R RTC_BKP2R_Msk </span></div>
|
||
<div class="line"><a id="l11069" name="l11069"></a><span class="lineno">11069</span> </div>
|
||
<div class="line"><a id="l11070" name="l11070"></a><span class="lineno">11070</span><span class="comment">/******************** Bits definition for RTC_BKP3R register ****************/</span></div>
|
||
<div class="line"><a id="l11071" name="l11071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad53baa189d917e48c2c274655adc9483">11071</a></span><span class="preprocessor">#define RTC_BKP3R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11072" name="l11072"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e99106bc39a8e81bf48352827d0ddaf">11072</a></span><span class="preprocessor">#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) </span></div>
|
||
<div class="line"><a id="l11073" name="l11073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90403ff99c08f0abc379447823e5e841">11073</a></span><span class="preprocessor">#define RTC_BKP3R RTC_BKP3R_Msk </span></div>
|
||
<div class="line"><a id="l11074" name="l11074"></a><span class="lineno">11074</span> </div>
|
||
<div class="line"><a id="l11075" name="l11075"></a><span class="lineno">11075</span><span class="comment">/******************** Bits definition for RTC_BKP4R register ****************/</span></div>
|
||
<div class="line"><a id="l11076" name="l11076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad62cbb0c17b02ce23ca2bdd29b0ed349">11076</a></span><span class="preprocessor">#define RTC_BKP4R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11077" name="l11077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64613b1fe898ececd40ffe481df742ab">11077</a></span><span class="preprocessor">#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) </span></div>
|
||
<div class="line"><a id="l11078" name="l11078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeed1b338e9526d817a1fd01304b8851c">11078</a></span><span class="preprocessor">#define RTC_BKP4R RTC_BKP4R_Msk </span></div>
|
||
<div class="line"><a id="l11079" name="l11079"></a><span class="lineno">11079</span> </div>
|
||
<div class="line"><a id="l11080" name="l11080"></a><span class="lineno">11080</span><span class="comment">/******************** Bits definition for RTC_BKP5R register ****************/</span></div>
|
||
<div class="line"><a id="l11081" name="l11081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga025745144302ad1dd444f09687634674">11081</a></span><span class="preprocessor">#define RTC_BKP5R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11082" name="l11082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2335682b85414d8d53d4fffdfc3bf190">11082</a></span><span class="preprocessor">#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) </span></div>
|
||
<div class="line"><a id="l11083" name="l11083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e8954ab0ead8bb788d5d8eebf2f5c4c">11083</a></span><span class="preprocessor">#define RTC_BKP5R RTC_BKP5R_Msk </span></div>
|
||
<div class="line"><a id="l11084" name="l11084"></a><span class="lineno">11084</span> </div>
|
||
<div class="line"><a id="l11085" name="l11085"></a><span class="lineno">11085</span><span class="comment">/******************** Bits definition for RTC_BKP6R register ****************/</span></div>
|
||
<div class="line"><a id="l11086" name="l11086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2e7347300206d08a294ba300b9dcdfd">11086</a></span><span class="preprocessor">#define RTC_BKP6R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11087" name="l11087"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cca326be267e10381f4d4f9d5951c32">11087</a></span><span class="preprocessor">#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) </span></div>
|
||
<div class="line"><a id="l11088" name="l11088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b9ee9eb5d024ccd5809fcc20fd51f5b">11088</a></span><span class="preprocessor">#define RTC_BKP6R RTC_BKP6R_Msk </span></div>
|
||
<div class="line"><a id="l11089" name="l11089"></a><span class="lineno">11089</span> </div>
|
||
<div class="line"><a id="l11090" name="l11090"></a><span class="lineno">11090</span><span class="comment">/******************** Bits definition for RTC_BKP7R register ****************/</span></div>
|
||
<div class="line"><a id="l11091" name="l11091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab37f3f4b5f12182f8fd48431c5b5d9fb">11091</a></span><span class="preprocessor">#define RTC_BKP7R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11092" name="l11092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3ad5bf67535cba7d3de78d72ae79d79">11092</a></span><span class="preprocessor">#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) </span></div>
|
||
<div class="line"><a id="l11093" name="l11093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0f1ae07f7b1815bf58b464dc7366731">11093</a></span><span class="preprocessor">#define RTC_BKP7R RTC_BKP7R_Msk </span></div>
|
||
<div class="line"><a id="l11094" name="l11094"></a><span class="lineno">11094</span> </div>
|
||
<div class="line"><a id="l11095" name="l11095"></a><span class="lineno">11095</span><span class="comment">/******************** Bits definition for RTC_BKP8R register ****************/</span></div>
|
||
<div class="line"><a id="l11096" name="l11096"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a01cc89fbe70d722025ba445143da77">11096</a></span><span class="preprocessor">#define RTC_BKP8R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11097" name="l11097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61ae366e9c0ad90225479d0d6d4e1544">11097</a></span><span class="preprocessor">#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) </span></div>
|
||
<div class="line"><a id="l11098" name="l11098"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bd10acb9e5ce5225af4ff895bd3bb82">11098</a></span><span class="preprocessor">#define RTC_BKP8R RTC_BKP8R_Msk </span></div>
|
||
<div class="line"><a id="l11099" name="l11099"></a><span class="lineno">11099</span> </div>
|
||
<div class="line"><a id="l11100" name="l11100"></a><span class="lineno">11100</span><span class="comment">/******************** Bits definition for RTC_BKP9R register ****************/</span></div>
|
||
<div class="line"><a id="l11101" name="l11101"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf98c5146f622b5e7a9aef16b75f0a76f">11101</a></span><span class="preprocessor">#define RTC_BKP9R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11102" name="l11102"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf039d5e2bf31dc293bd3b84a186bd8c8">11102</a></span><span class="preprocessor">#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) </span></div>
|
||
<div class="line"><a id="l11103" name="l11103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9aa3d0d90de22a1dbf3b6de2b7ed4c9e">11103</a></span><span class="preprocessor">#define RTC_BKP9R RTC_BKP9R_Msk </span></div>
|
||
<div class="line"><a id="l11104" name="l11104"></a><span class="lineno">11104</span> </div>
|
||
<div class="line"><a id="l11105" name="l11105"></a><span class="lineno">11105</span><span class="comment">/******************** Bits definition for RTC_BKP10R register ***************/</span></div>
|
||
<div class="line"><a id="l11106" name="l11106"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68a6b8b6fd6e38bcbb396de36791b97d">11106</a></span><span class="preprocessor">#define RTC_BKP10R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11107" name="l11107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga425836775a344f3d199760028c01b22f">11107</a></span><span class="preprocessor">#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) </span></div>
|
||
<div class="line"><a id="l11108" name="l11108"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2179063a3078a211c3b697ce012ab5a0">11108</a></span><span class="preprocessor">#define RTC_BKP10R RTC_BKP10R_Msk </span></div>
|
||
<div class="line"><a id="l11109" name="l11109"></a><span class="lineno">11109</span> </div>
|
||
<div class="line"><a id="l11110" name="l11110"></a><span class="lineno">11110</span><span class="comment">/******************** Bits definition for RTC_BKP11R register ***************/</span></div>
|
||
<div class="line"><a id="l11111" name="l11111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71f7a489ec11b5547afa3470d76ea62a">11111</a></span><span class="preprocessor">#define RTC_BKP11R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11112" name="l11112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga803ec730ae4020d5b80df83b21990b31">11112</a></span><span class="preprocessor">#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) </span></div>
|
||
<div class="line"><a id="l11113" name="l11113"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab250f9423dee41b165aa8f02d2fc1fe7">11113</a></span><span class="preprocessor">#define RTC_BKP11R RTC_BKP11R_Msk </span></div>
|
||
<div class="line"><a id="l11114" name="l11114"></a><span class="lineno">11114</span> </div>
|
||
<div class="line"><a id="l11115" name="l11115"></a><span class="lineno">11115</span><span class="comment">/******************** Bits definition for RTC_BKP12R register ***************/</span></div>
|
||
<div class="line"><a id="l11116" name="l11116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e64139e8db6dcca0efbb9e3a4e6a524">11116</a></span><span class="preprocessor">#define RTC_BKP12R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11117" name="l11117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaed050277146eb1c2fa2a8e8eb778888">11117</a></span><span class="preprocessor">#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) </span></div>
|
||
<div class="line"><a id="l11118" name="l11118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefe1b6108ac49197b28c9bee31bbaf3b">11118</a></span><span class="preprocessor">#define RTC_BKP12R RTC_BKP12R_Msk </span></div>
|
||
<div class="line"><a id="l11119" name="l11119"></a><span class="lineno">11119</span> </div>
|
||
<div class="line"><a id="l11120" name="l11120"></a><span class="lineno">11120</span><span class="comment">/******************** Bits definition for RTC_BKP13R register ***************/</span></div>
|
||
<div class="line"><a id="l11121" name="l11121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga704dac9c54b7afd7e51c026ef0093eed">11121</a></span><span class="preprocessor">#define RTC_BKP13R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11122" name="l11122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f1c04da88aaae10d0bcf45816608b8e">11122</a></span><span class="preprocessor">#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) </span></div>
|
||
<div class="line"><a id="l11123" name="l11123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e77435e16bdebf3491eb0e30bd10b0d">11123</a></span><span class="preprocessor">#define RTC_BKP13R RTC_BKP13R_Msk </span></div>
|
||
<div class="line"><a id="l11124" name="l11124"></a><span class="lineno">11124</span> </div>
|
||
<div class="line"><a id="l11125" name="l11125"></a><span class="lineno">11125</span><span class="comment">/******************** Bits definition for RTC_BKP14R register ***************/</span></div>
|
||
<div class="line"><a id="l11126" name="l11126"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35ea3d3c00bb891b7702428ab6b13526">11126</a></span><span class="preprocessor">#define RTC_BKP14R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11127" name="l11127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaceeefc705b2bd138b6ec84bd606dbe86">11127</a></span><span class="preprocessor">#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) </span></div>
|
||
<div class="line"><a id="l11128" name="l11128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f07ee6d227deaa11e0ae035121185b0">11128</a></span><span class="preprocessor">#define RTC_BKP14R RTC_BKP14R_Msk </span></div>
|
||
<div class="line"><a id="l11129" name="l11129"></a><span class="lineno">11129</span> </div>
|
||
<div class="line"><a id="l11130" name="l11130"></a><span class="lineno">11130</span><span class="comment">/******************** Bits definition for RTC_BKP15R register ***************/</span></div>
|
||
<div class="line"><a id="l11131" name="l11131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab300e7778a3b5f5e69b9e3c6a2f00244">11131</a></span><span class="preprocessor">#define RTC_BKP15R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11132" name="l11132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae55844e319f165ba23ba0b2d5a9ff2ee">11132</a></span><span class="preprocessor">#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) </span></div>
|
||
<div class="line"><a id="l11133" name="l11133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae543b0dd58f03c2f70bb6b3b65232863">11133</a></span><span class="preprocessor">#define RTC_BKP15R RTC_BKP15R_Msk </span></div>
|
||
<div class="line"><a id="l11134" name="l11134"></a><span class="lineno">11134</span> </div>
|
||
<div class="line"><a id="l11135" name="l11135"></a><span class="lineno">11135</span><span class="comment">/******************** Bits definition for RTC_BKP16R register ***************/</span></div>
|
||
<div class="line"><a id="l11136" name="l11136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8a577b0955f75ea83804f5d16b7361a">11136</a></span><span class="preprocessor">#define RTC_BKP16R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11137" name="l11137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad53cd82e4d08160a2169cf0d6122ba7a">11137</a></span><span class="preprocessor">#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) </span></div>
|
||
<div class="line"><a id="l11138" name="l11138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0add0c768094f0de71bb4e50fbcce6e">11138</a></span><span class="preprocessor">#define RTC_BKP16R RTC_BKP16R_Msk </span></div>
|
||
<div class="line"><a id="l11139" name="l11139"></a><span class="lineno">11139</span> </div>
|
||
<div class="line"><a id="l11140" name="l11140"></a><span class="lineno">11140</span><span class="comment">/******************** Bits definition for RTC_BKP17R register ***************/</span></div>
|
||
<div class="line"><a id="l11141" name="l11141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6036f283574a87f4d27610040c53eb1e">11141</a></span><span class="preprocessor">#define RTC_BKP17R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11142" name="l11142"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb00d71ec7bae68636740347f971bb05">11142</a></span><span class="preprocessor">#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) </span></div>
|
||
<div class="line"><a id="l11143" name="l11143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga059aaedb55963f39e8724d50d55d5282">11143</a></span><span class="preprocessor">#define RTC_BKP17R RTC_BKP17R_Msk </span></div>
|
||
<div class="line"><a id="l11144" name="l11144"></a><span class="lineno">11144</span> </div>
|
||
<div class="line"><a id="l11145" name="l11145"></a><span class="lineno">11145</span><span class="comment">/******************** Bits definition for RTC_BKP18R register ***************/</span></div>
|
||
<div class="line"><a id="l11146" name="l11146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad55ca335d5c133a1b773affcb87e421c">11146</a></span><span class="preprocessor">#define RTC_BKP18R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11147" name="l11147"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad06553479e94b2bbd23fde19bbcf0667">11147</a></span><span class="preprocessor">#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) </span></div>
|
||
<div class="line"><a id="l11148" name="l11148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66154eb091275e87a4bd53e87ef9214e">11148</a></span><span class="preprocessor">#define RTC_BKP18R RTC_BKP18R_Msk </span></div>
|
||
<div class="line"><a id="l11149" name="l11149"></a><span class="lineno">11149</span> </div>
|
||
<div class="line"><a id="l11150" name="l11150"></a><span class="lineno">11150</span><span class="comment">/******************** Bits definition for RTC_BKP19R register ***************/</span></div>
|
||
<div class="line"><a id="l11151" name="l11151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5eee6977105e1d1972deedeeb87efe2c">11151</a></span><span class="preprocessor">#define RTC_BKP19R_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11152" name="l11152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9dd25b421b61fc893df921c7ea4d58f1">11152</a></span><span class="preprocessor">#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) </span></div>
|
||
<div class="line"><a id="l11153" name="l11153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa4c31e33d851fde2715059ea28dac6f">11153</a></span><span class="preprocessor">#define RTC_BKP19R RTC_BKP19R_Msk </span></div>
|
||
<div class="line"><a id="l11154" name="l11154"></a><span class="lineno">11154</span> </div>
|
||
<div class="line"><a id="l11155" name="l11155"></a><span class="lineno">11155</span><span class="comment">/******************** Number of backup registers ******************************/</span></div>
|
||
<div class="line"><a id="l11156" name="l11156"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70de60adf3ddd7d029bb2c6ae26d9584">11156</a></span><span class="preprocessor">#define RTC_BKP_NUMBER 0x000000014U</span></div>
|
||
<div class="line"><a id="l11157" name="l11157"></a><span class="lineno">11157</span> </div>
|
||
<div class="line"><a id="l11158" name="l11158"></a><span class="lineno">11158</span> </div>
|
||
<div class="line"><a id="l11159" name="l11159"></a><span class="lineno">11159</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l11160" name="l11160"></a><span class="lineno">11160</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l11161" name="l11161"></a><span class="lineno">11161</span><span class="comment">/* SD host Interface */</span></div>
|
||
<div class="line"><a id="l11162" name="l11162"></a><span class="lineno">11162</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l11163" name="l11163"></a><span class="lineno">11163</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l11164" name="l11164"></a><span class="lineno">11164</span><span class="comment">/****************** Bit definition for SDIO_POWER register ******************/</span></div>
|
||
<div class="line"><a id="l11165" name="l11165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga980203971a9f5f4c5e02733c6106249f">11165</a></span><span class="preprocessor">#define SDIO_POWER_PWRCTRL_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11166" name="l11166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85685239a200e250d95c38f310fb9609">11166</a></span><span class="preprocessor">#define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos) </span></div>
|
||
<div class="line"><a id="l11167" name="l11167"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf125c56eeb40163b617c9fb6329da67f">11167</a></span><span class="preprocessor">#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk </span></div>
|
||
<div class="line"><a id="l11168" name="l11168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa82b7689b02f54318d3f629d70b85098">11168</a></span><span class="preprocessor">#define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos) </span></div>
|
||
<div class="line"><a id="l11169" name="l11169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd149efb1d6062f37165ac01268a875e">11169</a></span><span class="preprocessor">#define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos) </span></div>
|
||
<div class="line"><a id="l11171" name="l11171"></a><span class="lineno">11171</span><span class="comment">/****************** Bit definition for SDIO_CLKCR register ******************/</span></div>
|
||
<div class="line"><a id="l11172" name="l11172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b024ad152edaf86ad825ab3fe7450dd">11172</a></span><span class="preprocessor">#define SDIO_CLKCR_CLKDIV_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11173" name="l11173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9207dc12eed614d38a8faa4397a6c27">11173</a></span><span class="preprocessor">#define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos) </span></div>
|
||
<div class="line"><a id="l11174" name="l11174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga316271d0147b22c6267fc563d4c24424">11174</a></span><span class="preprocessor">#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk </span></div>
|
||
<div class="line"><a id="l11175" name="l11175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44234ca6af02a8e44da30f14f77acf09">11175</a></span><span class="preprocessor">#define SDIO_CLKCR_CLKEN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11176" name="l11176"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0952e49876e16cf5b7a15c2523b210d7">11176</a></span><span class="preprocessor">#define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos) </span></div>
|
||
<div class="line"><a id="l11177" name="l11177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf27847573683f91dbfe387a2571b514f">11177</a></span><span class="preprocessor">#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk </span></div>
|
||
<div class="line"><a id="l11178" name="l11178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72c1fdc5e585d2846743b06743c76639">11178</a></span><span class="preprocessor">#define SDIO_CLKCR_PWRSAV_Pos (9U) </span></div>
|
||
<div class="line"><a id="l11179" name="l11179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga258035422cd74f19e644272dc0eb2fa8">11179</a></span><span class="preprocessor">#define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos) </span></div>
|
||
<div class="line"><a id="l11180" name="l11180"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbb618f32aef2970fd8b8b285f7b4118">11180</a></span><span class="preprocessor">#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk </span></div>
|
||
<div class="line"><a id="l11181" name="l11181"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d2200f69dd69acf657ed6f3711d5dad">11181</a></span><span class="preprocessor">#define SDIO_CLKCR_BYPASS_Pos (10U) </span></div>
|
||
<div class="line"><a id="l11182" name="l11182"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga590aa2168f77032139685f5880229c2d">11182</a></span><span class="preprocessor">#define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos) </span></div>
|
||
<div class="line"><a id="l11183" name="l11183"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f362c1d228156c50639d79b9be99c9b">11183</a></span><span class="preprocessor">#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk </span></div>
|
||
<div class="line"><a id="l11185" name="l11185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d70e8c1461dadda0df1d84176764b6d">11185</a></span><span class="preprocessor">#define SDIO_CLKCR_WIDBUS_Pos (11U) </span></div>
|
||
<div class="line"><a id="l11186" name="l11186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d6f1ccab2c96629906dcf01ed68439f">11186</a></span><span class="preprocessor">#define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos) </span></div>
|
||
<div class="line"><a id="l11187" name="l11187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9d57d7917c39bdc5309506e8c28b7d7">11187</a></span><span class="preprocessor">#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk </span></div>
|
||
<div class="line"><a id="l11188" name="l11188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab532dbf366c3fb731488017b0a794151">11188</a></span><span class="preprocessor">#define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos) </span></div>
|
||
<div class="line"><a id="l11189" name="l11189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49f3e7998bca487f5354ef6f8dffbb21">11189</a></span><span class="preprocessor">#define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos) </span></div>
|
||
<div class="line"><a id="l11191" name="l11191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3e9d0be4756855a1e5e9753a6605077">11191</a></span><span class="preprocessor">#define SDIO_CLKCR_NEGEDGE_Pos (13U) </span></div>
|
||
<div class="line"><a id="l11192" name="l11192"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a4df6f204feaf9a52a36b6bbf8987ef">11192</a></span><span class="preprocessor">#define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos) </span></div>
|
||
<div class="line"><a id="l11193" name="l11193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad124bd76f6543497c90372e182ec48a2">11193</a></span><span class="preprocessor">#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk </span></div>
|
||
<div class="line"><a id="l11194" name="l11194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1318e107062a376681c0d8cdc18332f3">11194</a></span><span class="preprocessor">#define SDIO_CLKCR_HWFC_EN_Pos (14U) </span></div>
|
||
<div class="line"><a id="l11195" name="l11195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae43747a95ebebe7388114ed6990b976">11195</a></span><span class="preprocessor">#define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos) </span></div>
|
||
<div class="line"><a id="l11196" name="l11196"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga693d7b533dd5a5a668bc13b4365b18dc">11196</a></span><span class="preprocessor">#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk </span></div>
|
||
<div class="line"><a id="l11198" name="l11198"></a><span class="lineno">11198</span><span class="comment">/******************* Bit definition for SDIO_ARG register *******************/</span></div>
|
||
<div class="line"><a id="l11199" name="l11199"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd212d9a3891e8c282f50e82c207cce7">11199</a></span><span class="preprocessor">#define SDIO_ARG_CMDARG_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11200" name="l11200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c0c162d6eb9a15399e1fdc00a8a711f">11200</a></span><span class="preprocessor">#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos) </span></div>
|
||
<div class="line"><a id="l11201" name="l11201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d917a4fdc7442e270c2c727df78b819">11201</a></span><span class="preprocessor">#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk </span></div>
|
||
<div class="line"><a id="l11203" name="l11203"></a><span class="lineno">11203</span><span class="comment">/******************* Bit definition for SDIO_CMD register *******************/</span></div>
|
||
<div class="line"><a id="l11204" name="l11204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63a301afc3b24e6825aca5911f2292f7">11204</a></span><span class="preprocessor">#define SDIO_CMD_CMDINDEX_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11205" name="l11205"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5864df752017e82b545ecbef7a434000">11205</a></span><span class="preprocessor">#define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos) </span></div>
|
||
<div class="line"><a id="l11206" name="l11206"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf91b593b5681a68db5ff9fd11600c9c8">11206</a></span><span class="preprocessor">#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk </span></div>
|
||
<div class="line"><a id="l11208" name="l11208"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada8d884fac89d07c59f335635ba5cc6a">11208</a></span><span class="preprocessor">#define SDIO_CMD_WAITRESP_Pos (6U) </span></div>
|
||
<div class="line"><a id="l11209" name="l11209"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41c83bc85012033738be4722741c644e">11209</a></span><span class="preprocessor">#define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos) </span></div>
|
||
<div class="line"><a id="l11210" name="l11210"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d617f0e08d697c3b263e6a79f417d0f">11210</a></span><span class="preprocessor">#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk </span></div>
|
||
<div class="line"><a id="l11211" name="l11211"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5797a389fecf611dccd483658b822fa">11211</a></span><span class="preprocessor">#define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos) </span></div>
|
||
<div class="line"><a id="l11212" name="l11212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f5457b48feda0056466e5c380c44373">11212</a></span><span class="preprocessor">#define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos) </span></div>
|
||
<div class="line"><a id="l11214" name="l11214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6a63d6e5b6dbabf23b6c8da0a3582c9">11214</a></span><span class="preprocessor">#define SDIO_CMD_WAITINT_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11215" name="l11215"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga214e7747364d52fe038e33df70453c7b">11215</a></span><span class="preprocessor">#define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos) </span></div>
|
||
<div class="line"><a id="l11216" name="l11216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b037f34e297f38d56b14d46d008ef58">11216</a></span><span class="preprocessor">#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk </span></div>
|
||
<div class="line"><a id="l11217" name="l11217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a1219464c590ed80ea38fcf28c8335a">11217</a></span><span class="preprocessor">#define SDIO_CMD_WAITPEND_Pos (9U) </span></div>
|
||
<div class="line"><a id="l11218" name="l11218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae565c2ebe48768e1e6a8638c5f8df583">11218</a></span><span class="preprocessor">#define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos) </span></div>
|
||
<div class="line"><a id="l11219" name="l11219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4118c9200bae6732764f6c87a0962a9">11219</a></span><span class="preprocessor">#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk </span></div>
|
||
<div class="line"><a id="l11220" name="l11220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bcdcc89ef5863164462de6750a74caf">11220</a></span><span class="preprocessor">#define SDIO_CMD_CPSMEN_Pos (10U) </span></div>
|
||
<div class="line"><a id="l11221" name="l11221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f7c4c45069c802f2118cc0135d12dfe">11221</a></span><span class="preprocessor">#define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos) </span></div>
|
||
<div class="line"><a id="l11222" name="l11222"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga982f3fd09ce7e31709e0628b1fae86b8">11222</a></span><span class="preprocessor">#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk </span></div>
|
||
<div class="line"><a id="l11223" name="l11223"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69aeafb35e44b4b432e71cd4cc29e15b">11223</a></span><span class="preprocessor">#define SDIO_CMD_SDIOSUSPEND_Pos (11U) </span></div>
|
||
<div class="line"><a id="l11224" name="l11224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeecad1b553de683cb5cf9010d84b70d6">11224</a></span><span class="preprocessor">#define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos) </span></div>
|
||
<div class="line"><a id="l11225" name="l11225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad560080c3e7ab5aeafe151dafcc64368">11225</a></span><span class="preprocessor">#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk </span></div>
|
||
<div class="line"><a id="l11226" name="l11226"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2bceb6b0e29e84ad08434948b17059c">11226</a></span><span class="preprocessor">#define SDIO_CMD_ENCMDCOMPL_Pos (12U) </span></div>
|
||
<div class="line"><a id="l11227" name="l11227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcf48c2b726056d5e994836644481617">11227</a></span><span class="preprocessor">#define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos) </span></div>
|
||
<div class="line"><a id="l11228" name="l11228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga905b78ecf464857e6501ef5fd5e6ef1b">11228</a></span><span class="preprocessor">#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk </span></div>
|
||
<div class="line"><a id="l11229" name="l11229"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdc4381d56669dc173b95c161cf92954">11229</a></span><span class="preprocessor">#define SDIO_CMD_NIEN_Pos (13U) </span></div>
|
||
<div class="line"><a id="l11230" name="l11230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa07629f3e99beeb0e3d2ec96a6584f5a">11230</a></span><span class="preprocessor">#define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos) </span></div>
|
||
<div class="line"><a id="l11231" name="l11231"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a9d5b2366ec7ca38db9d6d9f0f63f81">11231</a></span><span class="preprocessor">#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk </span></div>
|
||
<div class="line"><a id="l11232" name="l11232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e4c944917a79c48b8393a4ca0208580">11232</a></span><span class="preprocessor">#define SDIO_CMD_CEATACMD_Pos (14U) </span></div>
|
||
<div class="line"><a id="l11233" name="l11233"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68429f74d1213129ab97de545b433d83">11233</a></span><span class="preprocessor">#define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos) </span></div>
|
||
<div class="line"><a id="l11234" name="l11234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87422225274de986e7abe6b2a91a79c5">11234</a></span><span class="preprocessor">#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk </span></div>
|
||
<div class="line"><a id="l11236" name="l11236"></a><span class="lineno">11236</span><span class="comment">/***************** Bit definition for SDIO_RESPCMD register *****************/</span></div>
|
||
<div class="line"><a id="l11237" name="l11237"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53f5c709c72c524a03ed26cc6a246f1a">11237</a></span><span class="preprocessor">#define SDIO_RESPCMD_RESPCMD_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11238" name="l11238"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f937e878d203e9f9dda3e12cec73153">11238</a></span><span class="preprocessor">#define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) </span></div>
|
||
<div class="line"><a id="l11239" name="l11239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27f9a6cbfd364bbb050b526ebc01d2d7">11239</a></span><span class="preprocessor">#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk </span></div>
|
||
<div class="line"><a id="l11241" name="l11241"></a><span class="lineno">11241</span><span class="comment">/****************** Bit definition for SDIO_RESP0 register ******************/</span></div>
|
||
<div class="line"><a id="l11242" name="l11242"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0050e8b5acaf5716002877e15744cea1">11242</a></span><span class="preprocessor">#define SDIO_RESP0_CARDSTATUS0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11243" name="l11243"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f6aa725abdb56f38c3c8783b9f15e47">11243</a></span><span class="preprocessor">#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) </span></div>
|
||
<div class="line"><a id="l11244" name="l11244"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56a55231f7a91cfd2cefaca0f6135cbc">11244</a></span><span class="preprocessor">#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk </span></div>
|
||
<div class="line"><a id="l11246" name="l11246"></a><span class="lineno">11246</span><span class="comment">/****************** Bit definition for SDIO_RESP1 register ******************/</span></div>
|
||
<div class="line"><a id="l11247" name="l11247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdf3d65acd80e89c5b3a85759cbf11ae">11247</a></span><span class="preprocessor">#define SDIO_RESP1_CARDSTATUS1_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11248" name="l11248"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccbe896832554a212ce0eb8d7650b850">11248</a></span><span class="preprocessor">#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) </span></div>
|
||
<div class="line"><a id="l11249" name="l11249"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d20abddfc99835a2954eda5899f6db1">11249</a></span><span class="preprocessor">#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk </span></div>
|
||
<div class="line"><a id="l11251" name="l11251"></a><span class="lineno">11251</span><span class="comment">/****************** Bit definition for SDIO_RESP2 register ******************/</span></div>
|
||
<div class="line"><a id="l11252" name="l11252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4fe5348e4b89d1b8307a399d2696684">11252</a></span><span class="preprocessor">#define SDIO_RESP2_CARDSTATUS2_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11253" name="l11253"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb0ef49057b923f3518c6f055a79b605">11253</a></span><span class="preprocessor">#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) </span></div>
|
||
<div class="line"><a id="l11254" name="l11254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31a482ff36bde1df56ab603c864c4066">11254</a></span><span class="preprocessor">#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk </span></div>
|
||
<div class="line"><a id="l11256" name="l11256"></a><span class="lineno">11256</span><span class="comment">/****************** Bit definition for SDIO_RESP3 register ******************/</span></div>
|
||
<div class="line"><a id="l11257" name="l11257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cc1aa3203ce39c556e1631c05d911ea">11257</a></span><span class="preprocessor">#define SDIO_RESP3_CARDSTATUS3_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11258" name="l11258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab48a641918cdc42f1f8da11703329a04">11258</a></span><span class="preprocessor">#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) </span></div>
|
||
<div class="line"><a id="l11259" name="l11259"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1075c96b5818b0500d5cce231ace89cf">11259</a></span><span class="preprocessor">#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk </span></div>
|
||
<div class="line"><a id="l11261" name="l11261"></a><span class="lineno">11261</span><span class="comment">/****************** Bit definition for SDIO_RESP4 register ******************/</span></div>
|
||
<div class="line"><a id="l11262" name="l11262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5fc053049c54b41a638649c8990c5b1">11262</a></span><span class="preprocessor">#define SDIO_RESP4_CARDSTATUS4_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11263" name="l11263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38cdffc0bf0950e987e8380d8f89f4c0">11263</a></span><span class="preprocessor">#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) </span></div>
|
||
<div class="line"><a id="l11264" name="l11264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga407ab1e46a80426602ab36e86457da26">11264</a></span><span class="preprocessor">#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk </span></div>
|
||
<div class="line"><a id="l11266" name="l11266"></a><span class="lineno">11266</span><span class="comment">/****************** Bit definition for SDIO_DTIMER register *****************/</span></div>
|
||
<div class="line"><a id="l11267" name="l11267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fe60be41b16f6fb05af07517115eda1">11267</a></span><span class="preprocessor">#define SDIO_DTIMER_DATATIME_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11268" name="l11268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ca7786fe8c3ebf5bf4b107ad2693b77">11268</a></span><span class="preprocessor">#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) </span></div>
|
||
<div class="line"><a id="l11269" name="l11269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27e45eea9ce17b7251f10ea763180690">11269</a></span><span class="preprocessor">#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk </span></div>
|
||
<div class="line"><a id="l11271" name="l11271"></a><span class="lineno">11271</span><span class="comment">/****************** Bit definition for SDIO_DLEN register *******************/</span></div>
|
||
<div class="line"><a id="l11272" name="l11272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb3ed134b1944407d86a64baff57bfbc">11272</a></span><span class="preprocessor">#define SDIO_DLEN_DATALENGTH_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11273" name="l11273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c419dbe5ccdf09fe276a876c5b644cf">11273</a></span><span class="preprocessor">#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) </span></div>
|
||
<div class="line"><a id="l11274" name="l11274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d3b07bca9aec8ef5456ba9b73f13adb">11274</a></span><span class="preprocessor">#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk </span></div>
|
||
<div class="line"><a id="l11276" name="l11276"></a><span class="lineno">11276</span><span class="comment">/****************** Bit definition for SDIO_DCTRL register ******************/</span></div>
|
||
<div class="line"><a id="l11277" name="l11277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5833159c058fcd329336b2259f33d20">11277</a></span><span class="preprocessor">#define SDIO_DCTRL_DTEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11278" name="l11278"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01116e33cb68129902284211af9f0e2e">11278</a></span><span class="preprocessor">#define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos) </span></div>
|
||
<div class="line"><a id="l11279" name="l11279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa03ff8fb9ff70e0a623a5c1f7aa2bc9a">11279</a></span><span class="preprocessor">#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk </span></div>
|
||
<div class="line"><a id="l11280" name="l11280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga306751502891360398d0046e484e418b">11280</a></span><span class="preprocessor">#define SDIO_DCTRL_DTDIR_Pos (1U) </span></div>
|
||
<div class="line"><a id="l11281" name="l11281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f8fcebfcdcd58383a72b8503f74597f">11281</a></span><span class="preprocessor">#define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos) </span></div>
|
||
<div class="line"><a id="l11282" name="l11282"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga801fe27f7175a308d56776db19776c93">11282</a></span><span class="preprocessor">#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk </span></div>
|
||
<div class="line"><a id="l11283" name="l11283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6f10964c5da8676885eda5000d33c1a">11283</a></span><span class="preprocessor">#define SDIO_DCTRL_DTMODE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l11284" name="l11284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78a712204e817e6ce1a96ffa421107fb">11284</a></span><span class="preprocessor">#define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos) </span></div>
|
||
<div class="line"><a id="l11285" name="l11285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa90cd50ae364b992ca8ccab319eb5513">11285</a></span><span class="preprocessor">#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk </span></div>
|
||
<div class="line"><a id="l11286" name="l11286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69e2071d77bd39d1d206ad785ea4b1f7">11286</a></span><span class="preprocessor">#define SDIO_DCTRL_DMAEN_Pos (3U) </span></div>
|
||
<div class="line"><a id="l11287" name="l11287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga947764dd929d0a703312d684ea22f214">11287</a></span><span class="preprocessor">#define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos) </span></div>
|
||
<div class="line"><a id="l11288" name="l11288"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03a2148910ae02dde7e4cd63e0f5e008">11288</a></span><span class="preprocessor">#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk </span></div>
|
||
<div class="line"><a id="l11290" name="l11290"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga119e44ccdca8f6bad3f3ad773bdd37c4">11290</a></span><span class="preprocessor">#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) </span></div>
|
||
<div class="line"><a id="l11291" name="l11291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed2493217bf1583aa33c8f1d755904a6">11291</a></span><span class="preprocessor">#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l11292" name="l11292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga948072d8a6db53d0c377944523a4b15a">11292</a></span><span class="preprocessor">#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk </span></div>
|
||
<div class="line"><a id="l11293" name="l11293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51e2cb99cf325bb32c8910204b1507db">11293</a></span><span class="preprocessor">#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l11294" name="l11294"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0add3ad2b72a21e7f8d48da3ea0b3d0f">11294</a></span><span class="preprocessor">#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l11295" name="l11295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93825036eceb86872e2ca179c63163ec">11295</a></span><span class="preprocessor">#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l11296" name="l11296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2025aa63b595bfccc747b99caec8799">11296</a></span><span class="preprocessor">#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos) </span></div>
|
||
<div class="line"><a id="l11298" name="l11298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2799704f4cb1d6a7165360302ad5487e">11298</a></span><span class="preprocessor">#define SDIO_DCTRL_RWSTART_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11299" name="l11299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7c075ad5172d81d8a0ebbba7bd368a1">11299</a></span><span class="preprocessor">#define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos) </span></div>
|
||
<div class="line"><a id="l11300" name="l11300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe9600da3e751118d49ea14ce44e91b9">11300</a></span><span class="preprocessor">#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk </span></div>
|
||
<div class="line"><a id="l11301" name="l11301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22dbec68a4c108406a71258aa0b42cba">11301</a></span><span class="preprocessor">#define SDIO_DCTRL_RWSTOP_Pos (9U) </span></div>
|
||
<div class="line"><a id="l11302" name="l11302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b25f8c2f40d6767bd6b61edb4891e7b">11302</a></span><span class="preprocessor">#define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos) </span></div>
|
||
<div class="line"><a id="l11303" name="l11303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f1b5b6a32ce712fbb3767090b1b045e">11303</a></span><span class="preprocessor">#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk </span></div>
|
||
<div class="line"><a id="l11304" name="l11304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0745b75ed0809ab27ddee511b7821595">11304</a></span><span class="preprocessor">#define SDIO_DCTRL_RWMOD_Pos (10U) </span></div>
|
||
<div class="line"><a id="l11305" name="l11305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5cbe9685d3f55431f7492463b902655b">11305</a></span><span class="preprocessor">#define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos) </span></div>
|
||
<div class="line"><a id="l11306" name="l11306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bf721a25f656b3de6fa0b0fe32edb6a">11306</a></span><span class="preprocessor">#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk </span></div>
|
||
<div class="line"><a id="l11307" name="l11307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga998b276365f499e3af5dc3e784c728bf">11307</a></span><span class="preprocessor">#define SDIO_DCTRL_SDIOEN_Pos (11U) </span></div>
|
||
<div class="line"><a id="l11308" name="l11308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbedb5de0b884547782c44dc914795c9">11308</a></span><span class="preprocessor">#define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos) </span></div>
|
||
<div class="line"><a id="l11309" name="l11309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa16b4c4037cf974162a591aea753fc21">11309</a></span><span class="preprocessor">#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk </span></div>
|
||
<div class="line"><a id="l11311" name="l11311"></a><span class="lineno">11311</span><span class="comment">/****************** Bit definition for SDIO_DCOUNT register *****************/</span></div>
|
||
<div class="line"><a id="l11312" name="l11312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga403440b7adc8fe670be0dc8786a0911b">11312</a></span><span class="preprocessor">#define SDIO_DCOUNT_DATACOUNT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11313" name="l11313"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac482f1add1ce39f8fb7c3bc9d8653f77">11313</a></span><span class="preprocessor">#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) </span></div>
|
||
<div class="line"><a id="l11314" name="l11314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f8ab9dfe9d4f809b61fa2b7826adbde">11314</a></span><span class="preprocessor">#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk </span></div>
|
||
<div class="line"><a id="l11316" name="l11316"></a><span class="lineno">11316</span><span class="comment">/****************** Bit definition for SDIO_STA register ********************/</span></div>
|
||
<div class="line"><a id="l11317" name="l11317"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb2c0bead439847c163d2b4166d3b7c8">11317</a></span><span class="preprocessor">#define SDIO_STA_CCRCFAIL_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11318" name="l11318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae72a4ab40725d2063cb2900512f79e57">11318</a></span><span class="preprocessor">#define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos) </span></div>
|
||
<div class="line"><a id="l11319" name="l11319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6dbe59c4bdd8b9a12b092cf84a9daef">11319</a></span><span class="preprocessor">#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk </span></div>
|
||
<div class="line"><a id="l11320" name="l11320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad788ced0bde93f188aed790a18cdde65">11320</a></span><span class="preprocessor">#define SDIO_STA_DCRCFAIL_Pos (1U) </span></div>
|
||
<div class="line"><a id="l11321" name="l11321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad51a35e09d9332c7402e7db2dd3b63d2">11321</a></span><span class="preprocessor">#define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos) </span></div>
|
||
<div class="line"><a id="l11322" name="l11322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga554d1f9986bf5c715dd6f27a6493ce31">11322</a></span><span class="preprocessor">#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk </span></div>
|
||
<div class="line"><a id="l11323" name="l11323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c834436a9afa85d118ef4a83f7cb283">11323</a></span><span class="preprocessor">#define SDIO_STA_CTIMEOUT_Pos (2U) </span></div>
|
||
<div class="line"><a id="l11324" name="l11324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27433ab3bb7c09bfd6c7e65daee2c1c2">11324</a></span><span class="preprocessor">#define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos) </span></div>
|
||
<div class="line"><a id="l11325" name="l11325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae72c4f34bb3ccffeef1d7cdcb7415bdc">11325</a></span><span class="preprocessor">#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk </span></div>
|
||
<div class="line"><a id="l11326" name="l11326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga889faf1ecb5ebaf770074f4228e0f372">11326</a></span><span class="preprocessor">#define SDIO_STA_DTIMEOUT_Pos (3U) </span></div>
|
||
<div class="line"><a id="l11327" name="l11327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9c4e52bb9c5041bd2be2eb216dd9e7c">11327</a></span><span class="preprocessor">#define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos) </span></div>
|
||
<div class="line"><a id="l11328" name="l11328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a2cad7ef3406a46ddba51f7ab5df94b">11328</a></span><span class="preprocessor">#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk </span></div>
|
||
<div class="line"><a id="l11329" name="l11329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c4f937a15d62a7e9a6d761104aab35e">11329</a></span><span class="preprocessor">#define SDIO_STA_TXUNDERR_Pos (4U) </span></div>
|
||
<div class="line"><a id="l11330" name="l11330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac651b75734596780cc225b1c1688741d">11330</a></span><span class="preprocessor">#define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos) </span></div>
|
||
<div class="line"><a id="l11331" name="l11331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b9dcdb8b90d8266eb0c5a2be81238aa">11331</a></span><span class="preprocessor">#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk </span></div>
|
||
<div class="line"><a id="l11332" name="l11332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae72faf7690680a4a9fbeb3da74699d0d">11332</a></span><span class="preprocessor">#define SDIO_STA_RXOVERR_Pos (5U) </span></div>
|
||
<div class="line"><a id="l11333" name="l11333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cd1da9061309343205c1421250ec2ac">11333</a></span><span class="preprocessor">#define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos) </span></div>
|
||
<div class="line"><a id="l11334" name="l11334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4b91289c9f6b773f928706ae8a5ddfc">11334</a></span><span class="preprocessor">#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk </span></div>
|
||
<div class="line"><a id="l11335" name="l11335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa10e00ee0c79b38dd2aa074d4d7d604">11335</a></span><span class="preprocessor">#define SDIO_STA_CMDREND_Pos (6U) </span></div>
|
||
<div class="line"><a id="l11336" name="l11336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ab895524d8a5cbf1b1104abcdf013fe">11336</a></span><span class="preprocessor">#define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos) </span></div>
|
||
<div class="line"><a id="l11337" name="l11337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga096f11117736a2252f1cd5c4cccdc6e6">11337</a></span><span class="preprocessor">#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk </span></div>
|
||
<div class="line"><a id="l11338" name="l11338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeec49be725a39b21c24769feb4f43b89">11338</a></span><span class="preprocessor">#define SDIO_STA_CMDSENT_Pos (7U) </span></div>
|
||
<div class="line"><a id="l11339" name="l11339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ff987cbe6f2afc731016591f7dca4f7">11339</a></span><span class="preprocessor">#define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos) </span></div>
|
||
<div class="line"><a id="l11340" name="l11340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa550641dc6aa942e1b524ad0e557a284">11340</a></span><span class="preprocessor">#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk </span></div>
|
||
<div class="line"><a id="l11341" name="l11341"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaaa45c46418b926d742e8c557eca124d">11341</a></span><span class="preprocessor">#define SDIO_STA_DATAEND_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11342" name="l11342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39ffad41e1ac6eb225eb1f06f320a9c2">11342</a></span><span class="preprocessor">#define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos) </span></div>
|
||
<div class="line"><a id="l11343" name="l11343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe7e354a903b957943cf5b6bed4cdf6b">11343</a></span><span class="preprocessor">#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk </span></div>
|
||
<div class="line"><a id="l11344" name="l11344"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2d7138c3bcb7ccf0d90c93daac3a43a">11344</a></span><span class="preprocessor">#define SDIO_STA_STBITERR_Pos (9U) </span></div>
|
||
<div class="line"><a id="l11345" name="l11345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c826404242f6e6ff56c3b6b3e42863a">11345</a></span><span class="preprocessor">#define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos) </span></div>
|
||
<div class="line"><a id="l11346" name="l11346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a9ef8e72604e9997da23601a2dd84a4">11346</a></span><span class="preprocessor">#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk </span></div>
|
||
<div class="line"><a id="l11347" name="l11347"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56b7b1a0c443227a070222af9cd212f5">11347</a></span><span class="preprocessor">#define SDIO_STA_DBCKEND_Pos (10U) </span></div>
|
||
<div class="line"><a id="l11348" name="l11348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9c1646ceeca1e8e93ca1f4bbb2fd12f">11348</a></span><span class="preprocessor">#define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos) </span></div>
|
||
<div class="line"><a id="l11349" name="l11349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fabf2c02cba6d4de1e90d8d1dc9793c">11349</a></span><span class="preprocessor">#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk </span></div>
|
||
<div class="line"><a id="l11350" name="l11350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2390484299f14b720b5f5e3fa5811538">11350</a></span><span class="preprocessor">#define SDIO_STA_CMDACT_Pos (11U) </span></div>
|
||
<div class="line"><a id="l11351" name="l11351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9c9c8a3be5f8615d36927da8c7152c2">11351</a></span><span class="preprocessor">#define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos) </span></div>
|
||
<div class="line"><a id="l11352" name="l11352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99ccdac7a223635ee5b38a4bae8f30cc">11352</a></span><span class="preprocessor">#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk </span></div>
|
||
<div class="line"><a id="l11353" name="l11353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47ef38c70701b9ca0d77927071bfdd10">11353</a></span><span class="preprocessor">#define SDIO_STA_TXACT_Pos (12U) </span></div>
|
||
<div class="line"><a id="l11354" name="l11354"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8013f5e0b7c82bd29351e0428af7240f">11354</a></span><span class="preprocessor">#define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos) </span></div>
|
||
<div class="line"><a id="l11355" name="l11355"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga908feb4957f48390bc2fc0bde47ac784">11355</a></span><span class="preprocessor">#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk </span></div>
|
||
<div class="line"><a id="l11356" name="l11356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a48d2dd6535975e9d584964067f41a6">11356</a></span><span class="preprocessor">#define SDIO_STA_RXACT_Pos (13U) </span></div>
|
||
<div class="line"><a id="l11357" name="l11357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6804febb98fae68a60c58b4c1e0935e3">11357</a></span><span class="preprocessor">#define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos) </span></div>
|
||
<div class="line"><a id="l11358" name="l11358"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad2f52b50765fa449dcfabc39b099796">11358</a></span><span class="preprocessor">#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk </span></div>
|
||
<div class="line"><a id="l11359" name="l11359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3a623bdff29b95c5a45c523a90fe12e">11359</a></span><span class="preprocessor">#define SDIO_STA_TXFIFOHE_Pos (14U) </span></div>
|
||
<div class="line"><a id="l11360" name="l11360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41135726ff869b6aa9a2f0ed1383ea53">11360</a></span><span class="preprocessor">#define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos) </span></div>
|
||
<div class="line"><a id="l11361" name="l11361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62b9e38be5956dde69049154facc62fd">11361</a></span><span class="preprocessor">#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk </span></div>
|
||
<div class="line"><a id="l11362" name="l11362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f8b161fe0ebbd71a38e85c8caa3a466">11362</a></span><span class="preprocessor">#define SDIO_STA_RXFIFOHF_Pos (15U) </span></div>
|
||
<div class="line"><a id="l11363" name="l11363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a590a016f50e757d6eb58248f9af026">11363</a></span><span class="preprocessor">#define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos) </span></div>
|
||
<div class="line"><a id="l11364" name="l11364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7916c47ee972376a0eaee584133ca36d">11364</a></span><span class="preprocessor">#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk </span></div>
|
||
<div class="line"><a id="l11365" name="l11365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga634b30add702067001f17455bc691740">11365</a></span><span class="preprocessor">#define SDIO_STA_TXFIFOF_Pos (16U) </span></div>
|
||
<div class="line"><a id="l11366" name="l11366"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9d17bbac6dd7388ed367c5ccfa5be1c">11366</a></span><span class="preprocessor">#define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos) </span></div>
|
||
<div class="line"><a id="l11367" name="l11367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1497b46f9a906001dabb7d7604f6c05">11367</a></span><span class="preprocessor">#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk </span></div>
|
||
<div class="line"><a id="l11368" name="l11368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86b297852e15be2ce6b2c08b7432f868">11368</a></span><span class="preprocessor">#define SDIO_STA_RXFIFOF_Pos (17U) </span></div>
|
||
<div class="line"><a id="l11369" name="l11369"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7af9ed233f8115b8d3123bb274d197ec">11369</a></span><span class="preprocessor">#define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos) </span></div>
|
||
<div class="line"><a id="l11370" name="l11370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85f46f873ca5fe91a1e8206d157b9446">11370</a></span><span class="preprocessor">#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk </span></div>
|
||
<div class="line"><a id="l11371" name="l11371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08db94989b17f7ad2e47a029afc89ae2">11371</a></span><span class="preprocessor">#define SDIO_STA_TXFIFOE_Pos (18U) </span></div>
|
||
<div class="line"><a id="l11372" name="l11372"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadae851570f79529e3027cd6ae80b9a19">11372</a></span><span class="preprocessor">#define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos) </span></div>
|
||
<div class="line"><a id="l11373" name="l11373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4624f95c5224c631f99571b5454acd86">11373</a></span><span class="preprocessor">#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk </span></div>
|
||
<div class="line"><a id="l11374" name="l11374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa66efed771cee7e43274a73357e77036">11374</a></span><span class="preprocessor">#define SDIO_STA_RXFIFOE_Pos (19U) </span></div>
|
||
<div class="line"><a id="l11375" name="l11375"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad68af59ab8a514fc2ec9735db58bc4bf">11375</a></span><span class="preprocessor">#define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos) </span></div>
|
||
<div class="line"><a id="l11376" name="l11376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44bf9f7321d65a3effd2df469a58a464">11376</a></span><span class="preprocessor">#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk </span></div>
|
||
<div class="line"><a id="l11377" name="l11377"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae685d8223202af5aaf85779c9b9c33ce">11377</a></span><span class="preprocessor">#define SDIO_STA_TXDAVL_Pos (20U) </span></div>
|
||
<div class="line"><a id="l11378" name="l11378"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ce2c8660375bdf8f10e49af1966f64f">11378</a></span><span class="preprocessor">#define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos) </span></div>
|
||
<div class="line"><a id="l11379" name="l11379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19b374518e813f7a1ac4aec3b24b7517">11379</a></span><span class="preprocessor">#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk </span></div>
|
||
<div class="line"><a id="l11380" name="l11380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5eff3fcfe1a6b51137bb2faa735ede8d">11380</a></span><span class="preprocessor">#define SDIO_STA_RXDAVL_Pos (21U) </span></div>
|
||
<div class="line"><a id="l11381" name="l11381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3c400c578bed5233c91c6e9570a651d">11381</a></span><span class="preprocessor">#define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos) </span></div>
|
||
<div class="line"><a id="l11382" name="l11382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcad9b8c0e3ccba1aa389d7713db6803">11382</a></span><span class="preprocessor">#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk </span></div>
|
||
<div class="line"><a id="l11383" name="l11383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1d1c55503940b44780c405d6e6f7581">11383</a></span><span class="preprocessor">#define SDIO_STA_SDIOIT_Pos (22U) </span></div>
|
||
<div class="line"><a id="l11384" name="l11384"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae20bfd0933cc814ac479a82f720ab423">11384</a></span><span class="preprocessor">#define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos) </span></div>
|
||
<div class="line"><a id="l11385" name="l11385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5df3c10c37285faedb2d853aea4e63dc">11385</a></span><span class="preprocessor">#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk </span></div>
|
||
<div class="line"><a id="l11386" name="l11386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66310759b05b535f231c7750a2cba57e">11386</a></span><span class="preprocessor">#define SDIO_STA_CEATAEND_Pos (23U) </span></div>
|
||
<div class="line"><a id="l11387" name="l11387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa51fdc310e3b16750da76a9d850278a3">11387</a></span><span class="preprocessor">#define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos) </span></div>
|
||
<div class="line"><a id="l11388" name="l11388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d8ef3b4157374fd2b5fc8ed12b77a0c">11388</a></span><span class="preprocessor">#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk </span></div>
|
||
<div class="line"><a id="l11390" name="l11390"></a><span class="lineno">11390</span><span class="comment">/******************* Bit definition for SDIO_ICR register *******************/</span></div>
|
||
<div class="line"><a id="l11391" name="l11391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab10c6948f7bdd82257df5c11a367162c">11391</a></span><span class="preprocessor">#define SDIO_ICR_CCRCFAILC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11392" name="l11392"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9217341f3df0a8ff9f874c86a12ce2b">11392</a></span><span class="preprocessor">#define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos) </span></div>
|
||
<div class="line"><a id="l11393" name="l11393"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44708c45f675cf065f1c7fc9311d6e43">11393</a></span><span class="preprocessor">#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk </span></div>
|
||
<div class="line"><a id="l11394" name="l11394"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b4ddca0c23778a5863dceeb2bbfbeb2">11394</a></span><span class="preprocessor">#define SDIO_ICR_DCRCFAILC_Pos (1U) </span></div>
|
||
<div class="line"><a id="l11395" name="l11395"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1da8c0983fb1afa1403cbb59e453ad8">11395</a></span><span class="preprocessor">#define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos) </span></div>
|
||
<div class="line"><a id="l11396" name="l11396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cb6cde5f88a5d2b635a830dd401c4e0">11396</a></span><span class="preprocessor">#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk </span></div>
|
||
<div class="line"><a id="l11397" name="l11397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96cc705eed0b33038e018d6b72096de3">11397</a></span><span class="preprocessor">#define SDIO_ICR_CTIMEOUTC_Pos (2U) </span></div>
|
||
<div class="line"><a id="l11398" name="l11398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e808d2c69f391700674c1a5e438b453">11398</a></span><span class="preprocessor">#define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos) </span></div>
|
||
<div class="line"><a id="l11399" name="l11399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4d128bee8a97ae9971d42f844d2e297">11399</a></span><span class="preprocessor">#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk </span></div>
|
||
<div class="line"><a id="l11400" name="l11400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada71c35f6df85b0c2193cf39745308fd">11400</a></span><span class="preprocessor">#define SDIO_ICR_DTIMEOUTC_Pos (3U) </span></div>
|
||
<div class="line"><a id="l11401" name="l11401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ca4ee048763e8a5a9205b8e3238ac2d">11401</a></span><span class="preprocessor">#define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos) </span></div>
|
||
<div class="line"><a id="l11402" name="l11402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcb64d3d07a5841ee9f18ff6bc75350b">11402</a></span><span class="preprocessor">#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk </span></div>
|
||
<div class="line"><a id="l11403" name="l11403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga991a111fad2d762541ba63c49ac2a8b8">11403</a></span><span class="preprocessor">#define SDIO_ICR_TXUNDERRC_Pos (4U) </span></div>
|
||
<div class="line"><a id="l11404" name="l11404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54a396bca8fa34f0e4d8387b814b9832">11404</a></span><span class="preprocessor">#define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos) </span></div>
|
||
<div class="line"><a id="l11405" name="l11405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9628d77973f35d628924172831b029f8">11405</a></span><span class="preprocessor">#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk </span></div>
|
||
<div class="line"><a id="l11406" name="l11406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8ed5c5350b9bc9edb9043d7cc0feda3">11406</a></span><span class="preprocessor">#define SDIO_ICR_RXOVERRC_Pos (5U) </span></div>
|
||
<div class="line"><a id="l11407" name="l11407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafab6dbc8ca0e4e78139131e59683aad7">11407</a></span><span class="preprocessor">#define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos) </span></div>
|
||
<div class="line"><a id="l11408" name="l11408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2513d040c7695b152b0b423ad6f5c81e">11408</a></span><span class="preprocessor">#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk </span></div>
|
||
<div class="line"><a id="l11409" name="l11409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24e00e57f1e28f8983ec21d94adbcdd7">11409</a></span><span class="preprocessor">#define SDIO_ICR_CMDRENDC_Pos (6U) </span></div>
|
||
<div class="line"><a id="l11410" name="l11410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga338691a5f364aa9d5c2e31741bf5e520">11410</a></span><span class="preprocessor">#define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos) </span></div>
|
||
<div class="line"><a id="l11411" name="l11411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fb5c67aef48d5ee27b60107d938a58f">11411</a></span><span class="preprocessor">#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk </span></div>
|
||
<div class="line"><a id="l11412" name="l11412"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbd31121662a8f43e9d1e93f7809a78c">11412</a></span><span class="preprocessor">#define SDIO_ICR_CMDSENTC_Pos (7U) </span></div>
|
||
<div class="line"><a id="l11413" name="l11413"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f77128e853dcdb4202ef930d242cc80">11413</a></span><span class="preprocessor">#define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos) </span></div>
|
||
<div class="line"><a id="l11414" name="l11414"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa27fe45ef7461caf704186630b26a196">11414</a></span><span class="preprocessor">#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk </span></div>
|
||
<div class="line"><a id="l11415" name="l11415"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8762bbd49f834e5cda527dada339a4ca">11415</a></span><span class="preprocessor">#define SDIO_ICR_DATAENDC_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11416" name="l11416"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f3222f8b80e53b265fca0c903baaf3f">11416</a></span><span class="preprocessor">#define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos) </span></div>
|
||
<div class="line"><a id="l11417" name="l11417"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga527e1f9cd295845d5be9975cf26bae7e">11417</a></span><span class="preprocessor">#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk </span></div>
|
||
<div class="line"><a id="l11418" name="l11418"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga374e5a92d4f2de580f73d098bba0dc52">11418</a></span><span class="preprocessor">#define SDIO_ICR_STBITERRC_Pos (9U) </span></div>
|
||
<div class="line"><a id="l11419" name="l11419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccd50f6a808007427eec1f2c823e78c5">11419</a></span><span class="preprocessor">#define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos) </span></div>
|
||
<div class="line"><a id="l11420" name="l11420"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae614b5ab8a8aecbc3c1ce74645cdc28c">11420</a></span><span class="preprocessor">#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk </span></div>
|
||
<div class="line"><a id="l11421" name="l11421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a5675867470f147be32bd684344d6c5">11421</a></span><span class="preprocessor">#define SDIO_ICR_DBCKENDC_Pos (10U) </span></div>
|
||
<div class="line"><a id="l11422" name="l11422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79f2c2204f0e3ea155189811ce855802">11422</a></span><span class="preprocessor">#define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos) </span></div>
|
||
<div class="line"><a id="l11423" name="l11423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc5518c07e39dc1f91603737d1a7180b">11423</a></span><span class="preprocessor">#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk </span></div>
|
||
<div class="line"><a id="l11424" name="l11424"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f237d6521d4dcdcb4bdb5049b4d8c16">11424</a></span><span class="preprocessor">#define SDIO_ICR_SDIOITC_Pos (22U) </span></div>
|
||
<div class="line"><a id="l11425" name="l11425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6439a7e034a5af888f93c0e393119573">11425</a></span><span class="preprocessor">#define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos) </span></div>
|
||
<div class="line"><a id="l11426" name="l11426"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2990db729fb017dfd659dc6cf8823761">11426</a></span><span class="preprocessor">#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk </span></div>
|
||
<div class="line"><a id="l11427" name="l11427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cb5a4fcac3d143b45a4a0092c3f3664">11427</a></span><span class="preprocessor">#define SDIO_ICR_CEATAENDC_Pos (23U) </span></div>
|
||
<div class="line"><a id="l11428" name="l11428"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51b6347d4f3229d35547e5ce5a27f481">11428</a></span><span class="preprocessor">#define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos) </span></div>
|
||
<div class="line"><a id="l11429" name="l11429"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f1cebd40fd1eafb59635b284c5a3f34">11429</a></span><span class="preprocessor">#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk </span></div>
|
||
<div class="line"><a id="l11431" name="l11431"></a><span class="lineno">11431</span><span class="comment">/****************** Bit definition for SDIO_MASK register *******************/</span></div>
|
||
<div class="line"><a id="l11432" name="l11432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd6b95c5dfb466ba4fe1d6ba24a69167">11432</a></span><span class="preprocessor">#define SDIO_MASK_CCRCFAILIE_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11433" name="l11433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac74c97fa260e2834d977ab7537bdd4ef">11433</a></span><span class="preprocessor">#define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos) </span></div>
|
||
<div class="line"><a id="l11434" name="l11434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e24d12a6c9af91337cb391d3ba698f3">11434</a></span><span class="preprocessor">#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk </span></div>
|
||
<div class="line"><a id="l11435" name="l11435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3cc4b96a34db55f9e9862e615f8c243">11435</a></span><span class="preprocessor">#define SDIO_MASK_DCRCFAILIE_Pos (1U) </span></div>
|
||
<div class="line"><a id="l11436" name="l11436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd0eb870977ae895b80ac57187a1d112">11436</a></span><span class="preprocessor">#define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) </span></div>
|
||
<div class="line"><a id="l11437" name="l11437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e2e106a1f7792f054c6cc1f60906a09">11437</a></span><span class="preprocessor">#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk </span></div>
|
||
<div class="line"><a id="l11438" name="l11438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6023176201d68b77f056f32e85d5e4fc">11438</a></span><span class="preprocessor">#define SDIO_MASK_CTIMEOUTIE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l11439" name="l11439"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01b92fda0043d94bfef382fb74bf588b">11439</a></span><span class="preprocessor">#define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) </span></div>
|
||
<div class="line"><a id="l11440" name="l11440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23f5a8c06e289522af0a679b08bdb014">11440</a></span><span class="preprocessor">#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk </span></div>
|
||
<div class="line"><a id="l11441" name="l11441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ee212e4944c5dd21acb553da80e84a5">11441</a></span><span class="preprocessor">#define SDIO_MASK_DTIMEOUTIE_Pos (3U) </span></div>
|
||
<div class="line"><a id="l11442" name="l11442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc92448e7adf15a3410f4c0a4c760eeb">11442</a></span><span class="preprocessor">#define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) </span></div>
|
||
<div class="line"><a id="l11443" name="l11443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b4cc63338fe72abd76e5b399c47379b">11443</a></span><span class="preprocessor">#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk </span></div>
|
||
<div class="line"><a id="l11444" name="l11444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0289babaca7a9d6ae404e78709152f20">11444</a></span><span class="preprocessor">#define SDIO_MASK_TXUNDERRIE_Pos (4U) </span></div>
|
||
<div class="line"><a id="l11445" name="l11445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga245c0ebe407cfe97f42c98563070a7ef">11445</a></span><span class="preprocessor">#define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) </span></div>
|
||
<div class="line"><a id="l11446" name="l11446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e02e525dc6ca1bb294b174e7391753d">11446</a></span><span class="preprocessor">#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk </span></div>
|
||
<div class="line"><a id="l11447" name="l11447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15463333aaa2b90d2339b6dc4bd4e3ea">11447</a></span><span class="preprocessor">#define SDIO_MASK_RXOVERRIE_Pos (5U) </span></div>
|
||
<div class="line"><a id="l11448" name="l11448"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a0b758cbc6aed0e4a7633e451b55303">11448</a></span><span class="preprocessor">#define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos) </span></div>
|
||
<div class="line"><a id="l11449" name="l11449"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39f494cf2a6af6ced9eaeac751ea81e4">11449</a></span><span class="preprocessor">#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk </span></div>
|
||
<div class="line"><a id="l11450" name="l11450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbd0400c13633977796a92dd74adeaf9">11450</a></span><span class="preprocessor">#define SDIO_MASK_CMDRENDIE_Pos (6U) </span></div>
|
||
<div class="line"><a id="l11451" name="l11451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74564e18483f0efdea46c242d9c3b3a5">11451</a></span><span class="preprocessor">#define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos) </span></div>
|
||
<div class="line"><a id="l11452" name="l11452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fdedfc60a2019ff5f64533fcdd0c3f1">11452</a></span><span class="preprocessor">#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk </span></div>
|
||
<div class="line"><a id="l11453" name="l11453"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ad32e7a435cc2eaaf3fb38a908a206e">11453</a></span><span class="preprocessor">#define SDIO_MASK_CMDSENTIE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l11454" name="l11454"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cbd551da11e6e93c52b6727075baf9f">11454</a></span><span class="preprocessor">#define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos) </span></div>
|
||
<div class="line"><a id="l11455" name="l11455"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d541aea02974c03bd8a8426125c35ff">11455</a></span><span class="preprocessor">#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk </span></div>
|
||
<div class="line"><a id="l11456" name="l11456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6fa6436185588c5ea061ea7f214e81f">11456</a></span><span class="preprocessor">#define SDIO_MASK_DATAENDIE_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11457" name="l11457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28535e2fb4bbf3caf2764a47535e837f">11457</a></span><span class="preprocessor">#define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos) </span></div>
|
||
<div class="line"><a id="l11458" name="l11458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6398bd3e8312eea3b986ab59b80b466">11458</a></span><span class="preprocessor">#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk </span></div>
|
||
<div class="line"><a id="l11459" name="l11459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga962af1aaad7bc9eb55689d694b3949a4">11459</a></span><span class="preprocessor">#define SDIO_MASK_STBITERRIE_Pos (9U) </span></div>
|
||
<div class="line"><a id="l11460" name="l11460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0192872018530a05a2cec00d61a6a39">11460</a></span><span class="preprocessor">#define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos) </span></div>
|
||
<div class="line"><a id="l11461" name="l11461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4194bed51eb4a951a58a5d4062ba978f">11461</a></span><span class="preprocessor">#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk </span></div>
|
||
<div class="line"><a id="l11462" name="l11462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75e2c1e3ade0e06784c004b34410e9ef">11462</a></span><span class="preprocessor">#define SDIO_MASK_DBCKENDIE_Pos (10U) </span></div>
|
||
<div class="line"><a id="l11463" name="l11463"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafd5167ec8f17f72e3d604c3f628bd06">11463</a></span><span class="preprocessor">#define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos) </span></div>
|
||
<div class="line"><a id="l11464" name="l11464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga947e5da36c9eeca0b48f3356067dff00">11464</a></span><span class="preprocessor">#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk </span></div>
|
||
<div class="line"><a id="l11465" name="l11465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2447a1963bd315c20f05574acd8efac0">11465</a></span><span class="preprocessor">#define SDIO_MASK_CMDACTIE_Pos (11U) </span></div>
|
||
<div class="line"><a id="l11466" name="l11466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae44d7772868e54b7a90f90a4a52520ec">11466</a></span><span class="preprocessor">#define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos) </span></div>
|
||
<div class="line"><a id="l11467" name="l11467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad63b504f02ea0b1e5ec48962799fde88">11467</a></span><span class="preprocessor">#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk </span></div>
|
||
<div class="line"><a id="l11468" name="l11468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga985a6a5e37ed6fb963deb83f0acd457b">11468</a></span><span class="preprocessor">#define SDIO_MASK_TXACTIE_Pos (12U) </span></div>
|
||
<div class="line"><a id="l11469" name="l11469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3bc5a7e08f3f427ccd7769c67233e5d">11469</a></span><span class="preprocessor">#define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos) </span></div>
|
||
<div class="line"><a id="l11470" name="l11470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9bbfbc3f69ab77171eb1a0058783b1e0">11470</a></span><span class="preprocessor">#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk </span></div>
|
||
<div class="line"><a id="l11471" name="l11471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga243af5a2aca3b596fa214416a70f969f">11471</a></span><span class="preprocessor">#define SDIO_MASK_RXACTIE_Pos (13U) </span></div>
|
||
<div class="line"><a id="l11472" name="l11472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70e765da34a593f616c4435093d0a1d8">11472</a></span><span class="preprocessor">#define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos) </span></div>
|
||
<div class="line"><a id="l11473" name="l11473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9768c39a5d9d3c5519eb522c62a75eae">11473</a></span><span class="preprocessor">#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk </span></div>
|
||
<div class="line"><a id="l11474" name="l11474"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad10c89cc7329707f9c9aa1c3ad259980">11474</a></span><span class="preprocessor">#define SDIO_MASK_TXFIFOHEIE_Pos (14U) </span></div>
|
||
<div class="line"><a id="l11475" name="l11475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31a0538971e372ab926c3a9f935b2502">11475</a></span><span class="preprocessor">#define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) </span></div>
|
||
<div class="line"><a id="l11476" name="l11476"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9cf28de8489fee023ea353df0e13fa7">11476</a></span><span class="preprocessor">#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk </span></div>
|
||
<div class="line"><a id="l11477" name="l11477"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad002b428c2d95c229b914fac2a620ef8">11477</a></span><span class="preprocessor">#define SDIO_MASK_RXFIFOHFIE_Pos (15U) </span></div>
|
||
<div class="line"><a id="l11478" name="l11478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4590335a3dcdb764c68d8f31bc58d2ba">11478</a></span><span class="preprocessor">#define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) </span></div>
|
||
<div class="line"><a id="l11479" name="l11479"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04d50028fc671494508aecb04e727102">11479</a></span><span class="preprocessor">#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk </span></div>
|
||
<div class="line"><a id="l11480" name="l11480"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadb33e583b2dd534458a807d4efa4d97">11480</a></span><span class="preprocessor">#define SDIO_MASK_TXFIFOFIE_Pos (16U) </span></div>
|
||
<div class="line"><a id="l11481" name="l11481"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae60848e2a91f045224142d4a9ba87baf">11481</a></span><span class="preprocessor">#define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos) </span></div>
|
||
<div class="line"><a id="l11482" name="l11482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03a602b975ce16ef03083947aded0172">11482</a></span><span class="preprocessor">#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk </span></div>
|
||
<div class="line"><a id="l11483" name="l11483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcac0bf1f49c1677a8fee6aab994a453">11483</a></span><span class="preprocessor">#define SDIO_MASK_RXFIFOFIE_Pos (17U) </span></div>
|
||
<div class="line"><a id="l11484" name="l11484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4550fadc2377f998ad61c94f37047e41">11484</a></span><span class="preprocessor">#define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos) </span></div>
|
||
<div class="line"><a id="l11485" name="l11485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf18c4bdf8fa4ee85596a89de00158fbb">11485</a></span><span class="preprocessor">#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk </span></div>
|
||
<div class="line"><a id="l11486" name="l11486"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c795dfbbb4b28e0acdec9ad9ec7f590">11486</a></span><span class="preprocessor">#define SDIO_MASK_TXFIFOEIE_Pos (18U) </span></div>
|
||
<div class="line"><a id="l11487" name="l11487"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05690f47ab17f3296f9e7c1f775546f1">11487</a></span><span class="preprocessor">#define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos) </span></div>
|
||
<div class="line"><a id="l11488" name="l11488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11e1d67150fad62dc1ca7783f3a19372">11488</a></span><span class="preprocessor">#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk </span></div>
|
||
<div class="line"><a id="l11489" name="l11489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac80b2ced5391058cad7184a273b7c8fd">11489</a></span><span class="preprocessor">#define SDIO_MASK_RXFIFOEIE_Pos (19U) </span></div>
|
||
<div class="line"><a id="l11490" name="l11490"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga432a6fa01c2c45135e5d7c43fef9f21b">11490</a></span><span class="preprocessor">#define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos) </span></div>
|
||
<div class="line"><a id="l11491" name="l11491"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbc23fa1c153a9e5216baeef7922e412">11491</a></span><span class="preprocessor">#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk </span></div>
|
||
<div class="line"><a id="l11492" name="l11492"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5efa0b963adeda521a951841b9da44e5">11492</a></span><span class="preprocessor">#define SDIO_MASK_TXDAVLIE_Pos (20U) </span></div>
|
||
<div class="line"><a id="l11493" name="l11493"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36e2a9aae5673ab117a1e33c2af0d801">11493</a></span><span class="preprocessor">#define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos) </span></div>
|
||
<div class="line"><a id="l11494" name="l11494"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a1988093a6df087ebb8ff41a51962da">11494</a></span><span class="preprocessor">#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk </span></div>
|
||
<div class="line"><a id="l11495" name="l11495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb8703a3b6e980002afae732dc62f40e">11495</a></span><span class="preprocessor">#define SDIO_MASK_RXDAVLIE_Pos (21U) </span></div>
|
||
<div class="line"><a id="l11496" name="l11496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20d7d199042e90d08b1542fbf551d756">11496</a></span><span class="preprocessor">#define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos) </span></div>
|
||
<div class="line"><a id="l11497" name="l11497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa9da7d15902e6f94b79968a07250696">11497</a></span><span class="preprocessor">#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk </span></div>
|
||
<div class="line"><a id="l11498" name="l11498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5b99a0d2f0e9d1629e5fe9904c8d042">11498</a></span><span class="preprocessor">#define SDIO_MASK_SDIOITIE_Pos (22U) </span></div>
|
||
<div class="line"><a id="l11499" name="l11499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab53292cf69bf87c65f8b41970b06c4fd">11499</a></span><span class="preprocessor">#define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos) </span></div>
|
||
<div class="line"><a id="l11500" name="l11500"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad73b7c7d480d2d71613995cfecc59138">11500</a></span><span class="preprocessor">#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk </span></div>
|
||
<div class="line"><a id="l11501" name="l11501"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc625ef424192b5a0875466d58b7d32a">11501</a></span><span class="preprocessor">#define SDIO_MASK_CEATAENDIE_Pos (23U) </span></div>
|
||
<div class="line"><a id="l11502" name="l11502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7131c534b24505a7ec74cfbcd2d2fbca">11502</a></span><span class="preprocessor">#define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos) </span></div>
|
||
<div class="line"><a id="l11503" name="l11503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a19dd3039888ebdc40b2406be400749">11503</a></span><span class="preprocessor">#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk </span></div>
|
||
<div class="line"><a id="l11505" name="l11505"></a><span class="lineno">11505</span><span class="comment">/***************** Bit definition for SDIO_FIFOCNT register *****************/</span></div>
|
||
<div class="line"><a id="l11506" name="l11506"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga078938dbe175e28e4d3898a04db76fc9">11506</a></span><span class="preprocessor">#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11507" name="l11507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f6da07732f3b3e77ffabfed13a613ea">11507</a></span><span class="preprocessor">#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) </span></div>
|
||
<div class="line"><a id="l11508" name="l11508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa45f5e0a2be89267f79cad57f456f0a2">11508</a></span><span class="preprocessor">#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk </span></div>
|
||
<div class="line"><a id="l11510" name="l11510"></a><span class="lineno">11510</span><span class="comment">/****************** Bit definition for SDIO_FIFO register *******************/</span></div>
|
||
<div class="line"><a id="l11511" name="l11511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga801e95e916e2fefcab25aad333e63c0c">11511</a></span><span class="preprocessor">#define SDIO_FIFO_FIFODATA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11512" name="l11512"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2000ca9b6103ee2ad7588b34283cfff">11512</a></span><span class="preprocessor">#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) </span></div>
|
||
<div class="line"><a id="l11513" name="l11513"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fc0d1e12c55398e2881fe917672da25">11513</a></span><span class="preprocessor">#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk </span></div>
|
||
<div class="line"><a id="l11515" name="l11515"></a><span class="lineno">11515</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l11516" name="l11516"></a><span class="lineno">11516</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l11517" name="l11517"></a><span class="lineno">11517</span><span class="comment">/* Serial Peripheral Interface */</span></div>
|
||
<div class="line"><a id="l11518" name="l11518"></a><span class="lineno">11518</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l11519" name="l11519"></a><span class="lineno">11519</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l11520" name="l11520"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf384b964839c07357ce8503464436ed">11520</a></span><span class="preprocessor">#define SPI_I2S_FULLDUPLEX_SUPPORT </span></div>
|
||
<div class="line"><a id="l11522" name="l11522"></a><span class="lineno">11522</span><span class="comment">/******************* Bit definition for SPI_CR1 register ********************/</span></div>
|
||
<div class="line"><a id="l11523" name="l11523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f1d2c5a9e481ca06d0e29332f6f948a">11523</a></span><span class="preprocessor">#define SPI_CR1_CPHA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11524" name="l11524"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07233629d8982af09168080501d30522">11524</a></span><span class="preprocessor">#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) </span></div>
|
||
<div class="line"><a id="l11525" name="l11525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97602d8ded14bbd2c1deadaf308755a3">11525</a></span><span class="preprocessor">#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk </span></div>
|
||
<div class="line"><a id="l11526" name="l11526"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd3274c0dce6293370773c5050f9c4be">11526</a></span><span class="preprocessor">#define SPI_CR1_CPOL_Pos (1U) </span></div>
|
||
<div class="line"><a id="l11527" name="l11527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95caab18b821909a9547771f9316e2b0">11527</a></span><span class="preprocessor">#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) </span></div>
|
||
<div class="line"><a id="l11528" name="l11528"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2616a10f5118cdc68fbdf0582481e124">11528</a></span><span class="preprocessor">#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk </span></div>
|
||
<div class="line"><a id="l11529" name="l11529"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27567886a2c76d088e01ad16851cdb71">11529</a></span><span class="preprocessor">#define SPI_CR1_MSTR_Pos (2U) </span></div>
|
||
<div class="line"><a id="l11530" name="l11530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab94621170d4ce16d6e7f2310461df97d">11530</a></span><span class="preprocessor">#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) </span></div>
|
||
<div class="line"><a id="l11531" name="l11531"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b3b6ae107fc37bf18e14506298d7a55">11531</a></span><span class="preprocessor">#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk </span></div>
|
||
<div class="line"><a id="l11533" name="l11533"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6a71c219a81b476e66c3579d72120b9">11533</a></span><span class="preprocessor">#define SPI_CR1_BR_Pos (3U) </span></div>
|
||
<div class="line"><a id="l11534" name="l11534"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec378749f03998b5d2769c3d83deef23">11534</a></span><span class="preprocessor">#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) </span></div>
|
||
<div class="line"><a id="l11535" name="l11535"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga261af22667719a32b3ce566c1e261936">11535</a></span><span class="preprocessor">#define SPI_CR1_BR SPI_CR1_BR_Msk </span></div>
|
||
<div class="line"><a id="l11536" name="l11536"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa364b123cf797044094cc229330ce321">11536</a></span><span class="preprocessor">#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) </span></div>
|
||
<div class="line"><a id="l11537" name="l11537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45e93d18c8966964ed1926d5ca87ef46">11537</a></span><span class="preprocessor">#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) </span></div>
|
||
<div class="line"><a id="l11538" name="l11538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28b823d564e9d90150bcc6744b4ed622">11538</a></span><span class="preprocessor">#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) </span></div>
|
||
<div class="line"><a id="l11540" name="l11540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f5515b536f82c1d91a64bd534030284">11540</a></span><span class="preprocessor">#define SPI_CR1_SPE_Pos (6U) </span></div>
|
||
<div class="line"><a id="l11541" name="l11541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5cf4679f3fe8cfa50ecbac5b45d084bb">11541</a></span><span class="preprocessor">#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) </span></div>
|
||
<div class="line"><a id="l11542" name="l11542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5a646d978d3b98eb7c6a5d95d75c3f9">11542</a></span><span class="preprocessor">#define SPI_CR1_SPE SPI_CR1_SPE_Msk </span></div>
|
||
<div class="line"><a id="l11543" name="l11543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga982b564879d1dc60a3be787409df0c27">11543</a></span><span class="preprocessor">#define SPI_CR1_LSBFIRST_Pos (7U) </span></div>
|
||
<div class="line"><a id="l11544" name="l11544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfc0bbf312eaf7e0a5bbe54fdcc2f12e">11544</a></span><span class="preprocessor">#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) </span></div>
|
||
<div class="line"><a id="l11545" name="l11545"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab929e9d5ddbb66f229c501ab18d0e6e8">11545</a></span><span class="preprocessor">#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk </span></div>
|
||
<div class="line"><a id="l11546" name="l11546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad99cf4909aa9307e01f61645451a9d0e">11546</a></span><span class="preprocessor">#define SPI_CR1_SSI_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11547" name="l11547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0bfe153c59ffd52199d4b37e3287f89">11547</a></span><span class="preprocessor">#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) </span></div>
|
||
<div class="line"><a id="l11548" name="l11548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f154374b58c0234f82ea326cb303a1e">11548</a></span><span class="preprocessor">#define SPI_CR1_SSI SPI_CR1_SSI_Msk </span></div>
|
||
<div class="line"><a id="l11549" name="l11549"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2909290fab17ee930afc335811f574c">11549</a></span><span class="preprocessor">#define SPI_CR1_SSM_Pos (9U) </span></div>
|
||
<div class="line"><a id="l11550" name="l11550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43417092a8ed735def35b386a251a7bb">11550</a></span><span class="preprocessor">#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) </span></div>
|
||
<div class="line"><a id="l11551" name="l11551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e236047e05106cf1ba7929766311382">11551</a></span><span class="preprocessor">#define SPI_CR1_SSM SPI_CR1_SSM_Msk </span></div>
|
||
<div class="line"><a id="l11552" name="l11552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd702fae4dcca65f3b43b2e02f67ee7b">11552</a></span><span class="preprocessor">#define SPI_CR1_RXONLY_Pos (10U) </span></div>
|
||
<div class="line"><a id="l11553" name="l11553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02d6321808ed988c60d703e062d58b64">11553</a></span><span class="preprocessor">#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) </span></div>
|
||
<div class="line"><a id="l11554" name="l11554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ffecf774b84a8cdc11ab1f931791883">11554</a></span><span class="preprocessor">#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk </span></div>
|
||
<div class="line"><a id="l11555" name="l11555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5290662db14690d4bcf30ed9e4694462">11555</a></span><span class="preprocessor">#define SPI_CR1_DFF_Pos (11U) </span></div>
|
||
<div class="line"><a id="l11556" name="l11556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a87fe55ac0f85e207a58fcd73610f46">11556</a></span><span class="preprocessor">#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) </span></div>
|
||
<div class="line"><a id="l11557" name="l11557"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ffabea0de695a19198d906bf6a1d9fd">11557</a></span><span class="preprocessor">#define SPI_CR1_DFF SPI_CR1_DFF_Msk </span></div>
|
||
<div class="line"><a id="l11558" name="l11558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4280bd0e8bcc3a268fa3a17b684499d7">11558</a></span><span class="preprocessor">#define SPI_CR1_CRCNEXT_Pos (12U) </span></div>
|
||
<div class="line"><a id="l11559" name="l11559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebbf9ed4a9723901f5414654f151d816">11559</a></span><span class="preprocessor">#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) </span></div>
|
||
<div class="line"><a id="l11560" name="l11560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57072f13c2e54c12186ae8c5fdecb250">11560</a></span><span class="preprocessor">#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk </span></div>
|
||
<div class="line"><a id="l11561" name="l11561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54cb3022c5e3d98cd81a7ff1cb087fac">11561</a></span><span class="preprocessor">#define SPI_CR1_CRCEN_Pos (13U) </span></div>
|
||
<div class="line"><a id="l11562" name="l11562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a5a712f31c65ea8ee829377edc5ede3">11562</a></span><span class="preprocessor">#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) </span></div>
|
||
<div class="line"><a id="l11563" name="l11563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9339b7c6466f09ad26c26b3bb81c51b">11563</a></span><span class="preprocessor">#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk </span></div>
|
||
<div class="line"><a id="l11564" name="l11564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2975c27caad9e31aad719d78d591ac1d">11564</a></span><span class="preprocessor">#define SPI_CR1_BIDIOE_Pos (14U) </span></div>
|
||
<div class="line"><a id="l11565" name="l11565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bcee503ed5669187bb980faf90d57ca">11565</a></span><span class="preprocessor">#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) </span></div>
|
||
<div class="line"><a id="l11566" name="l11566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga378953916b7701bd49f063c0366b703f">11566</a></span><span class="preprocessor">#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk </span></div>
|
||
<div class="line"><a id="l11567" name="l11567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab07c9facbfdb0a7d5d89b1fd6a3ef711">11567</a></span><span class="preprocessor">#define SPI_CR1_BIDIMODE_Pos (15U) </span></div>
|
||
<div class="line"><a id="l11568" name="l11568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2c9301aa73d6795e9739f8d12d42c15">11568</a></span><span class="preprocessor">#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) </span></div>
|
||
<div class="line"><a id="l11569" name="l11569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43608d3c2959fc9ca64398d61cbf484e">11569</a></span><span class="preprocessor">#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk </span></div>
|
||
<div class="line"><a id="l11571" name="l11571"></a><span class="lineno">11571</span><span class="comment">/******************* Bit definition for SPI_CR2 register ********************/</span></div>
|
||
<div class="line"><a id="l11572" name="l11572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3079c4eebd0aef7bd22817bb99f21021">11572</a></span><span class="preprocessor">#define SPI_CR2_RXDMAEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11573" name="l11573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae038c9a5d545c01038bf6628492cdc6e">11573</a></span><span class="preprocessor">#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) </span></div>
|
||
<div class="line"><a id="l11574" name="l11574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf23c590d98279634af05550702a806da">11574</a></span><span class="preprocessor">#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk </span></div>
|
||
<div class="line"><a id="l11575" name="l11575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24ae89d7e48296566cd18fb7495a2c81">11575</a></span><span class="preprocessor">#define SPI_CR2_TXDMAEN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l11576" name="l11576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga884bb8bbd8b60cea7b7fb11a23231678">11576</a></span><span class="preprocessor">#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) </span></div>
|
||
<div class="line"><a id="l11577" name="l11577"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3eee671793983a3bd669c9173b2ce210">11577</a></span><span class="preprocessor">#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk </span></div>
|
||
<div class="line"><a id="l11578" name="l11578"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0d0f5f51a5804e1a204bf1643516896">11578</a></span><span class="preprocessor">#define SPI_CR2_SSOE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l11579" name="l11579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4de245d8ff3e31709fd9a665e58f15c1">11579</a></span><span class="preprocessor">#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) </span></div>
|
||
<div class="line"><a id="l11580" name="l11580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae94612b95395eff626f5f3d7d28352dd">11580</a></span><span class="preprocessor">#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk </span></div>
|
||
<div class="line"><a id="l11581" name="l11581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa192ac1c1066c8867a6fec7de630d222">11581</a></span><span class="preprocessor">#define SPI_CR2_FRF_Pos (4U) </span></div>
|
||
<div class="line"><a id="l11582" name="l11582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47060f3941e2410bd9bc3b570f39a3d1">11582</a></span><span class="preprocessor">#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) </span></div>
|
||
<div class="line"><a id="l11583" name="l11583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09e3f41fa2150831afaac191046087f2">11583</a></span><span class="preprocessor">#define SPI_CR2_FRF SPI_CR2_FRF_Msk </span></div>
|
||
<div class="line"><a id="l11584" name="l11584"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga632cdba8557df9c3bbd2561b93f4e0f7">11584</a></span><span class="preprocessor">#define SPI_CR2_ERRIE_Pos (5U) </span></div>
|
||
<div class="line"><a id="l11585" name="l11585"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fb21a03a7b4e7bd38520e2909063c92">11585</a></span><span class="preprocessor">#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) </span></div>
|
||
<div class="line"><a id="l11586" name="l11586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf18705567de7ab52a62e5ef3ba27418b">11586</a></span><span class="preprocessor">#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk </span></div>
|
||
<div class="line"><a id="l11587" name="l11587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2e1e16fa6007b96880333d0321c5971">11587</a></span><span class="preprocessor">#define SPI_CR2_RXNEIE_Pos (6U) </span></div>
|
||
<div class="line"><a id="l11588" name="l11588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ad371f3900a415251ab34cd186d9a44">11588</a></span><span class="preprocessor">#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) </span></div>
|
||
<div class="line"><a id="l11589" name="l11589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7d4c37fbbcced7f2a0421e6ffd103ea">11589</a></span><span class="preprocessor">#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk </span></div>
|
||
<div class="line"><a id="l11590" name="l11590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01e9b00dc195c10d1baefd0687ab9262">11590</a></span><span class="preprocessor">#define SPI_CR2_TXEIE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l11591" name="l11591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64d3cd4fd2b7dca5e43332a3e2a36641">11591</a></span><span class="preprocessor">#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) </span></div>
|
||
<div class="line"><a id="l11592" name="l11592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23f683a1252ccaf625cae1a978989b2c">11592</a></span><span class="preprocessor">#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk </span></div>
|
||
<div class="line"><a id="l11594" name="l11594"></a><span class="lineno">11594</span><span class="comment">/******************** Bit definition for SPI_SR register ********************/</span></div>
|
||
<div class="line"><a id="l11595" name="l11595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga306a27b203d1275f848f2767d76c9e3b">11595</a></span><span class="preprocessor">#define SPI_SR_RXNE_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11596" name="l11596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85e7198d3d1f577cae637c8295e7691e">11596</a></span><span class="preprocessor">#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) </span></div>
|
||
<div class="line"><a id="l11597" name="l11597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40e14de547aa06864abcd4b0422d8b48">11597</a></span><span class="preprocessor">#define SPI_SR_RXNE SPI_SR_RXNE_Msk </span></div>
|
||
<div class="line"><a id="l11598" name="l11598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92e10388eb117c22b63994b491d9ec9d">11598</a></span><span class="preprocessor">#define SPI_SR_TXE_Pos (1U) </span></div>
|
||
<div class="line"><a id="l11599" name="l11599"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee9564d438c48424c767347324a2eb03">11599</a></span><span class="preprocessor">#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) </span></div>
|
||
<div class="line"><a id="l11600" name="l11600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bd5d21816947fcb25ccae7d3bf8eb2c">11600</a></span><span class="preprocessor">#define SPI_SR_TXE SPI_SR_TXE_Msk </span></div>
|
||
<div class="line"><a id="l11601" name="l11601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5b742da8b06539f6119d020885a6e0c">11601</a></span><span class="preprocessor">#define SPI_SR_CHSIDE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l11602" name="l11602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga226666adbdbd46974bcc4a05772bbfc4">11602</a></span><span class="preprocessor">#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) </span></div>
|
||
<div class="line"><a id="l11603" name="l11603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81bd052f0b2e819ddd6bb16c2292a2de">11603</a></span><span class="preprocessor">#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk </span></div>
|
||
<div class="line"><a id="l11604" name="l11604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93586e3966e74b1df8dbda75e68b26f0">11604</a></span><span class="preprocessor">#define SPI_SR_UDR_Pos (3U) </span></div>
|
||
<div class="line"><a id="l11605" name="l11605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ceaae6d492b8b844ff2b83e3251d28e">11605</a></span><span class="preprocessor">#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) </span></div>
|
||
<div class="line"><a id="l11606" name="l11606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13d3292e963499c0e9a36869909229e6">11606</a></span><span class="preprocessor">#define SPI_SR_UDR SPI_SR_UDR_Msk </span></div>
|
||
<div class="line"><a id="l11607" name="l11607"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga411b6a4aa85d06e425050130f82db35c">11607</a></span><span class="preprocessor">#define SPI_SR_CRCERR_Pos (4U) </span></div>
|
||
<div class="line"><a id="l11608" name="l11608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4f508924f9e531136bf0d4fadb68d48">11608</a></span><span class="preprocessor">#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) </span></div>
|
||
<div class="line"><a id="l11609" name="l11609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69e543fa9584fd636032a3ee735f750b">11609</a></span><span class="preprocessor">#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk </span></div>
|
||
<div class="line"><a id="l11610" name="l11610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb7ef73b03bbd542c54fc4e9c9124e73">11610</a></span><span class="preprocessor">#define SPI_SR_MODF_Pos (5U) </span></div>
|
||
<div class="line"><a id="l11611" name="l11611"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3db9b07f317546b9f724067956b07e9c">11611</a></span><span class="preprocessor">#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) </span></div>
|
||
<div class="line"><a id="l11612" name="l11612"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabaa043349833dc7b8138969c64f63adf">11612</a></span><span class="preprocessor">#define SPI_SR_MODF SPI_SR_MODF_Msk </span></div>
|
||
<div class="line"><a id="l11613" name="l11613"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6137ac3afbbc8b50c7a998368d2cb9be">11613</a></span><span class="preprocessor">#define SPI_SR_OVR_Pos (6U) </span></div>
|
||
<div class="line"><a id="l11614" name="l11614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73daf0783ad13468420bbf4d05e150dd">11614</a></span><span class="preprocessor">#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) </span></div>
|
||
<div class="line"><a id="l11615" name="l11615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8d902302c5eb81ce4a57029de281232">11615</a></span><span class="preprocessor">#define SPI_SR_OVR SPI_SR_OVR_Msk </span></div>
|
||
<div class="line"><a id="l11616" name="l11616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8313629719f8dc81536dd8faa824e6c8">11616</a></span><span class="preprocessor">#define SPI_SR_BSY_Pos (7U) </span></div>
|
||
<div class="line"><a id="l11617" name="l11617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcecff7ba1632cf4035a83dd588c4421">11617</a></span><span class="preprocessor">#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) </span></div>
|
||
<div class="line"><a id="l11618" name="l11618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3498df67729ae048dc5f315ef7c16bf">11618</a></span><span class="preprocessor">#define SPI_SR_BSY SPI_SR_BSY_Msk </span></div>
|
||
<div class="line"><a id="l11619" name="l11619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb0e70677f5775a55044111eb83e1ba6">11619</a></span><span class="preprocessor">#define SPI_SR_FRE_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11620" name="l11620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd7e467f149f7b4f7c6eb2deb8be5338">11620</a></span><span class="preprocessor">#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) </span></div>
|
||
<div class="line"><a id="l11621" name="l11621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace2c7cac9431231663af42e6f5aabce6">11621</a></span><span class="preprocessor">#define SPI_SR_FRE SPI_SR_FRE_Msk </span></div>
|
||
<div class="line"><a id="l11623" name="l11623"></a><span class="lineno">11623</span><span class="comment">/******************** Bit definition for SPI_DR register ********************/</span></div>
|
||
<div class="line"><a id="l11624" name="l11624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b57ca6bca45cfdaed4a26fefc0da85f">11624</a></span><span class="preprocessor">#define SPI_DR_DR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11625" name="l11625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf50021b52352481a497f21c72c33e966">11625</a></span><span class="preprocessor">#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) </span></div>
|
||
<div class="line"><a id="l11626" name="l11626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4da7d7f05a28d1aaa52ec557e55e1ad">11626</a></span><span class="preprocessor">#define SPI_DR_DR SPI_DR_DR_Msk </span></div>
|
||
<div class="line"><a id="l11628" name="l11628"></a><span class="lineno">11628</span><span class="comment">/******************* Bit definition for SPI_CRCPR register ******************/</span></div>
|
||
<div class="line"><a id="l11629" name="l11629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0244eb48f4c5158b03dd4b26cc0d2eac">11629</a></span><span class="preprocessor">#define SPI_CRCPR_CRCPOLY_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11630" name="l11630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67c234978a817dee4fc561201b3ef056">11630</a></span><span class="preprocessor">#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) </span></div>
|
||
<div class="line"><a id="l11631" name="l11631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae968658ab837800723eafcc21af10247">11631</a></span><span class="preprocessor">#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk </span></div>
|
||
<div class="line"><a id="l11633" name="l11633"></a><span class="lineno">11633</span><span class="comment">/****************** Bit definition for SPI_RXCRCR register ******************/</span></div>
|
||
<div class="line"><a id="l11634" name="l11634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b80d92a2b51c4c61d5a646ac2b36129">11634</a></span><span class="preprocessor">#define SPI_RXCRCR_RXCRC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11635" name="l11635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3318f05b5d1bebf96434ae4bc88e46da">11635</a></span><span class="preprocessor">#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) </span></div>
|
||
<div class="line"><a id="l11636" name="l11636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a01a578c2c7bb4e587a8f1610843181">11636</a></span><span class="preprocessor">#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk </span></div>
|
||
<div class="line"><a id="l11638" name="l11638"></a><span class="lineno">11638</span><span class="comment">/****************** Bit definition for SPI_TXCRCR register ******************/</span></div>
|
||
<div class="line"><a id="l11639" name="l11639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a0e6e24778c36e45838350d052916d1">11639</a></span><span class="preprocessor">#define SPI_TXCRCR_TXCRC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11640" name="l11640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca1f646ca0bb6ae44744956b39b0702d">11640</a></span><span class="preprocessor">#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) </span></div>
|
||
<div class="line"><a id="l11641" name="l11641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c69dc721e89e40056999b64572dff09">11641</a></span><span class="preprocessor">#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk </span></div>
|
||
<div class="line"><a id="l11643" name="l11643"></a><span class="lineno">11643</span><span class="comment">/****************** Bit definition for SPI_I2SCFGR register *****************/</span></div>
|
||
<div class="line"><a id="l11644" name="l11644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ea301a1a44423c53d2d388a9c7677bd">11644</a></span><span class="preprocessor">#define SPI_I2SCFGR_CHLEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11645" name="l11645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a842b52587ad0e434153bf9df2ecc50">11645</a></span><span class="preprocessor">#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) </span></div>
|
||
<div class="line"><a id="l11646" name="l11646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c362b3d703698a7891f032f6b29056f">11646</a></span><span class="preprocessor">#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk </span></div>
|
||
<div class="line"><a id="l11648" name="l11648"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a60bd1db55a2dfcf20a834e9ad05a66">11648</a></span><span class="preprocessor">#define SPI_I2SCFGR_DATLEN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l11649" name="l11649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbffb30650c0d4c84232813213271169">11649</a></span><span class="preprocessor">#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) </span></div>
|
||
<div class="line"><a id="l11650" name="l11650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc12f9d2003ab169a3f68e9d809f84ae">11650</a></span><span class="preprocessor">#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk </span></div>
|
||
<div class="line"><a id="l11651" name="l11651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa20ad624085d2e533eea3662cb03d8fa">11651</a></span><span class="preprocessor">#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) </span></div>
|
||
<div class="line"><a id="l11652" name="l11652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf6e940d195fa1633cb1b23414f00412">11652</a></span><span class="preprocessor">#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) </span></div>
|
||
<div class="line"><a id="l11654" name="l11654"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bf83ceaefcb4190b2fb5ae09f659d8d">11654</a></span><span class="preprocessor">#define SPI_I2SCFGR_CKPOL_Pos (3U) </span></div>
|
||
<div class="line"><a id="l11655" name="l11655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b3b7c3f4fc9a499410bff94553534f5">11655</a></span><span class="preprocessor">#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) </span></div>
|
||
<div class="line"><a id="l11656" name="l11656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c5be1f1c8b4689643e04cd5034e7f5f">11656</a></span><span class="preprocessor">#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk </span></div>
|
||
<div class="line"><a id="l11658" name="l11658"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d794bb7f4327025db354ad26bf83986">11658</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SSTD_Pos (4U) </span></div>
|
||
<div class="line"><a id="l11659" name="l11659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff08fac3bb90bd73b0bdadddb6a1411a">11659</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) </span></div>
|
||
<div class="line"><a id="l11660" name="l11660"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a822a80be3a51524b42491248f8031f">11660</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk </span></div>
|
||
<div class="line"><a id="l11661" name="l11661"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafeba0a45703463dfe05334364bdacbe8">11661</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) </span></div>
|
||
<div class="line"><a id="l11662" name="l11662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0142a3667f59bce9bae80d31e88a124a">11662</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) </span></div>
|
||
<div class="line"><a id="l11664" name="l11664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf486d8ce50abc465f372b6fcc7a0704d">11664</a></span><span class="preprocessor">#define SPI_I2SCFGR_PCMSYNC_Pos (7U) </span></div>
|
||
<div class="line"><a id="l11665" name="l11665"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeecf52a47dc8d82d6e3d3951c51f4dc1">11665</a></span><span class="preprocessor">#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) </span></div>
|
||
<div class="line"><a id="l11666" name="l11666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66a29efc32a31f903e89b7ddcd20857b">11666</a></span><span class="preprocessor">#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk </span></div>
|
||
<div class="line"><a id="l11668" name="l11668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c7f5184bc8db838c594b07965e81619">11668</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SCFG_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11669" name="l11669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3ca3fbea0bb2c306c0d7f4bcaee8b0d">11669</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) </span></div>
|
||
<div class="line"><a id="l11670" name="l11670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf09fd11f6f97000266b30b015bf2cb68">11670</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk </span></div>
|
||
<div class="line"><a id="l11671" name="l11671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga421c94680ee8a2583419e2b0c89e995e">11671</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) </span></div>
|
||
<div class="line"><a id="l11672" name="l11672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80c398b9e79fcc61a497f9d7dd910352">11672</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) </span></div>
|
||
<div class="line"><a id="l11674" name="l11674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga967de848b594a623b10019d912266ed3">11674</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SE_Pos (10U) </span></div>
|
||
<div class="line"><a id="l11675" name="l11675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafefdd032e0fcf3d4d73f5bf167f74c6b">11675</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) </span></div>
|
||
<div class="line"><a id="l11676" name="l11676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30d76c7552c91bbd5cbac70d9c56ebb3">11676</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk </span></div>
|
||
<div class="line"><a id="l11677" name="l11677"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga443830d47e0ebc5e0141dad4a7d43978">11677</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SMOD_Pos (11U) </span></div>
|
||
<div class="line"><a id="l11678" name="l11678"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa67cab1dd9189de25a0aec2cce90479a">11678</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) </span></div>
|
||
<div class="line"><a id="l11679" name="l11679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae99763414b3c2f11fcfecb1f93eb6701">11679</a></span><span class="preprocessor">#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk </span></div>
|
||
<div class="line"><a id="l11681" name="l11681"></a><span class="lineno">11681</span><span class="comment">/****************** Bit definition for SPI_I2SPR register *******************/</span></div>
|
||
<div class="line"><a id="l11682" name="l11682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab840a9d53e7de5f0de74d20d5e11e0fa">11682</a></span><span class="preprocessor">#define SPI_I2SPR_I2SDIV_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11683" name="l11683"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ae53c9d1c862f377fb76fb253324ac4">11683</a></span><span class="preprocessor">#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) </span></div>
|
||
<div class="line"><a id="l11684" name="l11684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga406ce88b2580a421f5b28bdbeb303543">11684</a></span><span class="preprocessor">#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk </span></div>
|
||
<div class="line"><a id="l11685" name="l11685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabfb7274ed8833e66663a995ca074c1d9">11685</a></span><span class="preprocessor">#define SPI_I2SPR_ODD_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11686" name="l11686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8892fa60c17ea6a9a645671d4d6ffdc">11686</a></span><span class="preprocessor">#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) </span></div>
|
||
<div class="line"><a id="l11687" name="l11687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d6d4136a5ae12f9bd5940324282355a">11687</a></span><span class="preprocessor">#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk </span></div>
|
||
<div class="line"><a id="l11688" name="l11688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1219b3f0097930dd635f434a019d38c6">11688</a></span><span class="preprocessor">#define SPI_I2SPR_MCKOE_Pos (9U) </span></div>
|
||
<div class="line"><a id="l11689" name="l11689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa466ff1b4340cc07fd6362f7bfb173f4">11689</a></span><span class="preprocessor">#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) </span></div>
|
||
<div class="line"><a id="l11690" name="l11690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25669c3686c0c577d2d371ac09200ff0">11690</a></span><span class="preprocessor">#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk </span></div>
|
||
<div class="line"><a id="l11692" name="l11692"></a><span class="lineno">11692</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l11693" name="l11693"></a><span class="lineno">11693</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l11694" name="l11694"></a><span class="lineno">11694</span><span class="comment">/* SYSCFG */</span></div>
|
||
<div class="line"><a id="l11695" name="l11695"></a><span class="lineno">11695</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l11696" name="l11696"></a><span class="lineno">11696</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l11697" name="l11697"></a><span class="lineno">11697</span><span class="comment">/****************** Bit definition for SYSCFG_MEMRMP register ***************/</span></div>
|
||
<div class="line"><a id="l11698" name="l11698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20a445ef41a942b3ec617cfce8297931">11698</a></span><span class="preprocessor">#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11699" name="l11699"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1309dcedba4fee11e085cdfaf974cc3d">11699</a></span><span class="preprocessor">#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) </span></div>
|
||
<div class="line"><a id="l11700" name="l11700"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c05039ec67573c00da29f58b914f258">11700</a></span><span class="preprocessor">#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk </span></div>
|
||
<div class="line"><a id="l11701" name="l11701"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30d5f406535f94faea2e7f924d50201b">11701</a></span><span class="preprocessor">#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) </span></div>
|
||
<div class="line"><a id="l11702" name="l11702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5d76e8b4d801b35c31ef352b33407be">11702</a></span><span class="preprocessor">#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) </span></div>
|
||
<div class="line"><a id="l11703" name="l11703"></a><span class="lineno">11703</span><span class="comment">/****************** Bit definition for SYSCFG_PMC register ******************/</span></div>
|
||
<div class="line"><a id="l11704" name="l11704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f2f7440818b83b95e29d526516e8d27">11704</a></span><span class="preprocessor">#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U) </span></div>
|
||
<div class="line"><a id="l11705" name="l11705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf63c23642e3d3c0f1a2c67f6a60957e1">11705</a></span><span class="preprocessor">#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) </span></div>
|
||
<div class="line"><a id="l11706" name="l11706"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9d8ca35cdab213cb2400c49434de326">11706</a></span><span class="preprocessor">#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk </span></div>
|
||
<div class="line"><a id="l11707" name="l11707"></a><span class="lineno">11707</span><span class="comment">/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */</span></div>
|
||
<div class="line"><a id="l11708" name="l11708"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf7af9191fbf95433bc0a76454118ce9">11708</a></span><span class="preprocessor">#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL </span></div>
|
||
<div class="line"><a id="l11709" name="l11709"></a><span class="lineno">11709</span> </div>
|
||
<div class="line"><a id="l11710" name="l11710"></a><span class="lineno">11710</span><span class="comment">/***************** Bit definition for SYSCFG_EXTICR1 register ***************/</span></div>
|
||
<div class="line"><a id="l11711" name="l11711"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae40db3f75cc81dcb1b6b8c18194d07a8">11711</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11712" name="l11712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c2b219e4d77fac522233905dc0d8de8">11712</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) </span></div>
|
||
<div class="line"><a id="l11713" name="l11713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75b70d07448c3037234bc2abb8e3d884">11713</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk </span></div>
|
||
<div class="line"><a id="l11714" name="l11714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e187825ececb74bc0dc9bb16a22e8af">11714</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_Pos (4U) </span></div>
|
||
<div class="line"><a id="l11715" name="l11715"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac033e65cf79968349e0fa5e52ebf4ccd">11715</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) </span></div>
|
||
<div class="line"><a id="l11716" name="l11716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fc84838c77f799cb7e57d6e97c6c16d">11716</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk </span></div>
|
||
<div class="line"><a id="l11717" name="l11717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga283584ecd69e2dfd310b2b09d1028457">11717</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11718" name="l11718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1383ce11441c048c62e317e78eff0545">11718</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) </span></div>
|
||
<div class="line"><a id="l11719" name="l11719"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d0a0a6b8223777937d8c9012658d6cd">11719</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk </span></div>
|
||
<div class="line"><a id="l11720" name="l11720"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08a505d92a83c5fc8d5d0c8202119f61">11720</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_Pos (12U) </span></div>
|
||
<div class="line"><a id="l11721" name="l11721"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90072fd2defc44f0975836484c9d9bbf">11721</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) </span></div>
|
||
<div class="line"><a id="l11722" name="l11722"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3bf2306f79ebb709da5ecf83e59ded4">11722</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk </span></div>
|
||
<div class="line"><a id="l11726" name="l11726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6de6aa8e32ae5cd07fd69e42e7226bd1">11726</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11727" name="l11727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf43c9ef6b61e39655cbe969967c79a69">11727</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U </span></div>
|
||
<div class="line"><a id="l11728" name="l11728"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga861a4d7b48ffd93997267baaad12fd51">11728</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U </span></div>
|
||
<div class="line"><a id="l11729" name="l11729"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6439042c8cd14f99fe3813cff47c0ee">11729</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U </span></div>
|
||
<div class="line"><a id="l11730" name="l11730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb087e2ded8ac927ee9e1fc0234bfdef">11730</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U </span></div>
|
||
<div class="line"><a id="l11731" name="l11731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa897f1ac8311e57339eaf7813239eaf4">11731</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U </span></div>
|
||
<div class="line"><a id="l11732" name="l11732"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98b2d929e79e5cc2ee7961a75a0ab094">11732</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U </span></div>
|
||
<div class="line"><a id="l11733" name="l11733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga766d0bf3501e207b0baa066cf756688f">11733</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U </span></div>
|
||
<div class="line"><a id="l11734" name="l11734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfc4b69ff5f5d9b35bf01f26d6aa4e60">11734</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U </span></div>
|
||
<div class="line"><a id="l11739" name="l11739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4b78c30e4ef4fa441582eb3c102865d">11739</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11740" name="l11740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19a11fce288d19546c76257483e0dcb6">11740</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U </span></div>
|
||
<div class="line"><a id="l11741" name="l11741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae45a8c814b13fa19f157364dc715c08a">11741</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U </span></div>
|
||
<div class="line"><a id="l11742" name="l11742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93cb136eaf357affc4a28a8d423cabbb">11742</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U </span></div>
|
||
<div class="line"><a id="l11743" name="l11743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f5c3d1e914af78112179a13e9c736d6">11743</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U </span></div>
|
||
<div class="line"><a id="l11744" name="l11744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43ea410456aa31dfe6ec4889de62428b">11744</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U </span></div>
|
||
<div class="line"><a id="l11745" name="l11745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9118efcafa89eeada012ff5ab98387d">11745</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U </span></div>
|
||
<div class="line"><a id="l11746" name="l11746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ac69d7f391e837d8e8adce27704d87d">11746</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U </span></div>
|
||
<div class="line"><a id="l11747" name="l11747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga010784c7bdee3c742b48c500ee52e223">11747</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U </span></div>
|
||
<div class="line"><a id="l11752" name="l11752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4096f472e87e021f4d4c94457ddaf5f1">11752</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11753" name="l11753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cd240d61fd8a9666621f0dee07a08e5">11753</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U </span></div>
|
||
<div class="line"><a id="l11754" name="l11754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03ce7faaf56aa9efcc74af65619e275e">11754</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U </span></div>
|
||
<div class="line"><a id="l11755" name="l11755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc35fcdcc89b487fab2901e1f5a7f41b">11755</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U </span></div>
|
||
<div class="line"><a id="l11756" name="l11756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3f2b7465d81745f7a772e7689a29618">11756</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U </span></div>
|
||
<div class="line"><a id="l11757" name="l11757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab538769f1da056b3f57fb984adeef252">11757</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U </span></div>
|
||
<div class="line"><a id="l11758" name="l11758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe4f5fa56e98b42b64e894f7a9216e05">11758</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U </span></div>
|
||
<div class="line"><a id="l11759" name="l11759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada5ffab92c39cbfc695ce57a4e6177e5">11759</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U </span></div>
|
||
<div class="line"><a id="l11760" name="l11760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00bc1224b7bfd46dcec32676a601de51">11760</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U </span></div>
|
||
<div class="line"><a id="l11765" name="l11765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45ed24773c389f4477944c2c43d106c0">11765</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11766" name="l11766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga652183838bb096717551bf8a1917c257">11766</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U </span></div>
|
||
<div class="line"><a id="l11767" name="l11767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb1809e5b8a9ebc4b1cbc8967d985929">11767</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U </span></div>
|
||
<div class="line"><a id="l11768" name="l11768"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga205440ffa174509d57c2b6a1814f8202">11768</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U </span></div>
|
||
<div class="line"><a id="l11769" name="l11769"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2b33beb6294fd7a257f0f3a36e0dcda">11769</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U </span></div>
|
||
<div class="line"><a id="l11770" name="l11770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40240ee616b6e06ecd8dabe9d8e56e71">11770</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U </span></div>
|
||
<div class="line"><a id="l11771" name="l11771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa73420dbafb7f20f16c350a12b0a0f5">11771</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U </span></div>
|
||
<div class="line"><a id="l11772" name="l11772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae49def2961bf528448a4fbb4aa9c9d94">11772</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U </span></div>
|
||
<div class="line"><a id="l11773" name="l11773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga337e37f58e8710ea8305a16c08e390b9">11773</a></span><span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U </span></div>
|
||
<div class="line"><a id="l11775" name="l11775"></a><span class="lineno">11775</span><span class="comment">/***************** Bit definition for SYSCFG_EXTICR2 register ***************/</span></div>
|
||
<div class="line"><a id="l11776" name="l11776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2d0b453a61771de5591f5eb58ccb174">11776</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11777" name="l11777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf05f6030b07cf7ca730a2ea8325e7640">11777</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) </span></div>
|
||
<div class="line"><a id="l11778" name="l11778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2a57b4872977812e60d521268190e1e">11778</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk </span></div>
|
||
<div class="line"><a id="l11779" name="l11779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade15c38da4f70df1a360337abac37314">11779</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_Pos (4U) </span></div>
|
||
<div class="line"><a id="l11780" name="l11780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa47b595915b1cd571357a04f31c79656">11780</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) </span></div>
|
||
<div class="line"><a id="l11781" name="l11781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6682a1b97b04c5c33085ffd2827ccd17">11781</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk </span></div>
|
||
<div class="line"><a id="l11782" name="l11782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab355e39e166c83c356999c3da7fd7893">11782</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11783" name="l11783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadbcd9e40a5da23a133cd3479d326c66">11783</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) </span></div>
|
||
<div class="line"><a id="l11784" name="l11784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c50caf6019fd7d5038d77e61f57ad7b">11784</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk </span></div>
|
||
<div class="line"><a id="l11785" name="l11785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa503d2cda916e0b9d0f621317c3f1601">11785</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_Pos (12U) </span></div>
|
||
<div class="line"><a id="l11786" name="l11786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97160d2262cb4ab1ae9098809391f52e">11786</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) </span></div>
|
||
<div class="line"><a id="l11787" name="l11787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga638ea3bb014752813d064d37b3388950">11787</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk </span></div>
|
||
<div class="line"><a id="l11792" name="l11792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51147f1747daf48dbcfad03285ae8889">11792</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11793" name="l11793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga917aeb0df688d6b34785085fc85d9e47">11793</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U </span></div>
|
||
<div class="line"><a id="l11794" name="l11794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14ac312beeb19d3bb34a552546477613">11794</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U </span></div>
|
||
<div class="line"><a id="l11795" name="l11795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec62164e18d1b525e8272169b1efe642">11795</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U </span></div>
|
||
<div class="line"><a id="l11796" name="l11796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1d2292b6a856a8a71d82f595b580b9b">11796</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U </span></div>
|
||
<div class="line"><a id="l11797" name="l11797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0adc3c72bddc65977e3ef56df74ed40e">11797</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U </span></div>
|
||
<div class="line"><a id="l11798" name="l11798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5aad8ed8589e28677332ea0b200617b">11798</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U </span></div>
|
||
<div class="line"><a id="l11799" name="l11799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga339f8994c317190a387a96b857aa79d0">11799</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U </span></div>
|
||
<div class="line"><a id="l11800" name="l11800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad36a509bf6deabd5446a07c20964f83">11800</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U </span></div>
|
||
<div class="line"><a id="l11805" name="l11805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb9581c515a4bdf1ed88fe96d8c24794">11805</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11806" name="l11806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90a3f610234dfa13f56e72c76a12be74">11806</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U </span></div>
|
||
<div class="line"><a id="l11807" name="l11807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33b6bdc1b4bfeda0d4034dc67f1a6046">11807</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U </span></div>
|
||
<div class="line"><a id="l11808" name="l11808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0eea392f1530c7cb794a63d04e268a70">11808</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U </span></div>
|
||
<div class="line"><a id="l11809" name="l11809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a4e6644d0144bfb0f913cf20eaf2f8e">11809</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U </span></div>
|
||
<div class="line"><a id="l11810" name="l11810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga740e27c5bead2c914a134ac4ed4d05b3">11810</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U </span></div>
|
||
<div class="line"><a id="l11811" name="l11811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d78839e577ab90090abcdcff88e18c8">11811</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U </span></div>
|
||
<div class="line"><a id="l11812" name="l11812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a06842a64138b5010186d980cb594f9">11812</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U </span></div>
|
||
<div class="line"><a id="l11813" name="l11813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f3c4ebe4d750f89465acd067ab0ee30">11813</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U </span></div>
|
||
<div class="line"><a id="l11818" name="l11818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e87c78fb6dfde7c8b7f81fe3b65aae9">11818</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11819" name="l11819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6528de8e4ca8741e86ae254e1d6b2a70">11819</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U </span></div>
|
||
<div class="line"><a id="l11820" name="l11820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53d8745705d5eb84c70a8554f61d59ac">11820</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U </span></div>
|
||
<div class="line"><a id="l11821" name="l11821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26c97cdece451441e49120e754020cdc">11821</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U </span></div>
|
||
<div class="line"><a id="l11822" name="l11822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga804218f2dd83c72e672143ec4f283ad3">11822</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U </span></div>
|
||
<div class="line"><a id="l11823" name="l11823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d36de53e52c8a4c7991513fec326df6">11823</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U </span></div>
|
||
<div class="line"><a id="l11824" name="l11824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga278997204184bfe7c951c1da327e6fb5">11824</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U </span></div>
|
||
<div class="line"><a id="l11825" name="l11825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga283486dccd660fbf830e8c44b0161a63">11825</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U </span></div>
|
||
<div class="line"><a id="l11826" name="l11826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4222e7d9ed672ea2de3a038c23f9566b">11826</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U </span></div>
|
||
<div class="line"><a id="l11831" name="l11831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f1bfd3af524288b6ce54d7f9aef410a">11831</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11832" name="l11832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab18d324986b18858f901febbcc2a57b7">11832</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U </span></div>
|
||
<div class="line"><a id="l11833" name="l11833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9f53618d9cf13af2b2ecf191da8595a">11833</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U </span></div>
|
||
<div class="line"><a id="l11834" name="l11834"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae38aa3b76227bb8e9d8cedc31c023f63">11834</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U </span></div>
|
||
<div class="line"><a id="l11835" name="l11835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90d097c1b5cbb62dc86327604907dcd4">11835</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U </span></div>
|
||
<div class="line"><a id="l11836" name="l11836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf2c3a661be3569fffe11515e37de1e4">11836</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U </span></div>
|
||
<div class="line"><a id="l11837" name="l11837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga987bc0488e57b14b0a98e4952df2b539">11837</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U </span></div>
|
||
<div class="line"><a id="l11838" name="l11838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0ce56e15f4eb86a3e262deaa845cb99">11838</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U </span></div>
|
||
<div class="line"><a id="l11839" name="l11839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae68ca6758cf36232dd5ac63afae97cbc">11839</a></span><span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U </span></div>
|
||
<div class="line"><a id="l11841" name="l11841"></a><span class="lineno">11841</span><span class="comment">/***************** Bit definition for SYSCFG_EXTICR3 register ***************/</span></div>
|
||
<div class="line"><a id="l11842" name="l11842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e1169e4f50e721a7c6b9d9c2b722035">11842</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11843" name="l11843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab693b7e686ba5646959113dd6b408673">11843</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) </span></div>
|
||
<div class="line"><a id="l11844" name="l11844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2a656b18cc728e38acb72cf8d7e7935">11844</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk </span></div>
|
||
<div class="line"><a id="l11845" name="l11845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f6d994a483df2e705db0343cb88fb53">11845</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_Pos (4U) </span></div>
|
||
<div class="line"><a id="l11846" name="l11846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ea1b3c5cb074a305ad06709a7023689">11846</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) </span></div>
|
||
<div class="line"><a id="l11847" name="l11847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga002462e4c233adc6dd502de726994575">11847</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk </span></div>
|
||
<div class="line"><a id="l11848" name="l11848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d6efb981e6435ae15643e438196ffba">11848</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11849" name="l11849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1803c2719fb53533547496e02c8b07d4">11849</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) </span></div>
|
||
<div class="line"><a id="l11850" name="l11850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fc06b17c3b3d393b749bf9924a43a80">11850</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk </span></div>
|
||
<div class="line"><a id="l11851" name="l11851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29b9c2241040cf831bbb18391cda402c">11851</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_Pos (12U) </span></div>
|
||
<div class="line"><a id="l11852" name="l11852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c7d37c95e30bf30ac80d455bfa9a842">11852</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) </span></div>
|
||
<div class="line"><a id="l11853" name="l11853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa66cc9a579696c8f5c41f5f138ee1e67">11853</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk </span></div>
|
||
<div class="line"><a id="l11858" name="l11858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1c6843a871f1a06ca25c0de50048b10">11858</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11859" name="l11859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4818dc7bffc8dfc2acc48995a62e66c5">11859</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U </span></div>
|
||
<div class="line"><a id="l11860" name="l11860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba0d34ff57632d7753981404cef548e2">11860</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U </span></div>
|
||
<div class="line"><a id="l11861" name="l11861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa15260ba354dee354f0a71e7913009c3">11861</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U </span></div>
|
||
<div class="line"><a id="l11862" name="l11862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga185287204b8cead31d3760f65c5ca19d">11862</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U </span></div>
|
||
<div class="line"><a id="l11863" name="l11863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga425e41001af4b205b8fbfba723572a81">11863</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U </span></div>
|
||
<div class="line"><a id="l11864" name="l11864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ecc7a12103b805da045093eb626614d">11864</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U </span></div>
|
||
<div class="line"><a id="l11865" name="l11865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bf3fc7a2e35b7cbb9f08f2e3b06a3c4">11865</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U </span></div>
|
||
<div class="line"><a id="l11866" name="l11866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0b679636c97041f5584012c78f6d7a3">11866</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U </span></div>
|
||
<div class="line"><a id="l11871" name="l11871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93e284e59c4ff887b2e79851ac0a81c4">11871</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11872" name="l11872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9271cbc1ed09774a5fef4b379cab260">11872</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U </span></div>
|
||
<div class="line"><a id="l11873" name="l11873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cc355176941881870c620c0837cab48">11873</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U </span></div>
|
||
<div class="line"><a id="l11874" name="l11874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75af3c7a94cfc78361c94b054f9fe064">11874</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U </span></div>
|
||
<div class="line"><a id="l11875" name="l11875"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafce176ef4b389251dadb98d9f59f8fe6">11875</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U </span></div>
|
||
<div class="line"><a id="l11876" name="l11876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76ef2422b4d021d0cc038cb6325ed311">11876</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U </span></div>
|
||
<div class="line"><a id="l11877" name="l11877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1b37bf746ccfe0750aebd28cfa52a0c">11877</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U </span></div>
|
||
<div class="line"><a id="l11878" name="l11878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31fdedc4a90328881fe8817f4eef61b2">11878</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U </span></div>
|
||
<div class="line"><a id="l11879" name="l11879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cd8a0da1b9ede601094f6c651a499e4">11879</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U </span></div>
|
||
<div class="line"><a id="l11884" name="l11884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25acdbb9e916c440c41a060d861130ee">11884</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11885" name="l11885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8d9aec4349bf38a4a9753b267b7de7e">11885</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U </span></div>
|
||
<div class="line"><a id="l11886" name="l11886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62d2b81d49e30ab4fe96572be5da8484">11886</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U </span></div>
|
||
<div class="line"><a id="l11887" name="l11887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab3553c540cd836d465824939c2e3b79">11887</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U </span></div>
|
||
<div class="line"><a id="l11888" name="l11888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabde568ef1c8f4bfaf18954e8ee0716a9">11888</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U </span></div>
|
||
<div class="line"><a id="l11889" name="l11889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09ed841a11367cda67c7a416ed6d9b99">11889</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U </span></div>
|
||
<div class="line"><a id="l11890" name="l11890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6dff840a6986b440e7633a3671ce57cc">11890</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U </span></div>
|
||
<div class="line"><a id="l11891" name="l11891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga791e7d2bd23ae969540e5509c6718255">11891</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U </span></div>
|
||
<div class="line"><a id="l11892" name="l11892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8bee76cf4bed88ff7b51145393b2cd19">11892</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U </span></div>
|
||
<div class="line"><a id="l11897" name="l11897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ca8a85d4512677eff6ed2aac897a366">11897</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11898" name="l11898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedb3a8cc6b1763e303986553c0e4e7f8">11898</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U </span></div>
|
||
<div class="line"><a id="l11899" name="l11899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b01c8ba6cb27899a4f5fa494bf2b3f5">11899</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U </span></div>
|
||
<div class="line"><a id="l11900" name="l11900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a69d636cda0352da0982c54f582787d">11900</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U </span></div>
|
||
<div class="line"><a id="l11901" name="l11901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44affe06868a0490f8d0cbbba51ff412">11901</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U </span></div>
|
||
<div class="line"><a id="l11902" name="l11902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66fb050835077047b576b3a510700d64">11902</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U </span></div>
|
||
<div class="line"><a id="l11903" name="l11903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7b66390eeb4a8d50ebb7e87e2f281b3">11903</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U </span></div>
|
||
<div class="line"><a id="l11904" name="l11904"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa58cfe5d03072c259582ba8fefa322bf">11904</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U </span></div>
|
||
<div class="line"><a id="l11905" name="l11905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafadb14df8764208abeeaf6197489f1b4">11905</a></span><span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U </span></div>
|
||
<div class="line"><a id="l11907" name="l11907"></a><span class="lineno">11907</span><span class="comment">/***************** Bit definition for SYSCFG_EXTICR4 register ***************/</span></div>
|
||
<div class="line"><a id="l11908" name="l11908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81bcb273eca8dad24924a1402c31411e">11908</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11909" name="l11909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabcd55b42c6aa84cdd8c36d7df16fcf5">11909</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) </span></div>
|
||
<div class="line"><a id="l11910" name="l11910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d4b31f4a75d935b6a52afe6a16463d1">11910</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk </span></div>
|
||
<div class="line"><a id="l11911" name="l11911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09cc7a3ec956c6849e56f0deb4bf94cc">11911</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_Pos (4U) </span></div>
|
||
<div class="line"><a id="l11912" name="l11912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafaf1614a726586aeefae87ca1d803656">11912</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) </span></div>
|
||
<div class="line"><a id="l11913" name="l11913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f04cda5bfe876431d5ad864302d7fa1">11913</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk </span></div>
|
||
<div class="line"><a id="l11914" name="l11914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga525a67279d0e7f222fd770de959a96d5">11914</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11915" name="l11915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95bb6740c8bc08eb716e3ef71841e81a">11915</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) </span></div>
|
||
<div class="line"><a id="l11916" name="l11916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabde06df3ec6e357374820a5a615991aa">11916</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk </span></div>
|
||
<div class="line"><a id="l11917" name="l11917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2d829ebf74fc207970f57a960bd8b4a">11917</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_Pos (12U) </span></div>
|
||
<div class="line"><a id="l11918" name="l11918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08ef44dcc2fb1d5cb2fab3ca7eb1a45a">11918</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) </span></div>
|
||
<div class="line"><a id="l11919" name="l11919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd325c27cff1ae3de773d5e205a33f4e">11919</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk </span></div>
|
||
<div class="line"><a id="l11924" name="l11924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ceaa63866465faa8145ce0c5d9a44d0">11924</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11925" name="l11925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8b00a462533a83c75c588340a2fa710">11925</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U </span></div>
|
||
<div class="line"><a id="l11926" name="l11926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d27668b1fa6b1accde06aa144faa970">11926</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U </span></div>
|
||
<div class="line"><a id="l11927" name="l11927"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa46ddd43a361d82abcb3cb7779ac74ff">11927</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U </span></div>
|
||
<div class="line"><a id="l11928" name="l11928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga102ee111e27fd67228c169836dd0849e">11928</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U </span></div>
|
||
<div class="line"><a id="l11929" name="l11929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9785209e7e13fcf9c4f82d57bae0837">11929</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U </span></div>
|
||
<div class="line"><a id="l11930" name="l11930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c78af5f130089bec32d6f782288765c">11930</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U </span></div>
|
||
<div class="line"><a id="l11931" name="l11931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b7baa5b844b78d3e05326607b2910a6">11931</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U </span></div>
|
||
<div class="line"><a id="l11936" name="l11936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0514aaa894c9be44ba47c1346756f90b">11936</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11937" name="l11937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34e6776e3ebfecc9e78c5aec77c48eff">11937</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U </span></div>
|
||
<div class="line"><a id="l11938" name="l11938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c7833d4e3c6b7f3878f62a200a6ab14">11938</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U </span></div>
|
||
<div class="line"><a id="l11939" name="l11939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabed530f628b3c37281f7a583af1cdb3c">11939</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U </span></div>
|
||
<div class="line"><a id="l11940" name="l11940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7dc5424bf39509a989464a81ec0714da">11940</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U </span></div>
|
||
<div class="line"><a id="l11941" name="l11941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf4c995587d7bae6436e6793b8214627">11941</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U </span></div>
|
||
<div class="line"><a id="l11942" name="l11942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dedb6adbf49c40e5a15ad2afc471155">11942</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U </span></div>
|
||
<div class="line"><a id="l11943" name="l11943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61214ec3d87450f54b959aab49ea65b6">11943</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U </span></div>
|
||
<div class="line"><a id="l11948" name="l11948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ad140a68e3e4e0406a182a504679ea9">11948</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11949" name="l11949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5c1b8a0f2b4f79bd868bbb2b4eff617">11949</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U </span></div>
|
||
<div class="line"><a id="l11950" name="l11950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ca668cdd447acb1740566f46de5eb19">11950</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U </span></div>
|
||
<div class="line"><a id="l11951" name="l11951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f20b2bfa9dc8b57a987c127c6dfa6fe">11951</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U </span></div>
|
||
<div class="line"><a id="l11952" name="l11952"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c13c49f6d93865ba05361cd86fddabf">11952</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U </span></div>
|
||
<div class="line"><a id="l11953" name="l11953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9df1ee6f60db93301acaa9220a591da9">11953</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U </span></div>
|
||
<div class="line"><a id="l11954" name="l11954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8ae4d091bb2c7148188ef430734020a">11954</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U </span></div>
|
||
<div class="line"><a id="l11955" name="l11955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07b38f38fa3957c6bc45ef4282b58377">11955</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U </span></div>
|
||
<div class="line"><a id="l11960" name="l11960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2f28920677dd99f9132ed28f7b1d5e2">11960</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U </span></div>
|
||
<div class="line"><a id="l11961" name="l11961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga412f44d6a8f8f60420d7e7f8b5635e09">11961</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U </span></div>
|
||
<div class="line"><a id="l11962" name="l11962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49778592caef3a176ee82c9b83e25148">11962</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U </span></div>
|
||
<div class="line"><a id="l11963" name="l11963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac23e07d92a68cf7f8c3e58b479638885">11963</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U </span></div>
|
||
<div class="line"><a id="l11964" name="l11964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefd64bc0ea005d03068f2e9b8f425944">11964</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U </span></div>
|
||
<div class="line"><a id="l11965" name="l11965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e88d51ebabe9f70e5b7c2ad60899d54">11965</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U </span></div>
|
||
<div class="line"><a id="l11966" name="l11966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51d341c45e98ccbd82bf7003bfa56e6b">11966</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U </span></div>
|
||
<div class="line"><a id="l11967" name="l11967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga701c1065ec215a34329017bae69046c3">11967</a></span><span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U </span></div>
|
||
<div class="line"><a id="l11969" name="l11969"></a><span class="lineno">11969</span><span class="comment">/****************** Bit definition for SYSCFG_CMPCR register ****************/</span></div>
|
||
<div class="line"><a id="l11970" name="l11970"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1747204ad5b1221e47a6610e46790e9">11970</a></span><span class="preprocessor">#define SYSCFG_CMPCR_CMP_PD_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11971" name="l11971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ff39240a251120eebbc18e4955be5db">11971</a></span><span class="preprocessor">#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) </span></div>
|
||
<div class="line"><a id="l11972" name="l11972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga261292a3a7ca1f767915b2e2ec3a7806">11972</a></span><span class="preprocessor">#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk </span></div>
|
||
<div class="line"><a id="l11973" name="l11973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d5884039c7c13bdef0f45090f48e275">11973</a></span><span class="preprocessor">#define SYSCFG_CMPCR_READY_Pos (8U) </span></div>
|
||
<div class="line"><a id="l11974" name="l11974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4d9717bd2df4c0742d09a2db4caa1ea">11974</a></span><span class="preprocessor">#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) </span></div>
|
||
<div class="line"><a id="l11975" name="l11975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae16bcca9b727e68f11467b6b3dad6215">11975</a></span><span class="preprocessor">#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk </span></div>
|
||
<div class="line"><a id="l11977" name="l11977"></a><span class="lineno">11977</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l11978" name="l11978"></a><span class="lineno">11978</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l11979" name="l11979"></a><span class="lineno">11979</span><span class="comment">/* TIM */</span></div>
|
||
<div class="line"><a id="l11980" name="l11980"></a><span class="lineno">11980</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l11981" name="l11981"></a><span class="lineno">11981</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l11982" name="l11982"></a><span class="lineno">11982</span><span class="comment">/******************* Bit definition for TIM_CR1 register ********************/</span></div>
|
||
<div class="line"><a id="l11983" name="l11983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9cdca91d88f73215ab00bc9a84938584">11983</a></span><span class="preprocessor">#define TIM_CR1_CEN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l11984" name="l11984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab39f58b244f6d1eb12be39b714e434e5">11984</a></span><span class="preprocessor">#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) </span></div>
|
||
<div class="line"><a id="l11985" name="l11985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93d86355e5e3b399ed45e1ca83abed2a">11985</a></span><span class="preprocessor">#define TIM_CR1_CEN TIM_CR1_CEN_Msk </span></div>
|
||
<div class="line"><a id="l11986" name="l11986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga014a0f9d40c6a34b7fdf70bd8908d14d">11986</a></span><span class="preprocessor">#define TIM_CR1_UDIS_Pos (1U) </span></div>
|
||
<div class="line"><a id="l11987" name="l11987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab930af301c357d666089faef3fe38982">11987</a></span><span class="preprocessor">#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) </span></div>
|
||
<div class="line"><a id="l11988" name="l11988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4f2a9f0cf7b60e3c623af451f141f3c">11988</a></span><span class="preprocessor">#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk </span></div>
|
||
<div class="line"><a id="l11989" name="l11989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa68d9cdf8e673e01035272fa228ab239">11989</a></span><span class="preprocessor">#define TIM_CR1_URS_Pos (2U) </span></div>
|
||
<div class="line"><a id="l11990" name="l11990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86b7788d2996e1a0b729c23f6c01df18">11990</a></span><span class="preprocessor">#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) </span></div>
|
||
<div class="line"><a id="l11991" name="l11991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06c997c2c23e8bef7ca07579762c113b">11991</a></span><span class="preprocessor">#define TIM_CR1_URS TIM_CR1_URS_Msk </span></div>
|
||
<div class="line"><a id="l11992" name="l11992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cae3644294078a1a12ac19f86ece98e">11992</a></span><span class="preprocessor">#define TIM_CR1_OPM_Pos (3U) </span></div>
|
||
<div class="line"><a id="l11993" name="l11993"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fbbf98af8ecd146d7eae1874c0f115a">11993</a></span><span class="preprocessor">#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) </span></div>
|
||
<div class="line"><a id="l11994" name="l11994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d3d1488296350af6d36fbbf71905d29">11994</a></span><span class="preprocessor">#define TIM_CR1_OPM TIM_CR1_OPM_Msk </span></div>
|
||
<div class="line"><a id="l11995" name="l11995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga161776b682c51f69581800125bf89a48">11995</a></span><span class="preprocessor">#define TIM_CR1_DIR_Pos (4U) </span></div>
|
||
<div class="line"><a id="l11996" name="l11996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5f92c5c62905feea73880ccbf6836aa">11996</a></span><span class="preprocessor">#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) </span></div>
|
||
<div class="line"><a id="l11997" name="l11997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacea10770904af189f3aaeb97b45722aa">11997</a></span><span class="preprocessor">#define TIM_CR1_DIR TIM_CR1_DIR_Msk </span></div>
|
||
<div class="line"><a id="l11999" name="l11999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8f425763d1d4c1483ca41a34cda2b2a">11999</a></span><span class="preprocessor">#define TIM_CR1_CMS_Pos (5U) </span></div>
|
||
<div class="line"><a id="l12000" name="l12000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee4916455eb6d08d131dd9ae5b8013ee">12000</a></span><span class="preprocessor">#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) </span></div>
|
||
<div class="line"><a id="l12001" name="l12001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga352b3c389bde13dd6049de0afdd874f1">12001</a></span><span class="preprocessor">#define TIM_CR1_CMS TIM_CR1_CMS_Msk </span></div>
|
||
<div class="line"><a id="l12002" name="l12002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83ca6f7810aba73dc8c12f22092d97a2">12002</a></span><span class="preprocessor">#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) </span></div>
|
||
<div class="line"><a id="l12003" name="l12003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3ee4adcde3c001d3b97d2eae1730ea9">12003</a></span><span class="preprocessor">#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) </span></div>
|
||
<div class="line"><a id="l12005" name="l12005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga517317561e18e823ac75a35ae05b2c29">12005</a></span><span class="preprocessor">#define TIM_CR1_ARPE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12006" name="l12006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e508ecc8ac453c2999b2ca7885f24a8">12006</a></span><span class="preprocessor">#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) </span></div>
|
||
<div class="line"><a id="l12007" name="l12007"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a3ad409f6b147cdcbafbfe29102f3fd">12007</a></span><span class="preprocessor">#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk </span></div>
|
||
<div class="line"><a id="l12009" name="l12009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee3940e6580a2f924894f6f2f80ca856">12009</a></span><span class="preprocessor">#define TIM_CR1_CKD_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12010" name="l12010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0894ca61f67f8ce59882c5a9645f68bd">12010</a></span><span class="preprocessor">#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) </span></div>
|
||
<div class="line"><a id="l12011" name="l12011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacacc4ff7e5b75fd2e4e6b672ccd33a72">12011</a></span><span class="preprocessor">#define TIM_CR1_CKD TIM_CR1_CKD_Msk </span></div>
|
||
<div class="line"><a id="l12012" name="l12012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga458d536d82aa3db7d227b0f00b36808f">12012</a></span><span class="preprocessor">#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) </span></div>
|
||
<div class="line"><a id="l12013" name="l12013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ff2d6c2c350e8b719a8ad49c9a6bcbe">12013</a></span><span class="preprocessor">#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) </span></div>
|
||
<div class="line"><a id="l12015" name="l12015"></a><span class="lineno">12015</span><span class="comment">/******************* Bit definition for TIM_CR2 register ********************/</span></div>
|
||
<div class="line"><a id="l12016" name="l12016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86a631cdfa58f91c731b709e27ee6d0d">12016</a></span><span class="preprocessor">#define TIM_CR2_CCPC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12017" name="l12017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ccf78eb52ea83a81ed28e4815860df9">12017</a></span><span class="preprocessor">#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) </span></div>
|
||
<div class="line"><a id="l12018" name="l12018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae22c9c1197107d6fa629f419a29541e">12018</a></span><span class="preprocessor">#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk </span></div>
|
||
<div class="line"><a id="l12019" name="l12019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga944661589a5e77ab328c5df5569d967a">12019</a></span><span class="preprocessor">#define TIM_CR2_CCUS_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12020" name="l12020"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac9908b05b59b90ba3e42124e7ad4347">12020</a></span><span class="preprocessor">#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) </span></div>
|
||
<div class="line"><a id="l12021" name="l12021"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0328c1339b2b1633ef7a8db4c02d0d5">12021</a></span><span class="preprocessor">#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk </span></div>
|
||
<div class="line"><a id="l12022" name="l12022"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga159a232ac14d50dc779712b5917e2ab5">12022</a></span><span class="preprocessor">#define TIM_CR2_CCDS_Pos (3U) </span></div>
|
||
<div class="line"><a id="l12023" name="l12023"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57abe8dfa0dc138ec4c9f4b0dd72299b">12023</a></span><span class="preprocessor">#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) </span></div>
|
||
<div class="line"><a id="l12024" name="l12024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade656832d3ec303a2a7a422638dd560e">12024</a></span><span class="preprocessor">#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk </span></div>
|
||
<div class="line"><a id="l12026" name="l12026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e8f8be33b5a8e48b67524b93e521a91">12026</a></span><span class="preprocessor">#define TIM_CR2_MMS_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12027" name="l12027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f6c31bf38844218cb8c8ee98aef46c4">12027</a></span><span class="preprocessor">#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) </span></div>
|
||
<div class="line"><a id="l12028" name="l12028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa6987d980e5c4c71c7d0faa1eb97a45">12028</a></span><span class="preprocessor">#define TIM_CR2_MMS TIM_CR2_MMS_Msk </span></div>
|
||
<div class="line"><a id="l12029" name="l12029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3e55308e84106d6501201e66bd46ab6">12029</a></span><span class="preprocessor">#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) </span></div>
|
||
<div class="line"><a id="l12030" name="l12030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b1036929b0a4ba5bd5cced9b8e0f4c3">12030</a></span><span class="preprocessor">#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) </span></div>
|
||
<div class="line"><a id="l12031" name="l12031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb74a815afdd856d51cfcf1ddf3fce6a">12031</a></span><span class="preprocessor">#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) </span></div>
|
||
<div class="line"><a id="l12033" name="l12033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga493bce1bb3c1243de9e4a9069c261e54">12033</a></span><span class="preprocessor">#define TIM_CR2_TI1S_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12034" name="l12034"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5aef7ed878a1f55f901cfdb25d3842ed">12034</a></span><span class="preprocessor">#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) </span></div>
|
||
<div class="line"><a id="l12035" name="l12035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad07504497b70af628fa1aee8fe7ef63c">12035</a></span><span class="preprocessor">#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk </span></div>
|
||
<div class="line"><a id="l12036" name="l12036"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5a3877d7270c1ddf25da016cc40ed21">12036</a></span><span class="preprocessor">#define TIM_CR2_OIS1_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12037" name="l12037"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a08d73020c32fdaa4cc403f234792b1">12037</a></span><span class="preprocessor">#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) </span></div>
|
||
<div class="line"><a id="l12038" name="l12038"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31b26bf058f88d771c33aff85ec89358">12038</a></span><span class="preprocessor">#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk </span></div>
|
||
<div class="line"><a id="l12039" name="l12039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga820e5a3fe5cf4265bc144c8bd697d839">12039</a></span><span class="preprocessor">#define TIM_CR2_OIS1N_Pos (9U) </span></div>
|
||
<div class="line"><a id="l12040" name="l12040"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga146f505a2802837aa5799069416206bc">12040</a></span><span class="preprocessor">#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) </span></div>
|
||
<div class="line"><a id="l12041" name="l12041"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae61f8d54923999fffb6db381e81f2b69">12041</a></span><span class="preprocessor">#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk </span></div>
|
||
<div class="line"><a id="l12042" name="l12042"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7e01ac6a03a0903067f24c11540e2f0">12042</a></span><span class="preprocessor">#define TIM_CR2_OIS2_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12043" name="l12043"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb2bd7f9b2666aa8205981e1c7ddb446">12043</a></span><span class="preprocessor">#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) </span></div>
|
||
<div class="line"><a id="l12044" name="l12044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61467648a433bd887683b9a4760021fa">12044</a></span><span class="preprocessor">#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk </span></div>
|
||
<div class="line"><a id="l12045" name="l12045"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60d70395acf83574da7c53ca126bdd4d">12045</a></span><span class="preprocessor">#define TIM_CR2_OIS2N_Pos (11U) </span></div>
|
||
<div class="line"><a id="l12046" name="l12046"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga831140b7e39cda6b158041797be1ed37">12046</a></span><span class="preprocessor">#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) </span></div>
|
||
<div class="line"><a id="l12047" name="l12047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga769146db660b832f3ef26f892b567bd4">12047</a></span><span class="preprocessor">#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk </span></div>
|
||
<div class="line"><a id="l12048" name="l12048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf56da9ea6f82692b87573a45abab7447">12048</a></span><span class="preprocessor">#define TIM_CR2_OIS3_Pos (12U) </span></div>
|
||
<div class="line"><a id="l12049" name="l12049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d5376e0d45eef0125cf133db5a7189a">12049</a></span><span class="preprocessor">#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) </span></div>
|
||
<div class="line"><a id="l12050" name="l12050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad974d7c91edf6f1bd47e892b3b6f7565">12050</a></span><span class="preprocessor">#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk </span></div>
|
||
<div class="line"><a id="l12051" name="l12051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0849600336151b9eb3a0b405913bdd96">12051</a></span><span class="preprocessor">#define TIM_CR2_OIS3N_Pos (13U) </span></div>
|
||
<div class="line"><a id="l12052" name="l12052"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1c25a6a16e1d0e6e3ae26eac52d8e08">12052</a></span><span class="preprocessor">#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) </span></div>
|
||
<div class="line"><a id="l12053" name="l12053"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20fb9b62a7e8d114fbd180abd9f8ceae">12053</a></span><span class="preprocessor">#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk </span></div>
|
||
<div class="line"><a id="l12054" name="l12054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab672f9b97f3346360d6d740328a780f7">12054</a></span><span class="preprocessor">#define TIM_CR2_OIS4_Pos (14U) </span></div>
|
||
<div class="line"><a id="l12055" name="l12055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8644bc052bc6251ddf877b79a2ef6f48">12055</a></span><span class="preprocessor">#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) </span></div>
|
||
<div class="line"><a id="l12056" name="l12056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad644f2f4b26e46587abedc8d3164e56e">12056</a></span><span class="preprocessor">#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk </span></div>
|
||
<div class="line"><a id="l12058" name="l12058"></a><span class="lineno">12058</span><span class="comment">/******************* Bit definition for TIM_SMCR register *******************/</span></div>
|
||
<div class="line"><a id="l12059" name="l12059"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40905e02ce0cff7e929a9e78e7f46bcb">12059</a></span><span class="preprocessor">#define TIM_SMCR_SMS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12060" name="l12060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34db507d082a38eb597b9a27bb659ace">12060</a></span><span class="preprocessor">#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) </span></div>
|
||
<div class="line"><a id="l12061" name="l12061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae92349731a6107e0f3a251b44a67c7ea">12061</a></span><span class="preprocessor">#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk </span></div>
|
||
<div class="line"><a id="l12062" name="l12062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d1ebece401aeb12abd466d2eafa78b2">12062</a></span><span class="preprocessor">#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) </span></div>
|
||
<div class="line"><a id="l12063" name="l12063"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa980a3121ab6cda5a4a42b959da8421e">12063</a></span><span class="preprocessor">#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) </span></div>
|
||
<div class="line"><a id="l12064" name="l12064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63847fc3c71f582403e6301b1229c3ed">12064</a></span><span class="preprocessor">#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) </span></div>
|
||
<div class="line"><a id="l12066" name="l12066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcaa765c40260187fc144e9e8138cc4b">12066</a></span><span class="preprocessor">#define TIM_SMCR_TS_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12067" name="l12067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2aa1e898f53a002c3bddaa336e8888b1">12067</a></span><span class="preprocessor">#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) </span></div>
|
||
<div class="line"><a id="l12068" name="l12068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8680e719bca2b672d850504220ae51fc">12068</a></span><span class="preprocessor">#define TIM_SMCR_TS TIM_SMCR_TS_Msk </span></div>
|
||
<div class="line"><a id="l12069" name="l12069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96">12069</a></span><span class="preprocessor">#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) </span></div>
|
||
<div class="line"><a id="l12070" name="l12070"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d">12070</a></span><span class="preprocessor">#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) </span></div>
|
||
<div class="line"><a id="l12071" name="l12071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8">12071</a></span><span class="preprocessor">#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) </span></div>
|
||
<div class="line"><a id="l12073" name="l12073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga904f429175a5ab1cfb78af1487d8b187">12073</a></span><span class="preprocessor">#define TIM_SMCR_MSM_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12074" name="l12074"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafba3fb13f79aeb124c0f496bef33e4b2">12074</a></span><span class="preprocessor">#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) </span></div>
|
||
<div class="line"><a id="l12075" name="l12075"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52101db4ca2c7b3003f1b16a49b2032c">12075</a></span><span class="preprocessor">#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk </span></div>
|
||
<div class="line"><a id="l12077" name="l12077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbb493ebc2ecb4f3759eb97f9496a1dd">12077</a></span><span class="preprocessor">#define TIM_SMCR_ETF_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12078" name="l12078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga423e64cbb40275055b1b92a6d3ab0a12">12078</a></span><span class="preprocessor">#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) </span></div>
|
||
<div class="line"><a id="l12079" name="l12079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2ed8b32d9eb8eea251bd1dac4f34668">12079</a></span><span class="preprocessor">#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk </span></div>
|
||
<div class="line"><a id="l12080" name="l12080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43745c2894cfc1e5ee619ac85d8d5a62">12080</a></span><span class="preprocessor">#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) </span></div>
|
||
<div class="line"><a id="l12081" name="l12081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga661e6cce23553cf0ad3a60d8573b9a2c">12081</a></span><span class="preprocessor">#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) </span></div>
|
||
<div class="line"><a id="l12082" name="l12082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb5528381fb64ffbcc719de478391ae2">12082</a></span><span class="preprocessor">#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) </span></div>
|
||
<div class="line"><a id="l12083" name="l12083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6082700946fc61a6f9d6209e258fcc14">12083</a></span><span class="preprocessor">#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) </span></div>
|
||
<div class="line"><a id="l12085" name="l12085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0f059d7026ed8c8b644ec62d416323b">12085</a></span><span class="preprocessor">#define TIM_SMCR_ETPS_Pos (12U) </span></div>
|
||
<div class="line"><a id="l12086" name="l12086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab319df2e386dc55f421f20a7f4c8a5d4">12086</a></span><span class="preprocessor">#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) </span></div>
|
||
<div class="line"><a id="l12087" name="l12087"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ebb9e631876435e276211d88e797386">12087</a></span><span class="preprocessor">#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk </span></div>
|
||
<div class="line"><a id="l12088" name="l12088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00b43cd09557a69ed10471ed76b228d8">12088</a></span><span class="preprocessor">#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) </span></div>
|
||
<div class="line"><a id="l12089" name="l12089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf12f04862dbc92ca238d1518b27b16b">12089</a></span><span class="preprocessor">#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) </span></div>
|
||
<div class="line"><a id="l12091" name="l12091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaef2d4adcfd438a4d19ea54ef7031ed0">12091</a></span><span class="preprocessor">#define TIM_SMCR_ECE_Pos (14U) </span></div>
|
||
<div class="line"><a id="l12092" name="l12092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7322ee5f5ebf6e9c70b7ffe4afe1fa3d">12092</a></span><span class="preprocessor">#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) </span></div>
|
||
<div class="line"><a id="l12093" name="l12093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga331a1d5f39d5f47b5409054e693fc651">12093</a></span><span class="preprocessor">#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk </span></div>
|
||
<div class="line"><a id="l12094" name="l12094"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada5b5864ba9fe393be0bcd168e3cf439">12094</a></span><span class="preprocessor">#define TIM_SMCR_ETP_Pos (15U) </span></div>
|
||
<div class="line"><a id="l12095" name="l12095"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77f8984e6ac3422454b0a586a2b973e3">12095</a></span><span class="preprocessor">#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) </span></div>
|
||
<div class="line"><a id="l12096" name="l12096"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a5f335c3d7a4f82d1e91dc1511e3322">12096</a></span><span class="preprocessor">#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk </span></div>
|
||
<div class="line"><a id="l12098" name="l12098"></a><span class="lineno">12098</span><span class="comment">/******************* Bit definition for TIM_DIER register *******************/</span></div>
|
||
<div class="line"><a id="l12099" name="l12099"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga177019595c3a462255e7ea4a64cde2a6">12099</a></span><span class="preprocessor">#define TIM_DIER_UIE_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12100" name="l12100"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab47c8f36981860ff345f922f6ba02662">12100</a></span><span class="preprocessor">#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) </span></div>
|
||
<div class="line"><a id="l12101" name="l12101"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c6d3e0495e6c06da4bdd0ad8995a32b">12101</a></span><span class="preprocessor">#define TIM_DIER_UIE TIM_DIER_UIE_Msk </span></div>
|
||
<div class="line"><a id="l12102" name="l12102"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ca1de767246ce92802bca84ae436364">12102</a></span><span class="preprocessor">#define TIM_DIER_CC1IE_Pos (1U) </span></div>
|
||
<div class="line"><a id="l12103" name="l12103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9cdfb1dc6e58a5f1ba2e4379b02f8be7">12103</a></span><span class="preprocessor">#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) </span></div>
|
||
<div class="line"><a id="l12104" name="l12104"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ba7f7ca97eeaf6cc23cd6765c6bf678">12104</a></span><span class="preprocessor">#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk </span></div>
|
||
<div class="line"><a id="l12105" name="l12105"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5dcc06e124f3980a1d8a949787acc90">12105</a></span><span class="preprocessor">#define TIM_DIER_CC2IE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12106" name="l12106"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5db58d01a8e92e3403fb44ecc09e5e5e">12106</a></span><span class="preprocessor">#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) </span></div>
|
||
<div class="line"><a id="l12107" name="l12107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga757c59b690770adebf33e20d3d9dec15">12107</a></span><span class="preprocessor">#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk </span></div>
|
||
<div class="line"><a id="l12108" name="l12108"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3a26f9fd83be5be909cdbbf59fb138d">12108</a></span><span class="preprocessor">#define TIM_DIER_CC3IE_Pos (3U) </span></div>
|
||
<div class="line"><a id="l12109" name="l12109"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78bd5f90a0f2d2d34132ef5568e18779">12109</a></span><span class="preprocessor">#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) </span></div>
|
||
<div class="line"><a id="l12110" name="l12110"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4edf003f04bcf250bddf5ed284201c2e">12110</a></span><span class="preprocessor">#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk </span></div>
|
||
<div class="line"><a id="l12111" name="l12111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac98032297756f6e341f92fa243278e98">12111</a></span><span class="preprocessor">#define TIM_DIER_CC4IE_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12112" name="l12112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66b5230621c6d2f44c44ff672a07ffaf">12112</a></span><span class="preprocessor">#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) </span></div>
|
||
<div class="line"><a id="l12113" name="l12113"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ad0f562a014572793b49fe87184338b">12113</a></span><span class="preprocessor">#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk </span></div>
|
||
<div class="line"><a id="l12114" name="l12114"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f87983f6cb8450b975286079c19ff29">12114</a></span><span class="preprocessor">#define TIM_DIER_COMIE_Pos (5U) </span></div>
|
||
<div class="line"><a id="l12115" name="l12115"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe9af339214666b3251fff9598277b1f">12115</a></span><span class="preprocessor">#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) </span></div>
|
||
<div class="line"><a id="l12116" name="l12116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade8a374e04740aac1ece248b868522fe">12116</a></span><span class="preprocessor">#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk </span></div>
|
||
<div class="line"><a id="l12117" name="l12117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa348f21e19ac18be00577cc2844941d6">12117</a></span><span class="preprocessor">#define TIM_DIER_TIE_Pos (6U) </span></div>
|
||
<div class="line"><a id="l12118" name="l12118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf3e781c907ca4774fae5c089e445f5a">12118</a></span><span class="preprocessor">#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) </span></div>
|
||
<div class="line"><a id="l12119" name="l12119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa755fef2c4e96c63f2ea1cd9a32f956a">12119</a></span><span class="preprocessor">#define TIM_DIER_TIE TIM_DIER_TIE_Msk </span></div>
|
||
<div class="line"><a id="l12120" name="l12120"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68f1acf20b177e729494b03d389fc879">12120</a></span><span class="preprocessor">#define TIM_DIER_BIE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12121" name="l12121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad054244795a6fcd3bc1ff35e4c651982">12121</a></span><span class="preprocessor">#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) </span></div>
|
||
<div class="line"><a id="l12122" name="l12122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fcb0d6d9fb7486a5901032fd81aef6a">12122</a></span><span class="preprocessor">#define TIM_DIER_BIE TIM_DIER_BIE_Msk </span></div>
|
||
<div class="line"><a id="l12123" name="l12123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5078f4d6a9f542a502194cd1499f90a3">12123</a></span><span class="preprocessor">#define TIM_DIER_UDE_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12124" name="l12124"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66544291fb58960e9f4018509a4dee09">12124</a></span><span class="preprocessor">#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) </span></div>
|
||
<div class="line"><a id="l12125" name="l12125"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9f47792b1c2f123464a2955f445c811">12125</a></span><span class="preprocessor">#define TIM_DIER_UDE TIM_DIER_UDE_Msk </span></div>
|
||
<div class="line"><a id="l12126" name="l12126"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15a2b408f82591fcffc36fb1b71e0ee4">12126</a></span><span class="preprocessor">#define TIM_DIER_CC1DE_Pos (9U) </span></div>
|
||
<div class="line"><a id="l12127" name="l12127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40247fa7b772b644df2754b599e71e22">12127</a></span><span class="preprocessor">#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) </span></div>
|
||
<div class="line"><a id="l12128" name="l12128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae181bb16ec916aba8ba86f58f745fdfd">12128</a></span><span class="preprocessor">#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk </span></div>
|
||
<div class="line"><a id="l12129" name="l12129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga567e807487bdcf4d7db0c50c02154420">12129</a></span><span class="preprocessor">#define TIM_DIER_CC2DE_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12130" name="l12130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74a3a6d017bcc45df793e9b1d19c013d">12130</a></span><span class="preprocessor">#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) </span></div>
|
||
<div class="line"><a id="l12131" name="l12131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58f97064991095b28c91028ca3cca28e">12131</a></span><span class="preprocessor">#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk </span></div>
|
||
<div class="line"><a id="l12132" name="l12132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e08651981fedc16b1ed9925c4f84373">12132</a></span><span class="preprocessor">#define TIM_DIER_CC3DE_Pos (11U) </span></div>
|
||
<div class="line"><a id="l12133" name="l12133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade4d3ce6b292c28e2fd7c9e9bd8f6ab6">12133</a></span><span class="preprocessor">#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) </span></div>
|
||
<div class="line"><a id="l12134" name="l12134"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1567bff5dc0564b26a8b3cff1f0fe0a4">12134</a></span><span class="preprocessor">#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk </span></div>
|
||
<div class="line"><a id="l12135" name="l12135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c72cedbdd1f3c2390f25bb181b76b39">12135</a></span><span class="preprocessor">#define TIM_DIER_CC4DE_Pos (12U) </span></div>
|
||
<div class="line"><a id="l12136" name="l12136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad81dbfb6c7c8907ec2debd892b48e9ba">12136</a></span><span class="preprocessor">#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) </span></div>
|
||
<div class="line"><a id="l12137" name="l12137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaba034412c54fa07024e516492748614">12137</a></span><span class="preprocessor">#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk </span></div>
|
||
<div class="line"><a id="l12138" name="l12138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0311dbc32a6e1b38dd0e6a5a7ae6c4ed">12138</a></span><span class="preprocessor">#define TIM_DIER_COMDE_Pos (13U) </span></div>
|
||
<div class="line"><a id="l12139" name="l12139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ed00410aeabe33fef5feebbaec1a0a6">12139</a></span><span class="preprocessor">#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) </span></div>
|
||
<div class="line"><a id="l12140" name="l12140"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79c3fab9d33de953a0a7f7d6516c73bc">12140</a></span><span class="preprocessor">#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk </span></div>
|
||
<div class="line"><a id="l12141" name="l12141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b1014527f96f63edc7dfa3b79297557">12141</a></span><span class="preprocessor">#define TIM_DIER_TDE_Pos (14U) </span></div>
|
||
<div class="line"><a id="l12142" name="l12142"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbd5aee3b64fd928be288ae86b4fa020">12142</a></span><span class="preprocessor">#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) </span></div>
|
||
<div class="line"><a id="l12143" name="l12143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a752d4295f100708df9b8be5a7f439d">12143</a></span><span class="preprocessor">#define TIM_DIER_TDE TIM_DIER_TDE_Msk </span></div>
|
||
<div class="line"><a id="l12145" name="l12145"></a><span class="lineno">12145</span><span class="comment">/******************** Bit definition for TIM_SR register ********************/</span></div>
|
||
<div class="line"><a id="l12146" name="l12146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga558df2cd4bfe780f9381149b4e0eab19">12146</a></span><span class="preprocessor">#define TIM_SR_UIF_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12147" name="l12147"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a713154f9408c97cd7b193f23affab2">12147</a></span><span class="preprocessor">#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) </span></div>
|
||
<div class="line"><a id="l12148" name="l12148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8c03fabc10654d2a3f76ea40fcdbde6">12148</a></span><span class="preprocessor">#define TIM_SR_UIF TIM_SR_UIF_Msk </span></div>
|
||
<div class="line"><a id="l12149" name="l12149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61c518804171ea0813d7dd5702adde4c">12149</a></span><span class="preprocessor">#define TIM_SR_CC1IF_Pos (1U) </span></div>
|
||
<div class="line"><a id="l12150" name="l12150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ce1be8a563567338d87977ddc0aa2c5">12150</a></span><span class="preprocessor">#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) </span></div>
|
||
<div class="line"><a id="l12151" name="l12151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga449a61344a97608d85384c29f003c0e9">12151</a></span><span class="preprocessor">#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk </span></div>
|
||
<div class="line"><a id="l12152" name="l12152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef088105198e8850e542fc8e0fd362ae">12152</a></span><span class="preprocessor">#define TIM_SR_CC2IF_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12153" name="l12153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac970c8ac8779185ba8f313e280c40902">12153</a></span><span class="preprocessor">#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) </span></div>
|
||
<div class="line"><a id="l12154" name="l12154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25a48bf099467169aa50464fbf462bd8">12154</a></span><span class="preprocessor">#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk </span></div>
|
||
<div class="line"><a id="l12155" name="l12155"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9d4e629577fc5a15dd907a0a2d6f43a">12155</a></span><span class="preprocessor">#define TIM_SR_CC3IF_Pos (3U) </span></div>
|
||
<div class="line"><a id="l12156" name="l12156"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77b2e69acc55c8d12f789fc5bf9a5f54">12156</a></span><span class="preprocessor">#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) </span></div>
|
||
<div class="line"><a id="l12157" name="l12157"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3cf234a1059c0a04799e88382cdc0f2">12157</a></span><span class="preprocessor">#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk </span></div>
|
||
<div class="line"><a id="l12158" name="l12158"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f5a114b99523c3f6766951ab28026f9">12158</a></span><span class="preprocessor">#define TIM_SR_CC4IF_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12159" name="l12159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62087fa2c5fa8166d6b4be7e32c60442">12159</a></span><span class="preprocessor">#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) </span></div>
|
||
<div class="line"><a id="l12160" name="l12160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacade8a06303bf216bfb03140c7e16cac">12160</a></span><span class="preprocessor">#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk </span></div>
|
||
<div class="line"><a id="l12161" name="l12161"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa44f0ec2b4134ef80ce28d7a878772af">12161</a></span><span class="preprocessor">#define TIM_SR_COMIF_Pos (5U) </span></div>
|
||
<div class="line"><a id="l12162" name="l12162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8af1c1f93eee747aaa7fdc3a5aeb5337">12162</a></span><span class="preprocessor">#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) </span></div>
|
||
<div class="line"><a id="l12163" name="l12163"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91775c029171c4585e9cca6ebf1cd57a">12163</a></span><span class="preprocessor">#define TIM_SR_COMIF TIM_SR_COMIF_Msk </span></div>
|
||
<div class="line"><a id="l12164" name="l12164"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc65e5e222f7625dda796d36e0c0d563">12164</a></span><span class="preprocessor">#define TIM_SR_TIF_Pos (6U) </span></div>
|
||
<div class="line"><a id="l12165" name="l12165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ad9bed9cae745d41a987675821b202a">12165</a></span><span class="preprocessor">#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) </span></div>
|
||
<div class="line"><a id="l12166" name="l12166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c8b16f3ced6ec03e9001276b134846e">12166</a></span><span class="preprocessor">#define TIM_SR_TIF TIM_SR_TIF_Msk </span></div>
|
||
<div class="line"><a id="l12167" name="l12167"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61bc5fc1383047eb82dd66cb44a52ff3">12167</a></span><span class="preprocessor">#define TIM_SR_BIF_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12168" name="l12168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga778093c3983d94f88d6da49de96c9826">12168</a></span><span class="preprocessor">#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) </span></div>
|
||
<div class="line"><a id="l12169" name="l12169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d52cd5a57c9a26b0d993c93d9875097">12169</a></span><span class="preprocessor">#define TIM_SR_BIF TIM_SR_BIF_Msk </span></div>
|
||
<div class="line"><a id="l12170" name="l12170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d3dd0efe5e5b6c21a10091bbb61d2c6">12170</a></span><span class="preprocessor">#define TIM_SR_CC1OF_Pos (9U) </span></div>
|
||
<div class="line"><a id="l12171" name="l12171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae38020b672e525cf31f3a21a01ee680f">12171</a></span><span class="preprocessor">#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) </span></div>
|
||
<div class="line"><a id="l12172" name="l12172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga819c4b27f8fa99b537c4407521f9780c">12172</a></span><span class="preprocessor">#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk </span></div>
|
||
<div class="line"><a id="l12173" name="l12173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a0188211bdf0406c2712d92e7d644c3">12173</a></span><span class="preprocessor">#define TIM_SR_CC2OF_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12174" name="l12174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga772886dce929789865cf7053728488d4">12174</a></span><span class="preprocessor">#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) </span></div>
|
||
<div class="line"><a id="l12175" name="l12175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b7798da5863d559ea9a642af6658050">12175</a></span><span class="preprocessor">#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk </span></div>
|
||
<div class="line"><a id="l12176" name="l12176"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga131fff23ae52a9ae98267f06f35b9abb">12176</a></span><span class="preprocessor">#define TIM_SR_CC3OF_Pos (11U) </span></div>
|
||
<div class="line"><a id="l12177" name="l12177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36d466016b806136b3e0251363e7e38d">12177</a></span><span class="preprocessor">#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) </span></div>
|
||
<div class="line"><a id="l12178" name="l12178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7a2d4c831eb641ba082156e41d03358">12178</a></span><span class="preprocessor">#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk </span></div>
|
||
<div class="line"><a id="l12179" name="l12179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa692368f903e95550c110a8cdbece996">12179</a></span><span class="preprocessor">#define TIM_SR_CC4OF_Pos (12U) </span></div>
|
||
<div class="line"><a id="l12180" name="l12180"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36421d430d4fd0d34d02444b5da804b5">12180</a></span><span class="preprocessor">#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) </span></div>
|
||
<div class="line"><a id="l12181" name="l12181"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81ba979e8309b66808e06e4de34bc740">12181</a></span><span class="preprocessor">#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk </span></div>
|
||
<div class="line"><a id="l12183" name="l12183"></a><span class="lineno">12183</span><span class="comment">/******************* Bit definition for TIM_EGR register ********************/</span></div>
|
||
<div class="line"><a id="l12184" name="l12184"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71cd5b80d699afa003cb407a74dc0593">12184</a></span><span class="preprocessor">#define TIM_EGR_UG_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12185" name="l12185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ff315da1492025d608eb2c71e1e4462">12185</a></span><span class="preprocessor">#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) </span></div>
|
||
<div class="line"><a id="l12186" name="l12186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16f52a8e9aad153223405b965566ae91">12186</a></span><span class="preprocessor">#define TIM_EGR_UG TIM_EGR_UG_Msk </span></div>
|
||
<div class="line"><a id="l12187" name="l12187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee06d20dfa5d132d221a28193dedd211">12187</a></span><span class="preprocessor">#define TIM_EGR_CC1G_Pos (1U) </span></div>
|
||
<div class="line"><a id="l12188" name="l12188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba7a2fa9e7341df84a32cf5d54e61ad3">12188</a></span><span class="preprocessor">#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) </span></div>
|
||
<div class="line"><a id="l12189" name="l12189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a1318609761df5de5213e9e75b5aa6a">12189</a></span><span class="preprocessor">#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk </span></div>
|
||
<div class="line"><a id="l12190" name="l12190"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49003c85e8c92b159faee96d1c6a8cea">12190</a></span><span class="preprocessor">#define TIM_EGR_CC2G_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12191" name="l12191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfa4c983163836490441a78e7bf89b67">12191</a></span><span class="preprocessor">#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) </span></div>
|
||
<div class="line"><a id="l12192" name="l12192"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5423de00e86aeb8a4657a509af485055">12192</a></span><span class="preprocessor">#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk </span></div>
|
||
<div class="line"><a id="l12193" name="l12193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8006ffc22a9a37d21364e8023d7eb145">12193</a></span><span class="preprocessor">#define TIM_EGR_CC3G_Pos (3U) </span></div>
|
||
<div class="line"><a id="l12194" name="l12194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab73c2e5ea59b860e342d2ea5f99ff672">12194</a></span><span class="preprocessor">#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) </span></div>
|
||
<div class="line"><a id="l12195" name="l12195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga064d2030abccc099ded418fd81d6aa07">12195</a></span><span class="preprocessor">#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk </span></div>
|
||
<div class="line"><a id="l12196" name="l12196"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49b4e300af06da863900ba29d894eb26">12196</a></span><span class="preprocessor">#define TIM_EGR_CC4G_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12197" name="l12197"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ae87478438e43366db04ac05db1db0e">12197</a></span><span class="preprocessor">#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) </span></div>
|
||
<div class="line"><a id="l12198" name="l12198"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c4e5555dd3be8ab1e631d1053f4a305">12198</a></span><span class="preprocessor">#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk </span></div>
|
||
<div class="line"><a id="l12199" name="l12199"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga235c6ad9b108e6640f0c3fb7b3b9e278">12199</a></span><span class="preprocessor">#define TIM_EGR_COMG_Pos (5U) </span></div>
|
||
<div class="line"><a id="l12200" name="l12200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab04646da2ee78ff6e2d4c483c8050d20">12200</a></span><span class="preprocessor">#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) </span></div>
|
||
<div class="line"><a id="l12201" name="l12201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb06f8bb364307695c7d6a028391de7b">12201</a></span><span class="preprocessor">#define TIM_EGR_COMG TIM_EGR_COMG_Msk </span></div>
|
||
<div class="line"><a id="l12202" name="l12202"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad68094deb44a74ef649c243ec840b9a2">12202</a></span><span class="preprocessor">#define TIM_EGR_TG_Pos (6U) </span></div>
|
||
<div class="line"><a id="l12203" name="l12203"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedb01f674152f674c87c21b6147963d5">12203</a></span><span class="preprocessor">#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) </span></div>
|
||
<div class="line"><a id="l12204" name="l12204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2eabface433d6adaa2dee3df49852585">12204</a></span><span class="preprocessor">#define TIM_EGR_TG TIM_EGR_TG_Msk </span></div>
|
||
<div class="line"><a id="l12205" name="l12205"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga068531a673c44015bef074e6c926ce77">12205</a></span><span class="preprocessor">#define TIM_EGR_BG_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12206" name="l12206"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cbac05839c59f31bd13664890685941">12206</a></span><span class="preprocessor">#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) </span></div>
|
||
<div class="line"><a id="l12207" name="l12207"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08c5635a0ac0ce5618485319a4fa0f18">12207</a></span><span class="preprocessor">#define TIM_EGR_BG TIM_EGR_BG_Msk </span></div>
|
||
<div class="line"><a id="l12209" name="l12209"></a><span class="lineno">12209</span><span class="comment">/****************** Bit definition for TIM_CCMR1 register *******************/</span></div>
|
||
<div class="line"><a id="l12210" name="l12210"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8824b80350897e1b65c1b98f1b7e9469">12210</a></span><span class="preprocessor">#define TIM_CCMR1_CC1S_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12211" name="l12211"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae45972a14def2a4e25e20a688e535b80">12211</a></span><span class="preprocessor">#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) </span></div>
|
||
<div class="line"><a id="l12212" name="l12212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95291df1eaf532c5c996d176648938eb">12212</a></span><span class="preprocessor">#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk </span></div>
|
||
<div class="line"><a id="l12213" name="l12213"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e4968b5500d58d1aebce888da31eb5d">12213</a></span><span class="preprocessor">#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) </span></div>
|
||
<div class="line"><a id="l12214" name="l12214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga299207b757f31c9c02471ab5f4f59dbe">12214</a></span><span class="preprocessor">#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) </span></div>
|
||
<div class="line"><a id="l12216" name="l12216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99fec0329d7dfc1ebe7d3cb9ca9b5bb1">12216</a></span><span class="preprocessor">#define TIM_CCMR1_OC1FE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12217" name="l12217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae9383afb4e7ea68c9254f69461ec626">12217</a></span><span class="preprocessor">#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) </span></div>
|
||
<div class="line"><a id="l12218" name="l12218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9c5878e85ce02c22d8a374deebd1b6e">12218</a></span><span class="preprocessor">#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk </span></div>
|
||
<div class="line"><a id="l12219" name="l12219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf34f1ffb1956f71bb24fb8229d76a6a7">12219</a></span><span class="preprocessor">#define TIM_CCMR1_OC1PE_Pos (3U) </span></div>
|
||
<div class="line"><a id="l12220" name="l12220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6ad2b511f62760051b61edc1d666b02">12220</a></span><span class="preprocessor">#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) </span></div>
|
||
<div class="line"><a id="l12221" name="l12221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1aa54ddf87a4b339881a8d5368ec80eb">12221</a></span><span class="preprocessor">#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk </span></div>
|
||
<div class="line"><a id="l12223" name="l12223"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4e6a8f6b0480f58e9632780bb393c4d">12223</a></span><span class="preprocessor">#define TIM_CCMR1_OC1M_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12224" name="l12224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45e26a7685848c6cd8572038f06ceab1">12224</a></span><span class="preprocessor">#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) </span></div>
|
||
<div class="line"><a id="l12225" name="l12225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ddb3dc889733e71d812baa3873cb13b">12225</a></span><span class="preprocessor">#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk </span></div>
|
||
<div class="line"><a id="l12226" name="l12226"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">12226</a></span><span class="preprocessor">#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) </span></div>
|
||
<div class="line"><a id="l12227" name="l12227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b5f6ec25063483641d6dc065d96d2b5">12227</a></span><span class="preprocessor">#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) </span></div>
|
||
<div class="line"><a id="l12228" name="l12228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">12228</a></span><span class="preprocessor">#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) </span></div>
|
||
<div class="line"><a id="l12230" name="l12230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78c5f97f5378df55d6b5bdf60219ecd2">12230</a></span><span class="preprocessor">#define TIM_CCMR1_OC1CE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12231" name="l12231"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga574f991bc328a80c9b44224e9a74d045">12231</a></span><span class="preprocessor">#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) </span></div>
|
||
<div class="line"><a id="l12232" name="l12232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f44c50cf9928d2afab014e2ca29baba">12232</a></span><span class="preprocessor">#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk </span></div>
|
||
<div class="line"><a id="l12234" name="l12234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e06c5ff5024706a767be3454512401e">12234</a></span><span class="preprocessor">#define TIM_CCMR1_CC2S_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12235" name="l12235"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1df8354fa71992fddecba93c6309c7f3">12235</a></span><span class="preprocessor">#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) </span></div>
|
||
<div class="line"><a id="l12236" name="l12236"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdb0986b78bea5b53ea61e4ddd667cbf">12236</a></span><span class="preprocessor">#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk </span></div>
|
||
<div class="line"><a id="l12237" name="l12237"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52bb0e50c11c35dcf42aeff7f1c22874">12237</a></span><span class="preprocessor">#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) </span></div>
|
||
<div class="line"><a id="l12238" name="l12238"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78303c37fdbe0be80f5fc7d21e9eba45">12238</a></span><span class="preprocessor">#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) </span></div>
|
||
<div class="line"><a id="l12240" name="l12240"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7240668687c24e88a8738b3a84be511">12240</a></span><span class="preprocessor">#define TIM_CCMR1_OC2FE_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12241" name="l12241"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga376f7fd88a0dc62039e03bbc2fdd9569">12241</a></span><span class="preprocessor">#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) </span></div>
|
||
<div class="line"><a id="l12242" name="l12242"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bf610cf77c3c6c936ce7c4f85992e6c">12242</a></span><span class="preprocessor">#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk </span></div>
|
||
<div class="line"><a id="l12243" name="l12243"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga819513a7183766b4427cddfb08413eb7">12243</a></span><span class="preprocessor">#define TIM_CCMR1_OC2PE_Pos (11U) </span></div>
|
||
<div class="line"><a id="l12244" name="l12244"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga664936de978a62b290fe7da4c2b1c395">12244</a></span><span class="preprocessor">#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) </span></div>
|
||
<div class="line"><a id="l12245" name="l12245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabddbf508732039730125ab3e87e9d370">12245</a></span><span class="preprocessor">#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk </span></div>
|
||
<div class="line"><a id="l12247" name="l12247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae31265c2d3adef5873acc64f2f0045a1">12247</a></span><span class="preprocessor">#define TIM_CCMR1_OC2M_Pos (12U) </span></div>
|
||
<div class="line"><a id="l12248" name="l12248"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7082e88c67576a8ce483e0534b0ae8cb">12248</a></span><span class="preprocessor">#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) </span></div>
|
||
<div class="line"><a id="l12249" name="l12249"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2326bafe64ba2ebdde908d66219eaa6f">12249</a></span><span class="preprocessor">#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk </span></div>
|
||
<div class="line"><a id="l12250" name="l12250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbb68b91da16ffd509a6c7a2a397083c">12250</a></span><span class="preprocessor">#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) </span></div>
|
||
<div class="line"><a id="l12251" name="l12251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedb673b7e2c016191579de704eb842e4">12251</a></span><span class="preprocessor">#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) </span></div>
|
||
<div class="line"><a id="l12252" name="l12252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad039a41e5fe97ddf904a0f9f95eb539e">12252</a></span><span class="preprocessor">#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) </span></div>
|
||
<div class="line"><a id="l12254" name="l12254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e30d09989e2a51517b5962e63baf1dd">12254</a></span><span class="preprocessor">#define TIM_CCMR1_OC2CE_Pos (15U) </span></div>
|
||
<div class="line"><a id="l12255" name="l12255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c788cd4e4e8549585b21e050bf91de5">12255</a></span><span class="preprocessor">#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) </span></div>
|
||
<div class="line"><a id="l12256" name="l12256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19a8dd4ea04d262ec4e97b5c7a8677a5">12256</a></span><span class="preprocessor">#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk </span></div>
|
||
<div class="line"><a id="l12258" name="l12258"></a><span class="lineno">12258</span><span class="comment">/*----------------------------------------------------------------------------*/</span></div>
|
||
<div class="line"><a id="l12259" name="l12259"></a><span class="lineno">12259</span> </div>
|
||
<div class="line"><a id="l12260" name="l12260"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84059edcc2ee8d02b8bc6757b667b47a">12260</a></span><span class="preprocessor">#define TIM_CCMR1_IC1PSC_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12261" name="l12261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a7ca2ec3b7bc576b7883702a45823d2">12261</a></span><span class="preprocessor">#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12262" name="l12262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab46b7186665f5308cd2ca52acfb63e72">12262</a></span><span class="preprocessor">#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk </span></div>
|
||
<div class="line"><a id="l12263" name="l12263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05673358a44aeaa56daefca67341b29d">12263</a></span><span class="preprocessor">#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12264" name="l12264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf42b75da9b2f127dca98b6ca616f7add">12264</a></span><span class="preprocessor">#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12266" name="l12266"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b270ce595ea92cabc0e62576b5cbdb0">12266</a></span><span class="preprocessor">#define TIM_CCMR1_IC1F_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12267" name="l12267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade8750e792254e281c4999de3fbf9e13">12267</a></span><span class="preprocessor">#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) </span></div>
|
||
<div class="line"><a id="l12268" name="l12268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0ee123675d8b8f98b5a6eeeccf37912">12268</a></span><span class="preprocessor">#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk </span></div>
|
||
<div class="line"><a id="l12269" name="l12269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7dde4afee556d2d8d22885f191da65a6">12269</a></span><span class="preprocessor">#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) </span></div>
|
||
<div class="line"><a id="l12270" name="l12270"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga201491465e6864088210bccb8491be84">12270</a></span><span class="preprocessor">#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) </span></div>
|
||
<div class="line"><a id="l12271" name="l12271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabaa55ab1e0109b055cabef579c32d67b">12271</a></span><span class="preprocessor">#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) </span></div>
|
||
<div class="line"><a id="l12272" name="l12272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23da95530eb6d6451c7c9e451a580f42">12272</a></span><span class="preprocessor">#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) </span></div>
|
||
<div class="line"><a id="l12274" name="l12274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5eb62126e13b62bf9ed83bcb358532b3">12274</a></span><span class="preprocessor">#define TIM_CCMR1_IC2PSC_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12275" name="l12275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa7570c3a71156c52b0d95b4199f5d3e">12275</a></span><span class="preprocessor">#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12276" name="l12276"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e8e704f9ce5742f45e15e3b3126aa9d">12276</a></span><span class="preprocessor">#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk </span></div>
|
||
<div class="line"><a id="l12277" name="l12277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39206b27b5b1c5941b2a14ee8e2f1223">12277</a></span><span class="preprocessor">#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12278" name="l12278"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae861d74943f3c045421f9fdc8b966841">12278</a></span><span class="preprocessor">#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12280" name="l12280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed5a16f773b95122caa60dbdd5b22964">12280</a></span><span class="preprocessor">#define TIM_CCMR1_IC2F_Pos (12U) </span></div>
|
||
<div class="line"><a id="l12281" name="l12281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b1456053707716ae50feded2a118887">12281</a></span><span class="preprocessor">#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) </span></div>
|
||
<div class="line"><a id="l12282" name="l12282"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b942752d686c23323880ff576e7dffb">12282</a></span><span class="preprocessor">#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk </span></div>
|
||
<div class="line"><a id="l12283" name="l12283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d75acd7072f28844074702683d8493f">12283</a></span><span class="preprocessor">#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) </span></div>
|
||
<div class="line"><a id="l12284" name="l12284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40e49318b54b16bda6fd7feea7c9a7dd">12284</a></span><span class="preprocessor">#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) </span></div>
|
||
<div class="line"><a id="l12285" name="l12285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga932148c784f5cbee4dfcafcbadaf0107">12285</a></span><span class="preprocessor">#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) </span></div>
|
||
<div class="line"><a id="l12286" name="l12286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafece48b6f595ef9717d523fa23cea1e8">12286</a></span><span class="preprocessor">#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) </span></div>
|
||
<div class="line"><a id="l12288" name="l12288"></a><span class="lineno">12288</span><span class="comment">/****************** Bit definition for TIM_CCMR2 register *******************/</span></div>
|
||
<div class="line"><a id="l12289" name="l12289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab00cf673f46bb5a112370ff94d5495b">12289</a></span><span class="preprocessor">#define TIM_CCMR2_CC3S_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12290" name="l12290"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac236d456c1635745129611f040e50392">12290</a></span><span class="preprocessor">#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) </span></div>
|
||
<div class="line"><a id="l12291" name="l12291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2eabcc7e322b02c9c406b3ff70308260">12291</a></span><span class="preprocessor">#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk </span></div>
|
||
<div class="line"><a id="l12292" name="l12292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68c04aea2e89f1e89bd323d6d6e5e6c0">12292</a></span><span class="preprocessor">#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) </span></div>
|
||
<div class="line"><a id="l12293" name="l12293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bed6648aad6e8d16196246b355452dc">12293</a></span><span class="preprocessor">#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) </span></div>
|
||
<div class="line"><a id="l12295" name="l12295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3fada082e0cea460d9722f5dca1fe1a8">12295</a></span><span class="preprocessor">#define TIM_CCMR2_OC3FE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12296" name="l12296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef7fdd716098d6370d1fbef9ec6de226">12296</a></span><span class="preprocessor">#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) </span></div>
|
||
<div class="line"><a id="l12297" name="l12297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6d8d2847058747ce23a648668ce4dba">12297</a></span><span class="preprocessor">#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk </span></div>
|
||
<div class="line"><a id="l12298" name="l12298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ebdd2a0a808080fac30e5ee1514f4cf">12298</a></span><span class="preprocessor">#define TIM_CCMR2_OC3PE_Pos (3U) </span></div>
|
||
<div class="line"><a id="l12299" name="l12299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga340c7064a44bc7478982f5ef7a7655f9">12299</a></span><span class="preprocessor">#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) </span></div>
|
||
<div class="line"><a id="l12300" name="l12300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga276fd2250d2b085b73ef51cb4c099d24">12300</a></span><span class="preprocessor">#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk </span></div>
|
||
<div class="line"><a id="l12302" name="l12302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc968db76163687538732d31cf4d4d91">12302</a></span><span class="preprocessor">#define TIM_CCMR2_OC3M_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12303" name="l12303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e306d8b3f5f98f8bfb6002dc2a7ff06">12303</a></span><span class="preprocessor">#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) </span></div>
|
||
<div class="line"><a id="l12304" name="l12304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52095cae524adb237339bfee92e8168a">12304</a></span><span class="preprocessor">#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk </span></div>
|
||
<div class="line"><a id="l12305" name="l12305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga899b26ffa9c5f30f143306b8598a537f">12305</a></span><span class="preprocessor">#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) </span></div>
|
||
<div class="line"><a id="l12306" name="l12306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91476ae2cc3449facafcad82569e14f8">12306</a></span><span class="preprocessor">#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) </span></div>
|
||
<div class="line"><a id="l12307" name="l12307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20394da7afcada6c3fc455b05004cff5">12307</a></span><span class="preprocessor">#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) </span></div>
|
||
<div class="line"><a id="l12309" name="l12309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03695b16c15f57bd329b050603e11ff6">12309</a></span><span class="preprocessor">#define TIM_CCMR2_OC3CE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12310" name="l12310"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga040e81b609666fec1f0476346bb8b942">12310</a></span><span class="preprocessor">#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) </span></div>
|
||
<div class="line"><a id="l12311" name="l12311"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4209d414df704ce96c54abb2ea2df66a">12311</a></span><span class="preprocessor">#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk </span></div>
|
||
<div class="line"><a id="l12313" name="l12313"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5774c57db57a50e9a1b7e6fa6c2833f6">12313</a></span><span class="preprocessor">#define TIM_CCMR2_CC4S_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12314" name="l12314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66957133f2ac46cacb14834a6ad46b9b">12314</a></span><span class="preprocessor">#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) </span></div>
|
||
<div class="line"><a id="l12315" name="l12315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga294e216b50edd1c2f891143e1f971048">12315</a></span><span class="preprocessor">#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk </span></div>
|
||
<div class="line"><a id="l12316" name="l12316"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabebaa6bffd90b32563bd0fc1ff4a9499">12316</a></span><span class="preprocessor">#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) </span></div>
|
||
<div class="line"><a id="l12317" name="l12317"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6386ec77a3a451954325a1512d44f893">12317</a></span><span class="preprocessor">#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) </span></div>
|
||
<div class="line"><a id="l12319" name="l12319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69ec4d183286e02653876ead0a835a09">12319</a></span><span class="preprocessor">#define TIM_CCMR2_OC4FE_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12320" name="l12320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01f0c4e1d96b5dde5af64ea95b2c3880">12320</a></span><span class="preprocessor">#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) </span></div>
|
||
<div class="line"><a id="l12321" name="l12321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70dc197250c2699d470aea1a7a42ad57">12321</a></span><span class="preprocessor">#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk </span></div>
|
||
<div class="line"><a id="l12322" name="l12322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1271844d8091a2494487cd082a585ca">12322</a></span><span class="preprocessor">#define TIM_CCMR2_OC4PE_Pos (11U) </span></div>
|
||
<div class="line"><a id="l12323" name="l12323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28c07cee007c349ef4ba4a954b341ff4">12323</a></span><span class="preprocessor">#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) </span></div>
|
||
<div class="line"><a id="l12324" name="l12324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e951cd3f6593e321cf79b662a1deaaa">12324</a></span><span class="preprocessor">#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk </span></div>
|
||
<div class="line"><a id="l12326" name="l12326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67d4d6f1f9b93ff94a941d8c574ca400">12326</a></span><span class="preprocessor">#define TIM_CCMR2_OC4M_Pos (12U) </span></div>
|
||
<div class="line"><a id="l12327" name="l12327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ffb46fed2d65aab83a895d8f791f84f">12327</a></span><span class="preprocessor">#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) </span></div>
|
||
<div class="line"><a id="l12328" name="l12328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbed61ff3ba57c7fe6d3386ce3b7af2b">12328</a></span><span class="preprocessor">#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk </span></div>
|
||
<div class="line"><a id="l12329" name="l12329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad866f52cce9ce32e3c0d181007b82de5">12329</a></span><span class="preprocessor">#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) </span></div>
|
||
<div class="line"><a id="l12330" name="l12330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd97b1c86dd4953f3382fea317d165af">12330</a></span><span class="preprocessor">#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) </span></div>
|
||
<div class="line"><a id="l12331" name="l12331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga431e5cdc0f3dc02fa5a54aa5193ddbab">12331</a></span><span class="preprocessor">#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) </span></div>
|
||
<div class="line"><a id="l12333" name="l12333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b06f4781d9ec977f5be9f010ee44b6b">12333</a></span><span class="preprocessor">#define TIM_CCMR2_OC4CE_Pos (15U) </span></div>
|
||
<div class="line"><a id="l12334" name="l12334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a3897ea2b9197cbc75507df645faefc">12334</a></span><span class="preprocessor">#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) </span></div>
|
||
<div class="line"><a id="l12335" name="l12335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1447dfe94bdd234382bb1f43307ea5c3">12335</a></span><span class="preprocessor">#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk </span></div>
|
||
<div class="line"><a id="l12337" name="l12337"></a><span class="lineno">12337</span><span class="comment">/*----------------------------------------------------------------------------*/</span></div>
|
||
<div class="line"><a id="l12338" name="l12338"></a><span class="lineno">12338</span> </div>
|
||
<div class="line"><a id="l12339" name="l12339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae531e77cc77a9a76a0f32074ad371cf2">12339</a></span><span class="preprocessor">#define TIM_CCMR2_IC3PSC_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12340" name="l12340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabec127dfbd39286e7467a88e42b0e2a2">12340</a></span><span class="preprocessor">#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12341" name="l12341"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc3d11f2e968752bc9ec7131c986c3a6">12341</a></span><span class="preprocessor">#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk </span></div>
|
||
<div class="line"><a id="l12342" name="l12342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga588513395cbf8be6f4749c140fbf811c">12342</a></span><span class="preprocessor">#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12343" name="l12343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd27b9bdcc161c90dc1712074a66f29d">12343</a></span><span class="preprocessor">#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12345" name="l12345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf23e70bb3dfe3c685a26e6ae00786b62">12345</a></span><span class="preprocessor">#define TIM_CCMR2_IC3F_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12346" name="l12346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac13900fc61a22d5b43f579e5854fa2c">12346</a></span><span class="preprocessor">#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) </span></div>
|
||
<div class="line"><a id="l12347" name="l12347"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad218af6bd1de72891e1b85d582b766cd">12347</a></span><span class="preprocessor">#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk </span></div>
|
||
<div class="line"><a id="l12348" name="l12348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31d5450ebc9ac6ea833a2b341ceea061">12348</a></span><span class="preprocessor">#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) </span></div>
|
||
<div class="line"><a id="l12349" name="l12349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26f92a3f831685d6df7ab69e68181849">12349</a></span><span class="preprocessor">#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) </span></div>
|
||
<div class="line"><a id="l12350" name="l12350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e7d7a3c2686a6e31adc1adf2ce65df9">12350</a></span><span class="preprocessor">#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) </span></div>
|
||
<div class="line"><a id="l12351" name="l12351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9696c3da027f2b292d077f1ab4cdd14b">12351</a></span><span class="preprocessor">#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) </span></div>
|
||
<div class="line"><a id="l12353" name="l12353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1df596e58e5b71467be3d85988fb302f">12353</a></span><span class="preprocessor">#define TIM_CCMR2_IC4PSC_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12354" name="l12354"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga289328a0304739b4459fa74978be5aa4">12354</a></span><span class="preprocessor">#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12355" name="l12355"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fd7591e2de10272f7fafb08cdd1b7b0">12355</a></span><span class="preprocessor">#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk </span></div>
|
||
<div class="line"><a id="l12356" name="l12356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80f7d206409bc551eab06819e17451e4">12356</a></span><span class="preprocessor">#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12357" name="l12357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6690f5e98e02addd5e75643767c6d66">12357</a></span><span class="preprocessor">#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12359" name="l12359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdce62241567cc540d3b7ce61084c1e2">12359</a></span><span class="preprocessor">#define TIM_CCMR2_IC4F_Pos (12U) </span></div>
|
||
<div class="line"><a id="l12360" name="l12360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9f59cf5cc82d482d733a365cc7d887c">12360</a></span><span class="preprocessor">#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) </span></div>
|
||
<div class="line"><a id="l12361" name="l12361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad51653fd06a591294d432385e794a19e">12361</a></span><span class="preprocessor">#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk </span></div>
|
||
<div class="line"><a id="l12362" name="l12362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d5fc8b9a6ea27582cb6c25f9654888c">12362</a></span><span class="preprocessor">#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) </span></div>
|
||
<div class="line"><a id="l12363" name="l12363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4dcc1562c0c017493e4ee6b32354e85">12363</a></span><span class="preprocessor">#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) </span></div>
|
||
<div class="line"><a id="l12364" name="l12364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b96de7db8b71ac7e414f247b871a53c">12364</a></span><span class="preprocessor">#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) </span></div>
|
||
<div class="line"><a id="l12365" name="l12365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25d0f55e5b751f2caed6a943f5682a09">12365</a></span><span class="preprocessor">#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) </span></div>
|
||
<div class="line"><a id="l12367" name="l12367"></a><span class="lineno">12367</span><span class="comment">/******************* Bit definition for TIM_CCER register *******************/</span></div>
|
||
<div class="line"><a id="l12368" name="l12368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6da61acdf3f1662c2a522820260f0ca1">12368</a></span><span class="preprocessor">#define TIM_CCER_CC1E_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12369" name="l12369"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga871be5249ffb7666a32f4e2e60e50a8c">12369</a></span><span class="preprocessor">#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) </span></div>
|
||
<div class="line"><a id="l12370" name="l12370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f494b9881e7b97bb2d79f7ad4e79937">12370</a></span><span class="preprocessor">#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk </span></div>
|
||
<div class="line"><a id="l12371" name="l12371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15c77329fadbcb3c84bde50fca4531fb">12371</a></span><span class="preprocessor">#define TIM_CCER_CC1P_Pos (1U) </span></div>
|
||
<div class="line"><a id="l12372" name="l12372"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3006ecce72e486321261536ae385732f">12372</a></span><span class="preprocessor">#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) </span></div>
|
||
<div class="line"><a id="l12373" name="l12373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ca0aedba14241caff739afb3c3ee291">12373</a></span><span class="preprocessor">#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk </span></div>
|
||
<div class="line"><a id="l12374" name="l12374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac27744605da2a44ce88bcd692a6dd639">12374</a></span><span class="preprocessor">#define TIM_CCER_CC1NE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12375" name="l12375"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f84300589fc23c7ad7c688b77adffd6">12375</a></span><span class="preprocessor">#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) </span></div>
|
||
<div class="line"><a id="l12376" name="l12376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga813056b3f90a13c4432aeba55f28957e">12376</a></span><span class="preprocessor">#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk </span></div>
|
||
<div class="line"><a id="l12377" name="l12377"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17cab7ddc6363d68c881d424dc2f95b3">12377</a></span><span class="preprocessor">#define TIM_CCER_CC1NP_Pos (3U) </span></div>
|
||
<div class="line"><a id="l12378" name="l12378"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22ca6b2d577776a67d48e9a7e1863700">12378</a></span><span class="preprocessor">#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) </span></div>
|
||
<div class="line"><a id="l12379" name="l12379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga403fc501d4d8de6cabee6b07acb81a36">12379</a></span><span class="preprocessor">#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk </span></div>
|
||
<div class="line"><a id="l12380" name="l12380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a7e6fef34c0f02a97140620a2429b84">12380</a></span><span class="preprocessor">#define TIM_CCER_CC2E_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12381" name="l12381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91010bed31fbd01d7013fe9be759b215">12381</a></span><span class="preprocessor">#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) </span></div>
|
||
<div class="line"><a id="l12382" name="l12382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76392a4d63674cd0db0a55762458f16c">12382</a></span><span class="preprocessor">#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk </span></div>
|
||
<div class="line"><a id="l12383" name="l12383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6eed48ffae9d0a886c124b2993b8a9f">12383</a></span><span class="preprocessor">#define TIM_CCER_CC2P_Pos (5U) </span></div>
|
||
<div class="line"><a id="l12384" name="l12384"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95f10f70479dce9444a304a58dfa52e1">12384</a></span><span class="preprocessor">#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) </span></div>
|
||
<div class="line"><a id="l12385" name="l12385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3136c6e776c6066509d298b6a9b34912">12385</a></span><span class="preprocessor">#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk </span></div>
|
||
<div class="line"><a id="l12386" name="l12386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a035ed74e6d62a0fcf54bd0b31f785a">12386</a></span><span class="preprocessor">#define TIM_CCER_CC2NE_Pos (6U) </span></div>
|
||
<div class="line"><a id="l12387" name="l12387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga395e49f88082d5e2144801c98047e03b">12387</a></span><span class="preprocessor">#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) </span></div>
|
||
<div class="line"><a id="l12388" name="l12388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a784649120eddec31998f34323d4156">12388</a></span><span class="preprocessor">#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk </span></div>
|
||
<div class="line"><a id="l12389" name="l12389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8de88ef55a7e82a4fe7379a0568da7ab">12389</a></span><span class="preprocessor">#define TIM_CCER_CC2NP_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12390" name="l12390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b294ed91060a15ee77651cd8e688e70">12390</a></span><span class="preprocessor">#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) </span></div>
|
||
<div class="line"><a id="l12391" name="l12391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga387de559d8b16b16f3934fddd2aa969f">12391</a></span><span class="preprocessor">#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk </span></div>
|
||
<div class="line"><a id="l12392" name="l12392"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaee67670829d7a6333cae4b5eada7899">12392</a></span><span class="preprocessor">#define TIM_CCER_CC3E_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12393" name="l12393"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga800a18a966d63d71dfc6cf7e3c18ca08">12393</a></span><span class="preprocessor">#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) </span></div>
|
||
<div class="line"><a id="l12394" name="l12394"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1da114e666b61f09cf25f50cdaa7f81f">12394</a></span><span class="preprocessor">#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk </span></div>
|
||
<div class="line"><a id="l12395" name="l12395"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab92731a4de3cb45962bfc34f3986a3bb">12395</a></span><span class="preprocessor">#define TIM_CCER_CC3P_Pos (9U) </span></div>
|
||
<div class="line"><a id="l12396" name="l12396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga647aadf30c1f4c7850a025bce9e264a6">12396</a></span><span class="preprocessor">#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) </span></div>
|
||
<div class="line"><a id="l12397" name="l12397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6220a5cd34c7a7a39e10c854aa00d2e5">12397</a></span><span class="preprocessor">#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk </span></div>
|
||
<div class="line"><a id="l12398" name="l12398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e4ec9ec3d3f6b778c7750f4861de8dc">12398</a></span><span class="preprocessor">#define TIM_CCER_CC3NE_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12399" name="l12399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34cbf30b58b4fa02ddc7c1bab93420b3">12399</a></span><span class="preprocessor">#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) </span></div>
|
||
<div class="line"><a id="l12400" name="l12400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad46cce61d3bd83b64257ba75e54ee1aa">12400</a></span><span class="preprocessor">#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk </span></div>
|
||
<div class="line"><a id="l12401" name="l12401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc4768173a56472e6f19ca49bb229e6a">12401</a></span><span class="preprocessor">#define TIM_CCER_CC3NP_Pos (11U) </span></div>
|
||
<div class="line"><a id="l12402" name="l12402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga013c6bc2ba905dea2713cdef67f39c6f">12402</a></span><span class="preprocessor">#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) </span></div>
|
||
<div class="line"><a id="l12403" name="l12403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4029686d3307111d3f9f4400e29e4521">12403</a></span><span class="preprocessor">#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk </span></div>
|
||
<div class="line"><a id="l12404" name="l12404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e4f1890df26547229ce711eed7a30c3">12404</a></span><span class="preprocessor">#define TIM_CCER_CC4E_Pos (12U) </span></div>
|
||
<div class="line"><a id="l12405" name="l12405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8f00da3ce9a145e9c7c0ece18706d05">12405</a></span><span class="preprocessor">#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) </span></div>
|
||
<div class="line"><a id="l12406" name="l12406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga940b041ab5975311f42f26d314a4b621">12406</a></span><span class="preprocessor">#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk </span></div>
|
||
<div class="line"><a id="l12407" name="l12407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b16bb9029a386a09ca24796a74f7fa8">12407</a></span><span class="preprocessor">#define TIM_CCER_CC4P_Pos (13U) </span></div>
|
||
<div class="line"><a id="l12408" name="l12408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22962f81c9abfc88ae30f50b5592d3a7">12408</a></span><span class="preprocessor">#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) </span></div>
|
||
<div class="line"><a id="l12409" name="l12409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3faf23dc47e1b0877352d7f5a00f72e1">12409</a></span><span class="preprocessor">#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk </span></div>
|
||
<div class="line"><a id="l12410" name="l12410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga451b690ca839a363b6b911bcacafffb4">12410</a></span><span class="preprocessor">#define TIM_CCER_CC4NP_Pos (15U) </span></div>
|
||
<div class="line"><a id="l12411" name="l12411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e263b29e870a454c029f4a825f4f50e">12411</a></span><span class="preprocessor">#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) </span></div>
|
||
<div class="line"><a id="l12412" name="l12412"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41b88bff3f38cec0617ce66fa5aef260">12412</a></span><span class="preprocessor">#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk </span></div>
|
||
<div class="line"><a id="l12414" name="l12414"></a><span class="lineno">12414</span><span class="comment">/******************* Bit definition for TIM_CNT register ********************/</span></div>
|
||
<div class="line"><a id="l12415" name="l12415"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf110ca46cc8cf7b55f63cafa563073b2">12415</a></span><span class="preprocessor">#define TIM_CNT_CNT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12416" name="l12416"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac54bb0107f222981fe8c8416af521fd0">12416</a></span><span class="preprocessor">#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) </span></div>
|
||
<div class="line"><a id="l12417" name="l12417"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8bc45c0315de82c1c3a38a243bcd00fc">12417</a></span><span class="preprocessor">#define TIM_CNT_CNT TIM_CNT_CNT_Msk </span></div>
|
||
<div class="line"><a id="l12419" name="l12419"></a><span class="lineno">12419</span><span class="comment">/******************* Bit definition for TIM_PSC register ********************/</span></div>
|
||
<div class="line"><a id="l12420" name="l12420"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac11163ae1ef14d3e7a1f047c40a501f4">12420</a></span><span class="preprocessor">#define TIM_PSC_PSC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12421" name="l12421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacff3a421342fafac2e25421084bd85df">12421</a></span><span class="preprocessor">#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12422" name="l12422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefb85e4000ddab0ada67c5964810da35">12422</a></span><span class="preprocessor">#define TIM_PSC_PSC TIM_PSC_PSC_Msk </span></div>
|
||
<div class="line"><a id="l12424" name="l12424"></a><span class="lineno">12424</span><span class="comment">/******************* Bit definition for TIM_ARR register ********************/</span></div>
|
||
<div class="line"><a id="l12425" name="l12425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8430ae919aa2e98c8a4cb32049ae5c3b">12425</a></span><span class="preprocessor">#define TIM_ARR_ARR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12426" name="l12426"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga166174bde137aa84aec495eef6907ed3">12426</a></span><span class="preprocessor">#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) </span></div>
|
||
<div class="line"><a id="l12427" name="l12427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace50256fdecc38f641050a4a3266e4d9">12427</a></span><span class="preprocessor">#define TIM_ARR_ARR TIM_ARR_ARR_Msk </span></div>
|
||
<div class="line"><a id="l12429" name="l12429"></a><span class="lineno">12429</span><span class="comment">/******************* Bit definition for TIM_RCR register ********************/</span></div>
|
||
<div class="line"><a id="l12430" name="l12430"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab062a3ee5ed93cef0fd1de937719fe5c">12430</a></span><span class="preprocessor">#define TIM_RCR_REP_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12431" name="l12431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06e8380ec8ac6138f401fa53833978fc">12431</a></span><span class="preprocessor">#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) </span></div>
|
||
<div class="line"><a id="l12432" name="l12432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcef8f28580e36cdfda3be1f7561afc7">12432</a></span><span class="preprocessor">#define TIM_RCR_REP TIM_RCR_REP_Msk </span></div>
|
||
<div class="line"><a id="l12434" name="l12434"></a><span class="lineno">12434</span><span class="comment">/******************* Bit definition for TIM_CCR1 register *******************/</span></div>
|
||
<div class="line"><a id="l12435" name="l12435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga815f704b96c35f8f2b4a9160913e36f6">12435</a></span><span class="preprocessor">#define TIM_CCR1_CCR1_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12436" name="l12436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1052d30a540b5332d39cc9e1e23587bb">12436</a></span><span class="preprocessor">#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) </span></div>
|
||
<div class="line"><a id="l12437" name="l12437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac927cc11eff415210dcf94657d8dfbe0">12437</a></span><span class="preprocessor">#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk </span></div>
|
||
<div class="line"><a id="l12439" name="l12439"></a><span class="lineno">12439</span><span class="comment">/******************* Bit definition for TIM_CCR2 register *******************/</span></div>
|
||
<div class="line"><a id="l12440" name="l12440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22f43b4f1a39a8ff5124a31e2e37efbf">12440</a></span><span class="preprocessor">#define TIM_CCR2_CCR2_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12441" name="l12441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4ef3300e4399d1b036c2e28061d9dd1">12441</a></span><span class="preprocessor">#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) </span></div>
|
||
<div class="line"><a id="l12442" name="l12442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga751e5efd90bdd1fd5f38609f3f5762ba">12442</a></span><span class="preprocessor">#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk </span></div>
|
||
<div class="line"><a id="l12444" name="l12444"></a><span class="lineno">12444</span><span class="comment">/******************* Bit definition for TIM_CCR3 register *******************/</span></div>
|
||
<div class="line"><a id="l12445" name="l12445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69a2438c905cf2e7f0c15b06090be697">12445</a></span><span class="preprocessor">#define TIM_CCR3_CCR3_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12446" name="l12446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3983e861f1f4418bf3df69d263550024">12446</a></span><span class="preprocessor">#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) </span></div>
|
||
<div class="line"><a id="l12447" name="l12447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e85064d37d387851e95c5c1f35315a1">12447</a></span><span class="preprocessor">#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk </span></div>
|
||
<div class="line"><a id="l12449" name="l12449"></a><span class="lineno">12449</span><span class="comment">/******************* Bit definition for TIM_CCR4 register *******************/</span></div>
|
||
<div class="line"><a id="l12450" name="l12450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga812691bb8cabc5eef6093926c6afb0fa">12450</a></span><span class="preprocessor">#define TIM_CCR4_CCR4_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12451" name="l12451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e2e10599fa35e837f604584c742551f">12451</a></span><span class="preprocessor">#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) </span></div>
|
||
<div class="line"><a id="l12452" name="l12452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15c9dd67a6701b5498926ae536773eca">12452</a></span><span class="preprocessor">#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk </span></div>
|
||
<div class="line"><a id="l12454" name="l12454"></a><span class="lineno">12454</span><span class="comment">/******************* Bit definition for TIM_BDTR register *******************/</span></div>
|
||
<div class="line"><a id="l12455" name="l12455"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20f8f8f7a4e2e060b4b51e0a8adc6201">12455</a></span><span class="preprocessor">#define TIM_BDTR_DTG_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12456" name="l12456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c52bd0a743ce97111f4f7210f4f0875">12456</a></span><span class="preprocessor">#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) </span></div>
|
||
<div class="line"><a id="l12457" name="l12457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabcf985e9c78f15e1e44b2bc4d2bafc67">12457</a></span><span class="preprocessor">#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk </span></div>
|
||
<div class="line"><a id="l12458" name="l12458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b575cca31b0e22ef1d5b842aa162bfc">12458</a></span><span class="preprocessor">#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) </span></div>
|
||
<div class="line"><a id="l12459" name="l12459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f33ae1e9b7847a60032a60d0cc7f81d">12459</a></span><span class="preprocessor">#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) </span></div>
|
||
<div class="line"><a id="l12460" name="l12460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f06a132eba960bd6cc972e3580d537c">12460</a></span><span class="preprocessor">#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) </span></div>
|
||
<div class="line"><a id="l12461" name="l12461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7868643a65285fc7132f040c8950f43">12461</a></span><span class="preprocessor">#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) </span></div>
|
||
<div class="line"><a id="l12462" name="l12462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga503b44e30a5fb77c34630d1faca70213">12462</a></span><span class="preprocessor">#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) </span></div>
|
||
<div class="line"><a id="l12463" name="l12463"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83a12ecb0a8dd21bc164d9a345ea564f">12463</a></span><span class="preprocessor">#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) </span></div>
|
||
<div class="line"><a id="l12464" name="l12464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7d418cbd0db89991522cb6be34a017e">12464</a></span><span class="preprocessor">#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) </span></div>
|
||
<div class="line"><a id="l12465" name="l12465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac945c8bcf5567912a88eb2acee53c45b">12465</a></span><span class="preprocessor">#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) </span></div>
|
||
<div class="line"><a id="l12467" name="l12467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71810028fd9aba73ee3b92d59017cb8d">12467</a></span><span class="preprocessor">#define TIM_BDTR_LOCK_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12468" name="l12468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31c7b82190b30d879c3c7b3a46b9ab82">12468</a></span><span class="preprocessor">#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) </span></div>
|
||
<div class="line"><a id="l12469" name="l12469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e4215d17f0548dfcf0b15fe4d0f4651">12469</a></span><span class="preprocessor">#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk </span></div>
|
||
<div class="line"><a id="l12470" name="l12470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbd1736c8172e7cd098bb591264b07bf">12470</a></span><span class="preprocessor">#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) </span></div>
|
||
<div class="line"><a id="l12471" name="l12471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga756df80ff8c34399435f52dca18e6eee">12471</a></span><span class="preprocessor">#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) </span></div>
|
||
<div class="line"><a id="l12473" name="l12473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga508a8d8aea6def7bd3dd689ff5f47312">12473</a></span><span class="preprocessor">#define TIM_BDTR_OSSI_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12474" name="l12474"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05ff8c5f843f6587554de55163a0f420">12474</a></span><span class="preprocessor">#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) </span></div>
|
||
<div class="line"><a id="l12475" name="l12475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1cf04e70ccf3d4aba5afcf2496a411a">12475</a></span><span class="preprocessor">#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk </span></div>
|
||
<div class="line"><a id="l12476" name="l12476"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5738bf6a27c598bc93b37db41f1a21c1">12476</a></span><span class="preprocessor">#define TIM_BDTR_OSSR_Pos (11U) </span></div>
|
||
<div class="line"><a id="l12477" name="l12477"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga396c60115df4f4f217ae3b2df15d130c">12477</a></span><span class="preprocessor">#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) </span></div>
|
||
<div class="line"><a id="l12478" name="l12478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9435f36d53c6be1107e57ab6a82c16e">12478</a></span><span class="preprocessor">#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk </span></div>
|
||
<div class="line"><a id="l12479" name="l12479"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27bff46bd1b077d0a152e4600397f98d">12479</a></span><span class="preprocessor">#define TIM_BDTR_BKE_Pos (12U) </span></div>
|
||
<div class="line"><a id="l12480" name="l12480"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2272c6e4c575623c1f46f482cd957415">12480</a></span><span class="preprocessor">#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) </span></div>
|
||
<div class="line"><a id="l12481" name="l12481"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74250b040dd9fd9c09dcc54cdd6d86d8">12481</a></span><span class="preprocessor">#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk </span></div>
|
||
<div class="line"><a id="l12482" name="l12482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf42525a0a24fac15595720c1ef01d57a">12482</a></span><span class="preprocessor">#define TIM_BDTR_BKP_Pos (13U) </span></div>
|
||
<div class="line"><a id="l12483" name="l12483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga101b7d11ccc8db986ee394ec26167130">12483</a></span><span class="preprocessor">#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) </span></div>
|
||
<div class="line"><a id="l12484" name="l12484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3247abbbf0d00260be051d176d88020e">12484</a></span><span class="preprocessor">#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk </span></div>
|
||
<div class="line"><a id="l12485" name="l12485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c59af6d6570d3f4c7bff1efcde8fd5a">12485</a></span><span class="preprocessor">#define TIM_BDTR_AOE_Pos (14U) </span></div>
|
||
<div class="line"><a id="l12486" name="l12486"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9f2a293cb57e4e53908ff3968b44eda">12486</a></span><span class="preprocessor">#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) </span></div>
|
||
<div class="line"><a id="l12487" name="l12487"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59f15008050f91fa3ecc9eaaa971a509">12487</a></span><span class="preprocessor">#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk </span></div>
|
||
<div class="line"><a id="l12488" name="l12488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1874eb52559400db69885a6dee768c4">12488</a></span><span class="preprocessor">#define TIM_BDTR_MOE_Pos (15U) </span></div>
|
||
<div class="line"><a id="l12489" name="l12489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaead4c63fdacf9c85e3c997275649aa8e">12489</a></span><span class="preprocessor">#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) </span></div>
|
||
<div class="line"><a id="l12490" name="l12490"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga277a096614829feba2d0a4fbb7d3dffc">12490</a></span><span class="preprocessor">#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk </span></div>
|
||
<div class="line"><a id="l12492" name="l12492"></a><span class="lineno">12492</span><span class="comment">/******************* Bit definition for TIM_DCR register ********************/</span></div>
|
||
<div class="line"><a id="l12493" name="l12493"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a306a1cb19e8538984d63e2728f18c9">12493</a></span><span class="preprocessor">#define TIM_DCR_DBA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12494" name="l12494"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga603bd90bfdd7e08fb4c749c926ae8d0d">12494</a></span><span class="preprocessor">#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) </span></div>
|
||
<div class="line"><a id="l12495" name="l12495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf9051ecac123cd89f9d2a835e4cde2e">12495</a></span><span class="preprocessor">#define TIM_DCR_DBA TIM_DCR_DBA_Msk </span></div>
|
||
<div class="line"><a id="l12496" name="l12496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaaf610e5fe4bb4b10736242df3b62bba">12496</a></span><span class="preprocessor">#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) </span></div>
|
||
<div class="line"><a id="l12497" name="l12497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a0185643c163930e30f0a1cf5fe364e">12497</a></span><span class="preprocessor">#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) </span></div>
|
||
<div class="line"><a id="l12498" name="l12498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa5a89b93b97b0968a7d5563a18ab9d1">12498</a></span><span class="preprocessor">#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) </span></div>
|
||
<div class="line"><a id="l12499" name="l12499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga105f44ff18cbbd4ff4d60368c9184430">12499</a></span><span class="preprocessor">#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) </span></div>
|
||
<div class="line"><a id="l12500" name="l12500"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe1bc4b6dd7265dee2857f23d835b2dc">12500</a></span><span class="preprocessor">#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) </span></div>
|
||
<div class="line"><a id="l12502" name="l12502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e78721748388667766590962b29f610">12502</a></span><span class="preprocessor">#define TIM_DCR_DBL_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12503" name="l12503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19d5bc5ed6177c1603a35d52918e5068">12503</a></span><span class="preprocessor">#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) </span></div>
|
||
<div class="line"><a id="l12504" name="l12504"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9e197a78484567d4c6093c28265f3eb">12504</a></span><span class="preprocessor">#define TIM_DCR_DBL TIM_DCR_DBL_Msk </span></div>
|
||
<div class="line"><a id="l12505" name="l12505"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga677195c0b4892bb6717564c0528126a9">12505</a></span><span class="preprocessor">#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) </span></div>
|
||
<div class="line"><a id="l12506" name="l12506"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad427ba987877e491f7a2be60e320dbea">12506</a></span><span class="preprocessor">#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) </span></div>
|
||
<div class="line"><a id="l12507" name="l12507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga369926f2a8ca5cf635ded9bb4619189c">12507</a></span><span class="preprocessor">#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) </span></div>
|
||
<div class="line"><a id="l12508" name="l12508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f1ec849c41d1abd46c528a4ac378c03">12508</a></span><span class="preprocessor">#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) </span></div>
|
||
<div class="line"><a id="l12509" name="l12509"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga607d7b87b1b4bf167aabad36f922a8f9">12509</a></span><span class="preprocessor">#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) </span></div>
|
||
<div class="line"><a id="l12511" name="l12511"></a><span class="lineno">12511</span><span class="comment">/******************* Bit definition for TIM_DMAR register *******************/</span></div>
|
||
<div class="line"><a id="l12512" name="l12512"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga404a796ef83390218d4aed467f779ca0">12512</a></span><span class="preprocessor">#define TIM_DMAR_DMAB_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12513" name="l12513"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5d6d71391fa416ce5c1aa65e459d92a">12513</a></span><span class="preprocessor">#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) </span></div>
|
||
<div class="line"><a id="l12514" name="l12514"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1afa2fc02bcd75c15122c4eb87d6cf83">12514</a></span><span class="preprocessor">#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk </span></div>
|
||
<div class="line"><a id="l12516" name="l12516"></a><span class="lineno">12516</span><span class="comment">/******************* Bit definition for TIM_OR register *********************/</span></div>
|
||
<div class="line"><a id="l12517" name="l12517"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f62ec5e16705319b0d7ecdc54471788">12517</a></span><span class="preprocessor">#define TIM_OR_TI1_RMP_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12518" name="l12518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e8ec8a0faf4bc51e04f909e3b13708e">12518</a></span><span class="preprocessor">#define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos) </span></div>
|
||
<div class="line"><a id="l12519" name="l12519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd0ec0e64e354c9670015c91aaf54c2e">12519</a></span><span class="preprocessor">#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk </span></div>
|
||
<div class="line"><a id="l12520" name="l12520"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59fa1246d851959d5231b5b0796fd3a5">12520</a></span><span class="preprocessor">#define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos) </span></div>
|
||
<div class="line"><a id="l12521" name="l12521"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98d9cdc55111a548e48df0819922852b">12521</a></span><span class="preprocessor">#define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos) </span></div>
|
||
<div class="line"><a id="l12523" name="l12523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaecd8b0b125d46d02c35f990903d6fcb">12523</a></span><span class="preprocessor">#define TIM_OR_TI4_RMP_Pos (6U) </span></div>
|
||
<div class="line"><a id="l12524" name="l12524"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef046d565911337566adcc67904847ea">12524</a></span><span class="preprocessor">#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) </span></div>
|
||
<div class="line"><a id="l12525" name="l12525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2916847c3545c06578d7ba8c381a4c20">12525</a></span><span class="preprocessor">#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk </span></div>
|
||
<div class="line"><a id="l12526" name="l12526"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9aea4f8a0abedbf08bb1e686933c1120">12526</a></span><span class="preprocessor">#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos) </span></div>
|
||
<div class="line"><a id="l12527" name="l12527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2a46aa18f15f2074b93233a18e85629">12527</a></span><span class="preprocessor">#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos) </span></div>
|
||
<div class="line"><a id="l12528" name="l12528"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50c5d626671e911a5d0943e6477e4aa7">12528</a></span><span class="preprocessor">#define TIM_OR_ITR1_RMP_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12529" name="l12529"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8bc0672804e61da192e6063e0bb82ed3">12529</a></span><span class="preprocessor">#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos) </span></div>
|
||
<div class="line"><a id="l12530" name="l12530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f413eac7f503dfddc9a9914efa555ac">12530</a></span><span class="preprocessor">#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk </span></div>
|
||
<div class="line"><a id="l12531" name="l12531"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7141f22c81a83134d9bb35cdeca5549">12531</a></span><span class="preprocessor">#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos) </span></div>
|
||
<div class="line"><a id="l12532" name="l12532"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ba54d02d962d04d2bdf16df11c7ccd0">12532</a></span><span class="preprocessor">#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos) </span></div>
|
||
<div class="line"><a id="l12535" name="l12535"></a><span class="lineno">12535</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l12536" name="l12536"></a><span class="lineno">12536</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l12537" name="l12537"></a><span class="lineno">12537</span><span class="comment">/* Universal Synchronous Asynchronous Receiver Transmitter */</span></div>
|
||
<div class="line"><a id="l12538" name="l12538"></a><span class="lineno">12538</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l12539" name="l12539"></a><span class="lineno">12539</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l12540" name="l12540"></a><span class="lineno">12540</span><span class="comment">/******************* Bit definition for USART_SR register *******************/</span></div>
|
||
<div class="line"><a id="l12541" name="l12541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0635e2ab8eac81f2a10164602121ccf2">12541</a></span><span class="preprocessor">#define USART_SR_PE_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12542" name="l12542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83b7f81b87e70796a8cffaae0eb9ba9a">12542</a></span><span class="preprocessor">#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) </span></div>
|
||
<div class="line"><a id="l12543" name="l12543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac88be3484245af8c1b271ae5c1b97a14">12543</a></span><span class="preprocessor">#define USART_SR_PE USART_SR_PE_Msk </span></div>
|
||
<div class="line"><a id="l12544" name="l12544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga780d79584f83d2873c4026cdaa93d848">12544</a></span><span class="preprocessor">#define USART_SR_FE_Pos (1U) </span></div>
|
||
<div class="line"><a id="l12545" name="l12545"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3050686c973903a8821196e0a7166f3">12545</a></span><span class="preprocessor">#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) </span></div>
|
||
<div class="line"><a id="l12546" name="l12546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9eb6fd3f820bd12e0b5a981de1894804">12546</a></span><span class="preprocessor">#define USART_SR_FE USART_SR_FE_Msk </span></div>
|
||
<div class="line"><a id="l12547" name="l12547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92528c798c4fa8ecfda09d6058cbb7f3">12547</a></span><span class="preprocessor">#define USART_SR_NE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12548" name="l12548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4150c4eff1939e0c1c474dce82ed76bf">12548</a></span><span class="preprocessor">#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) </span></div>
|
||
<div class="line"><a id="l12549" name="l12549"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8938468c5666a8305ade6d80d467c572">12549</a></span><span class="preprocessor">#define USART_SR_NE USART_SR_NE_Msk </span></div>
|
||
<div class="line"><a id="l12550" name="l12550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1413d933bfe380829bd883ce5ae6f27b">12550</a></span><span class="preprocessor">#define USART_SR_ORE_Pos (3U) </span></div>
|
||
<div class="line"><a id="l12551" name="l12551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga654b0cd0fb1fdf02de8f1af223eca9d5">12551</a></span><span class="preprocessor">#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) </span></div>
|
||
<div class="line"><a id="l12552" name="l12552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4560fc7a60df4bdf402fc7219ae7b558">12552</a></span><span class="preprocessor">#define USART_SR_ORE USART_SR_ORE_Msk </span></div>
|
||
<div class="line"><a id="l12553" name="l12553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2a7cf252454c0c27e5d4327bbd3206f">12553</a></span><span class="preprocessor">#define USART_SR_IDLE_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12554" name="l12554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2b2420f9c84d2adbb47dce8d0e65497">12554</a></span><span class="preprocessor">#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) </span></div>
|
||
<div class="line"><a id="l12555" name="l12555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga336fa8c9965ce18c10972ac80ded611f">12555</a></span><span class="preprocessor">#define USART_SR_IDLE USART_SR_IDLE_Msk </span></div>
|
||
<div class="line"><a id="l12556" name="l12556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5895ff1c2d076cb10c291c873eedc55">12556</a></span><span class="preprocessor">#define USART_SR_RXNE_Pos (5U) </span></div>
|
||
<div class="line"><a id="l12557" name="l12557"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64611f0aa4ba3dcafb6d934e831279e9">12557</a></span><span class="preprocessor">#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) </span></div>
|
||
<div class="line"><a id="l12558" name="l12558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0c99e2bb265b3d58a91aca7a93f7836">12558</a></span><span class="preprocessor">#define USART_SR_RXNE USART_SR_RXNE_Msk </span></div>
|
||
<div class="line"><a id="l12559" name="l12559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8cdb6c85343e4287d5c07bcff25d58e">12559</a></span><span class="preprocessor">#define USART_SR_TC_Pos (6U) </span></div>
|
||
<div class="line"><a id="l12560" name="l12560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga972584d838f708691ef3c153ad8233ac">12560</a></span><span class="preprocessor">#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) </span></div>
|
||
<div class="line"><a id="l12561" name="l12561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76229b05ac37a5a688e6ba45851a29f1">12561</a></span><span class="preprocessor">#define USART_SR_TC USART_SR_TC_Msk </span></div>
|
||
<div class="line"><a id="l12562" name="l12562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa708cd1b36e1ee1cfed89e85620a7c00">12562</a></span><span class="preprocessor">#define USART_SR_TXE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12563" name="l12563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe75a9021a84919f6c1ea3e3c08a23e0">12563</a></span><span class="preprocessor">#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) </span></div>
|
||
<div class="line"><a id="l12564" name="l12564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65e9cddf0890113d405342f1d8b5b980">12564</a></span><span class="preprocessor">#define USART_SR_TXE USART_SR_TXE_Msk </span></div>
|
||
<div class="line"><a id="l12565" name="l12565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae347aead943d5b4c1044a226380b3fda">12565</a></span><span class="preprocessor">#define USART_SR_LBD_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12566" name="l12566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga233a2963e3a24a14f98865224183d93d">12566</a></span><span class="preprocessor">#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) </span></div>
|
||
<div class="line"><a id="l12567" name="l12567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b868b59576f42421226d35628c6b628">12567</a></span><span class="preprocessor">#define USART_SR_LBD USART_SR_LBD_Msk </span></div>
|
||
<div class="line"><a id="l12568" name="l12568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d2b04e34749fc2ef806327e991dcad8">12568</a></span><span class="preprocessor">#define USART_SR_CTS_Pos (9U) </span></div>
|
||
<div class="line"><a id="l12569" name="l12569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d241b440c4595aac4bdf1ffee9c22f9">12569</a></span><span class="preprocessor">#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) </span></div>
|
||
<div class="line"><a id="l12570" name="l12570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9250ae2793db0541e6c4bb8837424541">12570</a></span><span class="preprocessor">#define USART_SR_CTS USART_SR_CTS_Msk </span></div>
|
||
<div class="line"><a id="l12572" name="l12572"></a><span class="lineno">12572</span><span class="comment">/******************* Bit definition for USART_DR register *******************/</span></div>
|
||
<div class="line"><a id="l12573" name="l12573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1d7d8f36a92c78b93ab1a3e4011b771">12573</a></span><span class="preprocessor">#define USART_DR_DR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12574" name="l12574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga911912bd628fd1fc33a1d8819d27e81f">12574</a></span><span class="preprocessor">#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) </span></div>
|
||
<div class="line"><a id="l12575" name="l12575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad84ad1e1d0202b41021e2d6e40486bff">12575</a></span><span class="preprocessor">#define USART_DR_DR USART_DR_DR_Msk </span></div>
|
||
<div class="line"><a id="l12577" name="l12577"></a><span class="lineno">12577</span><span class="comment">/****************** Bit definition for USART_BRR register *******************/</span></div>
|
||
<div class="line"><a id="l12578" name="l12578"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4c70e9b7c797d9a6e1e7a4e4e645ef1">12578</a></span><span class="preprocessor">#define USART_BRR_DIV_Fraction_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12579" name="l12579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cc35155a1120da23f3fc72cb26b4aea">12579</a></span><span class="preprocessor">#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) </span></div>
|
||
<div class="line"><a id="l12580" name="l12580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9dfae31be4ec2c8a3b0905eff30c7046">12580</a></span><span class="preprocessor">#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk </span></div>
|
||
<div class="line"><a id="l12581" name="l12581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21895f823b1422a7af307b0656560058">12581</a></span><span class="preprocessor">#define USART_BRR_DIV_Mantissa_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12582" name="l12582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace4259fb84cf5a9096ad62cd2453d28e">12582</a></span><span class="preprocessor">#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) </span></div>
|
||
<div class="line"><a id="l12583" name="l12583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60cfa3802798306b86231f828ed2e71e">12583</a></span><span class="preprocessor">#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk </span></div>
|
||
<div class="line"><a id="l12585" name="l12585"></a><span class="lineno">12585</span><span class="comment">/****************** Bit definition for USART_CR1 register *******************/</span></div>
|
||
<div class="line"><a id="l12586" name="l12586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23eec4bbb3ac06c22aff3355f965457a">12586</a></span><span class="preprocessor">#define USART_CR1_SBK_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12587" name="l12587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f06150e7efb4ee5858a0863c0af36e1">12587</a></span><span class="preprocessor">#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) </span></div>
|
||
<div class="line"><a id="l12588" name="l12588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac457c519baa28359ab7959fbe0c5cda1">12588</a></span><span class="preprocessor">#define USART_CR1_SBK USART_CR1_SBK_Msk </span></div>
|
||
<div class="line"><a id="l12589" name="l12589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64a90f545fa1ee315c277fd0f06f2274">12589</a></span><span class="preprocessor">#define USART_CR1_RWU_Pos (1U) </span></div>
|
||
<div class="line"><a id="l12590" name="l12590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e0cafa55c289e39145287325f9d7cf4">12590</a></span><span class="preprocessor">#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) </span></div>
|
||
<div class="line"><a id="l12591" name="l12591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7d61ab5a4e2beaa3f591c56bd15a27b">12591</a></span><span class="preprocessor">#define USART_CR1_RWU USART_CR1_RWU_Msk </span></div>
|
||
<div class="line"><a id="l12592" name="l12592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga678b98c07ad61dec17131716d1ddfa58">12592</a></span><span class="preprocessor">#define USART_CR1_RE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12593" name="l12593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga625927bbfd40ce911de7183cae92e682">12593</a></span><span class="preprocessor">#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) </span></div>
|
||
<div class="line"><a id="l12594" name="l12594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada0d5d407a22264de847bc1b40a17aeb">12594</a></span><span class="preprocessor">#define USART_CR1_RE USART_CR1_RE_Msk </span></div>
|
||
<div class="line"><a id="l12595" name="l12595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53df187761bfed354686b47e0a691564">12595</a></span><span class="preprocessor">#define USART_CR1_TE_Pos (3U) </span></div>
|
||
<div class="line"><a id="l12596" name="l12596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c5e02008c2fde7c5f0070d94ee77bce">12596</a></span><span class="preprocessor">#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) </span></div>
|
||
<div class="line"><a id="l12597" name="l12597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade7f090b04fd78b755b43357ecaa9622">12597</a></span><span class="preprocessor">#define USART_CR1_TE USART_CR1_TE_Msk </span></div>
|
||
<div class="line"><a id="l12598" name="l12598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ba3e0fc695108b77498a9fdbacc95d3">12598</a></span><span class="preprocessor">#define USART_CR1_IDLEIE_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12599" name="l12599"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ad37a38ae2c8a059a922f5b33c5c2aa">12599</a></span><span class="preprocessor">#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) </span></div>
|
||
<div class="line"><a id="l12600" name="l12600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5221d09eebd12445a20f221bf98066f8">12600</a></span><span class="preprocessor">#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk </span></div>
|
||
<div class="line"><a id="l12601" name="l12601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2232ea76bad178a6e945fe573c2dc984">12601</a></span><span class="preprocessor">#define USART_CR1_RXNEIE_Pos (5U) </span></div>
|
||
<div class="line"><a id="l12602" name="l12602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2e4ba1ab97599cbf7f182d2cfc80543">12602</a></span><span class="preprocessor">#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) </span></div>
|
||
<div class="line"><a id="l12603" name="l12603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91118f867adfdb2e805beea86666de04">12603</a></span><span class="preprocessor">#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk </span></div>
|
||
<div class="line"><a id="l12604" name="l12604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ee92ad658865410023fc8508325024a">12604</a></span><span class="preprocessor">#define USART_CR1_TCIE_Pos (6U) </span></div>
|
||
<div class="line"><a id="l12605" name="l12605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3ff7666f8e81e2cf6d40bebaf0a84b7">12605</a></span><span class="preprocessor">#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) </span></div>
|
||
<div class="line"><a id="l12606" name="l12606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa17130690a1ca95b972429eb64d4254e">12606</a></span><span class="preprocessor">#define USART_CR1_TCIE USART_CR1_TCIE_Msk </span></div>
|
||
<div class="line"><a id="l12607" name="l12607"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6931210415f36d727f75bfc856aed9ef">12607</a></span><span class="preprocessor">#define USART_CR1_TXEIE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12608" name="l12608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65436dd25155a36250ee090dd940caa5">12608</a></span><span class="preprocessor">#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) </span></div>
|
||
<div class="line"><a id="l12609" name="l12609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70422871d15f974b464365e7fe1877e9">12609</a></span><span class="preprocessor">#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk </span></div>
|
||
<div class="line"><a id="l12610" name="l12610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46a693e8924defd8e57b0b08323afa0b">12610</a></span><span class="preprocessor">#define USART_CR1_PEIE_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12611" name="l12611"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad99fb4719a46d6d1d423d7ffe7ce06e1">12611</a></span><span class="preprocessor">#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) </span></div>
|
||
<div class="line"><a id="l12612" name="l12612"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27405d413b6d355ccdb076d52fef6875">12612</a></span><span class="preprocessor">#define USART_CR1_PEIE USART_CR1_PEIE_Msk </span></div>
|
||
<div class="line"><a id="l12613" name="l12613"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2e65e62ab989658fec2bdaad7892c16">12613</a></span><span class="preprocessor">#define USART_CR1_PS_Pos (9U) </span></div>
|
||
<div class="line"><a id="l12614" name="l12614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08638afebc30caad3337f1faac6d904e">12614</a></span><span class="preprocessor">#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) </span></div>
|
||
<div class="line"><a id="l12615" name="l12615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e159d36ab2c93a2c1942df60e9eebbe">12615</a></span><span class="preprocessor">#define USART_CR1_PS USART_CR1_PS_Msk </span></div>
|
||
<div class="line"><a id="l12616" name="l12616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1029c679b6ce540fc8343e074387fa5b">12616</a></span><span class="preprocessor">#define USART_CR1_PCE_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12617" name="l12617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60894c2937928b5ca83fe73e60e1c9c1">12617</a></span><span class="preprocessor">#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) </span></div>
|
||
<div class="line"><a id="l12618" name="l12618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60f8fcf084f9a8514efafb617c70b074">12618</a></span><span class="preprocessor">#define USART_CR1_PCE USART_CR1_PCE_Msk </span></div>
|
||
<div class="line"><a id="l12619" name="l12619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86cc2060fef5dc3ce6820e31f0156492">12619</a></span><span class="preprocessor">#define USART_CR1_WAKE_Pos (11U) </span></div>
|
||
<div class="line"><a id="l12620" name="l12620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0bc41f3a11fced743f19684211eacd6">12620</a></span><span class="preprocessor">#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) </span></div>
|
||
<div class="line"><a id="l12621" name="l12621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad831dfc169fcf14b7284984dbecf322d">12621</a></span><span class="preprocessor">#define USART_CR1_WAKE USART_CR1_WAKE_Msk </span></div>
|
||
<div class="line"><a id="l12622" name="l12622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b16c1bf94dba8a889397c5933322308">12622</a></span><span class="preprocessor">#define USART_CR1_M_Pos (12U) </span></div>
|
||
<div class="line"><a id="l12623" name="l12623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b5f5bc798207f9cc9e54ab080637634">12623</a></span><span class="preprocessor">#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) </span></div>
|
||
<div class="line"><a id="l12624" name="l12624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95f0288b9c6aaeca7cb6550a2e6833e2">12624</a></span><span class="preprocessor">#define USART_CR1_M USART_CR1_M_Msk </span></div>
|
||
<div class="line"><a id="l12625" name="l12625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64f40c78bbc597ada96c2ec828722eeb">12625</a></span><span class="preprocessor">#define USART_CR1_UE_Pos (13U) </span></div>
|
||
<div class="line"><a id="l12626" name="l12626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8b32c050e6d9482a819e0107ceb9f83">12626</a></span><span class="preprocessor">#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) </span></div>
|
||
<div class="line"><a id="l12627" name="l12627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bb650676aaae4a5203f372d497d5947">12627</a></span><span class="preprocessor">#define USART_CR1_UE USART_CR1_UE_Msk </span></div>
|
||
<div class="line"><a id="l12628" name="l12628"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f51c380de00d417c76712183070ff01">12628</a></span><span class="preprocessor">#define USART_CR1_OVER8_Pos (15U) </span></div>
|
||
<div class="line"><a id="l12629" name="l12629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac009e53008167c20955efe87a147ea02">12629</a></span><span class="preprocessor">#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) </span></div>
|
||
<div class="line"><a id="l12630" name="l12630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed6caeb0cb48f1a7b34090f31a92a8e2">12630</a></span><span class="preprocessor">#define USART_CR1_OVER8 USART_CR1_OVER8_Msk </span></div>
|
||
<div class="line"><a id="l12632" name="l12632"></a><span class="lineno">12632</span><span class="comment">/****************** Bit definition for USART_CR2 register *******************/</span></div>
|
||
<div class="line"><a id="l12633" name="l12633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d1320f17e2f61e21a867e538c737ac3">12633</a></span><span class="preprocessor">#define USART_CR2_ADD_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12634" name="l12634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7ee87cc9cdc865b0f5a61af0c26ec28">12634</a></span><span class="preprocessor">#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) </span></div>
|
||
<div class="line"><a id="l12635" name="l12635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ee77fac25142271ad56d49685e518b3">12635</a></span><span class="preprocessor">#define USART_CR2_ADD USART_CR2_ADD_Msk </span></div>
|
||
<div class="line"><a id="l12636" name="l12636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf0b33cd8b6a3eb4a21bb6c34922a624">12636</a></span><span class="preprocessor">#define USART_CR2_LBDL_Pos (5U) </span></div>
|
||
<div class="line"><a id="l12637" name="l12637"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8d54a2e633ef8dda121c9d5670a5de5">12637</a></span><span class="preprocessor">#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) </span></div>
|
||
<div class="line"><a id="l12638" name="l12638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f9bc41700717fd93548e0e95b6072ed">12638</a></span><span class="preprocessor">#define USART_CR2_LBDL USART_CR2_LBDL_Msk </span></div>
|
||
<div class="line"><a id="l12639" name="l12639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9af36362bd69d0008e46a7ea7633b0f">12639</a></span><span class="preprocessor">#define USART_CR2_LBDIE_Pos (6U) </span></div>
|
||
<div class="line"><a id="l12640" name="l12640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad55383a0b8d928fd50c18c62faf44a7b">12640</a></span><span class="preprocessor">#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) </span></div>
|
||
<div class="line"><a id="l12641" name="l12641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa02ef5d22553f028ea48e5d9f08192b4">12641</a></span><span class="preprocessor">#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk </span></div>
|
||
<div class="line"><a id="l12642" name="l12642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0262849ac25bc43d23d46945c85851b0">12642</a></span><span class="preprocessor">#define USART_CR2_LBCL_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12643" name="l12643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d515f33359c44365712bfbcf34c7e94">12643</a></span><span class="preprocessor">#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) </span></div>
|
||
<div class="line"><a id="l12644" name="l12644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a62e93ae7864e89622bdd92508b615e">12644</a></span><span class="preprocessor">#define USART_CR2_LBCL USART_CR2_LBCL_Msk </span></div>
|
||
<div class="line"><a id="l12645" name="l12645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4188976dbf7f6455ba79d1afd830cf7a">12645</a></span><span class="preprocessor">#define USART_CR2_CPHA_Pos (9U) </span></div>
|
||
<div class="line"><a id="l12646" name="l12646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65c8198c5780edaa8ef67706d7d1ea34">12646</a></span><span class="preprocessor">#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) </span></div>
|
||
<div class="line"><a id="l12647" name="l12647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga362976ce813e58310399d113d2cf09cb">12647</a></span><span class="preprocessor">#define USART_CR2_CPHA USART_CR2_CPHA_Msk </span></div>
|
||
<div class="line"><a id="l12648" name="l12648"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga110f164794e57c70b9d7b0b26577e86a">12648</a></span><span class="preprocessor">#define USART_CR2_CPOL_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12649" name="l12649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga182e2b837ab775c53868a37a1e4eb05a">12649</a></span><span class="preprocessor">#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) </span></div>
|
||
<div class="line"><a id="l12650" name="l12650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbb4336ac93d94d4e78f9fb7b3a0dc68">12650</a></span><span class="preprocessor">#define USART_CR2_CPOL USART_CR2_CPOL_Msk </span></div>
|
||
<div class="line"><a id="l12651" name="l12651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff740ebbb84ac8db332d177cd6cc9235">12651</a></span><span class="preprocessor">#define USART_CR2_CLKEN_Pos (11U) </span></div>
|
||
<div class="line"><a id="l12652" name="l12652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f6a20180f8b2ad531009b33ecec1ed2">12652</a></span><span class="preprocessor">#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) </span></div>
|
||
<div class="line"><a id="l12653" name="l12653"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42a396cde02ffa0c4d3fd9817b6af853">12653</a></span><span class="preprocessor">#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk </span></div>
|
||
<div class="line"><a id="l12655" name="l12655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a46b8272a2fe5ae5e5ce7123db22d51">12655</a></span><span class="preprocessor">#define USART_CR2_STOP_Pos (12U) </span></div>
|
||
<div class="line"><a id="l12656" name="l12656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf73b228efa85f04a6b9a42e01b7f916c">12656</a></span><span class="preprocessor">#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12657" name="l12657"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf993e483318ebcecffd18649de766dc6">12657</a></span><span class="preprocessor">#define USART_CR2_STOP USART_CR2_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12658" name="l12658"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee6ee01c6e5325b378b2209ef20d0a61">12658</a></span><span class="preprocessor">#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12659" name="l12659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b24d14f0e5d1c76c878b08aad44d02b">12659</a></span><span class="preprocessor">#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12661" name="l12661"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f06b1d9300507573ffbf99f9a6ee57f">12661</a></span><span class="preprocessor">#define USART_CR2_LINEN_Pos (14U) </span></div>
|
||
<div class="line"><a id="l12662" name="l12662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga500c59de0f57986002b962dc9bccfbe8">12662</a></span><span class="preprocessor">#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) </span></div>
|
||
<div class="line"><a id="l12663" name="l12663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8931efa62c29d92f5c0ec5a05f907ef">12663</a></span><span class="preprocessor">#define USART_CR2_LINEN USART_CR2_LINEN_Msk </span></div>
|
||
<div class="line"><a id="l12665" name="l12665"></a><span class="lineno">12665</span><span class="comment">/****************** Bit definition for USART_CR3 register *******************/</span></div>
|
||
<div class="line"><a id="l12666" name="l12666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafeb00f27cc04dab7e9bcca92d6e7ad9e">12666</a></span><span class="preprocessor">#define USART_CR3_EIE_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12667" name="l12667"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac0414669386ae8dd26b993ddf96d7b0">12667</a></span><span class="preprocessor">#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) </span></div>
|
||
<div class="line"><a id="l12668" name="l12668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaed1a39c551b1641128f81893ff558d0">12668</a></span><span class="preprocessor">#define USART_CR3_EIE USART_CR3_EIE_Msk </span></div>
|
||
<div class="line"><a id="l12669" name="l12669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22ce6319d8acdb4a57215aeb933c7a57">12669</a></span><span class="preprocessor">#define USART_CR3_IREN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l12670" name="l12670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3c0575491453dbd478d5a3413ac759c">12670</a></span><span class="preprocessor">#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) </span></div>
|
||
<div class="line"><a id="l12671" name="l12671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31c66373bfbae7724c836ac63b8411dd">12671</a></span><span class="preprocessor">#define USART_CR3_IREN USART_CR3_IREN_Msk </span></div>
|
||
<div class="line"><a id="l12672" name="l12672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73290a1bb7594fc2016662ba4b927dd5">12672</a></span><span class="preprocessor">#define USART_CR3_IRLP_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12673" name="l12673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67262b96751aebc3a04d3a6d46213633">12673</a></span><span class="preprocessor">#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) </span></div>
|
||
<div class="line"><a id="l12674" name="l12674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22af8d399f1adda62e31186f0309af80">12674</a></span><span class="preprocessor">#define USART_CR3_IRLP USART_CR3_IRLP_Msk </span></div>
|
||
<div class="line"><a id="l12675" name="l12675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7df0071641a9cc2d70e4957c28f923c9">12675</a></span><span class="preprocessor">#define USART_CR3_HDSEL_Pos (3U) </span></div>
|
||
<div class="line"><a id="l12676" name="l12676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5553c10996ceb918244202407347848d">12676</a></span><span class="preprocessor">#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) </span></div>
|
||
<div class="line"><a id="l12677" name="l12677"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac71129810fab0b46d91161a39e3f8d01">12677</a></span><span class="preprocessor">#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk </span></div>
|
||
<div class="line"><a id="l12678" name="l12678"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga818bd165232f86477503e8f9bc9de049">12678</a></span><span class="preprocessor">#define USART_CR3_NACK_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12679" name="l12679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga214ed21d5354e7a14f013fd4954e4d3a">12679</a></span><span class="preprocessor">#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) </span></div>
|
||
<div class="line"><a id="l12680" name="l12680"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f3b70b2ee9ff0b59e952fd7ab04373c">12680</a></span><span class="preprocessor">#define USART_CR3_NACK USART_CR3_NACK_Msk </span></div>
|
||
<div class="line"><a id="l12681" name="l12681"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae269fb759007c1043534a3794f7b98d">12681</a></span><span class="preprocessor">#define USART_CR3_SCEN_Pos (5U) </span></div>
|
||
<div class="line"><a id="l12682" name="l12682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff592b0d891ba78201de2e08cd9305b8">12682</a></span><span class="preprocessor">#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) </span></div>
|
||
<div class="line"><a id="l12683" name="l12683"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9180b9249a26988f71d4bb2b0c3eec27">12683</a></span><span class="preprocessor">#define USART_CR3_SCEN USART_CR3_SCEN_Msk </span></div>
|
||
<div class="line"><a id="l12684" name="l12684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga173f2f38fdb5ba3db30d3b2686bd9773">12684</a></span><span class="preprocessor">#define USART_CR3_DMAR_Pos (6U) </span></div>
|
||
<div class="line"><a id="l12685" name="l12685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dd0232a385ce9760635c92556c3eadf">12685</a></span><span class="preprocessor">#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) </span></div>
|
||
<div class="line"><a id="l12686" name="l12686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff130f15493c765353ec2fd605667c5a">12686</a></span><span class="preprocessor">#define USART_CR3_DMAR USART_CR3_DMAR_Msk </span></div>
|
||
<div class="line"><a id="l12687" name="l12687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00afc87870cbe74aabf127179dedca3f">12687</a></span><span class="preprocessor">#define USART_CR3_DMAT_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12688" name="l12688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga114a52251ccd0dae87055bbd336add29">12688</a></span><span class="preprocessor">#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) </span></div>
|
||
<div class="line"><a id="l12689" name="l12689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bb515d3814d448f84e2c98bf44f3993">12689</a></span><span class="preprocessor">#define USART_CR3_DMAT USART_CR3_DMAT_Msk </span></div>
|
||
<div class="line"><a id="l12690" name="l12690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga790491b1c83dd6a84a6f86945cf74563">12690</a></span><span class="preprocessor">#define USART_CR3_RTSE_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12691" name="l12691"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae20cda51a847495ad5f32c5f5c252152">12691</a></span><span class="preprocessor">#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) </span></div>
|
||
<div class="line"><a id="l12692" name="l12692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c5d6fcd84a4728cda578a0339b4cac2">12692</a></span><span class="preprocessor">#define USART_CR3_RTSE USART_CR3_RTSE_Msk </span></div>
|
||
<div class="line"><a id="l12693" name="l12693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3bfa28091d9c8781aeb03fcb371dd01">12693</a></span><span class="preprocessor">#define USART_CR3_CTSE_Pos (9U) </span></div>
|
||
<div class="line"><a id="l12694" name="l12694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97e4c254d292233d827a898bda170fa4">12694</a></span><span class="preprocessor">#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) </span></div>
|
||
<div class="line"><a id="l12695" name="l12695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa125f026b1ca2d76eab48b191baed265">12695</a></span><span class="preprocessor">#define USART_CR3_CTSE USART_CR3_CTSE_Msk </span></div>
|
||
<div class="line"><a id="l12696" name="l12696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga660c0090fb7c6c17bce5f15a7b07ce7d">12696</a></span><span class="preprocessor">#define USART_CR3_CTSIE_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12697" name="l12697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ca77aa980a93f5b35bf318c20f500cc">12697</a></span><span class="preprocessor">#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) </span></div>
|
||
<div class="line"><a id="l12698" name="l12698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga636d5ec2e9556949fc68d13ad45a1e90">12698</a></span><span class="preprocessor">#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk </span></div>
|
||
<div class="line"><a id="l12699" name="l12699"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d9eb170fd3fa98254e243f588e5a068">12699</a></span><span class="preprocessor">#define USART_CR3_ONEBIT_Pos (11U) </span></div>
|
||
<div class="line"><a id="l12700" name="l12700"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09e3e99ce53ca74ca3396b63a51f18ac">12700</a></span><span class="preprocessor">#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) </span></div>
|
||
<div class="line"><a id="l12701" name="l12701"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a96fb1a7beab602cbc8cb0393593826">12701</a></span><span class="preprocessor">#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk </span></div>
|
||
<div class="line"><a id="l12703" name="l12703"></a><span class="lineno">12703</span><span class="comment">/****************** Bit definition for USART_GTPR register ******************/</span></div>
|
||
<div class="line"><a id="l12704" name="l12704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab09117d544d70ca803eb3831fc86b4a2">12704</a></span><span class="preprocessor">#define USART_GTPR_PSC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12705" name="l12705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga742100366bd139204afb3402a052a588">12705</a></span><span class="preprocessor">#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12706" name="l12706"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0b423f0f4baf7d510ea70477e5c9203">12706</a></span><span class="preprocessor">#define USART_GTPR_PSC USART_GTPR_PSC_Msk </span></div>
|
||
<div class="line"><a id="l12707" name="l12707"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c49c90d83a0e3746b56b2a0a3b0ddcb">12707</a></span><span class="preprocessor">#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12708" name="l12708"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8eab5000ab993991d0da8ffbd386c92b">12708</a></span><span class="preprocessor">#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12709" name="l12709"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d74604b6e1ab08a45ea4fe6b3f6b5cd">12709</a></span><span class="preprocessor">#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12710" name="l12710"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b6b237fcac675f8f047c4ff64248486">12710</a></span><span class="preprocessor">#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12711" name="l12711"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1c0e92df8edb974008b3d37d12f655a">12711</a></span><span class="preprocessor">#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12712" name="l12712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12dda4877432bc181c9684b0830b1b7b">12712</a></span><span class="preprocessor">#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12713" name="l12713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga045e834b03e7a06b2005a13923af424a">12713</a></span><span class="preprocessor">#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12714" name="l12714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3da67d3c9c3abf436098a86477d2dfc">12714</a></span><span class="preprocessor">#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) </span></div>
|
||
<div class="line"><a id="l12716" name="l12716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga219c2c6c797f288ff792f0b6c792070b">12716</a></span><span class="preprocessor">#define USART_GTPR_GT_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12717" name="l12717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddc06fc01cf5031610706007672f2780">12717</a></span><span class="preprocessor">#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) </span></div>
|
||
<div class="line"><a id="l12718" name="l12718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e927fad0bfa430f54007e158e01f43b">12718</a></span><span class="preprocessor">#define USART_GTPR_GT USART_GTPR_GT_Msk </span></div>
|
||
<div class="line"><a id="l12720" name="l12720"></a><span class="lineno">12720</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l12721" name="l12721"></a><span class="lineno">12721</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l12722" name="l12722"></a><span class="lineno">12722</span><span class="comment">/* Window WATCHDOG */</span></div>
|
||
<div class="line"><a id="l12723" name="l12723"></a><span class="lineno">12723</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l12724" name="l12724"></a><span class="lineno">12724</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l12725" name="l12725"></a><span class="lineno">12725</span><span class="comment">/******************* Bit definition for WWDG_CR register ********************/</span></div>
|
||
<div class="line"><a id="l12726" name="l12726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a1da6274cc0fb20e75dfbe1a20ab62e">12726</a></span><span class="preprocessor">#define WWDG_CR_T_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12727" name="l12727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8676c7d294b92a9ea0d0f1b088308ed">12727</a></span><span class="preprocessor">#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) </span></div>
|
||
<div class="line"><a id="l12728" name="l12728"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga400774feb33ed7544d57d6a0a76e0f70">12728</a></span><span class="preprocessor">#define WWDG_CR_T WWDG_CR_T_Msk </span></div>
|
||
<div class="line"><a id="l12729" name="l12729"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga305c0da4633020b9696d64a1785fa29c">12729</a></span><span class="preprocessor">#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) </span></div>
|
||
<div class="line"><a id="l12730" name="l12730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44e5ea3baea1e37b0446e56e910c3409">12730</a></span><span class="preprocessor">#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) </span></div>
|
||
<div class="line"><a id="l12731" name="l12731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67e7b9fa1867ecd6a9dd4b28381e4229">12731</a></span><span class="preprocessor">#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) </span></div>
|
||
<div class="line"><a id="l12732" name="l12732"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64ede5bff80b5b979a44d073205f5930">12732</a></span><span class="preprocessor">#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) </span></div>
|
||
<div class="line"><a id="l12733" name="l12733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbc9c4a71473ceb1fde58a1d6054a7fe">12733</a></span><span class="preprocessor">#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) </span></div>
|
||
<div class="line"><a id="l12734" name="l12734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f41b8c9b91c0632521373203bcb5b64">12734</a></span><span class="preprocessor">#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) </span></div>
|
||
<div class="line"><a id="l12735" name="l12735"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8abc0d44e390aabc2c7f787f2ed0b632">12735</a></span><span class="preprocessor">#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) </span></div>
|
||
<div class="line"><a id="l12736" name="l12736"></a><span class="lineno">12736</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l12737" name="l12737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d510237467b8e10ca1001574671ad8e">12737</a></span><span class="preprocessor">#define WWDG_CR_T0 WWDG_CR_T_0</span></div>
|
||
<div class="line"><a id="l12738" name="l12738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed4b5d3f4d2e0540058fd2253a8feb95">12738</a></span><span class="preprocessor">#define WWDG_CR_T1 WWDG_CR_T_1</span></div>
|
||
<div class="line"><a id="l12739" name="l12739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4e9559da387f10bac2dc8ab0d4f6e6c">12739</a></span><span class="preprocessor">#define WWDG_CR_T2 WWDG_CR_T_2</span></div>
|
||
<div class="line"><a id="l12740" name="l12740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1e344f4a12c60e57cb643511379b261">12740</a></span><span class="preprocessor">#define WWDG_CR_T3 WWDG_CR_T_3</span></div>
|
||
<div class="line"><a id="l12741" name="l12741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1f89d17eb4b3bb1b67c2b0185061e45">12741</a></span><span class="preprocessor">#define WWDG_CR_T4 WWDG_CR_T_4</span></div>
|
||
<div class="line"><a id="l12742" name="l12742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc9870e0e3a5c171b9c1db817afcf0ee">12742</a></span><span class="preprocessor">#define WWDG_CR_T5 WWDG_CR_T_5</span></div>
|
||
<div class="line"><a id="l12743" name="l12743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3a493575c9a7c6006a3af9d13399268">12743</a></span><span class="preprocessor">#define WWDG_CR_T6 WWDG_CR_T_6</span></div>
|
||
<div class="line"><a id="l12744" name="l12744"></a><span class="lineno">12744</span> </div>
|
||
<div class="line"><a id="l12745" name="l12745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51b9fed94bc5fdbc67446173e1b3676c">12745</a></span><span class="preprocessor">#define WWDG_CR_WDGA_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12746" name="l12746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06bd586be3859790f803c1275ea52390">12746</a></span><span class="preprocessor">#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) </span></div>
|
||
<div class="line"><a id="l12747" name="l12747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab647e9997b8b8e67de72af1aaea3f52f">12747</a></span><span class="preprocessor">#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk </span></div>
|
||
<div class="line"><a id="l12749" name="l12749"></a><span class="lineno">12749</span><span class="comment">/******************* Bit definition for WWDG_CFR register *******************/</span></div>
|
||
<div class="line"><a id="l12750" name="l12750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9c98c783bea6069765360fcd6df341b">12750</a></span><span class="preprocessor">#define WWDG_CFR_W_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12751" name="l12751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3aed21af49014ce535798f9beead136d">12751</a></span><span class="preprocessor">#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) </span></div>
|
||
<div class="line"><a id="l12752" name="l12752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabfbb9991bd6a3699399ca569c71fe8c9">12752</a></span><span class="preprocessor">#define WWDG_CFR_W WWDG_CFR_W_Msk </span></div>
|
||
<div class="line"><a id="l12753" name="l12753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26f4016f9990c2657acdf7521233d16d">12753</a></span><span class="preprocessor">#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) </span></div>
|
||
<div class="line"><a id="l12754" name="l12754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga546410b3ec62e976c0f590cf9f216bb3">12754</a></span><span class="preprocessor">#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) </span></div>
|
||
<div class="line"><a id="l12755" name="l12755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3de841283deaea061d977392805211d">12755</a></span><span class="preprocessor">#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) </span></div>
|
||
<div class="line"><a id="l12756" name="l12756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0394248f2a4e4b6ba6c28024fa961a99">12756</a></span><span class="preprocessor">#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) </span></div>
|
||
<div class="line"><a id="l12757" name="l12757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25594b7ced3e1277b636caf02416a4e7">12757</a></span><span class="preprocessor">#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) </span></div>
|
||
<div class="line"><a id="l12758" name="l12758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e730800b000f6fe3be5ea43a6e29cf9">12758</a></span><span class="preprocessor">#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) </span></div>
|
||
<div class="line"><a id="l12759" name="l12759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fc25f8d5c23a76d364c1cb5d7518a17">12759</a></span><span class="preprocessor">#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) </span></div>
|
||
<div class="line"><a id="l12760" name="l12760"></a><span class="lineno">12760</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l12761" name="l12761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae37e08098d003f44eb8770a9d9bd40d0">12761</a></span><span class="preprocessor">#define WWDG_CFR_W0 WWDG_CFR_W_0</span></div>
|
||
<div class="line"><a id="l12762" name="l12762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga698b68239773862647ef5f9d963b80c4">12762</a></span><span class="preprocessor">#define WWDG_CFR_W1 WWDG_CFR_W_1</span></div>
|
||
<div class="line"><a id="l12763" name="l12763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga166845425e89d01552bac0baeec686d9">12763</a></span><span class="preprocessor">#define WWDG_CFR_W2 WWDG_CFR_W_2</span></div>
|
||
<div class="line"><a id="l12764" name="l12764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga344253edc9710aa6db6047b76cce723b">12764</a></span><span class="preprocessor">#define WWDG_CFR_W3 WWDG_CFR_W_3</span></div>
|
||
<div class="line"><a id="l12765" name="l12765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec3a0817a2dcde78414d02c0cb5d201d">12765</a></span><span class="preprocessor">#define WWDG_CFR_W4 WWDG_CFR_W_4</span></div>
|
||
<div class="line"><a id="l12766" name="l12766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8032c21626b10fcf5cd8ad36bc051663">12766</a></span><span class="preprocessor">#define WWDG_CFR_W5 WWDG_CFR_W_5</span></div>
|
||
<div class="line"><a id="l12767" name="l12767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga106cdb96da03ce192628f54cefcbec2f">12767</a></span><span class="preprocessor">#define WWDG_CFR_W6 WWDG_CFR_W_6</span></div>
|
||
<div class="line"><a id="l12768" name="l12768"></a><span class="lineno">12768</span> </div>
|
||
<div class="line"><a id="l12769" name="l12769"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga496363a4b305b4aa94d9ec6c80d232f1">12769</a></span><span class="preprocessor">#define WWDG_CFR_WDGTB_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12770" name="l12770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga627018d443463abccf249b1b848e2b64">12770</a></span><span class="preprocessor">#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) </span></div>
|
||
<div class="line"><a id="l12771" name="l12771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga067b1d8238f1d5613481aba71a946638">12771</a></span><span class="preprocessor">#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk </span></div>
|
||
<div class="line"><a id="l12772" name="l12772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab94b761166186987f91d342a5f79695">12772</a></span><span class="preprocessor">#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) </span></div>
|
||
<div class="line"><a id="l12773" name="l12773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9120ceb094ab327ec766a06fc66ef401">12773</a></span><span class="preprocessor">#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) </span></div>
|
||
<div class="line"><a id="l12774" name="l12774"></a><span class="lineno">12774</span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l12775" name="l12775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4858525604534e493b8a09e0b04ace61">12775</a></span><span class="preprocessor">#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0</span></div>
|
||
<div class="line"><a id="l12776" name="l12776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d53e6fa74c43522ebacd6dd6f450d33">12776</a></span><span class="preprocessor">#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1</span></div>
|
||
<div class="line"><a id="l12777" name="l12777"></a><span class="lineno">12777</span> </div>
|
||
<div class="line"><a id="l12778" name="l12778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b4e702f6496841d60bc7ada8d68d648">12778</a></span><span class="preprocessor">#define WWDG_CFR_EWI_Pos (9U) </span></div>
|
||
<div class="line"><a id="l12779" name="l12779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca4ed7e970421b1b4b4b0f94e3296117">12779</a></span><span class="preprocessor">#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) </span></div>
|
||
<div class="line"><a id="l12780" name="l12780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga931941dc5d795502371ac5dd8fbac1e9">12780</a></span><span class="preprocessor">#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk </span></div>
|
||
<div class="line"><a id="l12782" name="l12782"></a><span class="lineno">12782</span><span class="comment">/******************* Bit definition for WWDG_SR register ********************/</span></div>
|
||
<div class="line"><a id="l12783" name="l12783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4c37d2819f82d4cec6c8c9a9250ee43">12783</a></span><span class="preprocessor">#define WWDG_SR_EWIF_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12784" name="l12784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga284cdb5e7c17598a03a9a0790dd7508c">12784</a></span><span class="preprocessor">#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) </span></div>
|
||
<div class="line"><a id="l12785" name="l12785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96cf9ddd91b6079c5aceef6f3e857b69">12785</a></span><span class="preprocessor">#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk </span></div>
|
||
<div class="line"><a id="l12788" name="l12788"></a><span class="lineno">12788</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l12789" name="l12789"></a><span class="lineno">12789</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l12790" name="l12790"></a><span class="lineno">12790</span><span class="comment">/* DBG */</span></div>
|
||
<div class="line"><a id="l12791" name="l12791"></a><span class="lineno">12791</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l12792" name="l12792"></a><span class="lineno">12792</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l12793" name="l12793"></a><span class="lineno">12793</span><span class="comment">/******************** Bit definition for DBGMCU_IDCODE register *************/</span></div>
|
||
<div class="line"><a id="l12794" name="l12794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad05a229877e557798dfbabe7188d7a54">12794</a></span><span class="preprocessor">#define DBGMCU_IDCODE_DEV_ID_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12795" name="l12795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf18661126fecb64b8c7d7d4e590fb33">12795</a></span><span class="preprocessor">#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) </span></div>
|
||
<div class="line"><a id="l12796" name="l12796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd961fcddc40341a817a9ec85b7c80ac">12796</a></span><span class="preprocessor">#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk </span></div>
|
||
<div class="line"><a id="l12797" name="l12797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e98f7579d16c36cbf6a09b04f2ee170">12797</a></span><span class="preprocessor">#define DBGMCU_IDCODE_REV_ID_Pos (16U) </span></div>
|
||
<div class="line"><a id="l12798" name="l12798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d92c620aed9b19c7e8d9d12f743b258">12798</a></span><span class="preprocessor">#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) </span></div>
|
||
<div class="line"><a id="l12799" name="l12799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga887eb26364a8693355024ca203323165">12799</a></span><span class="preprocessor">#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk </span></div>
|
||
<div class="line"><a id="l12800" name="l12800"></a><span class="lineno">12800</span> </div>
|
||
<div class="line"><a id="l12801" name="l12801"></a><span class="lineno">12801</span><span class="comment">/******************** Bit definition for DBGMCU_CR register *****************/</span></div>
|
||
<div class="line"><a id="l12802" name="l12802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b996a2be01fbeeaa868603c7bca6044">12802</a></span><span class="preprocessor">#define DBGMCU_CR_DBG_SLEEP_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12803" name="l12803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga127e0531bc305bb460fd2417106bee61">12803</a></span><span class="preprocessor">#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) </span></div>
|
||
<div class="line"><a id="l12804" name="l12804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga037c80fe1d7308cee68245715ef6cd9a">12804</a></span><span class="preprocessor">#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk </span></div>
|
||
<div class="line"><a id="l12805" name="l12805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga998b25ffd43297001c2f20ebb04fbcc9">12805</a></span><span class="preprocessor">#define DBGMCU_CR_DBG_STOP_Pos (1U) </span></div>
|
||
<div class="line"><a id="l12806" name="l12806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71cd122085cdadba462f9e251ac35349">12806</a></span><span class="preprocessor">#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12807" name="l12807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf511f21a8de5b0b66c862915eee8bf75">12807</a></span><span class="preprocessor">#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12808" name="l12808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74521b2e06cd16f46ea5987d82f9ff19">12808</a></span><span class="preprocessor">#define DBGMCU_CR_DBG_STANDBY_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12809" name="l12809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52e9a797b04f9577456af2499f5bd9ff">12809</a></span><span class="preprocessor">#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) </span></div>
|
||
<div class="line"><a id="l12810" name="l12810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga107a9396d63c892a8e614897c9d0b132">12810</a></span><span class="preprocessor">#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk </span></div>
|
||
<div class="line"><a id="l12811" name="l12811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2be1af4b18b8c9ce4001dd363e6626e7">12811</a></span><span class="preprocessor">#define DBGMCU_CR_TRACE_IOEN_Pos (5U) </span></div>
|
||
<div class="line"><a id="l12812" name="l12812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18007dc2c11d41a5dc449e37cb8c0c56">12812</a></span><span class="preprocessor">#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) </span></div>
|
||
<div class="line"><a id="l12813" name="l12813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9034b6eb9d4dceadffc6a1d1959056c9">12813</a></span><span class="preprocessor">#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk </span></div>
|
||
<div class="line"><a id="l12814" name="l12814"></a><span class="lineno">12814</span> </div>
|
||
<div class="line"><a id="l12815" name="l12815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20dddffa934315ca4a5902cbf45f4d93">12815</a></span><span class="preprocessor">#define DBGMCU_CR_TRACE_MODE_Pos (6U) </span></div>
|
||
<div class="line"><a id="l12816" name="l12816"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad641a08b344645d47a0789ffa25d7079">12816</a></span><span class="preprocessor">#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) </span></div>
|
||
<div class="line"><a id="l12817" name="l12817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1395189e10bdbc37bce9ea480e22d10">12817</a></span><span class="preprocessor">#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk </span></div>
|
||
<div class="line"><a id="l12818" name="l12818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d41a4027853783633d929a43f8d6d85">12818</a></span><span class="preprocessor">#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) </span></div>
|
||
<div class="line"><a id="l12819" name="l12819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ba3a830051b53d43d850768242c503e">12819</a></span><span class="preprocessor">#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) </span></div>
|
||
<div class="line"><a id="l12821" name="l12821"></a><span class="lineno">12821</span><span class="comment">/******************** Bit definition for DBGMCU_APB1_FZ register ************/</span></div>
|
||
<div class="line"><a id="l12822" name="l12822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1de6489ecedec59891894a54458bef2">12822</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12823" name="l12823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf96a2b1fb00169f78d3c8fb050ca35be">12823</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12824" name="l12824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae3c5b87084934a18748f5ec168f5aef">12824</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12825" name="l12825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bd5fd9c34fd75ddb5c77d526f8f53a1">12825</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) </span></div>
|
||
<div class="line"><a id="l12826" name="l12826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab210ab764b68711904243c0d11631b8">12826</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12827" name="l12827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fea6834f4ef9fc6b403cd079a001cec">12827</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12828" name="l12828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeef66d67708ae915fbbc2ee76aeaef3e">12828</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12829" name="l12829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7dfb56349db84ef1ef5753e13cf2f48">12829</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12830" name="l12830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ac65bf9342bb8acbcb25938e93abc45">12830</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12831" name="l12831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5218cc7d400bfb220c42a80b3a2a0603">12831</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U) </span></div>
|
||
<div class="line"><a id="l12832" name="l12832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4e288f717db03126942d03a1a6fafd8">12832</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12833" name="l12833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42d29d40515d36ce6ed7e5d34ed17dcf">12833</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12834" name="l12834"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf603706e632bf2df878b8ba6fc0c4736">12834</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12835" name="l12835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3215a197f13b82287892283886326d1">12835</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12836" name="l12836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadea6a1e90739bcf1d0723a0566c66de7">12836</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12837" name="l12837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8568c72922b902663a7ade0e9d6cb88">12837</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) </span></div>
|
||
<div class="line"><a id="l12838" name="l12838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29df0ea459e1900942f3e26141e0f9dd">12838</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12839" name="l12839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdade78c3d28a668f9826d0b72e5844b">12839</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12840" name="l12840"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9db1b0c37f083a12d94bbf6beeb4516e">12840</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U) </span></div>
|
||
<div class="line"><a id="l12841" name="l12841"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfcabcb2e0efbe9e76b3eae58b30943b">12841</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12842" name="l12842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ca0e04ad8c94e5b7fe29d8b9c20ebff">12842</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12843" name="l12843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab27cca037c1de40bf8855316c266abd2">12843</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12844" name="l12844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e25332c23efcacd48317de37e337af6">12844</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12845" name="l12845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68ef63b3c086ede54396596798553299">12845</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12846" name="l12846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf940f736a0f2e4531d141e53257e4e6d">12846</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12847" name="l12847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeec836ee0ced45ad06aa4b025f13987e">12847</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12848" name="l12848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd3acb3e632c74e326da7016073c7871">12848</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12849" name="l12849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga004684cb88ffb723509a9ca4193e78ec">12849</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12850" name="l12850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7fefeace05cb28675d23037f7b3966a">12850</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12851" name="l12851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e20246d389229ff46006b405bb56b1d">12851</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12852" name="l12852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaad459d6930c29babb7672cd26d0ea9b">12852</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) </span></div>
|
||
<div class="line"><a id="l12853" name="l12853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f24695b718a52f4a91297ee3c512db4">12853</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12854" name="l12854"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a49d5e849185d09ee6c7594512ffe88">12854</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12855" name="l12855"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bb0a55a4b7c9c3deeb61568b9c7e85c">12855</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) </span></div>
|
||
<div class="line"><a id="l12856" name="l12856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a7937e3a29764f7e80895b8fbe81baa">12856</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12857" name="l12857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada8989cb96dd5d6dbdaaf16e1f127c6a">12857</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12858" name="l12858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga303e9dea0617bb3f03a8cc825005d6ce">12858</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) </span></div>
|
||
<div class="line"><a id="l12859" name="l12859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga202de646d5890eec98b04ad2be808604">12859</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) </span></div>
|
||
<div class="line"><a id="l12860" name="l12860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae83fb5d62c6e6fa1c2fd06084528404e">12860</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk </span></div>
|
||
<div class="line"><a id="l12861" name="l12861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc66781299067fbbec7d1be708314c17">12861</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) </span></div>
|
||
<div class="line"><a id="l12862" name="l12862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae03e6603b8d1af65a2b5c026c8379908">12862</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) </span></div>
|
||
<div class="line"><a id="l12863" name="l12863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f6320aba695f6c3f97608e478533e96">12863</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk </span></div>
|
||
<div class="line"><a id="l12864" name="l12864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c17ca25c071d846eeecdc761f590bf0">12864</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U) </span></div>
|
||
<div class="line"><a id="l12865" name="l12865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ebb7cd7e57d8d9888025cfbdea082b4">12865</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) </span></div>
|
||
<div class="line"><a id="l12866" name="l12866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f7e5c708387aa1ddae35b892811b4e9">12866</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk </span></div>
|
||
<div class="line"><a id="l12867" name="l12867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf44a606db87b49504fc17760eba9290d">12867</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U) </span></div>
|
||
<div class="line"><a id="l12868" name="l12868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72cf0d5d23a0ac36f3c4c5515082221d">12868</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12869" name="l12869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b404dcea4857bccabbb03d6cce6be8c">12869</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12870" name="l12870"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac38ce10efced0708fe63650e0f855c3d">12870</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U) </span></div>
|
||
<div class="line"><a id="l12871" name="l12871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6c0ae534d156b18cd9254ab942f88ff">12871</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12872" name="l12872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadc3889d6b84d143c98ecbfd873a9a1a">12872</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12873" name="l12873"></a><span class="lineno">12873</span><span class="comment">/* Old IWDGSTOP bit definition, maintained for legacy purpose */</span></div>
|
||
<div class="line"><a id="l12874" name="l12874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe48f858edb831fbcb8769421df7d8e9">12874</a></span><span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP</span></div>
|
||
<div class="line"><a id="l12875" name="l12875"></a><span class="lineno">12875</span> </div>
|
||
<div class="line"><a id="l12876" name="l12876"></a><span class="lineno">12876</span><span class="comment">/******************** Bit definition for DBGMCU_APB2_FZ register ************/</span></div>
|
||
<div class="line"><a id="l12877" name="l12877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b30844d430324cfe63e4932275a6978">12877</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12878" name="l12878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74cb9644d7d1eaf1a71254121f926169">12878</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12879" name="l12879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3eb7be194b6ffb258b9e9f5ed08a931e">12879</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12880" name="l12880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac84a0fb177332acd69c944aa00e90340">12880</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U) </span></div>
|
||
<div class="line"><a id="l12881" name="l12881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98002708ee350ecf61a72911df9850b5">12881</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12882" name="l12882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37128bf689254919b07f64ee41cad1cf">12882</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12883" name="l12883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6fc3b8c8d5cbb8695e7cec3153bbe65">12883</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U) </span></div>
|
||
<div class="line"><a id="l12884" name="l12884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga983432f2957617c4215fe406dd932080">12884</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12885" name="l12885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf12c17533a1e3262ee11f760e44f5127">12885</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12886" name="l12886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2eb21a02384033248b1e45030a314598">12886</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U) </span></div>
|
||
<div class="line"><a id="l12887" name="l12887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9390f2c13a5b525bd1e7bbd6501c7a67">12887</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12888" name="l12888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24d4bbf803a65e8202b0019ed0ce0ebb">12888</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12889" name="l12889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0dd5b307e8d9992857942180b6f7358f">12889</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U) </span></div>
|
||
<div class="line"><a id="l12890" name="l12890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea914b4c8a46cb0be4909dfd4e3199d6">12890</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) </span></div>
|
||
<div class="line"><a id="l12891" name="l12891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga354671c942db40e69820fd783ef955b4">12891</a></span><span class="preprocessor">#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk </span></div>
|
||
<div class="line"><a id="l12892" name="l12892"></a><span class="lineno">12892</span> </div>
|
||
<div class="line"><a id="l12893" name="l12893"></a><span class="lineno">12893</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l12894" name="l12894"></a><span class="lineno">12894</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l12895" name="l12895"></a><span class="lineno">12895</span><span class="comment">/* Ethernet MAC Registers bits definitions */</span></div>
|
||
<div class="line"><a id="l12896" name="l12896"></a><span class="lineno">12896</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l12897" name="l12897"></a><span class="lineno">12897</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l12898" name="l12898"></a><span class="lineno">12898</span><span class="comment">/* Bit definition for Ethernet MAC Control Register register */</span></div>
|
||
<div class="line"><a id="l12899" name="l12899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae59108fa4b2f56d375f7b7b2e7d50e30">12899</a></span><span class="preprocessor">#define ETH_MACCR_WD_Pos (23U) </span></div>
|
||
<div class="line"><a id="l12900" name="l12900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6dbb23089a2b3d19fd5deb5009a527f3">12900</a></span><span class="preprocessor">#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) </span></div>
|
||
<div class="line"><a id="l12901" name="l12901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b90fbae827b1368b83cd9b0d9c64cc8">12901</a></span><span class="preprocessor">#define ETH_MACCR_WD ETH_MACCR_WD_Msk </span><span class="comment">/* Watchdog disable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12902" name="l12902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96003f027aa496dc4345472db3b60f10">12902</a></span><span class="preprocessor">#define ETH_MACCR_JD_Pos (22U) </span></div>
|
||
<div class="line"><a id="l12903" name="l12903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab36b8e9295e605680052d61f262843fc">12903</a></span><span class="preprocessor">#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) </span></div>
|
||
<div class="line"><a id="l12904" name="l12904"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ef1243e257142caa99c086b07fa5d42">12904</a></span><span class="preprocessor">#define ETH_MACCR_JD ETH_MACCR_JD_Msk </span><span class="comment">/* Jabber disable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12905" name="l12905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ef65cca0d90f5944aefd63db1505323">12905</a></span><span class="preprocessor">#define ETH_MACCR_IFG_Pos (17U) </span></div>
|
||
<div class="line"><a id="l12906" name="l12906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0081ebdecc02644f5a0a5304478e2f9c">12906</a></span><span class="preprocessor">#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos) </span></div>
|
||
<div class="line"><a id="l12907" name="l12907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga989c71f66d1361519d2b0586f30b148f">12907</a></span><span class="preprocessor">#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk </span><span class="comment">/* Inter-frame gap */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12908" name="l12908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga004e9dab4a5e1ed4f165facca6fd80aa">12908</a></span><span class="preprocessor">#define ETH_MACCR_IFG_96Bit 0x00000000U </span><span class="comment">/* Minimum IFG between frames during transmission is 96Bit */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12909" name="l12909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf0f2ad0cd583f00dd2739cbb3dbdeea">12909</a></span><span class="preprocessor">#define ETH_MACCR_IFG_88Bit 0x00020000U </span><span class="comment">/* Minimum IFG between frames during transmission is 88Bit */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12910" name="l12910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56adc3166c71f29d2d30efc6ed3a4369">12910</a></span><span class="preprocessor">#define ETH_MACCR_IFG_80Bit 0x00040000U </span><span class="comment">/* Minimum IFG between frames during transmission is 80Bit */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12911" name="l12911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2e77bc6fa5effe78706bfda4a51d1e2">12911</a></span><span class="preprocessor">#define ETH_MACCR_IFG_72Bit 0x00060000U </span><span class="comment">/* Minimum IFG between frames during transmission is 72Bit */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12912" name="l12912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75c191358878ffd90ad6a6af336b935b">12912</a></span><span class="preprocessor">#define ETH_MACCR_IFG_64Bit 0x00080000U </span><span class="comment">/* Minimum IFG between frames during transmission is 64Bit */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12913" name="l12913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebea1ff24623d7ba11f9eea98cd5466b">12913</a></span><span class="preprocessor">#define ETH_MACCR_IFG_56Bit 0x000A0000U </span><span class="comment">/* Minimum IFG between frames during transmission is 56Bit */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12914" name="l12914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8984fcb3cf6fb85c26878d9341324d77">12914</a></span><span class="preprocessor">#define ETH_MACCR_IFG_48Bit 0x000C0000U </span><span class="comment">/* Minimum IFG between frames during transmission is 48Bit */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12915" name="l12915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bc414a4c1360538a9ccbea64009d581">12915</a></span><span class="preprocessor">#define ETH_MACCR_IFG_40Bit 0x000E0000U </span><span class="comment">/* Minimum IFG between frames during transmission is 40Bit */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12916" name="l12916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga588e9336435c218354a75fc12f8bf612">12916</a></span><span class="preprocessor">#define ETH_MACCR_CSD_Pos (16U) </span></div>
|
||
<div class="line"><a id="l12917" name="l12917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad18e8d3284ce4ec318027d9f3d8ca491">12917</a></span><span class="preprocessor">#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos) </span></div>
|
||
<div class="line"><a id="l12918" name="l12918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad298d344663cc1213716b5981c61682c">12918</a></span><span class="preprocessor">#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk </span><span class="comment">/* Carrier sense disable (during transmission) */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12919" name="l12919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6147083b9250f2eb3364b02195fe737c">12919</a></span><span class="preprocessor">#define ETH_MACCR_FES_Pos (14U) </span></div>
|
||
<div class="line"><a id="l12920" name="l12920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f5dd4cb0742fd13187a8c200bb1f041">12920</a></span><span class="preprocessor">#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) </span></div>
|
||
<div class="line"><a id="l12921" name="l12921"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafaa2d12a706f5c166e1ed620ec53177c">12921</a></span><span class="preprocessor">#define ETH_MACCR_FES ETH_MACCR_FES_Msk </span><span class="comment">/* Fast ethernet speed */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12922" name="l12922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bbbcddaca5d36eea8da9241ece9bc03">12922</a></span><span class="preprocessor">#define ETH_MACCR_ROD_Pos (13U) </span></div>
|
||
<div class="line"><a id="l12923" name="l12923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7217c59c6e0a4c0fa327e7f5b40a435b">12923</a></span><span class="preprocessor">#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos) </span></div>
|
||
<div class="line"><a id="l12924" name="l12924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13f0065edda127d3f1fb6e88ca6f465b">12924</a></span><span class="preprocessor">#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk </span><span class="comment">/* Receive own disable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12925" name="l12925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59f9e595778a163299e230ac6fe01b07">12925</a></span><span class="preprocessor">#define ETH_MACCR_LM_Pos (12U) </span></div>
|
||
<div class="line"><a id="l12926" name="l12926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8a68cc960648c12120c8b374bdd8716">12926</a></span><span class="preprocessor">#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) </span></div>
|
||
<div class="line"><a id="l12927" name="l12927"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38ad823b7d50c85fc620a9a93d250d54">12927</a></span><span class="preprocessor">#define ETH_MACCR_LM ETH_MACCR_LM_Msk </span><span class="comment">/* loopback mode */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12928" name="l12928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3fb4a84c106fe35457d37c5b64c3329">12928</a></span><span class="preprocessor">#define ETH_MACCR_DM_Pos (11U) </span></div>
|
||
<div class="line"><a id="l12929" name="l12929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36a3d885827efdd8dff930201dfee8cb">12929</a></span><span class="preprocessor">#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) </span></div>
|
||
<div class="line"><a id="l12930" name="l12930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83e463b0497de6801773acd7984722b2">12930</a></span><span class="preprocessor">#define ETH_MACCR_DM ETH_MACCR_DM_Msk </span><span class="comment">/* Duplex mode */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12931" name="l12931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2debc54904a0cd2e8075c18b06b04607">12931</a></span><span class="preprocessor">#define ETH_MACCR_IPCO_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12932" name="l12932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8366318e6b656e2f84664b29cf67d4f5">12932</a></span><span class="preprocessor">#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos) </span></div>
|
||
<div class="line"><a id="l12933" name="l12933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbd6f6975a04c0ded0e1a9e98035e802">12933</a></span><span class="preprocessor">#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk </span><span class="comment">/* IP Checksum offload */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12934" name="l12934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab08db3705923934f19f57878b6aee621">12934</a></span><span class="preprocessor">#define ETH_MACCR_RD_Pos (9U) </span></div>
|
||
<div class="line"><a id="l12935" name="l12935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab35d6a69246d8b8e0df616af385338d8">12935</a></span><span class="preprocessor">#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos) </span></div>
|
||
<div class="line"><a id="l12936" name="l12936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2771077782e2dcac94367e54353696e">12936</a></span><span class="preprocessor">#define ETH_MACCR_RD ETH_MACCR_RD_Msk </span><span class="comment">/* Retry disable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12937" name="l12937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf11af5805335ea5bf4a581746770169">12937</a></span><span class="preprocessor">#define ETH_MACCR_APCS_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12938" name="l12938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64b76db821d5aacb94dd0ad98b9343b1">12938</a></span><span class="preprocessor">#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos) </span></div>
|
||
<div class="line"><a id="l12939" name="l12939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b5d2fe7260609d8186a7005f925dc28">12939</a></span><span class="preprocessor">#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk </span><span class="comment">/* Automatic Pad/CRC stripping */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12940" name="l12940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14f95db9a825ce4e8f6cd28c5451bad3">12940</a></span><span class="preprocessor">#define ETH_MACCR_BL_Pos (5U) </span></div>
|
||
<div class="line"><a id="l12941" name="l12941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ec3ac5f3f2541425180e8a899d3501f">12941</a></span><span class="preprocessor">#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) </span></div>
|
||
<div class="line"><a id="l12942" name="l12942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0fab432a0d01c8c1786b3d48489c0f9">12942</a></span><span class="preprocessor">#define ETH_MACCR_BL ETH_MACCR_BL_Msk </span><span class="comment">/* Back-off limit: random integer number (r) of slot time delays before rescheduling</span></div>
|
||
<div class="line"><a id="l12943" name="l12943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9bc0bcf13d6a51de76a67299ba40561f">12943</a></span><span class="comment"> a transmission attempt during retries after a collision: 0 =< r <2^k */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12944" name="l12944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga135a78ac267e35d598ed17aa776a1505">12944</a></span><span class="preprocessor">#define ETH_MACCR_BL_10 0x00000000U </span><span class="comment">/* k = min (n, 10) */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12945" name="l12945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d5f35dc63a68792a4abfaf9d11a2feb">12945</a></span><span class="preprocessor">#define ETH_MACCR_BL_8 0x00000020U </span><span class="comment">/* k = min (n, 8) */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12946" name="l12946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf4db303c5f5822875770938f7cfb7c5">12946</a></span><span class="preprocessor">#define ETH_MACCR_BL_4 0x00000040U </span><span class="comment">/* k = min (n, 4) */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12947" name="l12947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacec9ce3aee181fbc67675464bace4292">12947</a></span><span class="preprocessor">#define ETH_MACCR_BL_1 0x00000060U </span><span class="comment">/* k = min (n, 1) */</span><span class="preprocessor"> </span></div>
|
||
<div class="line"><a id="l12948" name="l12948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga725e7bba118c5f2780295c555a3ba916">12948</a></span><span class="preprocessor">#define ETH_MACCR_DC_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12949" name="l12949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90347f47e9623d4714e0631b1afbccc9">12949</a></span><span class="preprocessor">#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) </span></div>
|
||
<div class="line"><a id="l12950" name="l12950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad47f85fd08360f1244faff9cd913029c">12950</a></span><span class="preprocessor">#define ETH_MACCR_DC ETH_MACCR_DC_Msk </span><span class="comment">/* Defferal check */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12951" name="l12951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddcad0319763dc5cdb282dda26a50634">12951</a></span><span class="preprocessor">#define ETH_MACCR_TE_Pos (3U) </span></div>
|
||
<div class="line"><a id="l12952" name="l12952"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87c3818396ef51cad8be1f4c68fff164">12952</a></span><span class="preprocessor">#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) </span></div>
|
||
<div class="line"><a id="l12953" name="l12953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8c13b3b7d19a9a11df6ae71c01de129">12953</a></span><span class="preprocessor">#define ETH_MACCR_TE ETH_MACCR_TE_Msk </span><span class="comment">/* Transmitter enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12954" name="l12954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga074212b9bb2b4d5991e91277fdd6b18a">12954</a></span><span class="preprocessor">#define ETH_MACCR_RE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12955" name="l12955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77984e7a5202bdc300bccc9cc90fad3e">12955</a></span><span class="preprocessor">#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) </span></div>
|
||
<div class="line"><a id="l12956" name="l12956"></a><span class="lineno">12956</span><span class="preprocessor">#define ETH_MACCR_RE ETH_MACCR_RE_Msk </span><span class="comment">/* Receiver enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12957" name="l12957"></a><span class="lineno">12957</span> </div>
|
||
<div class="line"><a id="l12958" name="l12958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaaefa92c0f1afda53c779ae046f1bc8e">12958</a></span><span class="comment">/* Bit definition for Ethernet MAC Frame Filter Register */</span></div>
|
||
<div class="line"><a id="l12959" name="l12959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a98d8a880edf71d2b6fbf245adcbe4b">12959</a></span><span class="preprocessor">#define ETH_MACFFR_RA_Pos (31U) </span></div>
|
||
<div class="line"><a id="l12960" name="l12960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7970ce2fd938029f0a58cf668a82a0fb">12960</a></span><span class="preprocessor">#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos) </span></div>
|
||
<div class="line"><a id="l12961" name="l12961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f40208cefa46427f9038e48add7d195">12961</a></span><span class="preprocessor">#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk </span><span class="comment">/* Receive all */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12962" name="l12962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cb1611ef661179353862262e5685c53">12962</a></span><span class="preprocessor">#define ETH_MACFFR_HPF_Pos (10U) </span></div>
|
||
<div class="line"><a id="l12963" name="l12963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b902b5561e392e47ce5d66275902e29">12963</a></span><span class="preprocessor">#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos) </span></div>
|
||
<div class="line"><a id="l12964" name="l12964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa74c10f8950aa00a4ecab37d9fecac9">12964</a></span><span class="preprocessor">#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk </span><span class="comment">/* Hash or perfect filter */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12965" name="l12965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3aad930295c276453e51c416902b52cc">12965</a></span><span class="preprocessor">#define ETH_MACFFR_SAF_Pos (9U) </span></div>
|
||
<div class="line"><a id="l12966" name="l12966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e710eda13cca42c8da46d5d37f34552">12966</a></span><span class="preprocessor">#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos) </span></div>
|
||
<div class="line"><a id="l12967" name="l12967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga848f235f8e37e0293fc51aaa8b8b642e">12967</a></span><span class="preprocessor">#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk </span><span class="comment">/* Source address filter enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12968" name="l12968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabfa7482e8b8e0d949875ed2e94f3b5f7">12968</a></span><span class="preprocessor">#define ETH_MACFFR_SAIF_Pos (8U) </span></div>
|
||
<div class="line"><a id="l12969" name="l12969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa351de2818df9599ce6b3378ca31f87">12969</a></span><span class="preprocessor">#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos) </span></div>
|
||
<div class="line"><a id="l12970" name="l12970"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf59b0fd52b7f31dd5fa99ed3e0db1f24">12970</a></span><span class="preprocessor">#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk </span><span class="comment">/* SA inverse filtering */</span><span class="preprocessor"> </span></div>
|
||
<div class="line"><a id="l12971" name="l12971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga066564941ff14e4ee4110870be454835">12971</a></span><span class="preprocessor">#define ETH_MACFFR_PCF_Pos (6U) </span></div>
|
||
<div class="line"><a id="l12972" name="l12972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25724ed070e5948cb5541d890d2af603">12972</a></span><span class="preprocessor">#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos) </span></div>
|
||
<div class="line"><a id="l12973" name="l12973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafae24adcc21beedcf4d3668b07d9211d">12973</a></span><span class="preprocessor">#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk </span><span class="comment">/* Pass control frames: 3 cases */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12974" name="l12974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5382075fb7e487b0c2a1a97f0c1d0276">12974</a></span><span class="preprocessor">#define ETH_MACFFR_PCF_BlockAll_Pos (6U) </span></div>
|
||
<div class="line"><a id="l12975" name="l12975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9bcec681af42037508574944fe68d6ff">12975</a></span><span class="preprocessor">#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) </span></div>
|
||
<div class="line"><a id="l12976" name="l12976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9495c05d01a26d63e6c87461d5440410">12976</a></span><span class="preprocessor">#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk </span><span class="comment">/* MAC filters all control frames from reaching the application */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12977" name="l12977"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga600b088ad4e2326651b1b8d066a85a0c">12977</a></span><span class="preprocessor">#define ETH_MACFFR_PCF_ForwardAll_Pos (7U) </span></div>
|
||
<div class="line"><a id="l12978" name="l12978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf694466716e26c52452e21ce2a76f2fe">12978</a></span><span class="preprocessor">#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) </span></div>
|
||
<div class="line"><a id="l12979" name="l12979"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae90264da6a4c411fc2de7ed84c21de1b">12979</a></span><span class="preprocessor">#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk </span><span class="comment">/* MAC forwards all control frames to application even if they fail the Address Filter */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12980" name="l12980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85f6303d1d492b59bb26034343e3a4df">12980</a></span><span class="preprocessor">#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U) </span></div>
|
||
<div class="line"><a id="l12981" name="l12981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3e83e62d864be50e58455719d6df217">12981</a></span><span class="preprocessor">#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) </span></div>
|
||
<div class="line"><a id="l12982" name="l12982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac8a275e8b823431da6aa47d36271ce5">12982</a></span><span class="preprocessor">#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk </span><span class="comment">/* MAC forwards control frames that pass the Address Filter. */</span><span class="preprocessor"> </span></div>
|
||
<div class="line"><a id="l12983" name="l12983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb4108d0862a690e04665be0fc04412d">12983</a></span><span class="preprocessor">#define ETH_MACFFR_BFD_Pos (5U) </span></div>
|
||
<div class="line"><a id="l12984" name="l12984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fea3f3e6b264e362a84675e09f33cbd">12984</a></span><span class="preprocessor">#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos) </span></div>
|
||
<div class="line"><a id="l12985" name="l12985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2a5d3a1ce969272150c55c2a0f66143">12985</a></span><span class="preprocessor">#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk </span><span class="comment">/* Broadcast frame disable */</span><span class="preprocessor"> </span></div>
|
||
<div class="line"><a id="l12986" name="l12986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga118b021e83c7e4ba113c17eca935e538">12986</a></span><span class="preprocessor">#define ETH_MACFFR_PAM_Pos (4U) </span></div>
|
||
<div class="line"><a id="l12987" name="l12987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafaa7da9e50e9ecf39bdc614c01bc22e">12987</a></span><span class="preprocessor">#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos) </span></div>
|
||
<div class="line"><a id="l12988" name="l12988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5a60d5a987a14e474d8782af855e6f5">12988</a></span><span class="preprocessor">#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk </span><span class="comment">/* Pass all mutlicast */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12989" name="l12989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c15d55d7f391f42bd8751d76da28480">12989</a></span><span class="preprocessor">#define ETH_MACFFR_DAIF_Pos (3U) </span></div>
|
||
<div class="line"><a id="l12990" name="l12990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f50c885917d6df63e6250a530a9ce0c">12990</a></span><span class="preprocessor">#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos) </span></div>
|
||
<div class="line"><a id="l12991" name="l12991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cdf71d283afa6f77ce261fe5e197b92">12991</a></span><span class="preprocessor">#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk </span><span class="comment">/* DA Inverse filtering */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12992" name="l12992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3c33afcbb8d2ae59624915dc1bd2620">12992</a></span><span class="preprocessor">#define ETH_MACFFR_HM_Pos (2U) </span></div>
|
||
<div class="line"><a id="l12993" name="l12993"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaab1e7a61949844d578d7580b9d2c143">12993</a></span><span class="preprocessor">#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos) </span></div>
|
||
<div class="line"><a id="l12994" name="l12994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4087aca0085083cb8f5ce7a5842f42dc">12994</a></span><span class="preprocessor">#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk </span><span class="comment">/* Hash multicast */</span><span class="preprocessor"> </span></div>
|
||
<div class="line"><a id="l12995" name="l12995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d738065b86ca7845927a39e9b06846a">12995</a></span><span class="preprocessor">#define ETH_MACFFR_HU_Pos (1U) </span></div>
|
||
<div class="line"><a id="l12996" name="l12996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d925e8aa55a6b07772f86abce601529">12996</a></span><span class="preprocessor">#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos) </span></div>
|
||
<div class="line"><a id="l12997" name="l12997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3bf7fe779fc85379362777f881c8a2c">12997</a></span><span class="preprocessor">#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk </span><span class="comment">/* Hash unicast */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l12998" name="l12998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46fc57cc116b06aab750055588f841de">12998</a></span><span class="preprocessor">#define ETH_MACFFR_PM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l12999" name="l12999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga168f5e4a3eb11474c65396d75c07e086">12999</a></span><span class="preprocessor">#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos) </span></div>
|
||
<div class="line"><a id="l13000" name="l13000"></a><span class="lineno">13000</span><span class="preprocessor">#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk </span><span class="comment">/* Promiscuous mode */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13001" name="l13001"></a><span class="lineno">13001</span> </div>
|
||
<div class="line"><a id="l13002" name="l13002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef7a817f06b2aafafe6ff3210a3c41af">13002</a></span><span class="comment">/* Bit definition for Ethernet MAC Hash Table High Register */</span></div>
|
||
<div class="line"><a id="l13003" name="l13003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18191f472ac5fce293cc159e03ecf323">13003</a></span><span class="preprocessor">#define ETH_MACHTHR_HTH_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13004" name="l13004"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee61bc9033449996ae9f8f701b3bae23">13004</a></span><span class="preprocessor">#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) </span></div>
|
||
<div class="line"><a id="l13005" name="l13005"></a><span class="lineno">13005</span><span class="preprocessor">#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk </span><span class="comment">/* Hash table high */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13006" name="l13006"></a><span class="lineno">13006</span> </div>
|
||
<div class="line"><a id="l13007" name="l13007"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d7f015b0b97de99d91eee7ab01e5d5f">13007</a></span><span class="comment">/* Bit definition for Ethernet MAC Hash Table Low Register */</span></div>
|
||
<div class="line"><a id="l13008" name="l13008"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga263c1c48202e6c9c8ce639ef13a8ed85">13008</a></span><span class="preprocessor">#define ETH_MACHTLR_HTL_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13009" name="l13009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac90cb3090f29ee9e5e7d935e8a3f2340">13009</a></span><span class="preprocessor">#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) </span></div>
|
||
<div class="line"><a id="l13010" name="l13010"></a><span class="lineno">13010</span><span class="preprocessor">#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk </span><span class="comment">/* Hash table low */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13011" name="l13011"></a><span class="lineno">13011</span> </div>
|
||
<div class="line"><a id="l13012" name="l13012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf67cfdb4230e5d14ee041303582b91d">13012</a></span><span class="comment">/* Bit definition for Ethernet MAC MII Address Register */</span></div>
|
||
<div class="line"><a id="l13013" name="l13013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga036280a2fcae9747caca79a59f15dbc7">13013</a></span><span class="preprocessor">#define ETH_MACMIIAR_PA_Pos (11U) </span></div>
|
||
<div class="line"><a id="l13014" name="l13014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga712f44a77db4edfaf961e469153e34a4">13014</a></span><span class="preprocessor">#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos) </span></div>
|
||
<div class="line"><a id="l13015" name="l13015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50e38f04aa760a4f72b6d012cfb34f71">13015</a></span><span class="preprocessor">#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk </span><span class="comment">/* Physical layer address */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13016" name="l13016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfed7f5d1d0cb6f84b6442a3afc24496">13016</a></span><span class="preprocessor">#define ETH_MACMIIAR_MR_Pos (6U) </span></div>
|
||
<div class="line"><a id="l13017" name="l13017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2ab5db007b55dca29e98ba3b31f7e66">13017</a></span><span class="preprocessor">#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos) </span></div>
|
||
<div class="line"><a id="l13018" name="l13018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9498fb73edbb94c29ed6ccd963deef4e">13018</a></span><span class="preprocessor">#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk </span><span class="comment">/* MII register in the selected PHY */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13019" name="l13019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c7f3d710de7056d937f76f6f8329b83">13019</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13020" name="l13020"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0747e464ca8bb685ee34d28eb2677c40">13020</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos) </span></div>
|
||
<div class="line"><a id="l13021" name="l13021"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fc1c108e8e7faa35839b3f72b5570d7">13021</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk </span><span class="comment">/* CR clock range: 6 cases */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13022" name="l13022"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad42d271e9f8b028f4b77f9c6214f4b41">13022</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Div42 0x00000000U </span><span class="comment">/* HCLK:60-100 MHz; MDC clock= HCLK/42 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13023" name="l13023"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04311c7087462f41231e89b064c61015">13023</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Div62_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13024" name="l13024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0002142eea07988f854915782bd691c9">13024</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) </span></div>
|
||
<div class="line"><a id="l13025" name="l13025"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad97d20a7f5815f99bcb920d3be101deb">13025</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk </span><span class="comment">/* HCLK:100-150 MHz; MDC clock= HCLK/62 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13026" name="l13026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9eab0313c19320fe59b933c3bd355b15">13026</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Div16_Pos (3U) </span></div>
|
||
<div class="line"><a id="l13027" name="l13027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49474ccdc05637adbc870989373c6535">13027</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) </span></div>
|
||
<div class="line"><a id="l13028" name="l13028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1425435b4fac9a8f965e73d490d9144a">13028</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk </span><span class="comment">/* HCLK:20-35 MHz; MDC clock= HCLK/16 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13029" name="l13029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a42460a599738bc6fe1acfa835e61c1">13029</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Div26_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13030" name="l13030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69a9da5dbeb77d96a729afc82d4f246d">13030</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) </span></div>
|
||
<div class="line"><a id="l13031" name="l13031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8b402724d0798147654bb6a1193146e">13031</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk </span><span class="comment">/* HCLK:35-60 MHz; MDC clock= HCLK/26 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13032" name="l13032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56cbb5a10b42335d5355aab44552c33e">13032</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Div102_Pos (4U) </span></div>
|
||
<div class="line"><a id="l13033" name="l13033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga372d485677cd2e3a995dab470abe66b8">13033</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos) </span></div>
|
||
<div class="line"><a id="l13034" name="l13034"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0697f8d40c21c9b0c3ad91652ab0be4">13034</a></span><span class="preprocessor">#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk </span><span class="comment">/* HCLK:150-168 MHz; MDC clock= HCLK/102 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13035" name="l13035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a13e637f5ae98bda497300e3f65f859">13035</a></span><span class="preprocessor">#define ETH_MACMIIAR_MW_Pos (1U) </span></div>
|
||
<div class="line"><a id="l13036" name="l13036"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffdb940b35822107a5959cdd1ab06482">13036</a></span><span class="preprocessor">#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos) </span></div>
|
||
<div class="line"><a id="l13037" name="l13037"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bb3ef8fa6db10f02a9c54bc8d321fdd">13037</a></span><span class="preprocessor">#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk </span><span class="comment">/* MII write */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13038" name="l13038"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0973869be6711854cdbd8922973cad1f">13038</a></span><span class="preprocessor">#define ETH_MACMIIAR_MB_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13039" name="l13039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e3bd36fdbb97a3ec5b541997bf952aa">13039</a></span><span class="preprocessor">#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos) </span></div>
|
||
<div class="line"><a id="l13040" name="l13040"></a><span class="lineno">13040</span><span class="preprocessor">#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk </span><span class="comment">/* MII busy */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13041" name="l13041"></a><span class="lineno">13041</span> </div>
|
||
<div class="line"><a id="l13042" name="l13042"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ce09ce27fe279dba841d64e3da3824a">13042</a></span><span class="comment">/* Bit definition for Ethernet MAC MII Data Register */</span></div>
|
||
<div class="line"><a id="l13043" name="l13043"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga553476638dac48c385faf4fcfef738a5">13043</a></span><span class="preprocessor">#define ETH_MACMIIDR_MD_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13044" name="l13044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c1226bcd1fc955b69191cd84c1ffe6e">13044</a></span><span class="preprocessor">#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos) </span></div>
|
||
<div class="line"><a id="l13045" name="l13045"></a><span class="lineno">13045</span><span class="preprocessor">#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk </span><span class="comment">/* MII data: read/write data from/to PHY */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13046" name="l13046"></a><span class="lineno">13046</span> </div>
|
||
<div class="line"><a id="l13047" name="l13047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ae35995a0ce92670739ba359d77affc">13047</a></span><span class="comment">/* Bit definition for Ethernet MAC Flow Control Register */</span></div>
|
||
<div class="line"><a id="l13048" name="l13048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ccbe0fdabaaf7f572a77e70af27b949">13048</a></span><span class="preprocessor">#define ETH_MACFCR_PT_Pos (16U) </span></div>
|
||
<div class="line"><a id="l13049" name="l13049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b3bc8574eee69d1bf01d5ab91644bbc">13049</a></span><span class="preprocessor">#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos) </span></div>
|
||
<div class="line"><a id="l13050" name="l13050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab33dfecfb2d574506516b81d6098bd9f">13050</a></span><span class="preprocessor">#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk </span><span class="comment">/* Pause time */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13051" name="l13051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e17d8c6daf50d922b16cff17da9eea6">13051</a></span><span class="preprocessor">#define ETH_MACFCR_ZQPD_Pos (7U) </span></div>
|
||
<div class="line"><a id="l13052" name="l13052"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf34f51c72bc9733694ca11993cc384e1">13052</a></span><span class="preprocessor">#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos) </span></div>
|
||
<div class="line"><a id="l13053" name="l13053"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e9b2183e3ab25eaa732bc9cff1c1179">13053</a></span><span class="preprocessor">#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk </span><span class="comment">/* Zero-quanta pause disable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13054" name="l13054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebd5b76da52c58fd104576b7d2ff7edb">13054</a></span><span class="preprocessor">#define ETH_MACFCR_PLT_Pos (4U) </span></div>
|
||
<div class="line"><a id="l13055" name="l13055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa299b14f248991ea740c352c2e2ec1e5">13055</a></span><span class="preprocessor">#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos) </span></div>
|
||
<div class="line"><a id="l13056" name="l13056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23d3e1992eec79fe65413ab67d3a3850">13056</a></span><span class="preprocessor">#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk </span><span class="comment">/* Pause low threshold: 4 cases */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13057" name="l13057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0a1efb0a76dd9c1cb2b0cb4534e40d3">13057</a></span><span class="preprocessor">#define ETH_MACFCR_PLT_Minus4 0x00000000U </span><span class="comment">/* Pause time minus 4 slot times */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13058" name="l13058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43d3c34bc307b8592c4576e2e1f62a78">13058</a></span><span class="preprocessor">#define ETH_MACFCR_PLT_Minus28_Pos (4U) </span></div>
|
||
<div class="line"><a id="l13059" name="l13059"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga006139afdeadd79e8ead0233a202b3aa">13059</a></span><span class="preprocessor">#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) </span></div>
|
||
<div class="line"><a id="l13060" name="l13060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9824db95c539fb9d35eb4f0c70c78f0">13060</a></span><span class="preprocessor">#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk </span><span class="comment">/* Pause time minus 28 slot times */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13061" name="l13061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9574c5ecc97413442222dbfcda0b50c">13061</a></span><span class="preprocessor">#define ETH_MACFCR_PLT_Minus144_Pos (5U) </span></div>
|
||
<div class="line"><a id="l13062" name="l13062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d71124fba7219f43938d8cc25ba4fad">13062</a></span><span class="preprocessor">#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) </span></div>
|
||
<div class="line"><a id="l13063" name="l13063"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94bf0a9fd09b9e9354a2bf9360bdcd52">13063</a></span><span class="preprocessor">#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk </span><span class="comment">/* Pause time minus 144 slot times */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13064" name="l13064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74132d764aff9d748dcf05fb9b0216ec">13064</a></span><span class="preprocessor">#define ETH_MACFCR_PLT_Minus256_Pos (4U) </span></div>
|
||
<div class="line"><a id="l13065" name="l13065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf55b57c1a06e060afd934e7883a6ebca">13065</a></span><span class="preprocessor">#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) </span></div>
|
||
<div class="line"><a id="l13066" name="l13066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ff0b3e85c3bf432dd589bdab6e76cde">13066</a></span><span class="preprocessor">#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk </span><span class="comment">/* Pause time minus 256 slot times */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13067" name="l13067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80f30740b5201a4a56e2b1a6db8fe48e">13067</a></span><span class="preprocessor">#define ETH_MACFCR_UPFD_Pos (3U) </span></div>
|
||
<div class="line"><a id="l13068" name="l13068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50539e6dcdc828a70c91ab0cb0c1c27c">13068</a></span><span class="preprocessor">#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos) </span></div>
|
||
<div class="line"><a id="l13069" name="l13069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0612f97275b019ca840796bdd79d11e2">13069</a></span><span class="preprocessor">#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk </span><span class="comment">/* Unicast pause frame detect */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13070" name="l13070"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga433c5ff49f74755a37c1311ddc075093">13070</a></span><span class="preprocessor">#define ETH_MACFCR_RFCE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13071" name="l13071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2eec52cb081cdba237e1195fe8c324b">13071</a></span><span class="preprocessor">#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos) </span></div>
|
||
<div class="line"><a id="l13072" name="l13072"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89cab918808d77c19851211503d77e13">13072</a></span><span class="preprocessor">#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk </span><span class="comment">/* Receive flow control enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13073" name="l13073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b5da2d9c9ac891b2d281bf28683ca8d">13073</a></span><span class="preprocessor">#define ETH_MACFCR_TFCE_Pos (1U) </span></div>
|
||
<div class="line"><a id="l13074" name="l13074"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5cd88b7b637bef7a8022270ee02c64a">13074</a></span><span class="preprocessor">#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos) </span></div>
|
||
<div class="line"><a id="l13075" name="l13075"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae98c96a63ef61268f22ba4abec8d811a">13075</a></span><span class="preprocessor">#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk </span><span class="comment">/* Transmit flow control enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13076" name="l13076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabceb72e4e65bfaa290be58922efdb336">13076</a></span><span class="preprocessor">#define ETH_MACFCR_FCBBPA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13077" name="l13077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7dccd98a15d90caf17bcaa6ae13d60a3">13077</a></span><span class="preprocessor">#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos) </span></div>
|
||
<div class="line"><a id="l13078" name="l13078"></a><span class="lineno">13078</span><span class="preprocessor">#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk </span><span class="comment">/* Flow control busy/backpressure activate */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13079" name="l13079"></a><span class="lineno">13079</span> </div>
|
||
<div class="line"><a id="l13080" name="l13080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga425510877d0af2d2dca1daba3d77e4d9">13080</a></span><span class="comment">/* Bit definition for Ethernet MAC VLAN Tag Register */</span></div>
|
||
<div class="line"><a id="l13081" name="l13081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74a0075909956532506d7a507c059ea7">13081</a></span><span class="preprocessor">#define ETH_MACVLANTR_VLANTC_Pos (16U) </span></div>
|
||
<div class="line"><a id="l13082" name="l13082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd45480752cd22efecf0d7465bf49500">13082</a></span><span class="preprocessor">#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos) </span></div>
|
||
<div class="line"><a id="l13083" name="l13083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2584a4fa262f72e82d506a3c49c00ef">13083</a></span><span class="preprocessor">#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk </span><span class="comment">/* 12-bit VLAN tag comparison */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13084" name="l13084"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d9e35eaf745fa9f80be9a7a722031a7">13084</a></span><span class="preprocessor">#define ETH_MACVLANTR_VLANTI_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13085" name="l13085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50874dc921fd523d84621a337aebc53d">13085</a></span><span class="preprocessor">#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) </span></div>
|
||
<div class="line"><a id="l13086" name="l13086"></a><span class="lineno">13086</span><span class="preprocessor">#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk </span><span class="comment">/* VLAN tag identifier (for receive frames) */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13087" name="l13087"></a><span class="lineno">13087</span> </div>
|
||
<div class="line"><a id="l13088" name="l13088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25fbbd599df79ba574b9915e17c91990">13088</a></span><span class="comment">/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */</span> </div>
|
||
<div class="line"><a id="l13089" name="l13089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad54a741a972e56cb46f569b953895bc5">13089</a></span><span class="preprocessor">#define ETH_MACRWUFFR_D_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13090" name="l13090"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae49a607f4dc4ba71c695b3aa2fc0968">13090</a></span><span class="preprocessor">#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) </span></div>
|
||
<div class="line"><a id="l13091" name="l13091"></a><span class="lineno">13091</span><span class="preprocessor">#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk </span><span class="comment">/* Wake-up frame filter register data */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13092" name="l13092"></a><span class="lineno">13092</span><span class="comment">/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.</span></div>
|
||
<div class="line"><a id="l13093" name="l13093"></a><span class="lineno">13093</span><span class="comment"> Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */</span></div>
|
||
<div class="line"><a id="l13094" name="l13094"></a><span class="lineno">13094</span><span class="comment">/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask</span></div>
|
||
<div class="line"><a id="l13095" name="l13095"></a><span class="lineno">13095</span><span class="comment"> Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask</span></div>
|
||
<div class="line"><a id="l13096" name="l13096"></a><span class="lineno">13096</span><span class="comment"> Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask</span></div>
|
||
<div class="line"><a id="l13097" name="l13097"></a><span class="lineno">13097</span><span class="comment"> Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask</span></div>
|
||
<div class="line"><a id="l13098" name="l13098"></a><span class="lineno">13098</span><span class="comment"> Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - </span></div>
|
||
<div class="line"><a id="l13099" name="l13099"></a><span class="lineno">13099</span><span class="comment"> RSVD - Filter1 Command - RSVD - Filter0 Command</span></div>
|
||
<div class="line"><a id="l13100" name="l13100"></a><span class="lineno">13100</span><span class="comment"> Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset</span></div>
|
||
<div class="line"><a id="l13101" name="l13101"></a><span class="lineno">13101</span><span class="comment"> Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16</span></div>
|
||
<div class="line"><a id="l13102" name="l13102"></a><span class="lineno">13102</span><span class="comment"> Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */</span></div>
|
||
<div class="line"><a id="l13103" name="l13103"></a><span class="lineno">13103</span> </div>
|
||
<div class="line"><a id="l13104" name="l13104"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb526c7632b5374dce52fa2beb80a038">13104</a></span><span class="comment">/* Bit definition for Ethernet MAC PMT Control and Status Register */</span> </div>
|
||
<div class="line"><a id="l13105" name="l13105"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fae91e3c9a395769622d32cff6427b3">13105</a></span><span class="preprocessor">#define ETH_MACPMTCSR_WFFRPR_Pos (31U) </span></div>
|
||
<div class="line"><a id="l13106" name="l13106"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeaa7046c581aa1b663c819352930cdd8">13106</a></span><span class="preprocessor">#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) </span></div>
|
||
<div class="line"><a id="l13107" name="l13107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7877c7a6a9ed93454098e79a9a2a6281">13107</a></span><span class="preprocessor">#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk </span><span class="comment">/* Wake-Up Frame Filter Register Pointer Reset */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13108" name="l13108"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f845ccfd867098d3ec25775040a5c8f">13108</a></span><span class="preprocessor">#define ETH_MACPMTCSR_GU_Pos (9U) </span></div>
|
||
<div class="line"><a id="l13109" name="l13109"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c2d01faf67db27fb0b2cfeaf94242b4">13109</a></span><span class="preprocessor">#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos) </span></div>
|
||
<div class="line"><a id="l13110" name="l13110"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfbe013f1b1f93c7274e072c837709b1">13110</a></span><span class="preprocessor">#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk </span><span class="comment">/* Global Unicast */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13111" name="l13111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga832d4cc3d0951c965e6f515125842bc4">13111</a></span><span class="preprocessor">#define ETH_MACPMTCSR_WFR_Pos (6U) </span></div>
|
||
<div class="line"><a id="l13112" name="l13112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga597abfcc1408cb51980fa7a594a6cf30">13112</a></span><span class="preprocessor">#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos) </span></div>
|
||
<div class="line"><a id="l13113" name="l13113"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf1514e6ea9fdddbbb6ce396bee1855a">13113</a></span><span class="preprocessor">#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk </span><span class="comment">/* Wake-Up Frame Received */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13114" name="l13114"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae312b7c783a541e4dc026eef480398dd">13114</a></span><span class="preprocessor">#define ETH_MACPMTCSR_MPR_Pos (5U) </span></div>
|
||
<div class="line"><a id="l13115" name="l13115"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab855f00737fb7f828752e1353c3a1031">13115</a></span><span class="preprocessor">#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos) </span></div>
|
||
<div class="line"><a id="l13116" name="l13116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23adb9148c3a9603d070458e5744df8a">13116</a></span><span class="preprocessor">#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk </span><span class="comment">/* Magic Packet Received */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13117" name="l13117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4898617eb625181689fb6fbeace04705">13117</a></span><span class="preprocessor">#define ETH_MACPMTCSR_WFE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13118" name="l13118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga998f1f5665f94008e39dfabb489faf8e">13118</a></span><span class="preprocessor">#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos) </span></div>
|
||
<div class="line"><a id="l13119" name="l13119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2df8ebbf70fa09790c85774e1f5e8e0">13119</a></span><span class="preprocessor">#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk </span><span class="comment">/* Wake-Up Frame Enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13120" name="l13120"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71fdad55986e5e2b672ea1de7feb542c">13120</a></span><span class="preprocessor">#define ETH_MACPMTCSR_MPE_Pos (1U) </span></div>
|
||
<div class="line"><a id="l13121" name="l13121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81540e67436a755a7692b32a33871f63">13121</a></span><span class="preprocessor">#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos) </span></div>
|
||
<div class="line"><a id="l13122" name="l13122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e7bfb3f7e9212baa158705c26c44498">13122</a></span><span class="preprocessor">#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk </span><span class="comment">/* Magic Packet Enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13123" name="l13123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeaa6826d4d3fd55295dadbc3c3c73873">13123</a></span><span class="preprocessor">#define ETH_MACPMTCSR_PD_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13124" name="l13124"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab454be372dc141b6e515c4389cd18a12">13124</a></span><span class="preprocessor">#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos) </span></div>
|
||
<div class="line"><a id="l13125" name="l13125"></a><span class="lineno">13125</span><span class="preprocessor">#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk </span><span class="comment">/* Power Down */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13126" name="l13126"></a><span class="lineno">13126</span> </div>
|
||
<div class="line"><a id="l13127" name="l13127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27fd32b963677065b181f32e16e04b7b">13127</a></span><span class="comment">/* Bit definition for Ethernet MAC debug Register */</span></div>
|
||
<div class="line"><a id="l13128" name="l13128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5af5bce543dc0df3a800a2db110bbdc">13128</a></span><span class="preprocessor">#define ETH_MACDBGR_TFF_Pos (25U) </span></div>
|
||
<div class="line"><a id="l13129" name="l13129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94103a8c53ce5eab030b42165dd6916b">13129</a></span><span class="preprocessor">#define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos) </span></div>
|
||
<div class="line"><a id="l13130" name="l13130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67c688152c050956889165352ff65a16">13130</a></span><span class="preprocessor">#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk </span><span class="comment">/* Tx FIFO full */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13131" name="l13131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga176073c87c07e195f0b2ca7868b3cde5">13131</a></span><span class="preprocessor">#define ETH_MACDBGR_TFNE_Pos (24U) </span></div>
|
||
<div class="line"><a id="l13132" name="l13132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9dff0698db41111c7c99cb5973003d4">13132</a></span><span class="preprocessor">#define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos) </span></div>
|
||
<div class="line"><a id="l13133" name="l13133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b16b33e92d14f1a2b12b8a86700fcf6">13133</a></span><span class="preprocessor">#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk </span><span class="comment">/* Tx FIFO not empty */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13134" name="l13134"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b4ce9eaa80ad0cf60a5921737520507">13134</a></span><span class="preprocessor">#define ETH_MACDBGR_TFWA_Pos (22U) </span></div>
|
||
<div class="line"><a id="l13135" name="l13135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae53b57022944c49021787f52ed30117">13135</a></span><span class="preprocessor">#define ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos) </span></div>
|
||
<div class="line"><a id="l13136" name="l13136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7473c49e7a89cbb1b0e3c9cf67980284">13136</a></span><span class="preprocessor">#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk </span><span class="comment">/* Tx FIFO write active */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13137" name="l13137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97cc364a7442339bcbed0ffde5486ef0">13137</a></span><span class="preprocessor">#define ETH_MACDBGR_TFRS_Pos (20U) </span></div>
|
||
<div class="line"><a id="l13138" name="l13138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga112165ea108b32a86b135583c29a2386">13138</a></span><span class="preprocessor">#define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos) </span></div>
|
||
<div class="line"><a id="l13139" name="l13139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa14782f524bd2b25ed567532e80f4fcf">13139</a></span><span class="preprocessor">#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk </span><span class="comment">/* Tx FIFO read status mask */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13140" name="l13140"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fd97c33d20badcf4ec3cbafda38ddb3">13140</a></span><span class="preprocessor">#define ETH_MACDBGR_TFRS_WRITING_Pos (20U) </span></div>
|
||
<div class="line"><a id="l13141" name="l13141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4902aaee652f847dd0494a87189fb275">13141</a></span><span class="preprocessor">#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) </span></div>
|
||
<div class="line"><a id="l13142" name="l13142"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b3f3b4224569efda1658e0d8f0468bd">13142</a></span><span class="preprocessor">#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk </span><span class="comment">/* Writing the received TxStatus or flushing the TxFIFO */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13143" name="l13143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga745c2d38c8863ffb583471feb51c5a91">13143</a></span><span class="preprocessor">#define ETH_MACDBGR_TFRS_WAITING_Pos (21U) </span></div>
|
||
<div class="line"><a id="l13144" name="l13144"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b223d1c05a8e1503daa10e0f27f514d">13144</a></span><span class="preprocessor">#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) </span></div>
|
||
<div class="line"><a id="l13145" name="l13145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9d9294176f211cb62aef1e622cf8052">13145</a></span><span class="preprocessor">#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk </span><span class="comment">/* Waiting for TxStatus from MAC transmitter */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13146" name="l13146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21675a956d16a5aeac36b390b2bceb72">13146</a></span><span class="preprocessor">#define ETH_MACDBGR_TFRS_READ_Pos (20U) </span></div>
|
||
<div class="line"><a id="l13147" name="l13147"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga520c63ccb534f4fd8740e7ceb254373d">13147</a></span><span class="preprocessor">#define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) </span></div>
|
||
<div class="line"><a id="l13148" name="l13148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48bc21a580c771ed4ac9b797c0b41d25">13148</a></span><span class="preprocessor">#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk </span><span class="comment">/* Read state (transferring data to the MAC transmitter) */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13149" name="l13149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0e5a13ab003041865e72fe3b22a018c">13149</a></span><span class="preprocessor">#define ETH_MACDBGR_TFRS_IDLE 0x00000000U </span><span class="comment">/* Idle state */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13150" name="l13150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga680e2f1a81947b367c26cc628bc10259">13150</a></span><span class="preprocessor">#define ETH_MACDBGR_MTP_Pos (19U) </span></div>
|
||
<div class="line"><a id="l13151" name="l13151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03abbf9c3ee0c6531fd85e0e83596ca8">13151</a></span><span class="preprocessor">#define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos) </span></div>
|
||
<div class="line"><a id="l13152" name="l13152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae311faf908813d5e2431be06b785778a">13152</a></span><span class="preprocessor">#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk </span><span class="comment">/* MAC transmitter in pause */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13153" name="l13153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba7a88ee0e14eac0b53172fb50eb25d5">13153</a></span><span class="preprocessor">#define ETH_MACDBGR_MTFCS_Pos (17U) </span></div>
|
||
<div class="line"><a id="l13154" name="l13154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaede9295547f715df2272833f1245482a">13154</a></span><span class="preprocessor">#define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos) </span></div>
|
||
<div class="line"><a id="l13155" name="l13155"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacab9c8c877f4eb62417bc729bf9a06f">13155</a></span><span class="preprocessor">#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk </span><span class="comment">/* MAC transmit frame controller status mask */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13156" name="l13156"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga256a9d6a729fb24273de7934fda3382a">13156</a></span><span class="preprocessor">#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U) </span></div>
|
||
<div class="line"><a id="l13157" name="l13157"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga864ba1fd49a4814383f949cafe684e03">13157</a></span><span class="preprocessor">#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) </span></div>
|
||
<div class="line"><a id="l13158" name="l13158"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2557c4eac2221f1faab94f9b8cfe00e8">13158</a></span><span class="preprocessor">#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk </span><span class="comment">/* Transferring input frame for transmission */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13159" name="l13159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad83c11088ad9488ad95df4164d87a6aa">13159</a></span><span class="preprocessor">#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U) </span></div>
|
||
<div class="line"><a id="l13160" name="l13160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6e711aa626786701cf5a7be94022d51">13160</a></span><span class="preprocessor">#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) </span></div>
|
||
<div class="line"><a id="l13161" name="l13161"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga924c2a45180a5d6a97c57af4472bc6da">13161</a></span><span class="preprocessor">#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk </span><span class="comment">/* Generating and transmitting a Pause control frame (in full duplex mode) */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13162" name="l13162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c76dec4e7bed65b011abe14d172b63b">13162</a></span><span class="preprocessor">#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U) </span></div>
|
||
<div class="line"><a id="l13163" name="l13163"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b7c3b89c04bd5e78f21fbc80531d93d">13163</a></span><span class="preprocessor">#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) </span></div>
|
||
<div class="line"><a id="l13164" name="l13164"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac046bac41daecef700eab3b0b56cffc8">13164</a></span><span class="preprocessor">#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk </span><span class="comment">/* Waiting for Status of previous frame or IFG/backoff period to be over */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13165" name="l13165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga255b74ece40f98dd5d09daadbaaf35a5">13165</a></span><span class="preprocessor">#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U </span><span class="comment">/* Idle */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13166" name="l13166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaacb0318306838dab51594d9c70f1317">13166</a></span><span class="preprocessor">#define ETH_MACDBGR_MMTEA_Pos (16U) </span></div>
|
||
<div class="line"><a id="l13167" name="l13167"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga351f61d0b865bf9eef1c322a63470b9b">13167</a></span><span class="preprocessor">#define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos) </span></div>
|
||
<div class="line"><a id="l13168" name="l13168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga662cdc10d98ff6adaf37c06708632e18">13168</a></span><span class="preprocessor">#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk </span><span class="comment">/* MAC MII transmit engine active */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13169" name="l13169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga677c8cbf5dde19bafe80d61eeec6acdf">13169</a></span><span class="preprocessor">#define ETH_MACDBGR_RFFL_Pos (8U) </span></div>
|
||
<div class="line"><a id="l13170" name="l13170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeaada3f1e16d6196492ee883729b1bc5">13170</a></span><span class="preprocessor">#define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos) </span></div>
|
||
<div class="line"><a id="l13171" name="l13171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf89706d23f364ef3b84d865245142e81">13171</a></span><span class="preprocessor">#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk </span><span class="comment">/* Rx FIFO fill level mask */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13172" name="l13172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf21ee74d35ebd3ab19866e990b939cf7">13172</a></span><span class="preprocessor">#define ETH_MACDBGR_RFFL_FULL_Pos (8U) </span></div>
|
||
<div class="line"><a id="l13173" name="l13173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe77114eff677d5aa1a9e9fdff1dd012">13173</a></span><span class="preprocessor">#define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) </span></div>
|
||
<div class="line"><a id="l13174" name="l13174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd0c643a902e127cc756b7fd2f1addc7">13174</a></span><span class="preprocessor">#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk </span><span class="comment">/* RxFIFO full */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13175" name="l13175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10c2064f3b400195c7af25036b061a7a">13175</a></span><span class="preprocessor">#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U) </span></div>
|
||
<div class="line"><a id="l13176" name="l13176"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6641e0e8ac06b83bae463bc922f21d11">13176</a></span><span class="preprocessor">#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) </span></div>
|
||
<div class="line"><a id="l13177" name="l13177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga248a8dded9a74fcbffc47420902925cf">13177</a></span><span class="preprocessor">#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk </span><span class="comment">/* RxFIFO fill-level above flow-control activate threshold */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13178" name="l13178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19cdea0cde9945c403c6c06813c9bf62">13178</a></span><span class="preprocessor">#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U) </span></div>
|
||
<div class="line"><a id="l13179" name="l13179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ddf7ce69f167379613a4c7cdcc1e793">13179</a></span><span class="preprocessor">#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) </span></div>
|
||
<div class="line"><a id="l13180" name="l13180"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab858b8daec5ad2e262c045e2c356c8da">13180</a></span><span class="preprocessor">#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk </span><span class="comment">/* RxFIFO fill-level below flow-control de-activate threshold */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13181" name="l13181"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae559873efaadb3aeee1a88c9d57532f2">13181</a></span><span class="preprocessor">#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U </span><span class="comment">/* RxFIFO empty */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13182" name="l13182"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5bb3df9b84ce49d0cd478ad7c3c7853">13182</a></span><span class="preprocessor">#define ETH_MACDBGR_RFRCS_Pos (5U) </span></div>
|
||
<div class="line"><a id="l13183" name="l13183"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71dcc3ae1256f5d497268d17da32365f">13183</a></span><span class="preprocessor">#define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos) </span></div>
|
||
<div class="line"><a id="l13184" name="l13184"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ad0c45c41812a126604ca20edd26ea1">13184</a></span><span class="preprocessor">#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk </span><span class="comment">/* Rx FIFO read controller status mask */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13185" name="l13185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0dabbd91b31f2da515b27e58d3e4b382">13185</a></span><span class="preprocessor">#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U) </span></div>
|
||
<div class="line"><a id="l13186" name="l13186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c6dcca9f806cc4c605e87ff6688002f">13186</a></span><span class="preprocessor">#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) </span></div>
|
||
<div class="line"><a id="l13187" name="l13187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a03f0782ae649ffa10bf09cf6544c21">13187</a></span><span class="preprocessor">#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk </span><span class="comment">/* Flushing the frame data and status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13188" name="l13188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2441dce4a78077110e952be1e34afef">13188</a></span><span class="preprocessor">#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U) </span></div>
|
||
<div class="line"><a id="l13189" name="l13189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae60cfc823422bbec5008b06da236861e">13189</a></span><span class="preprocessor">#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) </span></div>
|
||
<div class="line"><a id="l13190" name="l13190"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0cf3fc9bd396cc8f571f20d977c36bd">13190</a></span><span class="preprocessor">#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk </span><span class="comment">/* Reading frame status (or time-stamp) */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13191" name="l13191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b84a8a7e5d71118ae3cec94160a1e95">13191</a></span><span class="preprocessor">#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U) </span></div>
|
||
<div class="line"><a id="l13192" name="l13192"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa876e6249677eb886802d0de921586a9">13192</a></span><span class="preprocessor">#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) </span></div>
|
||
<div class="line"><a id="l13193" name="l13193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02670bb4130b5700cd7c8a1b83fc5ea7">13193</a></span><span class="preprocessor">#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk </span><span class="comment">/* Reading frame data */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13194" name="l13194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8dd87eed0c5d5ae993d654abb251b63c">13194</a></span><span class="preprocessor">#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U </span><span class="comment">/* IDLE state */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13195" name="l13195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65529949f0603e73f75fa2a35890b5a3">13195</a></span><span class="preprocessor">#define ETH_MACDBGR_RFWRA_Pos (4U) </span></div>
|
||
<div class="line"><a id="l13196" name="l13196"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80fdd819a347bb13cbd5575fc15d914a">13196</a></span><span class="preprocessor">#define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos) </span></div>
|
||
<div class="line"><a id="l13197" name="l13197"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga667ffe9105a73ce0bde2927cf8f3d460">13197</a></span><span class="preprocessor">#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk </span><span class="comment">/* Rx FIFO write controller active */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13198" name="l13198"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52fd76b8f90767f087ec1c667025c8c3">13198</a></span><span class="preprocessor">#define ETH_MACDBGR_MSFRWCS_Pos (1U) </span></div>
|
||
<div class="line"><a id="l13199" name="l13199"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf075cce7b6d8d49b2371c84b978d68c0">13199</a></span><span class="preprocessor">#define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) </span></div>
|
||
<div class="line"><a id="l13200" name="l13200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c641484d2e209feeb8767877a275ded">13200</a></span><span class="preprocessor">#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk </span><span class="comment">/* MAC small FIFO read / write controllers status mask */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13201" name="l13201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fb3798487f2a257d688ac435a608341">13201</a></span><span class="preprocessor">#define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) </span></div>
|
||
<div class="line"><a id="l13202" name="l13202"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30e18ad6efe686ce4182e2f381b136d9">13202</a></span><span class="preprocessor">#define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) </span></div>
|
||
<div class="line"><a id="l13203" name="l13203"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e61368122a669649e18e073d92b9523">13203</a></span><span class="preprocessor">#define ETH_MACDBGR_MMRPEA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13204" name="l13204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ea39162c87ae99fc775d7c685f4cad9">13204</a></span><span class="preprocessor">#define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos) </span></div>
|
||
<div class="line"><a id="l13205" name="l13205"></a><span class="lineno">13205</span><span class="preprocessor">#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk </span><span class="comment">/* MAC MII receive protocol engine active */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13206" name="l13206"></a><span class="lineno">13206</span> </div>
|
||
<div class="line"><a id="l13207" name="l13207"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga812de501f25e360962652a2a17b65e52">13207</a></span><span class="comment">/* Bit definition for Ethernet MAC Status Register */</span></div>
|
||
<div class="line"><a id="l13208" name="l13208"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7a53b96de3d0f7dc394e745bafcc899">13208</a></span><span class="preprocessor">#define ETH_MACSR_TSTS_Pos (9U) </span></div>
|
||
<div class="line"><a id="l13209" name="l13209"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5e4af1a52a19f5b2d8f3ce74dd5c85e">13209</a></span><span class="preprocessor">#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos) </span></div>
|
||
<div class="line"><a id="l13210" name="l13210"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8b2cfde92f9bb04b084ea2af687689d">13210</a></span><span class="preprocessor">#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk </span><span class="comment">/* Time stamp trigger status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13211" name="l13211"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabce1cd290247069cb65dd4d96d0fb638">13211</a></span><span class="preprocessor">#define ETH_MACSR_MMCTS_Pos (6U) </span></div>
|
||
<div class="line"><a id="l13212" name="l13212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f628abfb1f1076cd89ac76a373d48d6">13212</a></span><span class="preprocessor">#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos) </span></div>
|
||
<div class="line"><a id="l13213" name="l13213"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e33ef451e773236892e9635f0aa7498">13213</a></span><span class="preprocessor">#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk </span><span class="comment">/* MMC transmit status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13214" name="l13214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06bed909940fa2ea61c81f38c0209262">13214</a></span><span class="preprocessor">#define ETH_MACSR_MMMCRS_Pos (5U) </span></div>
|
||
<div class="line"><a id="l13215" name="l13215"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9faeaa8069b56260ffc8ed2daa06fcd">13215</a></span><span class="preprocessor">#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos) </span></div>
|
||
<div class="line"><a id="l13216" name="l13216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6836cf875c27333b0358be060c931c9e">13216</a></span><span class="preprocessor">#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk </span><span class="comment">/* MMC receive status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13217" name="l13217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e9a4734bc3540aa6d658c928a15634c">13217</a></span><span class="preprocessor">#define ETH_MACSR_MMCS_Pos (4U) </span></div>
|
||
<div class="line"><a id="l13218" name="l13218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga764dd9b736867f6c5b590c7ca49017c2">13218</a></span><span class="preprocessor">#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos) </span></div>
|
||
<div class="line"><a id="l13219" name="l13219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c4e8dc8e8dad60de5b659a72ca7fe74">13219</a></span><span class="preprocessor">#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk </span><span class="comment">/* MMC status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13220" name="l13220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga279ac5f84e4f33e20f11d5bdbcf21cc2">13220</a></span><span class="preprocessor">#define ETH_MACSR_PMTS_Pos (3U) </span></div>
|
||
<div class="line"><a id="l13221" name="l13221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee99dd08ad3581436f53b7f22452dcb9">13221</a></span><span class="preprocessor">#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos) </span></div>
|
||
<div class="line"><a id="l13222" name="l13222"></a><span class="lineno">13222</span><span class="preprocessor">#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk </span><span class="comment">/* PMT status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13223" name="l13223"></a><span class="lineno">13223</span> </div>
|
||
<div class="line"><a id="l13224" name="l13224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaff7e97a761e2557458f09c24e91d507">13224</a></span><span class="comment">/* Bit definition for Ethernet MAC Interrupt Mask Register */</span></div>
|
||
<div class="line"><a id="l13225" name="l13225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2092019773b2c66261249da4c9eced6b">13225</a></span><span class="preprocessor">#define ETH_MACIMR_TSTIM_Pos (9U) </span></div>
|
||
<div class="line"><a id="l13226" name="l13226"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f17c13903c30bc301c7897b93a16a24">13226</a></span><span class="preprocessor">#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos) </span></div>
|
||
<div class="line"><a id="l13227" name="l13227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd408f2d5725c50c92eeedadc12b5b0e">13227</a></span><span class="preprocessor">#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk </span><span class="comment">/* Time stamp trigger interrupt mask */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13228" name="l13228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5de068ed7fd3905c55b6e2cca8324e25">13228</a></span><span class="preprocessor">#define ETH_MACIMR_PMTIM_Pos (3U) </span></div>
|
||
<div class="line"><a id="l13229" name="l13229"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2cdb4ba6c97aba3e82e8192ebddcb5f">13229</a></span><span class="preprocessor">#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos) </span></div>
|
||
<div class="line"><a id="l13230" name="l13230"></a><span class="lineno">13230</span><span class="preprocessor">#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk </span><span class="comment">/* PMT interrupt mask */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13231" name="l13231"></a><span class="lineno">13231</span> </div>
|
||
<div class="line"><a id="l13232" name="l13232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21bb827892ec43224afef17af302e1a3">13232</a></span><span class="comment">/* Bit definition for Ethernet MAC Address0 High Register */</span></div>
|
||
<div class="line"><a id="l13233" name="l13233"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga867c6c9c8a1a2c5559f99673debe33a3">13233</a></span><span class="preprocessor">#define ETH_MACA0HR_MACA0H_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13234" name="l13234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga142dbcbb7da81e8549dde3c239ed8251">13234</a></span><span class="preprocessor">#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) </span></div>
|
||
<div class="line"><a id="l13235" name="l13235"></a><span class="lineno">13235</span><span class="preprocessor">#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk </span><span class="comment">/* MAC address0 high */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13236" name="l13236"></a><span class="lineno">13236</span> </div>
|
||
<div class="line"><a id="l13237" name="l13237"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72f33ca841069471da9ca73b46d40ac5">13237</a></span><span class="comment">/* Bit definition for Ethernet MAC Address0 Low Register */</span></div>
|
||
<div class="line"><a id="l13238" name="l13238"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga994262dc8bd5b38a213503e3d2e6c398">13238</a></span><span class="preprocessor">#define ETH_MACA0LR_MACA0L_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13239" name="l13239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3ed9dbd9711ee9c19f40c73d8f33be3">13239</a></span><span class="preprocessor">#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) </span></div>
|
||
<div class="line"><a id="l13240" name="l13240"></a><span class="lineno">13240</span><span class="preprocessor">#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk </span><span class="comment">/* MAC address0 low */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13241" name="l13241"></a><span class="lineno">13241</span> </div>
|
||
<div class="line"><a id="l13242" name="l13242"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f3217cb3886e3c977a676a06b912eb2">13242</a></span><span class="comment">/* Bit definition for Ethernet MAC Address1 High Register */</span></div>
|
||
<div class="line"><a id="l13243" name="l13243"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ab67262fcf71a730f150aed61e3e173">13243</a></span><span class="preprocessor">#define ETH_MACA1HR_AE_Pos (31U) </span></div>
|
||
<div class="line"><a id="l13244" name="l13244"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f88c5ead1109f1e0abac07bcb2e44ea">13244</a></span><span class="preprocessor">#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) </span></div>
|
||
<div class="line"><a id="l13245" name="l13245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecdc77542da8b8c62da99702324479e1">13245</a></span><span class="preprocessor">#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk </span><span class="comment">/* Address enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13246" name="l13246"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac076f91767de8a428972303da56427d5">13246</a></span><span class="preprocessor">#define ETH_MACA1HR_SA_Pos (30U) </span></div>
|
||
<div class="line"><a id="l13247" name="l13247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3840a96465b73115d34360abf3704c5">13247</a></span><span class="preprocessor">#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) </span></div>
|
||
<div class="line"><a id="l13248" name="l13248"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c4a2a38360a644181c889a97a058791">13248</a></span><span class="preprocessor">#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk </span><span class="comment">/* Source address */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13249" name="l13249"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf98e44dbd971404c80536dab4459e295">13249</a></span><span class="preprocessor">#define ETH_MACA1HR_MBC_Pos (24U) </span></div>
|
||
<div class="line"><a id="l13250" name="l13250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7bf2fe1242cce62c3fe1cc49ce513b6a">13250</a></span><span class="preprocessor">#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) </span></div>
|
||
<div class="line"><a id="l13251" name="l13251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3e731440906539ecb1c52a84df889c5">13251</a></span><span class="preprocessor">#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk </span><span class="comment">/* Mask byte control: bits to mask for comparison of the MAC Address bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13252" name="l13252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8ebf87cc6584613fea5a49a382b2d67">13252</a></span><span class="preprocessor">#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U </span><span class="comment">/* Mask MAC Address high reg bits [15:8] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13253" name="l13253"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fa211fa742d34dd8e8d2ca2ea5e865a">13253</a></span><span class="preprocessor">#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U </span><span class="comment">/* Mask MAC Address high reg bits [7:0] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13254" name="l13254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d3767ea17fd333409e63262ab5f6878">13254</a></span><span class="preprocessor">#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U </span><span class="comment">/* Mask MAC Address low reg bits [31:24] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13255" name="l13255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3520a54e7e68617539b51885b7bb918">13255</a></span><span class="preprocessor">#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U </span><span class="comment">/* Mask MAC Address low reg bits [23:16] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13256" name="l13256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3894de2dc133fd5e03e4d4817852adfd">13256</a></span><span class="preprocessor">#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U </span><span class="comment">/* Mask MAC Address low reg bits [15:8] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13257" name="l13257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf00494291a47151e9c4ea357746f757d">13257</a></span><span class="preprocessor">#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U </span><span class="comment">/* Mask MAC Address low reg bits [7:0] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13258" name="l13258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga859884136a9b5a2924fa61ecb29d28d7">13258</a></span><span class="preprocessor">#define ETH_MACA1HR_MACA1H_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13259" name="l13259"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddd4d059d3d4734c2528ef12cadbd769">13259</a></span><span class="preprocessor">#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) </span></div>
|
||
<div class="line"><a id="l13260" name="l13260"></a><span class="lineno">13260</span><span class="preprocessor">#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk </span><span class="comment">/* MAC address1 high */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13261" name="l13261"></a><span class="lineno">13261</span> </div>
|
||
<div class="line"><a id="l13262" name="l13262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa29c12e370323d466187775345ab9d1e">13262</a></span><span class="comment">/* Bit definition for Ethernet MAC Address1 Low Register */</span></div>
|
||
<div class="line"><a id="l13263" name="l13263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93090bfada32ec17c3385ab72ec89ebb">13263</a></span><span class="preprocessor">#define ETH_MACA1LR_MACA1L_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13264" name="l13264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacce742aa0eabc2a8b23ba4f79f18409a">13264</a></span><span class="preprocessor">#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) </span></div>
|
||
<div class="line"><a id="l13265" name="l13265"></a><span class="lineno">13265</span><span class="preprocessor">#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk </span><span class="comment">/* MAC address1 low */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13266" name="l13266"></a><span class="lineno">13266</span> </div>
|
||
<div class="line"><a id="l13267" name="l13267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga153e9d30ef5f5fd7e8107e36e4a15757">13267</a></span><span class="comment">/* Bit definition for Ethernet MAC Address2 High Register */</span></div>
|
||
<div class="line"><a id="l13268" name="l13268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cdb03f087e227851c3ad964da076672">13268</a></span><span class="preprocessor">#define ETH_MACA2HR_AE_Pos (31U) </span></div>
|
||
<div class="line"><a id="l13269" name="l13269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5713abb4f70f5514d2d44c44ea17254e">13269</a></span><span class="preprocessor">#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) </span></div>
|
||
<div class="line"><a id="l13270" name="l13270"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga303b2c351db0593d5283e7f324cb725c">13270</a></span><span class="preprocessor">#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk </span><span class="comment">/* Address enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13271" name="l13271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade8dbf6a5ba0db18a839b799b9ae951a">13271</a></span><span class="preprocessor">#define ETH_MACA2HR_SA_Pos (30U) </span></div>
|
||
<div class="line"><a id="l13272" name="l13272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c3f0a2b08321c5441a87b385bfe0c41">13272</a></span><span class="preprocessor">#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) </span></div>
|
||
<div class="line"><a id="l13273" name="l13273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b46e39d1c8da3b5d032e57f2fe9c395">13273</a></span><span class="preprocessor">#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk </span><span class="comment">/* Source address */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13274" name="l13274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab90f57ac02ce2cf7223f3b0bfd0e7891">13274</a></span><span class="preprocessor">#define ETH_MACA2HR_MBC_Pos (24U) </span></div>
|
||
<div class="line"><a id="l13275" name="l13275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga270c0bb939fd71e02a8d221caada1071">13275</a></span><span class="preprocessor">#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) </span></div>
|
||
<div class="line"><a id="l13276" name="l13276"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga656070d9cc36501e927908e2f3903332">13276</a></span><span class="preprocessor">#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk </span><span class="comment">/* Mask byte control */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13277" name="l13277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga322aa03bccdcb0b2e85119629e95be57">13277</a></span><span class="preprocessor">#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U </span><span class="comment">/* Mask MAC Address high reg bits [15:8] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13278" name="l13278"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9519b002d1e0c04b1d5989bf410d24cb">13278</a></span><span class="preprocessor">#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U </span><span class="comment">/* Mask MAC Address high reg bits [7:0] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13279" name="l13279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cc71bd0499aaa5a76247a6bd6e5e79a">13279</a></span><span class="preprocessor">#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U </span><span class="comment">/* Mask MAC Address low reg bits [31:24] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13280" name="l13280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga394acdc62df68dadb1190d4f83f6dbaa">13280</a></span><span class="preprocessor">#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U </span><span class="comment">/* Mask MAC Address low reg bits [23:16] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13281" name="l13281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa87b47b25381694fdcc397cc63ea8810">13281</a></span><span class="preprocessor">#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U </span><span class="comment">/* Mask MAC Address low reg bits [15:8] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13282" name="l13282"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a9cabfc6b16557ae778be5010419be9">13282</a></span><span class="preprocessor">#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U </span><span class="comment">/* Mask MAC Address low reg bits [70] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13283" name="l13283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a378228b4b6bd086aa8931bb2b81326">13283</a></span><span class="preprocessor">#define ETH_MACA2HR_MACA2H_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13284" name="l13284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c73a460038c40e28b27fe0cfcd17cef">13284</a></span><span class="preprocessor">#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) </span></div>
|
||
<div class="line"><a id="l13285" name="l13285"></a><span class="lineno">13285</span><span class="preprocessor">#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk </span><span class="comment">/* MAC address1 high */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13286" name="l13286"></a><span class="lineno">13286</span> </div>
|
||
<div class="line"><a id="l13287" name="l13287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84d72f061c5bd14552d066fefc0bf13c">13287</a></span><span class="comment">/* Bit definition for Ethernet MAC Address2 Low Register */</span></div>
|
||
<div class="line"><a id="l13288" name="l13288"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41296fc9e2a6a59d5f7c16e94bc17736">13288</a></span><span class="preprocessor">#define ETH_MACA2LR_MACA2L_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13289" name="l13289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga757e0ceef1c6d529f28c7875ff3e88e7">13289</a></span><span class="preprocessor">#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) </span></div>
|
||
<div class="line"><a id="l13290" name="l13290"></a><span class="lineno">13290</span><span class="preprocessor">#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk </span><span class="comment">/* MAC address2 low */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13291" name="l13291"></a><span class="lineno">13291</span> </div>
|
||
<div class="line"><a id="l13292" name="l13292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19974f597cc028a35be1daec4a1ba531">13292</a></span><span class="comment">/* Bit definition for Ethernet MAC Address3 High Register */</span></div>
|
||
<div class="line"><a id="l13293" name="l13293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c36200e79d56aba3c56dc24c475406a">13293</a></span><span class="preprocessor">#define ETH_MACA3HR_AE_Pos (31U) </span></div>
|
||
<div class="line"><a id="l13294" name="l13294"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3bb6d5c1237b2c573f22876a62dcaa9">13294</a></span><span class="preprocessor">#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) </span></div>
|
||
<div class="line"><a id="l13295" name="l13295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga988fe5da295995ba022cb1a379673ad7">13295</a></span><span class="preprocessor">#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk </span><span class="comment">/* Address enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13296" name="l13296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b3ed7c73e177513e879d96e42f8fd5b">13296</a></span><span class="preprocessor">#define ETH_MACA3HR_SA_Pos (30U) </span></div>
|
||
<div class="line"><a id="l13297" name="l13297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54c41346fd61170b413812a19fcac8db">13297</a></span><span class="preprocessor">#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) </span></div>
|
||
<div class="line"><a id="l13298" name="l13298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadedd5cb92d6134fd4110664083f943f9">13298</a></span><span class="preprocessor">#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk </span><span class="comment">/* Source address */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13299" name="l13299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c9fa25a21daaf9673e50a75db9f4193">13299</a></span><span class="preprocessor">#define ETH_MACA3HR_MBC_Pos (24U) </span></div>
|
||
<div class="line"><a id="l13300" name="l13300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64ec855ed04aea21b400ae947b54a353">13300</a></span><span class="preprocessor">#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) </span></div>
|
||
<div class="line"><a id="l13301" name="l13301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga019fe5bc7d94ee1ee4a605e06e777bb5">13301</a></span><span class="preprocessor">#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk </span><span class="comment">/* Mask byte control */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13302" name="l13302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33587cdbe844563e853e3815b63c7c47">13302</a></span><span class="preprocessor">#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U </span><span class="comment">/* Mask MAC Address high reg bits [15:8] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13303" name="l13303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae147613a45eb3d13b84b66158217bb89">13303</a></span><span class="preprocessor">#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U </span><span class="comment">/* Mask MAC Address high reg bits [7:0] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13304" name="l13304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b47f3fddf3dcd39b3af7785c1e5cced">13304</a></span><span class="preprocessor">#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U </span><span class="comment">/* Mask MAC Address low reg bits [31:24] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13305" name="l13305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4744ba01934291f07b1b132b82cb1bd4">13305</a></span><span class="preprocessor">#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U </span><span class="comment">/* Mask MAC Address low reg bits [23:16] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13306" name="l13306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60f2f1ab81a02837ed96e5f92fe96181">13306</a></span><span class="preprocessor">#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U </span><span class="comment">/* Mask MAC Address low reg bits [15:8] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13307" name="l13307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c868df20fcf4144cff7cdaecec1c892">13307</a></span><span class="preprocessor">#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U </span><span class="comment">/* Mask MAC Address low reg bits [70] */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13308" name="l13308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a4c3dd7eb1ea655eb87161f5268de85">13308</a></span><span class="preprocessor">#define ETH_MACA3HR_MACA3H_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13309" name="l13309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b5d9faa67c4cc6d1c42ec26ad99d57b">13309</a></span><span class="preprocessor">#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) </span></div>
|
||
<div class="line"><a id="l13310" name="l13310"></a><span class="lineno">13310</span><span class="preprocessor">#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk </span><span class="comment">/* MAC address3 high */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13311" name="l13311"></a><span class="lineno">13311</span> </div>
|
||
<div class="line"><a id="l13312" name="l13312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec6beeb51e6198352c03b91615109947">13312</a></span><span class="comment">/* Bit definition for Ethernet MAC Address3 Low Register */</span></div>
|
||
<div class="line"><a id="l13313" name="l13313"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada2b7497b892a22692e464256513c9e4">13313</a></span><span class="preprocessor">#define ETH_MACA3LR_MACA3L_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13314" name="l13314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa08b4ccde1b7251ba6317e744b09a95f">13314</a></span><span class="preprocessor">#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) </span></div>
|
||
<div class="line"><a id="l13315" name="l13315"></a><span class="lineno">13315</span><span class="preprocessor">#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk </span><span class="comment">/* MAC address3 low */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13316" name="l13316"></a><span class="lineno">13316</span> </div>
|
||
<div class="line"><a id="l13317" name="l13317"></a><span class="lineno">13317</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l13318" name="l13318"></a><span class="lineno">13318</span><span class="comment">/* Ethernet MMC Registers bits definition */</span></div>
|
||
<div class="line"><a id="l13319" name="l13319"></a><span class="lineno">13319</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l13320" name="l13320"></a><span class="lineno">13320</span> </div>
|
||
<div class="line"><a id="l13321" name="l13321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54d376c32875a39afa0492c2506b4e45">13321</a></span><span class="comment">/* Bit definition for Ethernet MMC Control Register */</span></div>
|
||
<div class="line"><a id="l13322" name="l13322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ed0579e3320b27f2fbc0c55159d7552">13322</a></span><span class="preprocessor">#define ETH_MMCCR_MCFHP_Pos (5U) </span></div>
|
||
<div class="line"><a id="l13323" name="l13323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0eb309947d400951235c17953254fbf8">13323</a></span><span class="preprocessor">#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) </span></div>
|
||
<div class="line"><a id="l13324" name="l13324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17d60ddf79fe7ab501bcf68012f7b7ec">13324</a></span><span class="preprocessor">#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk </span><span class="comment">/* MMC counter Full-Half preset */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13325" name="l13325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf04f6b5deb3a53b8b506162772765171">13325</a></span><span class="preprocessor">#define ETH_MMCCR_MCP_Pos (4U) </span></div>
|
||
<div class="line"><a id="l13326" name="l13326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a6eeda6ffcafe7d8ba531ccaa3abf90">13326</a></span><span class="preprocessor">#define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos) </span></div>
|
||
<div class="line"><a id="l13327" name="l13327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e66af70554c0813685e282d1bb9c4d5">13327</a></span><span class="preprocessor">#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk </span><span class="comment">/* MMC counter preset */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13328" name="l13328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e4246e3804f51c0f04a91e42ee6f6b1">13328</a></span><span class="preprocessor">#define ETH_MMCCR_MCF_Pos (3U) </span></div>
|
||
<div class="line"><a id="l13329" name="l13329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17ab5fbe6c5189b3f98095f9adb1eeeb">13329</a></span><span class="preprocessor">#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos) </span></div>
|
||
<div class="line"><a id="l13330" name="l13330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ba16f3d8066423ef675d53633c3bf7f">13330</a></span><span class="preprocessor">#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk </span><span class="comment">/* MMC Counter Freeze */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13331" name="l13331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb19c7101d5986ae5582acf37c2fa730">13331</a></span><span class="preprocessor">#define ETH_MMCCR_ROR_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13332" name="l13332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga243ae6b3acbbd295be6f76a84657a48d">13332</a></span><span class="preprocessor">#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos) </span></div>
|
||
<div class="line"><a id="l13333" name="l13333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5f177ef83413fc7f8b139d2e61a195b">13333</a></span><span class="preprocessor">#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk </span><span class="comment">/* Reset on Read */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13334" name="l13334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f27d8db71e31940104b534eb8e10ca5">13334</a></span><span class="preprocessor">#define ETH_MMCCR_CSR_Pos (1U) </span></div>
|
||
<div class="line"><a id="l13335" name="l13335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga948b685211ced94ef5d4b8d2c94df78a">13335</a></span><span class="preprocessor">#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos) </span></div>
|
||
<div class="line"><a id="l13336" name="l13336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43cace7bf67560967d43822c7f2fa730">13336</a></span><span class="preprocessor">#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk </span><span class="comment">/* Counter Stop Rollover */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13337" name="l13337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36dc300b94cd6c761f4fb2105c306203">13337</a></span><span class="preprocessor">#define ETH_MMCCR_CR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13338" name="l13338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cb520c80fc0b2f00304bb7f8f7c5d4e">13338</a></span><span class="preprocessor">#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos) </span></div>
|
||
<div class="line"><a id="l13339" name="l13339"></a><span class="lineno">13339</span><span class="preprocessor">#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk </span><span class="comment">/* Counters Reset */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13340" name="l13340"></a><span class="lineno">13340</span> </div>
|
||
<div class="line"><a id="l13341" name="l13341"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa86865c319fd4a4bdc7f612169251a25">13341</a></span><span class="comment">/* Bit definition for Ethernet MMC Receive Interrupt Register */</span></div>
|
||
<div class="line"><a id="l13342" name="l13342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9dc1a19f41c18602c71bd10a99d70b8">13342</a></span><span class="preprocessor">#define ETH_MMCRIR_RGUFS_Pos (17U) </span></div>
|
||
<div class="line"><a id="l13343" name="l13343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4b78bde6602ca062513389b8bf43e17">13343</a></span><span class="preprocessor">#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos) </span></div>
|
||
<div class="line"><a id="l13344" name="l13344"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabea46fc5d1c9b634047e5b6a56171d58">13344</a></span><span class="preprocessor">#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk </span><span class="comment">/* Set when Rx good unicast frames counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13345" name="l13345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9456fe951f40d50ade33d8a0221d1a6c">13345</a></span><span class="preprocessor">#define ETH_MMCRIR_RFAES_Pos (6U) </span></div>
|
||
<div class="line"><a id="l13346" name="l13346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d3859ff0eb6fff48fb98919fe72da15">13346</a></span><span class="preprocessor">#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos) </span></div>
|
||
<div class="line"><a id="l13347" name="l13347"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d23ef057bd9e8cdb9ed25bffca057b6">13347</a></span><span class="preprocessor">#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk </span><span class="comment">/* Set when Rx alignment error counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13348" name="l13348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga707393c1886b72fdfed379967212a36c">13348</a></span><span class="preprocessor">#define ETH_MMCRIR_RFCES_Pos (5U) </span></div>
|
||
<div class="line"><a id="l13349" name="l13349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac74e35d76820f3c2b0eb743f26023792">13349</a></span><span class="preprocessor">#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos) </span></div>
|
||
<div class="line"><a id="l13350" name="l13350"></a><span class="lineno">13350</span><span class="preprocessor">#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk </span><span class="comment">/* Set when Rx crc error counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13351" name="l13351"></a><span class="lineno">13351</span> </div>
|
||
<div class="line"><a id="l13352" name="l13352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04a0d740674b1ef700a33c222fcedef6">13352</a></span><span class="comment">/* Bit definition for Ethernet MMC Transmit Interrupt Register */</span></div>
|
||
<div class="line"><a id="l13353" name="l13353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5361ed811dd1673f55cc0ca20096022a">13353</a></span><span class="preprocessor">#define ETH_MMCTIR_TGFS_Pos (21U) </span></div>
|
||
<div class="line"><a id="l13354" name="l13354"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5d5dcc69902946befc317ea5719a34c">13354</a></span><span class="preprocessor">#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos) </span></div>
|
||
<div class="line"><a id="l13355" name="l13355"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4524f1174601c98399967db0321779f">13355</a></span><span class="preprocessor">#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk </span><span class="comment">/* Set when Tx good frame count counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13356" name="l13356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd5834302f75346a6ce686d331b66cf2">13356</a></span><span class="preprocessor">#define ETH_MMCTIR_TGFMSCS_Pos (15U) </span></div>
|
||
<div class="line"><a id="l13357" name="l13357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga796d834a29d0fc6fdc1908ba6db487c3">13357</a></span><span class="preprocessor">#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) </span></div>
|
||
<div class="line"><a id="l13358" name="l13358"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7ac440ef59fd4dae474a77cff93b992">13358</a></span><span class="preprocessor">#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk </span><span class="comment">/* Set when Tx good multi col counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13359" name="l13359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c0fa21e33672cbf0d9e4404aa236663">13359</a></span><span class="preprocessor">#define ETH_MMCTIR_TGFSCS_Pos (14U) </span></div>
|
||
<div class="line"><a id="l13360" name="l13360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe8e920b9e135d3e3ba61e0db758ff19">13360</a></span><span class="preprocessor">#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos) </span></div>
|
||
<div class="line"><a id="l13361" name="l13361"></a><span class="lineno">13361</span><span class="preprocessor">#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk </span><span class="comment">/* Set when Tx good single col counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13362" name="l13362"></a><span class="lineno">13362</span> </div>
|
||
<div class="line"><a id="l13363" name="l13363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga828d9869b1337d57b50a82873a8c8702">13363</a></span><span class="comment">/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */</span></div>
|
||
<div class="line"><a id="l13364" name="l13364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga470c1e9e33a19b7da3110acd5e0d9254">13364</a></span><span class="preprocessor">#define ETH_MMCRIMR_RGUFM_Pos (17U) </span></div>
|
||
<div class="line"><a id="l13365" name="l13365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga873a3b1c0a7756647be8455ea6bea8df">13365</a></span><span class="preprocessor">#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos) </span></div>
|
||
<div class="line"><a id="l13366" name="l13366"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60b9afd54fab9bfc9df42907c63bd685">13366</a></span><span class="preprocessor">#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk </span><span class="comment">/* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13367" name="l13367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5a6a3b036b82adac210651815b69cb0">13367</a></span><span class="preprocessor">#define ETH_MMCRIMR_RFAEM_Pos (6U) </span></div>
|
||
<div class="line"><a id="l13368" name="l13368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c763ea4da19192ab30828971579400c">13368</a></span><span class="preprocessor">#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos) </span></div>
|
||
<div class="line"><a id="l13369" name="l13369"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50fbd3537b29ce431a76f1606791183d">13369</a></span><span class="preprocessor">#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk </span><span class="comment">/* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13370" name="l13370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89a2ad8a6b0429d309799de95538e83f">13370</a></span><span class="preprocessor">#define ETH_MMCRIMR_RFCEM_Pos (5U) </span></div>
|
||
<div class="line"><a id="l13371" name="l13371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3eb72a19c5a4bd34a9ec2c624bd8a8c">13371</a></span><span class="preprocessor">#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos) </span></div>
|
||
<div class="line"><a id="l13372" name="l13372"></a><span class="lineno">13372</span><span class="preprocessor">#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk </span><span class="comment">/* Mask the interrupt when Rx crc error counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13373" name="l13373"></a><span class="lineno">13373</span> </div>
|
||
<div class="line"><a id="l13374" name="l13374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1600c79485a47fa57888479428b8b72">13374</a></span><span class="comment">/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */</span></div>
|
||
<div class="line"><a id="l13375" name="l13375"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65ecd1dd64ba1588e1d83d9896f9e1f0">13375</a></span><span class="preprocessor">#define ETH_MMCTIMR_TGFM_Pos (21U) </span></div>
|
||
<div class="line"><a id="l13376" name="l13376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae67e69315d2e64d3f4c9b7e65aacf8be">13376</a></span><span class="preprocessor">#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos) </span></div>
|
||
<div class="line"><a id="l13377" name="l13377"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga383cc44ef2b8c2cb5cc9a7393a40ea6a">13377</a></span><span class="preprocessor">#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk </span><span class="comment">/* Mask the interrupt when Tx good frame count counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13378" name="l13378"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba449564725083891a9fc504321614cf">13378</a></span><span class="preprocessor">#define ETH_MMCTIMR_TGFMSCM_Pos (15U) </span></div>
|
||
<div class="line"><a id="l13379" name="l13379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20b6f12c07d34bcc014eaa31c6719486">13379</a></span><span class="preprocessor">#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) </span></div>
|
||
<div class="line"><a id="l13380" name="l13380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcd2ae936752f3c3f6e303ecdbd6ce77">13380</a></span><span class="preprocessor">#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk </span><span class="comment">/* Mask the interrupt when Tx good multi col counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13381" name="l13381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec67763632bc2229fca4167c7db268ce">13381</a></span><span class="preprocessor">#define ETH_MMCTIMR_TGFSCM_Pos (14U) </span></div>
|
||
<div class="line"><a id="l13382" name="l13382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f41666a525c61be9c88f3d54632ce34">13382</a></span><span class="preprocessor">#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) </span></div>
|
||
<div class="line"><a id="l13383" name="l13383"></a><span class="lineno">13383</span><span class="preprocessor">#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk </span><span class="comment">/* Mask the interrupt when Tx good single col counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13384" name="l13384"></a><span class="lineno">13384</span> </div>
|
||
<div class="line"><a id="l13385" name="l13385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0a86aabaf7c4a86f0609e67dfc2de72">13385</a></span><span class="comment">/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */</span></div>
|
||
<div class="line"><a id="l13386" name="l13386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac88648ccd808f151b1fc5c72083e4583">13386</a></span><span class="preprocessor">#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13387" name="l13387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga784008b2facbc9cab1982e0382057d1c">13387</a></span><span class="preprocessor">#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) </span></div>
|
||
<div class="line"><a id="l13388" name="l13388"></a><span class="lineno">13388</span><span class="preprocessor">#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk </span><span class="comment">/* Number of successfully transmitted frames after a single collision in Half-duplex mode. */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13389" name="l13389"></a><span class="lineno">13389</span> </div>
|
||
<div class="line"><a id="l13390" name="l13390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3b542ab35eb425c4878c828b365771d">13390</a></span><span class="comment">/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */</span></div>
|
||
<div class="line"><a id="l13391" name="l13391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedefca665609c9e6646ee60e8e91a0f9">13391</a></span><span class="preprocessor">#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13392" name="l13392"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4a8b771ec947fe2b944108f72e64fbf">13392</a></span><span class="preprocessor">#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) </span></div>
|
||
<div class="line"><a id="l13393" name="l13393"></a><span class="lineno">13393</span><span class="preprocessor">#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk </span><span class="comment">/* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13394" name="l13394"></a><span class="lineno">13394</span> </div>
|
||
<div class="line"><a id="l13395" name="l13395"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cd5d71ebd3cafd488e7eba99fcfaa3c">13395</a></span><span class="comment">/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */</span></div>
|
||
<div class="line"><a id="l13396" name="l13396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fdcd7783b8ea9e2c46c8b7d89a39a47">13396</a></span><span class="preprocessor">#define ETH_MMCTGFCR_TGFC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13397" name="l13397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68b659b400b12fd5c539e24bc115dff2">13397</a></span><span class="preprocessor">#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) </span></div>
|
||
<div class="line"><a id="l13398" name="l13398"></a><span class="lineno">13398</span><span class="preprocessor">#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk </span><span class="comment">/* Number of good frames transmitted. */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13399" name="l13399"></a><span class="lineno">13399</span> </div>
|
||
<div class="line"><a id="l13400" name="l13400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1deb0536d536852ede5d1ae0e6710164">13400</a></span><span class="comment">/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */</span></div>
|
||
<div class="line"><a id="l13401" name="l13401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfc0fdeab6719a464423e984ee5d3f96">13401</a></span><span class="preprocessor">#define ETH_MMCRFCECR_RFCEC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13402" name="l13402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ed4e2c7449a522ecbc811252ba1f12b">13402</a></span><span class="preprocessor">#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) </span></div>
|
||
<div class="line"><a id="l13403" name="l13403"></a><span class="lineno">13403</span><span class="preprocessor">#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk </span><span class="comment">/* Number of frames received with CRC error. */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13404" name="l13404"></a><span class="lineno">13404</span> </div>
|
||
<div class="line"><a id="l13405" name="l13405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e4a1a9a81806b92f26c999479b882f7">13405</a></span><span class="comment">/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */</span></div>
|
||
<div class="line"><a id="l13406" name="l13406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88b5da27b7870336e6dc92e75fbaf7bc">13406</a></span><span class="preprocessor">#define ETH_MMCRFAECR_RFAEC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13407" name="l13407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac52a70effea67d543da0842e323d2123">13407</a></span><span class="preprocessor">#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) </span></div>
|
||
<div class="line"><a id="l13408" name="l13408"></a><span class="lineno">13408</span><span class="preprocessor">#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk </span><span class="comment">/* Number of frames received with alignment (dribble) error */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13409" name="l13409"></a><span class="lineno">13409</span> </div>
|
||
<div class="line"><a id="l13410" name="l13410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cc3de8b52de82433d96f3621af5e9d6">13410</a></span><span class="comment">/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */</span></div>
|
||
<div class="line"><a id="l13411" name="l13411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3587339b8bbd30eeff94ee495a7fdbe5">13411</a></span><span class="preprocessor">#define ETH_MMCRGUFCR_RGUFC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13412" name="l13412"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2dd42857738b46f748bc6a9109ab0f9e">13412</a></span><span class="preprocessor">#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) </span></div>
|
||
<div class="line"><a id="l13413" name="l13413"></a><span class="lineno">13413</span><span class="preprocessor">#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk </span><span class="comment">/* Number of good unicast frames received. */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13414" name="l13414"></a><span class="lineno">13414</span> </div>
|
||
<div class="line"><a id="l13415" name="l13415"></a><span class="lineno">13415</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l13416" name="l13416"></a><span class="lineno">13416</span><span class="comment">/* Ethernet PTP Registers bits definition */</span></div>
|
||
<div class="line"><a id="l13417" name="l13417"></a><span class="lineno">13417</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l13418" name="l13418"></a><span class="lineno">13418</span> </div>
|
||
<div class="line"><a id="l13419" name="l13419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8547e484fdbe7554b28c4dbbfda55984">13419</a></span><span class="comment">/* Bit definition for Ethernet PTP Time Stamp Control Register */</span></div>
|
||
<div class="line"><a id="l13420" name="l13420"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07ddca2b8b3a89a0e844b12b45c0a7a1">13420</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)</span></div>
|
||
<div class="line"><a id="l13421" name="l13421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e755bd16b5f77c0e04690acf9f422a2">13421</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) </span></div>
|
||
<div class="line"><a id="l13422" name="l13422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8dee0d9d9d59df164911cfedd38f832e">13422</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk </span><span class="comment">/* Time stamp PTP frame filtering MAC address enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13423" name="l13423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6eb6cba0cbd040d7d39085c0056a7fc">13423</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSCNT_Pos (16U) </span></div>
|
||
<div class="line"><a id="l13424" name="l13424"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9d47a61f30e11b514ef0840f3a0fb91">13424</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) </span></div>
|
||
<div class="line"><a id="l13425" name="l13425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c64bd7449eae554c810dceb920c8f85">13425</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk </span><span class="comment">/* Time stamp clock node type */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13426" name="l13426"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ea5dd63a69ace6876b589be79c520bc">13426</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSMRME_Pos (15U) </span></div>
|
||
<div class="line"><a id="l13427" name="l13427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabfd289fdf804f8ab2240abd611fd36ee">13427</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) </span></div>
|
||
<div class="line"><a id="l13428" name="l13428"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18e9717d99801dd4c06219ef74516ab9">13428</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk </span><span class="comment">/* Time stamp snapshot for message relevant to master enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13429" name="l13429"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad299e7a85e91581bee8f41d8badd1210">13429</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSEME_Pos (14U) </span></div>
|
||
<div class="line"><a id="l13430" name="l13430"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cc8829467d2678bd11d90ec20049cbd">13430</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) </span></div>
|
||
<div class="line"><a id="l13431" name="l13431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52099e8ee00c7b8d08568e768af469d8">13431</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk </span><span class="comment">/* Time stamp snapshot for event message enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13432" name="l13432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7584fce8033ccf0a76c1d0571b1a42f7">13432</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U) </span></div>
|
||
<div class="line"><a id="l13433" name="l13433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e1ed6b41f9d8c686c294846b4a2fde0">13433</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) </span></div>
|
||
<div class="line"><a id="l13434" name="l13434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9861508d171c1c049ef136ab4c90f4ff">13434</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk </span><span class="comment">/* Time stamp snapshot for IPv4 frames enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13435" name="l13435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a1e31f374562426154d02d8e694d0cd">13435</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U) </span></div>
|
||
<div class="line"><a id="l13436" name="l13436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc3f015ae5624edbc57fd6482c9096b6">13436</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) </span></div>
|
||
<div class="line"><a id="l13437" name="l13437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34a9bf48d463d0bd45d5c133654c6319">13437</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk </span><span class="comment">/* Time stamp snapshot for IPv6 frames enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13438" name="l13438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b84221fe479a965fcc665a05e0d2190">13438</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U) </span></div>
|
||
<div class="line"><a id="l13439" name="l13439"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga615bc0bc378392c6a508bb9e28826b72">13439</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) </span></div>
|
||
<div class="line"><a id="l13440" name="l13440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae466858afa76b1a56f3da3221352ae5e">13440</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk </span><span class="comment">/* Time stamp snapshot for PTP over ethernet frames enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13441" name="l13441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbc463e7a55bfd585e2f87095164ed42">13441</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U) </span></div>
|
||
<div class="line"><a id="l13442" name="l13442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf06151b1fa7d4437bb664964de1ee12a">13442</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) </span></div>
|
||
<div class="line"><a id="l13443" name="l13443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7efbf85f1370fa44e7655bd0c4c6f830">13443</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk </span><span class="comment">/* Time stamp PTP packet snooping for version2 format enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13444" name="l13444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0770634e7a6a880384072a2974859d6e">13444</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSSR_Pos (9U) </span></div>
|
||
<div class="line"><a id="l13445" name="l13445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad653b859283fac4ed67f027d8af17dec">13445</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) </span></div>
|
||
<div class="line"><a id="l13446" name="l13446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5eaf028640c2b06b2debb0f1b16124b">13446</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk </span><span class="comment">/* Time stamp Sub-seconds rollover */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13447" name="l13447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6e14c1d9f9e1b4882f0c4380f18a4a8">13447</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSARFE_Pos (8U) </span></div>
|
||
<div class="line"><a id="l13448" name="l13448"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga553bc2c98222a09ce2a60fb0c098763e">13448</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) </span></div>
|
||
<div class="line"><a id="l13449" name="l13449"></a><span class="lineno">13449</span><span class="preprocessor">#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk </span><span class="comment">/* Time stamp snapshot for all received frames enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13450" name="l13450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga764ac2859fe42ac27c1c462c9889e1f1">13450</a></span> </div>
|
||
<div class="line"><a id="l13451" name="l13451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae38f60d94f4dd3d08f4ef813911adf79">13451</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSARU_Pos (5U) </span></div>
|
||
<div class="line"><a id="l13452" name="l13452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19406b465c944a3e465a8077cbfbf39e">13452</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) </span></div>
|
||
<div class="line"><a id="l13453" name="l13453"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9464fe8bfc44323aee790eb0768f6ab">13453</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk </span><span class="comment">/* Addend register update */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13454" name="l13454"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3731fcd0a402ff13734764182b29c99a">13454</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSITE_Pos (4U) </span></div>
|
||
<div class="line"><a id="l13455" name="l13455"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44670d6793da45549fb7ea38c3523783">13455</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos) </span></div>
|
||
<div class="line"><a id="l13456" name="l13456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga145b98f9a8b88b60ea10329203fbb745">13456</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk </span><span class="comment">/* Time stamp interrupt trigger enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13457" name="l13457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8573e45d80d88e5c90149584b3692421">13457</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSTU_Pos (3U) </span></div>
|
||
<div class="line"><a id="l13458" name="l13458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga589a3a200c3f68543f556432cdb98075">13458</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos) </span></div>
|
||
<div class="line"><a id="l13459" name="l13459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6405b2ac005034ee0ea0642f19efad4b">13459</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk </span><span class="comment">/* Time stamp update */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13460" name="l13460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88c53dbf12851d2e912b3748de382452">13460</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSTI_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13461" name="l13461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad484f7a6e6df6b3f2131d3bfb3dba856">13461</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos) </span></div>
|
||
<div class="line"><a id="l13462" name="l13462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga428f2c4ef53f655e679732f632c6f490">13462</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk </span><span class="comment">/* Time stamp initialize */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13463" name="l13463"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29d78884eed541cedaf8b46b6914899d">13463</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSFCU_Pos (1U) </span></div>
|
||
<div class="line"><a id="l13464" name="l13464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e58e22d5668ebf118f67df5eb13e834">13464</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos) </span></div>
|
||
<div class="line"><a id="l13465" name="l13465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga228aab4066179e8e0a8bb44d5a2205aa">13465</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk </span><span class="comment">/* Time stamp fine or coarse update */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13466" name="l13466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa354e48ec338c1aeb40ec642b98b49e5">13466</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSE_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13467" name="l13467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c1129b1d368bdef0c5c07d9acf8edd7">13467</a></span><span class="preprocessor">#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos) </span></div>
|
||
<div class="line"><a id="l13468" name="l13468"></a><span class="lineno">13468</span><span class="preprocessor">#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk </span><span class="comment">/* Time stamp enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13469" name="l13469"></a><span class="lineno">13469</span> </div>
|
||
<div class="line"><a id="l13470" name="l13470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3855f0e2e250856a890efb4a29b68c6">13470</a></span><span class="comment">/* Bit definition for Ethernet PTP Sub-Second Increment Register */</span></div>
|
||
<div class="line"><a id="l13471" name="l13471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fef6f1da60d4682780fd1ef4cf3435f">13471</a></span><span class="preprocessor">#define ETH_PTPSSIR_STSSI_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13472" name="l13472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab51d59cd679f65a179fe5e271b63a22c">13472</a></span><span class="preprocessor">#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos) </span></div>
|
||
<div class="line"><a id="l13473" name="l13473"></a><span class="lineno">13473</span><span class="preprocessor">#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk </span><span class="comment">/* System time Sub-second increment value */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13474" name="l13474"></a><span class="lineno">13474</span> </div>
|
||
<div class="line"><a id="l13475" name="l13475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e50177b2fb9ba8ac977b0dec45787fc">13475</a></span><span class="comment">/* Bit definition for Ethernet PTP Time Stamp High Register */</span></div>
|
||
<div class="line"><a id="l13476" name="l13476"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac54fba4639ea8278ac2679ecf5693f11">13476</a></span><span class="preprocessor">#define ETH_PTPTSHR_STS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13477" name="l13477"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4e066e9342e4f16955c1506d64b26d5">13477</a></span><span class="preprocessor">#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) </span></div>
|
||
<div class="line"><a id="l13478" name="l13478"></a><span class="lineno">13478</span><span class="preprocessor">#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk </span><span class="comment">/* System Time second */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13479" name="l13479"></a><span class="lineno">13479</span> </div>
|
||
<div class="line"><a id="l13480" name="l13480"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7678974b934e9b460c8f2525a2f0ead">13480</a></span><span class="comment">/* Bit definition for Ethernet PTP Time Stamp Low Register */</span></div>
|
||
<div class="line"><a id="l13481" name="l13481"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57b0d4d7480472e548d2745b71c73884">13481</a></span><span class="preprocessor">#define ETH_PTPTSLR_STPNS_Pos (31U) </span></div>
|
||
<div class="line"><a id="l13482" name="l13482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5db7e66364e5d2022b53561fc6fcbfc6">13482</a></span><span class="preprocessor">#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos) </span></div>
|
||
<div class="line"><a id="l13483" name="l13483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa00f00cc105d644a374cd3ec55f191d6">13483</a></span><span class="preprocessor">#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk </span><span class="comment">/* System Time Positive or negative time */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13484" name="l13484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ea6ac5920c1f09cda85a6efe885d159">13484</a></span><span class="preprocessor">#define ETH_PTPTSLR_STSS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13485" name="l13485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56d984d62fb4bfdc0677734863135ade">13485</a></span><span class="preprocessor">#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) </span></div>
|
||
<div class="line"><a id="l13486" name="l13486"></a><span class="lineno">13486</span><span class="preprocessor">#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk </span><span class="comment">/* System Time sub-seconds */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13487" name="l13487"></a><span class="lineno">13487</span> </div>
|
||
<div class="line"><a id="l13488" name="l13488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d89a6613925b5dd9ec20932d66fdb44">13488</a></span><span class="comment">/* Bit definition for Ethernet PTP Time Stamp High Update Register */</span></div>
|
||
<div class="line"><a id="l13489" name="l13489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b1af8c724a3bb0fbbc8d796581df651">13489</a></span><span class="preprocessor">#define ETH_PTPTSHUR_TSUS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13490" name="l13490"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga790cfc8e9a003b703e25d158e3490066">13490</a></span><span class="preprocessor">#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) </span></div>
|
||
<div class="line"><a id="l13491" name="l13491"></a><span class="lineno">13491</span><span class="preprocessor">#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk </span><span class="comment">/* Time stamp update seconds */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13492" name="l13492"></a><span class="lineno">13492</span> </div>
|
||
<div class="line"><a id="l13493" name="l13493"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf93e24b10684dff6d8a03817019e807c">13493</a></span><span class="comment">/* Bit definition for Ethernet PTP Time Stamp Low Update Register */</span></div>
|
||
<div class="line"><a id="l13494" name="l13494"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79eba1ff6e2e10261b485928bdaf9826">13494</a></span><span class="preprocessor">#define ETH_PTPTSLUR_TSUPNS_Pos (31U) </span></div>
|
||
<div class="line"><a id="l13495" name="l13495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae03c675fcd71d14198665cb8c5956086">13495</a></span><span class="preprocessor">#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) </span></div>
|
||
<div class="line"><a id="l13496" name="l13496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f59fc90e2a93ca826f9a221a0543254">13496</a></span><span class="preprocessor">#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk </span><span class="comment">/* Time stamp update Positive or negative time */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13497" name="l13497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40c328002f73284b6216df8d8390a040">13497</a></span><span class="preprocessor">#define ETH_PTPTSLUR_TSUSS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13498" name="l13498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17fdf1f11b40e68b24a27eb2c60f50b1">13498</a></span><span class="preprocessor">#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) </span></div>
|
||
<div class="line"><a id="l13499" name="l13499"></a><span class="lineno">13499</span><span class="preprocessor">#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk </span><span class="comment">/* Time stamp update sub-seconds */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13500" name="l13500"></a><span class="lineno">13500</span> </div>
|
||
<div class="line"><a id="l13501" name="l13501"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga142199a59a370ae94ef43febe1f0e27b">13501</a></span><span class="comment">/* Bit definition for Ethernet PTP Time Stamp Addend Register */</span></div>
|
||
<div class="line"><a id="l13502" name="l13502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f67b7a220cf80fec5ea4c9cd642fef3">13502</a></span><span class="preprocessor">#define ETH_PTPTSAR_TSA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13503" name="l13503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab944b9f1ceff57bb31beb689a19537c4">13503</a></span><span class="preprocessor">#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) </span></div>
|
||
<div class="line"><a id="l13504" name="l13504"></a><span class="lineno">13504</span><span class="preprocessor">#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk </span><span class="comment">/* Time stamp addend */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13505" name="l13505"></a><span class="lineno">13505</span> </div>
|
||
<div class="line"><a id="l13506" name="l13506"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a1209cf78ca23936fc172c225bcd13d">13506</a></span><span class="comment">/* Bit definition for Ethernet PTP Target Time High Register */</span></div>
|
||
<div class="line"><a id="l13507" name="l13507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80aac932c3b5b9dc4cffb160f27431af">13507</a></span><span class="preprocessor">#define ETH_PTPTTHR_TTSH_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13508" name="l13508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21db9a6b88a17aef32ccce70f017329e">13508</a></span><span class="preprocessor">#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) </span></div>
|
||
<div class="line"><a id="l13509" name="l13509"></a><span class="lineno">13509</span><span class="preprocessor">#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk </span><span class="comment">/* Target time stamp high */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13510" name="l13510"></a><span class="lineno">13510</span> </div>
|
||
<div class="line"><a id="l13511" name="l13511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafccab56e7239c4fc0c2c260ce3da9567">13511</a></span><span class="comment">/* Bit definition for Ethernet PTP Target Time Low Register */</span></div>
|
||
<div class="line"><a id="l13512" name="l13512"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7606deb781bd37b7ee59b6adcf9bc58f">13512</a></span><span class="preprocessor">#define ETH_PTPTTLR_TTSL_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13513" name="l13513"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61e7a9592215e36a8db010374f57d210">13513</a></span><span class="preprocessor">#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) </span></div>
|
||
<div class="line"><a id="l13514" name="l13514"></a><span class="lineno">13514</span><span class="preprocessor">#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk </span><span class="comment">/* Target time stamp low */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13515" name="l13515"></a><span class="lineno">13515</span> </div>
|
||
<div class="line"><a id="l13516" name="l13516"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a68e0dabcaf5d552e664091d33bf4a0">13516</a></span><span class="comment">/* Bit definition for Ethernet PTP Time Stamp Status Register */</span></div>
|
||
<div class="line"><a id="l13517" name="l13517"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6231f5b648b131af03c3eac1c3a01182">13517</a></span><span class="preprocessor">#define ETH_PTPTSSR_TSTTR_Pos (5U) </span></div>
|
||
<div class="line"><a id="l13518" name="l13518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga491e96ebf2d049900f049cead51f320a">13518</a></span><span class="preprocessor">#define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos) </span></div>
|
||
<div class="line"><a id="l13519" name="l13519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf46c9260e7e81f588ddc44c647ea9275">13519</a></span><span class="preprocessor">#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk </span><span class="comment">/* Time stamp target time reached */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13520" name="l13520"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga838b3f40f55f1ec42e054e2bc13af891">13520</a></span><span class="preprocessor">#define ETH_PTPTSSR_TSSO_Pos (4U) </span></div>
|
||
<div class="line"><a id="l13521" name="l13521"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa245035f820779346591bee91d96b473">13521</a></span><span class="preprocessor">#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) </span></div>
|
||
<div class="line"><a id="l13522" name="l13522"></a><span class="lineno">13522</span><span class="preprocessor">#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk </span><span class="comment">/* Time stamp seconds overflow */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13523" name="l13523"></a><span class="lineno">13523</span> </div>
|
||
<div class="line"><a id="l13524" name="l13524"></a><span class="lineno">13524</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l13525" name="l13525"></a><span class="lineno">13525</span><span class="comment">/* Ethernet DMA Registers bits definition */</span></div>
|
||
<div class="line"><a id="l13526" name="l13526"></a><span class="lineno">13526</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l13527" name="l13527"></a><span class="lineno">13527</span> </div>
|
||
<div class="line"><a id="l13528" name="l13528"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6754f2bead2bd9b49eeba732d109220e">13528</a></span><span class="comment">/* Bit definition for Ethernet DMA Bus Mode Register */</span></div>
|
||
<div class="line"><a id="l13529" name="l13529"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafccc7781fcfe97b198cd1dc91959e0e9">13529</a></span><span class="preprocessor">#define ETH_DMABMR_MB_Pos (26U)</span></div>
|
||
<div class="line"><a id="l13530" name="l13530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02d5b9592d4cb586352b11bc6ed179ff">13530</a></span><span class="preprocessor">#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) </span></div>
|
||
<div class="line"><a id="l13531" name="l13531"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e542f89aee68bd91d90d7546db209de">13531</a></span><span class="preprocessor">#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk </span><span class="comment">/* Mixed Burst */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13532" name="l13532"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f5eca1e6932299715114700f0015d2e">13532</a></span><span class="preprocessor">#define ETH_DMABMR_AAB_Pos (25U) </span></div>
|
||
<div class="line"><a id="l13533" name="l13533"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacec4fa12c34dc8fcacc2271f09ed0cbd">13533</a></span><span class="preprocessor">#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) </span></div>
|
||
<div class="line"><a id="l13534" name="l13534"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4fabf93610f531f3f2f1f4a601fe2498">13534</a></span><span class="preprocessor">#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk </span><span class="comment">/* Address-Aligned beats */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13535" name="l13535"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fdb196d2e2aba0246e12581b915f783">13535</a></span><span class="preprocessor">#define ETH_DMABMR_FPM_Pos (24U) </span></div>
|
||
<div class="line"><a id="l13536" name="l13536"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcb4414b6567f8b131712e0dc5c62beb">13536</a></span><span class="preprocessor">#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos) </span></div>
|
||
<div class="line"><a id="l13537" name="l13537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9c6b22e49c424a0c8380a6ac0b1716a">13537</a></span><span class="preprocessor">#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk </span><span class="comment">/* 4xPBL mode */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13538" name="l13538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f99d342b5c91127b4ab8a4b34ab19f8">13538</a></span><span class="preprocessor">#define ETH_DMABMR_USP_Pos (23U) </span></div>
|
||
<div class="line"><a id="l13539" name="l13539"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91e71c4054613222a8610bde0b191d00">13539</a></span><span class="preprocessor">#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos) </span></div>
|
||
<div class="line"><a id="l13540" name="l13540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e6b2716719f507d7cb5e7d140ac6fb9">13540</a></span><span class="preprocessor">#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk </span><span class="comment">/* Use separate PBL */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13541" name="l13541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45be619f0c8fa338658381e077b36fbb">13541</a></span><span class="preprocessor">#define ETH_DMABMR_RDP_Pos (17U) </span></div>
|
||
<div class="line"><a id="l13542" name="l13542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f8be5fad8f704e418e3d799d4c6d3d1">13542</a></span><span class="preprocessor">#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos) </span></div>
|
||
<div class="line"><a id="l13543" name="l13543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac56caa9d3b3a4300bd1aa0405131d7b9">13543</a></span><span class="preprocessor">#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk </span><span class="comment">/* RxDMA PBL */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13544" name="l13544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf9bcd9870547bd6f454db6667ccdecb">13544</a></span><span class="preprocessor">#define ETH_DMABMR_RDP_1Beat 0x00020000U </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 1 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13545" name="l13545"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf514499cdf6581fdcff5eaad5e6ab12f">13545</a></span><span class="preprocessor">#define ETH_DMABMR_RDP_2Beat 0x00040000U </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 2 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13546" name="l13546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5b0089dafe1c8c2410127e93ea40681">13546</a></span><span class="preprocessor">#define ETH_DMABMR_RDP_4Beat 0x00080000U </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 4 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13547" name="l13547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ed1d26d7d55828eadcea86f774c5dd3">13547</a></span><span class="preprocessor">#define ETH_DMABMR_RDP_8Beat 0x00100000U </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 8 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13548" name="l13548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3636f50cc2841e5a945f7e908420cbd5">13548</a></span><span class="preprocessor">#define ETH_DMABMR_RDP_16Beat 0x00200000U </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 16 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13549" name="l13549"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a8ea3f877aaa74f8ea2d1a788ae3180">13549</a></span><span class="preprocessor">#define ETH_DMABMR_RDP_32Beat 0x00400000U </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 32 */</span><span class="preprocessor"> </span></div>
|
||
<div class="line"><a id="l13550" name="l13550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f0258c404d957601ae069a77c82d39b">13550</a></span><span class="preprocessor">#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 4 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13551" name="l13551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ebf97fad14c750a087ed09210e42a1b">13551</a></span><span class="preprocessor">#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 8 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13552" name="l13552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5e2d5606e920b57f303f032b0bad32b">13552</a></span><span class="preprocessor">#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 16 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13553" name="l13553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1eab5835a2d15d943d5a8fbed274478">13553</a></span><span class="preprocessor">#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 32 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13554" name="l13554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ea2c20d00d2428c5f6a8fe4d7ebb392">13554</a></span><span class="preprocessor">#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 64 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13555" name="l13555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c8d22bcd14946c499d9a638e7aedc25">13555</a></span><span class="preprocessor">#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 128 */</span><span class="preprocessor"> </span></div>
|
||
<div class="line"><a id="l13556" name="l13556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga062f6878427a5d9cbb00432cc046ca7d">13556</a></span><span class="preprocessor">#define ETH_DMABMR_FB_Pos (16U) </span></div>
|
||
<div class="line"><a id="l13557" name="l13557"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga717f163fe72c7e1c999123160dde4143">13557</a></span><span class="preprocessor">#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos) </span></div>
|
||
<div class="line"><a id="l13558" name="l13558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e0752bf3c2a9ad5f6c2539dcf50a849">13558</a></span><span class="preprocessor">#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk </span><span class="comment">/* Fixed Burst */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13559" name="l13559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac84d16b246ae40bcd90ef3a5a000bc59">13559</a></span><span class="preprocessor">#define ETH_DMABMR_RTPR_Pos (14U) </span></div>
|
||
<div class="line"><a id="l13560" name="l13560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae06b7c29931b088e66f13b055aaddcd6">13560</a></span><span class="preprocessor">#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos) </span></div>
|
||
<div class="line"><a id="l13561" name="l13561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga478e7d5ec02db7237be51fa5b83b9e25">13561</a></span><span class="preprocessor">#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk </span><span class="comment">/* Rx Tx priority ratio */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13562" name="l13562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d9e5dda525076cc163bdc29f18e4055">13562</a></span><span class="preprocessor">#define ETH_DMABMR_RTPR_1_1 0x00000000U </span><span class="comment">/* Rx Tx priority ratio */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13563" name="l13563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9e4fd353c5a9ecee3feb428eb54ce2b">13563</a></span><span class="preprocessor">#define ETH_DMABMR_RTPR_2_1 0x00004000U </span><span class="comment">/* Rx Tx priority ratio */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13564" name="l13564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad6d57a1f21bc958fa0cfab0cfed02b1">13564</a></span><span class="preprocessor">#define ETH_DMABMR_RTPR_3_1 0x00008000U </span><span class="comment">/* Rx Tx priority ratio */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13565" name="l13565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b37497a07a1d574524931c0d35f62a1">13565</a></span><span class="preprocessor">#define ETH_DMABMR_RTPR_4_1 0x0000C000U </span><span class="comment">/* Rx Tx priority ratio */</span><span class="preprocessor"> </span></div>
|
||
<div class="line"><a id="l13566" name="l13566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga640bcbad2f68125c7593018245c80db6">13566</a></span><span class="preprocessor">#define ETH_DMABMR_PBL_Pos (8U) </span></div>
|
||
<div class="line"><a id="l13567" name="l13567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e3daa2867b6d01e8eda765e77648599">13567</a></span><span class="preprocessor">#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos) </span></div>
|
||
<div class="line"><a id="l13568" name="l13568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefeb5f1c9376d0a0bc956aba567c7cb9">13568</a></span><span class="preprocessor">#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk </span><span class="comment">/* Programmable burst length */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13569" name="l13569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a034f8cf671cba686e882172ad93949">13569</a></span><span class="preprocessor">#define ETH_DMABMR_PBL_1Beat 0x00000100U </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13570" name="l13570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55ff9b7cebc3489fcaab886a065d372c">13570</a></span><span class="preprocessor">#define ETH_DMABMR_PBL_2Beat 0x00000200U </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13571" name="l13571"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae920200ec813649824a20b434c1eecb5">13571</a></span><span class="preprocessor">#define ETH_DMABMR_PBL_4Beat 0x00000400U </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13572" name="l13572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6351d1d02e94053527b8e18f393b1e82">13572</a></span><span class="preprocessor">#define ETH_DMABMR_PBL_8Beat 0x00000800U </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13573" name="l13573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82d8ee65c1583f4ec9092bc45563d720">13573</a></span><span class="preprocessor">#define ETH_DMABMR_PBL_16Beat 0x00001000U </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13574" name="l13574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89566024f4f6772d59592f5bacc7828d">13574</a></span><span class="preprocessor">#define ETH_DMABMR_PBL_32Beat 0x00002000U </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */</span><span class="preprocessor"> </span></div>
|
||
<div class="line"><a id="l13575" name="l13575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33acf850c7d6f97899f69d76d87a3dd6">13575</a></span><span class="preprocessor">#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13576" name="l13576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5c68f3a0a692fbd81bac47bfe2340bb">13576</a></span><span class="preprocessor">#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13577" name="l13577"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21298fccc783e5c6d65b9d64960b4ca2">13577</a></span><span class="preprocessor">#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13578" name="l13578"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40a789fc58356a8084c5f1eeba366de2">13578</a></span><span class="preprocessor">#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13579" name="l13579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c90887a852a858c630ac388bec0b392">13579</a></span><span class="preprocessor">#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13580" name="l13580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga772af3cfca1669d65c2eb16413483032">13580</a></span><span class="preprocessor">#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13581" name="l13581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18544872c7f55ac2011ff1fe2ab6d353">13581</a></span><span class="preprocessor">#define ETH_DMABMR_EDE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l13582" name="l13582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf04f1ef51af153093743c190d25ea21b">13582</a></span><span class="preprocessor">#define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos) </span></div>
|
||
<div class="line"><a id="l13583" name="l13583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff399b83a19a6a62457cd0877bea35b7">13583</a></span><span class="preprocessor">#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk </span><span class="comment">/* Enhanced Descriptor Enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13584" name="l13584"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c0974106bccb288a14a4f5b055f2a88">13584</a></span><span class="preprocessor">#define ETH_DMABMR_DSL_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13585" name="l13585"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1931fd959cb78283ab0cf0bd9804387">13585</a></span><span class="preprocessor">#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos) </span></div>
|
||
<div class="line"><a id="l13586" name="l13586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabad048a02b9fbed0c5824a6a632d0daf">13586</a></span><span class="preprocessor">#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk </span><span class="comment">/* Descriptor Skip Length */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13587" name="l13587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7bd68646897581a06cbee2dacbdd0c14">13587</a></span><span class="preprocessor">#define ETH_DMABMR_DA_Pos (1U) </span></div>
|
||
<div class="line"><a id="l13588" name="l13588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd126734c36f2db46c51e73cef07afce">13588</a></span><span class="preprocessor">#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos) </span></div>
|
||
<div class="line"><a id="l13589" name="l13589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacef0ceff9d1440c18e92a28da757a8df">13589</a></span><span class="preprocessor">#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk </span><span class="comment">/* DMA arbitration scheme */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13590" name="l13590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf0350e3541f1c466e6544db265e36a4">13590</a></span><span class="preprocessor">#define ETH_DMABMR_SR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13591" name="l13591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e8dfe321aeaecaa87e290f4d6e710dc">13591</a></span><span class="preprocessor">#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos) </span></div>
|
||
<div class="line"><a id="l13592" name="l13592"></a><span class="lineno">13592</span><span class="preprocessor">#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk </span><span class="comment">/* Software reset */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13593" name="l13593"></a><span class="lineno">13593</span> </div>
|
||
<div class="line"><a id="l13594" name="l13594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37cc58720fbe96f7130a00e32023189f">13594</a></span><span class="comment">/* Bit definition for Ethernet DMA Transmit Poll Demand Register */</span></div>
|
||
<div class="line"><a id="l13595" name="l13595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04187d48766f865c479d26d2c6225fa9">13595</a></span><span class="preprocessor">#define ETH_DMATPDR_TPD_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13596" name="l13596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef2d9dbefaa6940adf6422092fae2da6">13596</a></span><span class="preprocessor">#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) </span></div>
|
||
<div class="line"><a id="l13597" name="l13597"></a><span class="lineno">13597</span><span class="preprocessor">#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk </span><span class="comment">/* Transmit poll demand */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13598" name="l13598"></a><span class="lineno">13598</span> </div>
|
||
<div class="line"><a id="l13599" name="l13599"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05a0babc0d1d7b6a2ff358a8ff819fb5">13599</a></span><span class="comment">/* Bit definition for Ethernet DMA Receive Poll Demand Register */</span></div>
|
||
<div class="line"><a id="l13600" name="l13600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56d192c68de928fdbb181eb063145446">13600</a></span><span class="preprocessor">#define ETH_DMARPDR_RPD_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13601" name="l13601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83f1c5a5628c6e7dcd853e511eac49e8">13601</a></span><span class="preprocessor">#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) </span></div>
|
||
<div class="line"><a id="l13602" name="l13602"></a><span class="lineno">13602</span><span class="preprocessor">#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk </span><span class="comment">/* Receive poll demand */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13603" name="l13603"></a><span class="lineno">13603</span> </div>
|
||
<div class="line"><a id="l13604" name="l13604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b8637d2710b95d2994fb20e620c6ee5">13604</a></span><span class="comment">/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */</span></div>
|
||
<div class="line"><a id="l13605" name="l13605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5cc8aee0138d0f2bfaf2c684376949f">13605</a></span><span class="preprocessor">#define ETH_DMARDLAR_SRL_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13606" name="l13606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34e60ae1c7b80cf199c372b5e701b46e">13606</a></span><span class="preprocessor">#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) </span></div>
|
||
<div class="line"><a id="l13607" name="l13607"></a><span class="lineno">13607</span><span class="preprocessor">#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk </span><span class="comment">/* Start of receive list */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13608" name="l13608"></a><span class="lineno">13608</span> </div>
|
||
<div class="line"><a id="l13609" name="l13609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6a7932a4408e67d5c10d5a2d18f9385">13609</a></span><span class="comment">/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */</span></div>
|
||
<div class="line"><a id="l13610" name="l13610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga001a009e3ed3f0fa5c8b8d99839d4f16">13610</a></span><span class="preprocessor">#define ETH_DMATDLAR_STL_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13611" name="l13611"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f9f12964bc4e019afface14df2dc87c">13611</a></span><span class="preprocessor">#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) </span></div>
|
||
<div class="line"><a id="l13612" name="l13612"></a><span class="lineno">13612</span><span class="preprocessor">#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk </span><span class="comment">/* Start of transmit list */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13613" name="l13613"></a><span class="lineno">13613</span> </div>
|
||
<div class="line"><a id="l13614" name="l13614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f397466df0a01f13dbc1487726a6fbc">13614</a></span><span class="comment">/* Bit definition for Ethernet DMA Status Register */</span></div>
|
||
<div class="line"><a id="l13615" name="l13615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72e40eb362f28f7ea04d874e73e70072">13615</a></span><span class="preprocessor">#define ETH_DMASR_TSTS_Pos (29U) </span></div>
|
||
<div class="line"><a id="l13616" name="l13616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac55027d33ea49f5498f5c9a0dab629d7">13616</a></span><span class="preprocessor">#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos) </span></div>
|
||
<div class="line"><a id="l13617" name="l13617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9532f43143213e838dd0ab5a24caf78">13617</a></span><span class="preprocessor">#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk </span><span class="comment">/* Time-stamp trigger status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13618" name="l13618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92bdb1d530baa75204516d6c8045f1dc">13618</a></span><span class="preprocessor">#define ETH_DMASR_PMTS_Pos (28U) </span></div>
|
||
<div class="line"><a id="l13619" name="l13619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4792ff5cd86cdea1edf34ea90448b34a">13619</a></span><span class="preprocessor">#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos) </span></div>
|
||
<div class="line"><a id="l13620" name="l13620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb58a6756ac7507049b458b398a3d6c4">13620</a></span><span class="preprocessor">#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk </span><span class="comment">/* PMT status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13621" name="l13621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5366f0a075f3c6821b4bade162bfc151">13621</a></span><span class="preprocessor">#define ETH_DMASR_MMCS_Pos (27U) </span></div>
|
||
<div class="line"><a id="l13622" name="l13622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d6207fe0c8383456188e9bb1e2fb9fe">13622</a></span><span class="preprocessor">#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos) </span></div>
|
||
<div class="line"><a id="l13623" name="l13623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad430939a2de7c270ecb359c5d1a32670">13623</a></span><span class="preprocessor">#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk </span><span class="comment">/* MMC status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13624" name="l13624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf72d998538d5fcb41440f203e916edc">13624</a></span><span class="preprocessor">#define ETH_DMASR_EBS_Pos (23U) </span></div>
|
||
<div class="line"><a id="l13625" name="l13625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga098b5395babfd8474a75a5a2034c94f2">13625</a></span><span class="preprocessor">#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos) </span></div>
|
||
<div class="line"><a id="l13626" name="l13626"></a><span class="lineno">13626</span><span class="preprocessor">#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk </span><span class="comment">/* Error bits status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13627" name="l13627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga357bae318615787a3891c3c493b916d7">13627</a></span> <span class="comment">/* combination with EBS[2:0] for GetFlagStatus function */</span></div>
|
||
<div class="line"><a id="l13628" name="l13628"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d01e1b20f21d635fd0e195148b12609">13628</a></span><span class="preprocessor">#define ETH_DMASR_EBS_DescAccess_Pos (25U) </span></div>
|
||
<div class="line"><a id="l13629" name="l13629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42e1dfda0e23a1ae10c0c05c405e5c73">13629</a></span><span class="preprocessor">#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) </span></div>
|
||
<div class="line"><a id="l13630" name="l13630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ec84cb6fb224f4511dd259a9947c6b3">13630</a></span><span class="preprocessor">#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk </span><span class="comment">/* Error bits 0-data buffer, 1-desc. access */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13631" name="l13631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ba2f75d57b076dd6fd741eb85569ea0">13631</a></span><span class="preprocessor">#define ETH_DMASR_EBS_ReadTransf_Pos (24U) </span></div>
|
||
<div class="line"><a id="l13632" name="l13632"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga315c68184fd0f0e510539dc8cd986393">13632</a></span><span class="preprocessor">#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) </span></div>
|
||
<div class="line"><a id="l13633" name="l13633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad72b89b7da590a72f8e9061c96111dbf">13633</a></span><span class="preprocessor">#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk </span><span class="comment">/* Error bits 0-write trnsf, 1-read transfr */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13634" name="l13634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb5f3f939bfb190ddd5837ecb203a7db">13634</a></span><span class="preprocessor">#define ETH_DMASR_EBS_DataTransfTx_Pos (23U) </span></div>
|
||
<div class="line"><a id="l13635" name="l13635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd56804ed872078d962ef5f01dc295e1">13635</a></span><span class="preprocessor">#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) </span></div>
|
||
<div class="line"><a id="l13636" name="l13636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9c98699ea2df54364b5232ff3d1cd30">13636</a></span><span class="preprocessor">#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk </span><span class="comment">/* Error bits 0-Rx DMA, 1-Tx DMA */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13637" name="l13637"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga706f64bbf5b12368955bc3d0fdba6a39">13637</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Pos (20U) </span></div>
|
||
<div class="line"><a id="l13638" name="l13638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga806073adcecb9139b1c1d7ed35a4f37c">13638</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos) </span></div>
|
||
<div class="line"><a id="l13639" name="l13639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c0d4830c8196127e9b26178b23b6f3e">13639</a></span><span class="preprocessor">#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk </span><span class="comment">/* Transmit process state */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13640" name="l13640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85ca0bb143abb15cf11a7edd9d5ca974">13640</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Stopped 0x00000000U </span><span class="comment">/* Stopped - Reset or Stop Tx Command issued */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13641" name="l13641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81cc65263215ebdbae36ff6f983e5611">13641</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Fetching_Pos (20U) </span></div>
|
||
<div class="line"><a id="l13642" name="l13642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd9af883f17d4bbbdde6866ecf67afe2">13642</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos) </span></div>
|
||
<div class="line"><a id="l13643" name="l13643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73cefac3fbaeed6be54b48bd24de4b8b">13643</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk </span><span class="comment">/* Running - fetching the Tx descriptor */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13644" name="l13644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga372a83db64b04814ac01ef9b072bdb09">13644</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Waiting_Pos (21U) </span></div>
|
||
<div class="line"><a id="l13645" name="l13645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga351ab7003c342ab1b43f9fd158fdc00d">13645</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos) </span></div>
|
||
<div class="line"><a id="l13646" name="l13646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1f8f06d72c8a90d32f78cd39ba9abee">13646</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk </span><span class="comment">/* Running - waiting for status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13647" name="l13647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76229b644063a64e1939b3c9e75c2539">13647</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Reading_Pos (20U) </span></div>
|
||
<div class="line"><a id="l13648" name="l13648"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72af54920faf4b54e760c3784dccaf65">13648</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos) </span></div>
|
||
<div class="line"><a id="l13649" name="l13649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1d5230313ea8ab7b2990fac846a769b">13649</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk </span><span class="comment">/* Running - reading the data from host memory */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13650" name="l13650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabebe05fb2f636f75f5cd2da28d465d8d">13650</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Suspended_Pos (21U) </span></div>
|
||
<div class="line"><a id="l13651" name="l13651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80b3558db79b5903dd3966ceed7bb1e8">13651</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos) </span></div>
|
||
<div class="line"><a id="l13652" name="l13652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98d18b94cc18a69e4522d1d4b4249a8e">13652</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk </span><span class="comment">/* Suspended - Tx Descriptor unavailable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13653" name="l13653"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga367081b68077417f3556e514f5ca1771">13653</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Closing_Pos (20U) </span></div>
|
||
<div class="line"><a id="l13654" name="l13654"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6e95d2a805ec4d8e50de467825c86e0">13654</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos) </span></div>
|
||
<div class="line"><a id="l13655" name="l13655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb7b51984ea407e0d049606fcc59b665">13655</a></span><span class="preprocessor">#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk </span><span class="comment">/* Running - closing Rx descriptor */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13656" name="l13656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade55bf5c8f6788537f16f5c535fca9df">13656</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Pos (17U) </span></div>
|
||
<div class="line"><a id="l13657" name="l13657"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae773175991a44530bcd26057a7b3819e">13657</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos) </span></div>
|
||
<div class="line"><a id="l13658" name="l13658"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a2dfc943902722a1bce1d0a24125e45">13658</a></span><span class="preprocessor">#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk </span><span class="comment">/* Receive process state */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13659" name="l13659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a722459468b128af26661078a2e6dd3">13659</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Stopped 0x00000000U </span><span class="comment">/* Stopped - Reset or Stop Rx Command issued */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13660" name="l13660"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ebd16304081748a0fc85659ca005b74">13660</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Fetching_Pos (17U) </span></div>
|
||
<div class="line"><a id="l13661" name="l13661"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92a04f8a6f4c047967d38e4fd3f4bbb9">13661</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos) </span></div>
|
||
<div class="line"><a id="l13662" name="l13662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69b95466c40968273837da5388e29d26">13662</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk </span><span class="comment">/* Running - fetching the Rx descriptor */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13663" name="l13663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02f12914ed1c79ed445e5dbbb0e085aa">13663</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Waiting_Pos (17U) </span></div>
|
||
<div class="line"><a id="l13664" name="l13664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5440bd06e487e3ca5d64afebc8b48bac">13664</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos) </span></div>
|
||
<div class="line"><a id="l13665" name="l13665"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga465fd4ba545bbfa3ba642e65102787de">13665</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk </span><span class="comment">/* Running - waiting for packet */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13666" name="l13666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1fb0ba5f7b3373caf68328175250e96">13666</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Suspended_Pos (19U) </span></div>
|
||
<div class="line"><a id="l13667" name="l13667"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5e1406af058b582a7f60f8415edde15">13667</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos) </span></div>
|
||
<div class="line"><a id="l13668" name="l13668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d0d9e0f3ccb8bb117dc2b6b01094ff2">13668</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk </span><span class="comment">/* Suspended - Rx Descriptor unavailable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13669" name="l13669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89428a8eb321c17f0d6319d5f8409d6e">13669</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Closing_Pos (17U) </span></div>
|
||
<div class="line"><a id="l13670" name="l13670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0976a4ba0b8dcbe42fdef38a8589fda8">13670</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos) </span></div>
|
||
<div class="line"><a id="l13671" name="l13671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38c80ba33689333b6f1a08318ebb31b2">13671</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk </span><span class="comment">/* Running - closing descriptor */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13672" name="l13672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga276f57d8860566be667d03e6f38f9840">13672</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Queuing_Pos (17U) </span></div>
|
||
<div class="line"><a id="l13673" name="l13673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6aaf0193e4f15e2937cb18586567e43">13673</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) </span></div>
|
||
<div class="line"><a id="l13674" name="l13674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c5b7e682ca590e3a6069be7111c04eb">13674</a></span><span class="preprocessor">#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk </span><span class="comment">/* Running - queuing the receive frame into host memory */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13675" name="l13675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a4beec3bd9093993f5b2434b1b1e09d">13675</a></span><span class="preprocessor">#define ETH_DMASR_NIS_Pos (16U) </span></div>
|
||
<div class="line"><a id="l13676" name="l13676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8585a6af3197e49831882373410d94c">13676</a></span><span class="preprocessor">#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) </span></div>
|
||
<div class="line"><a id="l13677" name="l13677"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf97acf90b407e4b509779b5af53d230b">13677</a></span><span class="preprocessor">#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk </span><span class="comment">/* Normal interrupt summary */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13678" name="l13678"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa257027c6436c5549724db8df50284db">13678</a></span><span class="preprocessor">#define ETH_DMASR_AIS_Pos (15U) </span></div>
|
||
<div class="line"><a id="l13679" name="l13679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cb15b33a997bec75b9c8750231ee411">13679</a></span><span class="preprocessor">#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos) </span></div>
|
||
<div class="line"><a id="l13680" name="l13680"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08262d444227cc81a46fa9e3b1dff314">13680</a></span><span class="preprocessor">#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk </span><span class="comment">/* Abnormal interrupt summary */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13681" name="l13681"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1038a467b90b609a7b709b179334c33">13681</a></span><span class="preprocessor">#define ETH_DMASR_ERS_Pos (14U) </span></div>
|
||
<div class="line"><a id="l13682" name="l13682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga899d94d62f011fc56aa5814e528055f7">13682</a></span><span class="preprocessor">#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos) </span></div>
|
||
<div class="line"><a id="l13683" name="l13683"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga491afda68d7906be911a8be5e16966ae">13683</a></span><span class="preprocessor">#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk </span><span class="comment">/* Early receive status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13684" name="l13684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga616a1ac8f4d7a70430585b6461fc0ce3">13684</a></span><span class="preprocessor">#define ETH_DMASR_FBES_Pos (13U) </span></div>
|
||
<div class="line"><a id="l13685" name="l13685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab28c0a99d8d2ff948096d06b6dfdab9c">13685</a></span><span class="preprocessor">#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos) </span></div>
|
||
<div class="line"><a id="l13686" name="l13686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacea84ae95fd863044bfb89895ce0edc6">13686</a></span><span class="preprocessor">#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk </span><span class="comment">/* Fatal bus error status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13687" name="l13687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86649ab55b955dee747af1266d117270">13687</a></span><span class="preprocessor">#define ETH_DMASR_ETS_Pos (10U) </span></div>
|
||
<div class="line"><a id="l13688" name="l13688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb828d827c627f704a53dc486cec821c">13688</a></span><span class="preprocessor">#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos) </span></div>
|
||
<div class="line"><a id="l13689" name="l13689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54e86ee5eaafdcced3a4d545fa49525a">13689</a></span><span class="preprocessor">#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk </span><span class="comment">/* Early transmit status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13690" name="l13690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a3f72a3dc3b046d2771cdcbf514b175">13690</a></span><span class="preprocessor">#define ETH_DMASR_RWTS_Pos (9U) </span></div>
|
||
<div class="line"><a id="l13691" name="l13691"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ce8d0c087f96b2b5c3e1db45cd1ecf5">13691</a></span><span class="preprocessor">#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos) </span></div>
|
||
<div class="line"><a id="l13692" name="l13692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67f272abdf029d7a2f9d8f111df46102">13692</a></span><span class="preprocessor">#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk </span><span class="comment">/* Receive watchdog timeout status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13693" name="l13693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2630d1d889e82544e5f3eaaa0c73efb">13693</a></span><span class="preprocessor">#define ETH_DMASR_RPSS_Pos (8U) </span></div>
|
||
<div class="line"><a id="l13694" name="l13694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70de31c814e36b7bb2b752e7b62bf840">13694</a></span><span class="preprocessor">#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos) </span></div>
|
||
<div class="line"><a id="l13695" name="l13695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafcf0fea72f556ad86e10f1f4261fdfe">13695</a></span><span class="preprocessor">#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk </span><span class="comment">/* Receive process stopped status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13696" name="l13696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03519d5ceec7c307530cd4d84ab77a86">13696</a></span><span class="preprocessor">#define ETH_DMASR_RBUS_Pos (7U) </span></div>
|
||
<div class="line"><a id="l13697" name="l13697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5569311c70d6ededf186d9a8af19d884">13697</a></span><span class="preprocessor">#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos) </span></div>
|
||
<div class="line"><a id="l13698" name="l13698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6121b0165acc877d7927a4c4c4cde2d0">13698</a></span><span class="preprocessor">#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk </span><span class="comment">/* Receive buffer unavailable status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13699" name="l13699"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad460f6aaea486c070dec64bbe36e7fa8">13699</a></span><span class="preprocessor">#define ETH_DMASR_RS_Pos (6U) </span></div>
|
||
<div class="line"><a id="l13700" name="l13700"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40f33df77007eab0110e1ffef365a2df">13700</a></span><span class="preprocessor">#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos) </span></div>
|
||
<div class="line"><a id="l13701" name="l13701"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea24133f548e4e4cfc21d0074a61a2e6">13701</a></span><span class="preprocessor">#define ETH_DMASR_RS ETH_DMASR_RS_Msk </span><span class="comment">/* Receive status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13702" name="l13702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3a7203a5fb55c1d6a69e6daab2e961b">13702</a></span><span class="preprocessor">#define ETH_DMASR_TUS_Pos (5U) </span></div>
|
||
<div class="line"><a id="l13703" name="l13703"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2597865c464586829cec4f8d26fb1f1">13703</a></span><span class="preprocessor">#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos) </span></div>
|
||
<div class="line"><a id="l13704" name="l13704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73b5f22a117c3ef116e9506999b5a3a0">13704</a></span><span class="preprocessor">#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk </span><span class="comment">/* Transmit underflow status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13705" name="l13705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89c38680c790e1e1717c0a0c76c4f9ef">13705</a></span><span class="preprocessor">#define ETH_DMASR_ROS_Pos (4U) </span></div>
|
||
<div class="line"><a id="l13706" name="l13706"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c2f1e3cb729230b1099026b6a53b867">13706</a></span><span class="preprocessor">#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos) </span></div>
|
||
<div class="line"><a id="l13707" name="l13707"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1736d46500149b490b990061e0e6504a">13707</a></span><span class="preprocessor">#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk </span><span class="comment">/* Receive overflow status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13708" name="l13708"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43884645887bb7d31bf18e4e5709d7dc">13708</a></span><span class="preprocessor">#define ETH_DMASR_TJTS_Pos (3U) </span></div>
|
||
<div class="line"><a id="l13709" name="l13709"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c543637a7e9669b8bdb12265b5ff448">13709</a></span><span class="preprocessor">#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos) </span></div>
|
||
<div class="line"><a id="l13710" name="l13710"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadae620d299f7887143c10c6b67953637">13710</a></span><span class="preprocessor">#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk </span><span class="comment">/* Transmit jabber timeout status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13711" name="l13711"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca6dd2813fb9e0bdf4bccedba156e4c7">13711</a></span><span class="preprocessor">#define ETH_DMASR_TBUS_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13712" name="l13712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26668ea80a2d794d72c0a441aa73d0d7">13712</a></span><span class="preprocessor">#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos) </span></div>
|
||
<div class="line"><a id="l13713" name="l13713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98138bcfbccf33bbfe3e5556ebf5d394">13713</a></span><span class="preprocessor">#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk </span><span class="comment">/* Transmit buffer unavailable status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13714" name="l13714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga531f361a12151e7c1335f9133526edb5">13714</a></span><span class="preprocessor">#define ETH_DMASR_TPSS_Pos (1U) </span></div>
|
||
<div class="line"><a id="l13715" name="l13715"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad48c871e98a7794ce6cd8294baee114a">13715</a></span><span class="preprocessor">#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos) </span></div>
|
||
<div class="line"><a id="l13716" name="l13716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab853a917a2d74fa41e630058426b301d">13716</a></span><span class="preprocessor">#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk </span><span class="comment">/* Transmit process stopped status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13717" name="l13717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabfe8fdf02110a1d44c6f28f1d641d92f">13717</a></span><span class="preprocessor">#define ETH_DMASR_TS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13718" name="l13718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9aa47191609cba66df647cb7e8e10974">13718</a></span><span class="preprocessor">#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos) </span></div>
|
||
<div class="line"><a id="l13719" name="l13719"></a><span class="lineno">13719</span><span class="preprocessor">#define ETH_DMASR_TS ETH_DMASR_TS_Msk </span><span class="comment">/* Transmit status */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13720" name="l13720"></a><span class="lineno">13720</span> </div>
|
||
<div class="line"><a id="l13721" name="l13721"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60ee4d9125ea52f825f501b8fb3a5023">13721</a></span><span class="comment">/* Bit definition for Ethernet DMA Operation Mode Register */</span></div>
|
||
<div class="line"><a id="l13722" name="l13722"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57a12e235193d9a8db8d635b59287bdc">13722</a></span><span class="preprocessor">#define ETH_DMAOMR_DTCEFD_Pos (26U) </span></div>
|
||
<div class="line"><a id="l13723" name="l13723"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade93bfc37c0b1fc371b2fa1278ee7dfd">13723</a></span><span class="preprocessor">#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos) </span></div>
|
||
<div class="line"><a id="l13724" name="l13724"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac568f4c7cfdae0a997fae6d41b397772">13724</a></span><span class="preprocessor">#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk </span><span class="comment">/* Disable Dropping of TCP/IP checksum error frames */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13725" name="l13725"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac86b0ef8cd7b378ad33471bf63fabf28">13725</a></span><span class="preprocessor">#define ETH_DMAOMR_RSF_Pos (25U) </span></div>
|
||
<div class="line"><a id="l13726" name="l13726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7132ff722841d431f9c6d3fc7e0c8912">13726</a></span><span class="preprocessor">#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos) </span></div>
|
||
<div class="line"><a id="l13727" name="l13727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2b6e2a9d1a9466c95e92fe1a095158f">13727</a></span><span class="preprocessor">#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk </span><span class="comment">/* Receive store and forward */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13728" name="l13728"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58b42f95e34f9fd0fd26a720830cef43">13728</a></span><span class="preprocessor">#define ETH_DMAOMR_DFRF_Pos (24U) </span></div>
|
||
<div class="line"><a id="l13729" name="l13729"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61cfaa51bb7973e7e3c4fd6d549c88b2">13729</a></span><span class="preprocessor">#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos) </span></div>
|
||
<div class="line"><a id="l13730" name="l13730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c6ccd5e3a792ff5bb20751121db1ad4">13730</a></span><span class="preprocessor">#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk </span><span class="comment">/* Disable flushing of received frames */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13731" name="l13731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga627c0721df614ee7895be0c8603965ab">13731</a></span><span class="preprocessor">#define ETH_DMAOMR_TSF_Pos (21U) </span></div>
|
||
<div class="line"><a id="l13732" name="l13732"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga600b35b875335358746524e5f6760613">13732</a></span><span class="preprocessor">#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos) </span></div>
|
||
<div class="line"><a id="l13733" name="l13733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8d8c2e989f7e596b73202f7c41361c7">13733</a></span><span class="preprocessor">#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk </span><span class="comment">/* Transmit store and forward */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13734" name="l13734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ef2167aa40e49e8f8d49b0283a8f832">13734</a></span><span class="preprocessor">#define ETH_DMAOMR_FTF_Pos (20U) </span></div>
|
||
<div class="line"><a id="l13735" name="l13735"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ba6031456a00e99638005b7af823a49">13735</a></span><span class="preprocessor">#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos) </span></div>
|
||
<div class="line"><a id="l13736" name="l13736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b3ede16f6855eec35690336a66089e3">13736</a></span><span class="preprocessor">#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk </span><span class="comment">/* Flush transmit FIFO */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13737" name="l13737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3c316b48c8c3a4e683b6e56cefa844d">13737</a></span><span class="preprocessor">#define ETH_DMAOMR_TTC_Pos (14U) </span></div>
|
||
<div class="line"><a id="l13738" name="l13738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8af2f55493df254efed28cad7fb72651">13738</a></span><span class="preprocessor">#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos) </span></div>
|
||
<div class="line"><a id="l13739" name="l13739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca0372554b5b8c2b816071ced929b30f">13739</a></span><span class="preprocessor">#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk </span><span class="comment">/* Transmit threshold control */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13740" name="l13740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a0af7e5f2074a30e33e4845b1c72155">13740</a></span><span class="preprocessor">#define ETH_DMAOMR_TTC_64Bytes 0x00000000U </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 64 Bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13741" name="l13741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a29aa54f61418b0086bef0d8c9a4868">13741</a></span><span class="preprocessor">#define ETH_DMAOMR_TTC_128Bytes 0x00004000U </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 128 Bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13742" name="l13742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9d703eb56388097660839c0dbb2dcf4">13742</a></span><span class="preprocessor">#define ETH_DMAOMR_TTC_192Bytes 0x00008000U </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 192 Bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13743" name="l13743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6c6cd2f59e4f784ef22ca7873bcafe6">13743</a></span><span class="preprocessor">#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 256 Bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13744" name="l13744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e74522b40a38dbc62dca1cc87f7b13f">13744</a></span><span class="preprocessor">#define ETH_DMAOMR_TTC_40Bytes 0x00010000U </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 40 Bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13745" name="l13745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2e990a61fd2ca6d1f5d9e0fddfc1a76">13745</a></span><span class="preprocessor">#define ETH_DMAOMR_TTC_32Bytes 0x00014000U </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 32 Bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13746" name="l13746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c21df36ca8ecb3c2d016cd4c683aded">13746</a></span><span class="preprocessor">#define ETH_DMAOMR_TTC_24Bytes 0x00018000U </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 24 Bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13747" name="l13747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e013ae0230f9b0c4f9598bb38c93b1e">13747</a></span><span class="preprocessor">#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 16 Bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13748" name="l13748"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd2cf0246f5b06eac0b6534c9802ac29">13748</a></span><span class="preprocessor">#define ETH_DMAOMR_ST_Pos (13U) </span></div>
|
||
<div class="line"><a id="l13749" name="l13749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f15d70215b151c4c151b7b8475939ce">13749</a></span><span class="preprocessor">#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos) </span></div>
|
||
<div class="line"><a id="l13750" name="l13750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4562507352bcedf8243532c8f3509cd1">13750</a></span><span class="preprocessor">#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk </span><span class="comment">/* Start/stop transmission command */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13751" name="l13751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46da3dc9006268330b091ea369040c7e">13751</a></span><span class="preprocessor">#define ETH_DMAOMR_FEF_Pos (7U) </span></div>
|
||
<div class="line"><a id="l13752" name="l13752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ff2d7be55ac4e29a18d8490012d8d8f">13752</a></span><span class="preprocessor">#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos) </span></div>
|
||
<div class="line"><a id="l13753" name="l13753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad86ef8a3fdd31501c9ad670c6e0ee358">13753</a></span><span class="preprocessor">#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk </span><span class="comment">/* Forward error frames */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13754" name="l13754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb00925901abe34858a008f599a3949d">13754</a></span><span class="preprocessor">#define ETH_DMAOMR_FUGF_Pos (6U) </span></div>
|
||
<div class="line"><a id="l13755" name="l13755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7fb0b48ffa17fb3c37e730e63790b95">13755</a></span><span class="preprocessor">#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos) </span></div>
|
||
<div class="line"><a id="l13756" name="l13756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67e6a96f920fd6dbe951e83bab2fcbc8">13756</a></span><span class="preprocessor">#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk </span><span class="comment">/* Forward undersized good frames */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13757" name="l13757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a10ffb355ad5a39fcee6c591a74c4f1">13757</a></span><span class="preprocessor">#define ETH_DMAOMR_RTC_Pos (3U) </span></div>
|
||
<div class="line"><a id="l13758" name="l13758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00653932f863ff8c73752e4dea63283d">13758</a></span><span class="preprocessor">#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos) </span></div>
|
||
<div class="line"><a id="l13759" name="l13759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29ec3c609bf796437bb50879be53974e">13759</a></span><span class="preprocessor">#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk </span><span class="comment">/* receive threshold control */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13760" name="l13760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f4f5e1950abb65d6ed23e30994b7a26">13760</a></span><span class="preprocessor">#define ETH_DMAOMR_RTC_64Bytes 0x00000000U </span><span class="comment">/* threshold level of the MTL Receive FIFO is 64 Bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13761" name="l13761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf73706fb0cf9a03909a55e3bcd19c75c">13761</a></span><span class="preprocessor">#define ETH_DMAOMR_RTC_32Bytes 0x00000008U </span><span class="comment">/* threshold level of the MTL Receive FIFO is 32 Bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13762" name="l13762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7099f07f7c61fdc118cebe38db796e9">13762</a></span><span class="preprocessor">#define ETH_DMAOMR_RTC_96Bytes 0x00000010U </span><span class="comment">/* threshold level of the MTL Receive FIFO is 96 Bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13763" name="l13763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0704646af78b6cf53b47640835429ae">13763</a></span><span class="preprocessor">#define ETH_DMAOMR_RTC_128Bytes 0x00000018U </span><span class="comment">/* threshold level of the MTL Receive FIFO is 128 Bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13764" name="l13764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3643718f1c533d40fd4f9868544cdb66">13764</a></span><span class="preprocessor">#define ETH_DMAOMR_OSF_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13765" name="l13765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a9e1270eefa558420deba526b7cd2c2">13765</a></span><span class="preprocessor">#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos) </span></div>
|
||
<div class="line"><a id="l13766" name="l13766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac945eacab78cad8b2f6149ad6ab3570">13766</a></span><span class="preprocessor">#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk </span><span class="comment">/* operate on second frame */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13767" name="l13767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16eb92e4f7b229407dcf6e7e836f3504">13767</a></span><span class="preprocessor">#define ETH_DMAOMR_SR_Pos (1U) </span></div>
|
||
<div class="line"><a id="l13768" name="l13768"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf08aaa0c916bb56d2e4e71fdf0f034da">13768</a></span><span class="preprocessor">#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos) </span></div>
|
||
<div class="line"><a id="l13769" name="l13769"></a><span class="lineno">13769</span><span class="preprocessor">#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk </span><span class="comment">/* Start/stop receive */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13770" name="l13770"></a><span class="lineno">13770</span> </div>
|
||
<div class="line"><a id="l13771" name="l13771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c2bf9775f1b2daae49c199875633b31">13771</a></span><span class="comment">/* Bit definition for Ethernet DMA Interrupt Enable Register */</span></div>
|
||
<div class="line"><a id="l13772" name="l13772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c8386338d800b390b1a94a7bf353b0b">13772</a></span><span class="preprocessor">#define ETH_DMAIER_NISE_Pos (16U) </span></div>
|
||
<div class="line"><a id="l13773" name="l13773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c12b833cb206d8bafa7d60faebea805">13773</a></span><span class="preprocessor">#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos) </span></div>
|
||
<div class="line"><a id="l13774" name="l13774"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea77db4415f16fb34552c4f2e4672ec2">13774</a></span><span class="preprocessor">#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk </span><span class="comment">/* Normal interrupt summary enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13775" name="l13775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabde04568b44b661a4ae2938663c0af68">13775</a></span><span class="preprocessor">#define ETH_DMAIER_AISE_Pos (15U) </span></div>
|
||
<div class="line"><a id="l13776" name="l13776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ae9340fa928abb4664efbb5c8478756">13776</a></span><span class="preprocessor">#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos) </span></div>
|
||
<div class="line"><a id="l13777" name="l13777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf996fdcd5fe7a43c250aee861d96cf8">13777</a></span><span class="preprocessor">#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk </span><span class="comment">/* Abnormal interrupt summary enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13778" name="l13778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2fbc6e64e1d5c1bf78ada2bf0bef741">13778</a></span><span class="preprocessor">#define ETH_DMAIER_ERIE_Pos (14U) </span></div>
|
||
<div class="line"><a id="l13779" name="l13779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4fe43c4432e0505a5509424665692807">13779</a></span><span class="preprocessor">#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos) </span></div>
|
||
<div class="line"><a id="l13780" name="l13780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e17cb26491d68d522f4aec00288a171">13780</a></span><span class="preprocessor">#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk </span><span class="comment">/* Early receive interrupt enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13781" name="l13781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1d818d82852308c7dc3884e4ab6bd0d">13781</a></span><span class="preprocessor">#define ETH_DMAIER_FBEIE_Pos (13U) </span></div>
|
||
<div class="line"><a id="l13782" name="l13782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92e94d1d37660b7cca9306ac020b4110">13782</a></span><span class="preprocessor">#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos) </span></div>
|
||
<div class="line"><a id="l13783" name="l13783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga369f3ea6bca9aebeceaf6b6d4d51b485">13783</a></span><span class="preprocessor">#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk </span><span class="comment">/* Fatal bus error interrupt enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13784" name="l13784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac753c8cb27122c6d9bb32ab8cfc2ae64">13784</a></span><span class="preprocessor">#define ETH_DMAIER_ETIE_Pos (10U) </span></div>
|
||
<div class="line"><a id="l13785" name="l13785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b1c57b5102ca78372420b45a707b43e">13785</a></span><span class="preprocessor">#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos) </span></div>
|
||
<div class="line"><a id="l13786" name="l13786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89d02c397b29b9a25d117baef252c11d">13786</a></span><span class="preprocessor">#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk </span><span class="comment">/* Early transmit interrupt enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13787" name="l13787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a773793e51e25028b71f7bc22127a84">13787</a></span><span class="preprocessor">#define ETH_DMAIER_RWTIE_Pos (9U) </span></div>
|
||
<div class="line"><a id="l13788" name="l13788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa28e115ada97b2e6d793f9d542f93e35">13788</a></span><span class="preprocessor">#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos) </span></div>
|
||
<div class="line"><a id="l13789" name="l13789"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83ecac2aa610bfebcf7ae2d63d8afbb2">13789</a></span><span class="preprocessor">#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk </span><span class="comment">/* Receive watchdog timeout interrupt enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13790" name="l13790"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97d3ac01bc13ea08b25b59e5e200aaf4">13790</a></span><span class="preprocessor">#define ETH_DMAIER_RPSIE_Pos (8U) </span></div>
|
||
<div class="line"><a id="l13791" name="l13791"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcfba49acf14e8a0194e1fef8b1837f7">13791</a></span><span class="preprocessor">#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos) </span></div>
|
||
<div class="line"><a id="l13792" name="l13792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac599bb486eff43714e2340c066df6d22">13792</a></span><span class="preprocessor">#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk </span><span class="comment">/* Receive process stopped interrupt enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13793" name="l13793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada6ce4050a22be8bf8ecd9f32a62cb51">13793</a></span><span class="preprocessor">#define ETH_DMAIER_RBUIE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l13794" name="l13794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c349d0b4aa329d39fcfd10d59de7b26">13794</a></span><span class="preprocessor">#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos) </span></div>
|
||
<div class="line"><a id="l13795" name="l13795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba03ad718ced9224bb8b34762994818e">13795</a></span><span class="preprocessor">#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk </span><span class="comment">/* Receive buffer unavailable interrupt enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13796" name="l13796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5bd8f0165aaa498cdafe884dd1343d9">13796</a></span><span class="preprocessor">#define ETH_DMAIER_RIE_Pos (6U) </span></div>
|
||
<div class="line"><a id="l13797" name="l13797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bce67fd8ee3363c1ab95b9f5324f745">13797</a></span><span class="preprocessor">#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos) </span></div>
|
||
<div class="line"><a id="l13798" name="l13798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe6b97c4e2981f246308d884fb2acd78">13798</a></span><span class="preprocessor">#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk </span><span class="comment">/* Receive interrupt enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13799" name="l13799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3479e12a504721ace0d9c1f2e9deae52">13799</a></span><span class="preprocessor">#define ETH_DMAIER_TUIE_Pos (5U) </span></div>
|
||
<div class="line"><a id="l13800" name="l13800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91a59aa3adff595051bdda2da948ec71">13800</a></span><span class="preprocessor">#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos) </span></div>
|
||
<div class="line"><a id="l13801" name="l13801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e9037ad879e5483c5c2bb1989a09b89">13801</a></span><span class="preprocessor">#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk </span><span class="comment">/* Transmit Underflow interrupt enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13802" name="l13802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf567f33d5a3d85984e52c65705f2c334">13802</a></span><span class="preprocessor">#define ETH_DMAIER_ROIE_Pos (4U) </span></div>
|
||
<div class="line"><a id="l13803" name="l13803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3cdf8611ab9a0a7f4fc0e0090a33ba6">13803</a></span><span class="preprocessor">#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos) </span></div>
|
||
<div class="line"><a id="l13804" name="l13804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad439769a7926aaf62c3053133fe87beb">13804</a></span><span class="preprocessor">#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk </span><span class="comment">/* Receive Overflow interrupt enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13805" name="l13805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf14e7f30233722f892e6af1d6428f7b8">13805</a></span><span class="preprocessor">#define ETH_DMAIER_TJTIE_Pos (3U) </span></div>
|
||
<div class="line"><a id="l13806" name="l13806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a9cd48115f0b32941ee3087e9c60ec9">13806</a></span><span class="preprocessor">#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos) </span></div>
|
||
<div class="line"><a id="l13807" name="l13807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga436fa7c9599495a1a1a55eb40ec00d63">13807</a></span><span class="preprocessor">#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk </span><span class="comment">/* Transmit jabber timeout interrupt enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13808" name="l13808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38bf7b752b9e72761ab2bd11400e7730">13808</a></span><span class="preprocessor">#define ETH_DMAIER_TBUIE_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13809" name="l13809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37fc5c9c473407d77a379d7032147b59">13809</a></span><span class="preprocessor">#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos) </span></div>
|
||
<div class="line"><a id="l13810" name="l13810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08ab269c60b0052ee58983d0fd7ceff0">13810</a></span><span class="preprocessor">#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk </span><span class="comment">/* Transmit buffer unavailable interrupt enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13811" name="l13811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8db6095575b73d506673d78d355fdcb">13811</a></span><span class="preprocessor">#define ETH_DMAIER_TPSIE_Pos (1U) </span></div>
|
||
<div class="line"><a id="l13812" name="l13812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d4b2c3e0d50326adf0e8b3955aa9972">13812</a></span><span class="preprocessor">#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos) </span></div>
|
||
<div class="line"><a id="l13813" name="l13813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7498e400e393f90604c092ce9bd5e74">13813</a></span><span class="preprocessor">#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk </span><span class="comment">/* Transmit process stopped interrupt enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13814" name="l13814"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a48f7292330cdb3c61e4e499357eb8b">13814</a></span><span class="preprocessor">#define ETH_DMAIER_TIE_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13815" name="l13815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a19f069ddf349de788130cefdbc4149">13815</a></span><span class="preprocessor">#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos) </span></div>
|
||
<div class="line"><a id="l13816" name="l13816"></a><span class="lineno">13816</span><span class="preprocessor">#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk </span><span class="comment">/* Transmit interrupt enable */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13817" name="l13817"></a><span class="lineno">13817</span> </div>
|
||
<div class="line"><a id="l13818" name="l13818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b868e9111c52d02c0df2319e41e40b2">13818</a></span><span class="comment">/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */</span></div>
|
||
<div class="line"><a id="l13819" name="l13819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff5db91b32eee3facb9523b1e8c7f836">13819</a></span><span class="preprocessor">#define ETH_DMAMFBOCR_OFOC_Pos (28U) </span></div>
|
||
<div class="line"><a id="l13820" name="l13820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3793f0a194ff3a19a1559824a821fe61">13820</a></span><span class="preprocessor">#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) </span></div>
|
||
<div class="line"><a id="l13821" name="l13821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf9e76a42bbf3d3b6de19402dc3c9cfa">13821</a></span><span class="preprocessor">#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk </span><span class="comment">/* Overflow bit for FIFO overflow counter */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13822" name="l13822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga265274e3d4f38a6e39a08b112fef1b63">13822</a></span><span class="preprocessor">#define ETH_DMAMFBOCR_MFA_Pos (17U) </span></div>
|
||
<div class="line"><a id="l13823" name="l13823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9595307f4b9d38f6e0991fa54c4bae8f">13823</a></span><span class="preprocessor">#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) </span></div>
|
||
<div class="line"><a id="l13824" name="l13824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d8683626bc1e997264dc41e58d7b1e9">13824</a></span><span class="preprocessor">#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk </span><span class="comment">/* Number of frames missed by the application */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13825" name="l13825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga948b0af4c7ca43ee7b22e4db7318c6fd">13825</a></span><span class="preprocessor">#define ETH_DMAMFBOCR_OMFC_Pos (16U) </span></div>
|
||
<div class="line"><a id="l13826" name="l13826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ffc962868d2b5ed265e7bffd6881aab">13826</a></span><span class="preprocessor">#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) </span></div>
|
||
<div class="line"><a id="l13827" name="l13827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9fd0920c44a894d3e2984214df300b3">13827</a></span><span class="preprocessor">#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk </span><span class="comment">/* Overflow bit for missed frame counter */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13828" name="l13828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac16af00ecd2def9c483943a7b60bb6ff">13828</a></span><span class="preprocessor">#define ETH_DMAMFBOCR_MFC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13829" name="l13829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81aa193a52d5b3757a008b84eb0c6182">13829</a></span><span class="preprocessor">#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) </span></div>
|
||
<div class="line"><a id="l13830" name="l13830"></a><span class="lineno">13830</span><span class="preprocessor">#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk </span><span class="comment">/* Number of frames missed by the controller */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13831" name="l13831"></a><span class="lineno">13831</span> </div>
|
||
<div class="line"><a id="l13832" name="l13832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac66c32e504b7893aab68fb675b30686f">13832</a></span><span class="comment">/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */</span></div>
|
||
<div class="line"><a id="l13833" name="l13833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e0d1eda1d389b3f99bbe46f26a25959">13833</a></span><span class="preprocessor">#define ETH_DMACHTDR_HTDAP_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13834" name="l13834"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae013d158ee1e13f61069722eff4d52ac">13834</a></span><span class="preprocessor">#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) </span></div>
|
||
<div class="line"><a id="l13835" name="l13835"></a><span class="lineno">13835</span><span class="preprocessor">#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk </span><span class="comment">/* Host transmit descriptor address pointer */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13836" name="l13836"></a><span class="lineno">13836</span> </div>
|
||
<div class="line"><a id="l13837" name="l13837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28f70ba69e471a3c4142c22529f41057">13837</a></span><span class="comment">/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */</span></div>
|
||
<div class="line"><a id="l13838" name="l13838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga385d61115e00ef2711fb128ba0bc58a8">13838</a></span><span class="preprocessor">#define ETH_DMACHRDR_HRDAP_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13839" name="l13839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb91f0f377b2bb0bfffe7df0ad46c7d3">13839</a></span><span class="preprocessor">#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) </span></div>
|
||
<div class="line"><a id="l13840" name="l13840"></a><span class="lineno">13840</span><span class="preprocessor">#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk </span><span class="comment">/* Host receive descriptor address pointer */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13841" name="l13841"></a><span class="lineno">13841</span> </div>
|
||
<div class="line"><a id="l13842" name="l13842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac708faf2f587cf1d4b48a9d9d864dad8">13842</a></span><span class="comment">/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */</span></div>
|
||
<div class="line"><a id="l13843" name="l13843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacc327724f91b8ddb36f526ec8d78dfa">13843</a></span><span class="preprocessor">#define ETH_DMACHTBAR_HTBAP_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13844" name="l13844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3524cdddc8525fe50c6754029011e12">13844</a></span><span class="preprocessor">#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) </span></div>
|
||
<div class="line"><a id="l13845" name="l13845"></a><span class="lineno">13845</span><span class="preprocessor">#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk </span><span class="comment">/* Host transmit buffer address pointer */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13846" name="l13846"></a><span class="lineno">13846</span> </div>
|
||
<div class="line"><a id="l13847" name="l13847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7efa5638b78f19fc5df0386817347add">13847</a></span><span class="comment">/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */</span></div>
|
||
<div class="line"><a id="l13848" name="l13848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6260b879f63938dfecd17e8d98f0a6dc">13848</a></span><span class="preprocessor">#define ETH_DMACHRBAR_HRBAP_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13849" name="l13849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cf1a9ed443f3498b67c658d26468212">13849</a></span><span class="preprocessor">#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) </span></div>
|
||
<div class="line"><a id="l13850" name="l13850"></a><span class="lineno">13850</span><span class="preprocessor">#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk </span><span class="comment">/* Host receive buffer address pointer */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l13851" name="l13851"></a><span class="lineno">13851</span> </div>
|
||
<div class="line"><a id="l13852" name="l13852"></a><span class="lineno">13852</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l13853" name="l13853"></a><span class="lineno">13853</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l13854" name="l13854"></a><span class="lineno">13854</span><span class="comment">/* USB_OTG */</span></div>
|
||
<div class="line"><a id="l13855" name="l13855"></a><span class="lineno">13855</span><span class="comment">/* */</span></div>
|
||
<div class="line"><a id="l13856" name="l13856"></a><span class="lineno">13856</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l13857" name="l13857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8ebcd754d775e8f9c405194f2b2258d">13857</a></span><span class="comment">/******************** Bit definition for USB_OTG_GOTGCTL register ***********/</span></div>
|
||
<div class="line"><a id="l13858" name="l13858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27144da12fabf5f20058022b7a060375">13858</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13859" name="l13859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae09ab672e632dfd87bfb97e10563dfac">13859</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) </span></div>
|
||
<div class="line"><a id="l13860" name="l13860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46b2b4067f78896b9de20b00d78beae7">13860</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk </span></div>
|
||
<div class="line"><a id="l13861" name="l13861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga911bbd5c9dff39b1539db5afda218133">13861</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_SRQ_Pos (1U) </span></div>
|
||
<div class="line"><a id="l13862" name="l13862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade39c1039ab30f1ca7ff7c33dd3e1c1b">13862</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) </span></div>
|
||
<div class="line"><a id="l13863" name="l13863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa11f463747ce5e1444256f11fd57e3bc">13863</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk </span></div>
|
||
<div class="line"><a id="l13864" name="l13864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1172acd99753812214a91f822770fad">13864</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) </span></div>
|
||
<div class="line"><a id="l13865" name="l13865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0325825760f66d4792be59cde2a6fb36">13865</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) </span></div>
|
||
<div class="line"><a id="l13866" name="l13866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga500945c12339a4e1350eaa5ca75c2767">13866</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk </span></div>
|
||
<div class="line"><a id="l13867" name="l13867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00ce59b4eac11aed163f9b0a40ebd830">13867</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) </span></div>
|
||
<div class="line"><a id="l13868" name="l13868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5db1466d8363575ab2cc8e61855b6d9">13868</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) </span></div>
|
||
<div class="line"><a id="l13869" name="l13869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49a2918e796f1451a374f53af914d19e">13869</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk </span></div>
|
||
<div class="line"><a id="l13870" name="l13870"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac02604ee9f359f998fac804332d8e82e">13870</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) </span></div>
|
||
<div class="line"><a id="l13871" name="l13871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62b67d7ea4c4a3d92b031b1dc4e2d014">13871</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) </span></div>
|
||
<div class="line"><a id="l13872" name="l13872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa13365d4746a4b49753d9f4852995063">13872</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk </span></div>
|
||
<div class="line"><a id="l13873" name="l13873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5c847c2f7db2b4f25a4b807847cf5fd">13873</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) </span></div>
|
||
<div class="line"><a id="l13874" name="l13874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad29b2224940ad3324855355f4fb52c51">13874</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) </span></div>
|
||
<div class="line"><a id="l13875" name="l13875"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61f4a444a7765ed3acc31d88e20a145b">13875</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk </span></div>
|
||
<div class="line"><a id="l13876" name="l13876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcbeabffac3327cd545d469b58baf2f2">13876</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) </span></div>
|
||
<div class="line"><a id="l13877" name="l13877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2ab7a1464a20fd128370a41c6b2c5db">13877</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) </span></div>
|
||
<div class="line"><a id="l13878" name="l13878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada74ca38296ae390167d8d6ef705b79c">13878</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk </span></div>
|
||
<div class="line"><a id="l13879" name="l13879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4cb7bd418b6f7625dd90c36be4a20008">13879</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_DBCT_Pos (17U) </span></div>
|
||
<div class="line"><a id="l13880" name="l13880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac28cd7384fa1d08b1aa518d5d8ed622d">13880</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) </span></div>
|
||
<div class="line"><a id="l13881" name="l13881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61b0ea0a085b2f7608a51fdb0a842b14">13881</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk </span></div>
|
||
<div class="line"><a id="l13882" name="l13882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga845bbc4c94240d4de22010b542f47ba8">13882</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) </span></div>
|
||
<div class="line"><a id="l13883" name="l13883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd37f8bf64b304c6e4d053849f56748c">13883</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) </span></div>
|
||
<div class="line"><a id="l13884" name="l13884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf05b62615285fd77bc354c072b7ba0cd">13884</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk </span></div>
|
||
<div class="line"><a id="l13885" name="l13885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4110e90ebb7c55aeb8b429fb5171e378">13885</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) </span></div>
|
||
<div class="line"><a id="l13886" name="l13886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc2ae24138663e92bdca36c8017b6c13">13886</a></span><span class="preprocessor">#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) </span></div>
|
||
<div class="line"><a id="l13887" name="l13887"></a><span class="lineno">13887</span><span class="preprocessor">#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk </span></div>
|
||
<div class="line"><a id="l13889" name="l13889"></a><span class="lineno">13889</span><span class="comment">/******************** Bit definition forUSB_OTG_HCFG register ********************/</span></div>
|
||
<div class="line"><a id="l13890" name="l13890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga473714ba284e49803fdf522f88151914">13890</a></span> </div>
|
||
<div class="line"><a id="l13891" name="l13891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad2eed76dce0ee687f52e08f16bc4c1b">13891</a></span><span class="preprocessor">#define USB_OTG_HCFG_FSLSPCS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13892" name="l13892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a881de3c707878018490b8b3db282f7">13892</a></span><span class="preprocessor">#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) </span></div>
|
||
<div class="line"><a id="l13893" name="l13893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad229aff8e0584e5b5abbf80629e141cc">13893</a></span><span class="preprocessor">#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk </span></div>
|
||
<div class="line"><a id="l13894" name="l13894"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga981001cbade2d922b72e1b06d6069da0">13894</a></span><span class="preprocessor">#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) </span></div>
|
||
<div class="line"><a id="l13895" name="l13895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab662285d2cc3bfd61c664e572fb69f5e">13895</a></span><span class="preprocessor">#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) </span></div>
|
||
<div class="line"><a id="l13896" name="l13896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebb27b8d77f15f8100c1d27149fb7186">13896</a></span><span class="preprocessor">#define USB_OTG_HCFG_FSLSS_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13897" name="l13897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98190493ea5b039322c77341e3cf61f8">13897</a></span><span class="preprocessor">#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) </span></div>
|
||
<div class="line"><a id="l13898" name="l13898"></a><span class="lineno">13898</span><span class="preprocessor">#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk </span></div>
|
||
<div class="line"><a id="l13900" name="l13900"></a><span class="lineno">13900</span><span class="comment">/******************** Bit definition for USB_OTG_DCFG register ********************/</span></div>
|
||
<div class="line"><a id="l13901" name="l13901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f814fca4fbed44bc00dc4fd248cba7f">13901</a></span> </div>
|
||
<div class="line"><a id="l13902" name="l13902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b6bf36ee06f07105efb0568bfb3c06d">13902</a></span><span class="preprocessor">#define USB_OTG_DCFG_DSPD_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13903" name="l13903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f008e2b969946597b56824fef3cc7ef">13903</a></span><span class="preprocessor">#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) </span></div>
|
||
<div class="line"><a id="l13904" name="l13904"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f73c1cb1213fd6e28ce7409fc3c63d1">13904</a></span><span class="preprocessor">#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk </span></div>
|
||
<div class="line"><a id="l13905" name="l13905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7d4f6f3e5002c73be03457ab3ac4023">13905</a></span><span class="preprocessor">#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) </span></div>
|
||
<div class="line"><a id="l13906" name="l13906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e34cb67fa67ee5ea04ca8ade51d10e5">13906</a></span><span class="preprocessor">#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) </span></div>
|
||
<div class="line"><a id="l13907" name="l13907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa785273cbe79b53e609ed2715cfbf98">13907</a></span><span class="preprocessor">#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13908" name="l13908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c492b6fc8389b58b1879aa7d822137f">13908</a></span><span class="preprocessor">#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) </span></div>
|
||
<div class="line"><a id="l13909" name="l13909"></a><span class="lineno">13909</span><span class="preprocessor">#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk </span></div>
|
||
<div class="line"><a id="l13911" name="l13911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67fabe86ac6ef650b9ad01a026b67a5d">13911</a></span><span class="preprocessor">#define USB_OTG_DCFG_DAD_Pos (4U) </span></div>
|
||
<div class="line"><a id="l13912" name="l13912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9fd5819883e2d18cad4c19af8146e1d">13912</a></span><span class="preprocessor">#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l13913" name="l13913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34aa0076cdeff59113e9880458ae79ba">13913</a></span><span class="preprocessor">#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk </span></div>
|
||
<div class="line"><a id="l13914" name="l13914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga646ba21ce25f42e2fbf706295a5ad031">13914</a></span><span class="preprocessor">#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l13915" name="l13915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d495202852341acc620ce02043281a6">13915</a></span><span class="preprocessor">#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l13916" name="l13916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fa407810d17c7f3795fe268bd01120b">13916</a></span><span class="preprocessor">#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l13917" name="l13917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72351ad7cdbbd7992f70892b49a2a669">13917</a></span><span class="preprocessor">#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l13918" name="l13918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61f0d5b909af5196782bbe6e03855f06">13918</a></span><span class="preprocessor">#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l13919" name="l13919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae949fe90d15c793eb011958a4f600ac">13919</a></span><span class="preprocessor">#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l13920" name="l13920"></a><span class="lineno">13920</span><span class="preprocessor">#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l13922" name="l13922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga273b5f0a16f8276d0f0e76f216caa03f">13922</a></span><span class="preprocessor">#define USB_OTG_DCFG_PFIVL_Pos (11U) </span></div>
|
||
<div class="line"><a id="l13923" name="l13923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08ae423d6325aa35bb037304ba8f8235">13923</a></span><span class="preprocessor">#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) </span></div>
|
||
<div class="line"><a id="l13924" name="l13924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4e78c573f8cd0548bce86ce8593353d">13924</a></span><span class="preprocessor">#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk </span></div>
|
||
<div class="line"><a id="l13925" name="l13925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9cc973db831fb86b1e122443a58aa7c">13925</a></span><span class="preprocessor">#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) </span></div>
|
||
<div class="line"><a id="l13926" name="l13926"></a><span class="lineno">13926</span><span class="preprocessor">#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) </span></div>
|
||
<div class="line"><a id="l13928" name="l13928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9a4c6ac40e44ccfe90a65c583c202b2">13928</a></span><span class="preprocessor">#define USB_OTG_DCFG_XCVRDLY_Pos (14U) </span></div>
|
||
<div class="line"><a id="l13929" name="l13929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fbc004fabda6fa9cda2977d45755e42">13929</a></span><span class="preprocessor">#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) </span></div>
|
||
<div class="line"><a id="l13930" name="l13930"></a><span class="lineno">13930</span><span class="preprocessor">#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk </span></div>
|
||
<div class="line"><a id="l13932" name="l13932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd12755447b5773fd5db5b71b5ea292a">13932</a></span><span class="preprocessor">#define USB_OTG_DCFG_ERRATIM_Pos (15U) </span></div>
|
||
<div class="line"><a id="l13933" name="l13933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36b7cce75bb4e60fe38760c78167b2ac">13933</a></span><span class="preprocessor">#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) </span></div>
|
||
<div class="line"><a id="l13934" name="l13934"></a><span class="lineno">13934</span><span class="preprocessor">#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk </span></div>
|
||
<div class="line"><a id="l13936" name="l13936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4407194cfda70b7408523c537ba03060">13936</a></span><span class="preprocessor">#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) </span></div>
|
||
<div class="line"><a id="l13937" name="l13937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fb78d02bad573871d6b9d92100561a4">13937</a></span><span class="preprocessor">#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) </span></div>
|
||
<div class="line"><a id="l13938" name="l13938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4eef8bf8e73d8b94b0caf98caa978c11">13938</a></span><span class="preprocessor">#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk </span></div>
|
||
<div class="line"><a id="l13939" name="l13939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e47455432a6c8c7c7400024427c25d8">13939</a></span><span class="preprocessor">#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) </span></div>
|
||
<div class="line"><a id="l13940" name="l13940"></a><span class="lineno">13940</span><span class="preprocessor">#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) </span></div>
|
||
<div class="line"><a id="l13942" name="l13942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b40c8b9e9f41a6d908e918591093dea">13942</a></span><span class="comment">/******************** Bit definition for USB_OTG_PCGCR register ********************/</span></div>
|
||
<div class="line"><a id="l13943" name="l13943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f118ddd4551c474f8edc23058876fdf">13943</a></span><span class="preprocessor">#define USB_OTG_PCGCR_STPPCLK_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13944" name="l13944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac696153ff9f165deadff3fe0225849e8">13944</a></span><span class="preprocessor">#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) </span></div>
|
||
<div class="line"><a id="l13945" name="l13945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf87ca67c6646747e2fbea26cda8890b5">13945</a></span><span class="preprocessor">#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk </span></div>
|
||
<div class="line"><a id="l13946" name="l13946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14c302139df9ab546ce190277ecbc090">13946</a></span><span class="preprocessor">#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) </span></div>
|
||
<div class="line"><a id="l13947" name="l13947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d6bcb65b4cb112d17466cf24c42e37f">13947</a></span><span class="preprocessor">#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) </span></div>
|
||
<div class="line"><a id="l13948" name="l13948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d0ac8d8fabee0eea8a1711ea7fafe02">13948</a></span><span class="preprocessor">#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk </span></div>
|
||
<div class="line"><a id="l13949" name="l13949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6bd9eee61333c5bd9565e74be8daacb2">13949</a></span><span class="preprocessor">#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) </span></div>
|
||
<div class="line"><a id="l13950" name="l13950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b8c8a29c623fc354c03942a6a414c06">13950</a></span><span class="preprocessor">#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) </span></div>
|
||
<div class="line"><a id="l13951" name="l13951"></a><span class="lineno">13951</span><span class="preprocessor">#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk </span></div>
|
||
<div class="line"><a id="l13953" name="l13953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7880e1cd896eb997da0931d7ec2382bd">13953</a></span><span class="comment">/******************** Bit definition for USB_OTG_GOTGINT register ********************/</span></div>
|
||
<div class="line"><a id="l13954" name="l13954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa244dfb48bb953763802745e978649b2">13954</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_SEDET_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13955" name="l13955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46e79a60810179da2479104fbf514a70">13955</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) </span></div>
|
||
<div class="line"><a id="l13956" name="l13956"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9485401fa0f22f9eece9f372d8189343">13956</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk </span></div>
|
||
<div class="line"><a id="l13957" name="l13957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga750e5c8cbb573197c89318c8b99771e0">13957</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) </span></div>
|
||
<div class="line"><a id="l13958" name="l13958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c5094462de3569f89fdcc641ead7d47">13958</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) </span></div>
|
||
<div class="line"><a id="l13959" name="l13959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga747d0bf0c6cd7caaaa24b7263689b6f7">13959</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk </span></div>
|
||
<div class="line"><a id="l13960" name="l13960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83eeecbc4aa4d8bc1c1c6cac82695577">13960</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) </span></div>
|
||
<div class="line"><a id="l13961" name="l13961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50fcdec0f5ff7e594b726dc63175a1f3">13961</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) </span></div>
|
||
<div class="line"><a id="l13962" name="l13962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad417dfa3c157c52bd339c8a832017bcd">13962</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk </span></div>
|
||
<div class="line"><a id="l13963" name="l13963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c87ba48d57c205ce011dfa8b6888a9f">13963</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_HNGDET_Pos (17U) </span></div>
|
||
<div class="line"><a id="l13964" name="l13964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab16a656720e4914c0935ef597f9719ef">13964</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) </span></div>
|
||
<div class="line"><a id="l13965" name="l13965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae10eaf27601d24b1501f70242905fee9">13965</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk </span></div>
|
||
<div class="line"><a id="l13966" name="l13966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e2f3eeb46b9addf20afbc0f4e0c3196">13966</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) </span></div>
|
||
<div class="line"><a id="l13967" name="l13967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac73e4e50f0fbe8376e87b833872f4b40">13967</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) </span></div>
|
||
<div class="line"><a id="l13968" name="l13968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d9e656b9e43f0959f16a86b21aef45e">13968</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk </span></div>
|
||
<div class="line"><a id="l13969" name="l13969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e2ad3f6e96de9fbe88f1e5f6d3be7d4">13969</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) </span></div>
|
||
<div class="line"><a id="l13970" name="l13970"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa17e41c826fded604c1837cacae0b66">13970</a></span><span class="preprocessor">#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) </span></div>
|
||
<div class="line"><a id="l13971" name="l13971"></a><span class="lineno">13971</span><span class="preprocessor">#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk </span></div>
|
||
<div class="line"><a id="l13973" name="l13973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c2fa606dfe64d8839dbfd7cb059eb1f">13973</a></span><span class="comment">/******************** Bit definition for USB_OTG_DCTL register ********************/</span></div>
|
||
<div class="line"><a id="l13974" name="l13974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6caa072b60a7c1c580d47f5ac1d4a63d">13974</a></span><span class="preprocessor">#define USB_OTG_DCTL_RWUSIG_Pos (0U) </span></div>
|
||
<div class="line"><a id="l13975" name="l13975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e87febbcda52c3b0b4679ce4fc10aae">13975</a></span><span class="preprocessor">#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) </span></div>
|
||
<div class="line"><a id="l13976" name="l13976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebac09e13aa5eb753c567253f7a7be17">13976</a></span><span class="preprocessor">#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk </span></div>
|
||
<div class="line"><a id="l13977" name="l13977"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34f43895b41cdf03141fd07278679e9c">13977</a></span><span class="preprocessor">#define USB_OTG_DCTL_SDIS_Pos (1U) </span></div>
|
||
<div class="line"><a id="l13978" name="l13978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga148c9f1be1abbca2c8568a079894c9d0">13978</a></span><span class="preprocessor">#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) </span></div>
|
||
<div class="line"><a id="l13979" name="l13979"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b3fab019e98600e57b4416eff4b0c6c">13979</a></span><span class="preprocessor">#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk </span></div>
|
||
<div class="line"><a id="l13980" name="l13980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf928315cb36f5a39a14f58cb15468ec8">13980</a></span><span class="preprocessor">#define USB_OTG_DCTL_GINSTS_Pos (2U) </span></div>
|
||
<div class="line"><a id="l13981" name="l13981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d3d6c5c6827fad61f6f8fa5553935fa">13981</a></span><span class="preprocessor">#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) </span></div>
|
||
<div class="line"><a id="l13982" name="l13982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62e7c5f4b5a7e317f9691805596a54cb">13982</a></span><span class="preprocessor">#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk </span></div>
|
||
<div class="line"><a id="l13983" name="l13983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa880c9c7c5ee16534e0156380cf04d28">13983</a></span><span class="preprocessor">#define USB_OTG_DCTL_GONSTS_Pos (3U) </span></div>
|
||
<div class="line"><a id="l13984" name="l13984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga199625403480a432df8f653b9bee0bd4">13984</a></span><span class="preprocessor">#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) </span></div>
|
||
<div class="line"><a id="l13985" name="l13985"></a><span class="lineno">13985</span><span class="preprocessor">#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk </span></div>
|
||
<div class="line"><a id="l13987" name="l13987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad771cd9b6f19e1f335016426d41dec48">13987</a></span><span class="preprocessor">#define USB_OTG_DCTL_TCTL_Pos (4U) </span></div>
|
||
<div class="line"><a id="l13988" name="l13988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebcf7c6c98c93f075f635cf0969c16f4">13988</a></span><span class="preprocessor">#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) </span></div>
|
||
<div class="line"><a id="l13989" name="l13989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48750394a0e7d020b3b1e4c4b73b981f">13989</a></span><span class="preprocessor">#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk </span></div>
|
||
<div class="line"><a id="l13990" name="l13990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27636cb092fce5a35e0dd25debc50294">13990</a></span><span class="preprocessor">#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) </span></div>
|
||
<div class="line"><a id="l13991" name="l13991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82ad49a50f4cb5a7c310e94d92daa889">13991</a></span><span class="preprocessor">#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) </span></div>
|
||
<div class="line"><a id="l13992" name="l13992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a6d0efe73a56eb7e63594717cd3784e">13992</a></span><span class="preprocessor">#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) </span></div>
|
||
<div class="line"><a id="l13993" name="l13993"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa822717fd13eed433f8496f8c0b81482">13993</a></span><span class="preprocessor">#define USB_OTG_DCTL_SGINAK_Pos (7U) </span></div>
|
||
<div class="line"><a id="l13994" name="l13994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafde278c400411575329026a0a8a67fa0">13994</a></span><span class="preprocessor">#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) </span></div>
|
||
<div class="line"><a id="l13995" name="l13995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2110acce46d292ea06baa8816332b516">13995</a></span><span class="preprocessor">#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk </span></div>
|
||
<div class="line"><a id="l13996" name="l13996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45fb8854f9cb1d9e5aa9b55e4392af8b">13996</a></span><span class="preprocessor">#define USB_OTG_DCTL_CGINAK_Pos (8U) </span></div>
|
||
<div class="line"><a id="l13997" name="l13997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga200f87e323c35612737fbaeb7b1c52f2">13997</a></span><span class="preprocessor">#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) </span></div>
|
||
<div class="line"><a id="l13998" name="l13998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7701014b6f5ba7a52bd48e8c8a1d1821">13998</a></span><span class="preprocessor">#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk </span></div>
|
||
<div class="line"><a id="l13999" name="l13999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54678325db99694db585d8ec50f46ae6">13999</a></span><span class="preprocessor">#define USB_OTG_DCTL_SGONAK_Pos (9U) </span></div>
|
||
<div class="line"><a id="l14000" name="l14000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga717ea6d52263b0b9938ebf1f3ef4b409">14000</a></span><span class="preprocessor">#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) </span></div>
|
||
<div class="line"><a id="l14001" name="l14001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57d32c2416c40902c1095f2e3e84c2c1">14001</a></span><span class="preprocessor">#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk </span></div>
|
||
<div class="line"><a id="l14002" name="l14002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07b9fd237b82bf4b3556a7a344a0058c">14002</a></span><span class="preprocessor">#define USB_OTG_DCTL_CGONAK_Pos (10U) </span></div>
|
||
<div class="line"><a id="l14003" name="l14003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga232f28bae3c9cd354b2fca1be518d043">14003</a></span><span class="preprocessor">#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) </span></div>
|
||
<div class="line"><a id="l14004" name="l14004"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga607c004ead13d867f5712fc7c46d335d">14004</a></span><span class="preprocessor">#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk </span></div>
|
||
<div class="line"><a id="l14005" name="l14005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2daaa82f3b3ea2bbfb3c0677c46b93b">14005</a></span><span class="preprocessor">#define USB_OTG_DCTL_POPRGDNE_Pos (11U) </span></div>
|
||
<div class="line"><a id="l14006" name="l14006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace837326945cc056aef6969fc24e1a09">14006</a></span><span class="preprocessor">#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) </span></div>
|
||
<div class="line"><a id="l14007" name="l14007"></a><span class="lineno">14007</span><span class="preprocessor">#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk </span></div>
|
||
<div class="line"><a id="l14009" name="l14009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97444625f6ff4b49606dc6f571bc66ff">14009</a></span><span class="comment">/******************** Bit definition for USB_OTG_HFIR register ********************/</span></div>
|
||
<div class="line"><a id="l14010" name="l14010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadcdb6f745b118b51a607d89bbf864a0">14010</a></span><span class="preprocessor">#define USB_OTG_HFIR_FRIVL_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14011" name="l14011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8345933ec4180c4ea9013291ce085a2d">14011</a></span><span class="preprocessor">#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) </span></div>
|
||
<div class="line"><a id="l14012" name="l14012"></a><span class="lineno">14012</span><span class="preprocessor">#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk </span></div>
|
||
<div class="line"><a id="l14014" name="l14014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d39ecc57d3e50e398dcca940eaf4a17">14014</a></span><span class="comment">/******************** Bit definition for USB_OTG_HFNUM register ********************/</span></div>
|
||
<div class="line"><a id="l14015" name="l14015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34a555bd57d9e8f2a41d5b9499ad7c44">14015</a></span><span class="preprocessor">#define USB_OTG_HFNUM_FRNUM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14016" name="l14016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab240bcea196fe42725639b82a3ceac75">14016</a></span><span class="preprocessor">#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14017" name="l14017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3bc7db92586a96e7a4c3cebb97644a5">14017</a></span><span class="preprocessor">#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk </span></div>
|
||
<div class="line"><a id="l14018" name="l14018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad58aef8796a09f03191b07f54244b67f">14018</a></span><span class="preprocessor">#define USB_OTG_HFNUM_FTREM_Pos (16U) </span></div>
|
||
<div class="line"><a id="l14019" name="l14019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51a24f44589040844690a0d6d2f23c13">14019</a></span><span class="preprocessor">#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) </span></div>
|
||
<div class="line"><a id="l14020" name="l14020"></a><span class="lineno">14020</span><span class="preprocessor">#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk </span></div>
|
||
<div class="line"><a id="l14022" name="l14022"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2c34163004ae2c55ba72739f5accd8d">14022</a></span><span class="comment">/******************** Bit definition for USB_OTG_DSTS register ********************/</span></div>
|
||
<div class="line"><a id="l14023" name="l14023"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga474e845231f3f8f1de1d4be1e99167ca">14023</a></span><span class="preprocessor">#define USB_OTG_DSTS_SUSPSTS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14024" name="l14024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8faf1dcd3fb686cc4acf23ca6f4b71ec">14024</a></span><span class="preprocessor">#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) </span></div>
|
||
<div class="line"><a id="l14025" name="l14025"></a><span class="lineno">14025</span><span class="preprocessor">#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk </span></div>
|
||
<div class="line"><a id="l14027" name="l14027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga270bfa6f7139f8a15af6a55c4b48c167">14027</a></span><span class="preprocessor">#define USB_OTG_DSTS_ENUMSPD_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14028" name="l14028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf68e749d3365b8b6aba2002718a16e94">14028</a></span><span class="preprocessor">#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) </span></div>
|
||
<div class="line"><a id="l14029" name="l14029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b85a30093b2120bd2f0dca9a2fabd46">14029</a></span><span class="preprocessor">#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk </span></div>
|
||
<div class="line"><a id="l14030" name="l14030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38dcfba81d842a0514d24f42fbea815c">14030</a></span><span class="preprocessor">#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) </span></div>
|
||
<div class="line"><a id="l14031" name="l14031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f6d51148141137f5b622379f7966cca">14031</a></span><span class="preprocessor">#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) </span></div>
|
||
<div class="line"><a id="l14032" name="l14032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3125d311d52b88b33109ffd3b1c2b194">14032</a></span><span class="preprocessor">#define USB_OTG_DSTS_EERR_Pos (3U) </span></div>
|
||
<div class="line"><a id="l14033" name="l14033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9787add94a212edfffa82dd2fe47863">14033</a></span><span class="preprocessor">#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) </span></div>
|
||
<div class="line"><a id="l14034" name="l14034"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27e73ebdbb3e3c257187546cda07466a">14034</a></span><span class="preprocessor">#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk </span></div>
|
||
<div class="line"><a id="l14035" name="l14035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9aa7bb17de01b147c98b6c23e4f146cd">14035</a></span><span class="preprocessor">#define USB_OTG_DSTS_FNSOF_Pos (8U) </span></div>
|
||
<div class="line"><a id="l14036" name="l14036"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga047ff56c1d9fbd02b738f2a5bf768a45">14036</a></span><span class="preprocessor">#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) </span></div>
|
||
<div class="line"><a id="l14037" name="l14037"></a><span class="lineno">14037</span><span class="preprocessor">#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk </span></div>
|
||
<div class="line"><a id="l14039" name="l14039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02c768ed073f3aaa6a43cf514e44a1d5">14039</a></span><span class="comment">/******************** Bit definition for USB_OTG_GAHBCFG register ********************/</span></div>
|
||
<div class="line"><a id="l14040" name="l14040"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfab3e804f69049a10d08b30d986ecf0">14040</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_GINT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14041" name="l14041"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd1bbe9e90d56d2aa225ff5532e15c6e">14041</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) </span></div>
|
||
<div class="line"><a id="l14042" name="l14042"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabaef2f23bb565f244cae0c2fed8655bf">14042</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk </span></div>
|
||
<div class="line"><a id="l14043" name="l14043"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f129cc1f698c1a272851d848541397c">14043</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14044" name="l14044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ffbca11bd10b4d94843a5084078fdd4">14044</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14045" name="l14045"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacccaf834ac65b3859e6f0519d2c4d75d">14045</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk </span></div>
|
||
<div class="line"><a id="l14046" name="l14046"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga944e91046cd27e0bea8954bd56a45a94">14046</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14047" name="l14047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b9994176dc5115431b0a537ad26900c">14047</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14048" name="l14048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ac6781cf82fd4c21a342b4e8c8f25f8">14048</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14049" name="l14049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae60a1aed37523932d2cbfa6e78963e28">14049</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14050" name="l14050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4dbb305ea29c5269f275bb2f727fc0a">14050</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14051" name="l14051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67d9f42ed7111f4a498e213ceae2d357">14051</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) </span></div>
|
||
<div class="line"><a id="l14052" name="l14052"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46b9ace9572bb6ec977594c8b4b0825f">14052</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) </span></div>
|
||
<div class="line"><a id="l14053" name="l14053"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59620c8a8f85f5f5986b0382152e2564">14053</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk </span></div>
|
||
<div class="line"><a id="l14054" name="l14054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbed93fcc3e44debab0f9a6b8f56a4e4">14054</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) </span></div>
|
||
<div class="line"><a id="l14055" name="l14055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a8af9d1d89b731426db773905ae4450">14055</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) </span></div>
|
||
<div class="line"><a id="l14056" name="l14056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf86fe83bcec3b4ce6a21c18bb0996af8">14056</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk </span></div>
|
||
<div class="line"><a id="l14057" name="l14057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ce05358bc5a54302af1f296bd1338c4">14057</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) </span></div>
|
||
<div class="line"><a id="l14058" name="l14058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7443f8ddb5b67b506637b282923a0c57">14058</a></span><span class="preprocessor">#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) </span></div>
|
||
<div class="line"><a id="l14059" name="l14059"></a><span class="lineno">14059</span><span class="preprocessor">#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk </span></div>
|
||
<div class="line"><a id="l14061" name="l14061"></a><span class="lineno">14061</span><span class="comment">/******************** Bit definition for USB_OTG_GUSBCFG register ********************/</span></div>
|
||
<div class="line"><a id="l14062" name="l14062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga652452baf3a68648d58eda39f8b95b17">14062</a></span> </div>
|
||
<div class="line"><a id="l14063" name="l14063"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa03324441e7f1d314a3d553097a97d98">14063</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14064" name="l14064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb035573c48f1055126d94a3c15dd5f3">14064</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) </span></div>
|
||
<div class="line"><a id="l14065" name="l14065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9afeebc0fdfffa134586228627d0994">14065</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk </span></div>
|
||
<div class="line"><a id="l14066" name="l14066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad406f5ebd83521f075d973f1afae39f8">14066</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) </span></div>
|
||
<div class="line"><a id="l14067" name="l14067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c336a75d6e5035c376667f9794d9aae">14067</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) </span></div>
|
||
<div class="line"><a id="l14068" name="l14068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55cc06db9db1914662fbcf8ad9de06b8">14068</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) </span></div>
|
||
<div class="line"><a id="l14069" name="l14069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3373712099429d9b7186af1f2bf1e662">14069</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) </span></div>
|
||
<div class="line"><a id="l14070" name="l14070"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2148059ec3e6a804d102ed9964c9a005">14070</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) </span></div>
|
||
<div class="line"><a id="l14071" name="l14071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24275f2398ac98c01acd951a7a03d3dc">14071</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk </span></div>
|
||
<div class="line"><a id="l14072" name="l14072"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffdc662f62192d4b3b04c2967dc17499">14072</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) </span></div>
|
||
<div class="line"><a id="l14073" name="l14073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26cadf8d7d278615a2681c308d69a1f4">14073</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) </span></div>
|
||
<div class="line"><a id="l14074" name="l14074"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f1e032b4bf712c5f02f8fcbf6493f9c">14074</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk </span></div>
|
||
<div class="line"><a id="l14075" name="l14075"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga014d25d1f767f3db5ad0c60e7c752607">14075</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) </span></div>
|
||
<div class="line"><a id="l14076" name="l14076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e220d23f5739e07442461204a70a2c7">14076</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) </span></div>
|
||
<div class="line"><a id="l14077" name="l14077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bb11f994508c0f3582a561c67784df2">14077</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk </span></div>
|
||
<div class="line"><a id="l14078" name="l14078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec02000199e190ce726adc091bd9fc18">14078</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TRDT_Pos (10U) </span></div>
|
||
<div class="line"><a id="l14079" name="l14079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedf4c990f79714f2747232ccb7470d4c">14079</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) </span></div>
|
||
<div class="line"><a id="l14080" name="l14080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09f21fcd7d2ba96955088e33afa034e5">14080</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk </span></div>
|
||
<div class="line"><a id="l14081" name="l14081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad316e69d3679d7fa0a73caf577e1d2b8">14081</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) </span></div>
|
||
<div class="line"><a id="l14082" name="l14082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8ecdc45ec0654c353bee6da6d17a9a6">14082</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) </span></div>
|
||
<div class="line"><a id="l14083" name="l14083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga019e347f4b9b5a2bf980b90e921c23f0">14083</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) </span></div>
|
||
<div class="line"><a id="l14084" name="l14084"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9374168e3afcc350fa7645900bec121">14084</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) </span></div>
|
||
<div class="line"><a id="l14085" name="l14085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga754ace191e8556620eec7c93ba53a914">14085</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) </span></div>
|
||
<div class="line"><a id="l14086" name="l14086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87e134cc67f7b77efcb1506f7ca57b64">14086</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) </span></div>
|
||
<div class="line"><a id="l14087" name="l14087"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cf18014a20add68d69f8cceb62e012e">14087</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk </span></div>
|
||
<div class="line"><a id="l14088" name="l14088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff2a24486b52bc1e86707e5e4f9ebbd9">14088</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) </span></div>
|
||
<div class="line"><a id="l14089" name="l14089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ad0a14d1e0b69f72209ac0de8290862">14089</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) </span></div>
|
||
<div class="line"><a id="l14090" name="l14090"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d99b3198a804e57d5b103de896cbae1">14090</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk </span></div>
|
||
<div class="line"><a id="l14091" name="l14091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2787eb50165fdc318425a15808e195d7">14091</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) </span></div>
|
||
<div class="line"><a id="l14092" name="l14092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9996da3f96fd45ce80d12a1db533b89d">14092</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) </span></div>
|
||
<div class="line"><a id="l14093" name="l14093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c0898ecb1e370e25eda1e7b4296f497">14093</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk </span></div>
|
||
<div class="line"><a id="l14094" name="l14094"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb75fefda7133445f8372502ee6dc415">14094</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) </span></div>
|
||
<div class="line"><a id="l14095" name="l14095"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7f25e19a542791bcb97956262637e9b">14095</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) </span></div>
|
||
<div class="line"><a id="l14096" name="l14096"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga971bd3927ed8382dc26b7031f44140ab">14096</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk </span></div>
|
||
<div class="line"><a id="l14097" name="l14097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51f99055d4e1309feeba94e88c767f03">14097</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) </span></div>
|
||
<div class="line"><a id="l14098" name="l14098"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafad0b734f8f4511d7839385a01f105b6">14098</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) </span></div>
|
||
<div class="line"><a id="l14099" name="l14099"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3c02da8d9118f5fb97e6ba78fd4d04f">14099</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk </span></div>
|
||
<div class="line"><a id="l14100" name="l14100"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04c1b32f50469cd6f5b5728b85af1ad0">14100</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) </span></div>
|
||
<div class="line"><a id="l14101" name="l14101"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a57c032717ceeeef110b7fd33cddd79">14101</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) </span></div>
|
||
<div class="line"><a id="l14102" name="l14102"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72a8efdaa2432c74a2e7e81a79ee96b0">14102</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk </span></div>
|
||
<div class="line"><a id="l14103" name="l14103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4f3f8f8230c13d226cfc088d2ef2f5b">14103</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) </span></div>
|
||
<div class="line"><a id="l14104" name="l14104"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe1cdbe63bf7a5b2212e602f88a16796">14104</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) </span></div>
|
||
<div class="line"><a id="l14105" name="l14105"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68a28d51da909433ba4244ba2a5e42d8">14105</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk </span></div>
|
||
<div class="line"><a id="l14106" name="l14106"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga013f30e987d548455287896e9f5600a6">14106</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_PCCI_Pos (23U) </span></div>
|
||
<div class="line"><a id="l14107" name="l14107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae325703f616d90c6c22198c288fa4f28">14107</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) </span></div>
|
||
<div class="line"><a id="l14108" name="l14108"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa08ed9b2e729e9b8ff29283ed8fadb84">14108</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk </span></div>
|
||
<div class="line"><a id="l14109" name="l14109"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab89a6d18ebdbf9a78551b167eedf7c2f">14109</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_PTCI_Pos (24U) </span></div>
|
||
<div class="line"><a id="l14110" name="l14110"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55174040ef4566af2326b0a424bff30a">14110</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) </span></div>
|
||
<div class="line"><a id="l14111" name="l14111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a20078b3fc4f5aad413fe73b96c7ed3">14111</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk </span></div>
|
||
<div class="line"><a id="l14112" name="l14112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c2349edc84b6a82c2e350ae60c3c49b">14112</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) </span></div>
|
||
<div class="line"><a id="l14113" name="l14113"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga240a106dc942384f0c0dae11a7efc018">14113</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) </span></div>
|
||
<div class="line"><a id="l14114" name="l14114"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78d129fd19d35e210ec7dcf9e50dfd07">14114</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk </span></div>
|
||
<div class="line"><a id="l14115" name="l14115"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b9aae8e1a49ed8a7d8b3d8a779581a3">14115</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) </span></div>
|
||
<div class="line"><a id="l14116" name="l14116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2bafa204b663017c8c08dcd42c1c031">14116</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) </span></div>
|
||
<div class="line"><a id="l14117" name="l14117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa1338a2855521cf8b23de215e0a24d4">14117</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk </span></div>
|
||
<div class="line"><a id="l14118" name="l14118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93cc2f6447eb4b2e36588e604b66d2b8">14118</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) </span></div>
|
||
<div class="line"><a id="l14119" name="l14119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga012379ec9a2c86e7d28f5dc882fed0c5">14119</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) </span></div>
|
||
<div class="line"><a id="l14120" name="l14120"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58fa0446165b4a2d5dbb3998ca3c8030">14120</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk </span></div>
|
||
<div class="line"><a id="l14121" name="l14121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90ac2f68e29f0584ba980f3d396eb1e2">14121</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) </span></div>
|
||
<div class="line"><a id="l14122" name="l14122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0efb62f80533abcf9cecd96815200380">14122</a></span><span class="preprocessor">#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) </span></div>
|
||
<div class="line"><a id="l14123" name="l14123"></a><span class="lineno">14123</span><span class="preprocessor">#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk </span></div>
|
||
<div class="line"><a id="l14125" name="l14125"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5123d9d21428692a45e351595b14954">14125</a></span><span class="comment">/******************** Bit definition for USB_OTG_GRSTCTL register ********************/</span></div>
|
||
<div class="line"><a id="l14126" name="l14126"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ff29d2fa7bd837e8130717b43e71a04">14126</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_CSRST_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14127" name="l14127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2e85306ee6705e7120877dee47d50b0">14127</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) </span></div>
|
||
<div class="line"><a id="l14128" name="l14128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2d70beddcb07affa73404fb00c02e9d">14128</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk </span></div>
|
||
<div class="line"><a id="l14129" name="l14129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff92f8742438f99c8e81d37c63e8fbf0">14129</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_HSRST_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14130" name="l14130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88a5f9be64498b49d12a3dc7b5bb4d0c">14130</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) </span></div>
|
||
<div class="line"><a id="l14131" name="l14131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace5718ced264cecb7108c689b6cf3d66">14131</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk </span></div>
|
||
<div class="line"><a id="l14132" name="l14132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e8b8125ce36876edcb9041304fb0d81">14132</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_FCRST_Pos (2U) </span></div>
|
||
<div class="line"><a id="l14133" name="l14133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6417d13d2568b05676800c9eda4bdfb">14133</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) </span></div>
|
||
<div class="line"><a id="l14134" name="l14134"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4801088b836b002fe4b2c7525cf8a4a">14134</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk </span></div>
|
||
<div class="line"><a id="l14135" name="l14135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e6d47098a622dd1002f38438db5db6d">14135</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) </span></div>
|
||
<div class="line"><a id="l14136" name="l14136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbe28fdd671e34e48f5d96119fd91cab">14136</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) </span></div>
|
||
<div class="line"><a id="l14137" name="l14137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a3cc0fc41e913807924741e7f197cbf">14137</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk </span></div>
|
||
<div class="line"><a id="l14138" name="l14138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a3ea77b9f0bdd2cb5e6c104d28278de">14138</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) </span></div>
|
||
<div class="line"><a id="l14139" name="l14139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac92d0ccd406f33733199edbee13eeb7b">14139</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) </span></div>
|
||
<div class="line"><a id="l14140" name="l14140"></a><span class="lineno">14140</span><span class="preprocessor">#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk </span></div>
|
||
<div class="line"><a id="l14143" name="l14143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15516a0193e467d3a42dfe24a7a20b09">14143</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) </span></div>
|
||
<div class="line"><a id="l14144" name="l14144"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d15f7c8d94dbf1b67b6d7fda680a5ad">14144</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14145" name="l14145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30d4785ae9db0a59b8e945be32582fa3">14145</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk </span></div>
|
||
<div class="line"><a id="l14146" name="l14146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga260a76595ceb569e47b30fc946ce7f84">14146</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14147" name="l14147"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82fc2f146c00833e94244fdb640fcbd4">14147</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14148" name="l14148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga625608800e950e7540f7888a281ab91e">14148</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14149" name="l14149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafacdf091f563680eafdd5500809c912f">14149</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14150" name="l14150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e0e58f272fdcbb69d964319b0cf58db">14150</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14151" name="l14151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac32cd68230279be0476ab2bafd5f8e1d">14151</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) </span></div>
|
||
<div class="line"><a id="l14152" name="l14152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf152b268977d411b34bf47e674a8239a">14152</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) </span></div>
|
||
<div class="line"><a id="l14153" name="l14153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25e845d8586bdcf102f99fde5ba85f40">14153</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk </span></div>
|
||
<div class="line"><a id="l14154" name="l14154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dd9f38aa1f6dcc20c4eeb13a6547a46">14154</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) </span></div>
|
||
<div class="line"><a id="l14155" name="l14155"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabfc525ece665c5448d652166bf962b7a">14155</a></span><span class="preprocessor">#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) </span></div>
|
||
<div class="line"><a id="l14156" name="l14156"></a><span class="lineno">14156</span><span class="preprocessor">#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk </span></div>
|
||
<div class="line"><a id="l14158" name="l14158"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77a95aac6875bc11ee78ffec7381ec24">14158</a></span><span class="comment">/******************** Bit definition for USB_OTG_DIEPMSK register ********************/</span></div>
|
||
<div class="line"><a id="l14159" name="l14159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d4f31482f2ac26051500e0c8f3a0869">14159</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14160" name="l14160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f5c0badd33dc95fa7897bd4bb558ad6">14160</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) </span></div>
|
||
<div class="line"><a id="l14161" name="l14161"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf33e7f717470ec3ffbaf5655caeb5042">14161</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk </span></div>
|
||
<div class="line"><a id="l14162" name="l14162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f93bf9a17e71b2f6d82c485ec81c464">14162</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_EPDM_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14163" name="l14163"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd42de5994316c7c765e349aceaf1718">14163</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) </span></div>
|
||
<div class="line"><a id="l14164" name="l14164"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23c48c84904e681f9f973b9e102dd45b">14164</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk </span></div>
|
||
<div class="line"><a id="l14165" name="l14165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3ef8fc38aa3179714c5ac82ac381e94">14165</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_TOM_Pos (3U) </span></div>
|
||
<div class="line"><a id="l14166" name="l14166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7329fbd5f4d78564704e80cbdcfb6a8f">14166</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) </span></div>
|
||
<div class="line"><a id="l14167" name="l14167"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b2199466036aae72f41437ca8d12305">14167</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk </span></div>
|
||
<div class="line"><a id="l14168" name="l14168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa7c9ebfa6013f1aed7b853573298a0a">14168</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) </span></div>
|
||
<div class="line"><a id="l14169" name="l14169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52a6c7819bcf9554d7f20c9ba4ad99dd">14169</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) </span></div>
|
||
<div class="line"><a id="l14170" name="l14170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e89f316e156b4d99a97be6c55c697ef">14170</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk </span></div>
|
||
<div class="line"><a id="l14171" name="l14171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9558bbbb276b63f32baf0dc2c9e37a87">14171</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) </span></div>
|
||
<div class="line"><a id="l14172" name="l14172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34f85531f0e6f963d30dbc284c23fb92">14172</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) </span></div>
|
||
<div class="line"><a id="l14173" name="l14173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62f0c997d4ec1a2a00c07963d66f4a19">14173</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk </span></div>
|
||
<div class="line"><a id="l14174" name="l14174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4413974123f59fa698d3f79b8218016">14174</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) </span></div>
|
||
<div class="line"><a id="l14175" name="l14175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26a366ee28afa322e37670c3eb5d0722">14175</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) </span></div>
|
||
<div class="line"><a id="l14176" name="l14176"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a917fb1c83934de74f903f2d5fb68ae">14176</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk </span></div>
|
||
<div class="line"><a id="l14177" name="l14177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e7e1dc554fdd79e23762aac9e2338b0">14177</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) </span></div>
|
||
<div class="line"><a id="l14178" name="l14178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d10ab688d3bf47aaf8180daf0624e9d">14178</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) </span></div>
|
||
<div class="line"><a id="l14179" name="l14179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16c9b6bfc32bc4fe2109567cc99efc3d">14179</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk </span></div>
|
||
<div class="line"><a id="l14180" name="l14180"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf510f548548201cdaef6370c77bd644">14180</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_BIM_Pos (9U) </span></div>
|
||
<div class="line"><a id="l14181" name="l14181"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2dd5dbb2c67a3dd71a8fe6563441d243">14181</a></span><span class="preprocessor">#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) </span></div>
|
||
<div class="line"><a id="l14182" name="l14182"></a><span class="lineno">14182</span><span class="preprocessor">#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk </span></div>
|
||
<div class="line"><a id="l14184" name="l14184"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a6aedb1b39e4e5adaacbc690e30515a">14184</a></span><span class="comment">/******************** Bit definition for USB_OTG_HPTXSTS register ********************/</span></div>
|
||
<div class="line"><a id="l14185" name="l14185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab49ec3e222a628b813a802f9ebb28448">14185</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14186" name="l14186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab37734d4115211633d584e59cbeabe19">14186</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) </span></div>
|
||
<div class="line"><a id="l14187" name="l14187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad838ab2d271e69a85003600c33fa636e">14187</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk </span></div>
|
||
<div class="line"><a id="l14188" name="l14188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57a34e5dc4826091ab53667fa1d0d6d7">14188</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) </span></div>
|
||
<div class="line"><a id="l14189" name="l14189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga338e5e7a3613da0d1dbca7bcdced15ca">14189</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14190" name="l14190"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0029668daec1137fa7373e7b151099ac">14190</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk </span></div>
|
||
<div class="line"><a id="l14191" name="l14191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96badb4855acc006656a4045db4170f2">14191</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14192" name="l14192"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51e29269f12dd3a01bdccd31b5fefcdf">14192</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14193" name="l14193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac36241d1f9e6a781b55952f6ae8ca4ea">14193</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14194" name="l14194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccf8f748b5a048fd46fc3c710daddf2a">14194</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14195" name="l14195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac0ab79df9fad1b945edb6384dbc8e3d">14195</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14196" name="l14196"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba458280e9d6532dd12837a90742f408">14196</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14197" name="l14197"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga873ee2b3f86e357de46cd936a899ed31">14197</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14198" name="l14198"></a><span class="lineno">14198</span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14200" name="l14200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4378a888dfbf5185446cdf184521471b">14200</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) </span></div>
|
||
<div class="line"><a id="l14201" name="l14201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c9381ee78a71b8c91e76a974fd633f1">14201</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14202" name="l14202"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc4f9d82388f22aedd70ffc2074f8526">14202</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk </span></div>
|
||
<div class="line"><a id="l14203" name="l14203"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b75ae59aa46eb3f366e0c0eb18a953e">14203</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14204" name="l14204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49c079a1cad8c676ff57e997fddcc939">14204</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14205" name="l14205"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37f71961a65f5c88a0bcfea71c88bfab">14205</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14206" name="l14206"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10291d16c7f539b1fb2d6e0b22fd7cbf">14206</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14207" name="l14207"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8bac7d58ce0353c4570601a5a8c04090">14207</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14208" name="l14208"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga164af5e3ff7a7c104028840b5ccb8447">14208</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14209" name="l14209"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad66e43fdfea8df808ae46b41537c5b0a">14209</a></span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14210" name="l14210"></a><span class="lineno">14210</span><span class="preprocessor">#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14212" name="l14212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb914e0dfd6e2f21aa41ce6e2ac289bf">14212</a></span><span class="comment">/******************** Bit definition for USB_OTG_HAINT register ********************/</span></div>
|
||
<div class="line"><a id="l14213" name="l14213"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d40f68bf4ce28cec78ad449152f16e2">14213</a></span><span class="preprocessor">#define USB_OTG_HAINT_HAINT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14214" name="l14214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13f6ce630f54df1a49314012a612d98d">14214</a></span><span class="preprocessor">#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) </span></div>
|
||
<div class="line"><a id="l14215" name="l14215"></a><span class="lineno">14215</span><span class="preprocessor">#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk </span></div>
|
||
<div class="line"><a id="l14217" name="l14217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6f7cf9e1a76b015dd90de4a3d5b3c2c">14217</a></span><span class="comment">/******************** Bit definition for USB_OTG_DOEPMSK register ********************/</span></div>
|
||
<div class="line"><a id="l14218" name="l14218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga722790431dd642e348bcded588d7e824">14218</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14219" name="l14219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e4371d47a5b0cfcc1235fbb9fbd7931">14219</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) </span></div>
|
||
<div class="line"><a id="l14220" name="l14220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b5c2c8efd16702ac54250eef9e71f5f">14220</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk </span></div>
|
||
<div class="line"><a id="l14221" name="l14221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3b3d4b03a79afdb9c3a5b9e40d07158">14221</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_EPDM_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14222" name="l14222"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6078d0855016e26c85d0a5b935e6f6ba">14222</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) </span></div>
|
||
<div class="line"><a id="l14223" name="l14223"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cee72a98e75f37cc4e9c71002ed9e74">14223</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk </span></div>
|
||
<div class="line"><a id="l14224" name="l14224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec4375fe9d10b890e84c603398653dbd">14224</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)</span></div>
|
||
<div class="line"><a id="l14225" name="l14225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc5eeb0500ce7832cf607829de07dc06">14225</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) </span></div>
|
||
<div class="line"><a id="l14226" name="l14226"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cc448d81a686805e6929bfa1b0733a0">14226</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk </span></div>
|
||
<div class="line"><a id="l14227" name="l14227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafccb9d1a7a0af8c8ed2be97eff94a8d1">14227</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_STUPM_Pos (3U) </span></div>
|
||
<div class="line"><a id="l14228" name="l14228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb61e805f1e512b80a7b33efcca6182e">14228</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) </span></div>
|
||
<div class="line"><a id="l14229" name="l14229"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71b98d5a957803fef609dcc8ce29e5e7">14229</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk </span></div>
|
||
<div class="line"><a id="l14230" name="l14230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7df1cf9a2583c2a2c079c2743db0c0a">14230</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) </span></div>
|
||
<div class="line"><a id="l14231" name="l14231"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad472667f09c79f0ca122586ae032e9df">14231</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) </span></div>
|
||
<div class="line"><a id="l14232" name="l14232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae44f78310897990a88aaef41fb7e0ec3">14232</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk </span></div>
|
||
<div class="line"><a id="l14233" name="l14233"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2715f06a8df58db51a00016f761d6b0">14233</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) </span></div>
|
||
<div class="line"><a id="l14234" name="l14234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22b959b8d57d5bace18e35d95de09a77">14234</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) </span></div>
|
||
<div class="line"><a id="l14235" name="l14235"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab4e6b15ce4e8b36a49a8e46d6354ab2">14235</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk </span></div>
|
||
<div class="line"><a id="l14236" name="l14236"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga990e43476d2858b9b8b0a1e10ddd3ca1">14236</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) </span></div>
|
||
<div class="line"><a id="l14237" name="l14237"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59ef878371c32d6157a619ec42144c09">14237</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) </span></div>
|
||
<div class="line"><a id="l14238" name="l14238"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5e214436522dcf78ba7057e0cd9e463">14238</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk </span></div>
|
||
<div class="line"><a id="l14239" name="l14239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf413b92fd7377313378c481fbf28c6f0">14239</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_OPEM_Pos (8U) </span></div>
|
||
<div class="line"><a id="l14240" name="l14240"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26bf486957377a746a55ae6203ea697c">14240</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) </span></div>
|
||
<div class="line"><a id="l14241" name="l14241"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf13c76bdd8af0056459a0ec9e8b38a50">14241</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk </span></div>
|
||
<div class="line"><a id="l14242" name="l14242"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa93f1e928648830df23013e8868ed53a">14242</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_BOIM_Pos (9U) </span></div>
|
||
<div class="line"><a id="l14243" name="l14243"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga980f37cfb000d12f7752530986d5069c">14243</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) </span></div>
|
||
<div class="line"><a id="l14244" name="l14244"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f60404d296c1b736ed763904914bbc4">14244</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk </span></div>
|
||
<div class="line"><a id="l14245" name="l14245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad22af854eb20c0c8f6c718703aa06cc">14245</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_BERRM_Pos (12U)</span></div>
|
||
<div class="line"><a id="l14246" name="l14246"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaac35f8747cd753d8534cfd8d6f4e6f2">14246</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) </span></div>
|
||
<div class="line"><a id="l14247" name="l14247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga849d7e79fa347faa484a293e99337c37">14247</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk </span></div>
|
||
<div class="line"><a id="l14248" name="l14248"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4282f15a3f24294c3de271447aa0b53a">14248</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_NAKM_Pos (13U)</span></div>
|
||
<div class="line"><a id="l14249" name="l14249"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga377812e187288777184fec2d96929ac3">14249</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) </span></div>
|
||
<div class="line"><a id="l14250" name="l14250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60d3e6971b726ef17a4f7518838813b5">14250</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk </span></div>
|
||
<div class="line"><a id="l14251" name="l14251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7d2f79cc4d6c27cc7d24cc63b2103d0">14251</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_NYETM_Pos (14U)</span></div>
|
||
<div class="line"><a id="l14252" name="l14252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a60db81ca4a7ab4ce864d70c5235498">14252</a></span><span class="preprocessor">#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) </span></div>
|
||
<div class="line"><a id="l14253" name="l14253"></a><span class="lineno">14253</span><span class="preprocessor">#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk </span></div>
|
||
<div class="line"><a id="l14254" name="l14254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd85c4ebf2f92718d17fe2d03542046a">14254</a></span><span class="comment">/******************** Bit definition for USB_OTG_GINTSTS register ********************/</span></div>
|
||
<div class="line"><a id="l14255" name="l14255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac38b6e32c779099c6cdba55e857f33e0">14255</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_CMOD_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14256" name="l14256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga357496f2734867ddaf5a00cc61ff0191">14256</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) </span></div>
|
||
<div class="line"><a id="l14257" name="l14257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabeb493e86d2c0348c72313101d37d35">14257</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk </span></div>
|
||
<div class="line"><a id="l14258" name="l14258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6421c9e8b57f5343e197c85008ae82d5">14258</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_MMIS_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14259" name="l14259"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0c1ac0fa6a6a1b95d1dfc2b90383a39">14259</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) </span></div>
|
||
<div class="line"><a id="l14260" name="l14260"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea398db5607b71a1f2502cf2070114b3">14260</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk </span></div>
|
||
<div class="line"><a id="l14261" name="l14261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7154d80c30c1c71720c35ce47aed996b">14261</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_OTGINT_Pos (2U) </span></div>
|
||
<div class="line"><a id="l14262" name="l14262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a7ff1e46bfa5481522003726a1b6304">14262</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) </span></div>
|
||
<div class="line"><a id="l14263" name="l14263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga241c59b3b0a4716cdfeae02bee7ee6f7">14263</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk </span></div>
|
||
<div class="line"><a id="l14264" name="l14264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga574b32ff2365c138b8454bec261a44e5">14264</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_SOF_Pos (3U) </span></div>
|
||
<div class="line"><a id="l14265" name="l14265"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga478373e0aea76bfad1c9d8e93c33a2f8">14265</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) </span></div>
|
||
<div class="line"><a id="l14266" name="l14266"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b883fbb67ff958f65920e91e1bef891">14266</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk </span></div>
|
||
<div class="line"><a id="l14267" name="l14267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fb089db587ace41b14385dda34247e5">14267</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) </span></div>
|
||
<div class="line"><a id="l14268" name="l14268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd7c264becfe7a116ae20933173b1e5b">14268</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) </span></div>
|
||
<div class="line"><a id="l14269" name="l14269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga445da8fb063099b3ad27f761ccbb5717">14269</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk </span></div>
|
||
<div class="line"><a id="l14270" name="l14270"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga750ef2111fed4186378990d5b4604911">14270</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) </span></div>
|
||
<div class="line"><a id="l14271" name="l14271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa84f417f4c311418505bcd04e6b9cbdf">14271</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) </span></div>
|
||
<div class="line"><a id="l14272" name="l14272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99b72bc7ac0386f0db4fe4525c29e29a">14272</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk </span></div>
|
||
<div class="line"><a id="l14273" name="l14273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac8bce3f4c26db797f4d5bc1fbbf56a3">14273</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) </span></div>
|
||
<div class="line"><a id="l14274" name="l14274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcf16d8b480c90018eaf6a717c989100">14274</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) </span></div>
|
||
<div class="line"><a id="l14275" name="l14275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga317bd1c94486fbce8c5fad17a0c1a888">14275</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk </span></div>
|
||
<div class="line"><a id="l14276" name="l14276"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2197d4cc945121d9c75d7d9701e64c5">14276</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) </span></div>
|
||
<div class="line"><a id="l14277" name="l14277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2966f09bafa5de7b1ee2bbddfc2628fc">14277</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) </span></div>
|
||
<div class="line"><a id="l14278" name="l14278"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cad1cf9f3eb790549029467955ec3ca">14278</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk </span></div>
|
||
<div class="line"><a id="l14279" name="l14279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d506f6959a079205ed975944e8e1189">14279</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_ESUSP_Pos (10U) </span></div>
|
||
<div class="line"><a id="l14280" name="l14280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99d72bb12c0c5bf1d17290c49b392027">14280</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) </span></div>
|
||
<div class="line"><a id="l14281" name="l14281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae44254e287488e465ba70a9a19d1b95a">14281</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk </span></div>
|
||
<div class="line"><a id="l14282" name="l14282"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e012bb063b871af8f27698f652d757d">14282</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) </span></div>
|
||
<div class="line"><a id="l14283" name="l14283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd16c90192e1c43d95c16265f86cdd5d">14283</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) </span></div>
|
||
<div class="line"><a id="l14284" name="l14284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf52cb564c30e26f503da97e15c1404cd">14284</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk </span></div>
|
||
<div class="line"><a id="l14285" name="l14285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cc0c061635f5ac73557643af51a1441">14285</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_USBRST_Pos (12U) </span></div>
|
||
<div class="line"><a id="l14286" name="l14286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga446f240725aaa8a702b70763cef41661">14286</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) </span></div>
|
||
<div class="line"><a id="l14287" name="l14287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fd05b6cfa6b54ec8258ccd9c4957859">14287</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk </span></div>
|
||
<div class="line"><a id="l14288" name="l14288"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4300a8cbfa6b81490d1747b67966f63b">14288</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) </span></div>
|
||
<div class="line"><a id="l14289" name="l14289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88d4e3bdfdfc08a0cc2db20a34cbd598">14289</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) </span></div>
|
||
<div class="line"><a id="l14290" name="l14290"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23417bce86919951f9fa8b03d99d9017">14290</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk </span></div>
|
||
<div class="line"><a id="l14291" name="l14291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ca4fde1933a925bf08275f0dc66fab3">14291</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) </span></div>
|
||
<div class="line"><a id="l14292" name="l14292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad550fd1c59868de214b47c06ef72af16">14292</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) </span></div>
|
||
<div class="line"><a id="l14293" name="l14293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3812f09bf415a4f1ee087e527f2f8ff2">14293</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk </span></div>
|
||
<div class="line"><a id="l14294" name="l14294"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1c09e625f1d9bc1b803c5930d0e0298">14294</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_EOPF_Pos (15U) </span></div>
|
||
<div class="line"><a id="l14295" name="l14295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e72bb03e22a40500af8f0cf4a34d4a8">14295</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) </span></div>
|
||
<div class="line"><a id="l14296" name="l14296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac190f90afc7a7800ce530536635c84db">14296</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk </span></div>
|
||
<div class="line"><a id="l14297" name="l14297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa17b5ac65578ca653e41479144a6f1fc">14297</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_IEPINT_Pos (18U) </span></div>
|
||
<div class="line"><a id="l14298" name="l14298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba3464cca97f65b232975c7ede5f3928">14298</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) </span></div>
|
||
<div class="line"><a id="l14299" name="l14299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8df58b4dcba0c0e787cd6b5943342c52">14299</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk </span></div>
|
||
<div class="line"><a id="l14300" name="l14300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga005e49f60424a85b2abd5315691093dd">14300</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_OEPINT_Pos (19U) </span></div>
|
||
<div class="line"><a id="l14301" name="l14301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7191a4ff25e5834f2ebdf0b61103294b">14301</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) </span></div>
|
||
<div class="line"><a id="l14302" name="l14302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac5e42d68b484721ee831b67ded60c83">14302</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk </span></div>
|
||
<div class="line"><a id="l14303" name="l14303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf380deb48e6ff5e99ab18c74684dd51e">14303</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) </span></div>
|
||
<div class="line"><a id="l14304" name="l14304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64d9ad7356460a81cfb01e4a39d9fe14">14304</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) </span></div>
|
||
<div class="line"><a id="l14305" name="l14305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58cee872eb24af9fbf28c6e5d736f6ea">14305</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk </span></div>
|
||
<div class="line"><a id="l14306" name="l14306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga038bf029239a7327a134697d89adf4d2">14306</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) </span></div>
|
||
<div class="line"><a id="l14307" name="l14307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga590d7ef0d41e8499b968429da4bbe289">14307</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) </span></div>
|
||
<div class="line"><a id="l14308" name="l14308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf89d028cf11771da190cb02568a7c711">14308</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk </span></div>
|
||
<div class="line"><a id="l14309" name="l14309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7b0f4c8c2bbc97f303685f3d236bb0b">14309</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) </span></div>
|
||
<div class="line"><a id="l14310" name="l14310"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e3ca6a1a8087c2c60a6980fa365776d">14310</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) </span></div>
|
||
<div class="line"><a id="l14311" name="l14311"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae42486a050eb3f8d9b546a06c955f831">14311</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk </span></div>
|
||
<div class="line"><a id="l14312" name="l14312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d8553b58efc1196c9390088c8c28cac">14312</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) </span></div>
|
||
<div class="line"><a id="l14313" name="l14313"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaea3470d78914a470f9aba4367f7609d">14313</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) </span></div>
|
||
<div class="line"><a id="l14314" name="l14314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ee336f2248571aab4d92adab169cff9">14314</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk </span></div>
|
||
<div class="line"><a id="l14315" name="l14315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga367de65d703dfe6cb6db52c76f996f85">14315</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_HCINT_Pos (25U) </span></div>
|
||
<div class="line"><a id="l14316" name="l14316"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedc1e52a9576a68e762d473c74225d2a">14316</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) </span></div>
|
||
<div class="line"><a id="l14317" name="l14317"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f8c0100f49bf442ec3aedc4b4d24d1c">14317</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk </span></div>
|
||
<div class="line"><a id="l14318" name="l14318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16028501b6619df3019f71876b649884">14318</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_PTXFE_Pos (26U) </span></div>
|
||
<div class="line"><a id="l14319" name="l14319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ce397157106fc508c7f067d8efb7396">14319</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) </span></div>
|
||
<div class="line"><a id="l14320" name="l14320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2695d008efbfc9c58c739542f8b5a3da">14320</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk </span></div>
|
||
<div class="line"><a id="l14321" name="l14321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99288d13e884a0c4c554d3219bf56f51">14321</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) </span></div>
|
||
<div class="line"><a id="l14322" name="l14322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga931ec3cde136bc655953191000a16855">14322</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) </span></div>
|
||
<div class="line"><a id="l14323" name="l14323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f782ddcb6d950f66177624dd4945906">14323</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk </span></div>
|
||
<div class="line"><a id="l14324" name="l14324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9bf091e3d68accaeb0237700d77c9fc3">14324</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_DISCINT_Pos (29U) </span></div>
|
||
<div class="line"><a id="l14325" name="l14325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7ef887fec0170857c82ad7a142cce98">14325</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) </span></div>
|
||
<div class="line"><a id="l14326" name="l14326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f3e7b8b9ed0fbb3398b29a092e775bb">14326</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk </span></div>
|
||
<div class="line"><a id="l14327" name="l14327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37cf1033876ca51d197c2652b87bd084">14327</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_SRQINT_Pos (30U) </span></div>
|
||
<div class="line"><a id="l14328" name="l14328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6f152a76e8a4457cf7f2cd93a95d3fd">14328</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) </span></div>
|
||
<div class="line"><a id="l14329" name="l14329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3a4034786904e2e3e8d6125d0e8c43d">14329</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk </span></div>
|
||
<div class="line"><a id="l14330" name="l14330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0607db8d81e1637d4f91fbddb26bc25">14330</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_WKUINT_Pos (31U) </span></div>
|
||
<div class="line"><a id="l14331" name="l14331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60bc942876444a039c20070d3a91055e">14331</a></span><span class="preprocessor">#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) </span></div>
|
||
<div class="line"><a id="l14332" name="l14332"></a><span class="lineno">14332</span><span class="preprocessor">#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk </span></div>
|
||
<div class="line"><a id="l14334" name="l14334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c01134b517eb3df18e9f5ef8468aa00">14334</a></span><span class="comment">/******************** Bit definition for USB_OTG_GINTMSK register ********************/</span></div>
|
||
<div class="line"><a id="l14335" name="l14335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5ccb0f8c7955022c74175b060f1a5e4">14335</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_MMISM_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14336" name="l14336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49ccdddf721bcdb2d44915f210b3e2e2">14336</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) </span></div>
|
||
<div class="line"><a id="l14337" name="l14337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6855459d5f63d37ac78e68e3b4e1c6c">14337</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk </span></div>
|
||
<div class="line"><a id="l14338" name="l14338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaff43c3b891b1e76c1e0242a2bab658c">14338</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_OTGINT_Pos (2U) </span></div>
|
||
<div class="line"><a id="l14339" name="l14339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1138fd4386ac29900b5c46ec7754b4ff">14339</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) </span></div>
|
||
<div class="line"><a id="l14340" name="l14340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d66ca67546aa82347d6c35b525d514e">14340</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk </span></div>
|
||
<div class="line"><a id="l14341" name="l14341"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03618e5abf25fbd2f495b47e6121402a">14341</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_SOFM_Pos (3U) </span></div>
|
||
<div class="line"><a id="l14342" name="l14342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbd83cf86e077c35fdc47e2a2666b391">14342</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) </span></div>
|
||
<div class="line"><a id="l14343" name="l14343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18b2b2a3983a115a57c5a8187568b1f5">14343</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk </span></div>
|
||
<div class="line"><a id="l14344" name="l14344"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e0f9299eaf0a9987bb07d6d4ba05228">14344</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) </span></div>
|
||
<div class="line"><a id="l14345" name="l14345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacca853066f092884b6c6af005eee77ed">14345</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) </span></div>
|
||
<div class="line"><a id="l14346" name="l14346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga980f36264fcd2e20e5d0f53fbde196f1">14346</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk </span></div>
|
||
<div class="line"><a id="l14347" name="l14347"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67278c309dddbbaa4cc520416c60d9be">14347</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) </span></div>
|
||
<div class="line"><a id="l14348" name="l14348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40b7860f3dc90a9f46e46e2dc133f2e4">14348</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) </span></div>
|
||
<div class="line"><a id="l14349" name="l14349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bc09652469952607ef86af53e1faa20">14349</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk </span></div>
|
||
<div class="line"><a id="l14350" name="l14350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53aed86becf8549f65f3038d0d5da115">14350</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) </span></div>
|
||
<div class="line"><a id="l14351" name="l14351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3eb2bbcd11ddee87630472eb01897d3d">14351</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) </span></div>
|
||
<div class="line"><a id="l14352" name="l14352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cd00e95e293a7cf81e2912b02a7cf58">14352</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk </span></div>
|
||
<div class="line"><a id="l14353" name="l14353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga360c770dba2809d002ba1cf317179988">14353</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) </span></div>
|
||
<div class="line"><a id="l14354" name="l14354"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba9de7677f70e7fcb4dab90228bdb484">14354</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) </span></div>
|
||
<div class="line"><a id="l14355" name="l14355"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7751043116b431d9ad344b0a58d57a9b">14355</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk </span></div>
|
||
<div class="line"><a id="l14356" name="l14356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabed33a7a408afafbce8c6243e2345433">14356</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) </span></div>
|
||
<div class="line"><a id="l14357" name="l14357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa0fc70a7e7198d7d6f179d9cae29394">14357</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) </span></div>
|
||
<div class="line"><a id="l14358" name="l14358"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7dc3bfe1c4f58eee80c49b1382df3a9">14358</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk </span></div>
|
||
<div class="line"><a id="l14359" name="l14359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44cee5301fb072bbea3e3b095d12e08d">14359</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) </span></div>
|
||
<div class="line"><a id="l14360" name="l14360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7afb2b0396964430aeb1c7650012fe6">14360</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) </span></div>
|
||
<div class="line"><a id="l14361" name="l14361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e9ba2c03e49bbe6da21b73e57e73c26">14361</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk </span></div>
|
||
<div class="line"><a id="l14362" name="l14362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9356341b405c61209433fd206e5edc4">14362</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_USBRST_Pos (12U) </span></div>
|
||
<div class="line"><a id="l14363" name="l14363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0935f9f5fb77fee0755ceaaa787bb7f6">14363</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) </span></div>
|
||
<div class="line"><a id="l14364" name="l14364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7bafbc1ce354519f9b0d53d8d8f4187f">14364</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk </span></div>
|
||
<div class="line"><a id="l14365" name="l14365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc647118b4e7ef089e014a6da2e42f9e">14365</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) </span></div>
|
||
<div class="line"><a id="l14366" name="l14366"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6066078d17a4216093855cc210ab6764">14366</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) </span></div>
|
||
<div class="line"><a id="l14367" name="l14367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga594d179afd1c73ca5c341fe09a67cbe7">14367</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk </span></div>
|
||
<div class="line"><a id="l14368" name="l14368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga442bbb88091efa2c2f707909e51477f3">14368</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) </span></div>
|
||
<div class="line"><a id="l14369" name="l14369"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e01710480bf4d5edf5c344798c88624">14369</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) </span></div>
|
||
<div class="line"><a id="l14370" name="l14370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9dc782a42d4b724d28494d0030b9a71">14370</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk </span></div>
|
||
<div class="line"><a id="l14371" name="l14371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53404953b235600349f7f631caff940b">14371</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_EOPFM_Pos (15U) </span></div>
|
||
<div class="line"><a id="l14372" name="l14372"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd06eee1627ac5ba7212a728f19e4fe8">14372</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) </span></div>
|
||
<div class="line"><a id="l14373" name="l14373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2c92fa81e0b29cbf873ac24bdcbc1ac">14373</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk </span></div>
|
||
<div class="line"><a id="l14374" name="l14374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf538166d934b884ae39bdfe98cbd16b6">14374</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_EPMISM_Pos (17U) </span></div>
|
||
<div class="line"><a id="l14375" name="l14375"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35ecb8ef940b0ace19712f5fefa1193c">14375</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) </span></div>
|
||
<div class="line"><a id="l14376" name="l14376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cf4b99bff0d732dfc46a83947266fce">14376</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk </span></div>
|
||
<div class="line"><a id="l14377" name="l14377"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae283ace2a396c147245a581322b25761">14377</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_IEPINT_Pos (18U) </span></div>
|
||
<div class="line"><a id="l14378" name="l14378"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7b0d0879e3d57e3a21610ab590da6ae">14378</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) </span></div>
|
||
<div class="line"><a id="l14379" name="l14379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e646bf0709fd1662301a3e81e167e8f">14379</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk </span></div>
|
||
<div class="line"><a id="l14380" name="l14380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcdffda36a1a980f7d77038e2e5acb29">14380</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_OEPINT_Pos (19U) </span></div>
|
||
<div class="line"><a id="l14381" name="l14381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff1341cabf6155e197f657b12237dbb8">14381</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) </span></div>
|
||
<div class="line"><a id="l14382" name="l14382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f677a85809f7741c7bce7d6486f4f0b">14382</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk </span></div>
|
||
<div class="line"><a id="l14383" name="l14383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga932753540aef5f14f8801ea26789cef4">14383</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) </span></div>
|
||
<div class="line"><a id="l14384" name="l14384"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a505c6af38c507dfe84028d6194e08e">14384</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) </span></div>
|
||
<div class="line"><a id="l14385" name="l14385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6a04d965084d298bd9902072771750f">14385</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk </span></div>
|
||
<div class="line"><a id="l14386" name="l14386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7fc2d5326991ca1857dcc4825688d21">14386</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) </span></div>
|
||
<div class="line"><a id="l14387" name="l14387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fb0cdc2b7f0d8de8bbd8beaf3d69ae1">14387</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) </span></div>
|
||
<div class="line"><a id="l14388" name="l14388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fc5d32a7e8a6828c986edb99360bb61">14388</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk </span></div>
|
||
<div class="line"><a id="l14389" name="l14389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga941f4e537d06501247b906cbd37410c7">14389</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) </span></div>
|
||
<div class="line"><a id="l14390" name="l14390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae29d6ecd5e6c802a6214b814f6466b58">14390</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) </span></div>
|
||
<div class="line"><a id="l14391" name="l14391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2401d68c3c2a2d7229572c214377615">14391</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk </span></div>
|
||
<div class="line"><a id="l14392" name="l14392"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2f3349ecf1e586219b22452f93d3725">14392</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_PRTIM_Pos (24U) </span></div>
|
||
<div class="line"><a id="l14393" name="l14393"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8b1d4a903966e3ad62a8c299875a082">14393</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) </span></div>
|
||
<div class="line"><a id="l14394" name="l14394"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad83cad33689d2b786e2ea01faece0f6a">14394</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk </span></div>
|
||
<div class="line"><a id="l14395" name="l14395"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91482bd34447d0e44c2bf4ad9b9e3aa0">14395</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_HCIM_Pos (25U) </span></div>
|
||
<div class="line"><a id="l14396" name="l14396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ff8e84db67f2f7c46998c2236f9c6cc">14396</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) </span></div>
|
||
<div class="line"><a id="l14397" name="l14397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe3c9998d70dd959dfa2afa021984bf6">14397</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk </span></div>
|
||
<div class="line"><a id="l14398" name="l14398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7146797fddc3a6bae1b081568810f35e">14398</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) </span></div>
|
||
<div class="line"><a id="l14399" name="l14399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2744ae4d8e4c018a9a541af8ce68d01d">14399</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) </span></div>
|
||
<div class="line"><a id="l14400" name="l14400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17256c345931101867a6244fffd296e5">14400</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk </span></div>
|
||
<div class="line"><a id="l14401" name="l14401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae4b71ca238b78977cad1c0362044065">14401</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) </span></div>
|
||
<div class="line"><a id="l14402" name="l14402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe390b69b7379dc93f9c25b6b35a71f2">14402</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) </span></div>
|
||
<div class="line"><a id="l14403" name="l14403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9413f2f7748902aa9b9e6997fdb2e59c">14403</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk </span></div>
|
||
<div class="line"><a id="l14404" name="l14404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34f387040509ac1ea94b3dbc95302e54">14404</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_DISCINT_Pos (29U) </span></div>
|
||
<div class="line"><a id="l14405" name="l14405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6de24048cab1948503c26d09ee5a4397">14405</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) </span></div>
|
||
<div class="line"><a id="l14406" name="l14406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b7fa3ef7a96e9fc563a90bdd46348e9">14406</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk </span></div>
|
||
<div class="line"><a id="l14407" name="l14407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga075abd906877496518197feccbd33643">14407</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_SRQIM_Pos (30U) </span></div>
|
||
<div class="line"><a id="l14408" name="l14408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga896592b90dc012f3c4d004cd2280fb8f">14408</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) </span></div>
|
||
<div class="line"><a id="l14409" name="l14409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5cfe069353fb275d12afa3e0a55e7e11">14409</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk </span></div>
|
||
<div class="line"><a id="l14410" name="l14410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf042e8854e22eacdba2faa356fe1b58">14410</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_WUIM_Pos (31U) </span></div>
|
||
<div class="line"><a id="l14411" name="l14411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab641d285c79ab1b54c1d0c615afe87f5">14411</a></span><span class="preprocessor">#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) </span></div>
|
||
<div class="line"><a id="l14412" name="l14412"></a><span class="lineno">14412</span><span class="preprocessor">#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk </span></div>
|
||
<div class="line"><a id="l14414" name="l14414"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae63137414d813c9639e678ce3f59d214">14414</a></span><span class="comment">/******************** Bit definition for USB_OTG_DAINT register ********************/</span></div>
|
||
<div class="line"><a id="l14415" name="l14415"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0458c7203562b2f88f6301ee5914b5be">14415</a></span><span class="preprocessor">#define USB_OTG_DAINT_IEPINT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14416" name="l14416"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac640d7686606412f8b3593fc3bc76976">14416</a></span><span class="preprocessor">#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) </span></div>
|
||
<div class="line"><a id="l14417" name="l14417"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25afe9767c710d1e25db2f40719e2d1e">14417</a></span><span class="preprocessor">#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk </span></div>
|
||
<div class="line"><a id="l14418" name="l14418"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae1224c9e9728d40025d9326e31a0c6b">14418</a></span><span class="preprocessor">#define USB_OTG_DAINT_OEPINT_Pos (16U) </span></div>
|
||
<div class="line"><a id="l14419" name="l14419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1da6e6b0cb689727710c7c23162fb5d">14419</a></span><span class="preprocessor">#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) </span></div>
|
||
<div class="line"><a id="l14420" name="l14420"></a><span class="lineno">14420</span><span class="preprocessor">#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk </span></div>
|
||
<div class="line"><a id="l14422" name="l14422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa567788f5117a97c9ac2f72065e49365">14422</a></span><span class="comment">/******************** Bit definition for USB_OTG_HAINTMSK register ********************/</span></div>
|
||
<div class="line"><a id="l14423" name="l14423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga326da6d7c5280028f57cf69bc5958b4a">14423</a></span><span class="preprocessor">#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14424" name="l14424"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1f2419baf94819340bd759b09004121">14424</a></span><span class="preprocessor">#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) </span></div>
|
||
<div class="line"><a id="l14425" name="l14425"></a><span class="lineno">14425</span><span class="preprocessor">#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk </span></div>
|
||
<div class="line"><a id="l14427" name="l14427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c7c5fd797eed7457c60a0edfa2578e5">14427</a></span><span class="comment">/******************** Bit definition for USB_OTG_GRXSTSP register ********************/</span></div>
|
||
<div class="line"><a id="l14428" name="l14428"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34de745d37102b0c8d8bc0daac0437a4">14428</a></span><span class="preprocessor">#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14429" name="l14429"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09b6ae9c0db0348ae11d171912651bf2">14429</a></span><span class="preprocessor">#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14430" name="l14430"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac000307f9a9c2cd3f342ea9bb1d5c53f">14430</a></span><span class="preprocessor">#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk </span></div>
|
||
<div class="line"><a id="l14431" name="l14431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffd3da88ae4fb7c15b79e072e2230441">14431</a></span><span class="preprocessor">#define USB_OTG_GRXSTSP_BCNT_Pos (4U) </span></div>
|
||
<div class="line"><a id="l14432" name="l14432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7cc28354cac4479286e02df84b82eaa">14432</a></span><span class="preprocessor">#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) </span></div>
|
||
<div class="line"><a id="l14433" name="l14433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13cf2cc9c798b4048a80c993020c4306">14433</a></span><span class="preprocessor">#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk </span></div>
|
||
<div class="line"><a id="l14434" name="l14434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76f9198db9bcb93fc1823fe6278c06ad">14434</a></span><span class="preprocessor">#define USB_OTG_GRXSTSP_DPID_Pos (15U) </span></div>
|
||
<div class="line"><a id="l14435" name="l14435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89a85cea9c8ee8cea016f80c1354b0e2">14435</a></span><span class="preprocessor">#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) </span></div>
|
||
<div class="line"><a id="l14436" name="l14436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27644858023a064bac6755fcdff30ab9">14436</a></span><span class="preprocessor">#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk </span></div>
|
||
<div class="line"><a id="l14437" name="l14437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02d6c9af341038ba6622a9ac14e0aeda">14437</a></span><span class="preprocessor">#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) </span></div>
|
||
<div class="line"><a id="l14438" name="l14438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga968cdd119ee75647a2ab2a6beecd54fc">14438</a></span><span class="preprocessor">#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) </span></div>
|
||
<div class="line"><a id="l14439" name="l14439"></a><span class="lineno">14439</span><span class="preprocessor">#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk </span></div>
|
||
<div class="line"><a id="l14441" name="l14441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c30ee057efc639e21534e6d8cff9a1f">14441</a></span><span class="comment">/******************** Bit definition for USB_OTG_DAINTMSK register ********************/</span></div>
|
||
<div class="line"><a id="l14442" name="l14442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafff61f58b2d93be3d36f44794981e80c">14442</a></span><span class="preprocessor">#define USB_OTG_DAINTMSK_IEPM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14443" name="l14443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9eaacec55a1e6d5ea06babfacf6a77c">14443</a></span><span class="preprocessor">#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) </span></div>
|
||
<div class="line"><a id="l14444" name="l14444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24fb9df620319cb9d09fb93822cf9673">14444</a></span><span class="preprocessor">#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk </span></div>
|
||
<div class="line"><a id="l14445" name="l14445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86dad56d8d5e8ced81ff1486b8f8b82c">14445</a></span><span class="preprocessor">#define USB_OTG_DAINTMSK_OEPM_Pos (16U) </span></div>
|
||
<div class="line"><a id="l14446" name="l14446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1e90f8633158170a810a7b739d280aa">14446</a></span><span class="preprocessor">#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) </span></div>
|
||
<div class="line"><a id="l14447" name="l14447"></a><span class="lineno">14447</span><span class="preprocessor">#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk </span></div>
|
||
<div class="line"><a id="l14449" name="l14449"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac57cf2cc40ef0ecb3f7162af3bde8417">14449</a></span><span class="comment">/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/</span></div>
|
||
<div class="line"><a id="l14450" name="l14450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19912b7862dbda078a7c986251282051">14450</a></span><span class="preprocessor">#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14451" name="l14451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga645e153273d36f18999be31a5f9c152b">14451</a></span><span class="preprocessor">#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) </span></div>
|
||
<div class="line"><a id="l14452" name="l14452"></a><span class="lineno">14452</span><span class="preprocessor">#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk </span></div>
|
||
<div class="line"><a id="l14454" name="l14454"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga068bb85a1956e5ef91ed2556a68814da">14454</a></span><span class="comment">/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/</span></div>
|
||
<div class="line"><a id="l14455" name="l14455"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05d481daeec0e3867bc14ddbf33c668b">14455</a></span><span class="preprocessor">#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14456" name="l14456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga749c7152aea411faaaeec1b43afb43e5">14456</a></span><span class="preprocessor">#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) </span></div>
|
||
<div class="line"><a id="l14457" name="l14457"></a><span class="lineno">14457</span><span class="preprocessor">#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk </span></div>
|
||
<div class="line"><a id="l14459" name="l14459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad33e0dcd0891b3d9175d22596f37335e">14459</a></span><span class="comment">/******************** Bit definition for OTG register ********************/</span></div>
|
||
<div class="line"><a id="l14460" name="l14460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d574718d661d828fdbd50dd9de84f79">14460</a></span><span class="preprocessor">#define USB_OTG_NPTXFSA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14461" name="l14461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7288bc9a03bd0068584bfbf7a00de132">14461</a></span><span class="preprocessor">#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) </span></div>
|
||
<div class="line"><a id="l14462" name="l14462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga954d5cbcea939dfff88dcbf8be48fcb8">14462</a></span><span class="preprocessor">#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk </span></div>
|
||
<div class="line"><a id="l14463" name="l14463"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga925ee7600d2f4c33f4ada106ad2da436">14463</a></span><span class="preprocessor">#define USB_OTG_NPTXFD_Pos (16U) </span></div>
|
||
<div class="line"><a id="l14464" name="l14464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa42909f04dfa46977d5d95ba84a81f7a">14464</a></span><span class="preprocessor">#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) </span></div>
|
||
<div class="line"><a id="l14465" name="l14465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09477e07dbd7bb519ed546c5a609f9e2">14465</a></span><span class="preprocessor">#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk </span></div>
|
||
<div class="line"><a id="l14466" name="l14466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1135e855d8d6bd816ab72978a82217d5">14466</a></span><span class="preprocessor">#define USB_OTG_TX0FSA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14467" name="l14467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga878564768aedb86dd987f933edd56ded">14467</a></span><span class="preprocessor">#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) </span></div>
|
||
<div class="line"><a id="l14468" name="l14468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1230d9e57244b6175d180f4055043add">14468</a></span><span class="preprocessor">#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk </span></div>
|
||
<div class="line"><a id="l14469" name="l14469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9db88da5ed817b0e836a7fe631b8a3c">14469</a></span><span class="preprocessor">#define USB_OTG_TX0FD_Pos (16U) </span></div>
|
||
<div class="line"><a id="l14470" name="l14470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd6ed0dba3c92506928f19a8dae4a4cd">14470</a></span><span class="preprocessor">#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) </span></div>
|
||
<div class="line"><a id="l14471" name="l14471"></a><span class="lineno">14471</span><span class="preprocessor">#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk </span></div>
|
||
<div class="line"><a id="l14473" name="l14473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1debd748822446b78fd35dd4e5bffb2">14473</a></span><span class="comment">/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/</span></div>
|
||
<div class="line"><a id="l14474" name="l14474"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0f53728ef57cfd0c9099458e5ede08b">14474</a></span><span class="preprocessor">#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14475" name="l14475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dc9a44df3a6bf09319feb0ade70219b">14475</a></span><span class="preprocessor">#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) </span></div>
|
||
<div class="line"><a id="l14476" name="l14476"></a><span class="lineno">14476</span><span class="preprocessor">#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk </span></div>
|
||
<div class="line"><a id="l14478" name="l14478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39a026cf1344c10820c26d7b2c6e6d05">14478</a></span><span class="comment">/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/</span></div>
|
||
<div class="line"><a id="l14479" name="l14479"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f2d1e26e3ce0e261b8fbe6fe2797edc">14479</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14480" name="l14480"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e0f0efb60ff9965a1ef407bb36b0c9b">14480</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14481" name="l14481"></a><span class="lineno">14481</span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk </span></div>
|
||
<div class="line"><a id="l14483" name="l14483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca3b71a13949ca23c81dfd7901d5078e">14483</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) </span></div>
|
||
<div class="line"><a id="l14484" name="l14484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0dbb974d940609afd19b073574c40019">14484</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14485" name="l14485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7731a3940c52add8741a9102d1d921b4">14485</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk </span></div>
|
||
<div class="line"><a id="l14486" name="l14486"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaead027a78b6c561c4ab16a7b138373c">14486</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14487" name="l14487"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0af12c08cce383a26e0eef3c6a6fa72">14487</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14488" name="l14488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga896f6671b046ebcba5dde1f267508c2f">14488</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14489" name="l14489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga207fc30605e39e471f9790f69e3fac74">14489</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14490" name="l14490"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d2c61ea0a8811b95ea5880adf869e0b">14490</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14491" name="l14491"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga787291b79ab2b19dcd87a188a8ad0c7b">14491</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14492" name="l14492"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1212da7f367d7ccc3bb3db806c0293c">14492</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14493" name="l14493"></a><span class="lineno">14493</span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) </span></div>
|
||
<div class="line"><a id="l14495" name="l14495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga730120d7b71007fb05f5e74b8d3e6264">14495</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) </span></div>
|
||
<div class="line"><a id="l14496" name="l14496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga111271d7bfdc7155f029c2402d2bac41">14496</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14497" name="l14497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e940aac39f5922c0b7c6ffa797ce691">14497</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk </span></div>
|
||
<div class="line"><a id="l14498" name="l14498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ff80fe229f3a0ca31450cf037ad3117">14498</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14499" name="l14499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb3f5554d1d052c25cba115f406d6f07">14499</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14500" name="l14500"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9fd208770d7a63c0c031fed2b650d19">14500</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14501" name="l14501"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga963a180ae1705b5161555d23fc8f9a1e">14501</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14502" name="l14502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad681db11aef73b8b65b2528f31fa9668">14502</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14503" name="l14503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba22a705c0bd9f3c18a22afcddd3edc4">14503</a></span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14504" name="l14504"></a><span class="lineno">14504</span><span class="preprocessor">#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) </span></div>
|
||
<div class="line"><a id="l14506" name="l14506"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa27b3b7a9c8d5bd43eeed11c120b6b94">14506</a></span><span class="comment">/******************** Bit definition for USB_OTG_DTHRCTL register ********************/</span></div>
|
||
<div class="line"><a id="l14507" name="l14507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb5a75e2c30cc44403d12a7fa3f3bbd6">14507</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14508" name="l14508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90deedb84e953f01c80f382926cc07f7">14508</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) </span></div>
|
||
<div class="line"><a id="l14509" name="l14509"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacad27878401eaeb8cbf31bcca1aec333">14509</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk </span></div>
|
||
<div class="line"><a id="l14510" name="l14510"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace1a2aa524f45130efc83e053acb865b">14510</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14511" name="l14511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04e741a79f38ab24adc52bd7143af049">14511</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) </span></div>
|
||
<div class="line"><a id="l14512" name="l14512"></a><span class="lineno">14512</span><span class="preprocessor">#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk </span></div>
|
||
<div class="line"><a id="l14514" name="l14514"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43e14dc940b6baf117c256d9c60aa2e0">14514</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) </span></div>
|
||
<div class="line"><a id="l14515" name="l14515"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89abc875678e55dd6f0404d06fd71ac4">14515</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14516" name="l14516"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6dc7e5363efa0a295aa92980b6cc04fa">14516</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk </span></div>
|
||
<div class="line"><a id="l14517" name="l14517"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77e5b0ffa7872b1a86a5c1b595e1010e">14517</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14518" name="l14518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05f69f648818f4c055d939afc66946ae">14518</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14519" name="l14519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf30c1d04c0cdd9d55beae15953ec7693">14519</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14520" name="l14520"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49b7ac9081652b86cba455dd0241ec67">14520</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14521" name="l14521"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5adde0e7e9543650a413afa08241a990">14521</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14522" name="l14522"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13d34b0ad2fc0bb5c9fef41cf8d139a2">14522</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14523" name="l14523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86ac850ea713f1545dcd207e2e5bd104">14523</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14524" name="l14524"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4eafc52de58d4605d63ba125ceb08e93">14524</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14525" name="l14525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18423f010a887869d9240587099fb245">14525</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14526" name="l14526"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7ea756a244f4f1c30f3d1feab40f90d">14526</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) </span></div>
|
||
<div class="line"><a id="l14527" name="l14527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccd6ccdda30038743b8857ec89c897d0">14527</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) </span></div>
|
||
<div class="line"><a id="l14528" name="l14528"></a><span class="lineno">14528</span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk </span></div>
|
||
<div class="line"><a id="l14530" name="l14530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86e3d673a7dffea2edb0212199ca55d8">14530</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) </span></div>
|
||
<div class="line"><a id="l14531" name="l14531"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33dd5d34180983c398a1944eafd47fac">14531</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14532" name="l14532"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabfb6edd2de6ee8c4680a604711920b83">14532</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk </span></div>
|
||
<div class="line"><a id="l14533" name="l14533"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga933148ffeb4784606b66a3229d77b921">14533</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14534" name="l14534"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4208cac73e194db119277ed12a69eedd">14534</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14535" name="l14535"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c499a8120b848257819105790c44aef">14535</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14536" name="l14536"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b8e7493d15184845243110b44ef4e45">14536</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14537" name="l14537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1a10cc9b79775c3c0067a1b005862f0">14537</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14538" name="l14538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee1447a1041c5a2b2a88fd2edacb9cdf">14538</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14539" name="l14539"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f753e4d8650b04a44a092c7581cda36">14539</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14540" name="l14540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb2dbf9b5e747cff136273b67258c36e">14540</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14541" name="l14541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1905c98a839664f140afc08295b0e5a2">14541</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) </span></div>
|
||
<div class="line"><a id="l14542" name="l14542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac23e9fc77b37f86b49a3e6f9bb4f711b">14542</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) </span></div>
|
||
<div class="line"><a id="l14543" name="l14543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gababbacdcc33bdd2be91513fd31c4efbc">14543</a></span><span class="preprocessor">#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) </span></div>
|
||
<div class="line"><a id="l14544" name="l14544"></a><span class="lineno">14544</span><span class="preprocessor">#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk </span></div>
|
||
<div class="line"><a id="l14546" name="l14546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga417e459f4724862c9832ec1a3762774c">14546</a></span><span class="comment">/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/</span></div>
|
||
<div class="line"><a id="l14547" name="l14547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e5d9742bbb59530bdf7648a369aa31a">14547</a></span><span class="preprocessor">#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14548" name="l14548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8129b6a9f51c5131fb60ae0b92887af">14548</a></span><span class="preprocessor">#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) </span></div>
|
||
<div class="line"><a id="l14549" name="l14549"></a><span class="lineno">14549</span><span class="preprocessor">#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk </span></div>
|
||
<div class="line"><a id="l14551" name="l14551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga199c8da83c26360084406b7ead8f5d3b">14551</a></span><span class="comment">/******************** Bit definition for USB_OTG_DEACHINT register ********************/</span></div>
|
||
<div class="line"><a id="l14552" name="l14552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad029d48387a2d3e0e29661bab1848c41">14552</a></span><span class="preprocessor">#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14553" name="l14553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc58bf6e4389a56f5482f3c3b9f0afae">14553</a></span><span class="preprocessor">#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) </span></div>
|
||
<div class="line"><a id="l14554" name="l14554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68088b39445739349ceaf47186f57b80">14554</a></span><span class="preprocessor">#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk </span></div>
|
||
<div class="line"><a id="l14555" name="l14555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15176fb77b4e56480776944239113e2d">14555</a></span><span class="preprocessor">#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) </span></div>
|
||
<div class="line"><a id="l14556" name="l14556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga303cb170236d7f710cc125fb1af37179">14556</a></span><span class="preprocessor">#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) </span></div>
|
||
<div class="line"><a id="l14557" name="l14557"></a><span class="lineno">14557</span><span class="preprocessor">#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk </span></div>
|
||
<div class="line"><a id="l14559" name="l14559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa044953a65f22022f0b54cf1f35216cc">14559</a></span><span class="comment">/******************** Bit definition for USB_OTG_GCCFG register ********************/</span></div>
|
||
<div class="line"><a id="l14560" name="l14560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29705f28087b457d2e6d6ade469b8da8">14560</a></span><span class="preprocessor">#define USB_OTG_GCCFG_PWRDWN_Pos (16U) </span></div>
|
||
<div class="line"><a id="l14561" name="l14561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c298cedbc73302fae613084ad098b22">14561</a></span><span class="preprocessor">#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) </span></div>
|
||
<div class="line"><a id="l14562" name="l14562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bd96a2a753042888490b2d8b5cdae0f">14562</a></span><span class="preprocessor">#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk </span></div>
|
||
<div class="line"><a id="l14563" name="l14563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4d5a74bbfa9c61ca56b7b1f5a511dd3">14563</a></span><span class="preprocessor">#define USB_OTG_GCCFG_I2CPADEN_Pos (17U) </span></div>
|
||
<div class="line"><a id="l14564" name="l14564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga048469450e7d634cafa2e5677e5182b3">14564</a></span><span class="preprocessor">#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) </span></div>
|
||
<div class="line"><a id="l14565" name="l14565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa59fa04d9f6d8e352b2a880b2cdd6163">14565</a></span><span class="preprocessor">#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk </span></div>
|
||
<div class="line"><a id="l14566" name="l14566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa234c38562741de2c25aa2d87a53b2b9">14566</a></span><span class="preprocessor">#define USB_OTG_GCCFG_VBUSASEN_Pos (18U) </span></div>
|
||
<div class="line"><a id="l14567" name="l14567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83a0db31f98476dc46d77a77475c2991">14567</a></span><span class="preprocessor">#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) </span></div>
|
||
<div class="line"><a id="l14568" name="l14568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90a2fb91409323a578610f09cac80a12">14568</a></span><span class="preprocessor">#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk </span></div>
|
||
<div class="line"><a id="l14569" name="l14569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11b625bb997a725e1965d4a678f0bea4">14569</a></span><span class="preprocessor">#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) </span></div>
|
||
<div class="line"><a id="l14570" name="l14570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1aa57c29a5c04621f54b2125536d11b2">14570</a></span><span class="preprocessor">#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) </span></div>
|
||
<div class="line"><a id="l14571" name="l14571"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36422f7842d3381290b5c7f1e1d920c8">14571</a></span><span class="preprocessor">#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk </span></div>
|
||
<div class="line"><a id="l14572" name="l14572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e05968150501b4f565898b43d33aed8">14572</a></span><span class="preprocessor">#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) </span></div>
|
||
<div class="line"><a id="l14573" name="l14573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3caba9befa711f3bdeb99e0ed33d608">14573</a></span><span class="preprocessor">#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) </span></div>
|
||
<div class="line"><a id="l14574" name="l14574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga198d2b56aa36042fd5874d004d8a71f5">14574</a></span><span class="preprocessor">#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk </span></div>
|
||
<div class="line"><a id="l14575" name="l14575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84a118dc6bff7012b8a6d944b15089b8">14575</a></span><span class="preprocessor">#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U) </span></div>
|
||
<div class="line"><a id="l14576" name="l14576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b38845c9338d0637983b3d81fc0c95d">14576</a></span><span class="preprocessor">#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) </span></div>
|
||
<div class="line"><a id="l14577" name="l14577"></a><span class="lineno">14577</span><span class="preprocessor">#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk </span></div>
|
||
<div class="line"><a id="l14579" name="l14579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ee42186200d9099506cd4c8f877eba3">14579</a></span><span class="comment">/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/</span></div>
|
||
<div class="line"><a id="l14580" name="l14580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8771cbb994263301333d9847621094e">14580</a></span><span class="preprocessor">#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14581" name="l14581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga258a2e60f2796217e28607252d4c57bf">14581</a></span><span class="preprocessor">#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) </span></div>
|
||
<div class="line"><a id="l14582" name="l14582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ddea2717e85931ae3085ef697f30311">14582</a></span><span class="preprocessor">#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk </span></div>
|
||
<div class="line"><a id="l14583" name="l14583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga429749723f28d5ac2c69768ec5340d17">14583</a></span><span class="preprocessor">#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) </span></div>
|
||
<div class="line"><a id="l14584" name="l14584"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fc88b5e76ded044e77ec4bebbe91ec5">14584</a></span><span class="preprocessor">#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) </span></div>
|
||
<div class="line"><a id="l14585" name="l14585"></a><span class="lineno">14585</span><span class="preprocessor">#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk </span></div>
|
||
<div class="line"><a id="l14587" name="l14587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga812e14aa406ecfa45f30df73aacbd611">14587</a></span><span class="comment">/******************** Bit definition for USB_OTG_CID register ********************/</span></div>
|
||
<div class="line"><a id="l14588" name="l14588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c0749f0863635f439e2d8b760eeee17">14588</a></span><span class="preprocessor">#define USB_OTG_CID_PRODUCT_ID_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14589" name="l14589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bad40ec1b2cb101eaa49a5605f7a097">14589</a></span><span class="preprocessor">#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) </span></div>
|
||
<div class="line"><a id="l14590" name="l14590"></a><span class="lineno">14590</span><span class="preprocessor">#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk </span></div>
|
||
<div class="line"><a id="l14592" name="l14592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5be6178b3fbce4257db1b3272e5108b1">14592</a></span><span class="comment">/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/</span></div>
|
||
<div class="line"><a id="l14593" name="l14593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e1c74dcd04816e72d4dcb0cb87407bb">14593</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14594" name="l14594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3720d0a07deae3c6ff0c6c30c03543c">14594</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) </span></div>
|
||
<div class="line"><a id="l14595" name="l14595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae21af2079e378d491e4fb43a5048b422">14595</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk </span></div>
|
||
<div class="line"><a id="l14596" name="l14596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cd0e0b574eba98114663d2eafcd3efd">14596</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14597" name="l14597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62e4b8c28bb41136e5d6d3de217e5afd">14597</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) </span></div>
|
||
<div class="line"><a id="l14598" name="l14598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7759259bb9b0d42d020b79d0fe3a8d1a">14598</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk </span></div>
|
||
<div class="line"><a id="l14599" name="l14599"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga460e8e6ba9daf019aa81f13d097a19fc">14599</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) </span></div>
|
||
<div class="line"><a id="l14600" name="l14600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae910eb3d34714653d43579dcface4ead">14600</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) </span></div>
|
||
<div class="line"><a id="l14601" name="l14601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8f0a7616486631d230baade93ed84d8">14601</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk </span></div>
|
||
<div class="line"><a id="l14602" name="l14602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f86ddcb79c7f4467cdcd206e95dec7e">14602</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) </span></div>
|
||
<div class="line"><a id="l14603" name="l14603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96b7b0c15d5b36f6f3925e51d56990ac">14603</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) </span></div>
|
||
<div class="line"><a id="l14604" name="l14604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabffd6dd8a5069f4eb0ceacde6f8b1c81">14604</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk </span></div>
|
||
<div class="line"><a id="l14605" name="l14605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdc16990fc5f01933112bbba2fa079a9">14605</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) </span></div>
|
||
<div class="line"><a id="l14606" name="l14606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcc0f1fab9aac10d6edff07dde25d5bc">14606</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) </span></div>
|
||
<div class="line"><a id="l14607" name="l14607"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae45a7ceb9a2a0fe26a60b723e80d7f4b">14607</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk </span></div>
|
||
<div class="line"><a id="l14608" name="l14608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga720ea28b3588862d6054ca5b13a7a883">14608</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) </span></div>
|
||
<div class="line"><a id="l14609" name="l14609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8ee1bc04de47f522a90619d57086b06">14609</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) </span></div>
|
||
<div class="line"><a id="l14610" name="l14610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e8c4451b16845ea560b21c80640b4d6">14610</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk </span></div>
|
||
<div class="line"><a id="l14611" name="l14611"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga227ade985d4eb585dc25efe080981d66">14611</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) </span></div>
|
||
<div class="line"><a id="l14612" name="l14612"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6c8f64ad39f7ca4fe195b0b03067866">14612</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) </span></div>
|
||
<div class="line"><a id="l14613" name="l14613"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c87f9f2c5c5eeedc735b455a1921afd">14613</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk </span></div>
|
||
<div class="line"><a id="l14614" name="l14614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga942df01e1be13f057f2e7ecc286d1621">14614</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) </span></div>
|
||
<div class="line"><a id="l14615" name="l14615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac4445e5439cad7796d3fc5de74a2ed8">14615</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) </span></div>
|
||
<div class="line"><a id="l14616" name="l14616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe57f29d04c457e07e50a6cbcd273505">14616</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk </span></div>
|
||
<div class="line"><a id="l14617" name="l14617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63e3d316ebc4d1b530ac5da37be23e6e">14617</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) </span></div>
|
||
<div class="line"><a id="l14618" name="l14618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4089e9aeb641963584d76c932f78e06">14618</a></span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) </span></div>
|
||
<div class="line"><a id="l14619" name="l14619"></a><span class="lineno">14619</span><span class="preprocessor">#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk </span></div>
|
||
<div class="line"><a id="l14621" name="l14621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd91baead77bc3be91bf92566210fca2">14621</a></span><span class="comment">/******************** Bit definition for USB_OTG_HPRT register ********************/</span></div>
|
||
<div class="line"><a id="l14622" name="l14622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6277ab1fc490e322b3da7f1ebab56dce">14622</a></span><span class="preprocessor">#define USB_OTG_HPRT_PCSTS_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14623" name="l14623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01b303083e66f3018e57dbb275b6f4b5">14623</a></span><span class="preprocessor">#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) </span></div>
|
||
<div class="line"><a id="l14624" name="l14624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20a5c1b6c67d02966503ed2867676c03">14624</a></span><span class="preprocessor">#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk </span></div>
|
||
<div class="line"><a id="l14625" name="l14625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd445d6f75df03444eb8b978d39f1e6f">14625</a></span><span class="preprocessor">#define USB_OTG_HPRT_PCDET_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14626" name="l14626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bd9f8a9da09f9d52f19b8e68551c285">14626</a></span><span class="preprocessor">#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) </span></div>
|
||
<div class="line"><a id="l14627" name="l14627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa45a500ec95308387eebdfb881c0fcfc">14627</a></span><span class="preprocessor">#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk </span></div>
|
||
<div class="line"><a id="l14628" name="l14628"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8068309917d8be1de7bc9a2d9dea22e6">14628</a></span><span class="preprocessor">#define USB_OTG_HPRT_PENA_Pos (2U) </span></div>
|
||
<div class="line"><a id="l14629" name="l14629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95ad10f10631095aeb7a27e0475242f0">14629</a></span><span class="preprocessor">#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) </span></div>
|
||
<div class="line"><a id="l14630" name="l14630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47e25510c52062775f4155eb233a4bca">14630</a></span><span class="preprocessor">#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk </span></div>
|
||
<div class="line"><a id="l14631" name="l14631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2e7655490c7bdff631166769d46838d">14631</a></span><span class="preprocessor">#define USB_OTG_HPRT_PENCHNG_Pos (3U) </span></div>
|
||
<div class="line"><a id="l14632" name="l14632"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d84be9a2f9c7f8750ee448c99164821">14632</a></span><span class="preprocessor">#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) </span></div>
|
||
<div class="line"><a id="l14633" name="l14633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3602a595b6dd2c43483e6df37567ebc">14633</a></span><span class="preprocessor">#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk </span></div>
|
||
<div class="line"><a id="l14634" name="l14634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf14c79e04bc40d676bb24be0b41145ca">14634</a></span><span class="preprocessor">#define USB_OTG_HPRT_POCA_Pos (4U) </span></div>
|
||
<div class="line"><a id="l14635" name="l14635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4d510d6215d72faac65ad3109f009af">14635</a></span><span class="preprocessor">#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) </span></div>
|
||
<div class="line"><a id="l14636" name="l14636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac12d375e01d04a960d38b26dd2e8685f">14636</a></span><span class="preprocessor">#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk </span></div>
|
||
<div class="line"><a id="l14637" name="l14637"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63a4749bf5614ee8388364463ef039d6">14637</a></span><span class="preprocessor">#define USB_OTG_HPRT_POCCHNG_Pos (5U) </span></div>
|
||
<div class="line"><a id="l14638" name="l14638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc46d2c0e7f2525ad2d1dcb41c5e3814">14638</a></span><span class="preprocessor">#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) </span></div>
|
||
<div class="line"><a id="l14639" name="l14639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33aaef70a252270021a2aaef1c33b726">14639</a></span><span class="preprocessor">#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk </span></div>
|
||
<div class="line"><a id="l14640" name="l14640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3cf39420fbe05f13da97b9d4f54c753">14640</a></span><span class="preprocessor">#define USB_OTG_HPRT_PRES_Pos (6U) </span></div>
|
||
<div class="line"><a id="l14641" name="l14641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga643fdc3285aa718952214857d15dadfb">14641</a></span><span class="preprocessor">#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) </span></div>
|
||
<div class="line"><a id="l14642" name="l14642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga017663af01aba7f6745732a92f731668">14642</a></span><span class="preprocessor">#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk </span></div>
|
||
<div class="line"><a id="l14643" name="l14643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5b1f55077b63ba7fda82f1d5d06de23">14643</a></span><span class="preprocessor">#define USB_OTG_HPRT_PSUSP_Pos (7U) </span></div>
|
||
<div class="line"><a id="l14644" name="l14644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98db6454c00ab942c1ca969ebb192f67">14644</a></span><span class="preprocessor">#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) </span></div>
|
||
<div class="line"><a id="l14645" name="l14645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac3ce670bb14739add1077513f30a91e">14645</a></span><span class="preprocessor">#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk </span></div>
|
||
<div class="line"><a id="l14646" name="l14646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26c4eb727f6b37a90e1b9a2aaa64414d">14646</a></span><span class="preprocessor">#define USB_OTG_HPRT_PRST_Pos (8U) </span></div>
|
||
<div class="line"><a id="l14647" name="l14647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5741bb0728c8ccf320ef609699c3425a">14647</a></span><span class="preprocessor">#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) </span></div>
|
||
<div class="line"><a id="l14648" name="l14648"></a><span class="lineno">14648</span><span class="preprocessor">#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk </span></div>
|
||
<div class="line"><a id="l14650" name="l14650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b757dac879fce7dae5214b192863ea2">14650</a></span><span class="preprocessor">#define USB_OTG_HPRT_PLSTS_Pos (10U) </span></div>
|
||
<div class="line"><a id="l14651" name="l14651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0a3c8eb0d6b7eea1f4aaf60bb27b15c">14651</a></span><span class="preprocessor">#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) </span></div>
|
||
<div class="line"><a id="l14652" name="l14652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bbb5a9719331ba00d44ff01b267bf7d">14652</a></span><span class="preprocessor">#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk </span></div>
|
||
<div class="line"><a id="l14653" name="l14653"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae87cecc544d0c1d8e778c3a598da9276">14653</a></span><span class="preprocessor">#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) </span></div>
|
||
<div class="line"><a id="l14654" name="l14654"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88c07618a453428a840a89100f6dab38">14654</a></span><span class="preprocessor">#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) </span></div>
|
||
<div class="line"><a id="l14655" name="l14655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cd2ac835835be4a80bc43659d300ebe">14655</a></span><span class="preprocessor">#define USB_OTG_HPRT_PPWR_Pos (12U) </span></div>
|
||
<div class="line"><a id="l14656" name="l14656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20965e6de30c19d8b0f355f62680c180">14656</a></span><span class="preprocessor">#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) </span></div>
|
||
<div class="line"><a id="l14657" name="l14657"></a><span class="lineno">14657</span><span class="preprocessor">#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk </span></div>
|
||
<div class="line"><a id="l14659" name="l14659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a02e11d6a1f700ee19fcc08117ebe16">14659</a></span><span class="preprocessor">#define USB_OTG_HPRT_PTCTL_Pos (13U) </span></div>
|
||
<div class="line"><a id="l14660" name="l14660"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01677a7e4ccb6c54d7bce0cba3899bfb">14660</a></span><span class="preprocessor">#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) </span></div>
|
||
<div class="line"><a id="l14661" name="l14661"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f4faf063b47c7bc83c090e6000e9162">14661</a></span><span class="preprocessor">#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk </span></div>
|
||
<div class="line"><a id="l14662" name="l14662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga791b063b5e86ffbbfd6980f447408e83">14662</a></span><span class="preprocessor">#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) </span></div>
|
||
<div class="line"><a id="l14663" name="l14663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6491b21dbe177ecb91628169d02b8c76">14663</a></span><span class="preprocessor">#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) </span></div>
|
||
<div class="line"><a id="l14664" name="l14664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga087d26522b46212d380ca5a1e1c16fed">14664</a></span><span class="preprocessor">#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) </span></div>
|
||
<div class="line"><a id="l14665" name="l14665"></a><span class="lineno">14665</span><span class="preprocessor">#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) </span></div>
|
||
<div class="line"><a id="l14667" name="l14667"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66c65cc05ea21eebd9013f9f84880385">14667</a></span><span class="preprocessor">#define USB_OTG_HPRT_PSPD_Pos (17U) </span></div>
|
||
<div class="line"><a id="l14668" name="l14668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a28ddd62304e263536ff9b5cd855ff5">14668</a></span><span class="preprocessor">#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) </span></div>
|
||
<div class="line"><a id="l14669" name="l14669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac47d8caa24e4f5e6b66e4d70d549d5fa">14669</a></span><span class="preprocessor">#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk </span></div>
|
||
<div class="line"><a id="l14670" name="l14670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b8f7977f0d956d6955efd2640530f73">14670</a></span><span class="preprocessor">#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) </span></div>
|
||
<div class="line"><a id="l14671" name="l14671"></a><span class="lineno">14671</span><span class="preprocessor">#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) </span></div>
|
||
<div class="line"><a id="l14673" name="l14673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50c80b485139155fd7ede8a5b78af293">14673</a></span><span class="comment">/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/</span></div>
|
||
<div class="line"><a id="l14674" name="l14674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1124b10adb855eb49ab052fd8f7adf5">14674</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14675" name="l14675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f709b5af2c771d66d240adef5d8be21">14675</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) </span></div>
|
||
<div class="line"><a id="l14676" name="l14676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac39a208617e70f246d83e7ca33f2d63a">14676</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk </span></div>
|
||
<div class="line"><a id="l14677" name="l14677"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c0d1dc807789f08756d5eebc35065e5">14677</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14678" name="l14678"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga866580df1a60ef8b3347d63b1369f76e">14678</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) </span></div>
|
||
<div class="line"><a id="l14679" name="l14679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2a3e66bdba3af962f77a2643a8dfe38">14679</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk </span></div>
|
||
<div class="line"><a id="l14680" name="l14680"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae427974c1d2cd44962a72e5ad4d9e68">14680</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) </span></div>
|
||
<div class="line"><a id="l14681" name="l14681"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga038706cd615636fe5bf10e6636b3c035">14681</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) </span></div>
|
||
<div class="line"><a id="l14682" name="l14682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20102cf4a07490f60bd525bce51de6b6">14682</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk </span></div>
|
||
<div class="line"><a id="l14683" name="l14683"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga958f2820ea10558695b00400bfed9927">14683</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) </span></div>
|
||
<div class="line"><a id="l14684" name="l14684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace8821806fb4cb204d97dbb965e5067d">14684</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) </span></div>
|
||
<div class="line"><a id="l14685" name="l14685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe0a86e9dbdf4a15922a6503e78c2f67">14685</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk </span></div>
|
||
<div class="line"><a id="l14686" name="l14686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0193a714c31b0cf57e25588071cc637">14686</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) </span></div>
|
||
<div class="line"><a id="l14687" name="l14687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20d91d742e89a430937207cca6dd0a1a">14687</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) </span></div>
|
||
<div class="line"><a id="l14688" name="l14688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga773825312f8b0edbb607a5fea843c882">14688</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk </span></div>
|
||
<div class="line"><a id="l14689" name="l14689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6b4fd478ae41b36f08356f9c98840d5">14689</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) </span></div>
|
||
<div class="line"><a id="l14690" name="l14690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73a879622564efeb3244262bf9419818">14690</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) </span></div>
|
||
<div class="line"><a id="l14691" name="l14691"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae23cef3a94a622721e9f36176b8ee292">14691</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk </span></div>
|
||
<div class="line"><a id="l14692" name="l14692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bd6db454cff3d758f6d9d36f8bac8c1">14692</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) </span></div>
|
||
<div class="line"><a id="l14693" name="l14693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3ca9111b1b74380566ce72b6c985560">14693</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) </span></div>
|
||
<div class="line"><a id="l14694" name="l14694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85a209e39fa583a74b58fa30ccc01496">14694</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk </span></div>
|
||
<div class="line"><a id="l14695" name="l14695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4b101ae377598650c667420a8465cef">14695</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) </span></div>
|
||
<div class="line"><a id="l14696" name="l14696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa99f230d086cf41692cfab0c1aad0f26">14696</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) </span></div>
|
||
<div class="line"><a id="l14697" name="l14697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d940b15d335a584cb074297e330804c">14697</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk </span></div>
|
||
<div class="line"><a id="l14698" name="l14698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb8873ed6ca0091147855a58b22054ed">14698</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) </span></div>
|
||
<div class="line"><a id="l14699" name="l14699"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3eecdae7aa0c9b1b40f219e8b0c18879">14699</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) </span></div>
|
||
<div class="line"><a id="l14700" name="l14700"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6935021f39b8b2ba43e5e963c441c0bf">14700</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk </span></div>
|
||
<div class="line"><a id="l14701" name="l14701"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94cf1998cd40af00f7295c221fd4850b">14701</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) </span></div>
|
||
<div class="line"><a id="l14702" name="l14702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98fa7db10f7b8e4998d30646a9e8e266">14702</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) </span></div>
|
||
<div class="line"><a id="l14703" name="l14703"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9738465ddedbad09f63f86d8932235ca">14703</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk </span></div>
|
||
<div class="line"><a id="l14704" name="l14704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5cfdf8dc17970f375d544ff23c3369fc">14704</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) </span></div>
|
||
<div class="line"><a id="l14705" name="l14705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bcea3bd49b83367b4f62c554815770e">14705</a></span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) </span></div>
|
||
<div class="line"><a id="l14706" name="l14706"></a><span class="lineno">14706</span><span class="preprocessor">#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk </span></div>
|
||
<div class="line"><a id="l14708" name="l14708"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga249c1794df3b2690031184ae330118e7">14708</a></span><span class="comment">/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/</span></div>
|
||
<div class="line"><a id="l14709" name="l14709"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9be1af071c308f74cf353d2ce3d691b9">14709</a></span><span class="preprocessor">#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14710" name="l14710"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62a28fc8c8ab16a52858febfbb0382ef">14710</a></span><span class="preprocessor">#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) </span></div>
|
||
<div class="line"><a id="l14711" name="l14711"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab930c4f0f50e3f18256064a8f2bdb2b4">14711</a></span><span class="preprocessor">#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk </span></div>
|
||
<div class="line"><a id="l14712" name="l14712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b5b79b979f2e9443324066faaa92245">14712</a></span><span class="preprocessor">#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) </span></div>
|
||
<div class="line"><a id="l14713" name="l14713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85a628f9094f55c620b2846635803781">14713</a></span><span class="preprocessor">#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) </span></div>
|
||
<div class="line"><a id="l14714" name="l14714"></a><span class="lineno">14714</span><span class="preprocessor">#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk </span></div>
|
||
<div class="line"><a id="l14716" name="l14716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f340944f765c7e6ed22c40b337d8fc1">14716</a></span><span class="comment">/******************** Bit definition for USB_OTG_DIEPCTL register ********************/</span></div>
|
||
<div class="line"><a id="l14717" name="l14717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ea4a7999fe1ba166d761a56a5f045aa">14717</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14718" name="l14718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabda35dcaaa3faa8443bec36b9edc438e">14718</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) </span></div>
|
||
<div class="line"><a id="l14719" name="l14719"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3259dc5bb86cce573ba8469dc82573f">14719</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk </span></div>
|
||
<div class="line"><a id="l14720" name="l14720"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2847317d82bfe14ae48839902c177dd">14720</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) </span></div>
|
||
<div class="line"><a id="l14721" name="l14721"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52604d4a0d7b24ad619a2860003e8fe3">14721</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) </span></div>
|
||
<div class="line"><a id="l14722" name="l14722"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4ea8a7d612c65303a2d6e6c89a6e99c">14722</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk </span></div>
|
||
<div class="line"><a id="l14723" name="l14723"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4d849a015e877f7b9e4a82291a9997b">14723</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) </span></div>
|
||
<div class="line"><a id="l14724" name="l14724"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f908cbb98598542f631c746bc3a85a1">14724</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) </span></div>
|
||
<div class="line"><a id="l14725" name="l14725"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78ccc71651a434402bef238206f3cd32">14725</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk </span></div>
|
||
<div class="line"><a id="l14726" name="l14726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48e2e960476f1b5e1e205bef19c30b5b">14726</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) </span></div>
|
||
<div class="line"><a id="l14727" name="l14727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3aa35782f7d920f0c6520db137bce768">14727</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) </span></div>
|
||
<div class="line"><a id="l14728" name="l14728"></a><span class="lineno">14728</span><span class="preprocessor">#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk </span></div>
|
||
<div class="line"><a id="l14730" name="l14730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf416ce016be26169bcb25b1eea153f08">14730</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) </span></div>
|
||
<div class="line"><a id="l14731" name="l14731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fc1b4e978ef3a22450da75f2608dff2">14731</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) </span></div>
|
||
<div class="line"><a id="l14732" name="l14732"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4da4d418faa4245347a4ad3c1b8334d9">14732</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk </span></div>
|
||
<div class="line"><a id="l14733" name="l14733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2ca76cb985239ed613062b1087075ab">14733</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) </span></div>
|
||
<div class="line"><a id="l14734" name="l14734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga740abf97e28d1670808797448f75d062">14734</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) </span></div>
|
||
<div class="line"><a id="l14735" name="l14735"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72b289fbf1a810cefd61091e9affcf62">14735</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_STALL_Pos (21U) </span></div>
|
||
<div class="line"><a id="l14736" name="l14736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab313ac4b4a0d85f45af3733d574cb9a9">14736</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) </span></div>
|
||
<div class="line"><a id="l14737" name="l14737"></a><span class="lineno">14737</span><span class="preprocessor">#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk </span></div>
|
||
<div class="line"><a id="l14739" name="l14739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e8e627baaad5f7ed0176d106ec0f43a">14739</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) </span></div>
|
||
<div class="line"><a id="l14740" name="l14740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2a4ce33e0e644c9439c9cce59b2edfa">14740</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14741" name="l14741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0cd18c0071ac8c9676fbc010a07ef49">14741</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk </span></div>
|
||
<div class="line"><a id="l14742" name="l14742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e710b13ec4621897335fe9e18c7398c">14742</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14743" name="l14743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bf5811bde53bd29c3c91ab07fdc2a5b">14743</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14744" name="l14744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae67a96234e062d1304a4af3afc938164">14744</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14745" name="l14745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34262b1369356b472f2f5fd07ab00329">14745</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14746" name="l14746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4398c0cf3ff27735935e0ec567d28dcc">14746</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_CNAK_Pos (26U) </span></div>
|
||
<div class="line"><a id="l14747" name="l14747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7aa93621e2379266fd2901742f9d652">14747</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) </span></div>
|
||
<div class="line"><a id="l14748" name="l14748"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae02f66b28850f4cde25bc3c4d844d7f5">14748</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk </span></div>
|
||
<div class="line"><a id="l14749" name="l14749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79c45bf1dcfa6b08ee039f3dde83926a">14749</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_SNAK_Pos (27U) </span></div>
|
||
<div class="line"><a id="l14750" name="l14750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04939f2cc7cab01a34b516197883c542">14750</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) </span></div>
|
||
<div class="line"><a id="l14751" name="l14751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa2ed3b1957b14db8a12ba9553356607">14751</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk </span></div>
|
||
<div class="line"><a id="l14752" name="l14752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cabb03e5a98b0496a9f019d337362dc">14752</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) </span></div>
|
||
<div class="line"><a id="l14753" name="l14753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5ea132b2710076fcc0ef9ebaffe7e1e">14753</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) </span></div>
|
||
<div class="line"><a id="l14754" name="l14754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2f39c24ed8d37c04b07b7decd807af2">14754</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk </span></div>
|
||
<div class="line"><a id="l14755" name="l14755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06e1743fc6505d240ba8929c579a807a">14755</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) </span></div>
|
||
<div class="line"><a id="l14756" name="l14756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae874b1d1b15b4ada193bab411634a37a">14756</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) </span></div>
|
||
<div class="line"><a id="l14757" name="l14757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2daf3ac53bfdfdbb7835126c245b34c2">14757</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk </span></div>
|
||
<div class="line"><a id="l14758" name="l14758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c56726a11ab538f4108a37ffd15f254">14758</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) </span></div>
|
||
<div class="line"><a id="l14759" name="l14759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9cc396ddf6cd0c0781acec4e278aa815">14759</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) </span></div>
|
||
<div class="line"><a id="l14760" name="l14760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga465665c0a5926a0b27ec5288e46d2394">14760</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk </span></div>
|
||
<div class="line"><a id="l14761" name="l14761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5eb8f53ab834ffe44f784baab031791">14761</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_EPENA_Pos (31U) </span></div>
|
||
<div class="line"><a id="l14762" name="l14762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6951a1febc2510628114a0297170bce">14762</a></span><span class="preprocessor">#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) </span></div>
|
||
<div class="line"><a id="l14763" name="l14763"></a><span class="lineno">14763</span><span class="preprocessor">#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk </span></div>
|
||
<div class="line"><a id="l14765" name="l14765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca874060952d9d5d5a31d3ce095d0358">14765</a></span><span class="comment">/******************** Bit definition for USB_OTG_HCCHAR register ********************/</span></div>
|
||
<div class="line"><a id="l14766" name="l14766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacaf54f4394f57b2eea234e1aeb4bb43">14766</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14767" name="l14767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7d25c42363f797cf4c2c308006de784">14767</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) </span></div>
|
||
<div class="line"><a id="l14768" name="l14768"></a><span class="lineno">14768</span><span class="preprocessor">#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk </span></div>
|
||
<div class="line"><a id="l14770" name="l14770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7341e59397aba116872d63a3606d0cb6">14770</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_EPNUM_Pos (11U) </span></div>
|
||
<div class="line"><a id="l14771" name="l14771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0ac25b2f10b80c3f529c97f225be728">14771</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14772" name="l14772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fa97e03ed82c3f48b7b8ceb38db62bf">14772</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk </span></div>
|
||
<div class="line"><a id="l14773" name="l14773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3898f15c5f3db168ab867f1dbfc8d3b">14773</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14774" name="l14774"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb6e82877f06b262cc0ec2143821ebf3">14774</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14775" name="l14775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3977b57bb81f942fcdde8f4d5e9fe24">14775</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14776" name="l14776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdd23192fd35d666bd97f831304d45d2">14776</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) </span></div>
|
||
<div class="line"><a id="l14777" name="l14777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93cab809dbd5a48454d9370b5cc83571">14777</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_EPDIR_Pos (15U) </span></div>
|
||
<div class="line"><a id="l14778" name="l14778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga303898c1943aede8d1ed6b9f259b9d0c">14778</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) </span></div>
|
||
<div class="line"><a id="l14779" name="l14779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20cb6423ef24ca58ed85c86a008849fc">14779</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk </span></div>
|
||
<div class="line"><a id="l14780" name="l14780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3a41d259407f924e05803713ee882b5">14780</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_LSDEV_Pos (17U) </span></div>
|
||
<div class="line"><a id="l14781" name="l14781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20e48f56546fe73be76efe518c239114">14781</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) </span></div>
|
||
<div class="line"><a id="l14782" name="l14782"></a><span class="lineno">14782</span><span class="preprocessor">#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk </span></div>
|
||
<div class="line"><a id="l14784" name="l14784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga108a8e59d323596cb35aae675e3422eb">14784</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_EPTYP_Pos (18U) </span></div>
|
||
<div class="line"><a id="l14785" name="l14785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1dcca7cc02f8f9f2adf14fdd36b36055">14785</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) </span></div>
|
||
<div class="line"><a id="l14786" name="l14786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a360a7769f0c9ec5a44bdf11b0787b5">14786</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk </span></div>
|
||
<div class="line"><a id="l14787" name="l14787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88b483febece6e61c20347d02dd98b8e">14787</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) </span></div>
|
||
<div class="line"><a id="l14788" name="l14788"></a><span class="lineno">14788</span><span class="preprocessor">#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) </span></div>
|
||
<div class="line"><a id="l14790" name="l14790"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab76a960e55c3396d2d3ef9b790ff9d44">14790</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_MC_Pos (20U) </span></div>
|
||
<div class="line"><a id="l14791" name="l14791"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga373dce758b81f5555b484092be97f4f7">14791</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) </span></div>
|
||
<div class="line"><a id="l14792" name="l14792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f3c212ab7781f5f354c8081d4ef1a60">14792</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk </span></div>
|
||
<div class="line"><a id="l14793" name="l14793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5ecb48ef55ed2a5c7cf5f4ab6f0fac9">14793</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) </span></div>
|
||
<div class="line"><a id="l14794" name="l14794"></a><span class="lineno">14794</span><span class="preprocessor">#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) </span></div>
|
||
<div class="line"><a id="l14796" name="l14796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08d35b165b6c8ca666c72993bee4a098">14796</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_DAD_Pos (22U) </span></div>
|
||
<div class="line"><a id="l14797" name="l14797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1ef60bbb223f7605a2b58d99b0c1734">14797</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l14798" name="l14798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3fd299a559b62badc881da2a5372ebc">14798</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk </span></div>
|
||
<div class="line"><a id="l14799" name="l14799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga172f14d42d36a6782891fc2bb8069258">14799</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l14800" name="l14800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6dc7e9e1a9dee8376aaa948b7caf6f8e">14800</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l14801" name="l14801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9209069e0fc607042c54ef7394aa6b61">14801</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l14802" name="l14802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga835ff39312f6b7b6b8610cdf0dcd3b99">14802</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l14803" name="l14803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79ad8aecc4f86e9d3446691c747a48da">14803</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l14804" name="l14804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0063e054d76ae8962838b7bf9d14ef2">14804</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l14805" name="l14805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b18ec4af69c872fde54266c33774b51">14805</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) </span></div>
|
||
<div class="line"><a id="l14806" name="l14806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3b86db5b44b232005a73d7c660ee326">14806</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) </span></div>
|
||
<div class="line"><a id="l14807" name="l14807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad866d817dedea4edb9514815ab3f5ae6">14807</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) </span></div>
|
||
<div class="line"><a id="l14808" name="l14808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74f85c58e9d1ba64d4bdb8f049cd11e2">14808</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk </span></div>
|
||
<div class="line"><a id="l14809" name="l14809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga917118333ba8be9747a356d0a27e71ae">14809</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_CHDIS_Pos (30U) </span></div>
|
||
<div class="line"><a id="l14810" name="l14810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39de05e23016253698aa5348fffdf8a2">14810</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) </span></div>
|
||
<div class="line"><a id="l14811" name="l14811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee61eaf9a8783c6a440b7835074818e5">14811</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk </span></div>
|
||
<div class="line"><a id="l14812" name="l14812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfdd5a74cad64a4655be2486fce7230b">14812</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_CHENA_Pos (31U) </span></div>
|
||
<div class="line"><a id="l14813" name="l14813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e7dc29241b644b8bcce53440658c93f">14813</a></span><span class="preprocessor">#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) </span></div>
|
||
<div class="line"><a id="l14814" name="l14814"></a><span class="lineno">14814</span><span class="preprocessor">#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk </span></div>
|
||
<div class="line"><a id="l14816" name="l14816"></a><span class="lineno">14816</span><span class="comment">/******************** Bit definition for USB_OTG_HCSPLT register ********************/</span></div>
|
||
<div class="line"><a id="l14817" name="l14817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58473c053e85bca6cd888f694dfc054a">14817</a></span> </div>
|
||
<div class="line"><a id="l14818" name="l14818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bf43d5ac1fcccf90a4a257da69fe9b9">14818</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14819" name="l14819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4fdaef6145025430a8d9d3742b11bf06">14819</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14820" name="l14820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga212d74a7af2379f1b7065bb46fbb9d2a">14820</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk </span></div>
|
||
<div class="line"><a id="l14821" name="l14821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0704e2d889ef64707ab85a66962e1004">14821</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14822" name="l14822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab33fa67bd58f2fa736d8f64bfbea4e5c">14822</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14823" name="l14823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac813f65324490b9885be03ff12328185">14823</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14824" name="l14824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6201a61e92821955efb64d3ccffb0da">14824</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14825" name="l14825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2617f8146fa1656b415f31e9717fd875">14825</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14826" name="l14826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c80e6a85b5960c708594433db74b713">14826</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14827" name="l14827"></a><span class="lineno">14827</span><span class="preprocessor">#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14829" name="l14829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16a3d74ca420462ff6493c0a299b49f8">14829</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) </span></div>
|
||
<div class="line"><a id="l14830" name="l14830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01754e9ee191528767bb4e9c4acb92d8">14830</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14831" name="l14831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6181cfe518eacf85a1fac93dd66327ec">14831</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk </span></div>
|
||
<div class="line"><a id="l14832" name="l14832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb05271f1a273bc14380c9ad00288701">14832</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14833" name="l14833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d1c70b3d92a311b13635ff67f491ec0">14833</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14834" name="l14834"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbb8d9ca0465a572fa7be1afcfa430a8">14834</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14835" name="l14835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad738cccdb8cd3c9db582d8f4aebc3e25">14835</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14836" name="l14836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeaa7e01257224ccaedb6ac4b34b962cf">14836</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14837" name="l14837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32808c2fdb053958a30c5ca464534557">14837</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14838" name="l14838"></a><span class="lineno">14838</span><span class="preprocessor">#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14840" name="l14840"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6229c6f4ebd9ee5ca4cc7feeda5d3e15">14840</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) </span></div>
|
||
<div class="line"><a id="l14841" name="l14841"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8a144d40531b5f7565d81ca90012f2f">14841</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) </span></div>
|
||
<div class="line"><a id="l14842" name="l14842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae22d65d33e06b57429f285a7ae7e655e">14842</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk </span></div>
|
||
<div class="line"><a id="l14843" name="l14843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d1c8241b689b9771dce804274470e08">14843</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) </span></div>
|
||
<div class="line"><a id="l14844" name="l14844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d085f79d265bd2588856d35fa1c83d1">14844</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) </span></div>
|
||
<div class="line"><a id="l14845" name="l14845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74893ad7550eb4c2d08e5568f1c75c6b">14845</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) </span></div>
|
||
<div class="line"><a id="l14846" name="l14846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3f351343c90321b0a43d3a86902bff1">14846</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) </span></div>
|
||
<div class="line"><a id="l14847" name="l14847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga166c9d0c9c88d3331c2ad15ce365d8d0">14847</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk </span></div>
|
||
<div class="line"><a id="l14848" name="l14848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa1a7031a99e4d180e1510827a84f09a">14848</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) </span></div>
|
||
<div class="line"><a id="l14849" name="l14849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa189a5468eabc8d2e05b2c94660060e4">14849</a></span><span class="preprocessor">#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) </span></div>
|
||
<div class="line"><a id="l14850" name="l14850"></a><span class="lineno">14850</span><span class="preprocessor">#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk </span></div>
|
||
<div class="line"><a id="l14852" name="l14852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56016189953a9cbb4085baf96bb4d6c8">14852</a></span><span class="comment">/******************** Bit definition for USB_OTG_HCINT register ********************/</span></div>
|
||
<div class="line"><a id="l14853" name="l14853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae073b77821aa500ba31c336cc510a2dd">14853</a></span><span class="preprocessor">#define USB_OTG_HCINT_XFRC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14854" name="l14854"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga332b761dd88ddfacac9ebff6fced8846">14854</a></span><span class="preprocessor">#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) </span></div>
|
||
<div class="line"><a id="l14855" name="l14855"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga356d30f2a7cbe9b63ac9dd149c872bd7">14855</a></span><span class="preprocessor">#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk </span></div>
|
||
<div class="line"><a id="l14856" name="l14856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga177761d89d797f8d6194e6618792be8d">14856</a></span><span class="preprocessor">#define USB_OTG_HCINT_CHH_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14857" name="l14857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4ecd695c1cc06335445a49780888bb1">14857</a></span><span class="preprocessor">#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) </span></div>
|
||
<div class="line"><a id="l14858" name="l14858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a20fc8de6dd01708697f76f73b9844b">14858</a></span><span class="preprocessor">#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk </span></div>
|
||
<div class="line"><a id="l14859" name="l14859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab7250908e6d8ad8ab40adccafdae4f9">14859</a></span><span class="preprocessor">#define USB_OTG_HCINT_AHBERR_Pos (2U) </span></div>
|
||
<div class="line"><a id="l14860" name="l14860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8b909ca659271857d9f3fcc817d8a4a">14860</a></span><span class="preprocessor">#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) </span></div>
|
||
<div class="line"><a id="l14861" name="l14861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d9beff066b9b48480c25194af3004aa">14861</a></span><span class="preprocessor">#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk </span></div>
|
||
<div class="line"><a id="l14862" name="l14862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd9b71968e54876f10fca2af973a95fb">14862</a></span><span class="preprocessor">#define USB_OTG_HCINT_STALL_Pos (3U) </span></div>
|
||
<div class="line"><a id="l14863" name="l14863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe1d65156f846dcecac479a451b5109e">14863</a></span><span class="preprocessor">#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) </span></div>
|
||
<div class="line"><a id="l14864" name="l14864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad31cbff32e8f912b9dd70fa421465fab">14864</a></span><span class="preprocessor">#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk </span></div>
|
||
<div class="line"><a id="l14865" name="l14865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62c4fd21ba532f275b90104da9c69825">14865</a></span><span class="preprocessor">#define USB_OTG_HCINT_NAK_Pos (4U) </span></div>
|
||
<div class="line"><a id="l14866" name="l14866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga069dfb657cf84125520ec5e4f20b8da0">14866</a></span><span class="preprocessor">#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) </span></div>
|
||
<div class="line"><a id="l14867" name="l14867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24055327fbeb5884d6df6de0657ae195">14867</a></span><span class="preprocessor">#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk </span></div>
|
||
<div class="line"><a id="l14868" name="l14868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ab325ca96f65ccaea0b7abb66b33702">14868</a></span><span class="preprocessor">#define USB_OTG_HCINT_ACK_Pos (5U) </span></div>
|
||
<div class="line"><a id="l14869" name="l14869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7bdbdb2fe8526b144ca06b537c5acdd0">14869</a></span><span class="preprocessor">#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) </span></div>
|
||
<div class="line"><a id="l14870" name="l14870"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c596c2aae4b88e04a122a9af560730e">14870</a></span><span class="preprocessor">#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk </span></div>
|
||
<div class="line"><a id="l14871" name="l14871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga516eea514a6024132cc66218882582dd">14871</a></span><span class="preprocessor">#define USB_OTG_HCINT_NYET_Pos (6U) </span></div>
|
||
<div class="line"><a id="l14872" name="l14872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f54751dc8abdbd65c786d2736cc2038">14872</a></span><span class="preprocessor">#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) </span></div>
|
||
<div class="line"><a id="l14873" name="l14873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cf2523fa4c59105d01a17d4caac3cbf">14873</a></span><span class="preprocessor">#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk </span></div>
|
||
<div class="line"><a id="l14874" name="l14874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga158802078f5364292b4b93103aef6b1f">14874</a></span><span class="preprocessor">#define USB_OTG_HCINT_TXERR_Pos (7U) </span></div>
|
||
<div class="line"><a id="l14875" name="l14875"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e34974081aceef1865b83e47d48d158">14875</a></span><span class="preprocessor">#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) </span></div>
|
||
<div class="line"><a id="l14876" name="l14876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaace090462b379413a409acffad4d33ca">14876</a></span><span class="preprocessor">#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk </span></div>
|
||
<div class="line"><a id="l14877" name="l14877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71fa9e120a3bfed31484cfd157f11fbc">14877</a></span><span class="preprocessor">#define USB_OTG_HCINT_BBERR_Pos (8U) </span></div>
|
||
<div class="line"><a id="l14878" name="l14878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3b7e21abc4b3e5ea1eff06eb0850441">14878</a></span><span class="preprocessor">#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) </span></div>
|
||
<div class="line"><a id="l14879" name="l14879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab72d52c361d7fc77fcca26897e5a1bd9">14879</a></span><span class="preprocessor">#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk </span></div>
|
||
<div class="line"><a id="l14880" name="l14880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa98c0c3233732702f627741e818b08ae">14880</a></span><span class="preprocessor">#define USB_OTG_HCINT_FRMOR_Pos (9U) </span></div>
|
||
<div class="line"><a id="l14881" name="l14881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7805a112e2897572bffee4c25042cc9">14881</a></span><span class="preprocessor">#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) </span></div>
|
||
<div class="line"><a id="l14882" name="l14882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69cbb7f274c4d4f82666599af8dd5428">14882</a></span><span class="preprocessor">#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk </span></div>
|
||
<div class="line"><a id="l14883" name="l14883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac35a8a3f2a57b8881cb825c07f263570">14883</a></span><span class="preprocessor">#define USB_OTG_HCINT_DTERR_Pos (10U) </span></div>
|
||
<div class="line"><a id="l14884" name="l14884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0089841c8301b5e572e29da28ef95467">14884</a></span><span class="preprocessor">#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) </span></div>
|
||
<div class="line"><a id="l14885" name="l14885"></a><span class="lineno">14885</span><span class="preprocessor">#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk </span></div>
|
||
<div class="line"><a id="l14887" name="l14887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48ad51eeb41d7d5a2708467685dc81b3">14887</a></span><span class="comment">/******************** Bit definition for USB_OTG_DIEPINT register ********************/</span></div>
|
||
<div class="line"><a id="l14888" name="l14888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2947aa5667ae63ee9bcb747ae955a0b">14888</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_XFRC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14889" name="l14889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab01f771d126cb58a8cb83841e08bec9b">14889</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) </span></div>
|
||
<div class="line"><a id="l14890" name="l14890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8e3323ea3b0713a2308da446c5d627b">14890</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk </span></div>
|
||
<div class="line"><a id="l14891" name="l14891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8a90367a919959f753ed93ac388259d">14891</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_EPDISD_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14892" name="l14892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga657c139dc16514808c516bff6e523531">14892</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) </span></div>
|
||
<div class="line"><a id="l14893" name="l14893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga928709eec43877b93798c748fdb8fe6e">14893</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk </span></div>
|
||
<div class="line"><a id="l14894" name="l14894"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3854f2057e03eb6e282a34d4d26f5093">14894</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_AHBERR_Pos (2U)</span></div>
|
||
<div class="line"><a id="l14895" name="l14895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga630e92ca04288a83f7f515cedbf01ca9">14895</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) </span></div>
|
||
<div class="line"><a id="l14896" name="l14896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86a45c7c6fc7a421171a0d6179646f85">14896</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk </span></div>
|
||
<div class="line"><a id="l14897" name="l14897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ca3db2648c05083065675eda6aaef0e">14897</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_TOC_Pos (3U) </span></div>
|
||
<div class="line"><a id="l14898" name="l14898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga253fce8bc78be1504c85d684f232dc43">14898</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) </span></div>
|
||
<div class="line"><a id="l14899" name="l14899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72bfd0fc0d049c2b27634300aba27e28">14899</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk </span></div>
|
||
<div class="line"><a id="l14900" name="l14900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad15ffda9000245db34322f4a75b31780">14900</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) </span></div>
|
||
<div class="line"><a id="l14901" name="l14901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0f91471274c3411579a7ede5a7d80f8">14901</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) </span></div>
|
||
<div class="line"><a id="l14902" name="l14902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c1240b1526225892f7518ed1e6ad3f8">14902</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk </span></div>
|
||
<div class="line"><a id="l14903" name="l14903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c72659090e081560681486217bc9e21">14903</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_INEPNM_Pos (5U)</span></div>
|
||
<div class="line"><a id="l14904" name="l14904"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb8ac53eab340e711478e5509be40e13">14904</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) </span></div>
|
||
<div class="line"><a id="l14905" name="l14905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99e5d6f548490c1a8e3c3b8f8332a6d0">14905</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk </span></div>
|
||
<div class="line"><a id="l14906" name="l14906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98ecb4c61f48a1fc073cda01f1599ad6">14906</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_INEPNE_Pos (6U) </span></div>
|
||
<div class="line"><a id="l14907" name="l14907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40fbe18a5838e768b9afca5c1695dbb3">14907</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) </span></div>
|
||
<div class="line"><a id="l14908" name="l14908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab28f246cb52201b01baa4f85be3c196">14908</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk </span></div>
|
||
<div class="line"><a id="l14909" name="l14909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadea85fa99c59be521a394f7cfeeadf25">14909</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_TXFE_Pos (7U) </span></div>
|
||
<div class="line"><a id="l14910" name="l14910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4770cce2b4f601e88fb512f6db688ec">14910</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) </span></div>
|
||
<div class="line"><a id="l14911" name="l14911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga795f1914ee10b65cd745129afc32b51f">14911</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk </span></div>
|
||
<div class="line"><a id="l14912" name="l14912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffc8a052f72319f433728b6571098ba0">14912</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) </span></div>
|
||
<div class="line"><a id="l14913" name="l14913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga934d166eae0af7663585c903567ebe2b">14913</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) </span></div>
|
||
<div class="line"><a id="l14914" name="l14914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c35d8a426e47ad0a81add3adb9adbad">14914</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk </span></div>
|
||
<div class="line"><a id="l14915" name="l14915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92124e1fe13558df5464e356658e67b2">14915</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_BNA_Pos (9U) </span></div>
|
||
<div class="line"><a id="l14916" name="l14916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22983c7c561dedc17e8688d313a50fb0">14916</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) </span></div>
|
||
<div class="line"><a id="l14917" name="l14917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45fcaff3092226af9b6df98e6f4e3c5f">14917</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk </span></div>
|
||
<div class="line"><a id="l14918" name="l14918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bbb4304aaa31dceb651eb6ebea21ca4">14918</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) </span></div>
|
||
<div class="line"><a id="l14919" name="l14919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bf74048c663e9dcc21c282a8c7be576">14919</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) </span></div>
|
||
<div class="line"><a id="l14920" name="l14920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b3a9433ebbf032f80b3a26b2b10e4c9">14920</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk </span></div>
|
||
<div class="line"><a id="l14921" name="l14921"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7902d1f040d0669ad22a9cb4a1e88bdd">14921</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_BERR_Pos (12U) </span></div>
|
||
<div class="line"><a id="l14922" name="l14922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga496c09a9096346e6141acc2464742b4c">14922</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) </span></div>
|
||
<div class="line"><a id="l14923" name="l14923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78a4751b6393d56bdd1d4e1c837c217e">14923</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk </span></div>
|
||
<div class="line"><a id="l14924" name="l14924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafb6909297147bb09786d5e20715656c">14924</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_NAK_Pos (13U) </span></div>
|
||
<div class="line"><a id="l14925" name="l14925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d91e68b693b9c8ff6fb2236093975cf">14925</a></span><span class="preprocessor">#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) </span></div>
|
||
<div class="line"><a id="l14926" name="l14926"></a><span class="lineno">14926</span><span class="preprocessor">#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk </span></div>
|
||
<div class="line"><a id="l14928" name="l14928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3a724642ee5e5c4fb980d2091e5f1b4">14928</a></span><span class="comment">/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/</span></div>
|
||
<div class="line"><a id="l14929" name="l14929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e1633eb41c92d2a0716e893d10ea404">14929</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14930" name="l14930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3647bba98a8f2c2234aadb2f9441874">14930</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) </span></div>
|
||
<div class="line"><a id="l14931" name="l14931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a9e51a34d9b5145d7c4d92a342ffb9c">14931</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk </span></div>
|
||
<div class="line"><a id="l14932" name="l14932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6cb390f8f0cf8a561f41a88a8339d7e">14932</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_CHHM_Pos (1U) </span></div>
|
||
<div class="line"><a id="l14933" name="l14933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f359b89c79fba4414e0838645f13a6b">14933</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) </span></div>
|
||
<div class="line"><a id="l14934" name="l14934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d753e4c1acd73bd24b7e4d07405d94a">14934</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk </span></div>
|
||
<div class="line"><a id="l14935" name="l14935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70c101e1a4e376d61f77fcf4f5f32bf6">14935</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) </span></div>
|
||
<div class="line"><a id="l14936" name="l14936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf281bb6b61c559e8b068ab32114572af">14936</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) </span></div>
|
||
<div class="line"><a id="l14937" name="l14937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafafbf0f454f7c9f2ca81e29897782cd7">14937</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk </span></div>
|
||
<div class="line"><a id="l14938" name="l14938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60f5b08f1a892221f86f3cb370260ef6">14938</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_STALLM_Pos (3U) </span></div>
|
||
<div class="line"><a id="l14939" name="l14939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga001d17d4511b40850fd7c338be250f08">14939</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) </span></div>
|
||
<div class="line"><a id="l14940" name="l14940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5163e183955b5eca93ec5dcaf1915a5f">14940</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk </span></div>
|
||
<div class="line"><a id="l14941" name="l14941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51cc9dd53764be5f1d2ff3d5c7241fd3">14941</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_NAKM_Pos (4U) </span></div>
|
||
<div class="line"><a id="l14942" name="l14942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51b9246da6c3a45ab697edc1cac74651">14942</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) </span></div>
|
||
<div class="line"><a id="l14943" name="l14943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67b66f3e3480ac1542b1a1f4ce8d0970">14943</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk </span></div>
|
||
<div class="line"><a id="l14944" name="l14944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga372e5e68431087f0fb3b25408ce9eec9">14944</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_ACKM_Pos (5U) </span></div>
|
||
<div class="line"><a id="l14945" name="l14945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21eb5c0fa8aafa12a725ab52f85023d1">14945</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) </span></div>
|
||
<div class="line"><a id="l14946" name="l14946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49e120401dd9574089323f30a21ce886">14946</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk </span></div>
|
||
<div class="line"><a id="l14947" name="l14947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6b099d2da095f8d31fe49ad9b9ecc90">14947</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_NYET_Pos (6U) </span></div>
|
||
<div class="line"><a id="l14948" name="l14948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga059e35d45f848183cf19399ac1e21ff5">14948</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) </span></div>
|
||
<div class="line"><a id="l14949" name="l14949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7091461a6aef6b084ca11343b1fcb8a">14949</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk </span></div>
|
||
<div class="line"><a id="l14950" name="l14950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bbe2d77401d28701eb827ac3d4cd149">14950</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) </span></div>
|
||
<div class="line"><a id="l14951" name="l14951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5322b79193b042004614b21c391d4880">14951</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) </span></div>
|
||
<div class="line"><a id="l14952" name="l14952"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabadb45319c35046abce6475a1105a3d6">14952</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk </span></div>
|
||
<div class="line"><a id="l14953" name="l14953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f9165c1fbf87679bb83efa46571b96c">14953</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) </span></div>
|
||
<div class="line"><a id="l14954" name="l14954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ae263bd38eec1c423b0a70904b5099a">14954</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) </span></div>
|
||
<div class="line"><a id="l14955" name="l14955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac75612d12f30f20d62f93d75bfe2d93a">14955</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk </span></div>
|
||
<div class="line"><a id="l14956" name="l14956"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada017fb34e00a15702d759ff174d33ff">14956</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) </span></div>
|
||
<div class="line"><a id="l14957" name="l14957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2178eb0791f9ea69122edfbd567ba48">14957</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) </span></div>
|
||
<div class="line"><a id="l14958" name="l14958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab10e5fcf2df7005211ca7b39160ee4a3">14958</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk </span></div>
|
||
<div class="line"><a id="l14959" name="l14959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cbd167749a70c575efd955503111f5c">14959</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) </span></div>
|
||
<div class="line"><a id="l14960" name="l14960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ab7105e77ce288988037b1df3406ab3">14960</a></span><span class="preprocessor">#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) </span></div>
|
||
<div class="line"><a id="l14961" name="l14961"></a><span class="lineno">14961</span><span class="preprocessor">#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk </span></div>
|
||
<div class="line"><a id="l14963" name="l14963"></a><span class="lineno">14963</span><span class="comment">/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/</span></div>
|
||
<div class="line"><a id="l14964" name="l14964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa981fab712cf94125aa509221dc26720">14964</a></span> </div>
|
||
<div class="line"><a id="l14965" name="l14965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b953496e53318844d2444b0d3982d2d">14965</a></span><span class="preprocessor">#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14966" name="l14966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5497667d259391162884390afd456f62">14966</a></span><span class="preprocessor">#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) </span></div>
|
||
<div class="line"><a id="l14967" name="l14967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga623bbf2a88cfc42a0e43ede442a58eca">14967</a></span><span class="preprocessor">#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk </span></div>
|
||
<div class="line"><a id="l14968" name="l14968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4032f4b698ca8efd7417e13471d834e0">14968</a></span><span class="preprocessor">#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) </span></div>
|
||
<div class="line"><a id="l14969" name="l14969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga664b39d163f9f2e400aa9fe2577ffc06">14969</a></span><span class="preprocessor">#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) </span></div>
|
||
<div class="line"><a id="l14970" name="l14970"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d027496fed28964c3a0ec36bfe5c03c">14970</a></span><span class="preprocessor">#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk </span></div>
|
||
<div class="line"><a id="l14971" name="l14971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b2138444cba4a94fea9ab112d212e1c">14971</a></span><span class="preprocessor">#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) </span></div>
|
||
<div class="line"><a id="l14972" name="l14972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga428da482bfd499096cff02a3d8aa6738">14972</a></span><span class="preprocessor">#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) </span></div>
|
||
<div class="line"><a id="l14973" name="l14973"></a><span class="lineno">14973</span><span class="preprocessor">#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk </span></div>
|
||
<div class="line"><a id="l14974" name="l14974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4879da0413028804a012612d7459804f">14974</a></span><span class="comment">/******************** Bit definition for USB_OTG_HCTSIZ register ********************/</span></div>
|
||
<div class="line"><a id="l14975" name="l14975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d0ecc462bdb146edeb44b1e1bf3ae08">14975</a></span><span class="preprocessor">#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14976" name="l14976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga983ec8ca0ffac66eea9219acb008fe9c">14976</a></span><span class="preprocessor">#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) </span></div>
|
||
<div class="line"><a id="l14977" name="l14977"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga386ed2405e9608d8846b344d4061eff0">14977</a></span><span class="preprocessor">#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk </span></div>
|
||
<div class="line"><a id="l14978" name="l14978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae242d5b51bdad2968cc7f59f2356195b">14978</a></span><span class="preprocessor">#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) </span></div>
|
||
<div class="line"><a id="l14979" name="l14979"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2177151366a5539b446104cb87d3059">14979</a></span><span class="preprocessor">#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) </span></div>
|
||
<div class="line"><a id="l14980" name="l14980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabd15ce174827e22c8ebd38fd41d4dcd">14980</a></span><span class="preprocessor">#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk </span></div>
|
||
<div class="line"><a id="l14981" name="l14981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63444676f787b5850bcd74a3dac24c06">14981</a></span><span class="preprocessor">#define USB_OTG_HCTSIZ_DOPING_Pos (31U) </span></div>
|
||
<div class="line"><a id="l14982" name="l14982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2dcc4677244eb50d430a62870b90c30c">14982</a></span><span class="preprocessor">#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) </span></div>
|
||
<div class="line"><a id="l14983" name="l14983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga015e511e5d6f38252ca6006e8b984bb7">14983</a></span><span class="preprocessor">#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk </span></div>
|
||
<div class="line"><a id="l14984" name="l14984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66d5133c860991521246501b6e1c055d">14984</a></span><span class="preprocessor">#define USB_OTG_HCTSIZ_DPID_Pos (29U) </span></div>
|
||
<div class="line"><a id="l14985" name="l14985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7037fb804f6e2a4a3e0c08bd3e345f18">14985</a></span><span class="preprocessor">#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) </span></div>
|
||
<div class="line"><a id="l14986" name="l14986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5509a0f869a4c7ba34f45be4b733b23">14986</a></span><span class="preprocessor">#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk </span></div>
|
||
<div class="line"><a id="l14987" name="l14987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ae95b441c770521507da1d1d4c51d18">14987</a></span><span class="preprocessor">#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) </span></div>
|
||
<div class="line"><a id="l14988" name="l14988"></a><span class="lineno">14988</span><span class="preprocessor">#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) </span></div>
|
||
<div class="line"><a id="l14990" name="l14990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f8a6b9128f9e824a0ae68346fb8fe73">14990</a></span><span class="comment">/******************** Bit definition for USB_OTG_DIEPDMA register ********************/</span></div>
|
||
<div class="line"><a id="l14991" name="l14991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17d3f62d2f03495bb28e7b65f00dbafa">14991</a></span><span class="preprocessor">#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14992" name="l14992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab177fc20463978ff09c399cb56e904bb">14992</a></span><span class="preprocessor">#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14993" name="l14993"></a><span class="lineno">14993</span><span class="preprocessor">#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk </span></div>
|
||
<div class="line"><a id="l14995" name="l14995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c69fd9913335fdca15a7dc32d1193cc">14995</a></span><span class="comment">/******************** Bit definition for USB_OTG_HCDMA register ********************/</span></div>
|
||
<div class="line"><a id="l14996" name="l14996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a98df839cd4108ef0b1b814d0f7020b">14996</a></span><span class="preprocessor">#define USB_OTG_HCDMA_DMAADDR_Pos (0U) </span></div>
|
||
<div class="line"><a id="l14997" name="l14997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2980c7f7c60bf5ff4842dc9e363ea7b">14997</a></span><span class="preprocessor">#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) </span></div>
|
||
<div class="line"><a id="l14998" name="l14998"></a><span class="lineno">14998</span><span class="preprocessor">#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk </span></div>
|
||
<div class="line"><a id="l15000" name="l15000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7bd1cf28f02f4bd52c71afee6f718e27">15000</a></span><span class="comment">/******************** Bit definition for USB_OTG_DTXFSTS register ********************/</span></div>
|
||
<div class="line"><a id="l15001" name="l15001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c1a0115d517ac979a61c81763f4ce8f">15001</a></span><span class="preprocessor">#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) </span></div>
|
||
<div class="line"><a id="l15002" name="l15002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1789e8c79b7a271a58f56cbff4bd03a">15002</a></span><span class="preprocessor">#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) </span></div>
|
||
<div class="line"><a id="l15003" name="l15003"></a><span class="lineno">15003</span><span class="preprocessor">#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk </span></div>
|
||
<div class="line"><a id="l15005" name="l15005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga129f8f89a1a613ce6f86fdb826238e16">15005</a></span><span class="comment">/******************** Bit definition for USB_OTG_DIEPTXF register ********************/</span></div>
|
||
<div class="line"><a id="l15006" name="l15006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5b86ac57a1176451f435dda801dbddb">15006</a></span><span class="preprocessor">#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) </span></div>
|
||
<div class="line"><a id="l15007" name="l15007"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga731c1eaaf15ec1b7f24e055172f7e0cf">15007</a></span><span class="preprocessor">#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) </span></div>
|
||
<div class="line"><a id="l15008" name="l15008"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c94d7d7bd4526bc8cef42790a10af14">15008</a></span><span class="preprocessor">#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk </span></div>
|
||
<div class="line"><a id="l15009" name="l15009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafccb927bfa114a368eea25db7d46c85f">15009</a></span><span class="preprocessor">#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) </span></div>
|
||
<div class="line"><a id="l15010" name="l15010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga015ec5caee27272afa335fa9d5892a40">15010</a></span><span class="preprocessor">#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) </span></div>
|
||
<div class="line"><a id="l15011" name="l15011"></a><span class="lineno">15011</span><span class="preprocessor">#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk </span></div>
|
||
<div class="line"><a id="l15013" name="l15013"></a><span class="lineno">15013</span><span class="comment">/******************** Bit definition for USB_OTG_DOEPCTL register ********************/</span></div>
|
||
<div class="line"><a id="l15014" name="l15014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef51a2cbd7e13a734ffdfded5b1e772d">15014</a></span> </div>
|
||
<div class="line"><a id="l15015" name="l15015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga103ef4c7123cb64007a1eb050d96c4b7">15015</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) </span></div>
|
||
<div class="line"><a id="l15016" name="l15016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ebce086e91feb566f223ae07d01ff57">15016</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) </span></div>
|
||
<div class="line"><a id="l15017" name="l15017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf003bdf82be8bff3e23452c7a83a9ed2">15017</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk </span></div>
|
||
<div class="line"><a id="l15018" name="l15018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31ba8e0d0b5bf08b034ba5cf27eaef4c">15018</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_USBAEP_Pos (15U) </span></div>
|
||
<div class="line"><a id="l15019" name="l15019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabed242624f140356cc793039988d89df">15019</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) </span></div>
|
||
<div class="line"><a id="l15020" name="l15020"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab721aee46a6d9aaabb0c1449155777c9">15020</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk </span></div>
|
||
<div class="line"><a id="l15021" name="l15021"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacca51b95d03a684417745d2870bc02aa">15021</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) </span></div>
|
||
<div class="line"><a id="l15022" name="l15022"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1735002d3abf233ca0cbe473da2d8fb">15022</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) </span></div>
|
||
<div class="line"><a id="l15023" name="l15023"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0a8dc23aee4dc031e4f2e85b8a09dbb">15023</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk </span></div>
|
||
<div class="line"><a id="l15024" name="l15024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1b8b770cb957bf0f4148311ddfef503">15024</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) </span></div>
|
||
<div class="line"><a id="l15025" name="l15025"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a06b55e9caa25873e734fb15cafbc51">15025</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) </span></div>
|
||
<div class="line"><a id="l15026" name="l15026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab617807c602f3dd930adca64b0c5fed1">15026</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk </span></div>
|
||
<div class="line"><a id="l15027" name="l15027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f4b73b3f5f6813412b392b8b619a1ae">15027</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) </span></div>
|
||
<div class="line"><a id="l15028" name="l15028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77ddb336230fa5a497dbb2393a180ae6">15028</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) </span></div>
|
||
<div class="line"><a id="l15029" name="l15029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3dd2ea9b1c00daf741f7ac74f32bebc3">15029</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk </span></div>
|
||
<div class="line"><a id="l15030" name="l15030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5fea8cfdb01a643000019dc830fc30f">15030</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_EPTYP_Pos (18U) </span></div>
|
||
<div class="line"><a id="l15031" name="l15031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e347921b96b8435ec2ef6cc9b3470d8">15031</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) </span></div>
|
||
<div class="line"><a id="l15032" name="l15032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48b0660b499862424b72cd59bca9226e">15032</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk </span></div>
|
||
<div class="line"><a id="l15033" name="l15033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89595201dd98cc05712d046e98c142fd">15033</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) </span></div>
|
||
<div class="line"><a id="l15034" name="l15034"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed30bbeec479174dbaeb4ec6342e7acc">15034</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) </span></div>
|
||
<div class="line"><a id="l15035" name="l15035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga592d0d387403b49dd841153e1c8ef922">15035</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_SNPM_Pos (20U) </span></div>
|
||
<div class="line"><a id="l15036" name="l15036"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14ef1fba78e67a55f665495ae7f8732e">15036</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) </span></div>
|
||
<div class="line"><a id="l15037" name="l15037"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga713faf56d7526c1671e9920f96207902">15037</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk </span></div>
|
||
<div class="line"><a id="l15038" name="l15038"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga600dc33e80274fdf8ec793bce5df9ad4">15038</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_STALL_Pos (21U) </span></div>
|
||
<div class="line"><a id="l15039" name="l15039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e6aea29335780171f8ce42aba031699">15039</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) </span></div>
|
||
<div class="line"><a id="l15040" name="l15040"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ce77ba5437dc8c547c7fe2b2851af15">15040</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk </span></div>
|
||
<div class="line"><a id="l15041" name="l15041"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92c45d7d3e789caf1b5a8967592939ae">15041</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_CNAK_Pos (26U) </span></div>
|
||
<div class="line"><a id="l15042" name="l15042"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd05c0aa7833e7467e0ff66cfa1f20cb">15042</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) </span></div>
|
||
<div class="line"><a id="l15043" name="l15043"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3f8d51a7d585bca9ab215fd90fcba33">15043</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk </span></div>
|
||
<div class="line"><a id="l15044" name="l15044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6be0f6d6ed75219981fc07465ba09298">15044</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_SNAK_Pos (27U) </span></div>
|
||
<div class="line"><a id="l15045" name="l15045"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05a3e120b2c56a13ff622b0a507f48ee">15045</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) </span></div>
|
||
<div class="line"><a id="l15046" name="l15046"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06d18faa6f215148241b0aa16a2708dc">15046</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk </span></div>
|
||
<div class="line"><a id="l15047" name="l15047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46881c1a50c0a2b48f4d107a9cdc540f">15047</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_EPDIS_Pos (30U) </span></div>
|
||
<div class="line"><a id="l15048" name="l15048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf170f97217b0a2e3f66a33a67257674e">15048</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) </span></div>
|
||
<div class="line"><a id="l15049" name="l15049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67d45681d84c4e5a4a1050291a2f1c4c">15049</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk </span></div>
|
||
<div class="line"><a id="l15050" name="l15050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga891f80e6cdbf19579db62d0214bc09b5">15050</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_EPENA_Pos (31U) </span></div>
|
||
<div class="line"><a id="l15051" name="l15051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8875f7311dfde66125b78dd715fd2d7c">15051</a></span><span class="preprocessor">#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) </span></div>
|
||
<div class="line"><a id="l15052" name="l15052"></a><span class="lineno">15052</span><span class="preprocessor">#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk </span></div>
|
||
<div class="line"><a id="l15054" name="l15054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22c42c63b15338fb0f80bc252ab8a1f9">15054</a></span><span class="comment">/******************** Bit definition for USB_OTG_DOEPINT register ********************/</span></div>
|
||
<div class="line"><a id="l15055" name="l15055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71bec204f2c5886251295d5ea7739331">15055</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_XFRC_Pos (0U) </span></div>
|
||
<div class="line"><a id="l15056" name="l15056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e51a7b1cc412e304246176c207cbcb8">15056</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) </span></div>
|
||
<div class="line"><a id="l15057" name="l15057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd8ea7d7381b81fc6ace42213c39c909">15057</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk </span></div>
|
||
<div class="line"><a id="l15058" name="l15058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2bee78f4eead58dd6e9d772d77c843d">15058</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_EPDISD_Pos (1U) </span></div>
|
||
<div class="line"><a id="l15059" name="l15059"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32e18140ad2c7902fe788947cea557d2">15059</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) </span></div>
|
||
<div class="line"><a id="l15060" name="l15060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e071c9b55a563d90d1ab1c0577390a4">15060</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk </span></div>
|
||
<div class="line"><a id="l15061" name="l15061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7dfe74336fa143f3b5a536a74ff77dcb">15061</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_AHBERR_Pos (2U)</span></div>
|
||
<div class="line"><a id="l15062" name="l15062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8957520b45ebd1ed0000d8a0c0cc9ef6">15062</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) </span></div>
|
||
<div class="line"><a id="l15063" name="l15063"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74a9a1fec27e8dd4a5a603a0d63fc104">15063</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk </span></div>
|
||
<div class="line"><a id="l15064" name="l15064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42dda03dc0034c884c0a51c1f749edfb">15064</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_STUP_Pos (3U) </span></div>
|
||
<div class="line"><a id="l15065" name="l15065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76444bdecd4d6def6c718ed1bb8e8b8c">15065</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) </span></div>
|
||
<div class="line"><a id="l15066" name="l15066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3e353ea229f93246f7fb4ef0efc90a9">15066</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk </span></div>
|
||
<div class="line"><a id="l15067" name="l15067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8a3dd1c173d5cd66abf1d5aff97f894">15067</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) </span></div>
|
||
<div class="line"><a id="l15068" name="l15068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f4c92b08606cf934de16b353053dd78">15068</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) </span></div>
|
||
<div class="line"><a id="l15069" name="l15069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cd4ee8b333b45244a950aec7b6d1756">15069</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk </span></div>
|
||
<div class="line"><a id="l15070" name="l15070"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c064a7156878cca72817277cce28cef">15070</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U) </span></div>
|
||
<div class="line"><a id="l15071" name="l15071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2451732dfee15831f09e28041dabf9ce">15071</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) </span></div>
|
||
<div class="line"><a id="l15072" name="l15072"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb2f0d32861f239d7cf694ce1f34d019">15072</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk </span></div>
|
||
<div class="line"><a id="l15073" name="l15073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab7623d1db984217c12acc54117994337">15073</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) </span></div>
|
||
<div class="line"><a id="l15074" name="l15074"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82261faaf818baade125d4de42f78fa5">15074</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) </span></div>
|
||
<div class="line"><a id="l15075" name="l15075"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92efd02af8d099a47efd3e038bada011">15075</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk </span></div>
|
||
<div class="line"><a id="l15076" name="l15076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f5870176a1b59ee2048b23087b677ae">15076</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)</span></div>
|
||
<div class="line"><a id="l15077" name="l15077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf82df64a03b0a9f6915a36a750488ac">15077</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) </span></div>
|
||
<div class="line"><a id="l15078" name="l15078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b77b085273952d4999950d52cd674c7">15078</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk </span></div>
|
||
<div class="line"><a id="l15079" name="l15079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaaa6114d1a7f5860c94bc9eb1ef1207c">15079</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_NAK_Pos (13U)</span></div>
|
||
<div class="line"><a id="l15080" name="l15080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d1b7add4ca4362bb47501b456d3bb8b">15080</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) </span></div>
|
||
<div class="line"><a id="l15081" name="l15081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3e46923e595b9049270b43fece30784">15081</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk </span></div>
|
||
<div class="line"><a id="l15082" name="l15082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ea8387720c1dd29d7c4689f4b83792f">15082</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_NYET_Pos (14U) </span></div>
|
||
<div class="line"><a id="l15083" name="l15083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf63ba909dd472b7ce95b05e8ed984ac3">15083</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) </span></div>
|
||
<div class="line"><a id="l15084" name="l15084"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05052a0dcef08b6e6acaf900e3f4b39d">15084</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk </span></div>
|
||
<div class="line"><a id="l15085" name="l15085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c90fbb29ef97f0974e4040889d12e34">15085</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)</span></div>
|
||
<div class="line"><a id="l15086" name="l15086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90d44e256af7596e109c61925dbdb6fd">15086</a></span><span class="preprocessor">#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) </span></div>
|
||
<div class="line"><a id="l15087" name="l15087"></a><span class="lineno">15087</span><span class="preprocessor">#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk </span></div>
|
||
<div class="line"><a id="l15088" name="l15088"></a><span class="lineno">15088</span><span class="comment">/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/</span></div>
|
||
<div class="line"><a id="l15089" name="l15089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fe13401b6bd1b7d884f5250ac4863bc">15089</a></span> </div>
|
||
<div class="line"><a id="l15090" name="l15090"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab5ef41f398424f0a7e6a4c7cd6010c2">15090</a></span><span class="preprocessor">#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) </span></div>
|
||
<div class="line"><a id="l15091" name="l15091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab954bdd4334a2643622e3d33fee16ad5">15091</a></span><span class="preprocessor">#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) </span></div>
|
||
<div class="line"><a id="l15092" name="l15092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4b9ba7c05cf5f15d1d68d5f01097daf">15092</a></span><span class="preprocessor">#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk </span></div>
|
||
<div class="line"><a id="l15093" name="l15093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga285281ff18968724fb73d8dc292b930b">15093</a></span><span class="preprocessor">#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U) </span></div>
|
||
<div class="line"><a id="l15094" name="l15094"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7bc1fb16d2d5b7a8d92fce5a61a038f">15094</a></span><span class="preprocessor">#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) </span></div>
|
||
<div class="line"><a id="l15095" name="l15095"></a><span class="lineno">15095</span><span class="preprocessor">#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk </span></div>
|
||
<div class="line"><a id="l15097" name="l15097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcb0c6895cd600227f3a037dfbddbbc5">15097</a></span><span class="preprocessor">#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) </span></div>
|
||
<div class="line"><a id="l15098" name="l15098"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a99a82646ef5a7a7785bec2d07334b5">15098</a></span><span class="preprocessor">#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) </span></div>
|
||
<div class="line"><a id="l15099" name="l15099"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cabae65ef4f05c5314de57beed11000">15099</a></span><span class="preprocessor">#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk </span></div>
|
||
<div class="line"><a id="l15100" name="l15100"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b109418cfad831c4f292eb86d132f0e">15100</a></span><span class="preprocessor">#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) </span></div>
|
||
<div class="line"><a id="l15101" name="l15101"></a><span class="lineno">15101</span><span class="preprocessor">#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) </span></div>
|
||
<div class="line"><a id="l15103" name="l15103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cf33736f41c6c0098df1ac2cb9dcb00">15103</a></span><span class="comment">/******************** Bit definition for PCGCCTL register ********************/</span></div>
|
||
<div class="line"><a id="l15104" name="l15104"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d4f9a974fab851fcfb0803ba5380b8d">15104</a></span><span class="preprocessor">#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) </span></div>
|
||
<div class="line"><a id="l15105" name="l15105"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77cb2d7ab53783663a7a6dd457d3ba25">15105</a></span><span class="preprocessor">#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) </span></div>
|
||
<div class="line"><a id="l15106" name="l15106"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga742b5f249d0b9b10fd616990149cf6c7">15106</a></span><span class="preprocessor">#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk </span></div>
|
||
<div class="line"><a id="l15107" name="l15107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa05b7e567009a05c0fbc460de78ece1f">15107</a></span><span class="preprocessor">#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) </span></div>
|
||
<div class="line"><a id="l15108" name="l15108"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8756280c79db9bdd546f6dabce92849">15108</a></span><span class="preprocessor">#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) </span></div>
|
||
<div class="line"><a id="l15109" name="l15109"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga370573700a56720b49363b5a166303de">15109</a></span><span class="preprocessor">#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk </span></div>
|
||
<div class="line"><a id="l15110" name="l15110"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac29bcd967dad8f66da440480b32b7b5d">15110</a></span><span class="preprocessor">#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U) </span></div>
|
||
<div class="line"><a id="l15111" name="l15111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f07a7549ecc61ab2df0775ea177df12">15111</a></span><span class="preprocessor">#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) </span></div>
|
||
<div class="line"><a id="l15112" name="l15112"></a><span class="lineno">15112</span><span class="preprocessor">#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk </span></div>
|
||
<div class="line"><a id="l15114" name="l15114"></a><span class="lineno">15114</span><span class="comment">/* Legacy define */</span></div>
|
||
<div class="line"><a id="l15115" name="l15115"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45900186e59c0e66989c65180095d603">15115</a></span><span class="comment">/******************** Bit definition for OTG register ********************/</span></div>
|
||
<div class="line"><a id="l15116" name="l15116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46419059b5b49059f5bdebe1b72722ef">15116</a></span><span class="preprocessor">#define USB_OTG_CHNUM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l15117" name="l15117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e22ae686ec18ff21f8f576178463115">15117</a></span><span class="preprocessor">#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) </span></div>
|
||
<div class="line"><a id="l15118" name="l15118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1901249182b97582cbe4a3644f31d20f">15118</a></span><span class="preprocessor">#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk </span></div>
|
||
<div class="line"><a id="l15119" name="l15119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabda64fd2296cefde4a9f304c0b5150e3">15119</a></span><span class="preprocessor">#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) </span></div>
|
||
<div class="line"><a id="l15120" name="l15120"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e852ea3f7aca27ba6cd281d1fdc5117">15120</a></span><span class="preprocessor">#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) </span></div>
|
||
<div class="line"><a id="l15121" name="l15121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga045af9896fe21c27d155de0bb98eb3bb">15121</a></span><span class="preprocessor">#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) </span></div>
|
||
<div class="line"><a id="l15122" name="l15122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace8389218deec60cbc2cc42db1ff5870">15122</a></span><span class="preprocessor">#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) </span></div>
|
||
<div class="line"><a id="l15123" name="l15123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8835a43d2c40f61caee8af97be8de8d3">15123</a></span><span class="preprocessor">#define USB_OTG_BCNT_Pos (4U) </span></div>
|
||
<div class="line"><a id="l15124" name="l15124"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85cc2bdcb428f49f2de38db43a6da61b">15124</a></span><span class="preprocessor">#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) </span></div>
|
||
<div class="line"><a id="l15125" name="l15125"></a><span class="lineno">15125</span><span class="preprocessor">#define USB_OTG_BCNT USB_OTG_BCNT_Msk </span></div>
|
||
<div class="line"><a id="l15127" name="l15127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a99858955bd807f3b3ab817ccb22dbf">15127</a></span><span class="preprocessor">#define USB_OTG_DPID_Pos (15U) </span></div>
|
||
<div class="line"><a id="l15128" name="l15128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba9fdf0a57d7a204dff9217d6b7e7a60">15128</a></span><span class="preprocessor">#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) </span></div>
|
||
<div class="line"><a id="l15129" name="l15129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cb8aeddd0bc7c194224de1c601c3aea">15129</a></span><span class="preprocessor">#define USB_OTG_DPID USB_OTG_DPID_Msk </span></div>
|
||
<div class="line"><a id="l15130" name="l15130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8822d847cc21c903bfe427927f3ebd8f">15130</a></span><span class="preprocessor">#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) </span></div>
|
||
<div class="line"><a id="l15131" name="l15131"></a><span class="lineno">15131</span><span class="preprocessor">#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) </span></div>
|
||
<div class="line"><a id="l15133" name="l15133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0bbc3a438b82f7739fdb08721163c3b">15133</a></span><span class="preprocessor">#define USB_OTG_PKTSTS_Pos (17U) </span></div>
|
||
<div class="line"><a id="l15134" name="l15134"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04a5d91a12a215c4eeeb06ce604c22e5">15134</a></span><span class="preprocessor">#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) </span></div>
|
||
<div class="line"><a id="l15135" name="l15135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77111a987b72536f21bfd7bb08594b35">15135</a></span><span class="preprocessor">#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk </span></div>
|
||
<div class="line"><a id="l15136" name="l15136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa2fb9acefebdda4d1178fd41152354a">15136</a></span><span class="preprocessor">#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) </span></div>
|
||
<div class="line"><a id="l15137" name="l15137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab280bdccc1f515e8b031ca572a40dbeb">15137</a></span><span class="preprocessor">#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) </span></div>
|
||
<div class="line"><a id="l15138" name="l15138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad095ea293b9f4a79f215502575bc3c70">15138</a></span><span class="preprocessor">#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) </span></div>
|
||
<div class="line"><a id="l15139" name="l15139"></a><span class="lineno">15139</span><span class="preprocessor">#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) </span></div>
|
||
<div class="line"><a id="l15141" name="l15141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa45e8d6116688de705fd0d55680e1a87">15141</a></span><span class="preprocessor">#define USB_OTG_EPNUM_Pos (0U) </span></div>
|
||
<div class="line"><a id="l15142" name="l15142"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91d336fd8272e4c22fc474e468b81af9">15142</a></span><span class="preprocessor">#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) </span></div>
|
||
<div class="line"><a id="l15143" name="l15143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61585b0ce43fd0b1e6b228598afc219c">15143</a></span><span class="preprocessor">#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk </span></div>
|
||
<div class="line"><a id="l15144" name="l15144"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga483d3ad09cb1f0a2c0b162c8a55ed7c6">15144</a></span><span class="preprocessor">#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) </span></div>
|
||
<div class="line"><a id="l15145" name="l15145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2438798104047b9b51f8c773d02858a">15145</a></span><span class="preprocessor">#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) </span></div>
|
||
<div class="line"><a id="l15146" name="l15146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42c2df6bfed558ca73545573166296bf">15146</a></span><span class="preprocessor">#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) </span></div>
|
||
<div class="line"><a id="l15147" name="l15147"></a><span class="lineno">15147</span><span class="preprocessor">#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) </span></div>
|
||
<div class="line"><a id="l15149" name="l15149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3dde44ba66dda008f4f22e73d6de3eb">15149</a></span><span class="preprocessor">#define USB_OTG_FRMNUM_Pos (21U) </span></div>
|
||
<div class="line"><a id="l15150" name="l15150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69105bca4abdabe5c66a1c44ae714776">15150</a></span><span class="preprocessor">#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) </span></div>
|
||
<div class="line"><a id="l15151" name="l15151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a9a2d9f4d804f38e9ee29038139498d">15151</a></span><span class="preprocessor">#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk </span></div>
|
||
<div class="line"><a id="l15152" name="l15152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d93a3bde8de46b481691a1e87b36bfd">15152</a></span><span class="preprocessor">#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) </span></div>
|
||
<div class="line"><a id="l15153" name="l15153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f8be72a63a9942462f0752d5371e619">15153</a></span><span class="preprocessor">#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) </span></div>
|
||
<div class="line"><a id="l15154" name="l15154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b50095fee4cb94be4d1d02aadd3964e">15154</a></span><span class="preprocessor">#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) </span></div>
|
||
<div class="line"><a id="l15155" name="l15155"></a><span class="lineno">15155</span><span class="preprocessor">#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) </span></div>
|
||
<div class="foldopen" id="foldopen15168" data-start="" data-end="">
|
||
<div class="line"><a id="l15168" name="l15168"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga2204b62b378bcf08b3b9006c184c7c23">15168</a></span><span class="comment">/******************************* ADC Instances ********************************/</span></div>
|
||
<div class="line"><a id="l15169" name="l15169"></a><span class="lineno">15169</span><span class="preprocessor">#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \</span></div>
|
||
<div class="line"><a id="l15170" name="l15170"></a><span class="lineno">15170</span><span class="preprocessor"> ((INSTANCE) == ADC2) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15171" name="l15171"></a><span class="lineno">15171</span><span class="preprocessor"> ((INSTANCE) == ADC3))</span></div>
|
||
<div class="line"><a id="l15172" name="l15172"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga26b4e299ac54d09082645a70f889c143">15172</a></span> </div>
|
||
<div class="line"><a id="l15173" name="l15173"></a><span class="lineno">15173</span><span class="preprocessor">#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)</span></div>
|
||
<div class="line"><a id="l15174" name="l15174"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gad8a5831c786b6b265531b890a194cbe2">15174</a></span> </div>
|
||
<div class="line"><a id="l15175" name="l15175"></a><span class="lineno">15175</span><span class="preprocessor">#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)</span></div>
|
||
<div class="line"><a id="l15176" name="l15176"></a><span class="lineno">15176</span> </div>
|
||
<div class="foldopen" id="foldopen15177" data-start="" data-end="">
|
||
<div class="line"><a id="l15177" name="l15177"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga974dd363bcb2a5f48ec032509fd4ece3">15177</a></span><span class="comment">/******************************* CAN Instances ********************************/</span></div>
|
||
<div class="line"><a id="l15178" name="l15178"></a><span class="lineno">15178</span><span class="preprocessor">#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15179" name="l15179"></a><span class="lineno">15179</span><span class="preprocessor"> ((INSTANCE) == CAN2))</span></div>
|
||
<div class="line"><a id="l15180" name="l15180"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gaa514941a7f02f65eb27450c05e4e8dd1">15180</a></span><span class="comment">/******************************* CRC Instances ********************************/</span></div>
|
||
<div class="line"><a id="l15181" name="l15181"></a><span class="lineno">15181</span><span class="preprocessor">#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)</span></div>
|
||
<div class="line"><a id="l15182" name="l15182"></a><span class="lineno">15182</span> </div>
|
||
<div class="line"><a id="l15183" name="l15183"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga94426b97cc5f1644d67f291cbcdba6d8">15183</a></span><span class="comment">/******************************* DAC Instances ********************************/</span></div>
|
||
<div class="line"><a id="l15184" name="l15184"></a><span class="lineno">15184</span><span class="preprocessor">#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)</span></div>
|
||
<div class="line"><a id="l15185" name="l15185"></a><span class="lineno">15185</span> </div>
|
||
<div class="line"><a id="l15186" name="l15186"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gaca27f42a2f7dd5715c74884bd9af310d">15186</a></span><span class="comment">/******************************* DCMI Instances *******************************/</span></div>
|
||
<div class="line"><a id="l15187" name="l15187"></a><span class="lineno">15187</span><span class="preprocessor">#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)</span></div>
|
||
<div class="line"><a id="l15188" name="l15188"></a><span class="lineno">15188</span> </div>
|
||
<div class="foldopen" id="foldopen15189" data-start="" data-end="">
|
||
<div class="line"><a id="l15189" name="l15189"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gafd60def465da605e33644e28072aee9c">15189</a></span><span class="comment">/******************************** DMA Instances *******************************/</span></div>
|
||
<div class="line"><a id="l15190" name="l15190"></a><span class="lineno">15190</span><span class="preprocessor">#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \</span></div>
|
||
<div class="line"><a id="l15191" name="l15191"></a><span class="lineno">15191</span><span class="preprocessor"> ((INSTANCE) == DMA1_Stream1) || \</span></div>
|
||
<div class="line"><a id="l15192" name="l15192"></a><span class="lineno">15192</span><span class="preprocessor"> ((INSTANCE) == DMA1_Stream2) || \</span></div>
|
||
<div class="line"><a id="l15193" name="l15193"></a><span class="lineno">15193</span><span class="preprocessor"> ((INSTANCE) == DMA1_Stream3) || \</span></div>
|
||
<div class="line"><a id="l15194" name="l15194"></a><span class="lineno">15194</span><span class="preprocessor"> ((INSTANCE) == DMA1_Stream4) || \</span></div>
|
||
<div class="line"><a id="l15195" name="l15195"></a><span class="lineno">15195</span><span class="preprocessor"> ((INSTANCE) == DMA1_Stream5) || \</span></div>
|
||
<div class="line"><a id="l15196" name="l15196"></a><span class="lineno">15196</span><span class="preprocessor"> ((INSTANCE) == DMA1_Stream6) || \</span></div>
|
||
<div class="line"><a id="l15197" name="l15197"></a><span class="lineno">15197</span><span class="preprocessor"> ((INSTANCE) == DMA1_Stream7) || \</span></div>
|
||
<div class="line"><a id="l15198" name="l15198"></a><span class="lineno">15198</span><span class="preprocessor"> ((INSTANCE) == DMA2_Stream0) || \</span></div>
|
||
<div class="line"><a id="l15199" name="l15199"></a><span class="lineno">15199</span><span class="preprocessor"> ((INSTANCE) == DMA2_Stream1) || \</span></div>
|
||
<div class="line"><a id="l15200" name="l15200"></a><span class="lineno">15200</span><span class="preprocessor"> ((INSTANCE) == DMA2_Stream2) || \</span></div>
|
||
<div class="line"><a id="l15201" name="l15201"></a><span class="lineno">15201</span><span class="preprocessor"> ((INSTANCE) == DMA2_Stream3) || \</span></div>
|
||
<div class="line"><a id="l15202" name="l15202"></a><span class="lineno">15202</span><span class="preprocessor"> ((INSTANCE) == DMA2_Stream4) || \</span></div>
|
||
<div class="line"><a id="l15203" name="l15203"></a><span class="lineno">15203</span><span class="preprocessor"> ((INSTANCE) == DMA2_Stream5) || \</span></div>
|
||
<div class="line"><a id="l15204" name="l15204"></a><span class="lineno">15204</span><span class="preprocessor"> ((INSTANCE) == DMA2_Stream6) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15205" name="l15205"></a><span class="lineno">15205</span><span class="preprocessor"> ((INSTANCE) == DMA2_Stream7))</span></div>
|
||
<div class="line"><a id="l15206" name="l15206"></a><span class="lineno">15206</span> </div>
|
||
<div class="foldopen" id="foldopen15207" data-start="" data-end="">
|
||
<div class="line"><a id="l15207" name="l15207"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga783626dd2431afebea836a102e318957">15207</a></span><span class="comment">/******************************* GPIO Instances *******************************/</span></div>
|
||
<div class="line"><a id="l15208" name="l15208"></a><span class="lineno">15208</span><span class="preprocessor">#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \</span></div>
|
||
<div class="line"><a id="l15209" name="l15209"></a><span class="lineno">15209</span><span class="preprocessor"> ((INSTANCE) == GPIOB) || \</span></div>
|
||
<div class="line"><a id="l15210" name="l15210"></a><span class="lineno">15210</span><span class="preprocessor"> ((INSTANCE) == GPIOC) || \</span></div>
|
||
<div class="line"><a id="l15211" name="l15211"></a><span class="lineno">15211</span><span class="preprocessor"> ((INSTANCE) == GPIOD) || \</span></div>
|
||
<div class="line"><a id="l15212" name="l15212"></a><span class="lineno">15212</span><span class="preprocessor"> ((INSTANCE) == GPIOE) || \</span></div>
|
||
<div class="line"><a id="l15213" name="l15213"></a><span class="lineno">15213</span><span class="preprocessor"> ((INSTANCE) == GPIOF) || \</span></div>
|
||
<div class="line"><a id="l15214" name="l15214"></a><span class="lineno">15214</span><span class="preprocessor"> ((INSTANCE) == GPIOG) || \</span></div>
|
||
<div class="line"><a id="l15215" name="l15215"></a><span class="lineno">15215</span><span class="preprocessor"> ((INSTANCE) == GPIOH) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15216" name="l15216"></a><span class="lineno">15216</span><span class="preprocessor"> ((INSTANCE) == GPIOI))</span></div>
|
||
<div class="line"><a id="l15217" name="l15217"></a><span class="lineno">15217</span> </div>
|
||
<div class="foldopen" id="foldopen15218" data-start="" data-end="">
|
||
<div class="line"><a id="l15218" name="l15218"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gacdf0149a4e8c41a6814c13613c38a6b2">15218</a></span><span class="comment">/******************************** I2C Instances *******************************/</span></div>
|
||
<div class="line"><a id="l15219" name="l15219"></a><span class="lineno">15219</span><span class="preprocessor">#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \</span></div>
|
||
<div class="line"><a id="l15220" name="l15220"></a><span class="lineno">15220</span><span class="preprocessor"> ((INSTANCE) == I2C2) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15221" name="l15221"></a><span class="lineno">15221</span><span class="preprocessor"> ((INSTANCE) == I2C3))</span></div>
|
||
<div class="line"><a id="l15222" name="l15222"></a><span class="lineno">15222</span> </div>
|
||
<div class="line"><a id="l15223" name="l15223"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga85b79d63f4643c0de9a7519290a0eceb">15223</a></span><span class="comment">/******************************* SMBUS Instances ******************************/</span></div>
|
||
<div class="line"><a id="l15224" name="l15224"></a><span class="lineno">15224</span><span class="preprocessor">#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE</span></div>
|
||
<div class="line"><a id="l15225" name="l15225"></a><span class="lineno">15225</span> </div>
|
||
<div class="line"><a id="l15226" name="l15226"></a><span class="lineno">15226</span><span class="comment">/******************************** I2S Instances *******************************/</span></div>
|
||
<div class="foldopen" id="foldopen15227" data-start="" data-end="">
|
||
<div class="line"><a id="l15227" name="l15227"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga0b35685911e3c7a38ee89e5cdc5a82fa">15227</a></span> </div>
|
||
<div class="line"><a id="l15228" name="l15228"></a><span class="lineno">15228</span><span class="preprocessor">#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15229" name="l15229"></a><span class="lineno">15229</span><span class="preprocessor"> ((INSTANCE) == SPI3))</span></div>
|
||
<div class="line"><a id="l15230" name="l15230"></a><span class="lineno">15230</span> </div>
|
||
<div class="foldopen" id="foldopen15231" data-start="" data-end="">
|
||
<div class="line"><a id="l15231" name="l15231"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga2f0d621c72fe4e5039562472460e29ab">15231</a></span><span class="comment">/*************************** I2S Extended Instances ***************************/</span></div>
|
||
<div class="line"><a id="l15232" name="l15232"></a><span class="lineno">15232</span><span class="preprocessor">#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15233" name="l15233"></a><span class="lineno">15233</span><span class="preprocessor"> ((INSTANCE) == I2S3ext))</span></div>
|
||
<div class="line"><a id="l15234" name="l15234"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga839b019f23ec240da66dd50a21ab5025">15234</a></span><span class="comment">/* Legacy Defines */</span></div>
|
||
<div class="line"><a id="l15235" name="l15235"></a><span class="lineno">15235</span><span class="preprocessor">#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE</span></div>
|
||
<div class="line"><a id="l15236" name="l15236"></a><span class="lineno">15236</span> </div>
|
||
<div class="line"><a id="l15237" name="l15237"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga7369db258c1b8931b427262d0673751f">15237</a></span><span class="comment">/******************************* RNG Instances ********************************/</span></div>
|
||
<div class="line"><a id="l15238" name="l15238"></a><span class="lineno">15238</span><span class="preprocessor">#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)</span></div>
|
||
<div class="line"><a id="l15239" name="l15239"></a><span class="lineno">15239</span> </div>
|
||
<div class="line"><a id="l15240" name="l15240"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gab4230e8bd4d88adc4250f041d67375ce">15240</a></span><span class="comment">/****************************** RTC Instances *********************************/</span></div>
|
||
<div class="line"><a id="l15241" name="l15241"></a><span class="lineno">15241</span><span class="preprocessor">#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)</span></div>
|
||
<div class="line"><a id="l15242" name="l15242"></a><span class="lineno">15242</span> </div>
|
||
<div class="line"><a id="l15243" name="l15243"></a><span class="lineno">15243</span> </div>
|
||
<div class="foldopen" id="foldopen15244" data-start="" data-end="">
|
||
<div class="line"><a id="l15244" name="l15244"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga59c7619a86c03df3ebeb4bd8aaef982c">15244</a></span><span class="comment">/******************************** SPI Instances *******************************/</span></div>
|
||
<div class="line"><a id="l15245" name="l15245"></a><span class="lineno">15245</span><span class="preprocessor">#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \</span></div>
|
||
<div class="line"><a id="l15246" name="l15246"></a><span class="lineno">15246</span><span class="preprocessor"> ((INSTANCE) == SPI2) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15247" name="l15247"></a><span class="lineno">15247</span><span class="preprocessor"> ((INSTANCE) == SPI3))</span></div>
|
||
<div class="line"><a id="l15248" name="l15248"></a><span class="lineno">15248</span> </div>
|
||
<div class="line"><a id="l15249" name="l15249"></a><span class="lineno">15249</span> </div>
|
||
<div class="foldopen" id="foldopen15250" data-start="" data-end="">
|
||
<div class="line"><a id="l15250" name="l15250"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gaba506eb03409b21388d7c5a6401a4f98">15250</a></span><span class="comment">/****************** TIM Instances : All supported instances *******************/</span></div>
|
||
<div class="line"><a id="l15251" name="l15251"></a><span class="lineno">15251</span><span class="preprocessor">#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15252" name="l15252"></a><span class="lineno">15252</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15253" name="l15253"></a><span class="lineno">15253</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15254" name="l15254"></a><span class="lineno">15254</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15255" name="l15255"></a><span class="lineno">15255</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
<div class="line"><a id="l15256" name="l15256"></a><span class="lineno">15256</span><span class="preprocessor"> ((INSTANCE) == TIM6) || \</span></div>
|
||
<div class="line"><a id="l15257" name="l15257"></a><span class="lineno">15257</span><span class="preprocessor"> ((INSTANCE) == TIM7) || \</span></div>
|
||
<div class="line"><a id="l15258" name="l15258"></a><span class="lineno">15258</span><span class="preprocessor"> ((INSTANCE) == TIM8) || \</span></div>
|
||
<div class="line"><a id="l15259" name="l15259"></a><span class="lineno">15259</span><span class="preprocessor"> ((INSTANCE) == TIM9) || \</span></div>
|
||
<div class="line"><a id="l15260" name="l15260"></a><span class="lineno">15260</span><span class="preprocessor"> ((INSTANCE) == TIM10)|| \</span></div>
|
||
<div class="line"><a id="l15261" name="l15261"></a><span class="lineno">15261</span><span class="preprocessor"> ((INSTANCE) == TIM11)|| \</span></div>
|
||
<div class="line"><a id="l15262" name="l15262"></a><span class="lineno">15262</span><span class="preprocessor"> ((INSTANCE) == TIM12)|| \</span></div>
|
||
<div class="line"><a id="l15263" name="l15263"></a><span class="lineno">15263</span><span class="preprocessor"> ((INSTANCE) == TIM13)|| \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15264" name="l15264"></a><span class="lineno">15264</span><span class="preprocessor"> ((INSTANCE) == TIM14))</span></div>
|
||
<div class="line"><a id="l15265" name="l15265"></a><span class="lineno">15265</span> </div>
|
||
<div class="foldopen" id="foldopen15266" data-start="" data-end="">
|
||
<div class="line"><a id="l15266" name="l15266"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga0c02efc77b1bfb640d7f6593f58ad464">15266</a></span><span class="comment">/************* TIM Instances : at least 1 capture/compare channel *************/</span></div>
|
||
<div class="line"><a id="l15267" name="l15267"></a><span class="lineno">15267</span><span class="preprocessor">#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15268" name="l15268"></a><span class="lineno">15268</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15269" name="l15269"></a><span class="lineno">15269</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15270" name="l15270"></a><span class="lineno">15270</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15271" name="l15271"></a><span class="lineno">15271</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
<div class="line"><a id="l15272" name="l15272"></a><span class="lineno">15272</span><span class="preprocessor"> ((INSTANCE) == TIM8) || \</span></div>
|
||
<div class="line"><a id="l15273" name="l15273"></a><span class="lineno">15273</span><span class="preprocessor"> ((INSTANCE) == TIM9) || \</span></div>
|
||
<div class="line"><a id="l15274" name="l15274"></a><span class="lineno">15274</span><span class="preprocessor"> ((INSTANCE) == TIM10) || \</span></div>
|
||
<div class="line"><a id="l15275" name="l15275"></a><span class="lineno">15275</span><span class="preprocessor"> ((INSTANCE) == TIM11) || \</span></div>
|
||
<div class="line"><a id="l15276" name="l15276"></a><span class="lineno">15276</span><span class="preprocessor"> ((INSTANCE) == TIM12) || \</span></div>
|
||
<div class="line"><a id="l15277" name="l15277"></a><span class="lineno">15277</span><span class="preprocessor"> ((INSTANCE) == TIM13) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15278" name="l15278"></a><span class="lineno">15278</span><span class="preprocessor"> ((INSTANCE) == TIM14))</span></div>
|
||
<div class="line"><a id="l15279" name="l15279"></a><span class="lineno">15279</span> </div>
|
||
<div class="foldopen" id="foldopen15280" data-start="" data-end="">
|
||
<div class="line"><a id="l15280" name="l15280"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga6ef84d278cf917c7e420b94687b39c7c">15280</a></span><span class="comment">/************ TIM Instances : at least 2 capture/compare channels *************/</span></div>
|
||
<div class="line"><a id="l15281" name="l15281"></a><span class="lineno">15281</span><span class="preprocessor">#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15282" name="l15282"></a><span class="lineno">15282</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15283" name="l15283"></a><span class="lineno">15283</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15284" name="l15284"></a><span class="lineno">15284</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15285" name="l15285"></a><span class="lineno">15285</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
<div class="line"><a id="l15286" name="l15286"></a><span class="lineno">15286</span><span class="preprocessor"> ((INSTANCE) == TIM8) || \</span></div>
|
||
<div class="line"><a id="l15287" name="l15287"></a><span class="lineno">15287</span><span class="preprocessor"> ((INSTANCE) == TIM9) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15288" name="l15288"></a><span class="lineno">15288</span><span class="preprocessor"> ((INSTANCE) == TIM12)) </span></div>
|
||
<div class="line"><a id="l15289" name="l15289"></a><span class="lineno">15289</span> </div>
|
||
<div class="foldopen" id="foldopen15290" data-start="" data-end="">
|
||
<div class="line"><a id="l15290" name="l15290"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga0c37cb8f925fd43622cce7a4c00fd95e">15290</a></span><span class="comment">/************ TIM Instances : at least 3 capture/compare channels *************/</span></div>
|
||
<div class="line"><a id="l15291" name="l15291"></a><span class="lineno">15291</span><span class="preprocessor">#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15292" name="l15292"></a><span class="lineno">15292</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15293" name="l15293"></a><span class="lineno">15293</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15294" name="l15294"></a><span class="lineno">15294</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15295" name="l15295"></a><span class="lineno">15295</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15296" name="l15296"></a><span class="lineno">15296</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15297" name="l15297"></a><span class="lineno">15297</span> </div>
|
||
<div class="foldopen" id="foldopen15298" data-start="" data-end="">
|
||
<div class="line"><a id="l15298" name="l15298"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gae72b7182a73d81c33196265b31091c07">15298</a></span><span class="comment">/************ TIM Instances : at least 4 capture/compare channels *************/</span></div>
|
||
<div class="line"><a id="l15299" name="l15299"></a><span class="lineno">15299</span><span class="preprocessor">#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15300" name="l15300"></a><span class="lineno">15300</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15301" name="l15301"></a><span class="lineno">15301</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15302" name="l15302"></a><span class="lineno">15302</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15303" name="l15303"></a><span class="lineno">15303</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15304" name="l15304"></a><span class="lineno">15304</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15305" name="l15305"></a><span class="lineno">15305</span> </div>
|
||
<div class="foldopen" id="foldopen15306" data-start="" data-end="">
|
||
<div class="line"><a id="l15306" name="l15306"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga7e85353dbe9dc9d80ad06f0b935c12e1">15306</a></span><span class="comment">/******************** TIM Instances : Advanced-control timers *****************/</span></div>
|
||
<div class="line"><a id="l15307" name="l15307"></a><span class="lineno">15307</span><span class="preprocessor">#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15308" name="l15308"></a><span class="lineno">15308</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15309" name="l15309"></a><span class="lineno">15309</span> </div>
|
||
<div class="foldopen" id="foldopen15310" data-start="" data-end="">
|
||
<div class="line"><a id="l15310" name="l15310"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga6e06388143bb7bb111c78a3686dd753a">15310</a></span><span class="comment">/******************* TIM Instances : Timer input XOR function *****************/</span></div>
|
||
<div class="line"><a id="l15311" name="l15311"></a><span class="lineno">15311</span><span class="preprocessor">#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15312" name="l15312"></a><span class="lineno">15312</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15313" name="l15313"></a><span class="lineno">15313</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15314" name="l15314"></a><span class="lineno">15314</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15315" name="l15315"></a><span class="lineno">15315</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15316" name="l15316"></a><span class="lineno">15316</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15317" name="l15317"></a><span class="lineno">15317</span> </div>
|
||
<div class="foldopen" id="foldopen15318" data-start="" data-end="">
|
||
<div class="line"><a id="l15318" name="l15318"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gad51d77b3bcc12a3a5c308d727b561371">15318</a></span><span class="comment">/****************** TIM Instances : DMA requests generation (UDE) *************/</span></div>
|
||
<div class="line"><a id="l15319" name="l15319"></a><span class="lineno">15319</span><span class="preprocessor">#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15320" name="l15320"></a><span class="lineno">15320</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15321" name="l15321"></a><span class="lineno">15321</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15322" name="l15322"></a><span class="lineno">15322</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15323" name="l15323"></a><span class="lineno">15323</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
<div class="line"><a id="l15324" name="l15324"></a><span class="lineno">15324</span><span class="preprocessor"> ((INSTANCE) == TIM6) || \</span></div>
|
||
<div class="line"><a id="l15325" name="l15325"></a><span class="lineno">15325</span><span class="preprocessor"> ((INSTANCE) == TIM7) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15326" name="l15326"></a><span class="lineno">15326</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15327" name="l15327"></a><span class="lineno">15327</span> </div>
|
||
<div class="foldopen" id="foldopen15328" data-start="" data-end="">
|
||
<div class="line"><a id="l15328" name="l15328"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gad80a186286ce3daa92249a8d52111aaf">15328</a></span><span class="comment">/************ TIM Instances : DMA requests generation (CCxDE) *****************/</span></div>
|
||
<div class="line"><a id="l15329" name="l15329"></a><span class="lineno">15329</span><span class="preprocessor">#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15330" name="l15330"></a><span class="lineno">15330</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15331" name="l15331"></a><span class="lineno">15331</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15332" name="l15332"></a><span class="lineno">15332</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15333" name="l15333"></a><span class="lineno">15333</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15334" name="l15334"></a><span class="lineno">15334</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15335" name="l15335"></a><span class="lineno">15335</span> </div>
|
||
<div class="foldopen" id="foldopen15336" data-start="" data-end="">
|
||
<div class="line"><a id="l15336" name="l15336"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga8111ef18a809cd882ef327399fdbfc8f">15336</a></span><span class="comment">/************ TIM Instances : DMA requests generation (COMDE) *****************/</span></div>
|
||
<div class="line"><a id="l15337" name="l15337"></a><span class="lineno">15337</span><span class="preprocessor">#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15338" name="l15338"></a><span class="lineno">15338</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15339" name="l15339"></a><span class="lineno">15339</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15340" name="l15340"></a><span class="lineno">15340</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15341" name="l15341"></a><span class="lineno">15341</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15342" name="l15342"></a><span class="lineno">15342</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15343" name="l15343"></a><span class="lineno">15343</span> </div>
|
||
<div class="foldopen" id="foldopen15344" data-start="" data-end="">
|
||
<div class="line"><a id="l15344" name="l15344"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga1ed43d4e9823446a1b9d43afc452f42e">15344</a></span><span class="comment">/******************** TIM Instances : DMA burst feature ***********************/</span></div>
|
||
<div class="line"><a id="l15345" name="l15345"></a><span class="lineno">15345</span><span class="preprocessor">#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15346" name="l15346"></a><span class="lineno">15346</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15347" name="l15347"></a><span class="lineno">15347</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15348" name="l15348"></a><span class="lineno">15348</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15349" name="l15349"></a><span class="lineno">15349</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15350" name="l15350"></a><span class="lineno">15350</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15351" name="l15351"></a><span class="lineno">15351</span> </div>
|
||
<div class="foldopen" id="foldopen15352" data-start="" data-end="">
|
||
<div class="line"><a id="l15352" name="l15352"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga98104b1522d066b0c20205ca179d0eba">15352</a></span><span class="comment">/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/</span></div>
|
||
<div class="line"><a id="l15353" name="l15353"></a><span class="lineno">15353</span><span class="preprocessor">#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15354" name="l15354"></a><span class="lineno">15354</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15355" name="l15355"></a><span class="lineno">15355</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15356" name="l15356"></a><span class="lineno">15356</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15357" name="l15357"></a><span class="lineno">15357</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
<div class="line"><a id="l15358" name="l15358"></a><span class="lineno">15358</span><span class="preprocessor"> ((INSTANCE) == TIM6) || \</span></div>
|
||
<div class="line"><a id="l15359" name="l15359"></a><span class="lineno">15359</span><span class="preprocessor"> ((INSTANCE) == TIM7) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15360" name="l15360"></a><span class="lineno">15360</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15361" name="l15361"></a><span class="lineno">15361</span> </div>
|
||
<div class="foldopen" id="foldopen15362" data-start="" data-end="">
|
||
<div class="line"><a id="l15362" name="l15362"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga3ba7d4187dba8dfb4ffd610312e8af14">15362</a></span><span class="comment">/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/</span></div>
|
||
<div class="line"><a id="l15363" name="l15363"></a><span class="lineno">15363</span><span class="preprocessor">#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15364" name="l15364"></a><span class="lineno">15364</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15365" name="l15365"></a><span class="lineno">15365</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15366" name="l15366"></a><span class="lineno">15366</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15367" name="l15367"></a><span class="lineno">15367</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
<div class="line"><a id="l15368" name="l15368"></a><span class="lineno">15368</span><span class="preprocessor"> ((INSTANCE) == TIM8) || \</span></div>
|
||
<div class="line"><a id="l15369" name="l15369"></a><span class="lineno">15369</span><span class="preprocessor"> ((INSTANCE) == TIM9) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15370" name="l15370"></a><span class="lineno">15370</span><span class="preprocessor"> ((INSTANCE) == TIM12))</span></div>
|
||
<div class="foldopen" id="foldopen15371" data-start="" data-end="">
|
||
<div class="line"><a id="l15371" name="l15371"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gac41867bf288927ff8ff10a85e67a591b">15371</a></span><span class="comment">/********************** TIM Instances : 32 bit Counter ************************/</span></div>
|
||
<div class="line"><a id="l15372" name="l15372"></a><span class="lineno">15372</span><span class="preprocessor">#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15373" name="l15373"></a><span class="lineno">15373</span><span class="preprocessor"> ((INSTANCE) == TIM5))</span></div>
|
||
<div class="line"><a id="l15374" name="l15374"></a><span class="lineno">15374</span> </div>
|
||
<div class="foldopen" id="foldopen15375" data-start="" data-end="">
|
||
<div class="line"><a id="l15375" name="l15375"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gac71942c3817f1a893ef84fefe69496b7">15375</a></span><span class="comment">/***************** TIM Instances : external trigger input available ************/</span></div>
|
||
<div class="line"><a id="l15376" name="l15376"></a><span class="lineno">15376</span><span class="preprocessor">#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15377" name="l15377"></a><span class="lineno">15377</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15378" name="l15378"></a><span class="lineno">15378</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15379" name="l15379"></a><span class="lineno">15379</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15380" name="l15380"></a><span class="lineno">15380</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15381" name="l15381"></a><span class="lineno">15381</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15382" name="l15382"></a><span class="lineno">15382</span> </div>
|
||
<div class="foldopen" id="foldopen15383" data-start="" data-end="">
|
||
<div class="line"><a id="l15383" name="l15383"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga6bb03cf116b07bfe1bd527f8ab61a7f9">15383</a></span><span class="comment">/****************** TIM Instances : remapping capability **********************/</span></div>
|
||
<div class="line"><a id="l15384" name="l15384"></a><span class="lineno">15384</span><span class="preprocessor">#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15385" name="l15385"></a><span class="lineno">15385</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15386" name="l15386"></a><span class="lineno">15386</span><span class="preprocessor"> ((INSTANCE) == TIM11))</span></div>
|
||
<div class="line"><a id="l15387" name="l15387"></a><span class="lineno">15387</span> </div>
|
||
<div class="foldopen" id="foldopen15388" data-start="" data-end="">
|
||
<div class="line"><a id="l15388" name="l15388"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga6517a51ea79512a42bc53c718a77f18e">15388</a></span><span class="comment">/******************* TIM Instances : output(s) available **********************/</span></div>
|
||
<div class="line"><a id="l15389" name="l15389"></a><span class="lineno">15389</span><span class="preprocessor">#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \</span></div>
|
||
<div class="line"><a id="l15390" name="l15390"></a><span class="lineno">15390</span><span class="preprocessor"> ((((INSTANCE) == TIM1) && \</span></div>
|
||
<div class="line"><a id="l15391" name="l15391"></a><span class="lineno">15391</span><span class="preprocessor"> (((CHANNEL) == TIM_CHANNEL_1) || \</span></div>
|
||
<div class="line"><a id="l15392" name="l15392"></a><span class="lineno">15392</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_2) || \</span></div>
|
||
<div class="line"><a id="l15393" name="l15393"></a><span class="lineno">15393</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_3) || \</span></div>
|
||
<div class="line"><a id="l15394" name="l15394"></a><span class="lineno">15394</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_4))) \</span></div>
|
||
<div class="line"><a id="l15395" name="l15395"></a><span class="lineno">15395</span><span class="preprocessor"> || \</span></div>
|
||
<div class="line"><a id="l15396" name="l15396"></a><span class="lineno">15396</span><span class="preprocessor"> (((INSTANCE) == TIM2) && \</span></div>
|
||
<div class="line"><a id="l15397" name="l15397"></a><span class="lineno">15397</span><span class="preprocessor"> (((CHANNEL) == TIM_CHANNEL_1) || \</span></div>
|
||
<div class="line"><a id="l15398" name="l15398"></a><span class="lineno">15398</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_2) || \</span></div>
|
||
<div class="line"><a id="l15399" name="l15399"></a><span class="lineno">15399</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_3) || \</span></div>
|
||
<div class="line"><a id="l15400" name="l15400"></a><span class="lineno">15400</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_4))) \</span></div>
|
||
<div class="line"><a id="l15401" name="l15401"></a><span class="lineno">15401</span><span class="preprocessor"> || \</span></div>
|
||
<div class="line"><a id="l15402" name="l15402"></a><span class="lineno">15402</span><span class="preprocessor"> (((INSTANCE) == TIM3) && \</span></div>
|
||
<div class="line"><a id="l15403" name="l15403"></a><span class="lineno">15403</span><span class="preprocessor"> (((CHANNEL) == TIM_CHANNEL_1) || \</span></div>
|
||
<div class="line"><a id="l15404" name="l15404"></a><span class="lineno">15404</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_2) || \</span></div>
|
||
<div class="line"><a id="l15405" name="l15405"></a><span class="lineno">15405</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_3) || \</span></div>
|
||
<div class="line"><a id="l15406" name="l15406"></a><span class="lineno">15406</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_4))) \</span></div>
|
||
<div class="line"><a id="l15407" name="l15407"></a><span class="lineno">15407</span><span class="preprocessor"> || \</span></div>
|
||
<div class="line"><a id="l15408" name="l15408"></a><span class="lineno">15408</span><span class="preprocessor"> (((INSTANCE) == TIM4) && \</span></div>
|
||
<div class="line"><a id="l15409" name="l15409"></a><span class="lineno">15409</span><span class="preprocessor"> (((CHANNEL) == TIM_CHANNEL_1) || \</span></div>
|
||
<div class="line"><a id="l15410" name="l15410"></a><span class="lineno">15410</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_2) || \</span></div>
|
||
<div class="line"><a id="l15411" name="l15411"></a><span class="lineno">15411</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_3) || \</span></div>
|
||
<div class="line"><a id="l15412" name="l15412"></a><span class="lineno">15412</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_4))) \</span></div>
|
||
<div class="line"><a id="l15413" name="l15413"></a><span class="lineno">15413</span><span class="preprocessor"> || \</span></div>
|
||
<div class="line"><a id="l15414" name="l15414"></a><span class="lineno">15414</span><span class="preprocessor"> (((INSTANCE) == TIM5) && \</span></div>
|
||
<div class="line"><a id="l15415" name="l15415"></a><span class="lineno">15415</span><span class="preprocessor"> (((CHANNEL) == TIM_CHANNEL_1) || \</span></div>
|
||
<div class="line"><a id="l15416" name="l15416"></a><span class="lineno">15416</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_2) || \</span></div>
|
||
<div class="line"><a id="l15417" name="l15417"></a><span class="lineno">15417</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_3) || \</span></div>
|
||
<div class="line"><a id="l15418" name="l15418"></a><span class="lineno">15418</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_4))) \</span></div>
|
||
<div class="line"><a id="l15419" name="l15419"></a><span class="lineno">15419</span><span class="preprocessor"> || \</span></div>
|
||
<div class="line"><a id="l15420" name="l15420"></a><span class="lineno">15420</span><span class="preprocessor"> (((INSTANCE) == TIM8) && \</span></div>
|
||
<div class="line"><a id="l15421" name="l15421"></a><span class="lineno">15421</span><span class="preprocessor"> (((CHANNEL) == TIM_CHANNEL_1) || \</span></div>
|
||
<div class="line"><a id="l15422" name="l15422"></a><span class="lineno">15422</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_2) || \</span></div>
|
||
<div class="line"><a id="l15423" name="l15423"></a><span class="lineno">15423</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_3) || \</span></div>
|
||
<div class="line"><a id="l15424" name="l15424"></a><span class="lineno">15424</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_4))) \</span></div>
|
||
<div class="line"><a id="l15425" name="l15425"></a><span class="lineno">15425</span><span class="preprocessor"> || \</span></div>
|
||
<div class="line"><a id="l15426" name="l15426"></a><span class="lineno">15426</span><span class="preprocessor"> (((INSTANCE) == TIM9) && \</span></div>
|
||
<div class="line"><a id="l15427" name="l15427"></a><span class="lineno">15427</span><span class="preprocessor"> (((CHANNEL) == TIM_CHANNEL_1) || \</span></div>
|
||
<div class="line"><a id="l15428" name="l15428"></a><span class="lineno">15428</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_2))) \</span></div>
|
||
<div class="line"><a id="l15429" name="l15429"></a><span class="lineno">15429</span><span class="preprocessor"> || \</span></div>
|
||
<div class="line"><a id="l15430" name="l15430"></a><span class="lineno">15430</span><span class="preprocessor"> (((INSTANCE) == TIM10) && \</span></div>
|
||
<div class="line"><a id="l15431" name="l15431"></a><span class="lineno">15431</span><span class="preprocessor"> (((CHANNEL) == TIM_CHANNEL_1))) \</span></div>
|
||
<div class="line"><a id="l15432" name="l15432"></a><span class="lineno">15432</span><span class="preprocessor"> || \</span></div>
|
||
<div class="line"><a id="l15433" name="l15433"></a><span class="lineno">15433</span><span class="preprocessor"> (((INSTANCE) == TIM11) && \</span></div>
|
||
<div class="line"><a id="l15434" name="l15434"></a><span class="lineno">15434</span><span class="preprocessor"> (((CHANNEL) == TIM_CHANNEL_1))) \</span></div>
|
||
<div class="line"><a id="l15435" name="l15435"></a><span class="lineno">15435</span><span class="preprocessor"> || \</span></div>
|
||
<div class="line"><a id="l15436" name="l15436"></a><span class="lineno">15436</span><span class="preprocessor"> (((INSTANCE) == TIM12) && \</span></div>
|
||
<div class="line"><a id="l15437" name="l15437"></a><span class="lineno">15437</span><span class="preprocessor"> (((CHANNEL) == TIM_CHANNEL_1) || \</span></div>
|
||
<div class="line"><a id="l15438" name="l15438"></a><span class="lineno">15438</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_2))) \</span></div>
|
||
<div class="line"><a id="l15439" name="l15439"></a><span class="lineno">15439</span><span class="preprocessor"> || \</span></div>
|
||
<div class="line"><a id="l15440" name="l15440"></a><span class="lineno">15440</span><span class="preprocessor"> (((INSTANCE) == TIM13) && \</span></div>
|
||
<div class="line"><a id="l15441" name="l15441"></a><span class="lineno">15441</span><span class="preprocessor"> (((CHANNEL) == TIM_CHANNEL_1))) \</span></div>
|
||
<div class="line"><a id="l15442" name="l15442"></a><span class="lineno">15442</span><span class="preprocessor"> || \</span></div>
|
||
<div class="line"><a id="l15443" name="l15443"></a><span class="lineno">15443</span><span class="preprocessor"> (((INSTANCE) == TIM14) && \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15444" name="l15444"></a><span class="lineno">15444</span><span class="preprocessor"> (((CHANNEL) == TIM_CHANNEL_1))))</span></div>
|
||
<div class="line"><a id="l15445" name="l15445"></a><span class="lineno">15445</span> </div>
|
||
<div class="foldopen" id="foldopen15446" data-start="" data-end="">
|
||
<div class="line"><a id="l15446" name="l15446"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga7181cfd1649c4e65e24b7c863e94a54f">15446</a></span><span class="comment">/************ TIM Instances : complementary output(s) available ***************/</span></div>
|
||
<div class="line"><a id="l15447" name="l15447"></a><span class="lineno">15447</span><span class="preprocessor">#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \</span></div>
|
||
<div class="line"><a id="l15448" name="l15448"></a><span class="lineno">15448</span><span class="preprocessor"> ((((INSTANCE) == TIM1) && \</span></div>
|
||
<div class="line"><a id="l15449" name="l15449"></a><span class="lineno">15449</span><span class="preprocessor"> (((CHANNEL) == TIM_CHANNEL_1) || \</span></div>
|
||
<div class="line"><a id="l15450" name="l15450"></a><span class="lineno">15450</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_2) || \</span></div>
|
||
<div class="line"><a id="l15451" name="l15451"></a><span class="lineno">15451</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_3))) \</span></div>
|
||
<div class="line"><a id="l15452" name="l15452"></a><span class="lineno">15452</span><span class="preprocessor"> || \</span></div>
|
||
<div class="line"><a id="l15453" name="l15453"></a><span class="lineno">15453</span><span class="preprocessor"> (((INSTANCE) == TIM8) && \</span></div>
|
||
<div class="line"><a id="l15454" name="l15454"></a><span class="lineno">15454</span><span class="preprocessor"> (((CHANNEL) == TIM_CHANNEL_1) || \</span></div>
|
||
<div class="line"><a id="l15455" name="l15455"></a><span class="lineno">15455</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_2) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15456" name="l15456"></a><span class="lineno">15456</span><span class="preprocessor"> ((CHANNEL) == TIM_CHANNEL_3))))</span></div>
|
||
<div class="line"><a id="l15457" name="l15457"></a><span class="lineno">15457</span> </div>
|
||
<div class="foldopen" id="foldopen15458" data-start="" data-end="">
|
||
<div class="line"><a id="l15458" name="l15458"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gaac0e3e7e7a18fd8eb81734b2baf9e3be">15458</a></span><span class="comment">/****************** TIM Instances : supporting counting mode selection ********/</span></div>
|
||
<div class="line"><a id="l15459" name="l15459"></a><span class="lineno">15459</span><span class="preprocessor">#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15460" name="l15460"></a><span class="lineno">15460</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15461" name="l15461"></a><span class="lineno">15461</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15462" name="l15462"></a><span class="lineno">15462</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15463" name="l15463"></a><span class="lineno">15463</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15464" name="l15464"></a><span class="lineno">15464</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15465" name="l15465"></a><span class="lineno">15465</span> </div>
|
||
<div class="foldopen" id="foldopen15466" data-start="" data-end="">
|
||
<div class="line"><a id="l15466" name="l15466"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gac54b9f42e8ab07c41abe7d96d13d698a">15466</a></span><span class="comment">/****************** TIM Instances : supporting clock division *****************/</span></div>
|
||
<div class="line"><a id="l15467" name="l15467"></a><span class="lineno">15467</span><span class="preprocessor">#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15468" name="l15468"></a><span class="lineno">15468</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15469" name="l15469"></a><span class="lineno">15469</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15470" name="l15470"></a><span class="lineno">15470</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15471" name="l15471"></a><span class="lineno">15471</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
<div class="line"><a id="l15472" name="l15472"></a><span class="lineno">15472</span><span class="preprocessor"> ((INSTANCE) == TIM8) || \</span></div>
|
||
<div class="line"><a id="l15473" name="l15473"></a><span class="lineno">15473</span><span class="preprocessor"> ((INSTANCE) == TIM9) || \</span></div>
|
||
<div class="line"><a id="l15474" name="l15474"></a><span class="lineno">15474</span><span class="preprocessor"> ((INSTANCE) == TIM10)|| \</span></div>
|
||
<div class="line"><a id="l15475" name="l15475"></a><span class="lineno">15475</span><span class="preprocessor"> ((INSTANCE) == TIM11)|| \</span></div>
|
||
<div class="line"><a id="l15476" name="l15476"></a><span class="lineno">15476</span><span class="preprocessor"> ((INSTANCE) == TIM12)|| \</span></div>
|
||
<div class="line"><a id="l15477" name="l15477"></a><span class="lineno">15477</span><span class="preprocessor"> ((INSTANCE) == TIM13)|| \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15478" name="l15478"></a><span class="lineno">15478</span><span class="preprocessor"> ((INSTANCE) == TIM14))</span></div>
|
||
<div class="line"><a id="l15479" name="l15479"></a><span class="lineno">15479</span> </div>
|
||
<div class="foldopen" id="foldopen15480" data-start="" data-end="">
|
||
<div class="line"><a id="l15480" name="l15480"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga5f61206c3c8b20784f9d237dce300afd">15480</a></span><span class="comment">/****************** TIM Instances : supporting commutation event generation ***/</span></div>
|
||
<div class="line"><a id="l15481" name="l15481"></a><span class="lineno">15481</span><span class="preprocessor">#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15482" name="l15482"></a><span class="lineno">15482</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15483" name="l15483"></a><span class="lineno">15483</span> </div>
|
||
<div class="line"><a id="l15484" name="l15484"></a><span class="lineno">15484</span> </div>
|
||
<div class="foldopen" id="foldopen15485" data-start="" data-end="">
|
||
<div class="line"><a id="l15485" name="l15485"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga7bf2abf939c55a4c8284c184735accdc">15485</a></span><span class="comment">/****************** TIM Instances : supporting OCxREF clear *******************/</span></div>
|
||
<div class="line"><a id="l15486" name="l15486"></a><span class="lineno">15486</span><span class="preprocessor">#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15487" name="l15487"></a><span class="lineno">15487</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15488" name="l15488"></a><span class="lineno">15488</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15489" name="l15489"></a><span class="lineno">15489</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15490" name="l15490"></a><span class="lineno">15490</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15491" name="l15491"></a><span class="lineno">15491</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15492" name="l15492"></a><span class="lineno">15492</span> </div>
|
||
<div class="foldopen" id="foldopen15493" data-start="" data-end="">
|
||
<div class="line"><a id="l15493" name="l15493"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga0ca20886f56bf7611ad511433b9caade">15493</a></span><span class="comment">/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/</span></div>
|
||
<div class="line"><a id="l15494" name="l15494"></a><span class="lineno">15494</span><span class="preprocessor">#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15495" name="l15495"></a><span class="lineno">15495</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15496" name="l15496"></a><span class="lineno">15496</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15497" name="l15497"></a><span class="lineno">15497</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15498" name="l15498"></a><span class="lineno">15498</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
<div class="line"><a id="l15499" name="l15499"></a><span class="lineno">15499</span><span class="preprocessor"> ((INSTANCE) == TIM8) || \</span></div>
|
||
<div class="line"><a id="l15500" name="l15500"></a><span class="lineno">15500</span><span class="preprocessor"> ((INSTANCE) == TIM9) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15501" name="l15501"></a><span class="lineno">15501</span><span class="preprocessor"> ((INSTANCE) == TIM12))</span></div>
|
||
<div class="line"><a id="l15502" name="l15502"></a><span class="lineno">15502</span> </div>
|
||
<div class="foldopen" id="foldopen15503" data-start="" data-end="">
|
||
<div class="line"><a id="l15503" name="l15503"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga7beb8f84094e6a1567d10177cc4fdae9">15503</a></span><span class="comment">/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/</span></div>
|
||
<div class="line"><a id="l15504" name="l15504"></a><span class="lineno">15504</span><span class="preprocessor">#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15505" name="l15505"></a><span class="lineno">15505</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15506" name="l15506"></a><span class="lineno">15506</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15507" name="l15507"></a><span class="lineno">15507</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15508" name="l15508"></a><span class="lineno">15508</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15509" name="l15509"></a><span class="lineno">15509</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15510" name="l15510"></a><span class="lineno">15510</span> </div>
|
||
<div class="foldopen" id="foldopen15511" data-start="" data-end="">
|
||
<div class="line"><a id="l15511" name="l15511"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gacbd23fd1f9f73dc249b16c89131a671c">15511</a></span><span class="comment">/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/</span></div>
|
||
<div class="line"><a id="l15512" name="l15512"></a><span class="lineno">15512</span><span class="preprocessor">#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15513" name="l15513"></a><span class="lineno">15513</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15514" name="l15514"></a><span class="lineno">15514</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15515" name="l15515"></a><span class="lineno">15515</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15516" name="l15516"></a><span class="lineno">15516</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
<div class="line"><a id="l15517" name="l15517"></a><span class="lineno">15517</span><span class="preprocessor"> ((INSTANCE) == TIM8) || \</span></div>
|
||
<div class="line"><a id="l15518" name="l15518"></a><span class="lineno">15518</span><span class="preprocessor"> ((INSTANCE) == TIM9) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15519" name="l15519"></a><span class="lineno">15519</span><span class="preprocessor"> ((INSTANCE) == TIM12))</span></div>
|
||
<div class="line"><a id="l15520" name="l15520"></a><span class="lineno">15520</span> </div>
|
||
<div class="foldopen" id="foldopen15521" data-start="" data-end="">
|
||
<div class="line"><a id="l15521" name="l15521"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga57882c3c75fddf0ccf0c6ecf99b3d3df">15521</a></span><span class="comment">/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/</span></div>
|
||
<div class="line"><a id="l15522" name="l15522"></a><span class="lineno">15522</span><span class="preprocessor">#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15523" name="l15523"></a><span class="lineno">15523</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15524" name="l15524"></a><span class="lineno">15524</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15525" name="l15525"></a><span class="lineno">15525</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15526" name="l15526"></a><span class="lineno">15526</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
<div class="line"><a id="l15527" name="l15527"></a><span class="lineno">15527</span><span class="preprocessor"> ((INSTANCE) == TIM8) || \</span></div>
|
||
<div class="line"><a id="l15528" name="l15528"></a><span class="lineno">15528</span><span class="preprocessor"> ((INSTANCE) == TIM9) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15529" name="l15529"></a><span class="lineno">15529</span><span class="preprocessor"> ((INSTANCE) == TIM12))</span></div>
|
||
<div class="line"><a id="l15530" name="l15530"></a><span class="lineno">15530</span> </div>
|
||
<div class="foldopen" id="foldopen15531" data-start="" data-end="">
|
||
<div class="line"><a id="l15531" name="l15531"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga3b470612fd4c4e29fb985247056b1e07">15531</a></span><span class="comment">/****************** TIM Instances : supporting repetition counter *************/</span></div>
|
||
<div class="line"><a id="l15532" name="l15532"></a><span class="lineno">15532</span><span class="preprocessor">#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15533" name="l15533"></a><span class="lineno">15533</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15534" name="l15534"></a><span class="lineno">15534</span> </div>
|
||
<div class="foldopen" id="foldopen15535" data-start="" data-end="">
|
||
<div class="line"><a id="l15535" name="l15535"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gacb14170c4996e004849647d8cb626402">15535</a></span><span class="comment">/****************** TIM Instances : supporting encoder interface **************/</span></div>
|
||
<div class="line"><a id="l15536" name="l15536"></a><span class="lineno">15536</span><span class="preprocessor">#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15537" name="l15537"></a><span class="lineno">15537</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15538" name="l15538"></a><span class="lineno">15538</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15539" name="l15539"></a><span class="lineno">15539</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15540" name="l15540"></a><span class="lineno">15540</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
<div class="line"><a id="l15541" name="l15541"></a><span class="lineno">15541</span><span class="preprocessor"> ((INSTANCE) == TIM8) || \</span></div>
|
||
<div class="line"><a id="l15542" name="l15542"></a><span class="lineno">15542</span><span class="preprocessor"> ((INSTANCE) == TIM9) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15543" name="l15543"></a><span class="lineno">15543</span><span class="preprocessor"> ((INSTANCE) == TIM12))</span></div>
|
||
<div class="foldopen" id="foldopen15544" data-start="" data-end="">
|
||
<div class="line"><a id="l15544" name="l15544"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga979ea18ba0931f5ed15cc2f3ac84794b">15544</a></span><span class="comment">/****************** TIM Instances : supporting Hall sensor interface **********/</span></div>
|
||
<div class="line"><a id="l15545" name="l15545"></a><span class="lineno">15545</span><span class="preprocessor">#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
<div class="line"><a id="l15546" name="l15546"></a><span class="lineno">15546</span><span class="preprocessor"> ((INSTANCE) == TIM2) || \</span></div>
|
||
<div class="line"><a id="l15547" name="l15547"></a><span class="lineno">15547</span><span class="preprocessor"> ((INSTANCE) == TIM3) || \</span></div>
|
||
<div class="line"><a id="l15548" name="l15548"></a><span class="lineno">15548</span><span class="preprocessor"> ((INSTANCE) == TIM4) || \</span></div>
|
||
<div class="line"><a id="l15549" name="l15549"></a><span class="lineno">15549</span><span class="preprocessor"> ((INSTANCE) == TIM5) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15550" name="l15550"></a><span class="lineno">15550</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="foldopen" id="foldopen15551" data-start="" data-end="">
|
||
<div class="line"><a id="l15551" name="l15551"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga68b8d9ca22720c9034753c604d83500d">15551</a></span><span class="comment">/****************** TIM Instances : supporting the break function *************/</span></div>
|
||
<div class="line"><a id="l15552" name="l15552"></a><span class="lineno">15552</span><span class="preprocessor">#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15553" name="l15553"></a><span class="lineno">15553</span><span class="preprocessor"> ((INSTANCE) == TIM8))</span></div>
|
||
<div class="line"><a id="l15554" name="l15554"></a><span class="lineno">15554</span> </div>
|
||
<div class="foldopen" id="foldopen15555" data-start="" data-end="">
|
||
<div class="line"><a id="l15555" name="l15555"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gafbce654f84a7c994817453695ac91cbe">15555</a></span><span class="comment">/******************** USART Instances : Synchronous mode **********************/</span></div>
|
||
<div class="line"><a id="l15556" name="l15556"></a><span class="lineno">15556</span><span class="preprocessor">#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \</span></div>
|
||
<div class="line"><a id="l15557" name="l15557"></a><span class="lineno">15557</span><span class="preprocessor"> ((INSTANCE) == USART2) || \</span></div>
|
||
<div class="line"><a id="l15558" name="l15558"></a><span class="lineno">15558</span><span class="preprocessor"> ((INSTANCE) == USART3) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15559" name="l15559"></a><span class="lineno">15559</span><span class="preprocessor"> ((INSTANCE) == USART6))</span></div>
|
||
<div class="line"><a id="l15560" name="l15560"></a><span class="lineno">15560</span> </div>
|
||
<div class="foldopen" id="foldopen15561" data-start="" data-end="">
|
||
<div class="line"><a id="l15561" name="l15561"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga69c4aa0c561c4c39c621710fbbb0cb7b">15561</a></span><span class="comment">/******************** UART Instances : Half-Duplex mode **********************/</span></div>
|
||
<div class="line"><a id="l15562" name="l15562"></a><span class="lineno">15562</span><span class="preprocessor">#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \</span></div>
|
||
<div class="line"><a id="l15563" name="l15563"></a><span class="lineno">15563</span><span class="preprocessor"> ((INSTANCE) == USART2) || \</span></div>
|
||
<div class="line"><a id="l15564" name="l15564"></a><span class="lineno">15564</span><span class="preprocessor"> ((INSTANCE) == USART3) || \</span></div>
|
||
<div class="line"><a id="l15565" name="l15565"></a><span class="lineno">15565</span><span class="preprocessor"> ((INSTANCE) == UART4) || \</span></div>
|
||
<div class="line"><a id="l15566" name="l15566"></a><span class="lineno">15566</span><span class="preprocessor"> ((INSTANCE) == UART5) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15567" name="l15567"></a><span class="lineno">15567</span><span class="preprocessor"> ((INSTANCE) == USART6))</span></div>
|
||
<div class="line"><a id="l15568" name="l15568"></a><span class="lineno">15568</span> </div>
|
||
<div class="line"><a id="l15569" name="l15569"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga14e4b19f7c750110f6c27cf26347ba45">15569</a></span><span class="comment">/* Legacy defines */</span></div>
|
||
<div class="line"><a id="l15570" name="l15570"></a><span class="lineno">15570</span><span class="preprocessor">#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE</span></div>
|
||
<div class="line"><a id="l15571" name="l15571"></a><span class="lineno">15571</span> </div>
|
||
<div class="foldopen" id="foldopen15572" data-start="" data-end="">
|
||
<div class="line"><a id="l15572" name="l15572"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gaf9a11d0720f3efa780126414a4ac50ad">15572</a></span><span class="comment">/****************** UART Instances : Hardware Flow control ********************/</span></div>
|
||
<div class="line"><a id="l15573" name="l15573"></a><span class="lineno">15573</span><span class="preprocessor">#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \</span></div>
|
||
<div class="line"><a id="l15574" name="l15574"></a><span class="lineno">15574</span><span class="preprocessor"> ((INSTANCE) == USART2) || \</span></div>
|
||
<div class="line"><a id="l15575" name="l15575"></a><span class="lineno">15575</span><span class="preprocessor"> ((INSTANCE) == USART3) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15576" name="l15576"></a><span class="lineno">15576</span><span class="preprocessor"> ((INSTANCE) == USART6))</span></div>
|
||
<div class="line"><a id="l15577" name="l15577"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gaf7905bb5a02acf0e92ddf40bdd8dcdc0">15577</a></span><span class="comment">/******************** UART Instances : LIN mode **********************/</span></div>
|
||
<div class="line"><a id="l15578" name="l15578"></a><span class="lineno">15578</span><span class="preprocessor">#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE</span></div>
|
||
<div class="line"><a id="l15579" name="l15579"></a><span class="lineno">15579</span> </div>
|
||
<div class="foldopen" id="foldopen15580" data-start="" data-end="">
|
||
<div class="line"><a id="l15580" name="l15580"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gab2734c105403831749ccb34eeb058988">15580</a></span><span class="comment">/********************* UART Instances : Smart card mode ***********************/</span></div>
|
||
<div class="line"><a id="l15581" name="l15581"></a><span class="lineno">15581</span><span class="preprocessor">#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \</span></div>
|
||
<div class="line"><a id="l15582" name="l15582"></a><span class="lineno">15582</span><span class="preprocessor"> ((INSTANCE) == USART2) || \</span></div>
|
||
<div class="line"><a id="l15583" name="l15583"></a><span class="lineno">15583</span><span class="preprocessor"> ((INSTANCE) == USART3) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15584" name="l15584"></a><span class="lineno">15584</span><span class="preprocessor"> ((INSTANCE) == USART6))</span></div>
|
||
<div class="line"><a id="l15585" name="l15585"></a><span class="lineno">15585</span> </div>
|
||
<div class="foldopen" id="foldopen15586" data-start="" data-end="">
|
||
<div class="line"><a id="l15586" name="l15586"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga98ae6698dc54d8441fce553a65bf5429">15586</a></span><span class="comment">/*********************** UART Instances : IRDA mode ***************************/</span></div>
|
||
<div class="line"><a id="l15587" name="l15587"></a><span class="lineno">15587</span><span class="preprocessor">#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \</span></div>
|
||
<div class="line"><a id="l15588" name="l15588"></a><span class="lineno">15588</span><span class="preprocessor"> ((INSTANCE) == USART2) || \</span></div>
|
||
<div class="line"><a id="l15589" name="l15589"></a><span class="lineno">15589</span><span class="preprocessor"> ((INSTANCE) == USART3) || \</span></div>
|
||
<div class="line"><a id="l15590" name="l15590"></a><span class="lineno">15590</span><span class="preprocessor"> ((INSTANCE) == UART4) || \</span></div>
|
||
<div class="line"><a id="l15591" name="l15591"></a><span class="lineno">15591</span><span class="preprocessor"> ((INSTANCE) == UART5) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15592" name="l15592"></a><span class="lineno">15592</span><span class="preprocessor"> ((INSTANCE) == USART6))</span></div>
|
||
<div class="line"><a id="l15593" name="l15593"></a><span class="lineno">15593</span> </div>
|
||
<div class="line"><a id="l15594" name="l15594"></a><span class="lineno">15594</span> </div>
|
||
<div class="foldopen" id="foldopen15595" data-start="" data-end="">
|
||
<div class="line"><a id="l15595" name="l15595"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gadaf663c55446f04fa69ee912b8890b32">15595</a></span><span class="comment">/*********************** PCD Instances ****************************************/</span></div>
|
||
<div class="line"><a id="l15596" name="l15596"></a><span class="lineno">15596</span><span class="preprocessor">#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15597" name="l15597"></a><span class="lineno">15597</span><span class="preprocessor"> ((INSTANCE) == USB_OTG_HS))</span></div>
|
||
<div class="line"><a id="l15598" name="l15598"></a><span class="lineno">15598</span> </div>
|
||
<div class="foldopen" id="foldopen15599" data-start="" data-end="">
|
||
<div class="line"><a id="l15599" name="l15599"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga6696ebd1aea007a19e831517f3e1f497">15599</a></span><span class="comment">/*********************** HCD Instances ****************************************/</span></div>
|
||
<div class="line"><a id="l15600" name="l15600"></a><span class="lineno">15600</span><span class="preprocessor">#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \</span></div>
|
||
</div>
|
||
<div class="line"><a id="l15601" name="l15601"></a><span class="lineno">15601</span><span class="preprocessor"> ((INSTANCE) == USB_OTG_HS))</span></div>
|
||
<div class="line"><a id="l15602" name="l15602"></a><span class="lineno">15602</span> </div>
|
||
<div class="line"><a id="l15603" name="l15603"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga73932cb2c83be6be1884d3cba2fc0063">15603</a></span><span class="comment">/****************************** SDIO Instances ********************************/</span></div>
|
||
<div class="line"><a id="l15604" name="l15604"></a><span class="lineno">15604</span><span class="preprocessor">#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)</span></div>
|
||
<div class="line"><a id="l15605" name="l15605"></a><span class="lineno">15605</span> </div>
|
||
<div class="line"><a id="l15606" name="l15606"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gad9ec4c52f0572ee67d043e006f1d5e39">15606</a></span><span class="comment">/****************************** IWDG Instances ********************************/</span></div>
|
||
<div class="line"><a id="l15607" name="l15607"></a><span class="lineno">15607</span><span class="preprocessor">#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)</span></div>
|
||
<div class="line"><a id="l15608" name="l15608"></a><span class="lineno">15608</span> </div>
|
||
<div class="line"><a id="l15609" name="l15609"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gac2a8aaec233e19987232455643a04d6f">15609</a></span><span class="comment">/****************************** WWDG Instances ********************************/</span></div>
|
||
<div class="line"><a id="l15610" name="l15610"></a><span class="lineno">15610</span><span class="preprocessor">#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)</span></div>
|
||
<div class="line"><a id="l15611" name="l15611"></a><span class="lineno">15611</span> </div>
|
||
<div class="line"><a id="l15612" name="l15612"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga4c58971ce9062c1c7bc42e1c7ea4df32">15612</a></span><span class="comment">/****************************** USB Exported Constants ************************/</span></div>
|
||
<div class="line"><a id="l15613" name="l15613"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gaccec7ca403e63ea963c363ceb7301ca6">15613</a></span><span class="preprocessor">#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U</span></div>
|
||
<div class="line"><a id="l15614" name="l15614"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga1d58ab8276cfdef9aa868bfdd2590aae">15614</a></span><span class="preprocessor">#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U </span><span class="comment">/* Including EP0 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l15615" name="l15615"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga1e726d88af0f77cb8a49ff7b666fd990">15615</a></span><span class="preprocessor">#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U </span><span class="comment">/* Including EP0 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l15616" name="l15616"></a><span class="lineno">15616</span><span class="preprocessor">#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U </span><span class="comment">/* in Bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l15617" name="l15617"></a><span class="lineno">15617</span> </div>
|
||
<div class="line"><a id="l15618" name="l15618"></a><span class="lineno">15618</span><span class="comment">/*</span></div>
|
||
<div class="line"><a id="l15619" name="l15619"></a><span class="lineno">15619</span><span class="comment"> * @brief Specific devices reset values definitions</span></div>
|
||
<div class="line"><a id="l15620" name="l15620"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gab0a3c8475d96f7bb0c8a6b8a7e0c943c">15620</a></span><span class="comment"> */</span></div>
|
||
<div class="line"><a id="l15621" name="l15621"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gab5ca7e3fcb49274bb60c660221bbca5b">15621</a></span><span class="preprocessor">#define RCC_PLLCFGR_RST_VALUE 0x24003010U</span></div>
|
||
<div class="line"><a id="l15622" name="l15622"></a><span class="lineno">15622</span><span class="preprocessor">#define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U</span></div>
|
||
<div class="line"><a id="l15623" name="l15623"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga08aeea283003a2c787227347087b5b1f">15623</a></span> </div>
|
||
<div class="line"><a id="l15624" name="l15624"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga152c4bb0b78589a06d72e0170dd3b304">15624</a></span><span class="preprocessor">#define RCC_MAX_FREQUENCY 168000000U </span></div>
|
||
<div class="line"><a id="l15625" name="l15625"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gafcb2c5211d9cbed86b111c83a0ce427b">15625</a></span><span class="preprocessor">#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY </span></div>
|
||
<div class="line"><a id="l15626" name="l15626"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga85746dffdc6d015f5142d7e16489ca84">15626</a></span><span class="preprocessor">#define RCC_MAX_FREQUENCY_SCALE2 144000000U </span></div>
|
||
<div class="line"><a id="l15627" name="l15627"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga288d68c2604cea8548eccdef3873923f">15627</a></span><span class="preprocessor">#define RCC_PLLVCO_OUTPUT_MIN 100000000U </span></div>
|
||
<div class="line"><a id="l15628" name="l15628"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gad3fd37dbfa74739a3c698ab4755fa27e">15628</a></span><span class="preprocessor">#define RCC_PLLVCO_INPUT_MIN 950000U </span></div>
|
||
<div class="line"><a id="l15629" name="l15629"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gaba6ddae0375763847f8dc3e91173d714">15629</a></span><span class="preprocessor">#define RCC_PLLVCO_INPUT_MAX 2100000U </span></div>
|
||
<div class="line"><a id="l15630" name="l15630"></a><span class="lineno">15630</span><span class="preprocessor">#define RCC_PLLVCO_OUTPUT_MAX 432000000U </span></div>
|
||
<div class="line"><a id="l15632" name="l15632"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga9d6c2fd92a420bb80caf8ca2cadb6a62">15632</a></span><span class="preprocessor">#define RCC_PLLN_MIN_VALUE 50U</span></div>
|
||
<div class="line"><a id="l15633" name="l15633"></a><span class="lineno">15633</span><span class="preprocessor">#define RCC_PLLN_MAX_VALUE 432U</span></div>
|
||
<div class="line"><a id="l15634" name="l15634"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga980965268c210a75ca5bb1e6b59b4052">15634</a></span> </div>
|
||
<div class="line"><a id="l15635" name="l15635"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga53673600707f291baa71c30919f8da98">15635</a></span><span class="preprocessor">#define FLASH_SCALE1_LATENCY1_FREQ 30000000U </span></div>
|
||
<div class="line"><a id="l15636" name="l15636"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga547cb8d59cf6a2a73a0f76331e4492df">15636</a></span><span class="preprocessor">#define FLASH_SCALE1_LATENCY2_FREQ 60000000U </span></div>
|
||
<div class="line"><a id="l15637" name="l15637"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga600fe88d1dfa0faef16947e24f52e84e">15637</a></span><span class="preprocessor">#define FLASH_SCALE1_LATENCY3_FREQ 90000000U </span></div>
|
||
<div class="line"><a id="l15638" name="l15638"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gaf576f3543b7909cf6c889e05829d37a0">15638</a></span><span class="preprocessor">#define FLASH_SCALE1_LATENCY4_FREQ 120000000U </span></div>
|
||
<div class="line"><a id="l15639" name="l15639"></a><span class="lineno">15639</span><span class="preprocessor">#define FLASH_SCALE1_LATENCY5_FREQ 150000000U </span></div>
|
||
<div class="line"><a id="l15641" name="l15641"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga98847021d5de23ea0458b490c74e6299">15641</a></span><span class="preprocessor">#define FLASH_SCALE2_LATENCY1_FREQ 30000000U </span></div>
|
||
<div class="line"><a id="l15642" name="l15642"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga6956d1ea5f9484a43213022ebff8cf03">15642</a></span><span class="preprocessor">#define FLASH_SCALE2_LATENCY2_FREQ 60000000U </span></div>
|
||
<div class="line"><a id="l15643" name="l15643"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga8fc5a396df42d76fb41f377e71513ecb">15643</a></span><span class="preprocessor">#define FLASH_SCALE2_LATENCY3_FREQ 90000000U </span></div>
|
||
<div class="line"><a id="l15644" name="l15644"></a><span class="lineno">15644</span><span class="preprocessor">#define FLASH_SCALE2_LATENCY4_FREQ 12000000U </span></div>
|
||
<div class="line"><a id="l15646" name="l15646"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gae79bbfa7391870814f10c8025ade8a2a">15646</a></span><span class="preprocessor">#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U</span></div>
|
||
<div class="line"><a id="l15647" name="l15647"></a><span class="lineno"><a class="line" href="group___exported__macros.html#gace63bb65e2fb24f0df6ebe1e65efa560">15647</a></span><span class="preprocessor">#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U </span><span class="comment">/* Including EP0 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l15648" name="l15648"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga55a4488eac406bcff895de59782fd6a7">15648</a></span><span class="preprocessor">#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U </span><span class="comment">/* Including EP0 */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l15649" name="l15649"></a><span class="lineno">15649</span><span class="preprocessor">#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U </span><span class="comment">/* in Bytes */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l15650" name="l15650"></a><span class="lineno">15650</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l15651" name="l15651"></a><span class="lineno">15651</span><span class="comment">/* For a painless codes migration between the STM32F4xx device product */</span></div>
|
||
<div class="line"><a id="l15652" name="l15652"></a><span class="lineno">15652</span><span class="comment">/* lines, the aliases defined below are put in place to overcome the */</span></div>
|
||
<div class="line"><a id="l15653" name="l15653"></a><span class="lineno">15653</span><span class="comment">/* differences in the interrupt handlers and IRQn definitions. */</span></div>
|
||
<div class="line"><a id="l15654" name="l15654"></a><span class="lineno">15654</span><span class="comment">/* No need to update developed interrupt code when moving across */</span></div>
|
||
<div class="line"><a id="l15655" name="l15655"></a><span class="lineno">15655</span><span class="comment">/* product lines within the same STM32F4 Family */</span></div>
|
||
<div class="line"><a id="l15656" name="l15656"></a><span class="lineno">15656</span><span class="comment">/******************************************************************************/</span></div>
|
||
<div class="line"><a id="l15657" name="l15657"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga1452f42f926ec3886d3688352472f960">15657</a></span><span class="comment">/* Aliases for __IRQn */</span></div>
|
||
<div class="line"><a id="l15658" name="l15658"></a><span class="lineno">15658</span><span class="preprocessor">#define FMC_IRQn FSMC_IRQn</span></div>
|
||
<div class="line"><a id="l15659" name="l15659"></a><span class="lineno">15659</span> </div>
|
||
<div class="line"><a id="l15660" name="l15660"></a><span class="lineno"><a class="line" href="group___exported__macros.html#ga3dec035cce31cf17473f915dade1ca25">15660</a></span><span class="comment">/* Aliases for __IRQHandler */</span></div>
|
||
<div class="line"><a id="l15661" name="l15661"></a><span class="lineno">15661</span><span class="preprocessor">#define FMC_IRQHandler FSMC_IRQHandler</span></div>
|
||
<div class="line"><a id="l15662" name="l15662"></a><span class="lineno">15662</span> </div>
|
||
<div class="line"><a id="l15675" name="l15675"></a><span class="lineno">15675</span><span class="preprocessor">#ifdef __cplusplus</span></div>
|
||
<div class="line"><a id="l15676" name="l15676"></a><span class="lineno">15676</span>}</div>
|
||
<div class="line"><a id="l15677" name="l15677"></a><span class="lineno">15677</span><span class="preprocessor">#endif </span><span class="comment">/* __cplusplus */</span><span class="preprocessor"></span></div>
|
||
<div class="line"><a id="l15678" name="l15678"></a><span class="lineno">15678</span> </div>
|
||
<div class="line"><a id="l15679" name="l15679"></a><span class="lineno">15679</span><span class="preprocessor">#endif </span><span class="comment">/* __STM32F407xx_H */</span><span class="preprocessor"></span></div>
|
||
<div class="ttc" id="aarm__defines_8h_html"><div class="ttname"><a href="arm__defines_8h.html">arm_defines.h</a></div></div>
|
||
<div class="ttc" id="aarm__defines_8h_html_aec43007d9998a0a0e01faede4133d6be"><div class="ttname"><a href="arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a></div><div class="ttdeci">#define __IO</div><div class="ttdef"><b>Definition</b> arm_defines.h:8</div></div>
|
||
<div class="ttc" id="acore__cm4__matlab_8h_html"><div class="ttname"><a href="core__cm4__matlab_8h.html">core_cm4_matlab.h</a></div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga003c4c00f70bd77298fc66a449822651"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga003c4c00f70bd77298fc66a449822651">SDIO_TypeDef::FIFOCNT</a></div><div class="ttdeci">__IO const uint32_t FIFOCNT</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:713</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga0234d794aba7ddae31f3da3c02c8a673"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga0234d794aba7ddae31f3da3c02c8a673">USB_OTG_DeviceTypeDef::DEACHMSK</a></div><div class="ttdeci">__IO uint32_t DEACHMSK</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:847</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga026f1fea708d42ed74b0bd8a488bc55e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga026f1fea708d42ed74b0bd8a488bc55e">USB_OTG_GlobalTypeDef::GRXSTSP</a></div><div class="ttdeci">__IO uint32_t GRXSTSP</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:815</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga02b589bb589df4f39e549dca4d5abb08"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga02b589bb589df4f39e549dca4d5abb08">CAN_TypeDef::RF1R</a></div><div class="ttdeci">__IO uint32_t RF1R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:267</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga042059c8b4168681d6aecf30211dd7b8"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga042059c8b4168681d6aecf30211dd7b8">RTC_TypeDef::TSTR</a></div><div class="ttdeci">__IO uint32_t TSTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:660</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga05a47a1664adc7a3db3fa3e83fe883b4"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga05a47a1664adc7a3db3fa3e83fe883b4">FSMC_Bank2_3_TypeDef::ECCR2</a></div><div class="ttdeci">__IO uint32_t ECCR2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:510</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga05fcc63652e936e715223e4423069959"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga05fcc63652e936e715223e4423069959">USB_OTG_INEndpointTypeDef::DIEPDMA</a></div><div class="ttdeci">__IO uint32_t DIEPDMA</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:864</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga0633538b8b7a6f1372d38938851bba87"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga0633538b8b7a6f1372d38938851bba87">USB_OTG_GlobalTypeDef::GUSBCFG</a></div><div class="ttdeci">__IO uint32_t GUSBCFG</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:810</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga0633c88accff51e7cc9d1e9c3db950d9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga0633c88accff51e7cc9d1e9c3db950d9">SDIO_TypeDef::STA</a></div><div class="ttdeci">__IO const uint32_t STA</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:709</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga07d4e63efcbde252c667e64a8d818aa9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga07d4e63efcbde252c667e64a8d818aa9">SDIO_TypeDef::ARG</a></div><div class="ttdeci">__IO uint32_t ARG</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:698</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga07fccbd85b91e6dca03ce333c1457fcb"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga07fccbd85b91e6dca03ce333c1457fcb">TIM_TypeDef::DIER</a></div><div class="ttdeci">__IO uint32_t DIER</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:745</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga081f4304e18753e5e8d0afd71ccca45e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga081f4304e18753e5e8d0afd71ccca45e">ADC_TypeDef::SR</a></div><div class="ttdeci">uint32_t SR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:192</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga08b4be0d626a00f26bc295b379b3bba6"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga08b4be0d626a00f26bc295b379b3bba6">I2C_TypeDef::OAR1</a></div><div class="ttdeci">__IO uint32_t OAR1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:572</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga08ddbac546fa9928256654d31255c8c3"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga08ddbac546fa9928256654d31255c8c3">SYSCFG_TypeDef::CMPCR</a></div><div class="ttdeci">__IO uint32_t CMPCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:561</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga091452256c9a16c33d891f4d32b395bf"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga091452256c9a16c33d891f4d32b395bf">TIM_TypeDef::CCMR2</a></div><div class="ttdeci">__IO uint32_t CCMR2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:749</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga092e59d908b2ca112e31047e942340cb"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga092e59d908b2ca112e31047e942340cb">USART_TypeDef::BRR</a></div><div class="ttdeci">__IO uint32_t BRR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:773</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga098110becfef10e1fd1b6a4f874da496"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga098110becfef10e1fd1b6a4f874da496">TIM_TypeDef::CCER</a></div><div class="ttdeci">__IO uint32_t CCER</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:750</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga0a6f11662e44ad485cc869f49e5aa9c9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga0a6f11662e44ad485cc869f49e5aa9c9">USB_OTG_HostTypeDef::HFIR</a></div><div class="ttdeci">__IO uint32_t HFIR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:889</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga0a8c8230846fd8ff154b9fde8dfa0399"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga0a8c8230846fd8ff154b9fde8dfa0399">DCMI_TypeDef::ICR</a></div><div class="ttdeci">__IO uint32_t ICR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:345</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga0acc8eb90b17bef5b9e03c7ddaacfb0b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga0acc8eb90b17bef5b9e03c7ddaacfb0b">CAN_FIFOMailBox_TypeDef::RIR</a></div><div class="ttdeci">__IO uint32_t RIR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:241</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga0b1eeda834c3cfd4d2c67f242f7b2a1c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga0b1eeda834c3cfd4d2c67f242f7b2a1c">RTC_TypeDef::BKP3R</a></div><div class="ttdeci">__IO uint32_t BKP3R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:671</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga0b9a3ced775287c8585a6a61af4b40e9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga0b9a3ced775287c8585a6a61af4b40e9">RCC_TypeDef::BDCR</a></div><div class="ttdeci">__IO uint32_t BDCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:635</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga0d952a17455687d6e9053730d028fa1d"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga0d952a17455687d6e9053730d028fa1d">EXTI_TypeDef::RTSR</a></div><div class="ttdeci">__IO uint32_t RTSR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:458</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga1140b76ff103608f66c26ad0a3d595d0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga1140b76ff103608f66c26ad0a3d595d0">USB_OTG_GlobalTypeDef::GRXFSIZ</a></div><div class="ttdeci">__IO uint32_t GRXFSIZ</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:816</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga1173127526cca9128e409bc83c7729dc"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga1173127526cca9128e409bc83c7729dc">ETH_TypeDef::MACSR</a></div><div class="ttdeci">__IO uint32_t MACSR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:394</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga11dbd3f7a82b3f3b91621321d3018e0a"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga11dbd3f7a82b3f3b91621321d3018e0a">USB_OTG_DeviceTypeDef::DOEPMSK</a></div><div class="ttdeci">__IO uint32_t DOEPMSK</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:837</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga11e65074b9f06b48c17cdfa5bea9f125"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga11e65074b9f06b48c17cdfa5bea9f125">ADC_TypeDef::JOFR2</a></div><div class="ttdeci">__IO uint32_t JOFR2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:198</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga121212bdb227106df681d24e5d896a4e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga121212bdb227106df681d24e5d896a4e">ETH_TypeDef::MACHTHR</a></div><div class="ttdeci">__IO uint32_t MACHTHR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:383</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga129dcc23d48588d5af7dd218b617933d"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga129dcc23d48588d5af7dd218b617933d">ETH_TypeDef::MACRWUFFR</a></div><div class="ttdeci">__IO uint32_t MACRWUFFR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:390</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga12eba1fc5d54aa50fdda201f7f9a84a3"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga12eba1fc5d54aa50fdda201f7f9a84a3">ETH_TypeDef::DMAMFBOCR</a></div><div class="ttdeci">__IO uint32_t DMAMFBOCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:441</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga12f62d3d3b9ee30c20c324b146e72795"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga12f62d3d3b9ee30c20c324b146e72795">ETH_TypeDef::MACFCR</a></div><div class="ttdeci">__IO uint32_t MACFCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:387</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga14d03244a7fda1d94b51ae9ed144ca12"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga14d03244a7fda1d94b51ae9ed144ca12">RTC_TypeDef::TAFCR</a></div><div class="ttdeci">__IO uint32_t TAFCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:664</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga1590b77e57f17e75193da259da72095e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga1590b77e57f17e75193da259da72095e">DAC_TypeDef::DHR12RD</a></div><div class="ttdeci">__IO uint32_t DHR12RD</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:314</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga17d14644b0d28710722b1c2c0149e472"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga17d14644b0d28710722b1c2c0149e472">USB_OTG_DeviceTypeDef::Reserved20</a></div><div class="ttdeci">uint32_t Reserved20</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:840</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga18e294dd2625a93ebf2aab9f2b3c4911"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga18e294dd2625a93ebf2aab9f2b3c4911">ETH_TypeDef::MMCTIMR</a></div><div class="ttdeci">__IO uint32_t MMCTIMR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:409</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga195d1a8a6ae4f6072f4e4b62298051fe"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga195d1a8a6ae4f6072f4e4b62298051fe">SDIO_TypeDef::RESPCMD</a></div><div class="ttdeci">__IO const uint32_t RESPCMD</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:700</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga196e86fc15ba228188d47468349de69b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga196e86fc15ba228188d47468349de69b">USB_OTG_DeviceTypeDef::DOUTEP1MSK</a></div><div class="ttdeci">__IO uint32_t DOUTEP1MSK</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:851</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga196ebdaac12b21e90320c6175da78ef6"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga196ebdaac12b21e90320c6175da78ef6">TIM_TypeDef::EGR</a></div><div class="ttdeci">__IO uint32_t EGR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:747</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga19cf1f1798a062c2a19afe9224e3f938"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga19cf1f1798a062c2a19afe9224e3f938">USB_OTG_INEndpointTypeDef::DIEPTSIZ</a></div><div class="ttdeci">__IO uint32_t DIEPTSIZ</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:863</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga1bcc039378b4ed4ac1261a0a758c3d1d"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga1bcc039378b4ed4ac1261a0a758c3d1d">USB_OTG_DeviceTypeDef::Reserved0C</a></div><div class="ttdeci">uint32_t Reserved0C</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:835</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga1c267db01a753d0b8a77afcaff6f9e13"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga1c267db01a753d0b8a77afcaff6f9e13">SDIO_TypeDef::DCOUNT</a></div><div class="ttdeci">__IO const uint32_t DCOUNT</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:708</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga1cb734df34f6520a7204c4c70634ebba"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga1cb734df34f6520a7204c4c70634ebba">CAN_TypeDef::FMR</a></div><div class="ttdeci">__IO uint32_t FMR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:275</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga1d34ab8e5c2041c00ba9526b3958099d"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga1d34ab8e5c2041c00ba9526b3958099d">ETH_TypeDef::MACHTLR</a></div><div class="ttdeci">__IO uint32_t MACHTLR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:384</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga1d6c2bc4c067d6a64ef30d16a5925796"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga1d6c2bc4c067d6a64ef30d16a5925796">RTC_TypeDef::TSSSR</a></div><div class="ttdeci">__IO uint32_t TSSSR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:662</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga1d854d2d7f0452f4c90035952b92d2ba"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga1d854d2d7f0452f4c90035952b92d2ba">RTC_TypeDef::BKP6R</a></div><div class="ttdeci">__IO uint32_t BKP6R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:674</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga1dd219eaeee8d9def822da843028bd02"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga1dd219eaeee8d9def822da843028bd02">SDIO_TypeDef::DTIMER</a></div><div class="ttdeci">__IO uint32_t DTIMER</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:705</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga1dddf235f246a1d4e7e5084cd51e2dd0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga1dddf235f246a1d4e7e5084cd51e2dd0">FLASH_TypeDef::OPTCR1</a></div><div class="ttdeci">__IO uint32_t OPTCR1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:476</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga1e9c75b06c99d0611535f38c7b4aa845"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga1e9c75b06c99d0611535f38c7b4aa845">RCC_TypeDef::AHB1ENR</a></div><div class="ttdeci">__IO uint32_t AHB1ENR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:621</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga1ebbda0d742e80ca3d53edfa3a95f627"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga1ebbda0d742e80ca3d53edfa3a95f627">ETH_TypeDef::PTPTSHR</a></div><div class="ttdeci">__IO uint32_t PTPTSHR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:423</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga20acbcac1c35f66de94c9ff0e2ddc7b0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga20acbcac1c35f66de94c9ff0e2ddc7b0">ETH_TypeDef::MACCR</a></div><div class="ttdeci">__IO uint32_t MACCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:381</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2130abf1fefb63ce4c4b138fd8c9822a"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2130abf1fefb63ce4c4b138fd8c9822a">SYSCFG_TypeDef::PMC</a></div><div class="ttdeci">__IO uint32_t PMC</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:558</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga22fa21352be442bd02f9c26a1013d598"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga22fa21352be442bd02f9c26a1013d598">ADC_TypeDef::JDR1</a></div><div class="ttdeci">__IO uint32_t JDR1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:207</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2372c05a6c5508e0a9adada793f68b4f"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2372c05a6c5508e0a9adada793f68b4f">RTC_TypeDef::SHIFTR</a></div><div class="ttdeci">__IO uint32_t SHIFTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:659</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga23970354d69354ab78165e76afd6c2f7"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga23970354d69354ab78165e76afd6c2f7">ETH_TypeDef::MMCTGFSCCR</a></div><div class="ttdeci">__IO uint32_t MMCTGFSCCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:411</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga24c3512abcc90ef75cf3e9145e5dbe9b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga24c3512abcc90ef75cf3e9145e5dbe9b">ADC_TypeDef::HTR</a></div><div class="ttdeci">__IO uint32_t HTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:201</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga24df28d0e440321b21f6f07b3bb93dea"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga24df28d0e440321b21f6f07b3bb93dea">DBGMCU_TypeDef::IDCODE</a></div><div class="ttdeci">__IO uint32_t IDCODE</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:328</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2612a0f4b3fbdbb6293f6dc70105e190"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2612a0f4b3fbdbb6293f6dc70105e190">GPIO_TypeDef::LCKR</a></div><div class="ttdeci">__IO uint32_t LCKR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:547</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga26f1e746ccbf9c9f67e7c60e61085ec1"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga26f1e746ccbf9c9f67e7c60e61085ec1">RCC_TypeDef::CFGR</a></div><div class="ttdeci">__IO uint32_t CFGR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:612</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga270ee3c6e9f87e5851422ae0ef255fd4"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga270ee3c6e9f87e5851422ae0ef255fd4">SDIO_TypeDef::RESP3</a></div><div class="ttdeci">__IO const uint32_t RESP3</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:703</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga27a478cc47a3dff478555ccb985b06a2"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga27a478cc47a3dff478555ccb985b06a2">TIM_TypeDef::CCR3</a></div><div class="ttdeci">__IO uint32_t CCR3</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:757</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga27af4e9f888f0b7b1e8da7e002d98798"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga27af4e9f888f0b7b1e8da7e002d98798">CAN_TypeDef::MCR</a></div><div class="ttdeci">__IO uint32_t MCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:263</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2842aa523df62f3508316eb3b2e08f4e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2842aa523df62f3508316eb3b2e08f4e">RTC_TypeDef::BKP17R</a></div><div class="ttdeci">__IO uint32_t BKP17R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:685</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga28560c5bfeb45326ea7f2019dba57bea"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga28560c5bfeb45326ea7f2019dba57bea">RCC_TypeDef::AHB3RSTR</a></div><div class="ttdeci">__IO uint32_t AHB3RSTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:616</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2870732a4fc2ecd7bbecfbcbbf5528b7"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2870732a4fc2ecd7bbecfbcbbf5528b7">TIM_TypeDef::SMCR</a></div><div class="ttdeci">__IO uint32_t SMCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:744</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga28e7b0195ce457d20f585f6587fc1cb8"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga28e7b0195ce457d20f585f6587fc1cb8">ETH_TypeDef::PTPTTLR</a></div><div class="ttdeci">__IO uint32_t PTPTTLR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:429</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2b30982547fae7d545d260312771b5c9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2b30982547fae7d545d260312771b5c9">RCC_TypeDef::AHB2LPENR</a></div><div class="ttdeci">__IO uint32_t AHB2LPENR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:629</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2b39f943954e0e7d177b511d9074a0b7"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2b39f943954e0e7d177b511d9074a0b7">CAN_TypeDef::ESR</a></div><div class="ttdeci">__IO uint32_t ESR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:269</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2b671a94c63a612f81e0e9de8152d01c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2b671a94c63a612f81e0e9de8152d01c">GPIO_TypeDef::MODER</a></div><div class="ttdeci">__IO uint32_t MODER</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:540</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2ba9f73c7fa756305d54a8f80872c6df"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2ba9f73c7fa756305d54a8f80872c6df">ETH_TypeDef::MACA3LR</a></div><div class="ttdeci">__IO uint32_t MACA3LR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:403</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2c8f65655aa14ec9ba63c9d0655223ec"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2c8f65655aa14ec9ba63c9d0655223ec">USB_OTG_DeviceTypeDef::DAINTMSK</a></div><div class="ttdeci">__IO uint32_t DAINTMSK</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:839</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2ca54ce1a8d2fa9d1ba6d5987ed5e2cf"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2ca54ce1a8d2fa9d1ba6d5987ed5e2cf">RTC_TypeDef::BKP7R</a></div><div class="ttdeci">__IO uint32_t BKP7R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:675</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2ce7c3842792c506635bb87a21588b58"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2ce7c3842792c506635bb87a21588b58">RTC_TypeDef::CALR</a></div><div class="ttdeci">__IO uint32_t CALR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:663</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2cf9dcd9008924334f20f0dc6b57042e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2cf9dcd9008924334f20f0dc6b57042e">SPI_TypeDef::RXCRCR</a></div><div class="ttdeci">__IO uint32_t RXCRCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:729</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2d08d5f995ed77228eb56741184a1bb6"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2d08d5f995ed77228eb56741184a1bb6">RCC_TypeDef::PLLI2SCFGR</a></div><div class="ttdeci">__IO uint32_t PLLI2SCFGR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:639</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2e45f9c9d67e384187b25334ba0a3e3d"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2e45f9c9d67e384187b25334ba0a3e3d">DAC_TypeDef::DHR12L2</a></div><div class="ttdeci">__IO uint32_t DHR12L2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:312</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2e5a7a96de68a6612affa6df8c309c3d"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2e5a7a96de68a6612affa6df8c309c3d">FSMC_Bank2_3_TypeDef::PMEM2</a></div><div class="ttdeci">__IO uint32_t PMEM2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:507</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2e60bc2eefc18398fb2459d1b44453e5"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2e60bc2eefc18398fb2459d1b44453e5">ETH_TypeDef::RESERVED8</a></div><div class="ttdeci">__IO uint32_t RESERVED8</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:430</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2f02e7acfbd7e549ede84633215eb6a1"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2f02e7acfbd7e549ede84633215eb6a1">FSMC_Bank4_TypeDef::PCR4</a></div><div class="ttdeci">__IO uint32_t PCR4</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:527</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2f692354bde770f2a5e3e1b294ec064b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2f692354bde770f2a5e3e1b294ec064b">IWDG_TypeDef::KR</a></div><div class="ttdeci">__IO uint32_t KR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:587</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2fd59854223e38158b4138ee8e913ab3"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2fd59854223e38158b4138ee8e913ab3">ADC_TypeDef::JOFR4</a></div><div class="ttdeci">__IO uint32_t JOFR4</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:200</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga2ff82b9bf0231645108965aa0febd766"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga2ff82b9bf0231645108965aa0febd766">RCC_TypeDef::AHB3LPENR</a></div><div class="ttdeci">__IO uint32_t AHB3LPENR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:630</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga328d16cc6213783ede54e4059ffd50a3"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga328d16cc6213783ede54e4059ffd50a3">GPIO_TypeDef::OSPEEDR</a></div><div class="ttdeci">__IO uint32_t OSPEEDR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:542</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga328d2fe9ef1d513c3a97d30f98f0047c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga328d2fe9ef1d513c3a97d30f98f0047c">GPIO_TypeDef::IDR</a></div><div class="ttdeci">__IO uint32_t IDR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:544</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga3302e1bcfdfbbfeb58779d0761fb377c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga3302e1bcfdfbbfeb58779d0761fb377c">ADC_TypeDef::SQR1</a></div><div class="ttdeci">__IO uint32_t SQR1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:203</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga35b668314acbac2580b98caf8b9c5c10"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga35b668314acbac2580b98caf8b9c5c10">USB_OTG_OUTEndpointTypeDef::DOEPTSIZ</a></div><div class="ttdeci">__IO uint32_t DOEPTSIZ</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:878</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga38f1ce04678d5141e115cfd6f7b803d1"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga38f1ce04678d5141e115cfd6f7b803d1">ETH_TypeDef::MACA2HR</a></div><div class="ttdeci">__IO uint32_t MACA2HR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:400</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga3903a00940c32a9f09889e08881e7a6a"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga3903a00940c32a9f09889e08881e7a6a">USB_OTG_HostTypeDef::HPTXSTS</a></div><div class="ttdeci">__IO uint32_t HPTXSTS</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:892</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga3a54028253a75a470fccf841178cba46"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga3a54028253a75a470fccf841178cba46">ADC_TypeDef::JDR3</a></div><div class="ttdeci">__IO uint32_t JDR3</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:209</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga3a6cc81e1024f9a93ec7653d32f12dcb"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga3a6cc81e1024f9a93ec7653d32f12dcb">ETH_TypeDef::MACA1HR</a></div><div class="ttdeci">__IO uint32_t MACA1HR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:398</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga3df0d8dfcd1ec958659ffe21eb64fa94"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94">ADC_TypeDef::DR</a></div><div class="ttdeci">__IO uint32_t DR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:211</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga3f82cc749845fb0dd7dfa8121d96b663"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga3f82cc749845fb0dd7dfa8121d96b663">FSMC_Bank4_TypeDef::PMEM4</a></div><div class="ttdeci">__IO uint32_t PMEM4</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:529</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga423b12ab536a1c4fdb1ce63f645822a7"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga423b12ab536a1c4fdb1ce63f645822a7">ETH_TypeDef::MACA2LR</a></div><div class="ttdeci">__IO uint32_t MACA2LR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:401</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga427dda1678f254bd98b1f321d7194a3b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga427dda1678f254bd98b1f321d7194a3b">ADC_TypeDef::JOFR1</a></div><div class="ttdeci">__IO uint32_t JOFR1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:197</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga44135a03aa87fb60abd479a09f71343d"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga44135a03aa87fb60abd479a09f71343d">USB_OTG_INEndpointTypeDef::DTXFSTS</a></div><div class="ttdeci">__IO uint32_t DTXFSTS</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:865</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga44614d7422faffd14af83884e76b2d3e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga44614d7422faffd14af83884e76b2d3e">SDIO_TypeDef::RESP2</a></div><div class="ttdeci">__IO const uint32_t RESP2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:702</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga45e8169adb601f00e411b840f9fbb5af"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga45e8169adb601f00e411b840f9fbb5af">ETH_TypeDef::MACA0LR</a></div><div class="ttdeci">__IO uint32_t MACA0LR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:397</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga4628a8c32f97ef93b15b2b503ef90c75"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga4628a8c32f97ef93b15b2b503ef90c75">DBGMCU_TypeDef::APB2FZ</a></div><div class="ttdeci">__IO uint32_t APB2FZ</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:331</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga46c20c598e9e12f919f0ea47ebcbc90f"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga46c20c598e9e12f919f0ea47ebcbc90f">RCC_TypeDef::AHB1RSTR</a></div><div class="ttdeci">__IO uint32_t AHB1RSTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:614</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga476bae602205d6a49c7e71e2bda28c0a"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga476bae602205d6a49c7e71e2bda28c0a">TIM_TypeDef::BDTR</a></div><div class="ttdeci">__IO uint32_t BDTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:759</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga4808ec597e5a5fefd8a83a9127dd1aec"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga4808ec597e5a5fefd8a83a9127dd1aec">RTC_TypeDef::BKP0R</a></div><div class="ttdeci">__IO uint32_t BKP0R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:668</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga48647281e48d96a96f701cf5ae3f4f63"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga48647281e48d96a96f701cf5ae3f4f63">USB_OTG_DeviceTypeDef::DIEPMSK</a></div><div class="ttdeci">__IO uint32_t DIEPMSK</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:836</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga4c435f0e34ace4421241cd5c3ae87fc2"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga4c435f0e34ace4421241cd5c3ae87fc2">DAC_TypeDef::DHR8R2</a></div><div class="ttdeci">__IO uint32_t DHR8R2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:313</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga4c9b972a304c0e08ca27cbe57627c496"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga4c9b972a304c0e08ca27cbe57627c496">CAN_TypeDef::RESERVED2</a></div><div class="ttdeci">uint32_t RESERVED2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:277</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga4d431ac4a59cbb89ed82a6c6cf9dfc39"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga4d431ac4a59cbb89ed82a6c6cf9dfc39">USB_OTG_HostTypeDef::HAINTMSK</a></div><div class="ttdeci">__IO uint32_t HAINTMSK</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:894</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga4e15c273373694f64b3f70226cb3ac35"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga4e15c273373694f64b3f70226cb3ac35">USB_OTG_DeviceTypeDef::DAINT</a></div><div class="ttdeci">__IO uint32_t DAINT</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:838</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga4e513deb9f58a138ad9f317cc5a3555d"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga4e513deb9f58a138ad9f317cc5a3555d">RTC_TypeDef::ALRMBR</a></div><div class="ttdeci">__IO uint32_t ALRMBR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:656</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga4ec1dd54d976989b7c9e59fb14d974fb"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga4ec1dd54d976989b7c9e59fb14d974fb">RTC_TypeDef::BKP19R</a></div><div class="ttdeci">__IO uint32_t BKP19R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:687</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga4ef7499da5d5beb1cfc81f7be057a7b2"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga4ef7499da5d5beb1cfc81f7be057a7b2">RTC_TypeDef::ALRMBSSR</a></div><div class="ttdeci">__IO uint32_t ALRMBSSR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:666</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga4f006a75f87074f02a532fbeb215bd24"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga4f006a75f87074f02a532fbeb215bd24">USB_OTG_GlobalTypeDef::GOTGCTL</a></div><div class="ttdeci">__IO uint32_t GOTGCTL</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:807</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga50c8425cf8d27268b3272ace0a224a94"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga50c8425cf8d27268b3272ace0a224a94">ETH_TypeDef::MMCTGFMSCCR</a></div><div class="ttdeci">__IO uint32_t MMCTGFMSCCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:412</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga524e134cec519206cb41d0545e382978"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga524e134cec519206cb41d0545e382978">DCMI_TypeDef::MISR</a></div><div class="ttdeci">__IO uint32_t MISR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:344</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga535f5001cfe9967fb7040cd5b081d944"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga535f5001cfe9967fb7040cd5b081d944">_memory::PERIPH_BASE</a></div><div class="ttdeci">uint8_t PERIPH_BASE[PERIPH_SIZE]</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:966</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga55c1058cd74dba0ed0cb8963684b9199"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga55c1058cd74dba0ed0cb8963684b9199">ETH_TypeDef::PTPTSLR</a></div><div class="ttdeci">__IO uint32_t PTPTSLR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:424</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga57bfa1d7c82d97792cbb6c2d366dd48d"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga57bfa1d7c82d97792cbb6c2d366dd48d">_memory::SRAM2_BASE</a></div><div class="ttdeci">uint8_t SRAM2_BASE[SRAM2_SIZE]</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:963</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga581ce491c035ce46db723260377c2032"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga581ce491c035ce46db723260377c2032">ETH_TypeDef::DMARDLAR</a></div><div class="ttdeci">__IO uint32_t DMARDLAR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:436</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga5c0fcd3e7b4c59ab1dd68f6bd8f74e07"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga5c0fcd3e7b4c59ab1dd68f6bd8f74e07">CAN_TypeDef::BTR</a></div><div class="ttdeci">__IO uint32_t BTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:270</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga5c955643593b4aedbe9f84f054d26522"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga5c955643593b4aedbe9f84f054d26522">SDIO_TypeDef::MASK</a></div><div class="ttdeci">__IO uint32_t MASK</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:711</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga5cdef358e9e95b570358e1f6a3a7f492"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga5cdef358e9e95b570358e1f6a3a7f492">DMA_TypeDef::LISR</a></div><div class="ttdeci">__IO uint32_t LISR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:369</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga5d5764c0ec44b661da957e6343f9e7b5"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga5d5764c0ec44b661da957e6343f9e7b5">I2C_TypeDef::TRISE</a></div><div class="ttdeci">__IO uint32_t TRISE</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:578</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga5d5cc7f32884945503dd29f8f6cbb415"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga5d5cc7f32884945503dd29f8f6cbb415">DMA_Stream_TypeDef::FCR</a></div><div class="ttdeci">__IO uint32_t FCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:364</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga5db33a541cebb596c2976d4fc409a611"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga5db33a541cebb596c2976d4fc409a611">_memory::SRAM2_BB_BASE</a></div><div class="ttdeci">uint8_t SRAM2_BB_BASE[SRAM2_SIZE]</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:965</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga5dc05e38e6d591cd88f820b7a0b3f727"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga5dc05e38e6d591cd88f820b7a0b3f727">USB_OTG_DeviceTypeDef::Reserved9</a></div><div class="ttdeci">uint32_t Reserved9</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:841</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga5dd0cb6c861eaf26470f56f451c1edbf"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga5dd0cb6c861eaf26470f56f451c1edbf">USART_TypeDef::GTPR</a></div><div class="ttdeci">__IO uint32_t GTPR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:777</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga5e1322e27c40bf91d172f9673f205c97"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga5e1322e27c40bf91d172f9673f205c97">ADC_Common_TypeDef::CCR</a></div><div class="ttdeci">__IO uint32_t CCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:217</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga5e92ed32c33c92e7ebf6919400ad535b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga5e92ed32c33c92e7ebf6919400ad535b">RCC_TypeDef::AHB2ENR</a></div><div class="ttdeci">__IO uint32_t AHB2ENR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:622</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga5eaefc557573ae7bdc632ef6b6d574b5"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga5eaefc557573ae7bdc632ef6b6d574b5">DBGMCU_TypeDef::APB1FZ</a></div><div class="ttdeci">__IO uint32_t APB1FZ</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:330</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga601d7b0ba761c987db359b2d7173b7e0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga601d7b0ba761c987db359b2d7173b7e0">CRC_TypeDef::IDR</a></div><div class="ttdeci">__IO uint8_t IDR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:294</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6034c7458d8e6030f6dacecf0f1a3a89"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6034c7458d8e6030f6dacecf0f1a3a89">EXTI_TypeDef::EMR</a></div><div class="ttdeci">__IO uint32_t EMR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:457</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6062be7dc144c07e01c303cb49d69ce2"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6062be7dc144c07e01c303cb49d69ce2">FSMC_Bank2_3_TypeDef::ECCR3</a></div><div class="ttdeci">__IO uint32_t ECCR3</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:518</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6095a27d764d06750fc0d642e08f8b2a"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6095a27d764d06750fc0d642e08f8b2a">TIM_TypeDef::CNT</a></div><div class="ttdeci">__IO uint32_t CNT</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:751</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga61282fa74cede526af85fd9d20513646"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga61282fa74cede526af85fd9d20513646">RTC_TypeDef::ALRMASSR</a></div><div class="ttdeci">__IO uint32_t ALRMASSR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:665</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga612edc78d2fa6288392f8ea32c36f7fb"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga612edc78d2fa6288392f8ea32c36f7fb">SDIO_TypeDef::DLEN</a></div><div class="ttdeci">__IO uint32_t DLEN</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:706</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga613f6b76d20c1a513976b920ecd7f4f8"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga613f6b76d20c1a513976b920ecd7f4f8">ADC_TypeDef::JOFR3</a></div><div class="ttdeci">__IO uint32_t JOFR3</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:199</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga614e0b81fce7cf218a357f8a0a3de7b8"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga614e0b81fce7cf218a357f8a0a3de7b8">ETH_TypeDef::MMCTIR</a></div><div class="ttdeci">__IO uint32_t MMCTIR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:407</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6204786b050eb135fabb15784698e86e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6204786b050eb135fabb15784698e86e">RTC_TypeDef::WPR</a></div><div class="ttdeci">__IO uint32_t WPR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:657</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga63872a3017c14a869c647123573dd002"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga63872a3017c14a869c647123573dd002">ETH_TypeDef::MMCRIMR</a></div><div class="ttdeci">__IO uint32_t MMCRIMR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:408</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga63b4d166f4ab5024db6b493a7ab7b640"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga63b4d166f4ab5024db6b493a7ab7b640">DMA_Stream_TypeDef::M0AR</a></div><div class="ttdeci">__IO uint32_t M0AR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:362</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga63d179b7a36a715dce7203858d3be132"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga63d179b7a36a715dce7203858d3be132">RTC_TypeDef::TR</a></div><div class="ttdeci">__IO uint32_t TR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:648</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga640ccb2ccfb6316b88c070362dc29339"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga640ccb2ccfb6316b88c070362dc29339">RTC_TypeDef::BKP18R</a></div><div class="ttdeci">__IO uint32_t BKP18R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:686</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga646bf44e807d10a09f980ace333d33ab"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga646bf44e807d10a09f980ace333d33ab">ETH_TypeDef::PTPTSLUR</a></div><div class="ttdeci">__IO uint32_t PTPTSLUR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:426</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6566f8cfbd1d8aa7e8db046aa35e77db"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6566f8cfbd1d8aa7e8db046aa35e77db">CAN_TypeDef::IER</a></div><div class="ttdeci">__IO uint32_t IER</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:268</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga65bb525a3f4d3ee131f9a7ed899d5eef"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga65bb525a3f4d3ee131f9a7ed899d5eef">ETH_TypeDef::MMCRFAECR</a></div><div class="ttdeci">__IO uint32_t MMCRFAECR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:417</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga65bff76f3af24c37708a1006d54720c7"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga65bff76f3af24c37708a1006d54720c7">SDIO_TypeDef::POWER</a></div><div class="ttdeci">__IO uint32_t POWER</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:696</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga65f69561c1cefe00ce608b7a3c2d8af5"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga65f69561c1cefe00ce608b7a3c2d8af5">USB_OTG_INEndpointTypeDef::DIEPINT</a></div><div class="ttdeci">__IO uint32_t DIEPINT</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:861</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga68bef1da5fd164cf0f884b4209670dc8"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga68bef1da5fd164cf0f884b4209670dc8">SDIO_TypeDef::FIFO</a></div><div class="ttdeci">__IO uint32_t FIFO</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:715</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6921aa1c578a7d17c6e0eb33a73b6630"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6921aa1c578a7d17c6e0eb33a73b6630">CAN_TxMailBox_TypeDef::TIR</a></div><div class="ttdeci">__IO uint32_t TIR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:229</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga69d9432b4272331bffb34e196b57cbdf"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga69d9432b4272331bffb34e196b57cbdf">USB_OTG_GlobalTypeDef::GINTMSK</a></div><div class="ttdeci">__IO uint32_t GINTMSK</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:813</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6a141fc0dab9ee8930465a2da604420f"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6a141fc0dab9ee8930465a2da604420f">USB_OTG_HostTypeDef::HFNUM</a></div><div class="ttdeci">__IO uint32_t HFNUM</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:890</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6ac83fae8377c7b7fcae50fa4211b0e8"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6ac83fae8377c7b7fcae50fa4211b0e8">ADC_TypeDef::SMPR2</a></div><div class="ttdeci">__IO uint32_t SMPR2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:196</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6be3d40baea405ecaf6b38462357dac0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6be3d40baea405ecaf6b38462357dac0">RTC_TypeDef::RESERVED7</a></div><div class="ttdeci">uint32_t RESERVED7</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:667</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6c33564df6eaf97400e0457dde9b14ef"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6c33564df6eaf97400e0457dde9b14ef">RTC_TypeDef::BKP9R</a></div><div class="ttdeci">__IO uint32_t BKP9R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:677</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6ed4c3a0d4588a75078e9f8e376b4d06"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6ed4c3a0d4588a75078e9f8e376b4d06">RTC_TypeDef::BKP13R</a></div><div class="ttdeci">__IO uint32_t BKP13R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:681</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6eefd74b3acdc3c1a88b833fcf5e8d81"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6eefd74b3acdc3c1a88b833fcf5e8d81">USB_OTG_GlobalTypeDef::CID</a></div><div class="ttdeci">__IO uint32_t CID</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:821</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6f7eee5ae8a32c07f9c8fe14281bdaf3"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6f7eee5ae8a32c07f9c8fe14281bdaf3">RTC_TypeDef::BKP12R</a></div><div class="ttdeci">__IO uint32_t BKP12R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:680</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6fe40f7ac1a18c2726b328b5ec02b262"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6fe40f7ac1a18c2726b328b5ec02b262">DMA_TypeDef::HISR</a></div><div class="ttdeci">__IO uint32_t HISR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:370</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6ff264b60a3b40f40d136288e5ec5ba8"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6ff264b60a3b40f40d136288e5ec5ba8">ETH_TypeDef::MMCRGUFCR</a></div><div class="ttdeci">__IO uint32_t MMCRGUFCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:419</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga6ff3c8a6647ae7e5dfcd2ccfbfed4948"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga6ff3c8a6647ae7e5dfcd2ccfbfed4948">USB_OTG_GlobalTypeDef::HNPTXSTS</a></div><div class="ttdeci">__IO uint32_t HNPTXSTS</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:818</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga7015e1046dbd3ea8783b33dc11a69e52"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga7015e1046dbd3ea8783b33dc11a69e52">IWDG_TypeDef::RLR</a></div><div class="ttdeci">__IO uint32_t RLR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:589</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga716e172ed03ae049eb501ad83207b4ed"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga716e172ed03ae049eb501ad83207b4ed">USB_OTG_INEndpointTypeDef::Reserved18</a></div><div class="ttdeci">uint32_t Reserved18</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:866</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga71d932b554a5548e5d85ed81e58c1ed0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga71d932b554a5548e5d85ed81e58c1ed0">ETH_TypeDef::MMCTGFCR</a></div><div class="ttdeci">__IO uint32_t MMCTGFCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:414</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga73861fa74b83973fa1b5f92735c042ef"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga73861fa74b83973fa1b5f92735c042ef">FSMC_Bank2_3_TypeDef::PCR3</a></div><div class="ttdeci">__IO uint32_t PCR3</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:513</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga75ade4a9b3d40781fd80ce3e6589e98b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga75ade4a9b3d40781fd80ce3e6589e98b">TIM_TypeDef::OR</a></div><div class="ttdeci">__IO uint32_t OR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:762</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga75e0cc079831adcc051df456737d3ae4"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga75e0cc079831adcc051df456737d3ae4">ADC_TypeDef::JSQR</a></div><div class="ttdeci">__IO uint32_t JSQR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:206</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga760f86a1a18dffffda54fc15a977979f"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga760f86a1a18dffffda54fc15a977979f">ADC_Common_TypeDef::CDR</a></div><div class="ttdeci">__IO uint32_t CDR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:218</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga78a4f036f29e552acad6a442fbb69420"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga78a4f036f29e552acad6a442fbb69420">USB_OTG_OUTEndpointTypeDef::DOEPDMA</a></div><div class="ttdeci">__IO uint32_t DOEPDMA</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:879</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga78a5aa9dd5694c48a7d8e66888a46450"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga78a5aa9dd5694c48a7d8e66888a46450">RCC_TypeDef::AHB2RSTR</a></div><div class="ttdeci">__IO uint32_t AHB2RSTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:615</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga7da5d372374bc59e9b9af750b01d6a78"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga7da5d372374bc59e9b9af750b01d6a78">RCC_TypeDef::APB1RSTR</a></div><div class="ttdeci">__IO uint32_t APB1RSTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:618</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga7da778413f6db1f83ae25caed03382d4"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga7da778413f6db1f83ae25caed03382d4">SDIO_TypeDef::RESP1</a></div><div class="ttdeci">__IO const uint32_t RESP1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:701</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga7dba9527df73350f35683140d73a5f8d"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga7dba9527df73350f35683140d73a5f8d">ETH_TypeDef::DMATDLAR</a></div><div class="ttdeci">__IO uint32_t DMATDLAR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:437</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga7f11f42ba9d3bc5cd4a4f5ea0214608e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga7f11f42ba9d3bc5cd4a4f5ea0214608e">CAN_FIFOMailBox_TypeDef::RDHR</a></div><div class="ttdeci">__IO uint32_t RDHR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:244</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga7f7d80b45b7574463d7030fc8a464582"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga7f7d80b45b7574463d7030fc8a464582">CAN_FilterRegister_TypeDef::FR2</a></div><div class="ttdeci">__IO uint32_t FR2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:254</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga804c7e15dbb587c7ea25511f6a7809f7"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga804c7e15dbb587c7ea25511f6a7809f7">DAC_TypeDef::DHR12R2</a></div><div class="ttdeci">__IO uint32_t DHR12R2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:311</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga8218d6e11dae5d4468c69303dec0b4fc"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga8218d6e11dae5d4468c69303dec0b4fc">FSMC_Bank4_TypeDef::SR4</a></div><div class="ttdeci">__IO uint32_t SR4</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:528</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga8249a3955aace28d92109b391311eb30"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga8249a3955aace28d92109b391311eb30">CRC_TypeDef::RESERVED1</a></div><div class="ttdeci">uint16_t RESERVED1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:296</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga830a2b58d0eb53a7ec8f9816103e3bc1"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga830a2b58d0eb53a7ec8f9816103e3bc1">USB_OTG_HostChannelTypeDef::HCINT</a></div><div class="ttdeci">__IO uint32_t HCINT</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:904</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga8371acd36203fa875cdea3f29b94d1fb"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga8371acd36203fa875cdea3f29b94d1fb">USB_OTG_DeviceTypeDef::DSTS</a></div><div class="ttdeci">__IO uint32_t DSTS</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:834</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga840b32fa57faa544c3000ae1d08564c7"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga840b32fa57faa544c3000ae1d08564c7">USB_OTG_INEndpointTypeDef::DIEPCTL</a></div><div class="ttdeci">__IO uint32_t DIEPCTL</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:859</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga84303738f0e64d5303c027932c055d87"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga84303738f0e64d5303c027932c055d87">_memory::FLASH_BASE</a></div><div class="ttdeci">uint8_t FLASH_BASE[FLASH_SIZE]</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:959</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga84c491be6c66b1d5b6a2efd0740b3d0c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga84c491be6c66b1d5b6a2efd0740b3d0c">FLASH_TypeDef::KEYR</a></div><div class="ttdeci">__IO uint32_t KEYR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:471</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga85fdb75569bd7ea26fa48544786535be"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga85fdb75569bd7ea26fa48544786535be">TIM_TypeDef::CCR4</a></div><div class="ttdeci">__IO uint32_t CCR4</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:758</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga876dd0a8546697065f406b7543e27af2"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga876dd0a8546697065f406b7543e27af2">ADC_Common_TypeDef::CSR</a></div><div class="ttdeci">__IO uint32_t CSR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:216</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga87c7687c35332bf5ee86473043652146"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga87c7687c35332bf5ee86473043652146">ETH_TypeDef::MACMIIDR</a></div><div class="ttdeci">__IO uint32_t MACMIIDR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:386</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga87e3001757a0cd493785f1f3337dd0e8"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga87e3001757a0cd493785f1f3337dd0e8">CAN_TypeDef::TSR</a></div><div class="ttdeci">__IO uint32_t TSR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:265</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga89623ee198737b29dc0a803310605a83"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga89623ee198737b29dc0a803310605a83">FSMC_Bank2_3_TypeDef::SR2</a></div><div class="ttdeci">__IO uint32_t SR2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:506</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga896bbb7153af0b67ad772360feaceeb4"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga896bbb7153af0b67ad772360feaceeb4">DAC_TypeDef::SWTRIGR</a></div><div class="ttdeci">__IO uint32_t SWTRIGR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:307</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga8a868e5e76b52ced04c536be3dee08ec"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga8a868e5e76b52ced04c536be3dee08ec">RTC_TypeDef::SSR</a></div><div class="ttdeci">__IO uint32_t SSR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:658</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga8ad4e3dbde1518ecde5d979c2a89a76a"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga8ad4e3dbde1518ecde5d979c2a89a76a">ETH_TypeDef::MACFFR</a></div><div class="ttdeci">__IO uint32_t MACFFR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:382</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga8f35b3865c1f5fce934c1d48b9a63442"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga8f35b3865c1f5fce934c1d48b9a63442">ETH_TypeDef::MACDBGR</a></div><div class="ttdeci">__IO uint32_t MACDBGR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:393</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga8f47c0f21e22b98bbc2c9f3b6342fbb8"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga8f47c0f21e22b98bbc2c9f3b6342fbb8">ETH_TypeDef::PTPTSAR</a></div><div class="ttdeci">__IO uint32_t PTPTSAR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:427</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga900f9f888342fbdd8ee07e3ee1d4b73c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga900f9f888342fbdd8ee07e3ee1d4b73c">ETH_TypeDef::DMACHTBAR</a></div><div class="ttdeci">__IO uint32_t DMACHTBAR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:446</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga905a2b4ece4882eb67c710e0db10e960"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga905a2b4ece4882eb67c710e0db10e960">USB_OTG_OUTEndpointTypeDef::DOEPCTL</a></div><div class="ttdeci">__IO uint32_t DOEPCTL</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:874</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga907d8154c80b7e385478943f90b17a3b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga907d8154c80b7e385478943f90b17a3b">RCC_TypeDef::CIR</a></div><div class="ttdeci">__IO uint32_t CIR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:613</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga90eb3fc2642288d3e7ca2416493bf8ae"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga90eb3fc2642288d3e7ca2416493bf8ae">_memory::BKPSRAM_BB_BASE</a></div><div class="ttdeci">uint8_t BKPSRAM_BB_BASE[BKPSRAM_SIZE]</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:969</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga90f7c1cf22683459c632d6040366eddf"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga90f7c1cf22683459c632d6040366eddf">CAN_TxMailBox_TypeDef::TDHR</a></div><div class="ttdeci">__IO uint32_t TDHR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:232</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga919b70dd8762e44263a02dfbafc7b8ce"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga919b70dd8762e44263a02dfbafc7b8ce">DCMI_TypeDef::CWSTRTR</a></div><div class="ttdeci">__IO uint32_t CWSTRTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:348</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga92036953ac673803fe001d843fea508b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga92036953ac673803fe001d843fea508b">CAN_FilterRegister_TypeDef::FR1</a></div><div class="ttdeci">__IO uint32_t FR1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:253</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9274ceea3b2c6d5c1903d0a7abad91a1"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9274ceea3b2c6d5c1903d0a7abad91a1">ADC_TypeDef::JDR4</a></div><div class="ttdeci">__IO uint32_t JDR4</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:210</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga928fd38284165374eb5aa85ed8d4e6cb"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga928fd38284165374eb5aa85ed8d4e6cb">USB_OTG_GlobalTypeDef::HPTXFSIZ</a></div><div class="ttdeci">__IO uint32_t HPTXFSIZ</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:823</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga92ff1fe799bb33d13efbaa1195867781"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga92ff1fe799bb33d13efbaa1195867781">ETH_TypeDef::MACVLANTR</a></div><div class="ttdeci">__IO uint32_t MACVLANTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:388</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga93412b352267d3faf0bd2dbac590b69e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga93412b352267d3faf0bd2dbac590b69e">USB_OTG_GlobalTypeDef::DIEPTXF0_HNPTXFSIZ</a></div><div class="ttdeci">__IO uint32_t DIEPTXF0_HNPTXFSIZ</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:817</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9543592bda60cb5261075594bdeedac9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9543592bda60cb5261075594bdeedac9">GPIO_TypeDef::OTYPER</a></div><div class="ttdeci">__IO uint32_t OTYPER</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:541</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga955cad1aab7fb2d5b6e216cb29b5e7e2"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga955cad1aab7fb2d5b6e216cb29b5e7e2">FSMC_Bank4_TypeDef::PATT4</a></div><div class="ttdeci">__IO uint32_t PATT4</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:530</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9563d8a88d0db403b8357331bea83a2e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9563d8a88d0db403b8357331bea83a2e">CAN_FIFOMailBox_TypeDef::RDTR</a></div><div class="ttdeci">__IO uint32_t RDTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:242</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9590269cba8412f1be96b0ddb846ef44"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9590269cba8412f1be96b0ddb846ef44">DAC_TypeDef::DHR8RD</a></div><div class="ttdeci">__IO uint32_t DHR8RD</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:316</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga96a3d1a050982fccc23c2e6dbe0de068"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga96a3d1a050982fccc23c2e6dbe0de068">SDIO_TypeDef::DCTRL</a></div><div class="ttdeci">__IO uint32_t DCTRL</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:707</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga97e40d9928fa25a5628d6442f0aa6c0f"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga97e40d9928fa25a5628d6442f0aa6c0f">ADC_TypeDef::SQR3</a></div><div class="ttdeci">__IO uint32_t SQR3</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:205</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9925d279a01c6e9713426315e2e44c87"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9925d279a01c6e9713426315e2e44c87">USB_OTG_GlobalTypeDef::GRXSTSR</a></div><div class="ttdeci">__IO uint32_t GRXSTSR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:814</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9980c4a55080745a11528f8c7ffa1c66"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9980c4a55080745a11528f8c7ffa1c66">USB_OTG_GlobalTypeDef::GINTSTS</a></div><div class="ttdeci">__IO uint32_t GINTSTS</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:812</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga99c6c50a3e3235c81b98a428ebd33d4c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga99c6c50a3e3235c81b98a428ebd33d4c">USB_OTG_DeviceTypeDef::DIEPEMPMSK</a></div><div class="ttdeci">__IO uint32_t DIEPEMPMSK</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:845</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9a163a0d5cfce7238b38067a1a53b324"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9a163a0d5cfce7238b38067a1a53b324">USB_OTG_DeviceTypeDef::DCFG</a></div><div class="ttdeci">__IO uint32_t DCFG</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:832</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9c1bc909ec5ed32df45444488ea6668b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9c1bc909ec5ed32df45444488ea6668b">FSMC_Bank2_3_TypeDef::PATT2</a></div><div class="ttdeci">__IO uint32_t PATT2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:508</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9c49de2e699886d6604fd2b3d376a0e9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9c49de2e699886d6604fd2b3d376a0e9">ETH_TypeDef::DMACHRDR</a></div><div class="ttdeci">__IO uint32_t DMACHRDR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:445</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9cb55206b29a8c16354747c556ab8bea"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9cb55206b29a8c16354747c556ab8bea">FLASH_TypeDef::ACR</a></div><div class="ttdeci">__IO uint32_t ACR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:470</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9cc4ec74be864c929261e0810f2fd7f0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9cc4ec74be864c929261e0810f2fd7f0">DCMI_TypeDef::ESCR</a></div><div class="ttdeci">__IO uint32_t ESCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:346</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9d4c753f09cbffdbe5c55008f0e8b180"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9d4c753f09cbffdbe5c55008f0e8b180">TIM_TypeDef::PSC</a></div><div class="ttdeci">__IO uint32_t PSC</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:752</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9e0c029846e94bf08ac8edb35b30ecb2"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9e0c029846e94bf08ac8edb35b30ecb2">USB_OTG_DeviceTypeDef::Reserved40</a></div><div class="ttdeci">uint32_t Reserved40</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:848</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9e7c3d04e4dcf975939eeaac246b25d0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9e7c3d04e4dcf975939eeaac246b25d0">ETH_TypeDef::DMASR</a></div><div class="ttdeci">__IO uint32_t DMASR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:438</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9ea1e1c6615eb3bd70eb328dba65fc87"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9ea1e1c6615eb3bd70eb328dba65fc87">ETH_TypeDef::MACMIIAR</a></div><div class="ttdeci">__IO uint32_t MACMIIAR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:385</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9eae93b6cc13d4d25e12f2224e2369c9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9eae93b6cc13d4d25e12f2224e2369c9">EXTI_TypeDef::SWIER</a></div><div class="ttdeci">__IO uint32_t SWIER</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:460</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9f8712dfef7125c0bb39db11f2b7416b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9f8712dfef7125c0bb39db11f2b7416b">ADC_TypeDef::LTR</a></div><div class="ttdeci">__IO uint32_t LTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:202</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9fb9e43255829e50b9e5416d58ae11be"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9fb9e43255829e50b9e5416d58ae11be">USB_OTG_HostTypeDef::HAINT</a></div><div class="ttdeci">__IO uint32_t HAINT</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:893</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_ga9fbcd0d73c2b2229b9f95743f280382c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#ga9fbcd0d73c2b2229b9f95743f280382c">_memory::PERIPH_BB_BASE</a></div><div class="ttdeci">uint8_t PERIPH_BB_BASE[PERIPH_BB_SIZE]</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:968</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaa0c41c8883cb0812d6aaf956c393584b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaa0c41c8883cb0812d6aaf956c393584b">SPI_TypeDef::I2SCFGR</a></div><div class="ttdeci">__IO uint32_t I2SCFGR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:731</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaa0f7c828c46ae6f6bc9f66f11720bbe6"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaa0f7c828c46ae6f6bc9f66f11720bbe6">EXTI_TypeDef::FTSR</a></div><div class="ttdeci">__IO uint32_t FTSR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:459</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaa15b972f30ee47f5df0d3ebc8866509d"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaa15b972f30ee47f5df0d3ebc8866509d">ETH_TypeDef::DMAOMR</a></div><div class="ttdeci">__IO uint32_t DMAOMR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:439</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaa15bc4ab9217b295560dbda2235c745a"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaa15bc4ab9217b295560dbda2235c745a">USB_OTG_HostTypeDef::HCFG</a></div><div class="ttdeci">__IO uint32_t HCFG</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:888</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaa196fddf0ba7d6e3ce29bdb04eb38b94"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaa196fddf0ba7d6e3ce29bdb04eb38b94">DCMI_TypeDef::RISR</a></div><div class="ttdeci">__IO uint32_t RISR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:342</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaa1b1b7107fcf35abe39d20f5dfc230ee"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaa1b1b7107fcf35abe39d20f5dfc230ee">TIM_TypeDef::RCR</a></div><div class="ttdeci">__IO uint32_t RCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:754</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaa3ccc5d081bbee3c61ae9aa5e0c83af9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaa3ccc5d081bbee3c61ae9aa5e0c83af9">DCMI_TypeDef::CWSIZER</a></div><div class="ttdeci">__IO uint32_t CWSIZER</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:349</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaa657aa42398bc8294976632d778b6db4"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaa657aa42398bc8294976632d778b6db4">ETH_TypeDef::PTPTSCR</a></div><div class="ttdeci">__IO uint32_t PTPTSCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:421</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaa710505be03a41981c35bacc7ce20746"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaa710505be03a41981c35bacc7ce20746">DAC_TypeDef::DOR1</a></div><div class="ttdeci">__IO uint32_t DOR1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:317</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaa74faef460a0c655439bcf20caac1653"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaa74faef460a0c655439bcf20caac1653">SDIO_TypeDef::RESP4</a></div><div class="ttdeci">__IO const uint32_t RESP4</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:704</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaa7d2bd5481ee985778c410a7e5826b71"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaa7d2bd5481ee985778c410a7e5826b71">CRC_TypeDef::RESERVED0</a></div><div class="ttdeci">uint8_t RESERVED0</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:295</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaa94197378e20fc739d269be49d9c5d40"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaa94197378e20fc739d269be49d9c5d40">SDIO_TypeDef::CLKCR</a></div><div class="ttdeci">__IO uint32_t CLKCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:697</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaaa251a80daa57ad0bd7db75cb3b9cdec"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaaa251a80daa57ad0bd7db75cb3b9cdec">RTC_TypeDef::BKP2R</a></div><div class="ttdeci">__IO uint32_t BKP2R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:670</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaaa6f4cf1f16aaa6d17ec6c410db76acf"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaaa6f4cf1f16aaa6d17ec6c410db76acf">CAN_TypeDef::FM1R</a></div><div class="ttdeci">__IO uint32_t FM1R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:276</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaab440b0ad8631f5666dd32768a89cf60"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaab440b0ad8631f5666dd32768a89cf60">ADC_TypeDef::SQR2</a></div><div class="ttdeci">__IO uint32_t SQR2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:204</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaad6309afe126da26921191697d7e5c43"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaad6309afe126da26921191697d7e5c43">ETH_TypeDef::DMARPDR</a></div><div class="ttdeci">__IO uint32_t DMARPDR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:435</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaade2881a3e408bfd106b27f78bbbcfc9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaade2881a3e408bfd106b27f78bbbcfc9">RTC_TypeDef::BKP10R</a></div><div class="ttdeci">__IO uint32_t BKP10R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:678</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaadfb486dd07e2fd02fb491733deffd9b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaadfb486dd07e2fd02fb491733deffd9b">ETH_TypeDef::MACA1LR</a></div><div class="ttdeci">__IO uint32_t MACA1LR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:399</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaae0256ae42106ee7f87fc7e5bdb779d4"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaae0256ae42106ee7f87fc7e5bdb779d4">CAN_TypeDef::FS1R</a></div><div class="ttdeci">__IO uint32_t FS1R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:278</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaae70b1922167eb58d564cb82d39fd10b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaae70b1922167eb58d564cb82d39fd10b">RCC_TypeDef::AHB1LPENR</a></div><div class="ttdeci">__IO uint32_t AHB1LPENR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:628</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaaef3da59eaf7c6dfdf9a12fd60ce58a8"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaaef3da59eaf7c6dfdf9a12fd60ce58a8">RCC_TypeDef::SSCGR</a></div><div class="ttdeci">__IO uint32_t SSCGR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:638</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaaf76271f4ab0b3deb3ceb6e2ac0d62d0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaaf76271f4ab0b3deb3ceb6e2ac0d62d0">CAN_TypeDef::FA1R</a></div><div class="ttdeci">__IO uint32_t FA1R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:282</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab0cb1d704ee64c62ad5be55522a2683a"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab0cb1d704ee64c62ad5be55522a2683a">FSMC_Bank2_3_TypeDef::PCR2</a></div><div class="ttdeci">__IO uint32_t PCR2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:505</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab0ec7102960640751d44e92ddac994f0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0">ADC_TypeDef::CR1</a></div><div class="ttdeci">__IO uint32_t CR1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:193</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab13e106cc2eca92d1f4022df3bfdbcd7"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab13e106cc2eca92d1f4022df3bfdbcd7">RTC_TypeDef::BKP4R</a></div><div class="ttdeci">__IO uint32_t BKP4R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:672</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab2c5389c9ff4ac188cd498b8f7170968"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab2c5389c9ff4ac188cd498b8f7170968">RCC_TypeDef::APB2RSTR</a></div><div class="ttdeci">__IO uint32_t APB2RSTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:619</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab36c409d0a009e3ce5a89ac55d3ff194"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab36c409d0a009e3ce5a89ac55d3ff194">SYSCFG_TypeDef::MEMRMP</a></div><div class="ttdeci">__IO uint32_t MEMRMP</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:557</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab3c49a96815fcbee63d95e1e74f20e75"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab3c49a96815fcbee63d95e1e74f20e75">RTC_TypeDef::ISR</a></div><div class="ttdeci">__IO uint32_t ISR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:651</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab40c89c59391aaa9d9a8ec011dd0907a"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a">CRC_TypeDef::CR</a></div><div class="ttdeci">__IO uint32_t CR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:297</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab4e4328504fd66285df8264d410deefd"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab4e4328504fd66285df8264d410deefd">SPI_TypeDef::TXCRCR</a></div><div class="ttdeci">__IO uint32_t TXCRCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:730</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab5bb348210fdd9a5538eb57abc5a5673"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab5bb348210fdd9a5538eb57abc5a5673">ETH_TypeDef::DMACHTDR</a></div><div class="ttdeci">__IO uint32_t DMACHTDR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:444</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab5c57ffed0351fa064038939a6c0bbf6"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab5c57ffed0351fa064038939a6c0bbf6">I2C_TypeDef::OAR2</a></div><div class="ttdeci">__IO uint32_t OAR2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:573</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab62b876c61e11199cf5c37aa944a5fed"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab62b876c61e11199cf5c37aa944a5fed">USB_OTG_DeviceTypeDef::DINEP1MSK</a></div><div class="ttdeci">__IO uint32_t DINEP1MSK</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:849</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab6bed862c0d0476ff4f89f7b9bf3e130"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab6bed862c0d0476ff4f89f7b9bf3e130">RTC_TypeDef::BKP5R</a></div><div class="ttdeci">__IO uint32_t BKP5R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:673</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab8b4520c137846f0a128146144514419"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab8b4520c137846f0a128146144514419">ETH_TypeDef::MACA0HR</a></div><div class="ttdeci">__IO uint32_t MACA0HR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:396</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab9087f2f31dd5edf59de6a59ae4e67ae"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab9087f2f31dd5edf59de6a59ae4e67ae">TIM_TypeDef::DMAR</a></div><div class="ttdeci">__IO uint32_t DMAR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:761</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab90aa584f07eeeac364a67f5e05faa93"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab90aa584f07eeeac364a67f5e05faa93">TIM_TypeDef::CCR2</a></div><div class="ttdeci">__IO uint32_t CCR2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:756</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab97f3e9584dda705dc10a5f4c5f6e636"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab97f3e9584dda705dc10a5f4c5f6e636">RTC_TypeDef::CALIBR</a></div><div class="ttdeci">__IO uint32_t CALIBR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:654</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gab9be89a916ee5904381e10da10e5e8e9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gab9be89a916ee5904381e10da10e5e8e9">SPI_TypeDef::I2SPR</a></div><div class="ttdeci">__IO uint32_t I2SPR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:732</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaba03fea9c1bb2242d963e29f1b94d25e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaba03fea9c1bb2242d963e29f1b94d25e">FSMC_Bank2_3_TypeDef::PATT3</a></div><div class="ttdeci">__IO uint32_t PATT3</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:516</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaba51c57f9506e14a6f5983526c78943b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaba51c57f9506e14a6f5983526c78943b">RCC_TypeDef::APB2LPENR</a></div><div class="ttdeci">__IO uint32_t APB2LPENR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:633</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaba8981e4f06cfb3db7d9959242052f80"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaba8981e4f06cfb3db7d9959242052f80">FSMC_Bank2_3_TypeDef::PMEM3</a></div><div class="ttdeci">__IO uint32_t PMEM3</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:515</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaba9fb810b0cf6cbc1280c5c63be2418b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaba9fb810b0cf6cbc1280c5c63be2418b">DAC_TypeDef::DOR2</a></div><div class="ttdeci">__IO uint32_t DOR2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:318</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gabbb2f4f89e7d8c3242365b4506e43217"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gabbb2f4f89e7d8c3242365b4506e43217">ETH_TypeDef::MACPMTCSR</a></div><div class="ttdeci">__IO uint32_t MACPMTCSR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:391</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gabeb6fb580a8fd128182aa9ba2738ac2c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gabeb6fb580a8fd128182aa9ba2738ac2c">RTC_TypeDef::TSDR</a></div><div class="ttdeci">__IO uint32_t TSDR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:661</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gabeed38529bd7b8de082e490e5d4f1727"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gabeed38529bd7b8de082e490e5d4f1727">GPIO_TypeDef::PUPDR</a></div><div class="ttdeci">__IO uint32_t PUPDR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:543</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gabff7fffd2b5a718715a130006590c75c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gabff7fffd2b5a718715a130006590c75c">GPIO_TypeDef::ODR</a></div><div class="ttdeci">__IO uint32_t ODR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:545</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac0018930ee9f18afda25b695b9a4ec16"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac0018930ee9f18afda25b695b9a4ec16">CAN_TypeDef::RESERVED4</a></div><div class="ttdeci">uint32_t RESERVED4</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:281</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac005b1a5bc52634d5a34578cc9d2c3f6"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac005b1a5bc52634d5a34578cc9d2c3f6">RTC_TypeDef::ALRMAR</a></div><div class="ttdeci">__IO uint32_t ALRMAR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:655</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac011ddcfe531f8e16787ea851c1f3667"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac011ddcfe531f8e16787ea851c1f3667">WWDG_TypeDef::CFR</a></div><div class="ttdeci">__IO uint32_t CFR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:787</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac1085f6aae54b353c30871fe90c59851"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac1085f6aae54b353c30871fe90c59851">RTC_TypeDef::BKP8R</a></div><div class="ttdeci">__IO uint32_t BKP8R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:676</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac1d0619a44758dcaeeda5c0b9c22f784"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac1d0619a44758dcaeeda5c0b9c22f784">USB_OTG_HostChannelTypeDef::HCCHAR</a></div><div class="ttdeci">__IO uint32_t HCCHAR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:902</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac25dd6b9e3d55e17589195b461c5ec80"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac25dd6b9e3d55e17589195b461c5ec80">GPIO_TypeDef::BSRR</a></div><div class="ttdeci">__IO uint32_t BSRR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:546</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac2bb55b037b800a25852736afdd7a258"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac2bb55b037b800a25852736afdd7a258">DAC_TypeDef::DHR12R1</a></div><div class="ttdeci">__IO uint32_t DHR12R1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:308</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac38ac55e4148686564478e95f345b833"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac38ac55e4148686564478e95f345b833">USB_OTG_GlobalTypeDef::GAHBCFG</a></div><div class="ttdeci">__IO uint32_t GAHBCFG</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:809</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac42b829c02429cb9363563f7eb9d58ed"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac42b829c02429cb9363563f7eb9d58ed">ETH_TypeDef::MACIMR</a></div><div class="ttdeci">__IO uint32_t MACIMR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:395</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac4ac04e673b5b8320d53f7b0947db902"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac4ac04e673b5b8320d53f7b0947db902">ETH_TypeDef::RESERVED1</a></div><div class="ttdeci">uint32_t RESERVED1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:392</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac4f7bf4cb172024bfc940c00167cd04e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac4f7bf4cb172024bfc940c00167cd04e">DMA_TypeDef::LIFCR</a></div><div class="ttdeci">__IO uint32_t LIFCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:371</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac53cd7a08093a4ae8f4de4bcff67a64f"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac53cd7a08093a4ae8f4de4bcff67a64f">FSMC_Bank4_TypeDef::PIO4</a></div><div class="ttdeci">__IO uint32_t PIO4</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:531</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac55c27aeea4107813c1e7da3fcf46961"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac55c27aeea4107813c1e7da3fcf46961">DMA_TypeDef::HIFCR</a></div><div class="ttdeci">__IO uint32_t HIFCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:372</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac5b3c8be61045a304d3076d4714d29f2"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac5b3c8be61045a304d3076d4714d29f2">RTC_TypeDef::WUTR</a></div><div class="ttdeci">__IO uint32_t WUTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:653</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac5d3a4bffd921da5d69f9a601263b573"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac5d3a4bffd921da5d69f9a601263b573">USB_OTG_DeviceTypeDef::DTHRCTL</a></div><div class="ttdeci">__IO uint32_t DTHRCTL</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:844</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac60f13e6619724747e61cfbff55b9fab"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac60f13e6619724747e61cfbff55b9fab">RTC_TypeDef::BKP14R</a></div><div class="ttdeci">__IO uint32_t BKP14R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:682</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac66d5e2d3459cff89794c47dbc8f7228"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac66d5e2d3459cff89794c47dbc8f7228">RTC_TypeDef::BKP11R</a></div><div class="ttdeci">__IO uint32_t BKP11R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:679</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac6fe9e194ed9d08bf6bd28ceb80ac4b0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac6fe9e194ed9d08bf6bd28ceb80ac4b0">ETH_TypeDef::DMARSWTR</a></div><div class="ttdeci">__IO uint32_t DMARSWTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:442</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac7c83f52956da4c75f4946348f7bfa1a"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac7c83f52956da4c75f4946348f7bfa1a">_memory::SRAM1_BASE</a></div><div class="ttdeci">uint8_t SRAM1_BASE[SRAM1_SIZE]</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:962</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac88901e2eb35079b7b58a185e6bf554c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac88901e2eb35079b7b58a185e6bf554c">RCC_TypeDef::APB1ENR</a></div><div class="ttdeci">__IO uint32_t APB1ENR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:625</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac88d0add27755615a9390fec8c64dafc"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac88d0add27755615a9390fec8c64dafc">_memory::SRAM1_BB_BASE</a></div><div class="ttdeci">uint8_t SRAM1_BB_BASE[SRAM1_SIZE]</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:964</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gac9b4c6c5b29f3461ce3f875eea69f35b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gac9b4c6c5b29f3461ce3f875eea69f35b">RTC_TypeDef::PRER</a></div><div class="ttdeci">__IO uint32_t PRER</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:652</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gacc269320aff0a6482730224a4b641a59"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gacc269320aff0a6482730224a4b641a59">DAC_TypeDef::DHR12LD</a></div><div class="ttdeci">__IO uint32_t DHR12LD</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:315</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gacc7bb47dddd2d94de124f74886d919be"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gacc7bb47dddd2d94de124f74886d919be">RCC_TypeDef::APB2ENR</a></div><div class="ttdeci">__IO uint32_t APB2ENR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:626</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gacc968fd160f83749ad4176ad8cb36fe0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gacc968fd160f83749ad4176ad8cb36fe0">USB_OTG_DeviceTypeDef::DVBUSPULSE</a></div><div class="ttdeci">__IO uint32_t DVBUSPULSE</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:843</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaccf4141cee239380d0ad4634ee21dbf6"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaccf4141cee239380d0ad4634ee21dbf6">CAN_TypeDef::RF0R</a></div><div class="ttdeci">__IO uint32_t RF0R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:266</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gacd6db2394f2b493a873059464d5b0e18"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gacd6db2394f2b493a873059464d5b0e18">_memory::CCMDATARAM_BASE</a></div><div class="ttdeci">uint8_t CCMDATARAM_BASE[CCMDATARAM_SIZE]</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:960</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gacdaa650fcd63730825479f6e8f70d4c0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gacdaa650fcd63730825479f6e8f70d4c0">RCC_TypeDef::AHB3ENR</a></div><div class="ttdeci">__IO uint32_t AHB3ENR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:623</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gacdd4c1b5466be103fb2bb2a225b1d3a9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gacdd4c1b5466be103fb2bb2a225b1d3a9">CAN_TypeDef::MSR</a></div><div class="ttdeci">__IO uint32_t MSR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:264</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gace450027b4b33f921dd8edd3425a717c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gace450027b4b33f921dd8edd3425a717c">SPI_TypeDef::CRCPR</a></div><div class="ttdeci">__IO uint32_t CRCPR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:728</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gace5daae0e2da2f05a6b63f3f68109284"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gace5daae0e2da2f05a6b63f3f68109284">_memory::FLASH_OTP_BASE</a></div><div class="ttdeci">uint8_t FLASH_OTP_BASE[FLASH_OTP_SIZE]</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:961</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gacefca4fd83c4b7846ae6d3cfe7bb8df9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gacefca4fd83c4b7846ae6d3cfe7bb8df9">I2C_TypeDef::SR1</a></div><div class="ttdeci">__IO uint32_t SR1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:575</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gacf0114902a52b7ffcc343e06484b3623"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gacf0114902a52b7ffcc343e06484b3623">ETH_TypeDef::DMATPDR</a></div><div class="ttdeci">__IO uint32_t DMATPDR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:434</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gacf3f7ecbf774d8d505655ac7f24761fc"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gacf3f7ecbf774d8d505655ac7f24761fc">ETH_TypeDef::DMACHRBAR</a></div><div class="ttdeci">__IO uint32_t DMACHRBAR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:447</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gacfe7efaa61db86840767dff6d73f8695"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gacfe7efaa61db86840767dff6d73f8695">USB_OTG_INEndpointTypeDef::Reserved04</a></div><div class="ttdeci">uint32_t Reserved04</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:860</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gacfef9b6d7da4271943edc04d7dfdf595"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gacfef9b6d7da4271943edc04d7dfdf595">FLASH_TypeDef::OPTCR</a></div><div class="ttdeci">__IO uint32_t OPTCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:475</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gad02ff09f7ce33f093ad04b84fee2bdec"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gad02ff09f7ce33f093ad04b84fee2bdec">ETH_TypeDef::MACA3HR</a></div><div class="ttdeci">__IO uint32_t MACA3HR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:402</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gad0a200e12acad17a5c7d2059159ea7e1"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gad0a200e12acad17a5c7d2059159ea7e1">DAC_TypeDef::DHR8R1</a></div><div class="ttdeci">__IO uint32_t DHR8R1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:310</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gad1e11eb1200e64e0563e3576bf258194"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gad1e11eb1200e64e0563e3576bf258194">ETH_TypeDef::DMABMR</a></div><div class="ttdeci">__IO uint32_t DMABMR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:433</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gad2f2eb2fb4b93e21515b10e920e719b6"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gad2f2eb2fb4b93e21515b10e920e719b6">RTC_TypeDef::BKP16R</a></div><div class="ttdeci">__IO uint32_t BKP16R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:684</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gad57490cb3a07132702f96d8b5d547c89"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gad57490cb3a07132702f96d8b5d547c89">ETH_TypeDef::MMCCR</a></div><div class="ttdeci">__IO uint32_t MMCCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:405</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gad715951248900b9a7c8c9ddb688bb3a0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gad715951248900b9a7c8c9ddb688bb3a0">USB_OTG_HostChannelTypeDef::HCSPLT</a></div><div class="ttdeci">__IO uint32_t HCSPLT</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:903</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gad85a9951a7be79fe08ffc90f796f071b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gad85a9951a7be79fe08ffc90f796f071b">RCC_TypeDef::APB1LPENR</a></div><div class="ttdeci">__IO uint32_t APB1LPENR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:632</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gadab1e24ef769bbcb3e3769feae192ffb"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gadab1e24ef769bbcb3e3769feae192ffb">TIM_TypeDef::CCR1</a></div><div class="ttdeci">__IO uint32_t CCR1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:755</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gadb72f64492a75e780dd2294075c70fed"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gadb72f64492a75e780dd2294075c70fed">TIM_TypeDef::CCMR1</a></div><div class="ttdeci">__IO uint32_t CCMR1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:748</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gadc1bdc4e76749ccda09c92e885b164ad"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gadc1bdc4e76749ccda09c92e885b164ad">USB_OTG_DeviceTypeDef::DCTL</a></div><div class="ttdeci">__IO uint32_t DCTL</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:833</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gadca0624d09f2c72eee9807cea80a4d0c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gadca0624d09f2c72eee9807cea80a4d0c">ETH_TypeDef::PTPTSSR</a></div><div class="ttdeci">__IO uint32_t PTPTSSR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:431</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gadcf812cbe5147d300507d59d4a55935d"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gadcf812cbe5147d300507d59d4a55935d">SDIO_TypeDef::CMD</a></div><div class="ttdeci">__IO uint32_t CMD</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:699</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gadd56f3652fd065c6797411e80477a064"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gadd56f3652fd065c6797411e80477a064">ETH_TypeDef::DMAIER</a></div><div class="ttdeci">__IO uint32_t DMAIER</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:440</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gadd5b8e29a64c55dcd65ca4201118e9d1"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gadd5b8e29a64c55dcd65ca4201118e9d1">USART_TypeDef::CR3</a></div><div class="ttdeci">__IO uint32_t CR3</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:776</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gadde42c516172a887c570545d965200cf"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gadde42c516172a887c570545d965200cf">USB_OTG_HostChannelTypeDef::HCTSIZ</a></div><div class="ttdeci">__IO uint32_t HCTSIZ</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:906</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaded1359e1a32512910bff534d57ade68"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaded1359e1a32512910bff534d57ade68">CAN_TxMailBox_TypeDef::TDLR</a></div><div class="ttdeci">__IO uint32_t TDLR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:231</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gae1c569688eedd49219cd505b9c22121b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gae1c569688eedd49219cd505b9c22121b">CAN_FIFOMailBox_TypeDef::RDLR</a></div><div class="ttdeci">__IO uint32_t RDLR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:243</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gae20eaf17d134d9c2136072bca05f36c0"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gae20eaf17d134d9c2136072bca05f36c0">_memory::BKPSRAM_BASE</a></div><div class="ttdeci">uint8_t BKPSRAM_BASE[BKPSRAM_SIZE]</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:967</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gae69520f078c84fb1d33cd7551ff23342"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gae69520f078c84fb1d33cd7551ff23342">USB_OTG_HostChannelTypeDef::HCINTMSK</a></div><div class="ttdeci">__IO uint32_t HCINTMSK</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:905</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gae6ff257862eba6b4b367feea786bf1fd"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gae6ff257862eba6b4b367feea786bf1fd">RCC_TypeDef::PLLCFGR</a></div><div class="ttdeci">__IO uint32_t PLLCFGR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:611</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gae845b86e973b4bf8a33c447c261633f6"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gae845b86e973b4bf8a33c447c261633f6">EXTI_TypeDef::IMR</a></div><div class="ttdeci">__IO uint32_t IMR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:456</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gae85e8a65a72f52a9daf3d2b66b77c2e2"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gae85e8a65a72f52a9daf3d2b66b77c2e2">USB_OTG_DeviceTypeDef::DEACHINT</a></div><div class="ttdeci">__IO uint32_t DEACHINT</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:846</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gae8e4ef158db1de28bfd759e40677ba4c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gae8e4ef158db1de28bfd759e40677ba4c">ETH_TypeDef::PTPTSHUR</a></div><div class="ttdeci">__IO uint32_t PTPTSHUR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:425</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gae9028b8bcb5118b7073165fb50fcd559"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gae9028b8bcb5118b7073165fb50fcd559">DAC_TypeDef::DHR12L1</a></div><div class="ttdeci">__IO uint32_t DHR12L1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:309</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gae9156af81694b7a85923348be45a2167"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gae9156af81694b7a85923348be45a2167">ADC_TypeDef::JDR2</a></div><div class="ttdeci">__IO uint32_t JDR2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:208</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaea29ac183c979d0cb95ad3781fe9ed91"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaea29ac183c979d0cb95ad3781fe9ed91">ETH_TypeDef::MMCRIR</a></div><div class="ttdeci">__IO uint32_t MMCRIR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:406</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaeb17f07e5976d0674b1afe60cffc79d4"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaeb17f07e5976d0674b1afe60cffc79d4">_memory::FSMC_R_BASE</a></div><div class="ttdeci">uint8_t FSMC_R_BASE[FSMC_R_SIZE]</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:970</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaecf297022669fda29294f6fe9818ebbd"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaecf297022669fda29294f6fe9818ebbd">USB_OTG_GlobalTypeDef::GRSTCTL</a></div><div class="ttdeci">__IO uint32_t GRSTCTL</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:811</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaed87bed042dd9523ce086119a3bab0ea"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaed87bed042dd9523ce086119a3bab0ea">CAN_TxMailBox_TypeDef::TDTR</a></div><div class="ttdeci">__IO uint32_t TDTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:230</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaee7782244ceb4791d9a3891804ac47ac"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaee7782244ceb4791d9a3891804ac47ac">DMA_Stream_TypeDef::M1AR</a></div><div class="ttdeci">__IO uint32_t M1AR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:363</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaef55be3d948c22dd32a97e8d4f8761fd"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaef55be3d948c22dd32a97e8d4f8761fd">DMA_Stream_TypeDef::PAR</a></div><div class="ttdeci">__IO uint32_t PAR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:361</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaef613e58417a7201da95b89b85931da9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaef613e58417a7201da95b89b85931da9">USB_OTG_GlobalTypeDef::GOTGINT</a></div><div class="ttdeci">__IO uint32_t GOTGINT</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:808</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaef85efc005db9a8e37d95644e92e9032"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaef85efc005db9a8e37d95644e92e9032">USB_OTG_GlobalTypeDef::GCCFG</a></div><div class="ttdeci">__IO uint32_t GCCFG</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:820</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaef96b3719a70e62cb004b1e292b7a348"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaef96b3719a70e62cb004b1e292b7a348">USB_OTG_DeviceTypeDef::DVBUSDIS</a></div><div class="ttdeci">__IO uint32_t DVBUSDIS</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:842</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf1405e594e39e5b34f9499f680157a25"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf1405e594e39e5b34f9499f680157a25">CAN_TypeDef::FFA1R</a></div><div class="ttdeci">__IO uint32_t FFA1R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:280</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf17f19bb4aeea3cc14fa73dfa7772cb8"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf17f19bb4aeea3cc14fa73dfa7772cb8">TIM_TypeDef::ARR</a></div><div class="ttdeci">__IO uint32_t ARR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:753</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf294702e1d54fe06b43e7a3b4033dc2e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf294702e1d54fe06b43e7a3b4033dc2e">USB_OTG_HostChannelTypeDef::HCDMA</a></div><div class="ttdeci">__IO uint32_t HCDMA</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:907</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf2b40c5e36a5e861490988275499e158"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf2b40c5e36a5e861490988275499e158">CAN_TypeDef::RESERVED3</a></div><div class="ttdeci">uint32_t RESERVED3</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:279</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf30c34f7c606cb9416a413ec5fa36491"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf30c34f7c606cb9416a413ec5fa36491">FSMC_Bank2_3_TypeDef::SR3</a></div><div class="ttdeci">__IO uint32_t SR3</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:514</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf34b7e8815984e272daa3f089014af4e"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf34b7e8815984e272daa3f089014af4e">ETH_TypeDef::PTPSSIR</a></div><div class="ttdeci">__IO uint32_t PTPSSIR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:422</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf60258ad5a25addc1e8969665d0c1731"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf60258ad5a25addc1e8969665d0c1731">DMA_Stream_TypeDef::NDTR</a></div><div class="ttdeci">__IO uint32_t NDTR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:360</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf6225cb8f4938f98204d11afaffd41c9"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf6225cb8f4938f98204d11afaffd41c9">TIM_TypeDef::DCR</a></div><div class="ttdeci">__IO uint32_t DCR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:760</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf66e42cdb83dc2eb156dfbbf42890f79"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf66e42cdb83dc2eb156dfbbf42890f79">USB_OTG_HostTypeDef::Reserved40C</a></div><div class="ttdeci">uint32_t Reserved40C</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:891</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf6aca2bbd40c0fb6df7c3aebe224a360"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360">DAC_TypeDef::SR</a></div><div class="ttdeci">__IO uint32_t SR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:319</div></div>
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||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf751d49ef824c1636c78822ecae066f4"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf751d49ef824c1636c78822ecae066f4">DCMI_TypeDef::ESUR</a></div><div class="ttdeci">__IO uint32_t ESUR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:347</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf85290529fb82acef7c9fcea3718346c"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf85290529fb82acef7c9fcea3718346c">RTC_TypeDef::BKP1R</a></div><div class="ttdeci">__IO uint32_t BKP1R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:669</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf86c61a5d38a4fc9cef942a12744486b"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf86c61a5d38a4fc9cef942a12744486b">FSMC_Bank2_3_TypeDef::RESERVED0</a></div><div class="ttdeci">uint32_t RESERVED0</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:509</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf8d25514079514d38c104402f46470af"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf8d25514079514d38c104402f46470af">EXTI_TypeDef::PR</a></div><div class="ttdeci">__IO uint32_t PR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:461</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf90723c7aee9c32113a2667b0a5c69f1"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf90723c7aee9c32113a2667b0a5c69f1">ETH_TypeDef::PTPTTHR</a></div><div class="ttdeci">__IO uint32_t PTPTTHR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:428</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaf9d6c604e365c7d9d7601bf4ef373498"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaf9d6c604e365c7d9d7601bf4ef373498">ADC_TypeDef::SMPR1</a></div><div class="ttdeci">__IO uint32_t SMPR1</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:195</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gafafaddc3a983eb71332b7526d82191ad"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gafafaddc3a983eb71332b7526d82191ad">RTC_TypeDef::BKP15R</a></div><div class="ttdeci">__IO uint32_t BKP15R</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:683</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gafc4900646681dfe1ca43133d376c4423"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gafc4900646681dfe1ca43133d376c4423">FLASH_TypeDef::OPTKEYR</a></div><div class="ttdeci">__IO uint32_t OPTKEYR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:472</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gafdfa307571967afb1d97943e982b6586"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586">ADC_TypeDef::CR2</a></div><div class="ttdeci">__IO uint32_t CR2</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:194</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaff6eeec1afa983f153ff0786c8902d43"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaff6eeec1afa983f153ff0786c8902d43">ETH_TypeDef::MMCRFCECR</a></div><div class="ttdeci">__IO uint32_t MMCRFCECR</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:416</div></div>
|
||
<div class="ttc" id="agroup___c_m_s_i_s___device_html_gaffd2c6f534c8f2c252f3a93d0cd04ea2"><div class="ttname"><a href="group___c_m_s_i_s___device.html#gaffd2c6f534c8f2c252f3a93d0cd04ea2">USB_OTG_OUTEndpointTypeDef::DOEPINT</a></div><div class="ttdeci">__IO uint32_t DOEPINT</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:876</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_ga7e1129cd8a196f4284d41db3e82ad5c8"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a></div><div class="ttdeci">IRQn_Type</div><div class="ttdoc">STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:77</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2">PendSV_IRQn</a></div><div class="ttdeci">@ PendSV_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:85</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a0485578005e12c2e2c0fb253a844ec6f"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0485578005e12c2e2c0fb253a844ec6f">ETH_WKUP_IRQn</a></div><div class="ttdeci">@ ETH_WKUP_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:150</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a082cb3f7839069a0715fd76c7eacbbc9"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a082cb3f7839069a0715fd76c7eacbbc9">EXTI2_IRQn</a></div><div class="ttdeci">@ EXTI2_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:96</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a0d9ec75e4478e70235b705d5a6b3efd8"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0d9ec75e4478e70235b705d5a6b3efd8">DMA1_Stream2_IRQn</a></div><div class="ttdeci">@ DMA1_Stream2_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:101</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a0f5f129d88a5606a378811e43039e274"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0f5f129d88a5606a378811e43039e274">CAN1_SCE_IRQn</a></div><div class="ttdeci">@ CAN1_SCE_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:110</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a16fe70a39348f3f27906dc268b5654e3"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a16fe70a39348f3f27906dc268b5654e3">SDIO_IRQn</a></div><div class="ttdeci">@ SDIO_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:137</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a173ccc3f31df1f7e43de2ddeab3d1777"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a173ccc3f31df1f7e43de2ddeab3d1777">RTC_WKUP_IRQn</a></div><div class="ttdeci">@ RTC_WKUP_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:91</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a1b040a7f76278a73cf5ea4c51f1be047"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a1b040a7f76278a73cf5ea4c51f1be047">OTG_HS_EP1_IN_IRQn</a></div><div class="ttdeci">@ OTG_HS_EP1_IN_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:163</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a1e5055722630fd4b12aff421964c2ebb"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a1e5055722630fd4b12aff421964c2ebb">DMA2_Stream0_IRQn</a></div><div class="ttdeci">@ DMA2_Stream0_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:144</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a21570761ad0b5ed751adc831691b7800"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a21570761ad0b5ed751adc831691b7800">DMA2_Stream6_IRQn</a></div><div class="ttdeci">@ DMA2_Stream6_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:157</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a2ec363869f4488782dc10a60abce3b34"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a2ec363869f4488782dc10a60abce3b34">I2C1_ER_IRQn</a></div><div class="ttdeci">@ I2C1_ER_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:120</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a3020193786527c47d2e4d8c92ceee804"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3020193786527c47d2e4d8c92ceee804">I2C2_EV_IRQn</a></div><div class="ttdeci">@ I2C2_EV_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:121</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa">MemoryManagement_IRQn</a></div><div class="ttdeci">@ MemoryManagement_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:80</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a368b899ca740b9ae0d75841f3abf68c4"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a368b899ca740b9ae0d75841f3abf68c4">TIM4_IRQn</a></div><div class="ttdeci">@ TIM4_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:118</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a3a4e2095a926e4095d3c846eb1c98afa"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3a4e2095a926e4095d3c846eb1c98afa">TIM2_IRQn</a></div><div class="ttdeci">@ TIM2_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:116</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a3d4cc0cd9b4d71e7ee002c4f8c1f8a77"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3d4cc0cd9b4d71e7ee002c4f8c1f8a77">DMA2_Stream7_IRQn</a></div><div class="ttdeci">@ DMA2_Stream7_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:158</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a3e01328006d19f7d32354271b9f61dce"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3e01328006d19f7d32354271b9f61dce">TIM8_BRK_TIM12_IRQn</a></div><div class="ttdeci">@ TIM8_BRK_TIM12_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:131</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a3f9c48714d0e5baaba6613343f0da68e"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3f9c48714d0e5baaba6613343f0da68e">USART2_IRQn</a></div><div class="ttdeci">@ USART2_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:126</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a3ff8f3439f509e6e985eb960e63e1be4"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3ff8f3439f509e6e985eb960e63e1be4">DMA2_Stream3_IRQn</a></div><div class="ttdeci">@ DMA2_Stream3_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:147</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237">SVCall_IRQn</a></div><div class="ttdeci">@ SVCall_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:83</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a4d69175258ae261dd545001e810421b3"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4d69175258ae261dd545001e810421b3">ADC_IRQn</a></div><div class="ttdeci">@ ADC_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:106</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a4e9331739fb76a2ca7781fede070ae44"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4e9331739fb76a2ca7781fede070ae44">SPI3_IRQn</a></div><div class="ttdeci">@ SPI3_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:139</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a505fbd4ccf7c2a14c8b76dc9e58f7ede"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a505fbd4ccf7c2a14c8b76dc9e58f7ede">SPI2_IRQn</a></div><div class="ttdeci">@ SPI2_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:124</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a53cadc1e164ec85d0ea4cd143608e8e1"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a53cadc1e164ec85d0ea4cd143608e8e1">TIM7_IRQn</a></div><div class="ttdeci">@ TIM7_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:143</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a56c0b5758f26f31494e74aab9273f9fd"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a56c0b5758f26f31494e74aab9273f9fd">CAN2_SCE_IRQn</a></div><div class="ttdeci">@ CAN2_SCE_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:154</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a5710b22392997bac63daa5c999730f77"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a5710b22392997bac63daa5c999730f77">RCC_IRQn</a></div><div class="ttdeci">@ RCC_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:93</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a5f581e9aedfaccd9b1db9ec793804b45"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a5f581e9aedfaccd9b1db9ec793804b45">TIM6_DAC_IRQn</a></div><div class="ttdeci">@ TIM6_DAC_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:142</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a60b6cc4b6dbeca39e29a475d26c9e080"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a60b6cc4b6dbeca39e29a475d26c9e080">OTG_HS_EP1_OUT_IRQn</a></div><div class="ttdeci">@ OTG_HS_EP1_OUT_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:162</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a60c35f2d48d512bd6818bc9fef7053d7"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a60c35f2d48d512bd6818bc9fef7053d7">I2C2_ER_IRQn</a></div><div class="ttdeci">@ I2C2_ER_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:122</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a637750639eff4e2b4aae80ed6f3cf67f"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a637750639eff4e2b4aae80ed6f3cf67f">TIM8_CC_IRQn</a></div><div class="ttdeci">@ TIM8_CC_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:134</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf">UsageFault_IRQn</a></div><div class="ttdeci">@ UsageFault_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:82</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a></div><div class="ttdeci">@ SysTick_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:86</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a6e954232d164a6942ebc7a6bd6f7736e"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6e954232d164a6942ebc7a6bd6f7736e">I2C3_ER_IRQn</a></div><div class="ttdeci">@ I2C3_ER_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:161</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a70450df88125476d5771f2ff3f562536"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a70450df88125476d5771f2ff3f562536">FSMC_IRQn</a></div><div class="ttdeci">@ FSMC_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:136</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a8326db2d570cb865ffa1d49fa29d562a"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8326db2d570cb865ffa1d49fa29d562a">I2C3_EV_IRQn</a></div><div class="ttdeci">@ I2C3_EV_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:160</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a851fd2f2ab1418710e7da80e1bdf348a"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a851fd2f2ab1418710e7da80e1bdf348a">CAN2_RX0_IRQn</a></div><div class="ttdeci">@ CAN2_RX0_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:152</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af">BusFault_IRQn</a></div><div class="ttdeci">@ BusFault_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:81</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c">DebugMonitor_IRQn</a></div><div class="ttdeci">@ DebugMonitor_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:84</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a90c4647e57cff99fac635c532802c4b5"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a90c4647e57cff99fac635c532802c4b5">RNG_IRQn</a></div><div class="ttdeci">@ RNG_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:167</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a91b73963ce243a1d031576d49e137fab"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a91b73963ce243a1d031576d49e137fab">FLASH_IRQn</a></div><div class="ttdeci">@ FLASH_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:92</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a933d4686213973abc01845a3da1c8a03"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a933d4686213973abc01845a3da1c8a03">DMA2_Stream5_IRQn</a></div><div class="ttdeci">@ DMA2_Stream5_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:156</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a971089d7566ef902dfa0c80ac3a8fd52"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a971089d7566ef902dfa0c80ac3a8fd52">WWDG_IRQn</a></div><div class="ttdeci">@ WWDG_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:88</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a9852dbbe8c014e716ce7e03a7b809751"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9852dbbe8c014e716ce7e03a7b809751">I2C1_EV_IRQn</a></div><div class="ttdeci">@ I2C1_EV_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:119</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a985574288f66e2a00e97387424a9a2d8"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a985574288f66e2a00e97387424a9a2d8">TIM3_IRQn</a></div><div class="ttdeci">@ TIM3_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:117</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a98abb3f02c1feb3831706bc1b82307cb"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a98abb3f02c1feb3831706bc1b82307cb">DMA2_Stream1_IRQn</a></div><div class="ttdeci">@ DMA2_Stream1_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:145</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a9ceb5175f7c10cf436955173c2246877"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9ceb5175f7c10cf436955173c2246877">CAN1_TX_IRQn</a></div><div class="ttdeci">@ CAN1_TX_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:107</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a9e5c9d81dd3985a88094f8158c0f0267"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9e5c9d81dd3985a88094f8158c0f0267">OTG_HS_WKUP_IRQn</a></div><div class="ttdeci">@ OTG_HS_WKUP_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:164</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a9ee33e72512c4cfb301b216f4fb9d68c"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9ee33e72512c4cfb301b216f4fb9d68c">DMA1_Stream0_IRQn</a></div><div class="ttdeci">@ DMA1_Stream0_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:99</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a9fb0ad0c850234d1983fafdb17378e2f"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9fb0ad0c850234d1983fafdb17378e2f">EXTI15_10_IRQn</a></div><div class="ttdeci">@ EXTI15_10_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:128</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aa3879e49013035601e17f83a51e0829f"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa3879e49013035601e17f83a51e0829f">TIM1_UP_TIM10_IRQn</a></div><div class="ttdeci">@ TIM1_UP_TIM10_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:113</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aa3aa50e0353871985facf62d055faa52"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa3aa50e0353871985facf62d055faa52">EXTI9_5_IRQn</a></div><div class="ttdeci">@ EXTI9_5_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:111</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aa45ca2c955060e2c2a7cbbe1d6753285"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa45ca2c955060e2c2a7cbbe1d6753285">DMA1_Stream1_IRQn</a></div><div class="ttdeci">@ DMA1_Stream1_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:100</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aa60a30b7ef03446a46fd72e084911f7e"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa60a30b7ef03446a46fd72e084911f7e">OTG_FS_IRQn</a></div><div class="ttdeci">@ OTG_FS_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:155</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aa612f35c4440359c35acbaa3c1458c5f"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa612f35c4440359c35acbaa3c1458c5f">OTG_FS_WKUP_IRQn</a></div><div class="ttdeci">@ OTG_FS_WKUP_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:130</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aa6b8ff01b016a798c6e639728c179e4f"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa6b8ff01b016a798c6e639728c179e4f">FPU_IRQn</a></div><div class="ttdeci">@ FPU_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:168</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aa8d8f67a98f24de6f0b36ad6b1f29a7d"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa8d8f67a98f24de6f0b36ad6b1f29a7d">TIM8_UP_TIM13_IRQn</a></div><div class="ttdeci">@ TIM8_UP_TIM13_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:132</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aa92bcb2bc3a87be869f05c5b07f04b8c"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa92bcb2bc3a87be869f05c5b07f04b8c">USART6_IRQn</a></div><div class="ttdeci">@ USART6_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:159</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aacdff1a9c42582ed663214cbe62c1174"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aacdff1a9c42582ed663214cbe62c1174">SPI1_IRQn</a></div><div class="ttdeci">@ SPI1_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:123</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aad2d5e47d27fe3a02f7059b20bb729c0"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aad2d5e47d27fe3a02f7059b20bb729c0">OTG_HS_IRQn</a></div><div class="ttdeci">@ OTG_HS_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:165</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ab0b51ffcc4dcf5661141b79c8e5bd924"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab0b51ffcc4dcf5661141b79c8e5bd924">PVD_IRQn</a></div><div class="ttdeci">@ PVD_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:89</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ab1a744bdceb8eface6ff57dd036e608e"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a744bdceb8eface6ff57dd036e608e">TIM1_TRG_COM_TIM11_IRQn</a></div><div class="ttdeci">@ TIM1_TRG_COM_TIM11_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:114</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ab35b4ce63cfb11453f84a3695c6df368"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab35b4ce63cfb11453f84a3695c6df368">TIM1_BRK_TIM9_IRQn</a></div><div class="ttdeci">@ TIM1_BRK_TIM9_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:112</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ab5023ff845be31a488ab63a0b8cf2b7a"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab5023ff845be31a488ab63a0b8cf2b7a">CAN2_RX1_IRQn</a></div><div class="ttdeci">@ CAN2_RX1_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:153</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ab6aa6f87d26bbc6cf99b067b8d75c2f7"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab6aa6f87d26bbc6cf99b067b8d75c2f7">EXTI0_IRQn</a></div><div class="ttdeci">@ EXTI0_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:94</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ab6bf73ac43a9856b3f2759a59f3d25b5"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab6bf73ac43a9856b3f2759a59f3d25b5">CAN1_RX0_IRQn</a></div><div class="ttdeci">@ CAN1_RX0_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:108</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ab70a40106ca4486770df5d2072d9ac0e"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab70a40106ca4486770df5d2072d9ac0e">EXTI4_IRQn</a></div><div class="ttdeci">@ EXTI4_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:98</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8abf5e189f3ac7aad9f65e65ea5a0f3b36"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8abf5e189f3ac7aad9f65e65ea5a0f3b36">DMA2_Stream2_IRQn</a></div><div class="ttdeci">@ DMA2_Stream2_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:146</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ac127cca7ae48bcf93924209f04e5e5a1"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac127cca7ae48bcf93924209f04e5e5a1">TAMP_STAMP_IRQn</a></div><div class="ttdeci">@ TAMP_STAMP_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:90</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ac55a11a64aae7432544d0ab0d4f7de09"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac55a11a64aae7432544d0ab0d4f7de09">UART5_IRQn</a></div><div class="ttdeci">@ UART5_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:141</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ac92efa72399fe58fa615d8bf8fd64a4e"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac92efa72399fe58fa615d8bf8fd64a4e">DMA1_Stream5_IRQn</a></div><div class="ttdeci">@ DMA1_Stream5_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:104</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ace3c0fc2c4d05a7c02e3c987da5bc8e8"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ace3c0fc2c4d05a7c02e3c987da5bc8e8">DCMI_IRQn</a></div><div class="ttdeci">@ DCMI_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:166</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ad71328dd95461b7c55b568cf25966f6a"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ad71328dd95461b7c55b568cf25966f6a">ETH_IRQn</a></div><div class="ttdeci">@ ETH_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:149</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ad97cb163e1f678367e37c50d54d161ab"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ad97cb163e1f678367e37c50d54d161ab">USART1_IRQn</a></div><div class="ttdeci">@ USART1_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:125</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8add889c84ba5de466ced209069e05d602"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8add889c84ba5de466ced209069e05d602">EXTI3_IRQn</a></div><div class="ttdeci">@ EXTI3_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:97</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">NonMaskableInt_IRQn</a></div><div class="ttdeci">@ NonMaskableInt_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:79</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aded5314b20c6e4e80cb6ab0668ffb8d5"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aded5314b20c6e4e80cb6ab0668ffb8d5">UART4_IRQn</a></div><div class="ttdeci">@ UART4_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:140</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ae252b31c3a341acbe9a467e243137307"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae252b31c3a341acbe9a467e243137307">TIM8_TRG_COM_TIM14_IRQn</a></div><div class="ttdeci">@ TIM8_TRG_COM_TIM14_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:133</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ae4badcdecdb94eb10129c4c0577c5e19"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae4badcdecdb94eb10129c4c0577c5e19">EXTI1_IRQn</a></div><div class="ttdeci">@ EXTI1_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:95</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8ae54eb8b30273b38a0576f75aba24eec0"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae54eb8b30273b38a0576f75aba24eec0">DMA2_Stream4_IRQn</a></div><div class="ttdeci">@ DMA2_Stream4_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:148</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aed2eb3f4bb721d55fcc1003125956645"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aed2eb3f4bb721d55fcc1003125956645">TIM5_IRQn</a></div><div class="ttdeci">@ TIM5_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:138</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aedaa9c14e7e5fa9c0dcbb0c2455546e8"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aedaa9c14e7e5fa9c0dcbb0c2455546e8">DMA1_Stream7_IRQn</a></div><div class="ttdeci">@ DMA1_Stream7_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:135</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aee2aaf365c6c297a63cee41ecae2301a"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aee2aaf365c6c297a63cee41ecae2301a">DMA1_Stream4_IRQn</a></div><div class="ttdeci">@ DMA1_Stream4_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:103</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8aef5e2b68f62f6f1781fab894f0b8f486"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aef5e2b68f62f6f1781fab894f0b8f486">DMA1_Stream6_IRQn</a></div><div class="ttdeci">@ DMA1_Stream6_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:105</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8af312f0a21f600f9b286427e50c549ca9"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af312f0a21f600f9b286427e50c549ca9">TIM1_CC_IRQn</a></div><div class="ttdeci">@ TIM1_CC_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:115</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8af6b8fbc990ac71c8425647bb684788a4"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af6b8fbc990ac71c8425647bb684788a4">CAN2_TX_IRQn</a></div><div class="ttdeci">@ CAN2_TX_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:151</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8af71ef06c4f9ff0e1691c21ff3670acd4"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af71ef06c4f9ff0e1691c21ff3670acd4">CAN1_RX1_IRQn</a></div><div class="ttdeci">@ CAN1_RX1_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:109</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8af77770e080206a7558decf09344fb2e2"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af77770e080206a7558decf09344fb2e2">DMA1_Stream3_IRQn</a></div><div class="ttdeci">@ DMA1_Stream3_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:102</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8afb13802afc1f5fdf5c90e73ee99e5ff3"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8afb13802afc1f5fdf5c90e73ee99e5ff3">USART3_IRQn</a></div><div class="ttdeci">@ USART3_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:127</div></div>
|
||
<div class="ttc" id="agroup___peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8afe09d6563a21a1540f658163a76a3b37"><div class="ttname"><a href="group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8afe09d6563a21a1540f658163a76a3b37">RTC_Alarm_IRQn</a></div><div class="ttdeci">@ RTC_Alarm_IRQn</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:129</div></div>
|
||
<div class="ttc" id="agroup___peripheral__memory__map_html_ga16c53e8ec3bcf87a7d170220d774956c"><div class="ttname"><a href="group___peripheral__memory__map.html#ga16c53e8ec3bcf87a7d170220d774956c">PERIPH_BB_SIZE</a></div><div class="ttdeci">#define PERIPH_BB_SIZE</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:950</div></div>
|
||
<div class="ttc" id="agroup___peripheral__memory__map_html_ga304d35aeeebef1445af976d8a5248d57"><div class="ttname"><a href="group___peripheral__memory__map.html#ga304d35aeeebef1445af976d8a5248d57">MCU_MemoryTypeDef</a></div><div class="ttdeci">struct _memory MCU_MemoryTypeDef</div></div>
|
||
<div class="ttc" id="agroup___peripheral__memory__map_html_ga36147b9ef36c5be4745a45162cd85be4"><div class="ttname"><a href="group___peripheral__memory__map.html#ga36147b9ef36c5be4745a45162cd85be4">FSMC_R_SIZE</a></div><div class="ttdeci">#define FSMC_R_SIZE</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:952</div></div>
|
||
<div class="ttc" id="agroup___peripheral__memory__map_html_ga71542ecbf91e5a2e4e7657ebf4743bb0"><div class="ttname"><a href="group___peripheral__memory__map.html#ga71542ecbf91e5a2e4e7657ebf4743bb0">CCMDATARAM_SIZE</a></div><div class="ttdeci">#define CCMDATARAM_SIZE</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:936</div></div>
|
||
<div class="ttc" id="agroup___peripheral__memory__map_html_ga85a080726cb1ade56443b458fc49404b"><div class="ttname"><a href="group___peripheral__memory__map.html#ga85a080726cb1ade56443b458fc49404b">DEBUG_MCU</a></div><div class="ttdeci">DBGMCU_TypeDef DEBUG_MCU</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:973</div></div>
|
||
<div class="ttc" id="agroup___peripheral__memory__map_html_gacb3e2951c91f038686e0cbcd4321814b"><div class="ttname"><a href="group___peripheral__memory__map.html#gacb3e2951c91f038686e0cbcd4321814b">FLASH_OTP_SIZE</a></div><div class="ttdeci">#define FLASH_OTP_SIZE</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:943</div></div>
|
||
<div class="ttc" id="agroup___peripheral__memory__map_html_gacf1c7f7eb345f8e1b617fd1b16320111"><div class="ttname"><a href="group___peripheral__memory__map.html#gacf1c7f7eb345f8e1b617fd1b16320111">SRAM1_SIZE</a></div><div class="ttdeci">#define SRAM1_SIZE</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:937</div></div>
|
||
<div class="ttc" id="agroup___peripheral__memory__map_html_gad89e757d25db6160b1aedeb58fcdac09"><div class="ttname"><a href="group___peripheral__memory__map.html#gad89e757d25db6160b1aedeb58fcdac09">SRAM2_SIZE</a></div><div class="ttdeci">#define SRAM2_SIZE</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:938</div></div>
|
||
<div class="ttc" id="agroup___peripheral__memory__map_html_gae69620948dea1b76e0ab7843ab719db7"><div class="ttname"><a href="group___peripheral__memory__map.html#gae69620948dea1b76e0ab7843ab719db7">FLASH_SIZE</a></div><div class="ttdeci">#define FLASH_SIZE</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:941</div></div>
|
||
<div class="ttc" id="agroup___peripheral__memory__map_html_gaf157a51d290d1383d493a6a2fe0241fc"><div class="ttname"><a href="group___peripheral__memory__map.html#gaf157a51d290d1383d493a6a2fe0241fc">MCU_MEM</a></div><div class="ttdeci">MCU_MemoryTypeDef MCU_MEM</div><div class="ttdef"><b>Definition</b> stm32f4xx_matlab_conf.c:8</div></div>
|
||
<div class="ttc" id="agroup___peripheral__memory__map_html_gaf91d23524f40a61d32fea568949043d0"><div class="ttname"><a href="group___peripheral__memory__map.html#gaf91d23524f40a61d32fea568949043d0">PERIPH_SIZE</a></div><div class="ttdeci">#define PERIPH_SIZE</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:948</div></div>
|
||
<div class="ttc" id="agroup___peripheral__memory__map_html_gafe7470549838cd29d6f2d7245f17176c"><div class="ttname"><a href="group___peripheral__memory__map.html#gafe7470549838cd29d6f2d7245f17176c">BKPSRAM_SIZE</a></div><div class="ttdeci">#define BKPSRAM_SIZE</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:939</div></div>
|
||
<div class="ttc" id="astdint_8h_html"><div class="ttname"><a href="stdint_8h.html">stdint.h</a></div></div>
|
||
<div class="ttc" id="astdint_8h_html_a435d1572bf3f880d55459d9805097f62"><div class="ttname"><a href="stdint_8h.html#a435d1572bf3f880d55459d9805097f62">uint32_t</a></div><div class="ttdeci">unsigned int uint32_t</div><div class="ttdef"><b>Definition</b> stdint.h:64</div></div>
|
||
<div class="ttc" id="astdint_8h_html_aba7bc1797add20fe3efdf37ced1182c5"><div class="ttname"><a href="stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5">uint8_t</a></div><div class="ttdeci">unsigned char uint8_t</div><div class="ttdef"><b>Definition</b> stdint.h:62</div></div>
|
||
<div class="ttc" id="astdint_8h_html_adf4d876453337156dde61095e1f20223"><div class="ttname"><a href="stdint_8h.html#adf4d876453337156dde61095e1f20223">uint16_t</a></div><div class="ttdeci">unsigned short int uint16_t</div><div class="ttdef"><b>Definition</b> stdint.h:63</div></div>
|
||
<div class="ttc" id="astruct__memory_html"><div class="ttname"><a href="struct__memory.html">_memory</a></div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:956</div></div>
|
||
<div class="ttc" id="astruct_a_d_c___common___type_def_html"><div class="ttname"><a href="struct_a_d_c___common___type_def.html">ADC_Common_TypeDef</a></div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:215</div></div>
|
||
<div class="ttc" id="astruct_a_d_c___type_def_html"><div class="ttname"><a href="struct_a_d_c___type_def.html">ADC_TypeDef</a></div><div class="ttdoc">Analog to Digital Converter</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:191</div></div>
|
||
<div class="ttc" id="astruct_c_a_n___f_i_f_o_mail_box___type_def_html"><div class="ttname"><a href="struct_c_a_n___f_i_f_o_mail_box___type_def.html">CAN_FIFOMailBox_TypeDef</a></div><div class="ttdoc">Controller Area Network FIFOMailBox.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:240</div></div>
|
||
<div class="ttc" id="astruct_c_a_n___filter_register___type_def_html"><div class="ttname"><a href="struct_c_a_n___filter_register___type_def.html">CAN_FilterRegister_TypeDef</a></div><div class="ttdoc">Controller Area Network FilterRegister.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:252</div></div>
|
||
<div class="ttc" id="astruct_c_a_n___tx_mail_box___type_def_html"><div class="ttname"><a href="struct_c_a_n___tx_mail_box___type_def.html">CAN_TxMailBox_TypeDef</a></div><div class="ttdoc">Controller Area Network TxMailBox.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:228</div></div>
|
||
<div class="ttc" id="astruct_c_a_n___type_def_html"><div class="ttname"><a href="struct_c_a_n___type_def.html">CAN_TypeDef</a></div><div class="ttdoc">Controller Area Network.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:262</div></div>
|
||
<div class="ttc" id="astruct_c_r_c___type_def_html"><div class="ttname"><a href="struct_c_r_c___type_def.html">CRC_TypeDef</a></div><div class="ttdoc">CRC calculation unit.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:292</div></div>
|
||
<div class="ttc" id="astruct_d_a_c___type_def_html"><div class="ttname"><a href="struct_d_a_c___type_def.html">DAC_TypeDef</a></div><div class="ttdoc">Digital to Analog Converter.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:305</div></div>
|
||
<div class="ttc" id="astruct_d_b_g_m_c_u___type_def_html"><div class="ttname"><a href="struct_d_b_g_m_c_u___type_def.html">DBGMCU_TypeDef</a></div><div class="ttdoc">Debug MCU.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:327</div></div>
|
||
<div class="ttc" id="astruct_d_c_m_i___type_def_html"><div class="ttname"><a href="struct_d_c_m_i___type_def.html">DCMI_TypeDef</a></div><div class="ttdoc">DCMI.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:339</div></div>
|
||
<div class="ttc" id="astruct_d_m_a___stream___type_def_html"><div class="ttname"><a href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a></div><div class="ttdoc">DMA Controller.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:358</div></div>
|
||
<div class="ttc" id="astruct_d_m_a___type_def_html"><div class="ttname"><a href="struct_d_m_a___type_def.html">DMA_TypeDef</a></div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:368</div></div>
|
||
<div class="ttc" id="astruct_e_t_h___type_def_html"><div class="ttname"><a href="struct_e_t_h___type_def.html">ETH_TypeDef</a></div><div class="ttdoc">Ethernet MAC.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:380</div></div>
|
||
<div class="ttc" id="astruct_e_x_t_i___type_def_html"><div class="ttname"><a href="struct_e_x_t_i___type_def.html">EXTI_TypeDef</a></div><div class="ttdoc">External Interrupt/Event Controller.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:455</div></div>
|
||
<div class="ttc" id="astruct_f_l_a_s_h___type_def_html"><div class="ttname"><a href="struct_f_l_a_s_h___type_def.html">FLASH_TypeDef</a></div><div class="ttdoc">FLASH Registers.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:469</div></div>
|
||
<div class="ttc" id="astruct_f_s_m_c___bank1___type_def_html"><div class="ttname"><a href="struct_f_s_m_c___bank1___type_def.html">FSMC_Bank1_TypeDef</a></div><div class="ttdoc">Flexible Static Memory Controller.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:486</div></div>
|
||
<div class="ttc" id="astruct_f_s_m_c___bank1_e___type_def_html"><div class="ttname"><a href="struct_f_s_m_c___bank1_e___type_def.html">FSMC_Bank1E_TypeDef</a></div><div class="ttdoc">Flexible Static Memory Controller Bank1E.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:495</div></div>
|
||
<div class="ttc" id="astruct_f_s_m_c___bank2__3___type_def_html"><div class="ttname"><a href="struct_f_s_m_c___bank2__3___type_def.html">FSMC_Bank2_3_TypeDef</a></div><div class="ttdoc">Flexible Static Memory Controller Bank2.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:504</div></div>
|
||
<div class="ttc" id="astruct_f_s_m_c___bank4___type_def_html"><div class="ttname"><a href="struct_f_s_m_c___bank4___type_def.html">FSMC_Bank4_TypeDef</a></div><div class="ttdoc">Flexible Static Memory Controller Bank4.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:526</div></div>
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<div class="ttc" id="astruct_g_p_i_o___type_def_html"><div class="ttname"><a href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a></div><div class="ttdoc">General Purpose I/O.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:539</div></div>
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<div class="ttc" id="astruct_i2_c___type_def_html"><div class="ttname"><a href="struct_i2_c___type_def.html">I2C_TypeDef</a></div><div class="ttdoc">Inter-integrated Circuit Interface.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:569</div></div>
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<div class="ttc" id="astruct_i_w_d_g___type_def_html"><div class="ttname"><a href="struct_i_w_d_g___type_def.html">IWDG_TypeDef</a></div><div class="ttdoc">Independent WATCHDOG.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:586</div></div>
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<div class="ttc" id="astruct_p_w_r___type_def_html"><div class="ttname"><a href="struct_p_w_r___type_def.html">PWR_TypeDef</a></div><div class="ttdoc">Power Control.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:599</div></div>
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<div class="ttc" id="astruct_r_c_c___type_def_html"><div class="ttname"><a href="struct_r_c_c___type_def.html">RCC_TypeDef</a></div><div class="ttdoc">Reset and Clock Control.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:609</div></div>
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<div class="ttc" id="astruct_r_n_g___type_def_html"><div class="ttname"><a href="struct_r_n_g___type_def.html">RNG_TypeDef</a></div><div class="ttdoc">RNG.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:796</div></div>
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<div class="ttc" id="astruct_r_t_c___type_def_html"><div class="ttname"><a href="struct_r_t_c___type_def.html">RTC_TypeDef</a></div><div class="ttdoc">Real-Time Clock.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:647</div></div>
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<div class="ttc" id="astruct_s_d_i_o___type_def_html"><div class="ttname"><a href="struct_s_d_i_o___type_def.html">SDIO_TypeDef</a></div><div class="ttdoc">SD host Interface.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:695</div></div>
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<div class="ttc" id="astruct_s_p_i___type_def_html"><div class="ttname"><a href="struct_s_p_i___type_def.html">SPI_TypeDef</a></div><div class="ttdoc">Serial Peripheral Interface.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:723</div></div>
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||
<div class="ttc" id="astruct_s_y_s_c_f_g___type_def_html"><div class="ttname"><a href="struct_s_y_s_c_f_g___type_def.html">SYSCFG_TypeDef</a></div><div class="ttdoc">System configuration controller.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:556</div></div>
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||
<div class="ttc" id="astruct_t_i_m___type_def_html"><div class="ttname"><a href="struct_t_i_m___type_def.html">TIM_TypeDef</a></div><div class="ttdoc">TIM.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:741</div></div>
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||
<div class="ttc" id="astruct_u_s_a_r_t___type_def_html"><div class="ttname"><a href="struct_u_s_a_r_t___type_def.html">USART_TypeDef</a></div><div class="ttdoc">Universal Synchronous Asynchronous Receiver Transmitter.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:770</div></div>
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<div class="ttc" id="astruct_u_s_b___o_t_g___device_type_def_html"><div class="ttname"><a href="struct_u_s_b___o_t_g___device_type_def.html">USB_OTG_DeviceTypeDef</a></div><div class="ttdoc">USB_OTG_device_Registers.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:831</div></div>
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||
<div class="ttc" id="astruct_u_s_b___o_t_g___global_type_def_html"><div class="ttname"><a href="struct_u_s_b___o_t_g___global_type_def.html">USB_OTG_GlobalTypeDef</a></div><div class="ttdoc">USB_OTG_Core_Registers.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:806</div></div>
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||
<div class="ttc" id="astruct_u_s_b___o_t_g___host_channel_type_def_html"><div class="ttname"><a href="struct_u_s_b___o_t_g___host_channel_type_def.html">USB_OTG_HostChannelTypeDef</a></div><div class="ttdoc">USB_OTG_Host_Channel_Specific_Registers.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:901</div></div>
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||
<div class="ttc" id="astruct_u_s_b___o_t_g___host_type_def_html"><div class="ttname"><a href="struct_u_s_b___o_t_g___host_type_def.html">USB_OTG_HostTypeDef</a></div><div class="ttdoc">USB_OTG_Host_Mode_Register_Structures.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:887</div></div>
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||
<div class="ttc" id="astruct_u_s_b___o_t_g___i_n_endpoint_type_def_html"><div class="ttname"><a href="struct_u_s_b___o_t_g___i_n_endpoint_type_def.html">USB_OTG_INEndpointTypeDef</a></div><div class="ttdoc">USB_OTG_IN_Endpoint-Specific_Register.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:858</div></div>
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||
<div class="ttc" id="astruct_u_s_b___o_t_g___o_u_t_endpoint_type_def_html"><div class="ttname"><a href="struct_u_s_b___o_t_g___o_u_t_endpoint_type_def.html">USB_OTG_OUTEndpointTypeDef</a></div><div class="ttdoc">USB_OTG_OUT_Endpoint-Specific_Registers.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:873</div></div>
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||
<div class="ttc" id="astruct_w_w_d_g___type_def_html"><div class="ttname"><a href="struct_w_w_d_g___type_def.html">WWDG_TypeDef</a></div><div class="ttdoc">Window WATCHDOG.</div><div class="ttdef"><b>Definition</b> stm32f407xx_matlab.h:785</div></div>
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||
<div class="ttc" id="asystem__stm32f4xx_8h_html"><div class="ttname"><a href="system__stm32f4xx_8h.html">system_stm32f4xx.h</a></div><div class="ttdoc">CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.</div></div>
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